1 /**************************************************************************//** 2 * @file ccap_reg.h 3 * @version V1.00 4 * @brief CCAP register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CCAP_REG_H__ 10 #define __CCAP_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup CCAP Camera Capture Interface Controller (CCAP) 23 Memory Mapped Structure for CCAP Controller 24 @{ */ 25 26 27 typedef struct { 28 29 30 /** 31 * @var CCAP_T::CTL 32 * Offset: 0x00 Camera Capture Interface Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |CCAPEN |Camera Capture Interface Enable 37 * | | |0 = Camera Capture Interface Disabled. 38 * | | |1 = Camera Capture Interface Enabled. 39 * |[3] |ADDRSW |Packet Buffer Address Switch 40 * | | |0 = Packet buffer address switch Disabled. 41 * | | |1 = Packet buffer address switch Enabled. 42 * |[6] |PKTEN |Packet Output Enable 43 * | | |0 = Packet output Disabled. 44 * | | |1 = Packet output Enabled. 45 * |[7] |MONO |Monochrome CMOS Sensor Select 46 * | | |0 = Color CMOS Sensor. 47 * | | |1 = Monochrome CMOS Sensor. The U/V components are ignored when the MONO is enabled. 48 * |[16] |SHUTTER |Image Capture Interface Automatically Disable The Capture Interface After A Frame Had Been Captured 49 * | | |0 = Shutter Disabled. 50 * | | |1 = Shutter Enabled. 51 * |[20] |UPDATE |Update Register At New Frame 52 * | | |0 = Update register at new frame Disabled. 53 * | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated). 54 * |[24] |VPRST |Capture Interface Reset 55 * | | |0 = Capture interface reset Disabled. 56 * | | |1 = Capture interface reset Enabled. 57 * @var CCAP_T::PAR 58 * Offset: 0x04 Camera Capture Interface Parameter Register 59 * --------------------------------------------------------------------------------------------------- 60 * |Bits |Field |Descriptions 61 * | :----: | :----: | :---- | 62 * |[0] |INFMT |Sensor Input Data Format 63 * | | |0 = YCbCr422. 64 * | | |1 = RGB565. 65 * |[1] |SENTYPE |Sensor Input Type 66 * | | |0 = CCIR601. 67 * | | |1 = CCIR656, VSync & Hsync embedded in the data signal. 68 * |[2:3] |INDATORD |Sensor Input Data Order 69 * | | |If INFMT = 0 (YCbCr),. 70 * | | | Byte 0 1 2 3 71 * | | |00 = Y0 U0 Y1 V0. 72 * | | |01 = Y0 V0 Y1 U0. 73 * | | |10 = U0 Y0 V0 Y1. 74 * | | |11 = V0 Y0 U0 Y1. 75 * | | |If INFMT = 1 (RGB565),. 76 * | | |00 = Byte0[R[4:0] G[5:3]] Byte1[G[2:0] B[4:0]] 77 * | | |01 = Byte0[B[4:0] G[5:3]] Byte1[G[2:0] R[4:0]] 78 * | | |10 = Byte0[G[2:0] B[4:0]] Byte1[R[4:0] G[5:3]] 79 * | | |11 = Byte0[G[2:0] R[4:0]] Byte1[B[4:0] G[5:3]] 80 * |[4:5] |OUTFMT |Image Data Format Output To System Memory 81 * | | |00 = YCbCr422. 82 * | | |01 = Only output Y. 83 * | | |10 = RGB555. 84 * | | |11 = RGB565. 85 * |[6] |RANGE |Scale Input YUV CCIR601 Color Range To Full Range 86 * | | |0 = default. 87 * | | |1 = Scale to full range. 88 * |[8] |PCLKP |Sensor Pixel Clock Polarity 89 * | | |0 = Input video data and signals are latched by falling edge of Pixel Clock. 90 * | | |1 = Input video data and signals are latched by rising edge of Pixel Clock. 91 * |[9] |HSP |Sensor Hsync Polarity 92 * | | |0 = Sync Low. 93 * | | |1 = Sync High. 94 * |[10] |VSP |Sensor Vsync Polarity 95 * | | |0 = Sync Low. 96 * | | |1 = Sync High. 97 * |[18] |FBB |Field By Blank 98 * | | |Hardware will tag field0 or field1 by vertical blanking instead of FIELD flag in CCIR-656 mode. 99 * | | |0 = Field by blank Disabled. 100 * | | |1 = Field by blank Enabled. 101 * @var CCAP_T::INT 102 * Offset: 0x08 Camera Capture Interface Interrupt Register 103 * --------------------------------------------------------------------------------------------------- 104 * |Bits |Field |Descriptions 105 * | :----: | :----: | :---- | 106 * |[0] |VINTF |Video Frame End Interrupt 107 * | | |If this bit shows 1, receiving a frame completed. 108 * | | |Write 1 to clear it. 109 * |[1] |MEINTF |Bus Master Transfer Error Interrupt 110 * | | |If this bit shows 1, Transfer Error occurred. Write 1 to clear it. 111 * |[3] |ADDRMINTF |Memory Address Match Interrupt 112 * | | |If this bit shows 1, Memory Address Match Interrupt occurred. 113 * | | |Write 1 to clear it. 114 * |[4] |MDINTF |Motion Detection Output Finish Interrupt 115 * | | |If this bit shows 1, Motion Detection Output Finish Interrupt occurred. 116 * | | |Write 1 to clear it. 117 * |[16] |VIEN |Video Frame End Interrupt Enable 118 * | | |0 = Video frame end interrupt Disabled. 119 * | | |1 = Video frame end interrupt Enabled. 120 * |[17] |MEIEN |System Memory Error Interrupt Enable 121 * | | |0 = System memory error interrupt Disabled. 122 * | | |1 = System memory error interrupt Enabled. 123 * |[19] |ADDRMIEN |Address Match Interrupt Enable 124 * | | |0 = Address match interrupt Disabled. 125 * | | |1 = Address match interrupt Enabled. 126 * @var CCAP_T::POSTERIZE 127 * Offset: 0x0C YUV Component Posterizing Factor Register 128 * --------------------------------------------------------------------------------------------------- 129 * |Bits |Field |Descriptions 130 * | :----: | :----: | :---- | 131 * |[0:7] |VCOMP |V Component Posterizing Factor 132 * | | |Final_V_Out = Original_V[7:0] & V_Posterizing_Factor. 133 * |[8:15] |UCOMP |U Component Posterizing Factor 134 * | | |Final_U_Out = Original_U[7:0] & U_Posterizing_Factor. 135 * |[16:23] |YCOMP |Y Component Posterizing Factor 136 * | | |Final_Y_Out = Original_Y[7:0] & Y_Posterizing_Factor. 137 * @var CCAP_T::MD 138 * Offset: 0x10 Motion Detection Register 139 * --------------------------------------------------------------------------------------------------- 140 * |Bits |Field |Descriptions 141 * | :----: | :----: | :---- | 142 * |[0] |MDEN |Motion Detection Enable 143 * | | |0 = CCAP_MD Disabled. 144 * | | |1 = CCAP_MD Enabled. 145 * |[8] |MDBS |Motion Detection Block Size 146 * | | |0 = 16x16. 147 * | | |1 = 8x8. 148 * |[9] |MDSM |Motion Detection Save Mode 149 * | | |0 = 1 bit DIFF + 7 bit Y Differential. 150 * | | |1 = 1 bit DIFF only. 151 * |[10:11] |MDDF |Motion Detection Detect Frequency 152 * | | |00 = Each frame. 153 * | | |01 = Every 2 frame. 154 * | | |10 = Every 3 frame. 155 * | | |11 = Every 4 frame. 156 * |[16:20] |MDTHR |Motion Detection Differential Threshold 157 * @var CCAP_T::MDADDR 158 * Offset: 0x14 Motion Detection Output Address Register 159 * --------------------------------------------------------------------------------------------------- 160 * |Bits |Field |Descriptions 161 * | :----: | :----: | :---- | 162 * |[0:31] |MDADDR |Motion Detection Output Address Register (Word Alignment) 163 * @var CCAP_T::MDYADDR 164 * Offset: 0x18 Motion Detection Temp Y Output Address Register 165 * --------------------------------------------------------------------------------------------------- 166 * |Bits |Field |Descriptions 167 * | :----: | :----: | :---- | 168 * |[0:31] |MDYADDR |Motion Detection Temp Y Output Address Register (Word Alignment) 169 * @var CCAP_T::SEPIA 170 * Offset: 0x1C Sepia Effect Control Register 171 * --------------------------------------------------------------------------------------------------- 172 * |Bits |Field |Descriptions 173 * | :----: | :----: | :---- | 174 * |[0:7] |VCOMP |Define the constant V component while Sepia color effect is turned on. 175 * |[8:15] |UCOMP |Define the constant U component while Sepia color effect is turned on. 176 * @var CCAP_T::CWSP 177 * Offset: 0x20 Cropping Window Starting Address Register 178 * --------------------------------------------------------------------------------------------------- 179 * |Bits |Field |Descriptions 180 * | :----: | :----: | :---- | 181 * |[0:11] |CWSADDRH |Cropping Window Horizontal Starting Address 182 * |[16:26] |CWSADDRV |Cropping Window Vertical Starting Address 183 * @var CCAP_T::CWS 184 * Offset: 0x24 Cropping Window Size Register 185 * --------------------------------------------------------------------------------------------------- 186 * |Bits |Field |Descriptions 187 * | :----: | :----: | :---- | 188 * |[0:11] |CIWW |Cropping Image Window Width 189 * |[16:26] |CIWH |Cropping Image Window Height 190 * @var CCAP_T::PKTSL 191 * Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB) 192 * --------------------------------------------------------------------------------------------------- 193 * |Bits |Field |Descriptions 194 * | :----: | :----: | :---- | 195 * |[0:7] |PKTSHML |Packet Scaling Horizontal Factor M (Lower 8-Bit) 196 * | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor. 197 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor. 198 * | | |The output image width will be equal to the image width * N/M. 199 * | | |Note: The value of N must be equal to or less than M. 200 * |[8:15] |PKTSHNL |Packet Scaling Horizontal Factor N (Lower 8-Bit) 201 * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. 202 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor. 203 * |[16:23] |PKTSVML |Packet Scaling Vertical Factor M (Lower 8-Bit) 204 * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. 205 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor. 206 * | | |The output image width will be equal to the image height * N/M. 207 * | | |Note: The value of N must be equal to or less than M. 208 * |[24:31] |PKTSVNL |Packet Scaling Vertical Factor N (Lower 8-Bit) 209 * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor. 210 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor 211 * @var CCAP_T::PLNSL 212 * Offset: 0x2C Planar Scaling Vertical/Horizontal Factor Register (LSB) 213 * --------------------------------------------------------------------------------------------------- 214 * |Bits |Field |Descriptions 215 * | :----: | :----: | :---- | 216 * |[0:7] |PLNSHML |Planar Scaling Horizontal Factor M (Lower 8-Bit) 217 * | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor. 218 * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHMH) to form a 16-bit denominator (M) of vertical factor. 219 * | | |The output image width will be equal to the image width * N/M. 220 * | | |Note: The value of N must be equal to or less than M. 221 * |[8:15] |PLNSHNL |Planar Scaling Horizontal Factor N (Lower 8-Bit) 222 * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. 223 * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHNH) to form a 16-bit numerator of horizontal factor. 224 * |[16:23] |PLNSVML |Planar Scaling Vertical Factor M (Lower 8-Bit) 225 * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. 226 * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVMH) to form a 16-bit denominator (M) of vertical factor. 227 * | | |The output image width will be equal to the image height * N/M. 228 * | | |Note: The value of N must be equal to or less than M. 229 * |[24:31] |PLNSVNL |Planar Scaling Vertical Factor N (Lower 8-Bit) 230 * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor. 231 * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVNH) to form a 16-bit numerator of vertical factor. 232 * @var CCAP_T::FRCTL 233 * Offset: 0x30 Scaling Frame Rate Factor Register 234 * --------------------------------------------------------------------------------------------------- 235 * |Bits |Field |Descriptions 236 * | :----: | :----: | :---- | 237 * |[0:5] |FRM |Scaling Frame Rate Factor M 238 * | | |Specify the denominator part (M) of the frame rate scaling factor. 239 * | | |The output image frame rate will be equal to input image frame rate * (N/M). 240 * | | |Note: The value of N must be equal to or less than M. 241 * |[8:13] |FRN |Scaling Frame Rate Factor N 242 * | | |Specify the denominator part (N) of the frame rate scaling factor. 243 * @var CCAP_T::STRIDE 244 * Offset: 0x34 Frame Output Pixel Stride Width Register 245 * --------------------------------------------------------------------------------------------------- 246 * |Bits |Field |Descriptions 247 * | :----: | :----: | :---- | 248 * |[0:13] |PKTSTRIDE |Packet Frame Output Pixel Stride Width 249 * | | |The output pixel stride size of packet pipe. 250 * |[16:29] |PLNSTRIDE |Planar Frame Output Pixel Stride Width 251 * | | |The output pixel stride size of planar pipe. 252 * @var CCAP_T::FIFOTH 253 * Offset: 0x3C FIFO Threshold Register 254 * --------------------------------------------------------------------------------------------------- 255 * |Bits |Field |Descriptions 256 * | :----: | :----: | :---- | 257 * |[0:3] |PLNVFTH |Planar V FIFO Threshold 258 * |[8:11] |PLNUFTH |Planar U FIFO Threshold 259 * |[16:20] |PLNYFTH |Planar Y FIFO Threshold 260 * |[24:28] |PKTFTH |Packet FIFO Threshold 261 * |[31] |OVF |FIFO Overflow Flag 262 * @var CCAP_T::CMPADDR 263 * Offset: 0x40 Compare Memory Base Address Register 264 * --------------------------------------------------------------------------------------------------- 265 * |Bits |Field |Descriptions 266 * | :----: | :----: | :---- | 267 * |[0:31] |CMPADDR |Compare Memory Base Address 268 * | | |Word aligns address; ignore the bits [1:0]. 269 * @var CCAP_T::LUMA_Y1_THD 270 * Offset: 0x44 Luminance Y8 to Y1 Threshold Value Register 271 * --------------------------------------------------------------------------------------------------- 272 * |Bits |Field |Descriptions 273 * | :----: | :-----------: | :---- | 274 * |[0:8] |LUMA_Y1_THRESH |Luminance Y8 to Y1 Threshold Value 275 * | | |Specify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion. 276 * @var CCAP_T::PKTSM 277 * Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB) 278 * --------------------------------------------------------------------------------------------------- 279 * |Bits |Field |Descriptions 280 * | :----: | :----: | :---- | 281 * |[0:7] |PKTSHMH |Packet Scaling Horizontal Factor M (Higher 8-Bit) 282 * | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor. 283 * | | |Please refer to the register CCAP_PKTSL?for the detailed operation. 284 * |[8:15] |PKTSHNH |Packet Scaling Horizontal Factor N (Higher 8-Bit) 285 * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. 286 * | | |Please refer to the register CCAP_PKTSL for the detailed operation. 287 * |[16:23] |PKTSVMH |Packet Scaling Vertical Factor M (Higher 8-Bit) 288 * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. 289 * | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers. 290 * |[24:31] |PKTSVNH |Packet Scaling Vertical Factor N (Higher 8-Bit) 291 * | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor. 292 * | | |Please refer to the register CCAP_PKTSL?to check the cooperation between these two registers. 293 * @var CCAP_T::PKTBA0 294 * Offset: 0x60 System Memory Packet Base Address 0 Register 295 * --------------------------------------------------------------------------------------------------- 296 * |Bits |Field |Descriptions 297 * | :----: | :----: | :---- | 298 * |[0:31] |BASEADDR |System Memory Packet Base Address 0 299 * | | |Word aligns address; ignore the bits [1:0]. 300 */ 301 __IO uint32_t CTL; 302 __IO uint32_t PAR; 303 __IO uint32_t INT; 304 __IO uint32_t POSTERIZE; 305 __IO uint32_t MD; 306 __IO uint32_t MDADDR; 307 __IO uint32_t MDYADDR; 308 __IO uint32_t SEPIA; 309 __IO uint32_t CWSP; 310 __IO uint32_t CWS; 311 __IO uint32_t PKTSL; 312 __IO uint32_t PLNSL; 313 __IO uint32_t FRCTL; 314 __IO uint32_t STRIDE; 315 /// @cond HIDDEN_SYMBOLS 316 uint32_t RESERVE0[1]; 317 /// @endcond //HIDDEN_SYMBOLS 318 __IO uint32_t FIFOTH; 319 __IO uint32_t CMPADDR; 320 __IO uint32_t LUMA_Y1_THD; 321 __IO uint32_t PKTSM; 322 /// @cond HIDDEN_SYMBOLS 323 uint32_t RESERVE2[5]; 324 /// @endcond //HIDDEN_SYMBOLS 325 __IO uint32_t PKTBA0; 326 } CCAP_T; 327 328 /** 329 @addtogroup CCAP_CONST CCAP Bit Field Definition 330 Constant Definitions for CCAP Controller 331 @{ */ 332 333 #define CCAP_CTL_CCAPEN_Pos (0) /*!< CCAP_T::CTL: CCAPEN Position */ 334 #define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos) /*!< CCAP_T::CTL: CCAPEN Mask */ 335 336 #define CCAP_CTL_ADDRSW_Pos (3) /*!< CCAP_T::CTL: ADDRSW Position */ 337 #define CCAP_CTL_ADDRSW_Msk (0x1ul << CCAP_CTL_ADDRSW_Pos) /*!< CCAP_T::CTL: ADDRSW Mask */ 338 339 #define CCAP_CTL_PLNEN_Pos (5) /*!< CCAP_T::CTL: PLNEN Position */ 340 #define CCAP_CTL_PLNEN_Msk (0x1ul << CCAP_CTL_PLNEN_Pos) /*!< CCAP_T::CTL: PLNEN Mask */ 341 342 #define CCAP_CTL_PKTEN_Pos (6) /*!< CCAP_T::CTL: PKTEN Position */ 343 #define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos) /*!< CCAP_T::CTL: PKTEN Mask */ 344 345 #define CCAP_CTL_MONO_Pos (7) /*!< CCAP_T::CTL: MONO Position */ 346 #define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos) /*!< CCAP_T::CTL: MONO Mask */ 347 348 #define CCAP_CTL_SHUTTER_Pos (16) /*!< CCAP_T::CTL: SHUTTER Position */ 349 #define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos) /*!< CCAP_T::CTL: SHUTTER Mask */ 350 351 #define CCAP_CTL_MY4_SWAP_Pos (17) /*!< CCAP_T::CTL: MY4_SWAP Position */ 352 #define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos) /*!< CCAP_T::CTL: MY4_SWAP Mask */ 353 354 #define CCAP_CTL_MY8_MY4_Pos (18) /*!< CCAP_T::CTL: MY8_MY4 Position */ 355 #define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos) /*!< CCAP_T::CTL: MY8_MY4 Mask */ 356 357 #define CCAP_CTL_Luma_Y_One_Pos (19) /*!< CCAP_T::CTL: Luma_Y_One Position */ 358 #define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos) /*!< CCAP_T::CTL: Luma_Y_One Mask */ 359 360 #define CCAP_CTL_UPDATE_Pos (20) /*!< CCAP_T::CTL: UPDATE Position */ 361 #define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos) /*!< CCAP_T::CTL: UPDATE Mask */ 362 363 #define CCAP_CTL_VPRST_Pos (24) /*!< CCAP_T::CTL: VPRST Position */ 364 #define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos) /*!< CCAP_T::CTL: VPRST Mask */ 365 366 #define CCAP_PAR_INFMT_Pos (0) /*!< CCAP_T::PAR: INFMT Position */ 367 #define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos) /*!< CCAP_T::PAR: INFMT Mask */ 368 369 #define CCAP_PAR_SENTYPE_Pos (1) /*!< CCAP_T::PAR: SENTYPE Position */ 370 #define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos) /*!< CCAP_T::PAR: SENTYPE Mask */ 371 372 #define CCAP_PAR_INDATORD_Pos (2) /*!< CCAP_T::PAR: INDATORD Position */ 373 #define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos) /*!< CCAP_T::PAR: INDATORD Mask */ 374 375 #define CCAP_PAR_OUTFMT_Pos (4) /*!< CCAP_T::PAR: OUTFMT Position */ 376 #define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */ 377 378 #define CCAP_PAR_RANGE_Pos (6) /*!< CCAP_T::PAR: RANGE Position */ 379 #define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos) /*!< CCAP_T::PAR: RANGE Mask */ 380 381 #define CCAP_PAR_PLNFMT_Pos (7) /*!< CCAP_T::PAR: PLNFMT Position */ 382 #define CCAP_PAR_PLNFMT_Msk (0x1ul << CCAP_PAR_PLNFMT_Pos) /*!< CCAP_T::PAR: PLNFMT Mask */ 383 384 #define CCAP_PAR_PCLKP_Pos (8) /*!< CCAP_T::PAR: PCLKP Position */ 385 #define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos) /*!< CCAP_T::PAR: PCLKP Mask */ 386 387 #define CCAP_PAR_HSP_Pos (9) /*!< CCAP_T::PAR: HSP Position */ 388 #define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos) /*!< CCAP_T::PAR: HSP Mask */ 389 390 #define CCAP_PAR_VSP_Pos (10) /*!< CCAP_T::PAR: VSP Position */ 391 #define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos) /*!< CCAP_T::PAR: VSP Mask */ 392 393 #define CCAP_PAR_COLORCTL_Pos (11) /*!< CCAP_T::PAR: COLORCTL Position */ 394 #define CCAP_PAR_COLORCTL_Msk (0x3ul << CCAP_PAR_COLORCTL_Pos) /*!< CCAP_T::PAR: COLORCTL Mask */ 395 396 #define CCAP_PAR_FBB_Pos (18) /*!< CCAP_T::PAR: FBB Position */ 397 #define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos) /*!< CCAP_T::PAR: FBB Mask */ 398 399 #define CCAP_INT_VINTF_Pos (0) /*!< CCAP_T::INT: VINTF Position */ 400 #define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos) /*!< CCAP_T::INT: VINTF Mask */ 401 402 #define CCAP_INT_MEINTF_Pos (1) /*!< CCAP_T::INT: MEINTF Position */ 403 #define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos) /*!< CCAP_T::INT: MEINTF Mask */ 404 405 #define CCAP_INT_ADDRMINTF_Pos (3) /*!< CCAP_T::INT: ADDRMINTF Position */ 406 #define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos) /*!< CCAP_T::INT: ADDRMINTF Mask */ 407 408 #define CCAP_INT_MDINTF_Pos (4) /*!< CCAP_T::INT: MDINTF Position */ 409 #define CCAP_INT_MDINTF_Msk (0x1ul << CCAP_INT_MDINTF_Pos) /*!< CCAP_T::INT: MDINTF Mask */ 410 411 #define CCAP_INT_VIEN_Pos (16) /*!< CCAP_T::INT: VIEN Position */ 412 #define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos) /*!< CCAP_T::INT: VIEN Mask */ 413 414 #define CCAP_INT_MEIEN_Pos (17) /*!< CCAP_T::INT: MEIEN Position */ 415 #define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos) /*!< CCAP_T::INT: MEIEN Mask */ 416 417 #define CCAP_INT_ADDRMIEN_Pos (19) /*!< CCAP_T::INT: ADDRMIEN Position */ 418 #define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos) /*!< CCAP_T::INT: ADDRMIEN Mask */ 419 420 #define CCAP_CWSP_CWSADDRH_Pos (0) /*!< CCAP_T::CWSP: CWSADDRH Position */ 421 #define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos) /*!< CCAP_T::CWSP: CWSADDRH Mask */ 422 423 #define CCAP_CWSP_CWSADDRV_Pos (16) /*!< CCAP_T::CWSP: CWSADDRV Position */ 424 #define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos) /*!< CCAP_T::CWSP: CWSADDRV Mask */ 425 426 #define CCAP_CWS_CWW_Pos (0) /*!< CCAP_T::CWS: CWW Position */ 427 #define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos) /*!< CCAP_T::CWS: CWW Mask */ 428 #define CCAP_CWS_CWH_Pos (16) /*!< CCAP_T::CWS: CIWH Position */ 429 #define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos) /*!< CCAP_T::CWS: CIWH Mask */ 430 431 #define CCAP_PKTSL_PKTSHML_Pos (0) /*!< CCAP_T::PKTSL: PKTSHML Position */ 432 #define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos) /*!< CCAP_T::PKTSL: PKTSHML Mask */ 433 434 #define CCAP_PKTSL_PKTSHNL_Pos (8) /*!< CCAP_T::PKTSL: PKTSHNL Position */ 435 #define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos) /*!< CCAP_T::PKTSL: PKTSHNL Mask */ 436 437 #define CCAP_PKTSL_PKTSVML_Pos (16) /*!< CCAP_T::PKTSL: PKTSVML Position */ 438 #define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos) /*!< CCAP_T::PKTSL: PKTSVML Mask */ 439 440 #define CCAP_PKTSL_PKTSVNL_Pos (24) /*!< CCAP_T::PKTSL: PKTSVNL Position */ 441 #define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos) /*!< CCAP_T::PKTSL: PKTSVNL Mask */ 442 443 #define CCAP_FRCTL_FRM_Pos (0) /*!< CCAP_T::FRCTL: FRM Position */ 444 #define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos) /*!< CCAP_T::FRCTL: FRM Mask */ 445 446 #define CCAP_FRCTL_FRN_Pos (8) /*!< CCAP_T::FRCTL: FRN Position */ 447 #define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos) /*!< CCAP_T::FRCTL: FRN Mask */ 448 449 #define CCAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CCAP_T::STRIDE: PKTSTRIDE Position */ 450 #define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos) /*!< CCAP_T::STRIDE: PKTSTRIDE Mask */ 451 452 #define CCAP_STRIDE_PLNSTRIDE_Pos (16) /*!< CCAP_T::STRIDE: PLNSTRIDE Position */ 453 #define CCAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos) /*!< CCAP_T::STRIDE: PLNSTRIDE Mask */ 454 455 #define CCAP_FIFOTH_PLNVFTH_Pos (0) /*!< CCAP_T::FIFOTH: PLNVFTH Position */ 456 #define CCAP_FIFOTH_PLNVFTH_Msk (0xful << CCAP_FIFOTH_PLNVFTH_Pos) /*!< CCAP_T::FIFOTH: PLNVFTH Mask */ 457 458 #define CCAP_FIFOTH_PLNUFTH_Pos (8) /*!< CCAP_T::FIFOTH: PLNUFTH Position */ 459 #define CCAP_FIFOTH_PLNUFTH_Msk (0xful << CCAP_FIFOTH_PLNUFTH_Pos) /*!< CCAP_T::FIFOTH: PLNUFTH Mask */ 460 461 #define CCAP_FIFOTH_PLNYFTH_Pos (16) /*!< CCAP_T::FIFOTH: PLNYFTH Position */ 462 #define CCAP_FIFOTH_PLNYFTH_Msk (0x1ful << CCAP_FIFOTH_PLNYFTH_Pos) /*!< CCAP_T::FIFOTH: PLNYFTH Mask */ 463 464 #define CCAP_FIFOTH_PKTFTH_Pos (24) /*!< CCAP_T::FIFOTH: PKTFTH Position */ 465 #define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos) /*!< CCAP_T::FIFOTH: PKTFTH Mask */ 466 467 #define CCAP_FIFOTH_OVF_Pos (31) /*!< CCAP_T::FIFOTH: OVF Position */ 468 #define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos) /*!< CCAP_T::FIFOTH: OVF Mask */ 469 470 #define CCAP_CMPADDR_CMPADDR_Pos (0) /*!< CCAP_T::CMPADDR: CMPADDR Position */ 471 #define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos) /*!< CCAP_T::CMPADDR: CMPADDR Mask */ 472 473 #define CCAP_PKTSM_PKTSHMH_Pos (0) /*!< CCAP_T::PKTSM: PKTSHMH Position */ 474 #define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos) /*!< CCAP_T::PKTSM: PKTSHMH Mask */ 475 476 #define CCAP_PKTSM_PKTSHNH_Pos (8) /*!< CCAP_T::PKTSM: PKTSHNH Position */ 477 #define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos) /*!< CCAP_T::PKTSM: PKTSHNH Mask */ 478 479 #define CCAP_PKTSM_PKTSVMH_Pos (16) /*!< CCAP_T::PKTSM: PKTSVMH Position */ 480 #define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos) /*!< CCAP_T::PKTSM: PKTSVMH Mask */ 481 482 #define CCAP_PKTSM_PKTSVNH_Pos (24) /*!< CCAP_T::PKTSM: PKTSVNH Position */ 483 #define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos) /*!< CCAP_T::PKTSM: PKTSVNH Mask */ 484 485 #define CCAP_PKTBA0_BASEADDR_Pos (0) /*!< CCAP_T::PKTBA0: BASEADDR Position */ 486 #define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) /*!< CCAP_T::PKTBA0: BASEADDR Mask */ 487 488 /**@}*/ /* CCAP_CONST */ 489 /**@}*/ /* end of CCAP register group */ 490 /**@}*/ /* end of REGISTER group */ 491 492 #if defined ( __CC_ARM ) 493 #pragma no_anon_unions 494 #endif 495 496 #endif /* __CCAP_REG_H__ */ 497
