1 /**************************************************************************//** 2 * @file pdma_reg.h 3 * @version V1.00 4 * @brief PDMA register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __PDMA_REG_H__ 10 #define __PDMA_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA) 23 Memory Mapped Structure for PDMA Controller 24 @{ */ 25 26 27 typedef struct 28 { 29 30 /** 31 * @var DSCT_T::CTL 32 * Offset: 0x00 Descriptor Table Control Register of PDMA Channel n. 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[1:0] |OPMODE |PDMA Operation Mode Selection 37 * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. 38 * | | |01 = Basic mode: The descriptor table only has one task 39 * | | |When this task is finished, the PDMA_INTSTS[n] will be asserted. 40 * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute. 41 * | | |11 = Reserved. 42 * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. 43 * |[2] |TXTYPE |Transfer Type 44 * | | |0 = Burst transfer type. 45 * | | |1 = Single transfer type. 46 * |[6:4] |BURSIZE |Burst Size 47 * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. 48 * | | |000 = 128 Transfers. 49 * | | |001 = 64 Transfers. 50 * | | |010 = 32 Transfers. 51 * | | |011 = 16 Transfers. 52 * | | |100 = 8 Transfers. 53 * | | |101 = 4 Transfers. 54 * | | |110 = 2 Transfers. 55 * | | |111 = 1 Transfers. 56 * | | |Note: This field is only useful in burst transfer type. 57 * |[7] |TBINTDIS |Table Interrupt Disable Bit 58 * | | |This field can be used to decide whether to enable table interrupt or not 59 * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt. 60 * | | |0 = Table interrupt Enabled. 61 * | | |1 = Table interrupt Disabled. 62 * |[9:8] |SAINC |Source Address Increment 63 * | | |This field is used to set the source address increment size. 64 * | | |11 = No increment (fixed address). 65 * | | |Others = Increment and size is depended on TXWIDTH selection. 66 * |[11:10] |DAINC |Destination Address Increment 67 * | | |This field is used to set the destination address increment size. 68 * | | |11 = No increment (fixed address). 69 * | | |Others = Increment and size is depended on TXWIDTH selection. 70 * |[13:12] |TXWIDTH |Transfer Width Selection 71 * | | |This field is used for transfer width. 72 * | | |00 = One byte (8 bit) is transferred for every operation. 73 * | | |01= One half-word (16 bit) is transferred for every operation. 74 * | | |10 = One word (32-bit) is transferred for every operation. 75 * | | |11 = Reserved. 76 * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection 77 * |[14] |TXACK |Transfer Acknowledge Selection 78 * | | |0 = transfer ack when transfer done. 79 * | | |1 = transfer ack when PDMA get transfer data. 80 * |[15] |STRIDEEN |Stride Mode Enable Bit 81 * | | |0 = Stride transfer mode Disabled. 82 * | | |1 = Stride transfer mode Enabled. 83 * |[31:16] |TXCNT |Transfer Count 84 * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. 85 * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately. 86 * @var DSCT_T::SA 87 * Offset: 0x04 Source Address Register of PDMA Channel n 88 * --------------------------------------------------------------------------------------------------- 89 * |Bits |Field |Descriptions 90 * | :----: | :----: | :---- | 91 * |[31:0] |SA |PDMA Transfer Source Address Register 92 * | | |This field indicates a 32-bit source address of PDMA controller. 93 * @var DSCT_T::DA 94 * Offset: 0x08 Destination Address Register of PDMA Channel n 95 * --------------------------------------------------------------------------------------------------- 96 * |Bits |Field |Descriptions 97 * | :----: | :----: | :---- | 98 * |[31:0] |DA |PDMA Transfer Destination Address Register 99 * | | |This field indicates a 32-bit destination address of PDMA controller. 100 * @var DSCT_T::NEXT 101 * Offset: 0x0C Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 102 * --------------------------------------------------------------------------------------------------- 103 * |Bits |Field |Descriptions 104 * | :----: | :----: | :---- | 105 * |[15:0] |EXENEXT |PDMA Execution Next Descriptor Table Offset 106 * | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. 107 * | | |Note: write operation is useless in this field. 108 * |[31:16] |NEXT |PDMA Next Descriptor Table Offset. 109 * | | |This field indicates the offset of the next descriptor table address in system memory. 110 * | | |Write Operation: 111 * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. 112 * | | |Read Operation: 113 * | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. 114 * | | |Note1: The descriptor table address must be word boundary. 115 * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. 116 */ 117 __IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n. */ 118 __IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */ 119 __IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */ 120 __IO uint32_t NEXT; /*!< [0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */ 121 } DSCT_T; 122 123 124 typedef struct 125 { 126 /** 127 * @var STRIDE_T::STCR 128 * Offset: 0x500 Stride Transfer Count Register of PDMA Channel n 129 * --------------------------------------------------------------------------------------------------- 130 * |Bits |Field |Descriptions 131 * | :----: | :----: | :---- | 132 * |[15:0] |STC |PDMA Stride Transfer Count 133 * | | |The 16-bit register defines the stride transfer count of each row. 134 * @var STRIDE_T::ASOCR 135 * Offset: 0x504 Address Stride Offset Register of PDMA Channel n 136 * --------------------------------------------------------------------------------------------------- 137 * |Bits |Field |Descriptions 138 * | :----: | :----: | :---- | 139 * |[15:0] |SASOL |VDMA Source Address Stride Offset Length 140 * | | |The 16-bit register defines the source address stride transfer offset count of each row. 141 * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length 142 * | | |The 16-bit register defines the destination address stride transfer offset count of each row. 143 */ 144 __IO uint32_t STCR; /*!< [0x0500] Stride Transfer Count Register of PDMA Channel 0 */ 145 __IO uint32_t ASOCR; /*!< [0x0504] Address Stride Offset Register of PDMA Channel 0 */ 146 } STRIDE_T; 147 148 typedef struct 149 { 150 /** 151 * @var REPEAT_T::AICTL 152 * Offset: 0x600 Address Interval Control Register of PDMA Channel n 153 * --------------------------------------------------------------------------------------------------- 154 * |Bits |Field |Descriptions 155 * | :----: | :----: | :---- | 156 * |[15:0] |SAICNT |PDMA Source Address Interval Count 157 * | | |The 16-bit register defines the source address interval count of each row. 158 * |[31:16] |DAICNT |PDMA Destination Address Interval Count 159 * | | |The 16-bit register defines the destination address interval count of each row. 160 * @var REPEAT_T::RCNT 161 * Offset: 0x604 Repeat Count Register of PDMA Channe n 162 * --------------------------------------------------------------------------------------------------- 163 * |Bits |Field |Descriptions 164 * | :----: | :----: | :---- | 165 * |[15:0] |RCNT |PDMA Repeat Count 166 * | | |The 16-bit register defines the repeat times of block transfer. 167 */ 168 __IO uint32_t AICTL; /*!< [0x0600] Address Interval Control Register of PDMA Channel 0 */ 169 __IO uint32_t RCNT; /*!< [0x0604] Repeat Count Register of PDMA Channel 0 */ 170 } REPEAT_T; 171 172 typedef struct 173 { 174 175 176 /** 177 * @var PDMA_T::CURSCAT 178 * Offset: 0x100 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 179 * --------------------------------------------------------------------------------------------------- 180 * |Bits |Field |Descriptions 181 * | :----: | :----: | :---- | 182 * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only) 183 * | | |This field indicates a 32-bit current external description address of PDMA controller. 184 * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. 185 * @var PDMA_T::CHCTL 186 * Offset: 0x400 PDMA Channel Control Register 187 * --------------------------------------------------------------------------------------------------- 188 * |Bits |Field |Descriptions 189 * | :----: | :----: | :---- | 190 * |[15:0] |CHENn |PDMA Channel Enable Bit 191 * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. 192 * | | |0 = PDMA channel [n] Disabled. 193 * | | |1 = PDMA channel [n] Enabled. 194 * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 195 * @var PDMA_T::PAUSE 196 * Offset: 0x404 PDMA Transfer Stop Control Register 197 * --------------------------------------------------------------------------------------------------- 198 * |Bits |Field |Descriptions 199 * | :----: | :----: | :---- | 200 * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only) 201 * | | |User can set PAUSEn bit field to pause the PDMA transfer 202 * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag 203 * | | |If re-enable the paused channel again, the remaining transfers will be processed. 204 * | | |0 = No effect. 205 * | | |1 = Pause PDMA channel n transfer. 206 * @var PDMA_T::SWREQ 207 * Offset: 0x408 PDMA Software Request Register 208 * --------------------------------------------------------------------------------------------------- 209 * |Bits |Field |Descriptions 210 * | :----: | :----: | :---- | 211 * |[15:0] |SWREQn |PDMA Software Request Register (Write Only) 212 * | | |Set this bit to 1 to generate a software request to PDMA [n]. 213 * | | |0 = No effect. 214 * | | |1 = Generate a software request. 215 * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active 216 * | | |Active flag may be triggered by software request or peripheral request. 217 * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored. 218 * @var PDMA_T::TRGSTS 219 * Offset: 0x40C PDMA Channel Request Status Register 220 * --------------------------------------------------------------------------------------------------- 221 * |Bits |Field |Descriptions 222 * | :----: | :----: | :---- | 223 * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only) 224 * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral 225 * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically. 226 * | | |0 = PDMA Channel n has no request. 227 * | | |1 = PDMA Channel n has a request. 228 * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer. 229 * @var PDMA_T::PRISET 230 * Offset: 0x410 PDMA Fixed Priority Setting Register 231 * --------------------------------------------------------------------------------------------------- 232 * |Bits |Field |Descriptions 233 * | :----: | :----: | :---- | 234 * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register 235 * | | |Set this bit to 1 to enable fixed priority level. 236 * | | |Write Operation: 237 * | | |0 = No effect. 238 * | | |1 = Set PDMA channel [n] to fixed priority channel. 239 * | | |Read Operation: 240 * | | |0 = Corresponding PDMA channel is round-robin priority. 241 * | | |1 = Corresponding PDMA channel is fixed priority. 242 * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 243 * @var PDMA_T::PRICLR 244 * Offset: 0x414 PDMA Fixed Priority Clear Register 245 * --------------------------------------------------------------------------------------------------- 246 * |Bits |Field |Descriptions 247 * | :----: | :----: | :---- | 248 * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only) 249 * | | |Set this bit to 1 to clear fixed priority level. 250 * | | |0 = No effect. 251 * | | |1 = Clear PDMA channel [n] fixed priority setting. 252 * | | |Note: User can read PDMA_PRISET register to know the channel priority. 253 * @var PDMA_T::INTEN 254 * Offset: 0x418 PDMA Interrupt Enable Register 255 * --------------------------------------------------------------------------------------------------- 256 * |Bits |Field |Descriptions 257 * | :----: | :----: | :---- | 258 * |[15:0] |INTENn |PDMA Interrupt Enable Register 259 * | | |This field is used for enabling PDMA channel[n] interrupt. 260 * | | |0 = PDMA channel n interrupt Disabled. 261 * | | |1 = PDMA channel n interrupt Enabled. 262 * @var PDMA_T::INTSTS 263 * Offset: 0x41C PDMA Interrupt Status Register 264 * --------------------------------------------------------------------------------------------------- 265 * |Bits |Field |Descriptions 266 * | :----: | :----: | :---- | 267 * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-only) 268 * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. 269 * | | |0 = No AHB bus ERROR response received. 270 * | | |1 = AHB bus ERROR response received. 271 * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) 272 * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. 273 * | | |0 = Not finished yet. 274 * | | |1 = PDMA channel has finished transmission. 275 * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) 276 * | | |0 = PDMA channel source address and destination address both follow transfer width setting. 277 * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. 278 * |[8] |REQTOF0 |Request Time-out Flag for Channel 0 279 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits. 280 * | | |0 = No request time-out. 281 * | | |1 = Peripheral request time-out. 282 * |[9] |REQTOF1 |Request Time-out Flag for Channel 1 283 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits. 284 * | | |0 = No request time-out. 285 * | | |1 = Peripheral request time-out. 286 * @var PDMA_T::ABTSTS 287 * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register 288 * --------------------------------------------------------------------------------------------------- 289 * |Bits |Field |Descriptions 290 * | :----: | :----: | :---- | 291 * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag 292 * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. 293 * | | |0 = No AHB bus ERROR response received when channel n transfer. 294 * | | |1 = AHB bus ERROR response received when channel n transfer. 295 * @var PDMA_T::TDSTS 296 * Offset: 0x424 PDMA Channel Transfer Done Flag Register 297 * --------------------------------------------------------------------------------------------------- 298 * |Bits |Field |Descriptions 299 * | :----: | :----: | :---- | 300 * |[15:0] |TDIFn |Transfer Done Flag Register 301 * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 302 * | | |0 = PDMA channel transfer has not finished. 303 * | | |1 = PDMA channel has finished transmission. 304 * @var PDMA_T::ALIGN 305 * Offset: 0x428 PDMA Transfer Alignment Status Register 306 * --------------------------------------------------------------------------------------------------- 307 * |Bits |Field |Descriptions 308 * | :----: | :----: | :---- | 309 * |[15:0] |ALIGNn |Transfer Alignment Flag Register 310 * | | |0 = PDMA channel source address and destination address both follow transfer width setting. 311 * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. 312 * @var PDMA_T::TACTSTS 313 * Offset: 0x42C PDMA Transfer Active Flag Register 314 * --------------------------------------------------------------------------------------------------- 315 * |Bits |Field |Descriptions 316 * | :----: | :----: | :---- | 317 * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only) 318 * | | |This bit indicates which PDMA channel is in active. 319 * | | |0 = PDMA channel is not finished. 320 * | | |1 = PDMA channel is active. 321 * @var PDMA_T::TOUTPSC 322 * Offset: 0x430 PDMA Time-out Prescaler Register 323 * --------------------------------------------------------------------------------------------------- 324 * |Bits |Field |Descriptions 325 * | :----: | :----: | :---- | 326 * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits 327 * | | |000 = PDMA channel 0 time-out clock source is HCLK/28. 328 * | | |001 = PDMA channel 0 time-out clock source is HCLK/29. 329 * | | |010 = PDMA channel 0 time-out clock source is HCLK/210. 330 * | | |011 = PDMA channel 0 time-out clock source is HCLK/211. 331 * | | |100 = PDMA channel 0 time-out clock source is HCLK/212. 332 * | | |101 = PDMA channel 0 time-out clock source is HCLK/213. 333 * | | |110 = PDMA channel 0 time-out clock source is HCLK/214. 334 * | | |111 = PDMA channel 0 time-out clock source is HCLK/215. 335 * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits 336 * | | |000 = PDMA channel 1 time-out clock source is HCLK/28. 337 * | | |001 = PDMA channel 1 time-out clock source is HCLK/29. 338 * | | |010 = PDMA channel 1 time-out clock source is HCLK/210. 339 * | | |011 = PDMA channel 1 time-out clock source is HCLK/211. 340 * | | |100 = PDMA channel 1 time-out clock source is HCLK/212. 341 * | | |101 = PDMA channel 1 time-out clock source is HCLK/213. 342 * | | |110 = PDMA channel 1 time-out clock source is HCLK/214. 343 * | | |111 = PDMA channel 1 time-out clock source is HCLK/215. 344 * @var PDMA_T::TOUTEN 345 * Offset: 0x434 PDMA Time-out Enable Register 346 * --------------------------------------------------------------------------------------------------- 347 * |Bits |Field |Descriptions 348 * | :----: | :----: | :---- | 349 * |[1:0] |TOUTENn |PDMA Time-out Enable Bits 350 * | | |0 = PDMA Channel n time-out function Disable. 351 * | | |1 = PDMA Channel n time-out function Enable. 352 * @var PDMA_T::TOUTIEN 353 * Offset: 0x438 PDMA Time-out Interrupt Enable Register 354 * --------------------------------------------------------------------------------------------------- 355 * |Bits |Field |Descriptions 356 * | :----: | :----: | :---- | 357 * |[1:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits 358 * | | |0 = PDMA Channel n time-out interrupt Disable. 359 * | | |1 = PDMA Channel n time-out interrupt Enable. 360 * @var PDMA_T::SCATBA 361 * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register 362 * --------------------------------------------------------------------------------------------------- 363 * |Bits |Field |Descriptions 364 * | :----: | :----: | :---- | 365 * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register 366 * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address 367 * | | |The next link address equation is 368 * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT. 369 * | | |Note: Only useful in Scatter-Gather mode. 370 * @var PDMA_T::TOC0_1 371 * Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register 372 * --------------------------------------------------------------------------------------------------- 373 * |Bits |Field |Descriptions 374 * | :----: | :----: | :---- | 375 * |[15:0] |TOC0 |Time-out Counter for Channel 0 376 * | | |This controls the period of time-out function for channel 0 377 * | | |The calculation unit is based on 10 kHz clock. 378 * |[31:16] |TOC1 |Time-out Counter for Channel 1 379 * | | |This controls the period of time-out function for channel 1 380 * | | |The calculation unit is based on 10 kHz clock. 381 * @var PDMA_T::CHRST 382 * Offset: 0x460 PDMA Channel Reset Register 383 * --------------------------------------------------------------------------------------------------- 384 * |Bits |Field |Descriptions 385 * | :----: | :----: | :---- | 386 * |[15:0] |CHnRST |Channel N Reset 387 * | | |0 = corresponding channel n not reset. 388 * | | |1 = corresponding channel n is reset. 389 * @var PDMA_T::REQSEL0_3 390 * Offset: 0x480 PDMA Request Source Select Register 0 391 * --------------------------------------------------------------------------------------------------- 392 * |Bits |Field |Descriptions 393 * | :----: | :----: | :---- | 394 * |[6:0] |REQSRC0 |Channel 0 Request Source Selection 395 * | | |This filed defines which peripheral is connected to PDMA channel 0 396 * | | |User can configure the peripheral by setting REQSRC0. 397 * | | |0 = Disable PDMA peripheral request. 398 * | | |1 = Reserved. 399 * | | |2 = Channel connects to USB_TX. 400 * | | |3 = Channel connects to USB_RX. 401 * | | |4 = Channel connects to UART0_TX. 402 * | | |5 = Channel connects to UART0_RX. 403 * | | |6 = Channel connects to UART1_TX. 404 * | | |7 = Channel connects to UART1_RX. 405 * | | |8 = Channel connects to UART2_TX. 406 * | | |9 = Channel connects to UART2_RX. 407 * | | |10=Channel connects to UART3_TX. 408 * | | |11 = Channel connects to UART3_RX. 409 * | | |12 = Channel connects to UART4_TX. 410 * | | |13 = Channel connects to UART4_RX. 411 * | | |14 = Channel connects to UART5_TX. 412 * | | |15 = Channel connects to UART5_RX. 413 * | | |16 = Channel connects to USCI0_TX. 414 * | | |17 = Channel connects to USCI0_RX. 415 * | | |18 = Channel connects to USCI1_TX. 416 * | | |19 = Channel connects to USCI1_RX. 417 * | | |20 = Channel connects to QSPI0_TX. 418 * | | |21 = Channel connects to QSPI0_RX. 419 * | | |22 = Channel connects to SPI0_TX. 420 * | | |23 = Channel connects to SPI0_RX. 421 * | | |24 = Channel connects to SPI1_TX. 422 * | | |25 = Channel connects to SPI1_RX. 423 * | | |26 = Channel connects to SPI2_TX. 424 * | | |27 = Channel connects to SPI2_RX. 425 * | | |28 = Channel connects to SPI3_TX. 426 * | | |29 = Channel connects to SPI3_RX. 427 * | | |30 = Reserved. 428 * | | |31 = Reserved. 429 * | | |32 = Channel connects to EPWM0_P1_RX. 430 * | | |33 = Channel connects to EPWM0_P2_RX. 431 * | | |34 = Channel connects to EPWM0_P3_RX. 432 * | | |35 = Channel connects to EPWM1_P1_RX. 433 * | | |36 = Channel connects to EPWM1_P2_RX. 434 * | | |37 = Channel connects to EPWM1_P3_RX. 435 * | | |38 = Channel connects to I2C0_TX. 436 * | | |39 = Channel connects to I2C0_RX. 437 * | | |40 = Channel connects to I2C1_TX. 438 * | | |41 = Channel connects to I2C1_RX. 439 * | | |42 = Channel connects to I2C2_TX. 440 * | | |43 = Channel connects to I2C2_RX. 441 * | | |44 = Channel connects to I2S0_TX. 442 * | | |45 = Channel connects to I2S0_RX. 443 * | | |46 = Channel connects to TMR0. 444 * | | |47 = Channel connects to TMR1. 445 * | | |48 = Channel connects to TMR2. 446 * | | |49 = Channel connects to TMR3. 447 * | | |50 = Channel connects to ADC_RX. 448 * | | |51 = Channel connects to DAC0_TX. 449 * | | |52 = Channel connects to DAC1_TX. 450 * | | |53 = Channel connects to EPWM0_CH0_TX. 451 * | | |54 = Channel connects to EPWM0_CH1_TX. 452 * | | |55 = Channel connects to EPWM0_CH2_TX. 453 * | | |56 = Channel connects to EPWM0_CH3_TX. 454 * | | |57 = Channel connects to EPWM0_CH4_TX. 455 * | | |58 = Channel connects to EPWM0_CH5_TX. 456 * | | |59 = Channel connects to EPWM1_CH0_TX. 457 * | | |60 = Channel connects to EPWM1_CH1_TX. 458 * | | |61 = Channel connects to EPWM1_CH2_TX. 459 * | | |62 = Channel connects to EPWM1_CH3_TX. 460 * | | |63 = Channel connects to EPWM1_CH4_TX. 461 * | | |64 = Channel connects to EPWM1_CH5_TX. 462 * | | |65 = Channel connects to ETMC_RX. 463 * | | |Others = Reserved. 464 * | | |Note 1: A peripheral can't assign to two channels at the same time. 465 * | | |Note 2: This field is useless when transfer between memory and memory. 466 * |[14:8] |REQSRC1 |Channel 1 Request Source Selection 467 * | | |This filed defines which peripheral is connected to PDMA channel 1 468 * | | |User can configure the peripheral setting by REQSRC1. 469 * | | |Note: The channel configuration is the same as REQSRC0 field 470 * | | |Please refer to the explanation of REQSRC0. 471 * |[22:16] |REQSRC2 |Channel 2 Request Source Selection 472 * | | |This filed defines which peripheral is connected to PDMA channel 2 473 * | | |User can configure the peripheral setting by REQSRC2. 474 * | | |Note: The channel configuration is the same as REQSRC0 field 475 * | | |Please refer to the explanation of REQSRC0. 476 * |[30:24] |REQSRC3 |Channel 3 Request Source Selection 477 * | | |This filed defines which peripheral is connected to PDMA channel 3 478 * | | |User can configure the peripheral setting by REQSRC3. 479 * | | |Note: The channel configuration is the same as REQSRC0 field 480 * | | |Please refer to the explanation of REQSRC0. 481 * @var PDMA_T::REQSEL4_7 482 * Offset: 0x484 PDMA Request Source Select Register 1 483 * --------------------------------------------------------------------------------------------------- 484 * |Bits |Field |Descriptions 485 * | :----: | :----: | :---- | 486 * |[6:0] |REQSRC4 |Channel 4 Request Source Selection 487 * | | |This filed defines which peripheral is connected to PDMA channel 4 488 * | | |User can configure the peripheral setting by REQSRC4. 489 * | | |Note: The channel configuration is the same as REQSRC0 field 490 * | | |Please refer to the explanation of REQSRC0. 491 * |[14:8] |REQSRC5 |Channel 5 Request Source Selection 492 * | | |This filed defines which peripheral is connected to PDMA channel 5 493 * | | |User can configure the peripheral setting by REQSRC5. 494 * | | |Note: The channel configuration is the same as REQSRC0 field 495 * | | |Please refer to the explanation of REQSRC0. 496 * |[22:16] |REQSRC6 |Channel 6 Request Source Selection 497 * | | |This filed defines which peripheral is connected to PDMA channel 6 498 * | | |User can configure the peripheral setting by REQSRC6. 499 * | | |Note: The channel configuration is the same as REQSRC0 field 500 * | | |Please refer to the explanation of REQSRC0. 501 * |[30:24] |REQSRC7 |Channel 7 Request Source Selection 502 * | | |This filed defines which peripheral is connected to PDMA channel 7 503 * | | |User can configure the peripheral setting by REQSRC7. 504 * | | |Note: The channel configuration is the same as REQSRC0 field 505 * | | |Please refer to the explanation of REQSRC0. 506 * @var PDMA_T::REQSEL8_11 507 * Offset: 0x488 PDMA Request Source Select Register 2 508 * --------------------------------------------------------------------------------------------------- 509 * |Bits |Field |Descriptions 510 * | :----: | :----: | :---- | 511 * |[6:0] |REQSRC8 |Channel 8 Request Source Selection 512 * | | |This filed defines which peripheral is connected to PDMA channel 8 513 * | | |User can configure the peripheral setting by REQSRC8. 514 * | | |Note: The channel configuration is the same as REQSRC0 field 515 * | | |Please refer to the explanation of REQSRC0. 516 * |[14:8] |REQSRC9 |Channel 9 Request Source Selection 517 * | | |This filed defines which peripheral is connected to PDMA channel 9 518 * | | |User can configure the peripheral setting by REQSRC9. 519 * | | |Note: The channel configuration is the same as REQSRC0 field 520 * | | |Please refer to the explanation of REQSRC0. 521 * |[22:16] |REQSRC10 |Channel 10 Request Source Selection 522 * | | |This filed defines which peripheral is connected to PDMA channel 10 523 * | | |User can configure the peripheral setting by REQSRC10. 524 * | | |Note: The channel configuration is the same as REQSRC0 field 525 * | | |Please refer to the explanation of REQSRC0. 526 * |[30:24] |REQSRC11 |Channel 11 Request Source Selection 527 * | | |This filed defines which peripheral is connected to PDMA channel 11 528 * | | |User can configure the peripheral setting by REQSRC11. 529 * | | |Note: The channel configuration is the same as REQSRC0 field 530 * | | |Please refer to the explanation of REQSRC0. 531 * @var PDMA_T::REQSEL12_15 532 * Offset: 0x48C PDMA Request Source Select Register 3 533 * --------------------------------------------------------------------------------------------------- 534 * |Bits |Field |Descriptions 535 * | :----: | :----: | :---- | 536 * |[6:0] |REQSRC12 |Channel 12 Request Source Selection 537 * | | |This filed defines which peripheral is connected to PDMA channel 12 538 * | | |User can configure the peripheral setting by REQSRC12. 539 * | | |Note: The channel configuration is the same as REQSRC0 field 540 * | | |Please refer to the explanation of REQSRC0. 541 * |[14:8] |REQSRC13 |Channel 13 Request Source Selection 542 * | | |This filed defines which peripheral is connected to PDMA channel 13 543 * | | |User can configure the peripheral setting by REQSRC13. 544 * | | |Note: The channel configuration is the same as REQSRC0 field 545 * | | |Please refer to the explanation of REQSRC0. 546 * |[22:16] |REQSRC14 |Channel 14 Request Source Selection 547 * | | |This filed defines which peripheral is connected to PDMA channel 14 548 * | | |User can configure the peripheral setting by REQSRC14. 549 * | | |Note: The channel configuration is the same as REQSRC0 field 550 * | | |Please refer to the explanation of REQSRC0. 551 * |[30:24] |REQSRC15 |Channel 15 Request Source Selection 552 * | | |This filed defines which peripheral is connected to PDMA channel 15 553 * | | |User can configure the peripheral setting by REQSRC15. 554 * | | |Note: The channel configuration is the same as REQSRC0 field 555 * | | |Please refer to the explanation of REQSRC0. 556 */ 557 DSCT_T DSCT[16]; 558 __I uint32_t CURSCAT[16]; /*!< [0x0100] Current Scatter-Gather Descriptor Table Address of PDMA Channel n */ 559 /// @cond HIDDEN_SYMBOLS 560 __I uint32_t RESERVE1[176]; 561 /// @endcond //HIDDEN_SYMBOLS 562 __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */ 563 __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */ 564 __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */ 565 __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */ 566 __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */ 567 __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */ 568 __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */ 569 __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */ 570 __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */ 571 __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */ 572 __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */ 573 __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */ 574 __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */ 575 __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */ 576 __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */ 577 __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */ 578 __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Time-out Counter Ch1 and Ch0 Register */ 579 /// @cond HIDDEN_SYMBOLS 580 __I uint32_t RESERVE2[7]; 581 /// @endcond //HIDDEN_SYMBOLS 582 __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */ 583 /// @cond HIDDEN_SYMBOLS 584 __I uint32_t RESERVE3[7]; 585 /// @endcond //HIDDEN_SYMBOLS 586 __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */ 587 __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */ 588 __IO uint32_t REQSEL8_11; /*!< [0x0488] PDMA Request Source Select Register 2 */ 589 __IO uint32_t REQSEL12_15; /*!< [0x048c] PDMA Request Source Select Register 3 */ 590 /// @cond HIDDEN_SYMBOLS 591 __I uint32_t RESERVE4[28]; 592 /// @endcond //HIDDEN_SYMBOLS 593 STRIDE_T STRIDE[6]; 594 /// @cond HIDDEN_SYMBOLS 595 __IO uint32_t RESERVE5[52]; 596 /// @endcond //HIDDEN_SYMBOLS 597 REPEAT_T REPEAT[2]; 598 } PDMA_T; 599 600 /** 601 @addtogroup PDMA_CONST PDMA Bit Field Definition 602 Constant Definitions for PDMA Controller 603 @{ */ 604 605 #define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */ 606 #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */ 607 608 #define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */ 609 #define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */ 610 611 #define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */ 612 #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */ 613 614 #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */ 615 #define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */ 616 617 #define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */ 618 #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */ 619 620 #define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */ 621 #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */ 622 623 #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */ 624 #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */ 625 626 #define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */ 627 #define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */ 628 629 #define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */ 630 #define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */ 631 632 #define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */ 633 #define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */ 634 635 #define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */ 636 #define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */ 637 638 #define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */ 639 #define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */ 640 641 #define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */ 642 #define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */ 643 644 #define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */ 645 #define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */ 646 647 #define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */ 648 #define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */ 649 650 #define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */ 651 #define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */ 652 653 #define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */ 654 #define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */ 655 656 #define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */ 657 #define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */ 658 659 #define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */ 660 #define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */ 661 662 #define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */ 663 #define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */ 664 665 #define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */ 666 #define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */ 667 668 #define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */ 669 #define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */ 670 671 #define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */ 672 #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */ 673 674 #define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */ 675 #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */ 676 677 #define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */ 678 #define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */ 679 680 #define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */ 681 #define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */ 682 683 #define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */ 684 #define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */ 685 686 #define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */ 687 #define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */ 688 689 #define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */ 690 #define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */ 691 692 #define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */ 693 #define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */ 694 695 #define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */ 696 #define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */ 697 698 #define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */ 699 #define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */ 700 701 #define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */ 702 #define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */ 703 704 #define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */ 705 #define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */ 706 707 #define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */ 708 #define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */ 709 710 #define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */ 711 #define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */ 712 713 #define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */ 714 #define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */ 715 716 #define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */ 717 #define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */ 718 719 #define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */ 720 #define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */ 721 722 #define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */ 723 #define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */ 724 725 #define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */ 726 #define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */ 727 728 #define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */ 729 #define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */ 730 731 #define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */ 732 #define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */ 733 734 #define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */ 735 #define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */ 736 737 #define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */ 738 #define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */ 739 740 #define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */ 741 #define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */ 742 743 #define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */ 744 #define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */ 745 746 #define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */ 747 #define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */ 748 749 #define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */ 750 #define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */ 751 752 #define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */ 753 #define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */ 754 755 #define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */ 756 #define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */ 757 758 #define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */ 759 #define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */ 760 761 #define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */ 762 #define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */ 763 764 #define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */ 765 #define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */ 766 767 #define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */ 768 #define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */ 769 770 #define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */ 771 #define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */ 772 773 #define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */ 774 #define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */ 775 776 #define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */ 777 #define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */ 778 779 #define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */ 780 #define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */ 781 782 #define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */ 783 #define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */ 784 785 #define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */ 786 #define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */ 787 788 #define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */ 789 #define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */ 790 791 #define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */ 792 #define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */ 793 794 #define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */ 795 #define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */ 796 797 #define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */ 798 #define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */ 799 800 #define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */ 801 #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */ 802 803 #define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */ 804 #define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */ 805 806 #define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */ 807 #define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */ 808 809 #define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */ 810 #define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */ 811 812 #define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */ 813 #define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */ 814 815 #define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */ 816 #define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */ 817 818 #define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */ 819 #define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */ 820 821 #define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */ 822 #define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */ 823 824 #define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */ 825 #define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */ 826 827 #define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */ 828 #define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */ 829 830 #define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */ 831 #define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */ 832 833 #define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */ 834 #define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */ 835 836 #define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */ 837 #define PDMA_REQSEL8_11_REQSRC8_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */ 838 839 #define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */ 840 #define PDMA_REQSEL8_11_REQSRC9_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */ 841 842 #define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */ 843 #define PDMA_REQSEL8_11_REQSRC10_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */ 844 845 #define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */ 846 #define PDMA_REQSEL8_11_REQSRC11_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */ 847 848 #define PDMA_REQSEL12_15_REQSRC12_Pos (0) /*!< PDMA_T::REQSEL12_15: REQSRC12 Position */ 849 #define PDMA_REQSEL12_15_REQSRC12_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC12 Mask */ 850 851 #define PDMA_REQSEL12_15_REQSRC13_Pos (8) /*!< PDMA_T::REQSEL12_15: REQSRC13 Position */ 852 #define PDMA_REQSEL12_15_REQSRC13_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC13 Mask */ 853 854 #define PDMA_REQSEL12_15_REQSRC14_Pos (16) /*!< PDMA_T::REQSEL12_15: REQSRC14 Position */ 855 #define PDMA_REQSEL12_15_REQSRC14_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC14 Mask */ 856 857 #define PDMA_REQSEL12_15_REQSRC15_Pos (24) /*!< PDMA_T::REQSEL12_15: REQSRC15 Position */ 858 #define PDMA_REQSEL12_15_REQSRC15_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC15 Mask */ 859 860 #define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */ 861 #define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */ 862 863 #define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */ 864 #define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */ 865 866 #define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */ 867 #define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */ 868 869 #define PDMA_RCNTn_RCNT_Pos (0) /*!< PDMA_T::RCNTn: RCNT Position */ 870 #define PDMA_RCNTn_RCNT_Msk (0xfffful << PDMA_STCRn_RCNT_Pos) /*!< PDMA_T::RCNTn: RCNT Mask */ 871 872 #define PDMA_AICTLn_SAICNT_Pos (0) /*!< PDMA_T::AICTLn: SAICNT Position */ 873 #define PDMA_AICTLn_SAICNT_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::AICTLn: SAICNT Mask */ 874 875 #define PDMA_AICTLn_DAICNT_Pos (16) /*!< PDMA_T::AICTLn: DAICNT Position */ 876 #define PDMA_AICTLn_DAICNT_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::AICTLn: DAICNT Mask */ 877 878 /**@}*/ /* PDMA_CONST */ 879 /**@}*/ /* end of PDMA register group */ 880 /**@}*/ /* end of REGISTER group */ 881 882 #if defined ( __CC_ARM ) 883 #pragma no_anon_unions 884 #endif 885 886 #endif /* __PDMA_REG_H__ */ 887
