1 /*
2 * Copyright (c) 2021 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRFY_GRTC_H__
35 #define NRFY_GRTC_H__
36
37 #include <nrfx.h>
38 #include <hal/nrf_grtc.h>
39 #include <soc/nrfx_coredep.h>
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 NRFY_STATIC_INLINE void __nrfy_internal_grtc_event_enabled_clear(NRF_GRTC_Type * p_reg,
46 uint32_t mask,
47 nrf_grtc_event_t event);
48
49 NRFY_STATIC_INLINE bool __nrfy_internal_grtc_event_handle(NRF_GRTC_Type * p_reg,
50 uint32_t mask,
51 nrf_grtc_event_t event,
52 uint32_t * p_evt_mask);
53
54 NRFY_STATIC_INLINE uint32_t __nrfy_internal_grtc_events_process(NRF_GRTC_Type * p_reg,
55 uint32_t mask);
56
57 #if NRF_GRTC_HAS_RTCOUNTER
58 NRFY_STATIC_INLINE uint64_t __nrfy_internal_grtc_rt_counter_read(NRF_GRTC_Type const * p_reg);
59 #endif
60
61 NRFY_STATIC_INLINE bool __nrfy_internal_grtc_sys_counter_ready_check(NRF_GRTC_Type const * p_reg);
62
63 /**
64 * @defgroup nrfy_grtc GRTC HALY
65 * @{
66 * @ingroup nrf_grtc
67 * @brief Hardware access layer with cache and barrier support for managing the GRTC peripheral.
68 */
69
70 #if NRF_GRTC_HAS_EXTENDED || defined(__NRFX_DOXYGEN__)
71 /** @refhal{NRF_GRTC_HAS_EXTENDED} */
72 #define NRFY_GRTC_HAS_EXTENDED 1
73 #else
74 #define NRFY_GRTC_HAS_EXTENDED 0
75 #endif
76
77 #if NRF_GRTC_HAS_RTCOUNTER || defined(__NRFX_DOXYGEN__)
78 /** @refhal{NRF_GRTC_HAS_RTCOUNTER} */
79 #define NRFY_GRTC_HAS_RTCOUNTER 1
80 #else
81 #define NRFY_GRTC_HAS_RTCOUNTER 0
82 #endif
83
84 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY || defined(__NRFX_DOXYGEN__)
85 /** @refhal{NRF_GRTC_HAS_SYSCOUNTER_ARRAY} */
86 #define NRFY_GRTC_HAS_SYSCOUNTER_ARRAY 1
87 #else
88 #define NRFY_GRTC_HAS_SYSCOUNTER_ARRAY 0
89 #endif
90
91 #if NRF_GRTC_HAS_SYSCOUNTERVALID || defined(__NRFX_DOXYGEN__)
92 /** @refhal{NRF_GRTC_HAS_SYSCOUNTERVALID} */
93 #define NRFY_GRTC_HAS_SYSCOUNTERVALID 1
94 #else
95 #define NRFY_GRTC_HAS_SYSCOUNTERVALID 0
96 #endif
97
98 #if NRF_GRTC_HAS_KEEPRUNNING || defined(__NRFX_DOXYGEN__)
99 /** @refhal{NRF_GRTC_HAS_KEEPRUNNING} */
100 #define NRFY_GRTC_HAS_KEEPRUNNING 1
101 #else
102 #define NRFY_GRTC_HAS_KEEPRUNNING 0
103 #endif
104
105 #if NRF_GRTC_HAS_PWM || defined(__NRFX_DOXYGEN__)
106 /** @refhal{NRF_GRTC_HAS_CLKOUT} */
107 #define NRFY_GRTC_HAS_PWM 1
108 #else
109 #define NRFY_GRTC_HAS_PWM 0
110 #endif
111
112 #if NRF_GRTC_HAS_CLKOUT || defined(__NRFX_DOXYGEN__)
113 /** @refhal{NRF_GRTC_HAS_CLKOUT} */
114 #define NRFY_GRTC_HAS_CLKOUT 1
115 #else
116 #define NRFY_GRTC_HAS_CLKOUT 0
117 #endif
118
119 #if NRF_GRTC_HAS_CLKSEL || defined(__NRFX_DOXYGEN__)
120 /** @refhal{NRF_GRTC_HAS_CLKSEL} */
121 #define NRFY_GRTC_HAS_CLKSEL 1
122 #else
123 #define NRFY_GRTC_HAS_CLKSEL 0
124 #endif
125
126 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY || defined(__NRFX_DOXYGEN__)
127 /** @brief Mask to determine whether the SYSCOUNTER value is reliable. */
128 #define NRFY_GRTC_SYSCOUNTER_RETRY_MASK \
129 ((uint64_t)(NRF_GRTC_SYSCOUNTERH_OVERFLOW_MASK + NRF_GRTC_SYSCOUNTERH_BUSY_MASK) << 32)
130 #else
131 #define NRFY_GRTC_SYSCOUNTER_RETRY_MASK ((uint64_t)(NRF_GRTC_SYSCOUNTERH_OVERFLOW_MASK) << 32)
132 #endif
133
134 /** @brief Mask of the SYSCOUNTER value. */
135 #define NRFY_GRTC_SYSCOUNTER_MASK ((uint64_t)(NRF_GRTC_SYSCOUNTERL_VALUE_MASK) + \
136 ((uint64_t)(NRF_GRTC_SYSCOUNTERH_VALUE_MASK) << 32))
137
138 /**
139 * @brief Function for initializing the specified GRTC interrupts.
140 *
141 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
142 * @param[in] mask Mask of interrupts to be initialized.
143 * @param[in] irq_priority Interrupt priority.
144 * @param[in] enable True if the interrupts are to be enabled, false otherwise.
145 */
nrfy_grtc_int_init(NRF_GRTC_Type * p_reg,uint32_t mask,uint8_t irq_priority,bool enable)146 NRFY_STATIC_INLINE void nrfy_grtc_int_init(NRF_GRTC_Type * p_reg,
147 uint32_t mask,
148 uint8_t irq_priority,
149 bool enable)
150 {
151 for (uint8_t cc_channel = 0; cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT; cc_channel++)
152 {
153 nrf_grtc_event_t event = nrf_grtc_sys_counter_compare_event_get(cc_channel);
154 __nrfy_internal_grtc_event_enabled_clear(p_reg, mask, event);
155 }
156 #if NRFY_GRTC_HAS_RTCOUNTER
157 __nrfy_internal_grtc_event_enabled_clear(p_reg, mask, NRF_GRTC_EVENT_RTCOMPARE);
158 __nrfy_internal_grtc_event_enabled_clear(p_reg, mask, NRF_GRTC_EVENT_RTCOMPARESYNC);
159 #endif
160 nrf_barrier_w();
161
162 NRFX_IRQ_PRIORITY_SET(GRTC_IRQn, irq_priority);
163 NRFX_IRQ_ENABLE(GRTC_IRQn);
164 if (enable)
165 {
166 nrf_grtc_int_enable(p_reg, mask);
167 }
168 nrf_barrier_w();
169 }
170
171 /**
172 * @brief Function for uninitializing the GRTC interrupts.
173 *
174 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
175 */
nrfy_grtc_int_uninit(NRF_GRTC_Type * p_reg)176 NRFY_STATIC_INLINE void nrfy_grtc_int_uninit(NRF_GRTC_Type * p_reg)
177 {
178 (void)p_reg;
179 NRFX_IRQ_DISABLE(GRTC_IRQn);
180 nrf_barrier_w();
181 }
182
183 /**
184 * @brief Function for processing the specified GRTC events.
185 *
186 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
187 * @param[in] mask Mask of events to be processed, created by @ref NRFY_EVENT_TO_INT_BITMASK().
188 *
189 * @return Mask of events that were generated and processed.
190 * To be checked against the result of @ref NRFY_EVENT_TO_INT_BITMASK().
191 */
nrfy_grtc_events_process(NRF_GRTC_Type * p_reg,uint32_t mask)192 NRFY_STATIC_INLINE uint32_t nrfy_grtc_events_process(NRF_GRTC_Type * p_reg,
193 uint32_t mask)
194 {
195 uint32_t evt_mask = __nrfy_internal_grtc_events_process(p_reg, mask);
196
197 nrf_barrier_w();
198 return evt_mask;
199 }
200
201 #if NRFY_GRTC_HAS_EXTENDED
202 /**
203 * @brief Function for preparing the GRTC peripheral.
204 *
205 * @note This function clears all shorts, interrupts, resets and starts the GRTC.
206 *
207 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
208 * @param[in] busy_wait True if wait for synchronization operation is to be performed,
209 * false otherwise.
210 */
nrfy_grtc_prepare(NRF_GRTC_Type * p_reg,bool busy_wait)211 NRFY_STATIC_INLINE void nrfy_grtc_prepare(NRF_GRTC_Type * p_reg, bool busy_wait)
212 {
213 #if NRFY_GRTC_HAS_CLKSEL
214 nrf_grtc_clksel_set(p_reg, NRF_GRTC_CLKSEL_LFCLK);
215 #endif
216 nrf_grtc_sys_counter_set(p_reg, false);
217 nrf_barrier_w();
218 #if NRFY_GRTC_HAS_RTCOUNTER
219 nrf_grtc_shorts_disable(p_reg, NRF_GRTC_SHORT_RTCOMPARE_CLEAR_MASK);
220 #endif
221 nrf_grtc_int_disable(p_reg, NRF_GRTC_INTEN_MASK);
222 for (uint8_t cc_channel = 0; cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT; cc_channel++)
223 {
224 nrf_grtc_publish_clear(p_reg, nrf_grtc_sys_counter_compare_event_get(cc_channel));
225 nrf_grtc_subscribe_clear(p_reg, nrf_grtc_sys_counter_capture_task_get(cc_channel));
226 }
227 #if NRFY_GRTC_HAS_RTCOUNTER
228 nrf_grtc_publish_clear(p_reg, NRF_GRTC_EVENT_RTCOMPARE);
229 #endif
230 #if NRFX_IS_ENABLED(NRFX_GRTC_CONFIG_CLEAR_AT_INIT)
231 nrf_grtc_task_trigger(p_reg, NRF_GRTC_TASK_CLEAR);
232 nrf_barrier_w();
233 #endif
234 nrf_grtc_task_trigger(p_reg, NRF_GRTC_TASK_START);
235 nrf_barrier_w();
236 if (busy_wait)
237 {
238 #if NRFY_GRTC_HAS_RTCOUNTER
239 #if NRFX_IS_ENABLED(NRFX_GRTC_CONFIG_CLEAR_AT_INIT)
240 // Make sure that RTCOUNTER is cleared and does not contain the old value.
241 while (__nrfy_internal_grtc_rt_counter_read(p_reg) > 1ULL)
242 {}
243 #endif
244 // Wait one 32k cycle to make sure that RTCOUNTER has started.
245 uint64_t t = __nrfy_internal_grtc_rt_counter_read(p_reg);
246 while (__nrfy_internal_grtc_rt_counter_read(p_reg) == t)
247 {}
248 #else
249 // Wait 3 32k cycles.
250 // `NRFX_DELAY_US()` macro cannot be used here because in Zephyr environment
251 // it calls `k_busy_wait()`. This function relies on system timer which is
252 // not started yet.
253 nrfx_coredep_delay_us(93);
254 #endif // NRFY_GRTC_HAS_RTCOUNTER
255 }
256 }
257
258 /**
259 * @brief Function for starting the SYSCOUNTER.
260 *
261 * @note This function enables the 1 MHz counter and set it as always active.
262 *
263 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
264 * @param[in] busy_wait True if wait for synchronization operation is to be performed,
265 * false otherwise.
266 */
nrfy_grtc_sys_counter_start(NRF_GRTC_Type * p_reg,bool busy_wait)267 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_start(NRF_GRTC_Type * p_reg, bool busy_wait)
268 {
269 nrf_grtc_sys_counter_set(p_reg, true);
270 nrf_barrier_w();
271 if (busy_wait)
272 {
273 bool active;
274 #if NRFY_GRTC_HAS_SYSCOUNTER_ARRAY
275 active = nrf_grtc_sys_counter_active_check(p_reg);
276 nrf_barrier_r();
277 if (!active)
278 {
279 nrf_grtc_sys_counter_active_set(p_reg, true);
280 nrf_barrier_w();
281 }
282 #else
283 active = nrf_grtc_sys_counter_active_state_request_check(p_reg);
284 nrf_barrier_r();
285 if (!active)
286 {
287 nrf_grtc_sys_counter_active_state_request_set(p_reg, true);
288 nrf_barrier_w();
289 }
290 #endif // NRFY_GRTC_HAS_SYSCOUNTER_ARRAY
291 while (!__nrfy_internal_grtc_sys_counter_ready_check(p_reg))
292 {}
293
294 if (!active)
295 {
296 #if NRFY_GRTC_HAS_SYSCOUNTER_ARRAY
297 nrf_grtc_sys_counter_active_set(p_reg, false);
298 #else
299 nrf_grtc_sys_counter_active_state_request_set(p_reg, true);
300 #endif
301 nrf_barrier_w();
302 }
303
304 }
305 }
306 #endif // NRFY_GRTC_HAS_EXTENDED
307
308 /**
309 * @brief Function for returning the SYSCOUNTER 1 MHz value.
310 *
311 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
312 *
313 * @return SYSCOUNTER value.
314 */
nrfy_grtc_sys_counter_get(NRF_GRTC_Type const * p_reg)315 NRFY_STATIC_INLINE uint64_t nrfy_grtc_sys_counter_get(NRF_GRTC_Type const * p_reg)
316 {
317 #if NRFX_CHECK(ISA_ARM) && (__CORTEX_M == 33U)
318 uint64_t counter;
319
320 do {
321 counter = nrf_grtc_sys_counter_get(p_reg);
322 } while (counter & NRFY_GRTC_SYSCOUNTER_RETRY_MASK);
323 return (counter & NRFY_GRTC_SYSCOUNTER_MASK);
324 #else
325 uint32_t counter_l, counter_h;
326
327 do {
328 counter_l = nrf_grtc_sys_counter_low_get(p_reg);
329 nrf_barrier_r();
330 counter_h = nrf_grtc_sys_counter_high_get(p_reg);
331 nrf_barrier_r();
332 } while (counter_h & NRF_GRTC_SYSCOUNTERH_OVERFLOW_MASK);
333 return (uint64_t)counter_l | ((uint64_t)(counter_h & NRF_GRTC_SYSCOUNTERH_VALUE_MASK) << 32);
334 #endif // NRFX_CHECK(ISA_ARM) && (__CORTEX_M == 33U)
335 }
336
337 /**
338 * @brief Function for checking whether SYSCOUNTER value is ready to be read.
339 *
340 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
341 *
342 * @return True if SYSCOUNTER is ready to be read, false otherwise.
343 */
nrfy_grtc_sys_counter_ready_check(NRF_GRTC_Type const * p_reg)344 NRFY_STATIC_INLINE bool nrfy_grtc_sys_counter_ready_check(NRF_GRTC_Type const * p_reg)
345 {
346 return __nrfy_internal_grtc_sys_counter_ready_check(p_reg);
347 }
348
349 #if NRFY_GRTC_HAS_RTCOUNTER
350 /**
351 * @brief Function for returning the RTCOUNTER 32 kHz value.
352 *
353 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
354 *
355 * @return RTCOUNTER value.
356 */
nrfy_grtc_rt_counter_get(NRF_GRTC_Type const * p_reg)357 NRFY_STATIC_INLINE uint64_t nrfy_grtc_rt_counter_get(NRF_GRTC_Type const * p_reg)
358 {
359 return __nrfy_internal_grtc_rt_counter_read(p_reg);
360 }
361 #endif // NRFY_GRTC_HAS_RTCOUNTER
362
363 /**
364 * @brief Function for enabling the GRTC compare event and optionally associated interrupt.
365 *
366 * @note Event is implicitly cleared before enabling the associated interrupt.
367 *
368 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
369 * @param[in] channel Channel representing the GRTC compare event.
370 * @param[in] enable True if associated interrupt is to be enabled, false otherwise.
371 */
372 NRFY_STATIC_INLINE
nrfy_grtc_sys_counter_compare_event_int_clear_enable(NRF_GRTC_Type * p_reg,uint8_t channel,bool enable)373 void nrfy_grtc_sys_counter_compare_event_int_clear_enable(NRF_GRTC_Type * p_reg,
374 uint8_t channel,
375 bool enable)
376 {
377 nrf_grtc_event_t event = nrf_grtc_sys_counter_compare_event_get(channel);
378
379 if (enable)
380 {
381 nrf_grtc_event_clear(p_reg, event);
382 nrf_barrier_w();
383 nrf_grtc_int_enable(p_reg, NRFY_EVENT_TO_INT_BITMASK(event));
384 }
385 nrf_grtc_sys_counter_compare_event_enable(p_reg, channel);
386 nrf_barrier_w();
387 }
388
389 /**
390 * @brief Function for retrieving the state of the compare GRTC event.
391 *
392 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
393 * @param[in] cc_channel Compare channel of the corresponding event to be checked.
394 *
395 * @retval true The event has been generated.
396 * @retval false The event has not been generated.
397 */
nrfy_grtc_sys_counter_compare_event_check(NRF_GRTC_Type const * p_reg,uint8_t cc_channel)398 NRFY_STATIC_INLINE bool nrfy_grtc_sys_counter_compare_event_check(NRF_GRTC_Type const * p_reg,
399 uint8_t cc_channel)
400 {
401 nrf_barrier_r();
402 bool check = nrf_grtc_event_check(p_reg, nrf_grtc_sys_counter_compare_event_get(cc_channel));
403 nrf_barrier_r();
404 return check;
405 }
406
407 /**
408 * @brief Function for clearing a compare GRTC event.
409 *
410 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
411 * @param[in] cc_channel Compare channel of the corresponding event to be cleared.
412 */
nrfy_grtc_sys_counter_compare_event_clear(NRF_GRTC_Type * p_reg,uint8_t cc_channel)413 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_compare_event_clear(NRF_GRTC_Type * p_reg,
414 uint8_t cc_channel)
415 {
416 nrf_grtc_event_clear(p_reg, nrf_grtc_sys_counter_compare_event_get(cc_channel));
417 nrf_barrier_w();
418 }
419
420 /**
421 * @brief Function for setting the subscribe configuration for a given
422 * GRTC capture channel.
423 *
424 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
425 * @param[in] cc_channel Compare channel for which to set the configuration.
426 * @param[in] channel Channel through which to subscribe events.
427 */
nrfy_grtc_sys_counter_capture_subscribe_set(NRF_GRTC_Type * p_reg,uint8_t cc_channel,uint8_t channel)428 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_capture_subscribe_set(NRF_GRTC_Type * p_reg,
429 uint8_t cc_channel,
430 uint8_t channel)
431 {
432 nrf_grtc_subscribe_set(p_reg, nrf_grtc_sys_counter_capture_task_get(cc_channel), channel);
433 nrf_barrier_w();
434 }
435
436 /**
437 * @brief Function for clearing the subscribe configuration for a given
438 * GRTC capture channel.
439 *
440 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
441 * @param[in] cc_channel Compare channel for which to clear the configuration.
442 */
nrfy_grtc_sys_counter_capture_subscribe_clear(NRF_GRTC_Type * p_reg,uint8_t cc_channel)443 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_capture_subscribe_clear(NRF_GRTC_Type * p_reg,
444 uint8_t cc_channel)
445 {
446 nrf_grtc_subscribe_clear(p_reg, nrf_grtc_sys_counter_capture_task_get(cc_channel));
447 nrf_barrier_w();
448 }
449
450 /**
451 * @brief Function for setting the publish configuration for a given
452 * GRTC compare channel.
453 *
454 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
455 * @param[in] cc_channel Compare channel for which to set the configuration.
456 * @param[in] channel Channel through which to publish the event.
457 */
nrfy_grtc_sys_counter_compare_publish_set(NRF_GRTC_Type * p_reg,uint8_t cc_channel,uint8_t channel)458 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_compare_publish_set(NRF_GRTC_Type * p_reg,
459 uint8_t cc_channel,
460 uint8_t channel)
461 {
462 nrf_grtc_publish_set(p_reg, nrf_grtc_sys_counter_compare_event_get(cc_channel), channel);
463 nrf_barrier_w();
464 }
465
466 /**
467 * @brief Function for clearing the publish configuration for a given
468 * GRTC compare channel.
469 *
470 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
471 * @param[in] cc_channel Compare channel for which to clear the configuration.
472 */
nrfy_grtc_sys_counter_compare_publish_clear(NRF_GRTC_Type * p_reg,uint8_t cc_channel)473 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_compare_publish_clear(NRF_GRTC_Type * p_reg,
474 uint8_t cc_channel)
475 {
476 nrf_grtc_publish_clear(p_reg, nrf_grtc_sys_counter_compare_event_get(cc_channel));
477 nrf_barrier_w();
478 }
479
480 /** @refhal{nrf_grtc_sys_counter_cc_set} */
nrfy_grtc_sys_counter_cc_set(NRF_GRTC_Type * p_reg,uint8_t cc_channel,uint64_t cc_value)481 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_cc_set(NRF_GRTC_Type * p_reg,
482 uint8_t cc_channel,
483 uint64_t cc_value)
484 {
485 nrf_grtc_sys_counter_cc_set(p_reg, cc_channel, cc_value);
486 nrf_barrier_w();
487 }
488
489 /** @refhal{nrf_grtc_sys_counter_cc_get} */
nrfy_grtc_sys_counter_cc_get(NRF_GRTC_Type const * p_reg,uint8_t cc_channel)490 NRFY_STATIC_INLINE uint64_t nrfy_grtc_sys_counter_cc_get(NRF_GRTC_Type const * p_reg,
491 uint8_t cc_channel)
492 {
493 nrf_barrier_rw();
494 uint64_t cc = nrf_grtc_sys_counter_cc_get(p_reg, cc_channel);
495 nrf_barrier_r();
496 return cc;
497 }
498
499 /** @refhal{nrf_grtc_sys_counter_cc_add_set} */
nrfy_grtc_sys_counter_cc_add_set(NRF_GRTC_Type * p_reg,uint8_t cc_channel,uint32_t value,nrf_grtc_cc_add_reference_t reference)500 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_cc_add_set(NRF_GRTC_Type * p_reg,
501 uint8_t cc_channel,
502 uint32_t value,
503 nrf_grtc_cc_add_reference_t reference)
504 {
505 nrf_grtc_sys_counter_cc_add_set(p_reg, cc_channel, value, reference);
506 nrf_barrier_w();
507 }
508
509 #if NRFY_GRTC_HAS_RTCOUNTER
510 /** @refhal{nrf_grtc_rt_counter_cc_set} */
nrfy_grtc_rt_counter_cc_set(NRF_GRTC_Type * p_reg,uint64_t cc_value,bool sync)511 NRFY_STATIC_INLINE void nrfy_grtc_rt_counter_cc_set(NRF_GRTC_Type * p_reg,
512 uint64_t cc_value,
513 bool sync)
514 {
515 nrf_grtc_rt_counter_cc_set(p_reg, cc_value, sync);
516 nrf_barrier_w();
517 }
518
519 /** @refhal{nrf_grtc_rt_counter_cc_get} */
nrfy_grtc_rt_counter_cc_get(NRF_GRTC_Type const * p_reg)520 NRFY_STATIC_INLINE uint64_t nrfy_grtc_rt_counter_cc_get(NRF_GRTC_Type const * p_reg)
521 {
522 nrf_barrier_rw();
523 uint64_t cc = nrf_grtc_rt_counter_cc_get(p_reg);
524 nrf_barrier_r();
525 return cc;
526 }
527 #endif // NRFY_GRTC_HAS_RTCOUNTER
528
529 /** @refhal{nrf_grtc_int_enable} */
nrfy_grtc_int_enable(NRF_GRTC_Type * p_reg,uint32_t mask)530 NRFY_STATIC_INLINE void nrfy_grtc_int_enable(NRF_GRTC_Type * p_reg, uint32_t mask)
531 {
532 nrf_grtc_int_enable(p_reg, mask);
533 nrf_barrier_w();
534 }
535
536 /** @refhal{nrf_grtc_int_disable} */
nrfy_grtc_int_disable(NRF_GRTC_Type * p_reg,uint32_t mask)537 NRFY_STATIC_INLINE void nrfy_grtc_int_disable(NRF_GRTC_Type * p_reg, uint32_t mask)
538 {
539 nrf_grtc_int_disable(p_reg, mask);
540 nrf_barrier_w();
541 }
542
543 /** @refhal{nrf_grtc_int_enable_check} */
nrfy_grtc_int_enable_check(NRF_GRTC_Type const * p_reg,uint32_t mask)544 NRFY_STATIC_INLINE uint32_t nrfy_grtc_int_enable_check(NRF_GRTC_Type const * p_reg, uint32_t mask)
545 {
546 nrf_barrier_rw();
547 uint32_t check = nrf_grtc_int_enable_check(p_reg, mask);
548 nrf_barrier_r();
549 return check;
550 }
551
552 /** @refhal{nrf_grtc_int_pending_get} */
nrfy_grtc_int_pending_get(NRF_GRTC_Type const * p_reg)553 NRFY_STATIC_INLINE uint32_t nrfy_grtc_int_pending_get(NRF_GRTC_Type const * p_reg)
554 {
555 nrf_barrier_r();
556 uint32_t pending = nrf_grtc_int_pending_get(p_reg);
557 nrf_barrier_r();
558 return pending;
559 }
560
561 #if NRFY_GRTC_HAS_EXTENDED
562 /** @refhal{nrf_grtc_shorts_enable} */
nrfy_grtc_shorts_enable(NRF_GRTC_Type * p_reg,uint32_t mask)563 NRFY_STATIC_INLINE void nrfy_grtc_shorts_enable(NRF_GRTC_Type * p_reg, uint32_t mask)
564 {
565 nrf_grtc_shorts_enable(p_reg, mask);
566 nrf_barrier_w();
567 }
568
569 /** @refhal{nrf_grtc_shorts_disable} */
nrfy_grtc_shorts_disable(NRF_GRTC_Type * p_reg,uint32_t mask)570 NRFY_STATIC_INLINE void nrfy_grtc_shorts_disable(NRF_GRTC_Type * p_reg, uint32_t mask)
571 {
572 nrf_grtc_shorts_disable(p_reg, mask);
573 nrf_barrier_w();
574 }
575
576 /** @refhal{nrf_grtc_shorts_set} */
nrfy_grtc_shorts_set(NRF_GRTC_Type * p_reg,uint32_t mask)577 NRFY_STATIC_INLINE void nrfy_grtc_shorts_set(NRF_GRTC_Type * p_reg, uint32_t mask)
578 {
579 nrf_grtc_shorts_set(p_reg, mask);
580 nrf_barrier_w();
581 }
582 #endif // NRFY_GRTC_HAS_EXTENDED
583
584 /** @refhal{nrf_grtc_subscribe_set} */
nrfy_grtc_subscribe_set(NRF_GRTC_Type * p_reg,nrf_grtc_task_t task,uint8_t channel)585 NRFY_STATIC_INLINE void nrfy_grtc_subscribe_set(NRF_GRTC_Type * p_reg,
586 nrf_grtc_task_t task,
587 uint8_t channel)
588 {
589 nrf_grtc_subscribe_set(p_reg, task, channel);
590 nrf_barrier_w();
591 }
592
593 /** @refhal{nrf_grtc_subscribe_clear} */
nrfy_grtc_subscribe_clear(NRF_GRTC_Type * p_reg,nrf_grtc_task_t task)594 NRFY_STATIC_INLINE void nrfy_grtc_subscribe_clear(NRF_GRTC_Type * p_reg, nrf_grtc_task_t task)
595 {
596 nrf_grtc_subscribe_clear(p_reg, task);
597 nrf_barrier_w();
598 }
599
600 /** @refhal{nrf_grtc_publish_set} */
nrfy_grtc_publish_set(NRF_GRTC_Type * p_reg,nrf_grtc_event_t event,uint8_t channel)601 NRFY_STATIC_INLINE void nrfy_grtc_publish_set(NRF_GRTC_Type * p_reg,
602 nrf_grtc_event_t event,
603 uint8_t channel)
604 {
605 nrf_grtc_publish_set(p_reg, event, channel);
606 nrf_barrier_w();
607 }
608
609 /** @refhal{nrf_grtc_publish_clear} */
nrfy_grtc_publish_clear(NRF_GRTC_Type * p_reg,nrf_grtc_event_t event)610 NRFY_STATIC_INLINE void nrfy_grtc_publish_clear(NRF_GRTC_Type * p_reg, nrf_grtc_event_t event)
611 {
612 nrf_grtc_publish_clear(p_reg, event);
613 nrf_barrier_w();
614 }
615
616 /** @refhal{nrf_grtc_event_check} */
nrfy_grtc_event_check(NRF_GRTC_Type const * p_reg,nrf_grtc_event_t event)617 NRFY_STATIC_INLINE bool nrfy_grtc_event_check(NRF_GRTC_Type const * p_reg, nrf_grtc_event_t event)
618 {
619 nrf_barrier_r();
620 bool check = nrf_grtc_event_check(p_reg, event);
621 nrf_barrier_r();
622 return check;
623 }
624
625 /** @refhal{nrf_grtc_event_clear} */
nrfy_grtc_event_clear(NRF_GRTC_Type * p_reg,nrf_grtc_event_t event)626 NRFY_STATIC_INLINE void nrfy_grtc_event_clear(NRF_GRTC_Type * p_reg, nrf_grtc_event_t event)
627 {
628 nrf_grtc_event_clear(p_reg, event);
629 nrf_barrier_w();
630 }
631
632 /** @refhal{nrf_grtc_sys_counter_overflow_check} */
nrfy_grtc_sys_counter_overflow_check(NRF_GRTC_Type const * p_reg)633 NRFY_STATIC_INLINE bool nrfy_grtc_sys_counter_overflow_check(NRF_GRTC_Type const * p_reg)
634 {
635 nrf_barrier_r();
636 bool check = nrf_grtc_sys_counter_overflow_check(p_reg);
637 nrf_barrier_r();
638 return check;
639 }
640
641 /** @refhal{nrf_grtc_event_address_get} */
nrfy_grtc_event_address_get(NRF_GRTC_Type const * p_reg,nrf_grtc_event_t event)642 NRFY_STATIC_INLINE uint32_t nrfy_grtc_event_address_get(NRF_GRTC_Type const * p_reg,
643 nrf_grtc_event_t event)
644 {
645 return nrf_grtc_event_address_get(p_reg, event);
646 }
647
648 /** @refhal{nrf_grtc_task_address_get} */
nrfy_grtc_task_address_get(NRF_GRTC_Type const * p_reg,nrf_grtc_task_t task)649 NRFY_STATIC_INLINE uint32_t nrfy_grtc_task_address_get(NRF_GRTC_Type const * p_reg,
650 nrf_grtc_task_t task)
651 {
652 return nrf_grtc_task_address_get(p_reg, task);
653 }
654
655 /** @refhal{nrf_grtc_task_trigger} */
nrfy_grtc_task_trigger(NRF_GRTC_Type * p_reg,nrf_grtc_task_t task)656 NRFY_STATIC_INLINE void nrfy_grtc_task_trigger(NRF_GRTC_Type * p_reg, nrf_grtc_task_t task)
657 {
658 nrf_grtc_task_trigger(p_reg, task);
659 nrf_barrier_w();
660 }
661
662 /** @refhal{nrf_grtc_sys_counter_capture_task_get} */
nrfy_grtc_sys_counter_capture_task_get(uint8_t cc_channel)663 NRFY_STATIC_INLINE nrf_grtc_task_t nrfy_grtc_sys_counter_capture_task_get(uint8_t cc_channel)
664 {
665 return nrf_grtc_sys_counter_capture_task_get(cc_channel);
666 }
667
668 /** @refhal{nrf_grtc_sys_counter_compare_event_enable} */
nrfy_grtc_sys_counter_compare_event_enable(NRF_GRTC_Type * p_reg,uint8_t cc_channel)669 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_compare_event_enable(NRF_GRTC_Type * p_reg,
670 uint8_t cc_channel)
671 {
672 nrf_grtc_sys_counter_compare_event_enable(p_reg, cc_channel);
673 nrf_barrier_w();
674 }
675
676 /** @refhal{nrf_grtc_sys_counter_compare_event_disable} */
nrfy_grtc_sys_counter_compare_event_disable(NRF_GRTC_Type * p_reg,uint8_t cc_channel)677 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_compare_event_disable(NRF_GRTC_Type * p_reg,
678 uint8_t cc_channel)
679 {
680 nrf_grtc_sys_counter_compare_event_disable(p_reg, cc_channel);
681 nrf_barrier_w();
682 }
683
684 /** @refhal{nrf_grtc_sys_counter_compare_event_get} */
nrfy_grtc_sys_counter_compare_event_get(uint8_t cc_channel)685 NRFY_STATIC_INLINE nrf_grtc_event_t nrfy_grtc_sys_counter_compare_event_get(uint8_t cc_channel)
686 {
687 return nrf_grtc_sys_counter_compare_event_get(cc_channel);
688 }
689
690 /** @refhal{nrf_grtc_sys_counter_cc_enable_check} */
nrfy_grtc_sys_counter_cc_enable_check(NRF_GRTC_Type const * p_reg,uint8_t cc_channel)691 NRFY_STATIC_INLINE bool nrfy_grtc_sys_counter_cc_enable_check(NRF_GRTC_Type const * p_reg,
692 uint8_t cc_channel)
693 {
694 nrf_barrier_rw();
695 bool check = nrf_grtc_sys_counter_cc_enable_check(p_reg, cc_channel);
696 nrf_barrier_r();
697 return check;
698 }
699
700 #if NRFY_GRTC_HAS_EXTENDED
701 /** @refhal{nrf_grtc_sys_counter_set} */
nrfy_grtc_sys_counter_set(NRF_GRTC_Type * p_reg,bool enable)702 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_set(NRF_GRTC_Type * p_reg, bool enable)
703 {
704 nrf_grtc_sys_counter_set(p_reg, enable);
705 nrf_barrier_w();
706 }
707
708 /** @refhal{nrf_grtc_sys_counter_auto_mode_set} */
nrfy_grtc_sys_counter_auto_mode_set(NRF_GRTC_Type * p_reg,bool enable)709 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_auto_mode_set(NRF_GRTC_Type * p_reg, bool enable)
710 {
711 nrf_grtc_sys_counter_auto_mode_set(p_reg, enable);
712 nrf_barrier_w();
713 }
714
715 /** @refhal{nrf_grtc_sys_counter_auto_mode_check} */
nrfy_grtc_sys_counter_auto_mode_check(NRF_GRTC_Type * p_reg)716 NRFY_STATIC_INLINE bool nrfy_grtc_sys_counter_auto_mode_check(NRF_GRTC_Type * p_reg)
717 {
718 nrf_barrier_rw();
719 bool check = nrf_grtc_sys_counter_auto_mode_check(p_reg);
720 nrf_barrier_r();
721 return check;
722 }
723 #endif // NRFY_GRTC_HAS_EXTENDED
724
725 #if NRFY_GRTC_HAS_SYSCOUNTER_ARRAY
726 /** @refhal{nrf_grtc_sys_counter_active_set} */
nrfy_grtc_sys_counter_active_set(NRF_GRTC_Type * p_reg,bool enable)727 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_active_set(NRF_GRTC_Type * p_reg, bool enable)
728 {
729 nrf_grtc_sys_counter_active_set(p_reg, enable);
730 nrf_barrier_w();
731 }
732
733 /** @refhal{nrf_grtc_sys_counter_active_check} */
nrfy_grtc_sys_counter_active_check(NRF_GRTC_Type const * p_reg)734 NRFY_STATIC_INLINE bool nrfy_grtc_sys_counter_active_check(NRF_GRTC_Type const * p_reg)
735 {
736 nrf_barrier_rw();
737 bool check = nrf_grtc_sys_counter_active_check(p_reg);
738 nrf_barrier_r();
739 return check;
740 }
741 #endif // NRFY_GRTC_HAS_SYSCOUNTER_ARRAY
742
743 /** @refhal{nrf_grtc_sys_counter_check} */
nrfy_grtc_sys_counter_check(NRF_GRTC_Type * p_reg)744 NRFY_STATIC_INLINE bool nrfy_grtc_sys_counter_check(NRF_GRTC_Type * p_reg)
745 {
746 return nrf_grtc_sys_counter_check(p_reg);
747 }
748
749 #if NRFY_GRTC_HAS_KEEPRUNNING
750 /** @refhal{nrf_grtc_sys_counter_active_state_request_set} */
nrfy_grtc_sys_counter_active_state_request_set(NRF_GRTC_Type * p_reg,bool enable)751 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_active_state_request_set(NRF_GRTC_Type * p_reg,
752 bool enable)
753 {
754 nrf_grtc_sys_counter_active_state_request_set(p_reg, enable);
755 nrf_barrier_w();
756 }
757
758 /** @refhal{nrf_grtc_sys_counter_active_state_request_check} */
759 NRFY_STATIC_INLINE
nrfy_grtc_sys_counter_active_state_request_check(NRF_GRTC_Type const * p_reg)760 bool nrfy_grtc_sys_counter_active_state_request_check(NRF_GRTC_Type const * p_reg)
761 {
762 nrf_barrier_rw();
763 bool check = nrf_grtc_sys_counter_active_state_request_check(p_reg);
764 nrf_barrier_r();
765 return check;
766 }
767
768 /** @refhal{nrf_grtc_sys_counter_active_state_request_get} */
769 NRFY_STATIC_INLINE
nrfy_grtc_sys_counter_active_state_request_get(NRF_GRTC_Type const * p_reg,uint32_t mask)770 uint32_t nrfy_grtc_sys_counter_active_state_request_get(NRF_GRTC_Type const * p_reg,
771 uint32_t mask)
772 {
773 nrf_barrier_rw();
774 uint32_t request = nrf_grtc_sys_counter_active_state_request_get(p_reg, mask);
775 nrf_barrier_r();
776 return request;
777 }
778 #endif // NRFY_GRTC_HAS_KEEPRUNNING
779
780 #if NRFY_GRTC_HAS_EXTENDED
781 /** @refhal{nrf_grtc_sys_counter_interval_set} */
nrfy_grtc_sys_counter_interval_set(NRF_GRTC_Type * p_reg,uint32_t value)782 NRFY_STATIC_INLINE void nrfy_grtc_sys_counter_interval_set(NRF_GRTC_Type * p_reg, uint32_t value)
783 {
784 nrf_grtc_sys_counter_interval_set(p_reg, value);
785 nrf_barrier_w();
786 }
787
788 /** @refhal{nrf_grtc_sys_counter_interval_get} */
nrfy_grtc_sys_counter_interval_get(NRF_GRTC_Type const * p_reg)789 NRFY_STATIC_INLINE uint32_t nrfy_grtc_sys_counter_interval_get(NRF_GRTC_Type const * p_reg)
790 {
791 nrf_barrier_rw();
792 uint32_t interval = nrf_grtc_sys_counter_interval_get(p_reg);
793 nrf_barrier_r();
794 return interval;
795 }
796
797 /** @refhal{nrf_grtc_timeout_set} */
nrfy_grtc_timeout_set(NRF_GRTC_Type * p_reg,uint32_t value)798 NRFY_STATIC_INLINE void nrfy_grtc_timeout_set(NRF_GRTC_Type * p_reg, uint32_t value)
799 {
800 nrf_grtc_timeout_set(p_reg, value);
801 nrf_barrier_w();
802 }
803
804 /** @refhal{nrf_grtc_timeout_get} */
nrfy_grtc_timeout_get(NRF_GRTC_Type const * p_reg)805 NRFY_STATIC_INLINE uint32_t nrfy_grtc_timeout_get(NRF_GRTC_Type const * p_reg)
806 {
807 nrf_barrier_rw();
808 uint32_t timeout = nrf_grtc_timeout_get(p_reg);
809 nrf_barrier_r();
810 return timeout;
811 }
812
813 /** @refhal{nrf_grtc_waketime_set} */
nrfy_grtc_waketime_set(NRF_GRTC_Type * p_reg,uint32_t value)814 NRFY_STATIC_INLINE void nrfy_grtc_waketime_set(NRF_GRTC_Type * p_reg, uint32_t value)
815 {
816 nrf_grtc_waketime_set(p_reg, value);
817 nrf_barrier_w();
818 }
819
820 /** @refhal{nrf_grtc_waketime_get} */
nrfy_grtc_waketime_get(NRF_GRTC_Type const * p_reg)821 NRFY_STATIC_INLINE uint32_t nrfy_grtc_waketime_get(NRF_GRTC_Type const * p_reg)
822 {
823 nrf_barrier_rw();
824 uint32_t waketime = nrf_grtc_waketime_get(p_reg);
825 nrf_barrier_r();
826 return waketime;
827 }
828 #endif // NRFY_GRTC_HAS_EXTENDED
829
830 #if NRFY_GRTC_HAS_PWM
831 /** @refhal{nrf_grtc_pwm_compare_set} */
nrfy_grtc_pwm_compare_set(NRF_GRTC_Type * p_reg,uint32_t value)832 NRFY_STATIC_INLINE void nrfy_grtc_pwm_compare_set(NRF_GRTC_Type * p_reg, uint32_t value)
833 {
834 nrf_grtc_pwm_compare_set(p_reg, value);
835 nrf_barrier_w();
836 }
837
838 /** @refhal{nrf_grtc_pwm_compare_get} */
nrfy_grtc_pwm_compare_get(NRF_GRTC_Type const * p_reg)839 NRFY_STATIC_INLINE uint32_t nrfy_grtc_pwm_compare_get(NRF_GRTC_Type const * p_reg)
840 {
841 nrf_barrier_rw();
842 uint32_t compare = nrf_grtc_pwm_compare_get(p_reg);
843 nrf_barrier_r();
844 return compare;
845 }
846 #endif // NRFY_GRTC_HAS_PWM
847
848 #if NRFY_GRTC_HAS_CLKOUT
849 /** @refhal{nrf_grtc_clkout_set} */
nrfy_grtc_clkout_set(NRF_GRTC_Type * p_reg,nrf_grtc_clkout_t clkout,bool enable)850 NRFY_STATIC_INLINE void nrfy_grtc_clkout_set(NRF_GRTC_Type * p_reg,
851 nrf_grtc_clkout_t clkout,
852 bool enable)
853 {
854 nrf_grtc_clkout_set(p_reg, clkout, enable);
855 nrf_barrier_w();
856 }
857
858 /** @refhal{nrf_grtc_clkout_enable_check} */
nrfy_grtc_clkout_enable_check(NRF_GRTC_Type const * p_reg,nrf_grtc_clkout_t clkout)859 NRFY_STATIC_INLINE bool nrfy_grtc_clkout_enable_check(NRF_GRTC_Type const * p_reg,
860 nrf_grtc_clkout_t clkout)
861 {
862 nrf_barrier_rw();
863 bool check = nrf_grtc_clkout_enable_check(p_reg, clkout);
864 nrf_barrier_r();
865 return check;
866 }
867
868 /** @refhal{nrf_grtc_clkout_divider_set} */
nrfy_grtc_clkout_divider_set(NRF_GRTC_Type * p_reg,uint32_t value)869 NRFY_STATIC_INLINE void nrfy_grtc_clkout_divider_set(NRF_GRTC_Type * p_reg, uint32_t value)
870 {
871 nrf_grtc_clkout_divider_set(p_reg, value);
872 nrf_barrier_w();
873 }
874
875 /** @refhal{nrf_grtc_clkout_divider_get} */
nrfy_grtc_clkout_divider_get(NRF_GRTC_Type const * p_reg)876 NRFY_STATIC_INLINE uint32_t nrfy_grtc_clkout_divider_get(NRF_GRTC_Type const * p_reg)
877 {
878 nrf_barrier_rw();
879 uint32_t divider = nrf_grtc_clkout_divider_get(p_reg);
880 nrf_barrier_r();
881 return divider;
882 }
883 #endif // NRFY_GRTC_HAS_CLKOUT
884
885 #if NRFY_GRTC_HAS_CLKSEL
886 /** @refhal{nrf_grtc_clksel_set} */
nrfy_grtc_clksel_set(NRF_GRTC_Type * p_reg,nrf_grtc_clksel_t clksel)887 NRFY_STATIC_INLINE void nrfy_grtc_clksel_set(NRF_GRTC_Type * p_reg, nrf_grtc_clksel_t clksel)
888 {
889 nrf_grtc_clksel_set(p_reg, clksel);
890 nrf_barrier_w();
891 }
892
893 /** @refhal{nrf_grtc_clksel_get} */
nrfy_grtc_clksel_get(NRF_GRTC_Type const * p_reg)894 NRFY_STATIC_INLINE nrf_grtc_clksel_t nrfy_grtc_clksel_get(NRF_GRTC_Type const * p_reg)
895 {
896 nrf_barrier_rw();
897 nrf_grtc_clksel_t clksel = nrf_grtc_clksel_get(p_reg);
898 nrf_barrier_r();
899 return clksel;
900 }
901 #endif // NRFY_GRTC_HAS_CLKSEL
902
903 /** @} */
904
__nrfy_internal_grtc_event_enabled_clear(NRF_GRTC_Type * p_reg,uint32_t mask,nrf_grtc_event_t event)905 NRFY_STATIC_INLINE void __nrfy_internal_grtc_event_enabled_clear(NRF_GRTC_Type * p_reg,
906 uint32_t mask,
907 nrf_grtc_event_t event)
908 {
909 if (mask & NRFY_EVENT_TO_INT_BITMASK(event))
910 {
911 nrf_grtc_event_clear(p_reg, event);
912 }
913 }
914
__nrfy_internal_grtc_event_handle(NRF_GRTC_Type * p_reg,uint32_t mask,nrf_grtc_event_t event,uint32_t * p_evt_mask)915 NRFY_STATIC_INLINE bool __nrfy_internal_grtc_event_handle(NRF_GRTC_Type * p_reg,
916 uint32_t mask,
917 nrf_grtc_event_t event,
918 uint32_t * p_evt_mask)
919 {
920 if ((mask & NRFY_EVENT_TO_INT_BITMASK(event)) && nrf_grtc_event_check(p_reg, event))
921 {
922 nrf_grtc_event_clear(p_reg, event);
923 if (p_evt_mask)
924 {
925 *p_evt_mask |= NRFY_EVENT_TO_INT_BITMASK(event);
926 }
927 return true;
928 }
929 return false;
930 }
931
__nrfy_internal_grtc_events_process(NRF_GRTC_Type * p_reg,uint32_t mask)932 NRFY_STATIC_INLINE uint32_t __nrfy_internal_grtc_events_process(NRF_GRTC_Type * p_reg,
933 uint32_t mask)
934 {
935 uint32_t event_mask = 0;
936 uint32_t channel_mask = NRF_GRTC_SYSCOUNTER_ALL_CHANNELS_INT_MASK & mask;
937
938 nrf_barrier_r();
939 while (channel_mask)
940 {
941 uint8_t cc_channel = (uint8_t)NRF_CTZ(channel_mask);
942 nrf_grtc_event_t event = nrf_grtc_sys_counter_compare_event_get(cc_channel);
943 (void)__nrfy_internal_grtc_event_handle(p_reg, mask, event, &event_mask);
944 channel_mask &= ~NRF_GRTC_CHANNEL_INT_MASK(cc_channel);
945 }
946 #if NRFY_GRTC_HAS_RTCOUNTER
947 (void)__nrfy_internal_grtc_event_handle(p_reg,
948 mask,
949 NRF_GRTC_EVENT_RTCOMPARE,
950 &event_mask);
951 (void)__nrfy_internal_grtc_event_handle(p_reg,
952 mask,
953 NRF_GRTC_EVENT_RTCOMPARESYNC,
954 &event_mask);
955 #endif // NRFY_GRTC_HAS_RTCOUNTER
956 return event_mask;
957 }
958
959 #if NRFY_GRTC_HAS_RTCOUNTER
__nrfy_internal_grtc_rt_counter_read(NRF_GRTC_Type const * p_reg)960 NRFY_STATIC_INLINE uint64_t __nrfy_internal_grtc_rt_counter_read(NRF_GRTC_Type const * p_reg)
961 {
962 uint32_t counter_l = nrf_grtc_rt_counter_low_get(p_reg);
963 uint32_t counter_h = nrf_grtc_rt_counter_high_get(p_reg);
964
965 nrf_barrier_r();
966 return (uint64_t)counter_l | ((uint64_t)counter_h << 32);
967 }
968 #endif // NRFY_GRTC_HAS_RTCOUNTER
969
__nrfy_internal_grtc_sys_counter_ready_check(NRF_GRTC_Type const * p_reg)970 NRFY_STATIC_INLINE bool __nrfy_internal_grtc_sys_counter_ready_check(NRF_GRTC_Type const * p_reg)
971 {
972 #if NRFY_GRTC_HAS_SYSCOUNTER_ARRAY
973 nrf_grtc_sys_counter_low_get(p_reg); // Dummy read, required.
974 nrf_barrier_r();
975 bool check = ((nrf_grtc_sys_counter_high_get(p_reg) & GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Msk)
976 >> GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Pos) == GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Ready;
977 nrf_barrier_r();
978 return check;
979 #else
980 bool check = nrf_grtc_event_check(p_reg, NRF_GRTC_EVENT_SYSCOUNTERVALID);
981 nrf_barrier_r();
982 return check;
983 #endif
984 }
985
986 #ifdef __cplusplus
987 }
988 #endif
989
990 #endif // NRFY_GRTC_H__
991
