1 /*
2 * Copyright (c) 2015 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_SPIS_H__
35 #define NRF_SPIS_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if defined(NRF54H20_XXAA) || defined(NRF92_SERIES)
44 #define NRF_SPIS_CLOCKPIN_MISO_NEEDED 1
45 #endif
46
47 #if defined(HALTIUM_XXAA)
48 #define NRF_SPIS_CLOCKPIN_SCK_NEEDED 1
49 #endif
50
51 /**
52 * @defgroup nrf_spis_hal SPIS HAL
53 * @{
54 * @ingroup nrf_spis
55 * @brief Hardware access layer for managing the SPIS peripheral.
56 */
57
58 #if defined(SPIS_DMA_TX_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
59 /** @brief Symbol indicating whether dedicated DMA register is present. */
60 #define NRF_SPIS_HAS_DMA_REG 1
61 #else
62 #define NRF_SPIS_HAS_DMA_REG 0
63 #endif
64
65 #if (defined(SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk) && \
66 defined(SPIS_EVENTS_DMA_RX_END_END_Msk)) || \
67 defined(__NRFX_DOXYGEN__)
68 /** @brief Symbol indicating whether SPIS DMA tasks and events are present. */
69 #define NRF_SPIS_HAS_DMA_TASKS_EVENTS 1
70 #else
71 #define NRF_SPIS_HAS_DMA_TASKS_EVENTS 0
72 #endif
73
74 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
75 /** @brief Maximum number of RX patterns. */
76 #define NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT SPIS_DMA_RX_MATCH_CANDIDATE_MaxCount
77 #endif
78
79 /**
80 * @brief Macro getting pointer to the structure of registers of the SPIS peripheral.
81 *
82 * @param[in] idx SPIS instance index.
83 *
84 * @return Pointer to the structure of registers of the SPIS peripheral.
85 */
86 #define NRF_SPIS_INST_GET(idx) NRFX_CONCAT(NRF_, SPIS, idx)
87
88 /**
89 * @brief This value can be used as a parameter for the @ref nrf_spis_pins_set
90 * function to specify that a given SPI signal (SCK, MOSI, or MISO)
91 * shall not be connected to a physical pin.
92 */
93 #define NRF_SPIS_PIN_NOT_CONNECTED 0xFFFFFFFF
94
95 /** @brief SPIS tasks. */
96 typedef enum
97 {
98 NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore.
99 NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it.
100 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
101 NRF_SPIS_TASK_ENABLERXMATCH0 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.ENABLEMATCH[0]), ///< Enable SPI pattern matching functionality for pattern 0.
102 NRF_SPIS_TASK_ENABLERXMATCH1 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.ENABLEMATCH[1]), ///< Enable SPI pattern matching functionality for pattern 1.
103 NRF_SPIS_TASK_ENABLERXMATCH2 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.ENABLEMATCH[2]), ///< Enable SPI pattern matching functionality for pattern 2.
104 NRF_SPIS_TASK_ENABLERXMATCH3 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.ENABLEMATCH[3]), ///< Enable SPI pattern matching functionality for pattern 3.
105 NRF_SPIS_TASK_DISABLERXMATCH0 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.DISABLEMATCH[0]), ///< Disable SPI pattern matching functionality for pattern 0.
106 NRF_SPIS_TASK_DISABLERXMATCH1 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.DISABLEMATCH[1]), ///< Disable SPI pattern matching functionality for pattern 1.
107 NRF_SPIS_TASK_DISABLERXMATCH2 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.DISABLEMATCH[2]), ///< Disable SPI pattern matching functionality for pattern 2.
108 NRF_SPIS_TASK_DISABLERXMATCH3 = offsetof(NRF_SPIS_Type, TASKS_DMA.RX.DISABLEMATCH[3]) ///< Disable SPI pattern matching functionality for pattern 3.
109 #endif
110 } nrf_spis_task_t;
111
112 /** @brief SPIS events. */
113 typedef enum
114 {
115 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
116 NRF_SPIS_EVENT_RXSTARTED = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.READY), ///< Receive sequence started.
117 NRF_SPIS_EVENT_RXBUSERROR = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.BUSERROR), ///< Memory bus error occurred during the RX transfer.
118 NRF_SPIS_EVENT_RXMATCH0 = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.MATCH[0]), ///< Pattern match for pattern 0 detected.
119 NRF_SPIS_EVENT_RXMATCH1 = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.MATCH[1]), ///< Pattern match for pattern 1 detected.
120 NRF_SPIS_EVENT_RXMATCH2 = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.MATCH[2]), ///< Pattern match for pattern 2 detected.
121 NRF_SPIS_EVENT_RXMATCH3 = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.MATCH[3]), ///< Pattern match for pattern 3 detected.
122 NRF_SPIS_EVENT_TXSTARTED = offsetof(NRF_SPIS_Type, EVENTS_DMA.TX.READY), ///< Transmit sequence started.
123 NRF_SPIS_EVENT_TXBUSERROR = offsetof(NRF_SPIS_Type, EVENTS_DMA.TX.BUSERROR), ///< Memory bus error occurred during the TX transfer.
124 NRF_SPIS_EVENT_ENDRX = offsetof(NRF_SPIS_Type, EVENTS_DMA.RX.END), ///< End of RXD buffer reached.
125 NRF_SPIS_EVENT_ENDTX = offsetof(NRF_SPIS_Type, EVENTS_DMA.TX.END), ///< End of TXD buffer reached.
126 #endif
127 NRF_SPIS_EVENT_END = offsetof(NRF_SPIS_Type, EVENTS_END), ///< Granted transaction completed.
128 NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired.
129 } nrf_spis_event_t;
130
131 /** @brief SPIS shortcuts. */
132 typedef enum
133 {
134 NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk, ///< Shortcut between END event and ACQUIRE task.
135 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
136 NRF_SPIS_SHORT_RXMATCH0_ENABLERXMATCH1_MASK = SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.ENABLEMATCH1 task.
137 NRF_SPIS_SHORT_RXMATCH1_ENABLERXMATCH2_MASK = SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.ENABLEMATCH2 task.
138 NRF_SPIS_SHORT_RXMATCH2_ENABLERXMATCH3_MASK = SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.ENABLEMATCH3 task.
139 NRF_SPIS_SHORT_RXMATCH3_ENABLERXMATCH0_MASK = SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.ENABLEMATCH0 task.
140 NRF_SPIS_SHORT_RXMATCH0_DISABLERXMATCH0_MASK = SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.DISABLEMATCH0 task.
141 NRF_SPIS_SHORT_RXMATCH1_DISABLERXMATCH1_MASK = SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.DISABLEMATCH1 task.
142 NRF_SPIS_SHORT_RXMATCH2_DISABLERXMATCH2_MASK = SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.DISABLEMATCH2 task.
143 NRF_SPIS_SHORT_RXMATCH3_DISABLERXMATCH3_MASK = SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.DISABLEMATCH3 task.
144 #endif
145 NRF_SPIS_ALL_SHORTS_MASK = NRF_SPIS_SHORT_END_ACQUIRE
146 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
147 | NRF_SPIS_SHORT_RXMATCH0_ENABLERXMATCH1_MASK
148 | NRF_SPIS_SHORT_RXMATCH1_ENABLERXMATCH2_MASK
149 | NRF_SPIS_SHORT_RXMATCH2_ENABLERXMATCH3_MASK
150 | NRF_SPIS_SHORT_RXMATCH3_ENABLERXMATCH0_MASK
151 | NRF_SPIS_SHORT_RXMATCH0_DISABLERXMATCH0_MASK
152 | NRF_SPIS_SHORT_RXMATCH1_DISABLERXMATCH1_MASK
153 | NRF_SPIS_SHORT_RXMATCH2_DISABLERXMATCH2_MASK
154 | NRF_SPIS_SHORT_RXMATCH3_DISABLERXMATCH3_MASK ///< All SPIS shortcuts.
155 #endif
156 } nrf_spis_short_mask_t;
157
158 /** @brief SPIS interrupts. */
159 typedef enum
160 {
161 NRF_SPIS_INT_END_MASK = SPIS_INTENSET_END_Msk, ///< Interrupt on END event.
162 NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk, ///< Interrupt on ACQUIRED event.
163 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
164 NRF_SPIS_INT_RXREADY_MASK = SPIS_INTENSET_DMARXREADY_Msk, ///< Interrupt on DMA.RX.READY event.
165 NRF_SPIS_INT_RXBUSERROR_MASK = SPIS_INTENSET_DMARXBUSERROR_Msk, ///< Interrupt on DMA.RX.BUSERROR event.
166 NRF_SPIS_INT_RXMATCH0_MASK = SPIS_INTENSET_DMARXMATCH0_Msk, ///< Interrupt on DMA.RX.MATCH0 event.
167 NRF_SPIS_INT_RXMATCH1_MASK = SPIS_INTENSET_DMARXMATCH1_Msk, ///< Interrupt on DMA.RX.MATCH1 event.
168 NRF_SPIS_INT_RXMATCH2_MASK = SPIS_INTENSET_DMARXMATCH2_Msk, ///< Interrupt on DMA.RX.MATCH2 event.
169 NRF_SPIS_INT_RXMATCH3_MASK = SPIS_INTENSET_DMARXMATCH3_Msk, ///< Interrupt on DMA.RX.MATCH3 event.
170 NRF_SPIS_INT_TXREADY_MASK = SPIS_INTENSET_DMATXREADY_Msk, ///< Interrupt on DMA.TX.READY event.
171 NRF_SPIS_INT_TXBUSERROR_MASK = SPIS_INTENSET_DMATXBUSERROR_Msk, ///< Interrupt on DMA.TX.BUSERROR event.
172 NRF_SPIS_INT_ENDRX_MASK = SPIS_INTENSET_DMARXEND_Msk, ///< Interrupt on ENDRX event.
173 NRF_SPIS_INT_ENDTX_MASK = SPIS_INTENSET_DMATXEND_Msk, ///< Interrupt on ENDTX event.
174 #endif
175 NRF_SPIS_ALL_INTS_MASK = NRF_SPIS_INT_END_MASK
176 | NRF_SPIS_INT_ACQUIRED_MASK
177 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
178 | NRF_SPIS_INT_RXREADY_MASK
179 | NRF_SPIS_INT_RXBUSERROR_MASK
180 | NRF_SPIS_INT_RXMATCH0_MASK
181 | NRF_SPIS_INT_RXMATCH1_MASK
182 | NRF_SPIS_INT_RXMATCH2_MASK
183 | NRF_SPIS_INT_RXMATCH3_MASK
184 | NRF_SPIS_INT_TXREADY_MASK
185 | NRF_SPIS_INT_TXBUSERROR_MASK
186 | NRF_SPIS_INT_ENDRX_MASK
187 | NRF_SPIS_INT_ENDTX_MASK ///< All SPIS interrupts.
188 #endif
189 } nrf_spis_int_mask_t;
190
191 /** @brief SPI modes. */
192 typedef enum
193 {
194 NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock.
195 NRF_SPIS_MODE_1, ///< SCK active high, sample on trailing edge of clock.
196 NRF_SPIS_MODE_2, ///< SCK active low, sample on leading edge of clock.
197 NRF_SPIS_MODE_3 ///< SCK active low, sample on trailing edge of clock.
198 } nrf_spis_mode_t;
199
200 /** @brief SPI bit orders. */
201 typedef enum
202 {
203 NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
204 NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
205 } nrf_spis_bit_order_t;
206
207 /** @brief SPI semaphore status. */
208 typedef enum
209 {
210 NRF_SPIS_SEMSTAT_FREE = 0, ///< Semaphore is free.
211 NRF_SPIS_SEMSTAT_CPU = 1, ///< Semaphore is assigned to the CPU.
212 NRF_SPIS_SEMSTAT_SPIS = 2, ///< Semaphore is assigned to the SPI slave.
213 NRF_SPIS_SEMSTAT_CPUPENDING = 3 ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending.
214 } nrf_spis_semstat_t;
215
216 /** @brief SPIS status. */
217 typedef enum
218 {
219 NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented.
220 NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk ///< RX buffer overflow detected and prevented.
221 } nrf_spis_status_mask_t;
222
223
224 /**
225 * @brief Function for activating the specified SPIS task.
226 *
227 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
228 * @param[in] task Task to be activated.
229 */
230 NRF_STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
231 nrf_spis_task_t task);
232
233 /**
234 * @brief Function for getting the address of the specified SPIS task register.
235 *
236 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
237 * @param[in] task The specified task.
238 *
239 * @return Address of the specified task register.
240 */
241 NRF_STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
242 nrf_spis_task_t task);
243
244 /**
245 * @brief Function for clearing the specified SPIS event.
246 *
247 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
248 * @param[in] event Event to be cleared.
249 */
250 NRF_STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
251 nrf_spis_event_t event);
252
253 /**
254 * @brief Function for retrieving the state of the SPIS event.
255 *
256 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
257 * @param[in] event Event to be checked.
258 *
259 * @retval true The event has been generated.
260 * @retval false The event has not been generated.
261 */
262 NRF_STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
263 nrf_spis_event_t event);
264
265 /**
266 * @brief Function for getting the address of the specified SPIS event register.
267 *
268 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
269 * @param[in] event The specified event.
270 *
271 * @return Address of the specified event register.
272 */
273 NRF_STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
274 nrf_spis_event_t event);
275
276 /**
277 * @brief Function for enabling the specified shortcuts.
278 *
279 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
280 * @param[in] mask Shortcuts to be enabled.
281 */
282 NRF_STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
283 uint32_t mask);
284
285 /**
286 * @brief Function for disabling the specified shortcuts.
287 *
288 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
289 * @param[in] mask Shortcuts to be disabled.
290 */
291 NRF_STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
292 uint32_t mask);
293
294 /**
295 * @brief Function for enabling the specified interrupts.
296 *
297 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
298 * @param[in] mask Mask of interrupts to be enabled.
299 * Use @ref nrf_spis_int_mask_t values for bit masking.
300 */
301 NRF_STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
302 uint32_t mask);
303
304 /**
305 * @brief Function for disabling the specified interrupts.
306 *
307 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
308 * @param[in] mask Mask of interrupts to be disabled.
309 * Use @ref nrf_spis_int_mask_t values for bit masking.
310 */
311 NRF_STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
312 uint32_t mask);
313
314 /**
315 * @brief Function for checking if the specified interrupts are enabled.
316 *
317 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
318 * @param[in] mask Mask of interrupts to be checked.
319 * Use @ref nrf_spis_int_mask_t values for bit masking.
320 *
321 * @return Mask of enabled interrupts.
322 */
323 NRF_STATIC_INLINE uint32_t nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg, uint32_t mask);
324
325 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
326 /**
327 * @brief Function for setting the subscribe configuration for a given
328 * SPIS task.
329 *
330 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
331 * @param[in] task Task for which to set the configuration.
332 * @param[in] channel Channel through which to subscribe events.
333 */
334 NRF_STATIC_INLINE void nrf_spis_subscribe_set(NRF_SPIS_Type * p_reg,
335 nrf_spis_task_t task,
336 uint8_t channel);
337
338 /**
339 * @brief Function for clearing the subscribe configuration for a given
340 * SPIS task.
341 *
342 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
343 * @param[in] task Task for which to clear the configuration.
344 */
345 NRF_STATIC_INLINE void nrf_spis_subscribe_clear(NRF_SPIS_Type * p_reg,
346 nrf_spis_task_t task);
347
348 /**
349 * @brief Function for setting the publish configuration for a given
350 * SPIS event.
351 *
352 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
353 * @param[in] event Event for which to set the configuration.
354 * @param[in] channel Channel through which to publish the event.
355 */
356 NRF_STATIC_INLINE void nrf_spis_publish_set(NRF_SPIS_Type * p_reg,
357 nrf_spis_event_t event,
358 uint8_t channel);
359
360 /**
361 * @brief Function for clearing the publish configuration for a given
362 * SPIS event.
363 *
364 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
365 * @param[in] event Event for which to clear the configuration.
366 */
367 NRF_STATIC_INLINE void nrf_spis_publish_clear(NRF_SPIS_Type * p_reg,
368 nrf_spis_event_t event);
369 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
370
371 /**
372 * @brief Function for enabling the SPIS peripheral.
373 *
374 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
375 */
376 NRF_STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg);
377
378 /**
379 * @brief Function for disabling the SPIS peripheral.
380 *
381 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
382 */
383 NRF_STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg);
384
385 /**
386 * @brief Function for checking if the SPIS peripheral is enabled.
387 *
388 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
389 *
390 * @retval true The SPIS is enabled.
391 * @retval false The SPIS is not enabled.
392 */
393 NRF_STATIC_INLINE bool nrf_spis_enable_check(NRF_SPIS_Type const * p_reg);
394
395 /**
396 * @brief Function for retrieving the SPIS semaphore status.
397 *
398 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
399 *
400 * @returns Current semaphore status.
401 */
402 NRF_STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type const * p_reg);
403
404 /**
405 * @brief Function for retrieving the SPIS status.
406 *
407 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
408 *
409 * @returns Current SPIS status.
410 */
411 NRF_STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type const * p_reg);
412
413 /**
414 * @brief Function for configuring SPIS pins.
415 *
416 * If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED
417 * value instead of its pin number.
418 *
419 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
420 * @param[in] sck_pin SCK pin number.
421 * @param[in] mosi_pin MOSI pin number.
422 * @param[in] miso_pin MISO pin number.
423 * @param[in] csn_pin CSN pin number.
424 */
425 NRF_STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
426 uint32_t sck_pin,
427 uint32_t mosi_pin,
428 uint32_t miso_pin,
429 uint32_t csn_pin);
430
431 /**
432 * @brief Function for setting the SCK pin.
433 *
434 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
435 * @param[in] pin SCK pin number.
436 */
437 NRF_STATIC_INLINE void nrf_spis_sck_pin_set(NRF_SPIS_Type * p_reg, uint32_t pin);
438
439 /**
440 * @brief Function for setting the MOSI pin
441 *
442 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
443 * @param[in] pin MOSI pin number.
444 */
445 NRF_STATIC_INLINE void nrf_spis_mosi_pin_set(NRF_SPIS_Type * p_reg, uint32_t pin);
446
447 /**
448 * @brief Function for setting the MISO pin.
449 *
450 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
451 * @param[in] pin MISO pin number.
452 */
453 NRF_STATIC_INLINE void nrf_spis_miso_pin_set(NRF_SPIS_Type * p_reg, uint32_t pin);
454
455 /**
456 * @brief Function for setting the CSN pin.
457 *
458 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
459 * @param[in] pin CSN pin number.
460 */
461 NRF_STATIC_INLINE void nrf_spis_csn_pin_set(NRF_SPIS_Type * p_reg, uint32_t pin);
462
463 /**
464 * @brief Function for getting the SCK pin selection.
465 *
466 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
467 *
468 * @return SCK pin selection.
469 */
470 NRF_STATIC_INLINE uint32_t nrf_spis_sck_pin_get(NRF_SPIS_Type const * p_reg);
471
472 /**
473 * @brief Function for getting the MOSI pin selection.
474 *
475 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
476 *
477 * @return MOSI pin selection.
478 */
479 NRF_STATIC_INLINE uint32_t nrf_spis_mosi_pin_get(NRF_SPIS_Type const * p_reg);
480
481 /**
482 * @brief Function for getting the MISO pin selection.
483 *
484 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
485 *
486 * @return MISO pin selection.
487 */
488 NRF_STATIC_INLINE uint32_t nrf_spis_miso_pin_get(NRF_SPIS_Type const * p_reg);
489
490 /**
491 * @brief Function for getting the CSN pin selection.
492 *
493 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
494 *
495 * @return CSN pin selection.
496 */
497 NRF_STATIC_INLINE uint32_t nrf_spis_csn_pin_get(NRF_SPIS_Type const * p_reg);
498
499 /**
500 * @brief Function for setting the transmit buffer.
501 *
502 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
503 * @param[in] p_buffer Pointer to the buffer that contains the data to send.
504 * @param[in] length Maximum number of data bytes to transmit.
505 */
506 NRF_STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
507 uint8_t const * p_buffer,
508 size_t length);
509
510 /**
511 * @brief Function for setting the receive buffer.
512 *
513 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
514 * @param[in] p_buffer Pointer to the buffer for received data.
515 * @param[in] length Maximum number of data bytes to receive.
516 */
517 NRF_STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
518 uint8_t * p_buffer,
519 size_t length);
520
521 /**
522 * @brief Function for getting the number of bytes transmitted
523 * in the last granted transaction.
524 *
525 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
526 *
527 * @returns Number of bytes transmitted.
528 */
529 NRF_STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg);
530
531 /**
532 * @brief Function for getting the number of bytes received
533 * in the last granted transaction.
534 *
535 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
536 *
537 * @returns Number of bytes received.
538 */
539 NRF_STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg);
540
541 /**
542 * @brief Function for setting the SPI configuration.
543 *
544 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
545 * @param[in] spi_mode SPI mode.
546 * @param[in] spi_bit_order SPI bit order.
547 */
548 NRF_STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
549 nrf_spis_mode_t spi_mode,
550 nrf_spis_bit_order_t spi_bit_order);
551
552 /**
553 * @brief Function for setting the default character.
554 *
555 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
556 * @param[in] def Default character that is clocked out in case of
557 * an overflow of the RXD buffer.
558 */
559 NRF_STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
560 uint8_t def);
561
562 /**
563 * @brief Function for setting the over-read character.
564 *
565 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
566 * @param[in] orc Over-read character that is clocked out in case of
567 * an over-read of the TXD buffer.
568 */
569 NRF_STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
570 uint8_t orc);
571
572 #if defined(SPIS_TXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__)
573 /**
574 * @brief Function for enabling the TX list feature.
575 *
576 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
577 */
578 NRF_STATIC_INLINE void nrf_spis_tx_list_enable(NRF_SPIS_Type * p_reg);
579
580 /**
581 * @brief Function for disabling the TX list feature.
582 *
583 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
584 */
585 NRF_STATIC_INLINE void nrf_spis_tx_list_disable(NRF_SPIS_Type * p_reg);
586 #endif // defined(SPIS_TXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__)
587
588 #if defined(SPIS_RXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__)
589 /**
590 * @brief Function for enabling the RX list feature.
591 *
592 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
593 */
594 NRF_STATIC_INLINE void nrf_spis_rx_list_enable(NRF_SPIS_Type * p_reg);
595
596 /**
597 * @brief Function for disabling the RX list feature.
598 *
599 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
600 */
601 NRF_STATIC_INLINE void nrf_spis_rx_list_disable(NRF_SPIS_Type * p_reg);
602 #endif // defined(SPIS_RXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__)
603
604 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
605 /**
606 * @brief Function for enabling individual pattern match filters.
607 *
608 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
609 * @param[in] index Index of pattern match filter.
610 * @param[in] enable True if pattern match filter is to be enabled, false otherwise.
611 */
612 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_enable_set(NRF_SPIS_Type * p_reg,
613 uint8_t index,
614 bool enable);
615
616 /**
617 * @brief Function for checking if the specified pattern match filter is enabled.
618 *
619 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
620 * @param[in] index Index of pattern match filter.
621 *
622 * @retval true Pattern match filter is enabled.
623 * @retval false Pattern match filter is disabled.
624 */
625 NRF_STATIC_INLINE bool nrf_spis_rx_pattern_match_enable_check(NRF_SPIS_Type const * p_reg,
626 uint8_t index);
627
628 /**
629 * @brief Function for enabling one-shot operation for the specified match filter.
630 *
631 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
632 * @param[in] index Index of pattern match filter.
633 */
634 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_one_shot_enable(NRF_SPIS_Type * p_reg,
635 uint8_t index);
636
637 /**
638 * @brief Function for disabling one-shot operation for the specified match filter.
639 *
640 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
641 * @param[in] index Index of pattern match filter.
642 */
643 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_one_shot_disable(NRF_SPIS_Type * p_reg,
644 uint8_t index);
645
646 /**
647 * @brief Function for checking if specified pattern match filter is configured as one-shot.
648 *
649 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
650 * @param[in] index Index of pattern match filter.
651 *
652 * @retval true Pattern match filter is configured as one-shot.
653 * @retval false Pattern match filter is configured as continuous.
654 */
655 NRF_STATIC_INLINE bool nrf_spis_rx_pattern_match_one_shot_check(NRF_SPIS_Type const * p_reg,
656 uint8_t index);
657
658 /**
659 * @brief Function for setting the pattern to be looked for by the specified match filter.
660 *
661 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
662 * @param[in] index Index of pattern match filter.
663 * @param[in] pattern Pattern to be looked for.
664 * Match will trigger the corresponding event, if enabled.
665 */
666 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_candidate_set(NRF_SPIS_Type * p_reg,
667 uint8_t index,
668 uint32_t pattern);
669
670 /**
671 * @brief Function for getting the pattern that the specified match filter is looking for.
672 *
673 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
674 * @param[in] index Index of pattern match filter.
675 *
676 * @return Pattern that the specified match filter is looking for.
677 */
678 NRF_STATIC_INLINE uint32_t nrf_spis_rx_pattern_match_candidate_get(NRF_SPIS_Type const * p_reg,
679 uint8_t index);
680 #endif // NRF_SPIS_HAS_DMA_TASKS_EVENTS
681
682 #if NRF_SPIS_HAS_DMA_REG
683 /**
684 * @brief Function for enabling the termination of the RX transaction after detecting the BUSERROR event.
685 *
686 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
687 */
688 NRF_STATIC_INLINE void nrf_spis_rx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg);
689
690 /**
691 * @brief Function for disabling the termination of the RX transaction after detecting the BUSERROR event.
692 *
693 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
694 */
695 NRF_STATIC_INLINE void nrf_spis_rx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg);
696
697 /**
698 * @brief Function for checking if RX transaction termination after detecting the BUSERROR event is enabled.
699 *
700 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
701 *
702 * @retval true RX transaction termination after detecting a BUSERROR event is enabled.
703 * @retval false RX transaction termination after detecting a BUSERROR event is disabled.
704 */
705 NRF_STATIC_INLINE bool nrf_spis_rx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg);
706
707 /**
708 * @brief Function for enabling the termination of the TX transaction after detecting the BUSERROR event.
709 *
710 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
711 */
712 NRF_STATIC_INLINE void nrf_spis_tx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg);
713
714 /**
715 * @brief Function for disabling the termination of the TX transaction after detecting the BUSERROR event.
716 *
717 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
718 */
719 NRF_STATIC_INLINE void nrf_spis_tx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg);
720
721 /**
722 * @brief Function for checking if TX transaction termination after detecting the BUSERROR event is enabled.
723 *
724 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
725 *
726 * @retval true TX transaction termination after detecting a BUSERROR event is enabled.
727 * @retval false TX transaction termination after detecting a BUSERROR event is disabled.
728 */
729 NRF_STATIC_INLINE bool nrf_spis_tx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg);
730 #endif // NRF_SPIS_HAS_DMA_REG
731
732 #ifndef NRF_DECLARE_ONLY
733
nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,nrf_spis_task_t task)734 NRF_STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
735 nrf_spis_task_t task)
736 {
737 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
738 }
739
nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,nrf_spis_task_t task)740 NRF_STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
741 nrf_spis_task_t task)
742 {
743 return (uint32_t)p_reg + (uint32_t)task;
744 }
745
nrf_spis_event_clear(NRF_SPIS_Type * p_reg,nrf_spis_event_t event)746 NRF_STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
747 nrf_spis_event_t event)
748 {
749 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
750 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
751 }
752
nrf_spis_event_check(NRF_SPIS_Type const * p_reg,nrf_spis_event_t event)753 NRF_STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
754 nrf_spis_event_t event)
755 {
756 return nrf_event_check(p_reg, event);
757 }
758
nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,nrf_spis_event_t event)759 NRF_STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
760 nrf_spis_event_t event)
761 {
762 return (uint32_t)p_reg + (uint32_t)event;
763 }
764
nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,uint32_t mask)765 NRF_STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
766 uint32_t mask)
767 {
768 p_reg->SHORTS |= mask;
769 }
770
nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,uint32_t mask)771 NRF_STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
772 uint32_t mask)
773 {
774 p_reg->SHORTS &= ~(mask);
775 }
776
nrf_spis_int_enable(NRF_SPIS_Type * p_reg,uint32_t mask)777 NRF_STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
778 uint32_t mask)
779 {
780 p_reg->INTENSET = mask;
781 }
782
nrf_spis_int_disable(NRF_SPIS_Type * p_reg,uint32_t mask)783 NRF_STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
784 uint32_t mask)
785 {
786 p_reg->INTENCLR = mask;
787 }
788
nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg,uint32_t mask)789 NRF_STATIC_INLINE uint32_t nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg, uint32_t mask)
790 {
791 return p_reg->INTENSET & mask;
792 }
793
794 #if defined(DPPI_PRESENT)
nrf_spis_subscribe_set(NRF_SPIS_Type * p_reg,nrf_spis_task_t task,uint8_t channel)795 NRF_STATIC_INLINE void nrf_spis_subscribe_set(NRF_SPIS_Type * p_reg,
796 nrf_spis_task_t task,
797 uint8_t channel)
798 {
799 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
800 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
801 }
802
nrf_spis_subscribe_clear(NRF_SPIS_Type * p_reg,nrf_spis_task_t task)803 NRF_STATIC_INLINE void nrf_spis_subscribe_clear(NRF_SPIS_Type * p_reg,
804 nrf_spis_task_t task)
805 {
806 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
807 }
808
nrf_spis_publish_set(NRF_SPIS_Type * p_reg,nrf_spis_event_t event,uint8_t channel)809 NRF_STATIC_INLINE void nrf_spis_publish_set(NRF_SPIS_Type * p_reg,
810 nrf_spis_event_t event,
811 uint8_t channel)
812 {
813 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
814 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
815 }
816
nrf_spis_publish_clear(NRF_SPIS_Type * p_reg,nrf_spis_event_t event)817 NRF_STATIC_INLINE void nrf_spis_publish_clear(NRF_SPIS_Type * p_reg,
818 nrf_spis_event_t event)
819 {
820 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
821 }
822 #endif // defined(DPPI_PRESENT)
823
nrf_spis_enable(NRF_SPIS_Type * p_reg)824 NRF_STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg)
825 {
826 p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
827 }
828
nrf_spis_disable(NRF_SPIS_Type * p_reg)829 NRF_STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg)
830 {
831 p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
832 }
833
nrf_spis_enable_check(NRF_SPIS_Type const * p_reg)834 NRF_STATIC_INLINE bool nrf_spis_enable_check(NRF_SPIS_Type const * p_reg)
835 {
836 return p_reg->ENABLE == SPIS_ENABLE_ENABLE_Enabled;
837 }
838
nrf_spis_semaphore_status_get(NRF_SPIS_Type const * p_reg)839 NRF_STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type const * p_reg)
840 {
841 return (nrf_spis_semstat_t) ((p_reg->SEMSTAT & SPIS_SEMSTAT_SEMSTAT_Msk)
842 >> SPIS_SEMSTAT_SEMSTAT_Pos);
843 }
844
nrf_spis_status_get(NRF_SPIS_Type const * p_reg)845 NRF_STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type const * p_reg)
846 {
847 return (nrf_spis_status_mask_t) p_reg->STATUS;
848 }
849
nrf_spis_pins_set(NRF_SPIS_Type * p_reg,uint32_t sck_pin,uint32_t mosi_pin,uint32_t miso_pin,uint32_t csn_pin)850 NRF_STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
851 uint32_t sck_pin,
852 uint32_t mosi_pin,
853 uint32_t miso_pin,
854 uint32_t csn_pin)
855 {
856 #if defined (NRF51)
857 p_reg->PSELSCK = sck_pin;
858 p_reg->PSELMOSI = mosi_pin;
859 p_reg->PSELMISO = miso_pin;
860 p_reg->PSELCSN = csn_pin;
861 #else
862 p_reg->PSEL.SCK = sck_pin;
863 p_reg->PSEL.MOSI = mosi_pin;
864 p_reg->PSEL.MISO = miso_pin;
865 p_reg->PSEL.CSN = csn_pin;
866 #endif
867 }
868
nrf_spis_sck_pin_set(NRF_SPIS_Type * p_reg,uint32_t pin)869 NRF_STATIC_INLINE void nrf_spis_sck_pin_set(NRF_SPIS_Type * p_reg, uint32_t pin)
870 {
871 #if defined (NRF51)
872 p_reg->PSELSCK = pin;
873 #else
874 p_reg->PSEL.SCK = pin;
875 #endif
876 }
877
nrf_spis_mosi_pin_set(NRF_SPIS_Type * p_reg,uint32_t pin)878 NRF_STATIC_INLINE void nrf_spis_mosi_pin_set(NRF_SPIS_Type * p_reg, uint32_t pin)
879 {
880 #if defined (NRF51)
881 p_reg->PSELMOSI = pin;
882 #else
883 p_reg->PSEL.MOSI = pin;
884 #endif
885 }
886
nrf_spis_miso_pin_set(NRF_SPIS_Type * p_reg,uint32_t pin)887 NRF_STATIC_INLINE void nrf_spis_miso_pin_set(NRF_SPIS_Type * p_reg, uint32_t pin)
888 {
889 #if defined (NRF51)
890 p_reg->PSELMISO = pin;
891 #else
892 p_reg->PSEL.MISO = pin;
893 #endif
894 }
895
nrf_spis_csn_pin_set(NRF_SPIS_Type * p_reg,uint32_t pin)896 NRF_STATIC_INLINE void nrf_spis_csn_pin_set(NRF_SPIS_Type * p_reg, uint32_t pin)
897 {
898 #if defined (NRF51)
899 p_reg->PSELCSN = pin;
900 #else
901 p_reg->PSEL.CSN = pin;
902 #endif
903 }
904
nrf_spis_sck_pin_get(NRF_SPIS_Type const * p_reg)905 NRF_STATIC_INLINE uint32_t nrf_spis_sck_pin_get(NRF_SPIS_Type const * p_reg)
906 {
907 #if defined (NRF51)
908 return p_reg->PSELSCK;
909 #else
910 return p_reg->PSEL.SCK;
911 #endif
912 }
913
nrf_spis_mosi_pin_get(NRF_SPIS_Type const * p_reg)914 NRF_STATIC_INLINE uint32_t nrf_spis_mosi_pin_get(NRF_SPIS_Type const * p_reg)
915 {
916 #if defined (NRF51)
917 return p_reg->PSELMOSI;
918 #else
919 return p_reg->PSEL.MOSI;
920 #endif
921 }
922
nrf_spis_miso_pin_get(NRF_SPIS_Type const * p_reg)923 NRF_STATIC_INLINE uint32_t nrf_spis_miso_pin_get(NRF_SPIS_Type const * p_reg)
924 {
925 #if defined (NRF51)
926 return p_reg->PSELMISO;
927 #else
928 return p_reg->PSEL.MISO;
929 #endif
930 }
931
nrf_spis_csn_pin_get(NRF_SPIS_Type const * p_reg)932 NRF_STATIC_INLINE uint32_t nrf_spis_csn_pin_get(NRF_SPIS_Type const * p_reg)
933 {
934 #if defined (NRF51)
935 return p_reg->PSELCSN;
936 #else
937 return p_reg->PSEL.CSN;
938 #endif
939 }
940
nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,uint8_t const * p_buffer,size_t length)941 NRF_STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
942 uint8_t const * p_buffer,
943 size_t length)
944 {
945 #if defined (NRF51)
946 p_reg->TXDPTR = (uint32_t)p_buffer;
947 p_reg->MAXTX = length;
948 #elif NRF_SPIS_HAS_DMA_REG
949 p_reg->DMA.TX.PTR = (uint32_t)p_buffer;
950 p_reg->DMA.TX.MAXCNT = length;
951 #else
952 p_reg->TXD.PTR = (uint32_t)p_buffer;
953 p_reg->TXD.MAXCNT = length;
954 #endif
955 }
956
nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,uint8_t * p_buffer,size_t length)957 NRF_STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
958 uint8_t * p_buffer,
959 size_t length)
960 {
961 #if defined (NRF51)
962 p_reg->RXDPTR = (uint32_t)p_buffer;
963 p_reg->MAXRX = length;
964 #elif NRF_SPIS_HAS_DMA_REG
965 p_reg->DMA.RX.PTR = (uint32_t)p_buffer;
966 p_reg->DMA.RX.MAXCNT = length;
967 #else
968 p_reg->RXD.PTR = (uint32_t)p_buffer;
969 p_reg->RXD.MAXCNT = length;
970 #endif
971 }
972
nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg)973 NRF_STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg)
974 {
975 #if defined (NRF51)
976 return p_reg->AMOUNTTX;
977 #elif NRF_SPIS_HAS_DMA_REG
978 return p_reg->DMA.TX.AMOUNT;
979 #else
980 return p_reg->TXD.AMOUNT;
981 #endif
982 }
983
nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg)984 NRF_STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg)
985 {
986 #if defined (NRF51)
987 return p_reg->AMOUNTRX;
988 #elif NRF_SPIS_HAS_DMA_REG
989 return p_reg->DMA.RX.AMOUNT;
990 #else
991 return p_reg->RXD.AMOUNT;
992 #endif
993 }
994
nrf_spis_configure(NRF_SPIS_Type * p_reg,nrf_spis_mode_t spi_mode,nrf_spis_bit_order_t spi_bit_order)995 NRF_STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
996 nrf_spis_mode_t spi_mode,
997 nrf_spis_bit_order_t spi_bit_order)
998 {
999 uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ?
1000 SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst);
1001
1002 switch (spi_mode)
1003 {
1004 default:
1005 case NRF_SPIS_MODE_0:
1006 config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
1007 (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos);
1008 break;
1009
1010 case NRF_SPIS_MODE_1:
1011 config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
1012 (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos);
1013 break;
1014
1015 case NRF_SPIS_MODE_2:
1016 config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) |
1017 (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos);
1018 break;
1019
1020 case NRF_SPIS_MODE_3:
1021 config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) |
1022 (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos);
1023 break;
1024 }
1025 p_reg->CONFIG = config;
1026 }
1027
nrf_spis_orc_set(NRF_SPIS_Type * p_reg,uint8_t orc)1028 NRF_STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
1029 uint8_t orc)
1030 {
1031 p_reg->ORC = orc;
1032 }
1033
nrf_spis_def_set(NRF_SPIS_Type * p_reg,uint8_t def)1034 NRF_STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
1035 uint8_t def)
1036 {
1037 p_reg->DEF = def;
1038 }
1039
1040 #if defined(SPIS_TXD_LIST_LIST_Msk)
nrf_spis_tx_list_enable(NRF_SPIS_Type * p_reg)1041 NRF_STATIC_INLINE void nrf_spis_tx_list_enable(NRF_SPIS_Type * p_reg)
1042 {
1043 p_reg->TXD.LIST = SPIS_TXD_LIST_LIST_ArrayList << SPIS_TXD_LIST_LIST_Pos;
1044 }
1045
nrf_spis_tx_list_disable(NRF_SPIS_Type * p_reg)1046 NRF_STATIC_INLINE void nrf_spis_tx_list_disable(NRF_SPIS_Type * p_reg)
1047 {
1048 p_reg->TXD.LIST = SPIS_TXD_LIST_LIST_Disabled << SPIS_TXD_LIST_LIST_Pos;
1049 }
1050 #endif // defined(SPIS_TXD_LIST_LIST_Msk)
1051
1052 #if defined(SPIS_RXD_LIST_LIST_Msk)
nrf_spis_rx_list_enable(NRF_SPIS_Type * p_reg)1053 NRF_STATIC_INLINE void nrf_spis_rx_list_enable(NRF_SPIS_Type * p_reg)
1054 {
1055 p_reg->RXD.LIST = SPIS_RXD_LIST_LIST_ArrayList << SPIS_RXD_LIST_LIST_Pos;
1056 }
1057
nrf_spis_rx_list_disable(NRF_SPIS_Type * p_reg)1058 NRF_STATIC_INLINE void nrf_spis_rx_list_disable(NRF_SPIS_Type * p_reg)
1059 {
1060 p_reg->RXD.LIST = SPIS_RXD_LIST_LIST_Disabled << SPIS_RXD_LIST_LIST_Pos;
1061 }
1062 #endif // defined(SPIS_RXD_LIST_LIST_Msk)
1063
1064 #if NRF_SPIS_HAS_DMA_TASKS_EVENTS
nrf_spis_rx_pattern_match_enable_set(NRF_SPIS_Type * p_reg,uint8_t index,bool enable)1065 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_enable_set(NRF_SPIS_Type * p_reg,
1066 uint8_t index,
1067 bool enable)
1068 {
1069 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1070 switch (index)
1071 {
1072 case 0:
1073 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1074 ~SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Msk) |
1075 ((enable ?
1076 SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled :
1077 SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled)
1078 << SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos));
1079 break;
1080 case 1:
1081 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1082 ~SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Msk) |
1083 ((enable ?
1084 SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled :
1085 SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled)
1086 << SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos));
1087 break;
1088 case 2:
1089 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1090 ~SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Msk) |
1091 ((enable ?
1092 SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled :
1093 SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled)
1094 << SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos));
1095 break;
1096 case 3:
1097 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1098 ~SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Msk) |
1099 ((enable ?
1100 SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled :
1101 SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled)
1102 << SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos));
1103 break;
1104 default:
1105 NRFX_ASSERT(false);
1106 break;
1107 }
1108 }
1109
nrf_spis_rx_pattern_match_enable_check(NRF_SPIS_Type const * p_reg,uint8_t index)1110 NRF_STATIC_INLINE bool nrf_spis_rx_pattern_match_enable_check(NRF_SPIS_Type const * p_reg,
1111 uint8_t index)
1112 {
1113 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1114 switch (index)
1115 {
1116 case 0:
1117 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Msk)
1118 >> SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) ==
1119 SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled;
1120 case 1:
1121 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Msk)
1122 >> SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) ==
1123 SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled;
1124 case 2:
1125 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Msk)
1126 >> SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) ==
1127 SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled;
1128 case 3:
1129 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Msk)
1130 >> SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) ==
1131 SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled;
1132 default:
1133 NRFX_ASSERT(false);
1134 return 0;
1135 }
1136 }
1137
nrf_spis_rx_pattern_match_one_shot_enable(NRF_SPIS_Type * p_reg,uint8_t index)1138 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_one_shot_enable(NRF_SPIS_Type * p_reg,
1139 uint8_t index)
1140 {
1141 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1142 switch (index)
1143 {
1144 case 0:
1145 p_reg->DMA.RX.MATCH.CONFIG |= SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk;
1146 break;
1147 case 1:
1148 p_reg->DMA.RX.MATCH.CONFIG |= SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk;
1149 break;
1150 case 2:
1151 p_reg->DMA.RX.MATCH.CONFIG |= SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk;
1152 break;
1153 case 3:
1154 p_reg->DMA.RX.MATCH.CONFIG |= SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk;
1155 break;
1156 default:
1157 NRFX_ASSERT(false);
1158 break;
1159 }
1160 }
1161
nrf_spis_rx_pattern_match_one_shot_disable(NRF_SPIS_Type * p_reg,uint8_t index)1162 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_one_shot_disable(NRF_SPIS_Type * p_reg,
1163 uint8_t index)
1164 {
1165 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1166 switch (index)
1167 {
1168 case 0:
1169 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk);
1170 break;
1171 case 1:
1172 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk);
1173 break;
1174 case 2:
1175 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk);
1176 break;
1177 case 3:
1178 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk);
1179 break;
1180 default:
1181 NRFX_ASSERT(false);
1182 break;
1183 }
1184 }
1185
nrf_spis_rx_pattern_match_one_shot_check(NRF_SPIS_Type const * p_reg,uint8_t index)1186 NRF_STATIC_INLINE bool nrf_spis_rx_pattern_match_one_shot_check(NRF_SPIS_Type const * p_reg,
1187 uint8_t index)
1188 {
1189 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1190 switch (index)
1191 {
1192 case 0:
1193 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk)
1194 >> SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) ==
1195 SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot;
1196 case 1:
1197 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk)
1198 >> SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) ==
1199 SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot;
1200 case 2:
1201 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk)
1202 >> SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) ==
1203 SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot;
1204 case 3:
1205 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk)
1206 >> SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) ==
1207 SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot;
1208 default:
1209 NRFX_ASSERT(false);
1210 return 0;
1211 }
1212 }
1213
nrf_spis_rx_pattern_match_candidate_set(NRF_SPIS_Type * p_reg,uint8_t index,uint32_t pattern)1214 NRF_STATIC_INLINE void nrf_spis_rx_pattern_match_candidate_set(NRF_SPIS_Type * p_reg,
1215 uint8_t index,
1216 uint32_t pattern)
1217 {
1218 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1219 p_reg->DMA.RX.MATCH.CANDIDATE[index] = pattern;
1220 }
1221
nrf_spis_rx_pattern_match_candidate_get(NRF_SPIS_Type const * p_reg,uint8_t index)1222 NRF_STATIC_INLINE uint32_t nrf_spis_rx_pattern_match_candidate_get(NRF_SPIS_Type const * p_reg,
1223 uint8_t index)
1224 {
1225 NRFX_ASSERT(index < NRF_SPIS_DMA_RX_PATTERN_MAX_COUNT);
1226 return p_reg->DMA.RX.MATCH.CANDIDATE[index];
1227 }
1228 #endif // NRF_SPIS_HAS_DMA_TASKS_EVENTS
1229
1230 #if NRF_SPIS_HAS_DMA_REG
nrf_spis_rx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg)1231 NRF_STATIC_INLINE void nrf_spis_rx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg)
1232 {
1233 p_reg->DMA.RX.TERMINATEONBUSERROR |= SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk;
1234 }
1235
nrf_spis_rx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg)1236 NRF_STATIC_INLINE void nrf_spis_rx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg)
1237 {
1238 p_reg->DMA.RX.TERMINATEONBUSERROR &= ~(SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk);
1239 }
1240
nrf_spis_rx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg)1241 NRF_STATIC_INLINE bool nrf_spis_rx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg)
1242 {
1243 return ((p_reg->DMA.RX.TERMINATEONBUSERROR & SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk)
1244 >> SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1245 SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled;
1246 }
1247
nrf_spis_tx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg)1248 NRF_STATIC_INLINE void nrf_spis_tx_terminate_on_bus_error_enable(NRF_SPIS_Type * p_reg)
1249 {
1250 p_reg->DMA.TX.TERMINATEONBUSERROR |= SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk;
1251 }
1252
nrf_spis_tx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg)1253 NRF_STATIC_INLINE void nrf_spis_tx_terminate_on_bus_error_disable(NRF_SPIS_Type * p_reg)
1254 {
1255 p_reg->DMA.TX.TERMINATEONBUSERROR &= ~(SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk);
1256 }
1257
nrf_spis_tx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg)1258 NRF_STATIC_INLINE bool nrf_spis_tx_terminate_on_bus_error_check(NRF_SPIS_Type const * p_reg)
1259 {
1260 return ((p_reg->DMA.TX.TERMINATEONBUSERROR & SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk)
1261 >> SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1262 SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled;
1263 }
1264 #endif // NRF_SPIS_HAS_DMA_REG
1265
1266 #endif // NRF_DECLARE_ONLY
1267
1268 /** @} */
1269
1270 #ifdef __cplusplus
1271 }
1272 #endif
1273
1274 #endif // NRF_SPIS_H__
1275
