1 /*
2 * Copyright (c) 2016 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_QSPI_H__
35 #define NRF_QSPI_H__
36
37 #include <nrfx.h>
38 #include <nrf_erratas.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /**
45 * @defgroup nrf_qspi_hal QSPI HAL
46 * @{
47 * @ingroup nrf_qspi
48 * @brief Hardware access layer for managing the QSPI peripheral.
49 */
50
51 #if defined(QSPI_XIPEN_XIPEN_Msk) || defined(__NRFX_DOXYGEN__)
52 /** @brief Symbol indicating whether XIP can be explicitly enabled or disabled via XIPEN register. */
53 #define NRF_QSPI_HAS_XIPEN 1
54 #else
55 #define NRF_QSPI_HAS_XIPEN 0
56 #endif
57
58 #if defined(QSPI_XIP_ENC_ENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__)
59 /** @brief Symbol indicating whether encryption for XIP is present. */
60 #define NRF_QSPI_HAS_XIP_ENC 1
61 #else
62 #define NRF_QSPI_HAS_XIP_ENC 0
63 #endif
64
65 #if defined(QSPI_DMA_ENC_ENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__)
66 /** @brief Symbol indicating whether encryption for EasyDMA is present. */
67 #define NRF_QSPI_HAS_DMA_ENC 1
68 #else
69 #define NRF_QSPI_HAS_DMA_ENC 0
70 #endif
71
72 #if defined(QSPI_IFCONFIG1_SPIMODE_MODE3) || defined(__NRFX_DOXYGEN__)
73 /** @brief Symbol indicating whether support for QSPI mode 1 is present. */
74 #define NRF_QSPI_HAS_MODE_1 1
75 #else
76 #define NRF_QSPI_HAS_MODE_1 0
77 #endif
78
79 #if defined(NRF53_SERIES) || defined(__NRFX_DOXYGEN__)
80 /** @brief Value representing QSPI base clock frequency. */
81 #define NRF_QSPI_BASE_CLOCK_FREQ 96000000uL
82 #else
83 #define NRF_QSPI_BASE_CLOCK_FREQ 32000000uL
84 #endif
85
86 /**
87 * @brief This value can be used as a parameter for the @ref nrf_qspi_pins_set
88 * function to specify that a given QSPI signal (SCK, CSN, IO0, IO1, IO2, or IO3)
89 * will not be connected to a physical pin.
90 */
91 #define NRF_QSPI_PIN_NOT_CONNECTED 0xFF
92
93 /** @brief Macro for setting proper values to pin registers. */
94 #define NRF_QSPI_PIN_VAL(pin) (pin) == NRF_QSPI_PIN_NOT_CONNECTED ? 0xFFFFFFFF : (pin)
95
96
97 /** @brief QSPI tasks. */
98 typedef enum
99 {
100 NRF_QSPI_TASK_ACTIVATE = offsetof(NRF_QSPI_Type, TASKS_ACTIVATE), /**< Activate the QSPI interface. */
101 NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART), /**< Start transfer from external flash memory to internal RAM. */
102 NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART), /**< Start transfer from internal RAM to external flash memory. */
103 NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART), /**< Start external flash memory erase operation. */
104 NRF_QSPI_TASK_DEACTIVATE = offsetof(NRF_QSPI_Type, TASKS_DEACTIVATE), /**< Deactivate the QSPI interface. */
105 } nrf_qspi_task_t;
106
107 /** @brief QSPI events. */
108 typedef enum
109 {
110 NRF_QSPI_EVENT_READY = offsetof(NRF_QSPI_Type, EVENTS_READY) /**< QSPI peripheral is ready after it executes any task. */
111 } nrf_qspi_event_t;
112
113 /** @brief QSPI interrupts. */
114 typedef enum
115 {
116 NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk /**< Interrupt on READY event. */
117 } nrf_qspi_int_mask_t;
118
119 /** @brief QSPI base clock frequency divider values. */
120 typedef enum
121 {
122 NRF_QSPI_FREQ_DIV1, /**< Divide by 1. */
123 NRF_QSPI_FREQ_DIV2, /**< Divide by 2. */
124 NRF_QSPI_FREQ_DIV3, /**< Divide by 3. */
125 NRF_QSPI_FREQ_DIV4, /**< Divide by 4. */
126 NRF_QSPI_FREQ_DIV5, /**< Divide by 5. */
127 NRF_QSPI_FREQ_DIV6, /**< Divide by 6. */
128 NRF_QSPI_FREQ_DIV7, /**< Divide by 7. */
129 NRF_QSPI_FREQ_DIV8, /**< Divide by 8. */
130 NRF_QSPI_FREQ_DIV9, /**< Divide by 9. */
131 NRF_QSPI_FREQ_DIV10, /**< Divide by 10. */
132 NRF_QSPI_FREQ_DIV11, /**< Divide by 11. */
133 NRF_QSPI_FREQ_DIV12, /**< Divide by 12. */
134 NRF_QSPI_FREQ_DIV13, /**< Divide by 13. */
135 NRF_QSPI_FREQ_DIV14, /**< Divide by 14. */
136 NRF_QSPI_FREQ_DIV15, /**< Divide by 15. */
137 NRF_QSPI_FREQ_DIV16, /**< Divide by 16. */
138 } nrf_qspi_frequency_t;
139
140 #if defined(NRF52_SERIES)
141 /** Symbols translation for backward compatibility. */
142 #define NRF_QSPI_FREQ_32MDIV1 NRF_QSPI_FREQ_DIV1
143 #define NRF_QSPI_FREQ_32MDIV2 NRF_QSPI_FREQ_DIV2
144 #define NRF_QSPI_FREQ_32MDIV3 NRF_QSPI_FREQ_DIV3
145 #define NRF_QSPI_FREQ_32MDIV4 NRF_QSPI_FREQ_DIV4
146 #define NRF_QSPI_FREQ_32MDIV5 NRF_QSPI_FREQ_DIV5
147 #define NRF_QSPI_FREQ_32MDIV6 NRF_QSPI_FREQ_DIV6
148 #define NRF_QSPI_FREQ_32MDIV7 NRF_QSPI_FREQ_DIV7
149 #define NRF_QSPI_FREQ_32MDIV8 NRF_QSPI_FREQ_DIV8
150 #define NRF_QSPI_FREQ_32MDIV9 NRF_QSPI_FREQ_DIV9
151 #define NRF_QSPI_FREQ_32MDIV10 NRF_QSPI_FREQ_DIV10
152 #define NRF_QSPI_FREQ_32MDIV11 NRF_QSPI_FREQ_DIV11
153 #define NRF_QSPI_FREQ_32MDIV12 NRF_QSPI_FREQ_DIV12
154 #define NRF_QSPI_FREQ_32MDIV13 NRF_QSPI_FREQ_DIV13
155 #define NRF_QSPI_FREQ_32MDIV14 NRF_QSPI_FREQ_DIV14
156 #define NRF_QSPI_FREQ_32MDIV15 NRF_QSPI_FREQ_DIV15
157 #define NRF_QSPI_FREQ_32MDIV16 NRF_QSPI_FREQ_DIV16
158 #endif
159
160 /** @brief Interface configuration for a read operation. */
161 typedef enum
162 {
163 NRF_QSPI_READOC_FASTREAD = QSPI_IFCONFIG0_READOC_FASTREAD, /**< Single data line SPI. FAST_READ (opcode 0x0B). */
164 NRF_QSPI_READOC_READ2O = QSPI_IFCONFIG0_READOC_READ2O, /**< Dual data line SPI. READ2O (opcode 0x3B). */
165 NRF_QSPI_READOC_READ2IO = QSPI_IFCONFIG0_READOC_READ2IO, /**< Dual data line SPI. READ2IO (opcode 0xBB). */
166 NRF_QSPI_READOC_READ4O = QSPI_IFCONFIG0_READOC_READ4O, /**< Quad data line SPI. READ4O (opcode 0x6B). */
167 NRF_QSPI_READOC_READ4IO = QSPI_IFCONFIG0_READOC_READ4IO /**< Quad data line SPI. READ4IO (opcode 0xEB). */
168 } nrf_qspi_readoc_t;
169
170 /** @brief Interface configuration for a write operation. */
171 typedef enum
172 {
173 NRF_QSPI_WRITEOC_PP = QSPI_IFCONFIG0_WRITEOC_PP, /**< Single data line SPI. PP (opcode 0x02). */
174 NRF_QSPI_WRITEOC_PP2O = QSPI_IFCONFIG0_WRITEOC_PP2O, /**< Dual data line SPI. PP2O (opcode 0xA2). */
175 NRF_QSPI_WRITEOC_PP4O = QSPI_IFCONFIG0_WRITEOC_PP4O, /**< Quad data line SPI. PP4O (opcode 0x32). */
176 NRF_QSPI_WRITEOC_PP4IO = QSPI_IFCONFIG0_WRITEOC_PP4IO, /**< Quad data line SPI. READ4O (opcode 0x38). */
177 } nrf_qspi_writeoc_t;
178
179 /** @brief Interface configuration for addressing mode. */
180 typedef enum
181 {
182 NRF_QSPI_ADDRMODE_24BIT = QSPI_IFCONFIG0_ADDRMODE_24BIT, /**< 24-bit addressing. */
183 NRF_QSPI_ADDRMODE_32BIT = QSPI_IFCONFIG0_ADDRMODE_32BIT /**< 32-bit addressing. */
184 } nrf_qspi_addrmode_t;
185
186 /** @brief QSPI SPI mode. Polarization and phase configuration. */
187 typedef enum
188 {
189 NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */
190 #if NRF_QSPI_HAS_MODE_1
191 NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */
192 #endif
193 } nrf_qspi_spi_mode_t;
194
195 /** @brief Addressing configuration mode. */
196 typedef enum
197 {
198 NRF_QSPI_ADDRCONF_MODE_NOINSTR = QSPI_ADDRCONF_MODE_NoInstr, /**< Do not send any instruction. */
199 NRF_QSPI_ADDRCONF_MODE_OPCODE = QSPI_ADDRCONF_MODE_Opcode, /**< Send opcode. */
200 NRF_QSPI_ADDRCONF_MODE_OPBYTE0 = QSPI_ADDRCONF_MODE_OpByte0, /**< Send opcode, byte0. */
201 NRF_QSPI_ADDRCONF_MODE_ALL = QSPI_ADDRCONF_MODE_All /**< Send opcode, byte0, byte1. */
202 } nrf_qspi_addrconfig_mode_t;
203
204 /** @brief Erasing data length. */
205 typedef enum
206 {
207 NRF_QSPI_ERASE_LEN_4KB = QSPI_ERASE_LEN_LEN_4KB, /**< Erase 4 kB block (flash command 0x20). */
208 NRF_QSPI_ERASE_LEN_64KB = QSPI_ERASE_LEN_LEN_64KB, /**< Erase 64 kB block (flash command 0xD8). */
209 NRF_QSPI_ERASE_LEN_ALL = QSPI_ERASE_LEN_LEN_All /**< Erase all (flash command 0xC7). */
210 } nrf_qspi_erase_len_t;
211
212 /** @brief Custom instruction length. */
213 typedef enum
214 {
215 NRF_QSPI_CINSTR_LEN_1B = QSPI_CINSTRCONF_LENGTH_1B, /**< Send opcode only. */
216 NRF_QSPI_CINSTR_LEN_2B = QSPI_CINSTRCONF_LENGTH_2B, /**< Send opcode, CINSTRDAT0.BYTE0. */
217 NRF_QSPI_CINSTR_LEN_3B = QSPI_CINSTRCONF_LENGTH_3B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */
218 NRF_QSPI_CINSTR_LEN_4B = QSPI_CINSTRCONF_LENGTH_4B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */
219 NRF_QSPI_CINSTR_LEN_5B = QSPI_CINSTRCONF_LENGTH_5B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */
220 NRF_QSPI_CINSTR_LEN_6B = QSPI_CINSTRCONF_LENGTH_6B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */
221 NRF_QSPI_CINSTR_LEN_7B = QSPI_CINSTRCONF_LENGTH_7B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */
222 NRF_QSPI_CINSTR_LEN_8B = QSPI_CINSTRCONF_LENGTH_8B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */
223 NRF_QSPI_CINSTR_LEN_9B = QSPI_CINSTRCONF_LENGTH_9B /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */
224 } nrf_qspi_cinstr_len_t;
225
226 /** @brief Pin configuration. */
227 typedef struct
228 {
229 uint32_t sck_pin; /**< SCK pin number. */
230 uint32_t csn_pin; /**< Chip select pin number. */
231 uint32_t io0_pin; /**< IO0/MOSI pin number. */
232 uint32_t io1_pin; /**< IO1/MISO pin number. */
233 uint32_t io2_pin; /**< IO2 pin number (optional).
234 * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
235 */
236 uint32_t io3_pin; /**< IO3 pin number (optional).
237 * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
238 */
239 } nrf_qspi_pins_t;
240
241 /** @brief Custom instruction configuration. */
242 typedef struct
243 {
244 uint8_t opcode; /**< Opcode used in custom instruction transmission. */
245 nrf_qspi_cinstr_len_t length; /**< Length of the custom instruction data. */
246 bool io2_level; /**< I/O line level during transmission. */
247 bool io3_level; /**< I/O line level during transmission. */
248 bool wipwait; /**< Wait if a Wait in Progress bit is set in the memory status byte. */
249 bool wren; /**< Send write enable before instruction. */
250 } nrf_qspi_cinstr_conf_t;
251
252 /** @brief Addressing mode register configuration. See @ref nrf_qspi_addrconfig_set */
253 typedef struct
254 {
255 uint8_t opcode; /**< Opcode used to enter the proper addressing mode. */
256 uint8_t byte0; /**< Byte following the opcode. */
257 uint8_t byte1; /**< Byte following byte0. */
258 nrf_qspi_addrconfig_mode_t mode; /**< Extended addresing mode. */
259 bool wipwait; /**< Enable or disable waiting for complete operation execution. */
260 bool wren; /**< Send write enable before instruction. */
261 } nrf_qspi_addrconfig_conf_t;
262
263 /** @brief Structure with QSPI protocol interface configuration. */
264 typedef struct
265 {
266 nrf_qspi_readoc_t readoc; /**< Read operation code. */
267 nrf_qspi_writeoc_t writeoc; /**< Write operation code. */
268 nrf_qspi_addrmode_t addrmode; /**< Addresing mode (24-bit or 32-bit). */
269 bool dpmconfig; /**< Enable the Deep Power-down Mode (DPM) feature. */
270 } nrf_qspi_prot_conf_t;
271
272 /** @brief QSPI physical interface configuration. */
273 typedef struct
274 {
275 uint8_t sck_delay; /**< tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns). */
276 bool dpmen; /**< Enable the DPM feature. */
277 nrf_qspi_spi_mode_t spi_mode; /**< SPI phase and polarization. */
278 nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as QSPI base clock frequency divider.
279 * To calculate @p sck_freq value corresponding to chosen frequency,
280 * use the following equation:
281 *
282 * sck_freq = (NRF_QSPI_BASE_CLOCK_FREQ / frequency) - 1
283 *
284 * @note Achievable frequencies are determined by available
285 * divider values and QSPI base clock frequency.
286 */
287 } nrf_qspi_phy_conf_t;
288
289
290 #if NRF_QSPI_HAS_XIP_ENC || NRF_QSPI_HAS_DMA_ENC
291 /** @brief QSPI encryption settings for XIP and DMA transfers. */
292 typedef struct
293 {
294 uint32_t key[4]; /**< AES 128-bit key, stored on 4 32-bit words. */
295 uint32_t nonce[3]; /**< AES 96-bit nonce, stored on 3 32-bit words. */
296 } nrf_qspi_encryption_t;
297 #endif
298
299 /**
300 * @brief Function for activating the specified QSPI task.
301 *
302 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
303 * @param[in] task Task to be activated.
304 */
305 NRF_STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task);
306
307 /**
308 * @brief Function for getting the address of the specified QSPI task register.
309 *
310 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
311 * @param[in] task QSPI task.
312 *
313 * @return Address of the specified task register.
314 */
315 NRF_STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
316 nrf_qspi_task_t task);
317
318 /**
319 * @brief Function for clearing the specified QSPI event.
320 *
321 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
322 * @param[in] event Event to be cleared.
323 */
324 NRF_STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event);
325
326 /**
327 * @brief Function for retrieving the state of the QSPI event.
328 *
329 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
330 * @param[in] event Event to be checked.
331 *
332 * @retval true The event has been generated.
333 * @retval false The event has not been generated.
334 */
335 NRF_STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event);
336
337 /**
338 * @brief Function for getting the address of the specified QSPI event register.
339 *
340 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
341 * @param[in] event The specified event.
342 *
343 * @return Address of the specified event register.
344 */
345 NRF_STATIC_INLINE uint32_t nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
346 nrf_qspi_event_t event);
347
348 /**
349 * @brief Function for enabling specified interrupts.
350 *
351 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
352 * @param[in] mask Mask of interrupts to be enabled.
353 * Use @ref nrf_qspi_int_mask_t values for bit masking.
354 */
355 NRF_STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask);
356
357 /**
358 * @brief Function for disabling specified interrupts.
359 *
360 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
361 * @param[in] mask Mask of interrupts to be disabled.
362 * Use @ref nrf_qspi_int_mask_t values for bit masking.
363 */
364 NRF_STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask);
365
366 /**
367 * @brief Function for checking if the specified interrupts are enabled.
368 *
369 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
370 * @param[in] mask Mask of interrupts to be checked.
371 * Use @ref nrf_qspi_int_mask_t values for bit masking.
372 *
373 * @return Mask of enabled interrupts.
374 */
375 NRF_STATIC_INLINE uint32_t nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, uint32_t mask);
376
377 /**
378 * @brief Function for enabling the QSPI peripheral.
379 *
380 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
381 */
382 NRF_STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg);
383
384 /**
385 * @brief Function for disabling the QSPI peripheral.
386 *
387 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
388 */
389 NRF_STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg);
390
391 /**
392 * @brief Function for configuring QSPI pins.
393 *
394 * If a given signal is not needed, pass the @ref NRF_QSPI_PIN_NOT_CONNECTED
395 * value instead of its pin number.
396 *
397 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
398 * @param[in] p_pins Pointer to the pins configuration structure. See @ref nrf_qspi_pins_t.
399 */
400 NRF_STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,
401 nrf_qspi_pins_t const * p_pins);
402
403 /**
404 * @brief Function for setting the SCK pin.
405 *
406 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
407 * @param[in] pin SCK pin number.
408 */
409 NRF_STATIC_INLINE void nrf_qspi_pin_sck_set(NRF_QSPI_Type * p_reg, uint32_t pin);
410
411 /**
412 * @brief Function for setting the CSN pin.
413 *
414 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
415 * @param[in] pin CSN pin number.
416 */
417 NRF_STATIC_INLINE void nrf_qspi_pin_csn_set(NRF_QSPI_Type * p_reg, uint32_t pin);
418
419 /**
420 * @brief Function for setting the IO0 pin.
421 *
422 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
423 * @param[in] pin IO0 pin number.
424 */
425 NRF_STATIC_INLINE void nrf_qspi_pin_io0_set(NRF_QSPI_Type * p_reg, uint32_t pin);
426
427 /**
428 * @brief Function for setting the IO1 pin.
429 *
430 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
431 * @param[in] pin IO1 pin number.
432 */
433 NRF_STATIC_INLINE void nrf_qspi_pin_io1_set(NRF_QSPI_Type * p_reg, uint32_t pin);
434
435 /**
436 * @brief Function for setting the IO2 pin.
437 *
438 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
439 * @param[in] pin IO2 pin number.
440 */
441 NRF_STATIC_INLINE void nrf_qspi_pin_io2_set(NRF_QSPI_Type * p_reg, uint32_t pin);
442
443 /**
444 * @brief Function for setting the IO3 pin.
445 *
446 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
447 * @param[in] pin IO3 pin number.
448 */
449 NRF_STATIC_INLINE void nrf_qspi_pin_io3_set(NRF_QSPI_Type * p_reg, uint32_t pin);
450
451 /**
452 * @brief Function for getting the currently configured QSPI pins.
453 *
454 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
455 * @param[out] p_pins Pointer to the pins configuration structure to be filled with QSPI pins.
456 */
457 NRF_STATIC_INLINE void nrf_qspi_pins_get(NRF_QSPI_Type const * p_reg,
458 nrf_qspi_pins_t * p_pins);
459
460 /**
461 * @brief Function for setting the QSPI XIPOFFSET register.
462 *
463 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
464 * @param[in] xip_offset Address offset in the external memory for Execute in Place operation.
465 */
466 NRF_STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
467 uint32_t xip_offset);
468
469 /**
470 * @brief Function for setting the QSPI IFCONFIG0 register.
471 *
472 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
473 * @param[in] p_config Pointer to the QSPI protocol interface configuration structure.
474 * See @ref nrf_qspi_prot_conf_t.
475 */
476 NRF_STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
477 nrf_qspi_prot_conf_t const * p_config);
478
479 /**
480 * @brief Function for setting the explicit value of the QSPI IFCONFIG0 register.
481 *
482 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
483 * @param[in] regval Register value to be set.
484 */
485 NRF_STATIC_INLINE void nrf_qspi_ifconfig0_raw_set(NRF_QSPI_Type * p_reg, uint32_t regval);
486
487 /**
488 * @brief Function for getting the explicit value of the QSPI IFCONFIG0 register.
489 *
490 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
491 *
492 * @return Value of IFCONFIG0 register.
493 */
494 NRF_STATIC_INLINE uint32_t nrf_qspi_ifconfig0_raw_get(NRF_QSPI_Type const * p_reg);
495
496 /**
497 * @brief Function for setting the QSPI IFCONFIG1 register.
498 *
499 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
500 * @param[in] p_config Pointer to the QSPI physical interface configuration structure.
501 * See @ref nrf_qspi_phy_conf_t.
502 */
503 NRF_STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
504 nrf_qspi_phy_conf_t const * p_config);
505
506 /**
507 * @brief Function for setting the QSPI ADDRCONF register.
508 *
509 * This function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure
510 * is sent during the start of the peripheral. Remember that the reset instruction can set
511 * addressing mode to default in the memory device. If memory reset is necessary before configuring
512 * the addressing mode, use custom instruction feature instead of this function.
513 * Case with reset: Enable the peripheral without setting ADDRCONF register, send reset instructions
514 * using a custom instruction feature (reset enable and then reset), set proper addressing mode
515 * using the custom instruction feature.
516 *
517 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
518 * @param[in] p_config Pointer to the addressing mode configuration structure.
519 * See @ref nrf_qspi_addrconfig_conf_t.
520 */
521 NRF_STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
522 nrf_qspi_addrconfig_conf_t const * p_config);
523
524 /**
525 * @brief Function for setting write data into the peripheral register (without starting the process).
526 *
527 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
528 * @param[in] p_buffer Pointer to the writing buffer.
529 * @param[in] length Lenght of the writing data.
530 * @param[in] dest_addr Address in memory to write to.
531 */
532 NRF_STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
533 void const * p_buffer,
534 uint32_t length,
535 uint32_t dest_addr);
536
537 /**
538 * @brief Function for setting read data into the peripheral register (without starting the process).
539 *
540 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
541 * @param[out] p_buffer Pointer to the reading buffer.
542 * @param[in] length Length of the read data.
543 * @param[in] src_addr Address in memory to read from.
544 */
545 NRF_STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
546 void * p_buffer,
547 uint32_t length,
548 uint32_t src_addr);
549
550 /**
551 * @brief Function for setting erase data into the peripheral register (without starting the process).
552 *
553 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
554 * @param[in] erase_addr Start address to erase. Address must have padding set to 4 bytes.
555 * @param[in] len Size of erasing area.
556 */
557 NRF_STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
558 uint32_t erase_addr,
559 nrf_qspi_erase_len_t len);
560
561 /**
562 * @brief Function for getting the currently configured erase pointer.
563 *
564 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
565 *
566 * @return Erase pointer.
567 */
568 NRF_STATIC_INLINE uint32_t nrf_qspi_erase_ptr_get(NRF_QSPI_Type const * p_reg);
569
570 /**
571 * @brief Function for getting the currently configured erase length.
572 *
573 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
574 *
575 * @return Erase length.
576 */
577 NRF_STATIC_INLINE nrf_qspi_erase_len_t nrf_qspi_erase_len_get(NRF_QSPI_Type const * p_reg);
578
579 /**
580 * @brief Function for getting the peripheral status register.
581 *
582 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
583 *
584 * @return Peripheral status register.
585 */
586 NRF_STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg);
587
588 /**
589 * @brief Function for getting the device status register stored in the peripheral status register.
590 *
591 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
592 *
593 * @return Device status register (lower byte).
594 */
595 NRF_STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg);
596
597 /**
598 * @brief Function for checking if the peripheral is busy or not.
599 *
600 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
601 *
602 * @retval true The QSPI is busy.
603 * @retval false The QSPI is ready.
604 */
605 NRF_STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg);
606
607 /**
608 * @brief Function for setting registers sending with custom instruction transmission.
609 *
610 * This function can be ommited when using NRF_QSPI_CINSTR_LEN_1B as the length argument
611 * (sending only opcode without data).
612 *
613 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
614 * @param[in] length Length of the custom instruction data.
615 * @param[in] p_tx_data Pointer to the data to send with the custom instruction.
616 */
617 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
618 nrf_qspi_cinstr_len_t length,
619 void const * p_tx_data);
620
621 /**
622 * @brief Function for getting data from register after custom instruction transmission.
623 *
624 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
625 * @param[in] length Length of the custom instruction data.
626 * @param[in] p_rx_data Pointer to the reading buffer.
627 */
628 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
629 nrf_qspi_cinstr_len_t length,
630 void * p_rx_data);
631
632 /**
633 * @brief Function for sending custom instruction to external memory.
634 *
635 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
636 * @param[in] p_config Pointer to the custom instruction configuration structure.
637 * See @ref nrf_qspi_cinstr_conf_t.
638 */
639 NRF_STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
640 nrf_qspi_cinstr_conf_t const * p_config);
641
642 /**
643 * @brief Function for starting a custom instruction long transfer.
644 *
645 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
646 * @param[in] p_config Pointer to the custom instruction configuration structure.
647 * See @ref nrf_qspi_cinstr_conf_t.
648 */
649 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
650 nrf_qspi_cinstr_conf_t const * p_config);
651
652 /**
653 * @brief Function for checking whether a custom instruction long transfer is ongoing.
654 *
655 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
656 *
657 * @retval true Custom instruction long transfer is ongoing.
658 * @retval false Custom instruction long transfer is not ongoing.
659 */
660 NRF_STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg);
661
662 /**
663 * @brief Function for continuing a custom instruction long transfer.
664 *
665 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
666 * @param[in] length Length of the custom instruction data.
667 * @param[in] finalize True if the custom instruction long transfer is to be finalized.
668 * False if the custom instruction long transfer is to be continued.
669 */
670 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
671 nrf_qspi_cinstr_len_t length,
672 bool finalize);
673
674 #if NRF_QSPI_HAS_XIPEN
675 /**
676 * @brief Function for enabling or disabling Execute in Place (XIP) operation.
677 *
678 * @note XIP can be enabled after reset. See Product Specification.
679 *
680 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
681 * @param[in] enable True if XIP is to be enabled, false otherwise.
682 */
683 NRF_STATIC_INLINE void nrf_qspi_xip_set(NRF_QSPI_Type * p_reg, bool enable);
684 #endif
685
686 #if NRF_QSPI_HAS_XIP_ENC
687 /**
688 * @brief Function for configuring the XIP encryption.
689 *
690 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
691 * @param[in] p_cfg Pointer to encryption configuration structure.
692 */
693 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_configure(NRF_QSPI_Type * p_reg,
694 nrf_qspi_encryption_t const * p_cfg);
695
696 /**
697 * @brief Function for enabling or disabling the XIP encryption.
698 *
699 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
700 * @param[in] enable True if XIP encryption is to be enabled, false otherwise.
701 */
702 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg, bool enable);
703 #endif
704
705 #if NRF_QSPI_HAS_DMA_ENC
706 /**
707 * @brief Function for configuring the EasyDMA encryption.
708 *
709 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
710 * @param[in] p_cfg Pointer to encryption configuration structure.
711 */
712 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * p_reg,
713 nrf_qspi_encryption_t const * p_cfg);
714
715 /**
716 * @brief Function for enabling or disabling the EasyDMA encryption.
717 *
718 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
719 * @param[in] enable True if EasyDMA encryption is to be enabled, false otherwise.
720 */
721 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool enable);
722 #endif
723
724 /**
725 * @brief Function for setting the timing related to sampling of the input serial data.
726 *
727 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
728 * @param[in] rxdelay Number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the clock
729 * until the input serial data is sampled.
730 */
731 NRF_STATIC_INLINE void nrf_qspi_iftiming_set(NRF_QSPI_Type * p_reg, uint8_t rxdelay);
732
733 #ifndef NRF_DECLARE_ONLY
734
nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg,nrf_qspi_task_t task)735 NRF_STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task)
736 {
737 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
738 }
739
nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,nrf_qspi_task_t task)740 NRF_STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
741 nrf_qspi_task_t task)
742 {
743 return ((uint32_t)p_reg + (uint32_t)task);
744 }
745
nrf_qspi_event_clear(NRF_QSPI_Type * p_reg,nrf_qspi_event_t event)746 NRF_STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event)
747 {
748 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
749 }
750
nrf_qspi_event_check(NRF_QSPI_Type const * p_reg,nrf_qspi_event_t event)751 NRF_STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event)
752 {
753 return nrf_event_check(p_reg, event);
754 }
755
nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,nrf_qspi_event_t event)756 NRF_STATIC_INLINE uint32_t nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
757 nrf_qspi_event_t event)
758 {
759 return nrf_task_event_address_get(p_reg, event);
760 }
761
nrf_qspi_int_enable(NRF_QSPI_Type * p_reg,uint32_t mask)762 NRF_STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask)
763 {
764 p_reg->INTENSET = mask;
765 }
766
nrf_qspi_int_disable(NRF_QSPI_Type * p_reg,uint32_t mask)767 NRF_STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask)
768 {
769 p_reg->INTENCLR = mask;
770 }
771
nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,uint32_t mask)772 NRF_STATIC_INLINE uint32_t nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, uint32_t mask)
773 {
774 return p_reg->INTENSET & mask;
775 }
776
nrf_qspi_enable(NRF_QSPI_Type * p_reg)777 NRF_STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg)
778 {
779 p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos);
780 }
781
nrf_qspi_disable(NRF_QSPI_Type * p_reg)782 NRF_STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg)
783 {
784 if (nrf52_errata_122())
785 {
786 // Workaround for anomaly 122: "QSPI: QSPI uses current after being disabled".
787 *(volatile uint32_t *)0x40029054ul = 1ul;
788 }
789 p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos);
790 }
791
nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,nrf_qspi_pins_t const * p_pins)792 NRF_STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, nrf_qspi_pins_t const * p_pins)
793 {
794 p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin);
795 p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin);
796 p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin);
797 p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin);
798 p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin);
799 p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin);
800 }
801
nrf_qspi_pin_sck_set(NRF_QSPI_Type * p_reg,uint32_t pin)802 NRF_STATIC_INLINE void nrf_qspi_pin_sck_set(NRF_QSPI_Type * p_reg, uint32_t pin)
803 {
804 p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(pin);
805 }
806
nrf_qspi_pin_csn_set(NRF_QSPI_Type * p_reg,uint32_t pin)807 NRF_STATIC_INLINE void nrf_qspi_pin_csn_set(NRF_QSPI_Type * p_reg, uint32_t pin)
808 {
809 p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(pin);
810 }
811
nrf_qspi_pin_io0_set(NRF_QSPI_Type * p_reg,uint32_t pin)812 NRF_STATIC_INLINE void nrf_qspi_pin_io0_set(NRF_QSPI_Type * p_reg, uint32_t pin)
813 {
814 p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(pin);
815 }
816
nrf_qspi_pin_io1_set(NRF_QSPI_Type * p_reg,uint32_t pin)817 NRF_STATIC_INLINE void nrf_qspi_pin_io1_set(NRF_QSPI_Type * p_reg, uint32_t pin)
818 {
819 p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(pin);
820 }
821
nrf_qspi_pin_io2_set(NRF_QSPI_Type * p_reg,uint32_t pin)822 NRF_STATIC_INLINE void nrf_qspi_pin_io2_set(NRF_QSPI_Type * p_reg, uint32_t pin)
823 {
824 p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(pin);
825 }
826
nrf_qspi_pin_io3_set(NRF_QSPI_Type * p_reg,uint32_t pin)827 NRF_STATIC_INLINE void nrf_qspi_pin_io3_set(NRF_QSPI_Type * p_reg, uint32_t pin)
828 {
829 p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(pin);
830 }
831
nrf_qspi_pins_get(NRF_QSPI_Type const * p_reg,nrf_qspi_pins_t * p_pins)832 NRF_STATIC_INLINE void nrf_qspi_pins_get(NRF_QSPI_Type const * p_reg,
833 nrf_qspi_pins_t * p_pins)
834 {
835 p_pins->sck_pin = (uint8_t)p_reg->PSEL.SCK;
836 p_pins->csn_pin = (uint8_t)p_reg->PSEL.CSN;
837 p_pins->io0_pin = (uint8_t)p_reg->PSEL.IO0;
838 p_pins->io1_pin = (uint8_t)p_reg->PSEL.IO1;
839 p_pins->io2_pin = (uint8_t)p_reg->PSEL.IO2;
840 p_pins->io3_pin = (uint8_t)p_reg->PSEL.IO3;
841 }
842
nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,uint32_t xip_offset)843 NRF_STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
844 uint32_t xip_offset)
845 {
846 p_reg->XIPOFFSET = xip_offset;
847 }
848
nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,nrf_qspi_prot_conf_t const * p_config)849 NRF_STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
850 nrf_qspi_prot_conf_t const * p_config)
851 {
852 uint32_t config = p_config->readoc;
853 config |= ((uint32_t)p_config->writeoc) << QSPI_IFCONFIG0_WRITEOC_Pos;
854 config |= ((uint32_t)p_config->addrmode) << QSPI_IFCONFIG0_ADDRMODE_Pos;
855 config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos;
856
857 p_reg->IFCONFIG0 = config;
858 }
859
nrf_qspi_ifconfig0_raw_set(NRF_QSPI_Type * p_reg,uint32_t regval)860 NRF_STATIC_INLINE void nrf_qspi_ifconfig0_raw_set(NRF_QSPI_Type * p_reg, uint32_t regval)
861 {
862 p_reg->IFCONFIG0 = regval;
863 }
864
nrf_qspi_ifconfig0_raw_get(NRF_QSPI_Type const * p_reg)865 NRF_STATIC_INLINE uint32_t nrf_qspi_ifconfig0_raw_get(NRF_QSPI_Type const * p_reg)
866 {
867 return p_reg->IFCONFIG0;
868 }
869
nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,nrf_qspi_phy_conf_t const * p_config)870 NRF_STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
871 nrf_qspi_phy_conf_t const * p_config)
872 {
873 // IFCONFIG1 mask for reserved fields in the register.
874 uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00;
875 config |= p_config->sck_delay;
876 config |= (p_config->dpmen ? 1U : 0U) << QSPI_IFCONFIG1_DPMEN_Pos;
877 config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos;
878 config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos;
879
880 p_reg->IFCONFIG1 = config;
881 }
882
nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,nrf_qspi_addrconfig_conf_t const * p_config)883 NRF_STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
884 nrf_qspi_addrconfig_conf_t const * p_config)
885 {
886 uint32_t config = p_config->opcode;
887 config |= ((uint32_t)p_config->byte0) << QSPI_ADDRCONF_BYTE0_Pos;
888 config |= ((uint32_t)p_config->byte1) << QSPI_ADDRCONF_BYTE1_Pos;
889 config |= ((uint32_t)(p_config->mode)) << QSPI_ADDRCONF_MODE_Pos;
890 config |= (p_config->wipwait ? 1U : 0U) << QSPI_ADDRCONF_WIPWAIT_Pos;
891 config |= (p_config->wren ? 1U : 0U) << QSPI_ADDRCONF_WREN_Pos;
892
893 p_reg->ADDRCONF = config;
894 }
895
nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,void const * p_buffer,uint32_t length,uint32_t dest_addr)896 NRF_STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
897 void const * p_buffer,
898 uint32_t length,
899 uint32_t dest_addr)
900 {
901 p_reg->WRITE.DST = dest_addr;
902 p_reg->WRITE.SRC = (uint32_t) p_buffer;
903 p_reg->WRITE.CNT = length;
904 }
905
nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,void * p_buffer,uint32_t length,uint32_t src_addr)906 NRF_STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
907 void * p_buffer,
908 uint32_t length,
909 uint32_t src_addr)
910 {
911 p_reg->READ.SRC = src_addr;
912 p_reg->READ.DST = (uint32_t) p_buffer;
913 p_reg->READ.CNT = length;
914 }
915
nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,uint32_t erase_addr,nrf_qspi_erase_len_t len)916 NRF_STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
917 uint32_t erase_addr,
918 nrf_qspi_erase_len_t len)
919 {
920 p_reg->ERASE.PTR = erase_addr;
921 p_reg->ERASE.LEN = len;
922 }
923
nrf_qspi_erase_ptr_get(NRF_QSPI_Type const * p_reg)924 NRF_STATIC_INLINE uint32_t nrf_qspi_erase_ptr_get(NRF_QSPI_Type const * p_reg)
925 {
926 return p_reg->ERASE.PTR;
927 }
928
nrf_qspi_erase_len_get(NRF_QSPI_Type const * p_reg)929 NRF_STATIC_INLINE nrf_qspi_erase_len_t nrf_qspi_erase_len_get(NRF_QSPI_Type const * p_reg)
930 {
931 return (nrf_qspi_erase_len_t)p_reg->ERASE.LEN;
932 }
933
nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg)934 NRF_STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg)
935 {
936 return p_reg->STATUS;
937 }
938
nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg)939 NRF_STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg)
940 {
941 return (uint8_t)(p_reg->STATUS & QSPI_STATUS_SREG_Msk) >> QSPI_STATUS_SREG_Pos;
942 }
943
nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg)944 NRF_STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg)
945 {
946 return ((p_reg->STATUS & QSPI_STATUS_READY_Msk) >>
947 QSPI_STATUS_READY_Pos) == QSPI_STATUS_READY_BUSY;
948 }
949
nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_len_t length,void const * p_tx_data)950 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
951 nrf_qspi_cinstr_len_t length,
952 void const * p_tx_data)
953 {
954 uint32_t reg = 0;
955 uint8_t const *p_tx_data_8 = (uint8_t const *) p_tx_data;
956
957 // Load custom instruction.
958 switch (length)
959 {
960 case NRF_QSPI_CINSTR_LEN_9B:
961 reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos;
962 /* FALLTHROUGH */
963 case NRF_QSPI_CINSTR_LEN_8B:
964 reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos;
965 /* FALLTHROUGH */
966 case NRF_QSPI_CINSTR_LEN_7B:
967 reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos;
968 /* FALLTHROUGH */
969 case NRF_QSPI_CINSTR_LEN_6B:
970 reg |= ((uint32_t)p_tx_data_8[4]);
971 p_reg->CINSTRDAT1 = reg;
972 reg = 0;
973 /* FALLTHROUGH */
974 case NRF_QSPI_CINSTR_LEN_5B:
975 reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos;
976 /* FALLTHROUGH */
977 case NRF_QSPI_CINSTR_LEN_4B:
978 reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos;
979 /* FALLTHROUGH */
980 case NRF_QSPI_CINSTR_LEN_3B:
981 reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos;
982 /* FALLTHROUGH */
983 case NRF_QSPI_CINSTR_LEN_2B:
984 reg |= ((uint32_t)p_tx_data_8[0]);
985 p_reg->CINSTRDAT0 = reg;
986 /* FALLTHROUGH */
987 case NRF_QSPI_CINSTR_LEN_1B:
988 /* Send only opcode. Case to avoid compiler warnings. */
989 break;
990 default:
991 break;
992 }
993 }
994
nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,nrf_qspi_cinstr_len_t length,void * p_rx_data)995 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
996 nrf_qspi_cinstr_len_t length,
997 void * p_rx_data)
998 {
999 uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data;
1000
1001 uint32_t reg1 = p_reg->CINSTRDAT1;
1002 uint32_t reg0 = p_reg->CINSTRDAT0;
1003 switch (length)
1004 {
1005 case NRF_QSPI_CINSTR_LEN_9B:
1006 p_rx_data_8[7] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE7_Pos);
1007 /* FALLTHROUGH */
1008 case NRF_QSPI_CINSTR_LEN_8B:
1009 p_rx_data_8[6] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE6_Pos);
1010 /* FALLTHROUGH */
1011 case NRF_QSPI_CINSTR_LEN_7B:
1012 p_rx_data_8[5] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE5_Pos);
1013 /* FALLTHROUGH */
1014 case NRF_QSPI_CINSTR_LEN_6B:
1015 p_rx_data_8[4] = (uint8_t)(reg1);
1016 /* FALLTHROUGH */
1017 case NRF_QSPI_CINSTR_LEN_5B:
1018 p_rx_data_8[3] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE3_Pos);
1019 /* FALLTHROUGH */
1020 case NRF_QSPI_CINSTR_LEN_4B:
1021 p_rx_data_8[2] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE2_Pos);
1022 /* FALLTHROUGH */
1023 case NRF_QSPI_CINSTR_LEN_3B:
1024 p_rx_data_8[1] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE1_Pos);
1025 /* FALLTHROUGH */
1026 case NRF_QSPI_CINSTR_LEN_2B:
1027 p_rx_data_8[0] = (uint8_t)(reg0);
1028 /* FALLTHROUGH */
1029 case NRF_QSPI_CINSTR_LEN_1B:
1030 /* Send only opcode. Case to avoid compiler warnings. */
1031 break;
1032 default:
1033 break;
1034 }
1035 }
1036
nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_conf_t const * p_config)1037 NRF_STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
1038 nrf_qspi_cinstr_conf_t const * p_config)
1039 {
1040 p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
1041 ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
1042 ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
1043 ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
1044 ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
1045 ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos));
1046 }
1047
nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_conf_t const * p_config)1048 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
1049 nrf_qspi_cinstr_conf_t const * p_config)
1050 {
1051 p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
1052 ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
1053 ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
1054 ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
1055 ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
1056 ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos) |
1057 (QSPI_CINSTRCONF_LFEN_Msk));
1058 }
1059
nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg)1060 NRF_STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg)
1061 {
1062 return (bool)((p_reg->CINSTRCONF & (QSPI_CINSTRCONF_LFEN_Msk | QSPI_CINSTRCONF_LFSTOP_Msk))
1063 == QSPI_CINSTRCONF_LFEN_Msk);
1064 }
1065
nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_len_t length,bool finalize)1066 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
1067 nrf_qspi_cinstr_len_t length,
1068 bool finalize)
1069 {
1070 uint32_t mask = (((uint32_t)length << QSPI_CINSTRCONF_LENGTH_Pos) | (QSPI_CINSTRCONF_LFEN_Msk));
1071 mask |= (finalize ? QSPI_CINSTRCONF_LFSTOP_Msk : 0);
1072
1073 p_reg->CINSTRCONF = mask;
1074 }
1075
1076 #if NRF_QSPI_HAS_XIPEN
nrf_qspi_xip_set(NRF_QSPI_Type * p_reg,bool enable)1077 NRF_STATIC_INLINE void nrf_qspi_xip_set(NRF_QSPI_Type * p_reg, bool enable)
1078 {
1079 p_reg->XIPEN = (enable ? QSPI_XIPEN_XIPEN_Enable << QSPI_XIPEN_XIPEN_Pos
1080 : QSPI_XIPEN_XIPEN_Disable << QSPI_XIPEN_XIPEN_Pos);
1081 }
1082 #endif
1083
1084 #if NRF_QSPI_HAS_XIP_ENC
nrf_qspi_xip_encryption_configure(NRF_QSPI_Type * p_reg,nrf_qspi_encryption_t const * p_cfg)1085 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_configure(NRF_QSPI_Type * p_reg,
1086 nrf_qspi_encryption_t const * p_cfg)
1087 {
1088 p_reg->XIP_ENC.KEY0 = p_cfg->key[0];
1089 p_reg->XIP_ENC.KEY1 = p_cfg->key[1];
1090 p_reg->XIP_ENC.KEY2 = p_cfg->key[2];
1091 p_reg->XIP_ENC.KEY3 = p_cfg->key[3];
1092 p_reg->XIP_ENC.NONCE0 = p_cfg->nonce[0];
1093 p_reg->XIP_ENC.NONCE1 = p_cfg->nonce[1];
1094 p_reg->XIP_ENC.NONCE2 = p_cfg->nonce[2];
1095 }
1096
nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg,bool enable)1097 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg, bool enable)
1098 {
1099 p_reg->XIP_ENC.ENABLE =
1100 (enable ? QSPI_XIP_ENC_ENABLE_ENABLE_Enabled << QSPI_XIP_ENC_ENABLE_ENABLE_Pos
1101 : QSPI_XIP_ENC_ENABLE_ENABLE_Disabled << QSPI_XIP_ENC_ENABLE_ENABLE_Pos);
1102 }
1103 #endif
1104
1105 #if NRF_QSPI_HAS_DMA_ENC
nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * p_reg,nrf_qspi_encryption_t const * p_cfg)1106 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * p_reg,
1107 nrf_qspi_encryption_t const * p_cfg)
1108 {
1109 p_reg->DMA_ENC.KEY0 = p_cfg->key[0];
1110 p_reg->DMA_ENC.KEY1 = p_cfg->key[1];
1111 p_reg->DMA_ENC.KEY2 = p_cfg->key[2];
1112 p_reg->DMA_ENC.KEY3 = p_cfg->key[3];
1113 p_reg->DMA_ENC.NONCE0 = p_cfg->nonce[0];
1114 p_reg->DMA_ENC.NONCE1 = p_cfg->nonce[1];
1115 p_reg->DMA_ENC.NONCE2 = p_cfg->nonce[2];
1116 }
1117
nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg,bool enable)1118 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool enable)
1119 {
1120 p_reg->DMA_ENC.ENABLE =
1121 (enable ? QSPI_DMA_ENC_ENABLE_ENABLE_Enabled << QSPI_DMA_ENC_ENABLE_ENABLE_Pos
1122 : QSPI_DMA_ENC_ENABLE_ENABLE_Disabled << QSPI_DMA_ENC_ENABLE_ENABLE_Pos);
1123 }
1124 #endif
1125
nrf_qspi_iftiming_set(NRF_QSPI_Type * p_reg,uint8_t rxdelay)1126 NRF_STATIC_INLINE void nrf_qspi_iftiming_set(NRF_QSPI_Type * p_reg, uint8_t rxdelay)
1127 {
1128 p_reg->IFTIMING = ((uint32_t)rxdelay << QSPI_IFTIMING_RXDELAY_Pos) & QSPI_IFTIMING_RXDELAY_Msk;
1129 }
1130
1131 #endif // NRF_DECLARE_ONLY
1132
1133 /** @} */
1134
1135 #ifdef __cplusplus
1136 }
1137 #endif
1138
1139 #endif // NRF_QSPI_H__
1140
