1 /*
2 * Copyright (c) 2023 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_GRTC_H
35 #define NRF_GRTC_H
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if defined(LUMOS_XXAA)
44 #if defined(NRF_APPLICATION) && defined(NRF_TRUSTZONE_NONSECURE)
45 #define GRTC_IRQn GRTC_1_IRQn
46 #define GRTC_IRQHandler GRTC_1_IRQHandler
47 #elif defined(NRF_APPLICATION) && !defined(NRF_TRUSTZONE_NONSECURE)
48 #define GRTC_IRQn GRTC_2_IRQn
49 #define GRTC_IRQHandler GRTC_2_IRQHandler
50 #elif defined(NRF_FLPR)
51 #define GRTC_IRQn GRTC_0_IRQn
52 #define GRTC_IRQHandler GRTC_0_IRQHandler
53 #endif
54 #endif
55
56 #if defined(HALTIUM_XXAA)
57 #if (defined(ISA_ARM) && defined(NRF_TRUSTZONE_NONSECURE)) || defined(ISA_RISCV)
58 #define GRTC_IRQn GRTC_0_IRQn
59 #define GRTC_IRQHandler GRTC_0_IRQHandler
60 #else
61 #define GRTC_IRQn GRTC_1_IRQn
62 #define GRTC_IRQHandler GRTC_1_IRQHandler
63 #endif
64 #endif
65
66 /**
67 * @defgroup nrf_grtc_hal GRTC HAL
68 * @{
69 * @ingroup nrf_grtc
70 * @brief Hardware access layer for managing the Global Real Time Counter (GRTC) peripheral.
71 */
72
73 #if NRFX_CHECK(GRTC_PWMREGS) || defined(__NRFX_DOXYGEN__)
74 /** @brief Symbol indicating whether GRTC has PWM registers. */
75 #define NRF_GRTC_HAS_PWM 1
76 #else
77 #define NRF_GRTC_HAS_PWM 0
78 #endif
79
80 #if NRFX_CHECK(GRTC_CLKOUTREG) || defined(__NRFX_DOXYGEN__)
81 /** @brief Symbol indicating whether GRTC has clock output registers. */
82 #define NRF_GRTC_HAS_CLKOUT 1
83 #else
84 #define NRF_GRTC_HAS_CLKOUT 0
85 #endif
86
87 #if defined(GRTC_CLKCFG_CLKSEL_Msk) || defined(__NRFX_DOXYGEN__)
88 /** @brief Symbol indicating whether GRTC has clock source selection. */
89 #define NRF_GRTC_HAS_CLKSEL 1
90 #else
91 #define NRF_GRTC_HAS_CLKSEL 0
92 #endif
93
94 #if defined(GRTC_CLKCFG_CLKSEL_LFLPRC) || defined(__NRFX_DOXYGEN__)
95 /** @brief Symbol indicating whether RC oscillator clock source is available. */
96 #define NRF_GRTC_HAS_CLKSEL_LFLPRC 1
97 #else
98 #define NRF_GRTC_HAS_CLKSEL_LFLPRC 0
99 #endif
100
101 #if defined(GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
102 /** @brief Symbol indicating whether GRTC has multiple SYSCOUNTER registers. */
103 #define NRF_GRTC_HAS_SYSCOUNTER_ARRAY 1
104 #else
105 #define NRF_GRTC_HAS_SYSCOUNTER_ARRAY 0
106 #endif
107
108 #if defined(GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Msk) || defined(__NRFX_DOXYGEN__)
109 /** @brief Symbol indicating whether SYSCOUNTERVALID event is present. */
110 #define NRF_GRTC_HAS_SYSCOUNTERVALID 1
111 #else
112 #define NRF_GRTC_HAS_SYSCOUNTERVALID 0
113 #endif
114
115 #if defined(GRTC_KEEPRUNNING_DOMAIN0_Msk) || defined(GRTC_KEEPRUNNING_REQUEST0_Msk) || \
116 defined(__NRFX_DOXYGEN__)
117 /** @brief Symbol indicating whether KEEPRUNNING register is present. */
118 #define NRF_GRTC_HAS_KEEPRUNNING 1
119 #else
120 #define NRF_GRTC_HAS_KEEPRUNNING 0
121 #endif
122
123 #if defined(__NRFX_DOXYGEN__)
124 /** @brief Symbol indicating whether GRTC has RTCOUNTER. */
125 #define NRF_GRTC_HAS_RTCOUNTER 1
126 #elif !defined(NRF_GRTC_HAS_RTCOUNTER)
127 #define NRF_GRTC_HAS_RTCOUNTER 0
128 #endif
129
130 #if !defined(NRF_GRTC_HAS_EXTENDED)
131 #if defined(LUMOS_XXAA) || defined(__NRFX_DOXYGEN__)
132 /** @brief Symbol indicating whether GRTC has extended functionality. */
133 #define NRF_GRTC_HAS_EXTENDED 1
134 #else
135 #define NRF_GRTC_HAS_EXTENDED 0
136 #endif
137 #endif // !defined(NRF_GRTC_HAS_EXTENDED)
138
139 #if defined(GRTC_IRQ_GROUP) || defined(__NRFX_DOXYGEN__)
140 /** @brief Symbol indicating whether GRTC interrupt groups are present. */
141 #define NRF_GRTC_HAS_INT_GROUPS 1
142 #else
143 #define NRF_GRTC_HAS_INT_GROUPS 0
144 #endif
145
146 /** @brief Symbol indicating actual domain index. */
147 #define NRF_GRTC_DOMAIN_INDEX GRTC_IRQ_GROUP
148
149 /** @brief Symbol indicating actual SYSCOUNTER index. */
150 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
151 #define GRTC_SYSCOUNTER SYSCOUNTER[NRF_GRTC_DOMAIN_INDEX]
152 #endif
153
154 /** @brief Number of capture/compare channels for SYSCOUNTER. */
155 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
156 #define NRF_GRTC_SYSCOUNTER_COUNT GRTC_SYSCOUNTER_MaxCount
157 #endif
158
159 /** @brief Interrupts INTEN register definition. */
160 #define GRTC_INTEN NRFX_CONCAT_2(INTEN, GRTC_IRQ_GROUP)
161 /** @brief Interrupts INTENSET register definition. */
162 #define GRTC_INTENSET NRFX_CONCAT_2(INTENSET, GRTC_IRQ_GROUP)
163 /** @brief Interrupts INTENCLR register definition. */
164 #define GRTC_INTENCLR NRFX_CONCAT_2(INTENCLR, GRTC_IRQ_GROUP)
165 /** @brief Interrupts INTPEND register definition. */
166 #define GRTC_INTPEND NRFX_CONCAT_2(INTPEND, GRTC_IRQ_GROUP)
167
168 /** @brief Main SYSCOUNTER frequency in Hz. */
169 #define NRF_GRTC_SYSCOUNTER_MAIN_FREQUENCY_HZ 1000000UL
170
171 /** @brief Number of capture/compare channels for SYSCOUNTER. */
172 #define NRF_GRTC_SYSCOUNTER_CC_COUNT GRTC_CC_MaxCount
173
174 /** @brief Bitmask of the higher 32-bits of capture/compare register for the SYSCOUNTER. */
175 #define NRF_GRTC_SYSCOUNTER_CCH_MASK GRTC_CC_CCH_CCH_Msk
176
177 /** @brief Bitmask of CCADD register for the SYSCOUNTER. */
178 #define NRF_GRTC_SYSCOUNTER_CCADD_MASK GRTC_CC_CCADD_VALUE_Msk
179
180 #if defined(GRTC_SYSCOUNTERL_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
181 /** @brief Bitmask of the lower part of the SYSCOUNTER value. */
182 #define NRF_GRTC_SYSCOUNTERL_VALUE_MASK GRTC_SYSCOUNTERL_VALUE_Msk
183 #else
184 #define NRF_GRTC_SYSCOUNTERL_VALUE_MASK GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Msk
185 #endif
186
187 #if defined(GRTC_SYSCOUNTERH_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
188 /** @brief Bitmask of the higher part of the SYSCOUNTER value. */
189 #define NRF_GRTC_SYSCOUNTERH_VALUE_MASK GRTC_SYSCOUNTERH_VALUE_Msk
190 #else
191 #define NRF_GRTC_SYSCOUNTERH_VALUE_MASK GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Msk
192 #endif
193
194 /** @brief Bitmask of the higher 32-bits of capture/compare register for the RTCOUNTER. */
195 #define NRF_GRTC_RTCOUNTER_CCH_MASK GRTC_RTCOMPAREH_VALUE_Msk
196
197 #if defined(GRTC_SYSCOUNTERH_OVERFLOW_Msk) || defined(__NRFX_DOXYGEN__)
198 /** @brief Bitmask of the OVERFLOW bit. */
199 #define NRF_GRTC_SYSCOUNTERH_OVERFLOW_MASK GRTC_SYSCOUNTERH_OVERFLOW_Msk
200 #else
201 #define NRF_GRTC_SYSCOUNTERH_OVERFLOW_MASK GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Msk
202 #endif
203
204 #if defined(GRTC_SYSCOUNTERH_BUSY_Msk) || defined(__NRFX_DOXYGEN__)
205 /** @brief Bitmask of the BUSY bit. */
206 #define NRF_GRTC_SYSCOUNTERH_BUSY_MASK GRTC_SYSCOUNTERH_BUSY_Msk
207 #else
208 #define NRF_GRTC_SYSCOUNTERH_BUSY_MASK GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Msk
209 #endif
210
211 /** @brief Maximum value of TIMEOUT register content. */
212 #define NRF_GRTC_TIMEOUT_MAX_VALUE (GRTC_TIMEOUT_VALUE_Msk >> GRTC_TIMEOUT_VALUE_Pos)
213
214 /** @brief Maximum value of WAKETIME register content. */
215 #define NRF_GRTC_WAKETIME_MAX_VALUE (GRTC_WAKETIME_VALUE_Msk >> GRTC_WAKETIME_VALUE_Pos)
216
217 /** @brief Maximum value of CLKFASTDIV register content. */
218 #define NRF_GRTC_CLKCFG_CLKFASTDIV_MAX_VALUE GRTC_CLKCFG_CLKFASTDIV_Max
219
220 /** @brief Macro for creating the interrupt bitmask for the specified compare channel. */
221 #define NRF_GRTC_CHANNEL_INT_MASK(ch) ((uint32_t)(NRF_GRTC_INT_COMPARE0_MASK) << (ch))
222
223 /** @brief Main channel that can be used only by the owner of GRTC. */
224 #if defined(LUMOS_XXAA)
225 #if defined(ISA_RISCV)
226 #define NRF_GRTC_MAIN_CC_CHANNEL 4
227 #else
228 #define NRF_GRTC_MAIN_CC_CHANNEL 0
229 #endif
230 #else
231 #define NRF_GRTC_MAIN_CC_CHANNEL 1
232 #endif
233
234 /** @brief Bitmask of interrupt enable. */
235 #define NRF_GRTC_INTEN_MASK NRFX_BIT_MASK(GRTC_CC_MaxCount)
236
237 /** @brief Mask for all channels represented by CC channels. */
238 #define NRF_GRTC_SYSCOUNTER_ALL_CHANNELS_INT_MASK \
239 ((uint32_t)(((1 << NRF_GRTC_SYSCOUNTER_CC_COUNT) - 1) << GRTC_INTEN0_COMPARE0_Pos))
240
241 /** @brief GRTC tasks. */
242 typedef enum
243 {
244 #if NRF_GRTC_HAS_EXTENDED
245 NRF_GRTC_TASK_START = offsetof(NRF_GRTC_Type, TASKS_START), /**< Start. */
246 NRF_GRTC_TASK_STOP = offsetof(NRF_GRTC_Type, TASKS_STOP), /**< Stop. */
247 NRF_GRTC_TASK_CLEAR = offsetof(NRF_GRTC_Type, TASKS_CLEAR), /**< Clear. */
248 #endif
249 #if NRF_GRTC_HAS_PWM
250 NRF_GRTC_TASK_PWM_START = offsetof(NRF_GRTC_Type, TASKS_PWMSTART), /**< Start the PWM. */
251 NRF_GRTC_TASK_PWM_STOP = offsetof(NRF_GRTC_Type, TASKS_PWMSTOP), /**< Stop the PWM. */
252 #endif // NRF_GRTC_HAS_PWM
253 NRF_GRTC_TASK_CAPTURE_0 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[0]), /**< Capture the counter value on channel 0. */
254 NRF_GRTC_TASK_CAPTURE_1 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[1]), /**< Capture the counter value on channel 1. */
255 NRF_GRTC_TASK_CAPTURE_2 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[2]), /**< Capture the counter value on channel 2. */
256 NRF_GRTC_TASK_CAPTURE_3 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[3]), /**< Capture the counter value on channel 3. */
257 NRF_GRTC_TASK_CAPTURE_4 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[4]), /**< Capture the counter value on channel 4. */
258 NRF_GRTC_TASK_CAPTURE_5 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[5]), /**< Capture the counter value on channel 5. */
259 NRF_GRTC_TASK_CAPTURE_6 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[6]), /**< Capture the counter value on channel 6. */
260 NRF_GRTC_TASK_CAPTURE_7 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[7]), /**< Capture the counter value on channel 7. */
261 NRF_GRTC_TASK_CAPTURE_8 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[8]), /**< Capture the counter value on channel 8. */
262 NRF_GRTC_TASK_CAPTURE_9 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[9]), /**< Capture the counter value on channel 9. */
263 NRF_GRTC_TASK_CAPTURE_10 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[10]), /**< Capture the counter value on channel 10. */
264 NRF_GRTC_TASK_CAPTURE_11 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[11]), /**< Capture the counter value on channel 11. */
265 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 12
266 NRF_GRTC_TASK_CAPTURE_12 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[12]), /**< Capture the counter value on channel 12. */
267 NRF_GRTC_TASK_CAPTURE_13 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[13]), /**< Capture the counter value on channel 13. */
268 NRF_GRTC_TASK_CAPTURE_14 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[14]), /**< Capture the counter value on channel 14. */
269 NRF_GRTC_TASK_CAPTURE_15 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[15]), /**< Capture the counter value on channel 15. */
270 #endif
271 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 16
272 NRF_GRTC_TASK_CAPTURE_16 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[16]), /**< Capture the counter value on channel 16. */
273 NRF_GRTC_TASK_CAPTURE_17 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[17]), /**< Capture the counter value on channel 17. */
274 #endif
275 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 18
276 NRF_GRTC_TASK_CAPTURE_18 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[18]), /**< Capture the counter value on channel 18. */
277 #endif
278 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 19
279 NRF_GRTC_TASK_CAPTURE_19 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[19]), /**< Capture the counter value on channel 19. */
280 #endif
281 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 20
282 NRF_GRTC_TASK_CAPTURE_20 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[20]), /**< Capture the counter value on channel 20. */
283 NRF_GRTC_TASK_CAPTURE_21 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[21]), /**< Capture the counter value on channel 21. */
284 NRF_GRTC_TASK_CAPTURE_22 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[22]), /**< Capture the counter value on channel 22. */
285 NRF_GRTC_TASK_CAPTURE_23 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[23]), /**< Capture the counter value on channel 23. */
286 #endif
287 } nrf_grtc_task_t;
288
289 /** @brief GRTC events. */
290 typedef enum
291 {
292 NRF_GRTC_EVENT_COMPARE_0 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[0]), /**< Compare 0 event. */
293 NRF_GRTC_EVENT_COMPARE_1 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[1]), /**< Compare 1 event. */
294 NRF_GRTC_EVENT_COMPARE_2 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[2]), /**< Compare 2 event. */
295 NRF_GRTC_EVENT_COMPARE_3 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[3]), /**< Compare 3 event. */
296 NRF_GRTC_EVENT_COMPARE_4 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[4]), /**< Compare 4 event. */
297 NRF_GRTC_EVENT_COMPARE_5 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[5]), /**< Compare 5 event. */
298 NRF_GRTC_EVENT_COMPARE_6 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[6]), /**< Compare 6 event. */
299 NRF_GRTC_EVENT_COMPARE_7 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[7]), /**< Compare 7 event. */
300 NRF_GRTC_EVENT_COMPARE_8 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[8]), /**< Compare 8 event. */
301 NRF_GRTC_EVENT_COMPARE_9 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[9]), /**< Compare 9 event. */
302 NRF_GRTC_EVENT_COMPARE_10 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[10]), /**< Compare 10 event. */
303 NRF_GRTC_EVENT_COMPARE_11 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[11]), /**< Compare 11 event. */
304 NRF_GRTC_EVENT_COMPARE_12 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[12]), /**< Compare 12 event. */
305 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 12
306 NRF_GRTC_EVENT_COMPARE_13 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[13]), /**< Compare 13 event. */
307 NRF_GRTC_EVENT_COMPARE_14 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[14]), /**< Compare 14 event. */
308 NRF_GRTC_EVENT_COMPARE_15 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[15]), /**< Compare 15 event. */
309 #endif
310 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 16
311 NRF_GRTC_EVENT_COMPARE_16 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[16]), /**< Compare 16 event. */
312 NRF_GRTC_EVENT_COMPARE_17 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[17]), /**< Compare 17 event. */
313 #endif
314 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 18
315 NRF_GRTC_EVENT_COMPARE_18 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[18]), /**< Compare 18 event. */
316 #endif
317 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 19
318 NRF_GRTC_EVENT_COMPARE_19 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[19]), /**< Compare 19 event. */
319 #endif
320 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 20
321 NRF_GRTC_EVENT_COMPARE_20 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[20]), /**< Compare 20 event. */
322 NRF_GRTC_EVENT_COMPARE_21 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[21]), /**< Compare 21 event. */
323 NRF_GRTC_EVENT_COMPARE_22 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[22]), /**< Compare 22 event. */
324 NRF_GRTC_EVENT_COMPARE_23 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[23]), /**< Compare 23 event. */
325 #endif
326 #if NRF_GRTC_HAS_RTCOUNTER
327 NRF_GRTC_EVENT_RTCOMPARE = offsetof(NRF_GRTC_Type, EVENTS_RTCOMPARE), /**< RTCOUNTER compare event. */
328 NRF_GRTC_EVENT_RTCOMPARESYNC = offsetof(NRF_GRTC_Type, EVENTS_RTCOMPARESYNC), /**< RTCOUNTER synchronized compare event. */
329 #endif
330 #if NRF_GRTC_HAS_SYSCOUNTERVALID
331 NRF_GRTC_EVENT_SYSCOUNTERVALID = offsetof(NRF_GRTC_Type, EVENTS_SYSCOUNTERVALID), /**< SYSCOUNTER value valid event. */
332 #endif
333 #if NRF_GRTC_HAS_PWM
334 NRF_GRTC_EVENT_PWM_PERIOD_END = offsetof(NRF_GRTC_Type, EVENTS_PWMPERIODEND), /**< End of PWM period event. */
335 #endif // NRF_GRTC_HAS_PWM
336 } nrf_grtc_event_t;
337
338 #if NRF_GRTC_HAS_RTCOUNTER
339 /** @brief Types of GRTC shortcuts. */
340 typedef enum
341 {
342 NRF_GRTC_SHORT_RTCOMPARE_CLEAR_MASK = GRTC_SHORTS_RTCOMPARE_CLEAR_Msk, /**< Shortcut between RTCOMPARE event and CLEAR task. */
343 } nrf_grtc_short_mask_t;
344 #endif
345
346 /** @brief Types of GRTC CC references. */
347 typedef enum
348 {
349 NRF_GRTC_CC_ADD_REFERENCE_SYSCOUNTER = GRTC_CC_CCADD_REFERENCE_SYSCOUNTER, /**< The SYSCOUNTER register's content will be used as the reference. */
350 NRF_GRTC_CC_ADD_REFERENCE_CC = GRTC_CC_CCADD_REFERENCE_CC /**< The CC[n] register's content will be used as the reference. */
351 } nrf_grtc_cc_add_reference_t;
352
353 /** @brief GRTC interrupts. */
354 typedef enum
355 {
356 NRF_GRTC_INT_COMPARE0_MASK = GRTC_INTENSET0_COMPARE0_Msk, /**< GRTC interrupt from compare event on channel 0. */
357 NRF_GRTC_INT_COMPARE1_MASK = GRTC_INTENSET0_COMPARE1_Msk, /**< GRTC interrupt from compare event on channel 1. */
358 NRF_GRTC_INT_COMPARE2_MASK = GRTC_INTENSET0_COMPARE2_Msk, /**< GRTC interrupt from compare event on channel 2. */
359 NRF_GRTC_INT_COMPARE3_MASK = GRTC_INTENSET0_COMPARE3_Msk, /**< GRTC interrupt from compare event on channel 3. */
360 NRF_GRTC_INT_COMPARE4_MASK = GRTC_INTENSET0_COMPARE4_Msk, /**< GRTC interrupt from compare event on channel 4. */
361 NRF_GRTC_INT_COMPARE5_MASK = GRTC_INTENSET0_COMPARE5_Msk, /**< GRTC interrupt from compare event on channel 5. */
362 NRF_GRTC_INT_COMPARE6_MASK = GRTC_INTENSET0_COMPARE6_Msk, /**< GRTC interrupt from compare event on channel 6. */
363 NRF_GRTC_INT_COMPARE7_MASK = GRTC_INTENSET0_COMPARE7_Msk, /**< GRTC interrupt from compare event on channel 7. */
364 NRF_GRTC_INT_COMPARE8_MASK = GRTC_INTENSET0_COMPARE8_Msk, /**< GRTC interrupt from compare event on channel 8. */
365 NRF_GRTC_INT_COMPARE9_MASK = GRTC_INTENSET0_COMPARE9_Msk, /**< GRTC interrupt from compare event on channel 9. */
366 NRF_GRTC_INT_COMPARE10_MASK = GRTC_INTENSET0_COMPARE10_Msk, /**< GRTC interrupt from compare event on channel 10. */
367 NRF_GRTC_INT_COMPARE11_MASK = GRTC_INTENSET0_COMPARE11_Msk, /**< GRTC interrupt from compare event on channel 11. */
368 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 12
369 NRF_GRTC_INT_COMPARE12_MASK = GRTC_INTENSET0_COMPARE12_Msk, /**< GRTC interrupt from compare event on channel 12. */
370 NRF_GRTC_INT_COMPARE13_MASK = GRTC_INTENSET0_COMPARE13_Msk, /**< GRTC interrupt from compare event on channel 13. */
371 NRF_GRTC_INT_COMPARE14_MASK = GRTC_INTENSET0_COMPARE14_Msk, /**< GRTC interrupt from compare event on channel 14. */
372 NRF_GRTC_INT_COMPARE15_MASK = GRTC_INTENSET0_COMPARE15_Msk, /**< GRTC interrupt from compare event on channel 15. */
373 #endif
374 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 16
375 NRF_GRTC_INT_COMPARE16_MASK = GRTC_INTENSET0_COMPARE16_Msk, /**< GRTC interrupt from compare event on channel 16. */
376 NRF_GRTC_INT_COMPARE17_MASK = GRTC_INTENSET0_COMPARE17_Msk, /**< GRTC interrupt from compare event on channel 17. */
377 #endif
378 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 18
379 NRF_GRTC_INT_COMPARE18_MASK = GRTC_INTENSET0_COMPARE18_Msk, /**< GRTC interrupt from compare event on channel 18. */
380 #endif
381 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 19
382 NRF_GRTC_INT_COMPARE19_MASK = GRTC_INTENSET0_COMPARE19_Msk, /**< GRTC interrupt from compare event on channel 19. */
383 #endif
384 #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 20
385 NRF_GRTC_INT_COMPARE20_MASK = GRTC_INTENSET0_COMPARE20_Msk, /**< GRTC interrupt from compare event on channel 20. */
386 NRF_GRTC_INT_COMPARE21_MASK = GRTC_INTENSET0_COMPARE21_Msk, /**< GRTC interrupt from compare event on channel 21. */
387 NRF_GRTC_INT_COMPARE22_MASK = GRTC_INTENSET0_COMPARE22_Msk, /**< GRTC interrupt from compare event on channel 22. */
388 NRF_GRTC_INT_COMPARE23_MASK = GRTC_INTENSET0_COMPARE23_Msk, /**< GRTC interrupt from compare event on channel 23. */
389 #endif
390 #if NRF_GRTC_HAS_RTCOUNTER
391 NRF_GRTC_INT_RTCOMPARE_MASK = GRTC_INTENSET0_RTCOMPARE_Msk, /**< GRTC interrupt from RTCOUNTER compare event. */
392 NRF_GRTC_INT_RTCOMPARESYNC_MASK = GRTC_INTENSET0_RTCOMPARESYNC_Msk, /**< GRTC interrupt from RTCOUNTER synchronized compare event. */
393 #endif
394 #if NRF_GRTC_HAS_EXTENDED && NRF_GRTC_HAS_SYSCOUNTERVALID
395 NRF_GRTC_INT_SYSCOUNTERVALID_MASK = GRTC_INTENSET0_SYSCOUNTERVALID_Msk, /**< GRTC interrupt from SYSCOUNTER valid event. */
396 #endif
397 } nrf_grtc_int_mask_t;
398
399 #if NRF_GRTC_HAS_CLKOUT
400 /** @brief Configuration of clock output. */
401 typedef enum
402 {
403 NRF_GRTC_CLKOUT_32K = GRTC_CLKOUT_CLKOUT32K_Msk, /**< Enable 32K clock output on pin. */
404 NRF_GRTC_CLKOUT_FAST = GRTC_CLKOUT_CLKOUTFAST_Msk, /**< Enable fast clock output on pin. */
405 } nrf_grtc_clkout_t;
406 #endif
407
408 #if NRF_GRTC_HAS_CLKSEL
409 /** @brief Configuration of the GRTC clock source selection. */
410 typedef enum
411 {
412 NRF_GRTC_CLKSEL_LFXO = GRTC_CLKCFG_CLKSEL_LFXO, /**< LFXO oscillator as the clock source. */
413 NRF_GRTC_CLKSEL_LFCLK = GRTC_CLKCFG_CLKSEL_SystemLFCLK, /**< System LFCLK as the clock source. */
414 #if NRF_GRTC_HAS_CLKSEL_LFLPRC
415 NRF_GRTC_CLKSEL_LFLPRC = GRTC_CLKCFG_CLKSEL_LFLPRC, /**< System LFLPRC as the clock source. */
416 #endif
417 } nrf_grtc_clksel_t;
418 #endif
419
420 /**
421 * @brief Function for setting the compare value of channel for the SYSCOUNTER.
422 *
423 * @note The corresponding event is automatically disabled by hardware during the operation.
424 *
425 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
426 * @param[in] cc_channel The specified capture/compare channel.
427 * @param[in] cc_value Compare value to be set in 1 MHz units.
428 */
429 NRF_STATIC_INLINE void nrf_grtc_sys_counter_cc_set(NRF_GRTC_Type * p_reg,
430 uint8_t cc_channel,
431 uint64_t cc_value);
432
433 /**
434 * @brief Function for getting the capture/compare value of channel for the SYSCOUNTER.
435 *
436 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
437 * @param[in] cc_channel The specified capture/compare channel.
438 *
439 * @return Value from the specified capture/compare register in 1MHz units.
440 */
441 NRF_STATIC_INLINE uint64_t nrf_grtc_sys_counter_cc_get(NRF_GRTC_Type const * p_reg,
442 uint8_t cc_channel);
443
444 /**
445 * @brief Function for setting the value to be added to capture/compare register for
446 * the SYSCOUNTER.
447 *
448 * @note There are two available configurations of adding operation:
449 * When @p reference value equals @ref NRF_GRTC_CC_ADD_REFERENCE_SYSCOUNTER then
450 * the final value of capture/compare register is a sum of SYSCOUNTER current value
451 * and @p value.
452 * When @p reference value equals @ref NRF_GRTC_CC_ADD_REFERENCE_CC then
453 * the final value of capture/compare register is a sum of current capture/compare
454 * value and @p value.
455 * If the capture/compare register overflows after this write, then the corresponding event
456 * is generated immediately.
457 *
458 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
459 * @param[in] cc_channel The specified capture/compare channel.
460 * @param[in] value Value to be added in 1 MHz units.
461 * @param[in] reference Configuration of adding mode.
462 */
463 NRF_STATIC_INLINE void nrf_grtc_sys_counter_cc_add_set(NRF_GRTC_Type * p_reg,
464 uint8_t cc_channel,
465 uint32_t value,
466 nrf_grtc_cc_add_reference_t reference);
467
468 #if NRF_GRTC_HAS_RTCOUNTER
469 /**
470 * @brief Function for setting a compare value for the RTCOUNTER.
471 *
472 * @note The internal synchronization mechanism ensures that the desired value will be properly
473 * latched by the GRTC. However when @p sync parameter is true then the process of capturing
474 * the value lasts up to two 32 kHz cycles.
475 * If the @p sync parameter is false then the capturing the value will occur on the
476 * following rising edge of 32 kHz clock. In this case it is user's responsibility
477 * to execute the function between the 32 kHz rising edges.
478 *
479 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
480 * @param[in] cc_value Compare value to be set in 32 kHz units.
481 * @param[in] sync True if the internal synchronization mechanism shall be used,
482 * false otherwise.
483 */
484 NRF_STATIC_INLINE void nrf_grtc_rt_counter_cc_set(NRF_GRTC_Type * p_reg,
485 uint64_t cc_value,
486 bool sync);
487
488 /**
489 * @brief Function for returning the compare value for the RTCOUNTER.
490 *
491 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
492 *
493 * @return Value from the capture/compare register in 32 kHz units.
494 */
495 NRF_STATIC_INLINE uint64_t nrf_grtc_rt_counter_cc_get(NRF_GRTC_Type const * p_reg);
496 #endif // NRF_GRTC_HAS_RTCOUNTER
497
498 /**
499 * @brief Function for enabling specified interrupts.
500 *
501 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
502 * @param[in] mask Mask of interrupts to be enabled.
503 * Use @ref nrf_grtc_int_mask_t values for bit masking.
504 */
505 NRF_STATIC_INLINE void nrf_grtc_int_enable(NRF_GRTC_Type * p_reg, uint32_t mask);
506
507 /**
508 * @brief Function for disabling specified interrupts.
509 *
510 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
511 * @param[in] mask Mask of interrupts to be disabled.
512 * Use @ref nrf_grtc_int_mask_t values for bit masking.
513 */
514 NRF_STATIC_INLINE void nrf_grtc_int_disable(NRF_GRTC_Type * p_reg, uint32_t mask);
515
516 /**
517 * @brief Function for checking if the specified interrupts are enabled.
518 *
519 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
520 * @param[in] mask Mask of interrupts to be checked.
521 * Use @ref nrf_grtc_int_mask_t values for bit masking.
522 *
523 * @return Mask of enabled interrupts.
524 */
525 NRF_STATIC_INLINE uint32_t nrf_grtc_int_enable_check(NRF_GRTC_Type const * p_reg, uint32_t mask);
526
527 /**
528 * @brief Function for retrieving the state of pending interrupts.
529 *
530 * @note States of pending interrupt are saved as a bitmask.
531 * One set at particular position means that interrupt for event is pending.
532 *
533 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
534 *
535 * @return Bitmask with information about pending interrupts.
536 * Use @ref nrf_grtc_int_mask_t values for bit masking.
537 */
538 NRF_STATIC_INLINE uint32_t nrf_grtc_int_pending_get(NRF_GRTC_Type const * p_reg);
539
540 #if NRF_GRTC_HAS_INT_GROUPS
541 /**
542 * @brief Function for enabling interrupts in the specified group.
543 *
544 * @note Not all @p group_idx might be valid.
545 * Refer to the Product Specification for more information.
546 *
547 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
548 * @param[in] group_idx Index of interrupt group to be enabled.
549 * @param[in] mask Mask of interrupts to be enabled.
550 * Use @ref nrf_grtc_int_mask_t values for bit masking.
551 */
552 NRF_STATIC_INLINE void nrf_grtc_int_group_enable(NRF_GRTC_Type * p_reg,
553 uint8_t group_idx,
554 uint32_t mask);
555
556 /**
557 * @brief Function for disabling interrupts in the specified group.
558 *
559 * @note Not all @p group_idx might be valid.
560 * Refer to the Product Specification for more information.
561 *
562 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
563 * @param[in] group_idx Index of interrupt group to be disabled.
564 * @param[in] mask Mask of interrupts to be disabled.
565 * Use @ref nrf_grtc_int_mask_t values for bit masking.
566 */
567 NRF_STATIC_INLINE void nrf_grtc_int_group_disable(NRF_GRTC_Type * p_reg,
568 uint8_t group_idx,
569 uint32_t mask);
570
571 /**
572 * @brief Function for checking if the specified interrupts from a given group are enabled.
573 *
574 * @note Not all @p group_idx might be valid.
575 * Refer to the Product Specification for more information.
576 *
577 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
578 * @param[in] group_idx Index of interrupt group to be checked.
579 * @param[in] mask Mask of interrupts to be checked.
580 * Use @ref nrf_grtc_int_mask_t values for bit masking.
581 *
582 * @return Mask of enabled interrupts.
583 */
584 NRF_STATIC_INLINE uint32_t nrf_grtc_int_group_enable_check(NRF_GRTC_Type const * p_reg,
585 uint8_t group_idx,
586 uint32_t mask);
587 #endif // NRF_GRTC_HAS_INT_GROUPS
588
589 #if NRF_GRTC_HAS_PWM
590 /**
591 * @brief Function for enabling events.
592 *
593 * @note Only specific events can be individually enabled or disabled.
594 *
595 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
596 * @param[in] mask Mask of event flags to be enabled.
597 */
598 NRF_STATIC_INLINE void nrf_grtc_event_enable(NRF_GRTC_Type * p_reg, uint32_t mask);
599
600 /**
601 * @brief Function for disabling events.
602 *
603 * @note Only specific events can be individually enabled or disabled.
604 *
605 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
606 * @param[in] mask Mask of event flags to be disabled.
607 */
608 NRF_STATIC_INLINE void nrf_grtc_event_disable(NRF_GRTC_Type * p_reg, uint32_t mask);
609 #endif // NRF_GRTC_HAS_PWM
610
611 #if NRF_GRTC_HAS_EXTENDED
612 /**
613 * @brief Function for enabling the specified shortcuts.
614 *
615 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
616 * @param[in] mask Bitmask of shortcuts to be enabled.
617 */
618 NRF_STATIC_INLINE void nrf_grtc_shorts_enable(NRF_GRTC_Type * p_reg, uint32_t mask);
619
620 /**
621 * @brief Function for disabling the specified shortcuts.
622 *
623 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
624 * @param[in] mask Bitmask of shortcuts to be disabled.
625 */
626 NRF_STATIC_INLINE void nrf_grtc_shorts_disable(NRF_GRTC_Type * p_reg, uint32_t mask);
627
628 /**
629 * @brief Function for setting the specified shortcuts.
630 *
631 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
632 * @param[in] mask Bitmask of shortcuts to be set.
633 */
634 NRF_STATIC_INLINE void nrf_grtc_shorts_set(NRF_GRTC_Type * p_reg, uint32_t mask);
635 #endif // NRF_GRTC_HAS_EXTENDED
636
637 /**
638 * @brief Function for setting the subscribe configuration for a given
639 * GRTC task.
640 *
641 * @note Not every task has its corresponding subscribe register.
642 * Refer to the Product Specification for more information.
643 *
644 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
645 * @param[in] task Task for which to set the configuration.
646 * @param[in] channel Channel through which to subscribe events.
647 */
648 NRF_STATIC_INLINE void nrf_grtc_subscribe_set(NRF_GRTC_Type * p_reg,
649 nrf_grtc_task_t task,
650 uint8_t channel);
651
652 /**
653 * @brief Function for clearing the subscribe configuration for a given
654 * GRTC task.
655 *
656 * @note Not every task has its corresponding subscribe register.
657 * Refer to the Product Specification for more information.
658 *
659 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
660 * @param[in] task Task for which to clear the configuration.
661 */
662 NRF_STATIC_INLINE void nrf_grtc_subscribe_clear(NRF_GRTC_Type * p_reg,
663 nrf_grtc_task_t task);
664
665 /**
666 * @brief Function for setting the publish configuration for a given
667 * GRTC event.
668 *
669 * @note Not every event has its corresponding publish register.
670 * Refer to the Product Specification for more information.
671 *
672 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
673 * @param[in] event Event for which to set the configuration.
674 * @param[in] channel Channel through which to publish the event.
675 */
676 NRF_STATIC_INLINE void nrf_grtc_publish_set(NRF_GRTC_Type * p_reg,
677 nrf_grtc_event_t event,
678 uint8_t channel);
679
680 /**
681 * @brief Function for clearing the publish configuration for a given
682 * GRTC event.
683 *
684 * @note Not every event has its corresponding publish register.
685 * Refer to the Product Specification for more information.
686 *
687 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
688 * @param[in] event Event for which to clear the configuration.
689 */
690 NRF_STATIC_INLINE void nrf_grtc_publish_clear(NRF_GRTC_Type * p_reg,
691 nrf_grtc_event_t event);
692
693 /**
694 * @brief Function for retrieving the state of the GRTC event.
695 *
696 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
697 * @param[in] event Event to be checked.
698 *
699 * @retval true The event has been generated.
700 * @retval false The event has not been generated.
701 */
702 NRF_STATIC_INLINE bool nrf_grtc_event_check(NRF_GRTC_Type const * p_reg, nrf_grtc_event_t event);
703
704 /**
705 * @brief Function for clearing an event.
706 *
707 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
708 * @param[in] event Event to be cleared.
709 */
710 NRF_STATIC_INLINE void nrf_grtc_event_clear(NRF_GRTC_Type * p_reg, nrf_grtc_event_t event);
711
712 #if NRF_GRTC_HAS_RTCOUNTER
713 /**
714 * @brief Function for returning the lower 32-bits of RTCOUNTER value.
715 *
716 * @note The whole RTCOUNTER value is latched when @ref nrf_grtc_rt_counter_low_get function
717 * is executed. Thus @ref nrf_grtc_rt_counter_low_get must be executed before calling
718 * @ref nrf_grtc_rt_counter_high_get.
719 *
720 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
721 *
722 * @return Lower part of RTCOUNTER value.
723 */
724 NRF_STATIC_INLINE uint32_t nrf_grtc_rt_counter_low_get(NRF_GRTC_Type const * p_reg);
725
726 /**
727 * @brief Function for returning the higher 32-bits of RTCOUNTER value.
728 *
729 * @note The whole RTCOUNTER value is latched when @ref nrf_grtc_rt_counter_low_get function
730 * is executed. Thus @ref nrf_grtc_rt_counter_low_get must be executed before calling
731 * @ref nrf_grtc_rt_counter_high_get.
732 *
733 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
734 *
735 * @return Higher part of RTCOUNTER value.
736 */
737 NRF_STATIC_INLINE uint32_t nrf_grtc_rt_counter_high_get(NRF_GRTC_Type const * p_reg);
738 #endif // NRF_GRTC_HAS_RTCOUNTER
739
740 /**
741 * @brief Function for returning the lower 32-bits of SYSCOUNTER value.
742 *
743 * @note @ref nrf_grtc_sys_counter_low_get must be executed before calling
744 * @ref nrf_grtc_sys_counter_high_get. In addition, after this,
745 * @ref nrf_grtc_sys_counter_overflow_check should be called. If it retuns true,
746 * whole procedure should be repeated.
747 *
748 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
749 *
750 * @return Lower part of SYSCOUNTER value.
751 */
752 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_low_get(NRF_GRTC_Type const * p_reg);
753
754 /**
755 * @brief Function for returning the higher 32-bits of SYSCOUNTER value.
756 *
757 * @note @ref nrf_grtc_sys_counter_low_get must be executed before calling
758 * @ref nrf_grtc_sys_counter_high_get. In addition, after this,
759 * @ref nrf_grtc_sys_counter_overflow_check should be called. If it retuns true,
760 * whole procedure should be repeated.
761 *
762 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
763 *
764 * @return Higher part SYSCOUNTER value.
765 */
766 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_high_get(NRF_GRTC_Type const * p_reg);
767
768 /**
769 * @brief Function for returning the 64-bit SYSCOUNTER value.
770 *
771 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
772 *
773 * @return SYSCOUNTER value.
774 */
775 NRF_STATIC_INLINE uint64_t nrf_grtc_sys_counter_get(NRF_GRTC_Type const * p_reg);
776
777 /**
778 * @brief Function for checking whether the lower 32-bits of SYSCOUNTER overflowed after
779 * last execution of @ref nrf_grtc_sys_counter_low_get.
780 *
781 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
782 *
783 * @retval True if the lower 32-bits of SYSCOUNTER overflowed, false otherwise.
784 */
785 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_overflow_check(NRF_GRTC_Type const * p_reg);
786
787 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
788 /**
789 * @brief Function for returning the 64-bit SYSCOUNTER value of the specified index.
790 *
791 * @note Not all @p index might be valid.
792 * Refer to the Product Specification for more information.
793 *
794 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
795 * @param[in] index Index of SYSCOUNTER value to be read.
796 *
797 * @return SYSCOUNTER value of specified index.
798 */
799 NRF_STATIC_INLINE uint64_t nrf_grtc_sys_counter_indexed_get(NRF_GRTC_Type const * p_reg,
800 uint8_t index);
801
802 /**
803 * @brief Function for setting the request to keep the specified SYSCOUNTER channel active.
804 *
805 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
806 * @param[in] enable True if the SYSCOUNTER channel is to be kept active, false otherwise.
807 */
808 NRF_STATIC_INLINE void nrf_grtc_sys_counter_active_set(NRF_GRTC_Type * p_reg, bool enable);
809
810 /**
811 * @brief Function for checking whether the specified SYSCOUNTER channel is requested to remain active.
812 *
813 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
814 *
815 * @retval True if SYSCOUNTER channel is requested to remain active, false otherwise.
816 */
817 NRF_STATIC_INLINE
818 bool nrf_grtc_sys_counter_active_check(NRF_GRTC_Type const * p_reg);
819 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
820
821 /**
822 * @brief Function for returning the address of an event.
823 *
824 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
825 * @param[in] event Requested event.
826 *
827 * @return Address of the requested event register.
828 */
829 NRF_STATIC_INLINE uint32_t nrf_grtc_event_address_get(NRF_GRTC_Type const * p_reg,
830 nrf_grtc_event_t event);
831
832 /**
833 * @brief Function for returning the address of a task.
834 *
835 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
836 * @param[in] task Requested task.
837 *
838 * @return Address of the requested task register.
839 */
840 NRF_STATIC_INLINE uint32_t nrf_grtc_task_address_get(NRF_GRTC_Type const * p_reg,
841 nrf_grtc_task_t task);
842
843 /**
844 * @brief Function for starting a task.
845 *
846 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
847 * @param[in] task Requested task.
848 */
849 NRF_STATIC_INLINE void nrf_grtc_task_trigger(NRF_GRTC_Type * p_reg, nrf_grtc_task_t task);
850
851 /**
852 * @brief Function for getting the 1 MHz SYSCOUNTER timer capture task associated with the
853 * specified channel.
854 *
855 * @param[in] cc_channel Capture channel.
856 *
857 * @return Capture task.
858 */
859 NRF_STATIC_INLINE nrf_grtc_task_t nrf_grtc_sys_counter_capture_task_get(uint8_t cc_channel);
860
861 /**
862 * @brief Function for enabling SYSCOUNTER compare event.
863 *
864 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
865 * @param[in] cc_channel Channel number of compare event to be enabled.
866 */
867 NRF_STATIC_INLINE void nrf_grtc_sys_counter_compare_event_enable(NRF_GRTC_Type * p_reg,
868 uint8_t cc_channel);
869
870 /**
871 * @brief Function for disabling SYSCOUNTER compare event.
872 *
873 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
874 * @param[in] cc_channel Channel number of compare event to be disabled.
875 */
876 NRF_STATIC_INLINE void nrf_grtc_sys_counter_compare_event_disable(NRF_GRTC_Type * p_reg,
877 uint8_t cc_channel);
878
879 /**
880 * @brief Function for getting the SYSCOUNTER compare event associated with the specified
881 * compare cc_channel.
882 *
883 * @param[in] cc_channel Compare channel number.
884 *
885 * @return Requested compare event.
886 */
887 NRF_STATIC_INLINE nrf_grtc_event_t nrf_grtc_sys_counter_compare_event_get(uint8_t cc_channel);
888
889 /**
890 * @brief Function for checking whether the specified capture/compare channel is enabled.
891 *
892 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
893 * @param[in] cc_channel Channel to be checked.
894 *
895 * @retval true Specified channel is enabled.
896 * @retval false Specified channel is disabled.
897 */
898 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_cc_enable_check(NRF_GRTC_Type const * p_reg,
899 uint8_t cc_channel);
900
901 #if NRF_GRTC_HAS_EXTENDED
902 /**
903 * @brief Function for setting the SYSCOUNTER.
904 *
905 * @note When the SYSCOUNTER is disabled the GRTC uses RTCOUNTER by default.
906 *
907 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
908 * @param[in] enable True if SYSCOUNTER is to be enabled, false otherwise.
909 */
910 NRF_STATIC_INLINE void nrf_grtc_sys_counter_set(NRF_GRTC_Type * p_reg, bool enable);
911
912 /**
913 * @brief Function for setting automatic mode for the SYSCOUNTER.
914 *
915 * @note When @p enable is false then the SYSCOUNTER remains active when KEEPRUNNING is set,
916 * or any task register, INT register or SYSCOUNTER register is being accessed.
917 * When @p enable is true then in addition the SYSCOUNTER remains active when
918 * any local CPU that is not sleeping keeps the SYSCOUNTER active.
919 *
920 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
921 * @param[in] enable True if the automatic mode is to be enabled, false otherwise.
922 */
923 NRF_STATIC_INLINE void nrf_grtc_sys_counter_auto_mode_set(NRF_GRTC_Type * p_reg, bool enable);
924
925 /**
926 * @brief Function for checking whether the SYSCOUNTER has automatic mode enabled.
927 *
928 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
929 *
930 * @return True Automatic mode is enabled.
931 * @return False Automatic mode is disabled.
932 */
933 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_auto_mode_check(NRF_GRTC_Type * p_reg);
934 #endif // NRF_GRTC_HAS_EXTENDED
935
936 /**
937 * @brief Function for checking whether the SYSCOUNTER is in active state.
938 *
939 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
940 *
941 * @retval True if the SYSCOUNTER is active, false otherwise.
942 */
943 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_check(NRF_GRTC_Type const * p_reg);
944
945 #if NRF_GRTC_HAS_KEEPRUNNING
946 /**
947 * @brief Function for setting the request to keep the SYSCOUNTER active.
948 *
949 * @note This function modifies the KEEPRUNNING register, which possesses information
950 * whether any local CPU needs keeping the SYSCOUNTER active.
951 *
952 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
953 * @param[in] enable True if the automatic mode is to be enabled, false otherwise.
954 */
955 NRF_STATIC_INLINE void nrf_grtc_sys_counter_active_state_request_set(NRF_GRTC_Type * p_reg,
956 bool enable);
957
958 /**
959 * @brief Function for checking whether the SYSCOUNTER is requested to remain active.
960 *
961 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
962 *
963 * @retval True if request for keeping the SYSCOUNTER is active, false otherwise.
964 */
965 NRF_STATIC_INLINE
966 bool nrf_grtc_sys_counter_active_state_request_check(NRF_GRTC_Type const * p_reg);
967
968 /**
969 * @brief Function for getting the domains that requested the SYSCOUNTER to remain active.
970 *
971 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
972 * @param[in] mask Domains mask.
973 *
974 * @retval Bitmask of domains that keep the SYSCOUNTER active.
975 */
976 NRF_STATIC_INLINE
977 uint32_t nrf_grtc_sys_counter_active_state_request_get(NRF_GRTC_Type const * p_reg,
978 uint32_t mask);
979 #endif // NRF_GRTC_HAS_KEEPRUNNING
980
981 #if NRF_GRTC_HAS_EXTENDED
982 /**
983 * @brief Function for setting the periodic compare event for capture/compare channel 0.
984 *
985 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
986 * @param[in] value Period value in 1 MHz units.
987 */
988 NRF_STATIC_INLINE void nrf_grtc_sys_counter_interval_set(NRF_GRTC_Type * p_reg, uint32_t value);
989
990 /**
991 * @brief Function for getting the value of interval for periodic capture/compare event
992 * for channel 0.
993 *
994 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
995 *
996 * @retval Value of the interval in 1 MHz units.
997 */
998 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_interval_get(NRF_GRTC_Type const * p_reg);
999
1000 /**
1001 * @brief Function for setting the timeout value for GRTC.
1002 *
1003 * @note Timeout between all CPUs going to sleep and stopping the SYSCOUNTER.
1004 *
1005 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1006 * @param[in] value Timeout value in 32 kHz units.
1007 */
1008 NRF_STATIC_INLINE void nrf_grtc_timeout_set(NRF_GRTC_Type * p_reg, uint32_t value);
1009
1010 /**
1011 * @brief Function for getting the value of the timeout value for GRTC.
1012 *
1013 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1014 *
1015 * @retval Value of the timeout in 32 kHz units.
1016 */
1017 NRF_STATIC_INLINE uint32_t nrf_grtc_timeout_get(NRF_GRTC_Type const * p_reg);
1018
1019 /**
1020 * @brief Function for setting the wake time value for GRTC.
1021 *
1022 * @note The wake time is maximum number of 32 kHz cycles takes to restore the APB registers
1023 * when waking from sleep state.
1024 *
1025 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1026 * @param[in] value Wake time value in 32 kHz units.
1027 */
1028 NRF_STATIC_INLINE void nrf_grtc_waketime_set(NRF_GRTC_Type * p_reg, uint32_t value);
1029
1030 /**
1031 * @brief Function for getting the wake time value.
1032 *
1033 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1034 *
1035 * @retval Value of wake time in 32 kHz units.
1036 */
1037 NRF_STATIC_INLINE uint32_t nrf_grtc_waketime_get(NRF_GRTC_Type const * p_reg);
1038 #endif // NRF_GRTC_HAS_EXTENDED
1039
1040 #if NRF_GRTC_HAS_PWM
1041 /**
1042 * @brief Function for setting the PWM compare value.
1043 *
1044 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1045 * @param[in] value PWM compare value.
1046 */
1047 NRF_STATIC_INLINE void nrf_grtc_pwm_compare_set(NRF_GRTC_Type * p_reg, uint32_t value);
1048
1049 /**
1050 * @brief Function for getting the PWM compare value.
1051 *
1052 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1053 *
1054 * @retval Value of PWM compare.
1055 */
1056 NRF_STATIC_INLINE uint32_t nrf_grtc_pwm_compare_get(NRF_GRTC_Type const * p_reg);
1057 #endif // NRF_GRTC_HAS_PWM
1058
1059 #if NRF_GRTC_HAS_CLKOUT
1060 /**
1061 * @brief Function for setting the specified clock source to be connected to output pin.
1062 *
1063 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1064 * @param[in] clkout Selected clkout source.
1065 * @param[in] enable True if the clkout source is to be enabled, false otherwise.
1066 */
1067 NRF_STATIC_INLINE void nrf_grtc_clkout_set(NRF_GRTC_Type * p_reg,
1068 nrf_grtc_clkout_t clkout,
1069 bool enable);
1070
1071 /**
1072 * @brief Function for checking whether clock source is connected to clkout pin.
1073 *
1074 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1075 * @param[in] clkout Selected clkout source.
1076 *
1077 * @retval True if the clkout source is enabled, false otherwise.
1078 */
1079 NRF_STATIC_INLINE bool nrf_grtc_clkout_enable_check(NRF_GRTC_Type const * p_reg,
1080 nrf_grtc_clkout_t clkout);
1081
1082 /**
1083 * @brief Function for setting the fast clock divisor value of clock output.
1084 *
1085 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1086 * @param[in] value Fast clock divisor value.
1087 */
1088 NRF_STATIC_INLINE void nrf_grtc_clkout_divider_set(NRF_GRTC_Type * p_reg, uint32_t value);
1089
1090 /**
1091 * @brief Function for getting the fast clock divisor value of clock output.
1092 *
1093 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1094 *
1095 * @retval Fast clock divisor value.
1096 */
1097 NRF_STATIC_INLINE uint32_t nrf_grtc_clkout_divider_get(NRF_GRTC_Type const * p_reg);
1098 #endif // NRF_GRTC_HAS_CLKOUT
1099
1100 #if NRF_GRTC_HAS_CLKSEL
1101 /**
1102 * @brief Function for setting the clock source for the GRTC low-frequency clock.
1103 *
1104 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1105 * @param[in] clksel Selected clock source.
1106 */
1107 NRF_STATIC_INLINE void nrf_grtc_clksel_set(NRF_GRTC_Type * p_reg, nrf_grtc_clksel_t clksel);
1108
1109 /**
1110 * @brief Function for getting the clock source of the GRTC low-frequency clock.
1111 *
1112 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1113 *
1114 * @return Clock source configuration.
1115 */
1116 NRF_STATIC_INLINE nrf_grtc_clksel_t nrf_grtc_clksel_get(NRF_GRTC_Type const * p_reg);
1117 #endif // NRF_GRTC_HAS_CLKSEL
1118
1119 #ifndef NRF_DECLARE_ONLY
1120
nrf_grtc_sys_counter_cc_set(NRF_GRTC_Type * p_reg,uint8_t cc_channel,uint64_t cc_value)1121 NRF_STATIC_INLINE void nrf_grtc_sys_counter_cc_set(NRF_GRTC_Type * p_reg,
1122 uint8_t cc_channel,
1123 uint64_t cc_value)
1124 {
1125 #if NRF_GRTC_HAS_EXTENDED
1126 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT);
1127 #else
1128 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT &&
1129 cc_channel > NRF_GRTC_MAIN_CC_CHANNEL);
1130 #endif
1131 uint32_t cc_h = (uint32_t)(cc_value >> 32);
1132 NRFX_ASSERT(cc_h <= NRF_GRTC_SYSCOUNTER_CCH_MASK);
1133
1134 p_reg->CC[cc_channel].CCL = (uint32_t)cc_value;
1135 p_reg->CC[cc_channel].CCH = cc_h & NRF_GRTC_SYSCOUNTER_CCH_MASK;
1136 }
1137
nrf_grtc_sys_counter_cc_get(NRF_GRTC_Type const * p_reg,uint8_t cc_channel)1138 NRF_STATIC_INLINE uint64_t nrf_grtc_sys_counter_cc_get(NRF_GRTC_Type const * p_reg,
1139 uint8_t cc_channel)
1140 {
1141 #if NRF_GRTC_HAS_EXTENDED
1142 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT);
1143 #else
1144 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT &&
1145 cc_channel > NRF_GRTC_MAIN_CC_CHANNEL);
1146 #endif
1147 uint32_t cc_h = p_reg->CC[cc_channel].CCH;
1148
1149 return (uint64_t)p_reg->CC[cc_channel].CCL | ((uint64_t)cc_h << 32);
1150 }
1151
nrf_grtc_sys_counter_cc_add_set(NRF_GRTC_Type * p_reg,uint8_t cc_channel,uint32_t value,nrf_grtc_cc_add_reference_t reference)1152 NRF_STATIC_INLINE void nrf_grtc_sys_counter_cc_add_set(NRF_GRTC_Type * p_reg,
1153 uint8_t cc_channel,
1154 uint32_t value,
1155 nrf_grtc_cc_add_reference_t reference)
1156 {
1157 #if NRF_GRTC_HAS_EXTENDED
1158 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT);
1159 #else
1160 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT &&
1161 cc_channel > NRF_GRTC_MAIN_CC_CHANNEL);
1162 #endif
1163 NRFX_ASSERT(value <= NRF_GRTC_SYSCOUNTER_CCADD_MASK);
1164
1165 p_reg->CC[cc_channel].CCADD = ((uint32_t)reference << GRTC_CC_CCADD_REFERENCE_Pos) |
1166 (value & NRF_GRTC_SYSCOUNTER_CCADD_MASK);
1167 }
1168
1169 #if NRF_GRTC_HAS_RTCOUNTER
nrf_grtc_rt_counter_cc_set(NRF_GRTC_Type * p_reg,uint64_t cc_value,bool sync)1170 NRF_STATIC_INLINE void nrf_grtc_rt_counter_cc_set(NRF_GRTC_Type * p_reg,
1171 uint64_t cc_value,
1172 bool sync)
1173 {
1174 uint32_t cc_h = (uint32_t)(cc_value >> 32);
1175 NRFX_ASSERT(cc_h <= NRF_GRTC_RTCOUNTER_CCH_MASK);
1176
1177 if (sync)
1178 {
1179 p_reg->RTCOMPARESYNCL = (uint32_t)cc_value;
1180 p_reg->RTCOMPARESYNCH = cc_h & NRF_GRTC_RTCOUNTER_CCH_MASK;
1181 }
1182 else
1183 {
1184 p_reg->RTCOMPAREL = (uint32_t)cc_value;
1185 p_reg->RTCOMPAREH = cc_h & NRF_GRTC_RTCOUNTER_CCH_MASK;
1186 }
1187 }
1188
nrf_grtc_rt_counter_cc_get(NRF_GRTC_Type const * p_reg)1189 NRF_STATIC_INLINE uint64_t nrf_grtc_rt_counter_cc_get(NRF_GRTC_Type const * p_reg)
1190 {
1191 uint32_t cc_h = p_reg->RTCOMPAREH;
1192
1193 return (uint64_t)p_reg->RTCOMPAREL | ((uint64_t)cc_h << 32);
1194 }
1195 #endif // NRF_GRTC_HAS_RTCOUNTER
1196
nrf_grtc_int_enable(NRF_GRTC_Type * p_reg,uint32_t mask)1197 NRF_STATIC_INLINE void nrf_grtc_int_enable(NRF_GRTC_Type * p_reg, uint32_t mask)
1198 {
1199 p_reg->GRTC_INTENSET = mask;
1200 }
1201
nrf_grtc_int_disable(NRF_GRTC_Type * p_reg,uint32_t mask)1202 NRF_STATIC_INLINE void nrf_grtc_int_disable(NRF_GRTC_Type * p_reg, uint32_t mask)
1203 {
1204 p_reg->GRTC_INTENCLR = mask;
1205 }
1206
nrf_grtc_int_enable_check(NRF_GRTC_Type const * p_reg,uint32_t mask)1207 NRF_STATIC_INLINE uint32_t nrf_grtc_int_enable_check(NRF_GRTC_Type const * p_reg, uint32_t mask)
1208 {
1209 return p_reg->GRTC_INTEN & mask;
1210 }
1211
nrf_grtc_int_pending_get(NRF_GRTC_Type const * p_reg)1212 NRF_STATIC_INLINE uint32_t nrf_grtc_int_pending_get(NRF_GRTC_Type const * p_reg)
1213 {
1214 return p_reg->GRTC_INTPEND;
1215 }
1216
1217 #if NRF_GRTC_HAS_INT_GROUPS
nrf_grtc_int_group_enable(NRF_GRTC_Type * p_reg,uint8_t group_idx,uint32_t mask)1218 NRF_STATIC_INLINE void nrf_grtc_int_group_enable(NRF_GRTC_Type * p_reg,
1219 uint8_t group_idx,
1220 uint32_t mask)
1221 {
1222 switch (group_idx)
1223 {
1224 case 0:
1225 p_reg->INTENSET0 = mask;
1226 break;
1227 case 1:
1228 p_reg->INTENSET1 = mask;
1229 break;
1230 #if defined(GRTC_INTENSET2_COMPARE0_Msk)
1231 case 2:
1232 p_reg->INTENSET2 = mask;
1233 break;
1234 #endif
1235 #if defined(GRTC_INTENSET3_COMPARE0_Msk)
1236 case 3:
1237 p_reg->INTENSET3 = mask;
1238 break;
1239 #endif
1240 #if defined(GRTC_INTENSET4_COMPARE0_Msk)
1241 case 4:
1242 p_reg->INTENSET4 = mask;
1243 break;
1244 #endif
1245 #if defined(GRTC_INTENSET5_COMPARE0_Msk)
1246 case 5:
1247 p_reg->INTENSET5 = mask;
1248 break;
1249 #endif
1250 #if defined(GRTC_INTENSET6_COMPARE0_Msk)
1251 case 6:
1252 p_reg->INTENSET6 = mask;
1253 break;
1254 #endif
1255 #if defined(GRTC_INTENSET7_COMPARE0_Msk)
1256 case 7:
1257 p_reg->INTENSET7 = mask;
1258 break;
1259 #endif
1260 #if defined(GRTC_INTENSET8_COMPARE0_Msk)
1261 case 8:
1262 p_reg->INTENSET8 = mask;
1263 break;
1264 #endif
1265 #if defined(GRTC_INTENSET9_COMPARE0_Msk)
1266 case 9:
1267 p_reg->INTENSET9 = mask;
1268 break;
1269 #endif
1270 #if defined(GRTC_INTENSET10_COMPARE0_Msk)
1271 case 10:
1272 p_reg->INTENSET10 = mask;
1273 break;
1274 #endif
1275 #if defined(GRTC_INTENSET11_COMPARE0_Msk)
1276 case 11:
1277 p_reg->INTENSET11 = mask;
1278 break;
1279 #endif
1280 #if defined(GRTC_INTENSET12_COMPARE0_Msk)
1281 case 12:
1282 p_reg->INTENSET12 = mask;
1283 break;
1284 #endif
1285 #if defined(GRTC_INTENSET13_COMPARE0_Msk)
1286 case 13:
1287 p_reg->INTENSET13 = mask;
1288 break;
1289 #endif
1290 #if defined(GRTC_INTENSET14_COMPARE0_Msk)
1291 case 14:
1292 p_reg->INTENSET14 = mask;
1293 break;
1294 #endif
1295 #if defined(GRTC_INTENSET15_COMPARE0_Msk)
1296 case 15:
1297 p_reg->INTENSET15 = mask;
1298 break;
1299 #endif
1300 default:
1301 NRFX_ASSERT(false);
1302 break;
1303 }
1304 }
1305
nrf_grtc_int_group_disable(NRF_GRTC_Type * p_reg,uint8_t group_idx,uint32_t mask)1306 NRF_STATIC_INLINE void nrf_grtc_int_group_disable(NRF_GRTC_Type * p_reg,
1307 uint8_t group_idx,
1308 uint32_t mask)
1309 {
1310 switch (group_idx)
1311 {
1312 case 0:
1313 p_reg->INTENCLR0 = mask;
1314 break;
1315 case 1:
1316 p_reg->INTENCLR1 = mask;
1317 break;
1318 #if defined(GRTC_INTENCLR2_COMPARE0_Msk)
1319 case 2:
1320 p_reg->INTENCLR2 = mask;
1321 break;
1322 #endif
1323 #if defined(GRTC_INTENCLR3_COMPARE0_Msk)
1324 case 3:
1325 p_reg->INTENCLR3 = mask;
1326 break;
1327 #endif
1328 #if defined(GRTC_INTENCLR4_COMPARE0_Msk)
1329 case 4:
1330 p_reg->INTENCLR4 = mask;
1331 break;
1332 #endif
1333 #if defined(GRTC_INTENCLR5_COMPARE0_Msk)
1334 case 5:
1335 p_reg->INTENCLR5 = mask;
1336 break;
1337 #endif
1338 #if defined(GRTC_INTENCLR6_COMPARE0_Msk)
1339 case 6:
1340 p_reg->INTENCLR6 = mask;
1341 break;
1342 #endif
1343 #if defined(GRTC_INTENCLR7_COMPARE0_Msk)
1344 case 7:
1345 p_reg->INTENCLR7 = mask;
1346 break;
1347 #endif
1348 #if defined(GRTC_INTENCLR8_COMPARE0_Msk)
1349 case 8:
1350 p_reg->INTENCLR8 = mask;
1351 break;
1352 #endif
1353 #if defined(GRTC_INTENCLR9_COMPARE0_Msk)
1354 case 9:
1355 p_reg->INTENCLR9 = mask;
1356 break;
1357 #endif
1358 #if defined(GRTC_INTENCLR10_COMPARE0_Msk)
1359 case 10:
1360 p_reg->INTENCLR10 = mask;
1361 break;
1362 #endif
1363 #if defined(GRTC_INTENCLR11_COMPARE0_Msk)
1364 case 11:
1365 p_reg->INTENCLR11 = mask;
1366 break;
1367 #endif
1368 #if defined(GRTC_INTENCLR12_COMPARE0_Msk)
1369 case 12:
1370 p_reg->INTENCLR12 = mask;
1371 break;
1372 #endif
1373 #if defined(GRTC_INTENCLR13_COMPARE0_Msk)
1374 case 13:
1375 p_reg->INTENCLR13 = mask;
1376 break;
1377 #endif
1378 #if defined(GRTC_INTENCLR14_COMPARE0_Msk)
1379 case 14:
1380 p_reg->INTENCLR14 = mask;
1381 break;
1382 #endif
1383 #if defined(GRTC_INTENCLR15_COMPARE0_Msk)
1384 case 15:
1385 p_reg->INTENCLR15 = mask;
1386 break;
1387 #endif
1388 default:
1389 NRFX_ASSERT(false);
1390 break;
1391 }
1392 }
1393
nrf_grtc_int_group_enable_check(NRF_GRTC_Type const * p_reg,uint8_t group_idx,uint32_t mask)1394 NRF_STATIC_INLINE uint32_t nrf_grtc_int_group_enable_check(NRF_GRTC_Type const * p_reg,
1395 uint8_t group_idx,
1396 uint32_t mask)
1397 {
1398 switch (group_idx)
1399 {
1400 case 0:
1401 return p_reg->INTENSET0 & mask;
1402 case 1:
1403 return p_reg->INTENSET1 & mask;
1404 #if defined(GRTC_INTENSET2_COMPARE0_Msk)
1405 case 2:
1406 return p_reg->INTENSET2 & mask;
1407 #endif
1408 #if defined(GRTC_INTENSET3_COMPARE0_Msk)
1409 case 3:
1410 return p_reg->INTENSET3 & mask;
1411 #endif
1412 #if defined(GRTC_INTENSET4_COMPARE0_Msk)
1413 case 4:
1414 return p_reg->INTENSET4 & mask;
1415 #endif
1416 #if defined(GRTC_INTENSET5_COMPARE0_Msk)
1417 case 5:
1418 return p_reg->INTENSET5 & mask;
1419 #endif
1420 #if defined(GRTC_INTENSET6_COMPARE0_Msk)
1421 case 6:
1422 return p_reg->INTENSET6 & mask;
1423 #endif
1424 #if defined(GRTC_INTENSET7_COMPARE0_Msk)
1425 case 7:
1426 return p_reg->INTENSET7 & mask;
1427 #endif
1428 #if defined(GRTC_INTENSET8_COMPARE0_Msk)
1429 case 8:
1430 return p_reg->INTENSET8 & mask;
1431 #endif
1432 #if defined(GRTC_INTENSET9_COMPARE0_Msk)
1433 case 9:
1434 return p_reg->INTENSET9 & mask;
1435 #endif
1436 #if defined(GRTC_INTENSET10_COMPARE0_Msk)
1437 case 10:
1438 return p_reg->INTENSET10 & mask;
1439 #endif
1440 #if defined(GRTC_INTENSET11_COMPARE0_Msk)
1441 case 11:
1442 return p_reg->INTENSET11 & mask;
1443 #endif
1444 #if defined(GRTC_INTENSET12_COMPARE0_Msk)
1445 case 12:
1446 return p_reg->INTENSET12 & mask;
1447 #endif
1448 #if defined(GRTC_INTENSET13_COMPARE0_Msk)
1449 case 13:
1450 return p_reg->INTENSET13 & mask;
1451 #endif
1452 #if defined(GRTC_INTENSET14_COMPARE0_Msk)
1453 case 14:
1454 return p_reg->INTENSET14 & mask;
1455 #endif
1456 #if defined(GRTC_INTENSET15_COMPARE0_Msk)
1457 case 15:
1458 return p_reg->INTENSET15 & mask;
1459 #endif
1460 default:
1461 NRFX_ASSERT(false);
1462 return 0;
1463 }
1464 }
1465 #endif // NRF_GRTC_HAS_INT_GROUPS
1466
1467 #if NRF_GRTC_HAS_PWM
nrf_grtc_event_enable(NRF_GRTC_Type * p_reg,uint32_t mask)1468 NRF_STATIC_INLINE void nrf_grtc_event_enable(NRF_GRTC_Type * p_reg, uint32_t mask)
1469 {
1470 p_reg->EVTENSET = mask;
1471 }
1472
nrf_grtc_event_disable(NRF_GRTC_Type * p_reg,uint32_t mask)1473 NRF_STATIC_INLINE void nrf_grtc_event_disable(NRF_GRTC_Type * p_reg, uint32_t mask)
1474 {
1475 p_reg->EVTENCLR = mask;
1476 }
1477 #endif // NRF_GRTC_HAS_PWM
1478
1479 #if NRF_GRTC_HAS_EXTENDED
nrf_grtc_shorts_enable(NRF_GRTC_Type * p_reg,uint32_t mask)1480 NRF_STATIC_INLINE void nrf_grtc_shorts_enable(NRF_GRTC_Type * p_reg, uint32_t mask)
1481 {
1482 p_reg->SHORTS |= mask;
1483 }
1484
nrf_grtc_shorts_disable(NRF_GRTC_Type * p_reg,uint32_t mask)1485 NRF_STATIC_INLINE void nrf_grtc_shorts_disable(NRF_GRTC_Type * p_reg, uint32_t mask)
1486 {
1487 p_reg->SHORTS &= ~(mask);
1488 }
1489
nrf_grtc_shorts_set(NRF_GRTC_Type * p_reg,uint32_t mask)1490 NRF_STATIC_INLINE void nrf_grtc_shorts_set(NRF_GRTC_Type * p_reg, uint32_t mask)
1491 {
1492 p_reg->SHORTS = mask;
1493 }
1494 #endif // NRF_GRTC_HAS_EXTENDED
1495
nrf_grtc_subscribe_set(NRF_GRTC_Type * p_reg,nrf_grtc_task_t task,uint8_t channel)1496 NRF_STATIC_INLINE void nrf_grtc_subscribe_set(NRF_GRTC_Type * p_reg,
1497 nrf_grtc_task_t task,
1498 uint8_t channel)
1499 {
1500 #if NRF_GRTC_HAS_EXTENDED
1501 NRFX_ASSERT((task != NRF_GRTC_TASK_START) &&
1502 (task != NRF_GRTC_TASK_CLEAR) &&
1503 (task != NRF_GRTC_TASK_STOP));
1504 #endif
1505
1506 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
1507 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1508 }
1509
nrf_grtc_subscribe_clear(NRF_GRTC_Type * p_reg,nrf_grtc_task_t task)1510 NRF_STATIC_INLINE void nrf_grtc_subscribe_clear(NRF_GRTC_Type * p_reg,
1511 nrf_grtc_task_t task)
1512 {
1513 #if NRF_GRTC_HAS_EXTENDED
1514 NRFX_ASSERT((task != NRF_GRTC_TASK_START) &&
1515 (task != NRF_GRTC_TASK_CLEAR) &&
1516 (task != NRF_GRTC_TASK_STOP));
1517 #endif
1518
1519 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
1520 }
1521
nrf_grtc_publish_set(NRF_GRTC_Type * p_reg,nrf_grtc_event_t event,uint8_t channel)1522 NRF_STATIC_INLINE void nrf_grtc_publish_set(NRF_GRTC_Type * p_reg,
1523 nrf_grtc_event_t event,
1524 uint8_t channel)
1525 {
1526 #if NRF_GRTC_HAS_SYSCOUNTERVALID
1527 NRFX_ASSERT(event != NRF_GRTC_EVENT_SYSCOUNTERVALID);
1528 #endif
1529 #if NRF_GRTC_HAS_RTCOUNTER
1530 NRFX_ASSERT(event != NRF_GRTC_EVENT_RTCOMPARESYNC);
1531 #endif
1532
1533 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80UL)) =
1534 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1535 }
1536
nrf_grtc_publish_clear(NRF_GRTC_Type * p_reg,nrf_grtc_event_t event)1537 NRF_STATIC_INLINE void nrf_grtc_publish_clear(NRF_GRTC_Type * p_reg,
1538 nrf_grtc_event_t event)
1539 {
1540 #if NRF_GRTC_HAS_SYSCOUNTERVALID
1541 NRFX_ASSERT(event != NRF_GRTC_EVENT_SYSCOUNTERVALID);
1542 #endif
1543 #if NRF_GRTC_HAS_RTCOUNTER
1544 NRFX_ASSERT(event != NRF_GRTC_EVENT_RTCOMPARESYNC);
1545 #endif
1546
1547 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80UL)) = 0x0UL;
1548 }
1549
nrf_grtc_event_check(NRF_GRTC_Type const * p_reg,nrf_grtc_event_t event)1550 NRF_STATIC_INLINE bool nrf_grtc_event_check(NRF_GRTC_Type const * p_reg, nrf_grtc_event_t event)
1551 {
1552 return nrf_event_check(p_reg, event);
1553 }
1554
nrf_grtc_event_clear(NRF_GRTC_Type * p_reg,nrf_grtc_event_t event)1555 NRF_STATIC_INLINE void nrf_grtc_event_clear(NRF_GRTC_Type * p_reg, nrf_grtc_event_t event)
1556 {
1557 #if NRF_GRTC_HAS_SYSCOUNTERVALID
1558 NRFX_ASSERT(event != NRF_GRTC_EVENT_SYSCOUNTERVALID);
1559 #endif
1560
1561 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
1562 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
1563 }
1564
1565 #if NRF_GRTC_HAS_RTCOUNTER
nrf_grtc_rt_counter_low_get(NRF_GRTC_Type const * p_reg)1566 NRF_STATIC_INLINE uint32_t nrf_grtc_rt_counter_low_get(NRF_GRTC_Type const * p_reg)
1567 {
1568 return p_reg->RTCOUNTERL;
1569 }
1570
nrf_grtc_rt_counter_high_get(NRF_GRTC_Type const * p_reg)1571 NRF_STATIC_INLINE uint32_t nrf_grtc_rt_counter_high_get(NRF_GRTC_Type const * p_reg)
1572 {
1573 return p_reg->RTCOUNTERH;
1574 }
1575 #endif // NRF_GRTC_HAS_RTCOUNTER
1576
nrf_grtc_sys_counter_low_get(NRF_GRTC_Type const * p_reg)1577 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_low_get(NRF_GRTC_Type const * p_reg)
1578 {
1579 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1580 return p_reg->GRTC_SYSCOUNTER.SYSCOUNTERL;
1581 #else
1582 return p_reg->SYSCOUNTERL;
1583 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1584 }
1585
nrf_grtc_sys_counter_high_get(NRF_GRTC_Type const * p_reg)1586 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_high_get(NRF_GRTC_Type const * p_reg)
1587 {
1588 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1589 return p_reg->GRTC_SYSCOUNTER.SYSCOUNTERH;
1590 #else
1591 return p_reg->SYSCOUNTERH;
1592 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1593 }
1594
nrf_grtc_sys_counter_get(NRF_GRTC_Type const * p_reg)1595 NRF_STATIC_INLINE uint64_t nrf_grtc_sys_counter_get(NRF_GRTC_Type const * p_reg)
1596 {
1597 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1598 return *((const uint64_t volatile *)&p_reg->GRTC_SYSCOUNTER.SYSCOUNTERL);
1599 #else
1600 return *((const uint64_t volatile *)&p_reg->SYSCOUNTERL);
1601 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1602 }
1603
nrf_grtc_sys_counter_overflow_check(NRF_GRTC_Type const * p_reg)1604 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_overflow_check(NRF_GRTC_Type const * p_reg)
1605 {
1606 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1607 return (p_reg->GRTC_SYSCOUNTER.SYSCOUNTERH &
1608 GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Msk) ? true : false;
1609 #else
1610 return (p_reg->SYSCOUNTERH & GRTC_SYSCOUNTERH_OVERFLOW_Msk) ? true : false;
1611 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1612 }
1613
1614 #if NRF_GRTC_HAS_SYSCOUNTER_ARRAY
nrf_grtc_sys_counter_indexed_get(NRF_GRTC_Type const * p_reg,uint8_t index)1615 NRF_STATIC_INLINE uint64_t nrf_grtc_sys_counter_indexed_get(NRF_GRTC_Type const * p_reg,
1616 uint8_t index)
1617 {
1618 NRFX_ASSERT(index < NRF_GRTC_SYSCOUNTER_COUNT);
1619 return *((const uint64_t volatile *)&p_reg->SYSCOUNTER[index]);
1620 }
1621
nrf_grtc_sys_counter_active_set(NRF_GRTC_Type * p_reg,bool enable)1622 NRF_STATIC_INLINE void nrf_grtc_sys_counter_active_set(NRF_GRTC_Type * p_reg, bool enable)
1623 {
1624 p_reg->GRTC_SYSCOUNTER.ACTIVE = ((p_reg->GRTC_SYSCOUNTER.ACTIVE &
1625 ~(GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Msk)) |
1626 (enable ? GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Active :
1627 GRTC_SYSCOUNTER_ACTIVE_ACTIVE_NotActive));
1628 }
1629
nrf_grtc_sys_counter_active_check(NRF_GRTC_Type const * p_reg)1630 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_active_check(NRF_GRTC_Type const * p_reg)
1631 {
1632 return (p_reg->GRTC_SYSCOUNTER.ACTIVE & GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Msk) ==
1633 GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Active;
1634 }
1635 #endif // NRF_GRTC_HAS_SYSCOUNTER_ARRAY
1636
nrf_grtc_event_address_get(NRF_GRTC_Type const * p_reg,nrf_grtc_event_t event)1637 NRF_STATIC_INLINE uint32_t nrf_grtc_event_address_get(NRF_GRTC_Type const * p_reg,
1638 nrf_grtc_event_t event)
1639 {
1640 return (uint32_t)p_reg + (uint32_t)event;
1641 }
1642
nrf_grtc_task_address_get(NRF_GRTC_Type const * p_reg,nrf_grtc_task_t task)1643 NRF_STATIC_INLINE uint32_t nrf_grtc_task_address_get(NRF_GRTC_Type const * p_reg,
1644 nrf_grtc_task_t task)
1645 {
1646 return (uint32_t)p_reg + (uint32_t)task;
1647 }
1648
nrf_grtc_task_trigger(NRF_GRTC_Type * p_reg,nrf_grtc_task_t task)1649 NRF_STATIC_INLINE void nrf_grtc_task_trigger(NRF_GRTC_Type * p_reg, nrf_grtc_task_t task)
1650 {
1651 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
1652 }
1653
nrf_grtc_sys_counter_capture_task_get(uint8_t cc_channel)1654 NRF_STATIC_INLINE nrf_grtc_task_t nrf_grtc_sys_counter_capture_task_get(uint8_t cc_channel)
1655 {
1656 return (nrf_grtc_task_t)NRFX_OFFSETOF(NRF_GRTC_Type, TASKS_CAPTURE[cc_channel]);
1657 }
1658
nrf_grtc_sys_counter_compare_event_enable(NRF_GRTC_Type * p_reg,uint8_t cc_channel)1659 NRF_STATIC_INLINE void nrf_grtc_sys_counter_compare_event_enable(NRF_GRTC_Type * p_reg,
1660 uint8_t cc_channel)
1661 {
1662
1663 #if NRF_GRTC_HAS_EXTENDED
1664 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT);
1665 #else
1666 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT &&
1667 cc_channel > NRF_GRTC_MAIN_CC_CHANNEL);
1668 #endif
1669 p_reg->CC[cc_channel].CCEN = GRTC_CC_CCEN_ACTIVE_Enable;
1670 }
1671
nrf_grtc_sys_counter_compare_event_disable(NRF_GRTC_Type * p_reg,uint8_t cc_channel)1672 NRF_STATIC_INLINE void nrf_grtc_sys_counter_compare_event_disable(NRF_GRTC_Type * p_reg,
1673 uint8_t cc_channel)
1674 {
1675 #if NRF_GRTC_HAS_EXTENDED
1676 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT);
1677 #else
1678 NRFX_ASSERT(cc_channel < NRF_GRTC_SYSCOUNTER_CC_COUNT &&
1679 cc_channel > NRF_GRTC_MAIN_CC_CHANNEL);
1680 #endif
1681 p_reg->CC[cc_channel].CCEN = GRTC_CC_CCEN_ACTIVE_Disable;
1682 }
1683
nrf_grtc_sys_counter_compare_event_get(uint8_t cc_channel)1684 NRF_STATIC_INLINE nrf_grtc_event_t nrf_grtc_sys_counter_compare_event_get(uint8_t cc_channel)
1685 {
1686 return (nrf_grtc_event_t)NRFX_OFFSETOF(NRF_GRTC_Type, EVENTS_COMPARE[cc_channel]);
1687 }
1688
nrf_grtc_sys_counter_cc_enable_check(NRF_GRTC_Type const * p_reg,uint8_t cc_channel)1689 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_cc_enable_check(NRF_GRTC_Type const * p_reg,
1690 uint8_t cc_channel)
1691 {
1692 return ((p_reg->CC[cc_channel].CCEN & GRTC_CC_CCEN_ACTIVE_Msk) >> GRTC_CC_CCEN_ACTIVE_Pos) ==
1693 GRTC_CC_CCEN_ACTIVE_Enable;
1694 }
1695
1696 #if NRF_GRTC_HAS_EXTENDED
nrf_grtc_sys_counter_set(NRF_GRTC_Type * p_reg,bool enable)1697 NRF_STATIC_INLINE void nrf_grtc_sys_counter_set(NRF_GRTC_Type * p_reg, bool enable)
1698 {
1699 p_reg->MODE = ((p_reg->MODE & ~GRTC_MODE_SYSCOUNTEREN_Msk) |
1700 ((enable ? GRTC_MODE_SYSCOUNTEREN_Enabled :
1701 GRTC_MODE_SYSCOUNTEREN_Disabled) << GRTC_MODE_SYSCOUNTEREN_Pos));
1702 }
1703
nrf_grtc_sys_counter_auto_mode_set(NRF_GRTC_Type * p_reg,bool enable)1704 NRF_STATIC_INLINE void nrf_grtc_sys_counter_auto_mode_set(NRF_GRTC_Type * p_reg, bool enable)
1705 {
1706 p_reg->MODE = ((p_reg->MODE & ~GRTC_MODE_AUTOEN_Msk) |
1707 ((enable ? GRTC_MODE_AUTOEN_CpuActive :
1708 GRTC_MODE_AUTOEN_Default) << GRTC_MODE_AUTOEN_Pos));
1709 }
1710
nrf_grtc_sys_counter_auto_mode_check(NRF_GRTC_Type * p_reg)1711 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_auto_mode_check(NRF_GRTC_Type * p_reg)
1712 {
1713 return (p_reg->MODE & GRTC_MODE_AUTOEN_Msk) == GRTC_MODE_AUTOEN_CpuActive;
1714 }
1715
1716 #endif // NRF_GRTC_HAS_EXTENDED
1717
nrf_grtc_sys_counter_check(NRF_GRTC_Type const * p_reg)1718 NRF_STATIC_INLINE bool nrf_grtc_sys_counter_check(NRF_GRTC_Type const * p_reg)
1719 {
1720 return (p_reg->MODE & GRTC_MODE_SYSCOUNTEREN_Msk) ? true : false;
1721 }
1722
1723 #if NRF_GRTC_HAS_KEEPRUNNING
nrf_grtc_sys_counter_active_state_request_set(NRF_GRTC_Type * p_reg,bool enable)1724 NRF_STATIC_INLINE void nrf_grtc_sys_counter_active_state_request_set(NRF_GRTC_Type * p_reg,
1725 bool enable)
1726 {
1727 #if defined(GRTC_KEEPRUNNING_DOMAIN0_Msk)
1728 p_reg->KEEPRUNNING = ((p_reg->KEEPRUNNING &
1729 ~(GRTC_KEEPRUNNING_DOMAIN0_Active << NRF_GRTC_DOMAIN_INDEX)) |
1730 ((enable ? GRTC_KEEPRUNNING_DOMAIN0_Active :
1731 GRTC_KEEPRUNNING_DOMAIN0_NotActive) << NRF_GRTC_DOMAIN_INDEX));
1732 #else
1733 p_reg->KEEPRUNNING = ((p_reg->KEEPRUNNING &
1734 ~(GRTC_KEEPRUNNING_REQUEST0_Active << NRF_GRTC_DOMAIN_INDEX)) |
1735 ((enable ? GRTC_KEEPRUNNING_REQUEST0_Active :
1736 GRTC_KEEPRUNNING_REQUEST0_NotActive) << NRF_GRTC_DOMAIN_INDEX));
1737 #endif
1738 }
1739
1740 NRF_STATIC_INLINE
nrf_grtc_sys_counter_active_state_request_check(NRF_GRTC_Type const * p_reg)1741 bool nrf_grtc_sys_counter_active_state_request_check(NRF_GRTC_Type const * p_reg)
1742 {
1743 #if defined(GRTC_KEEPRUNNING_DOMAIN0_Msk)
1744 return (p_reg->KEEPRUNNING &
1745 (GRTC_KEEPRUNNING_DOMAIN0_Active << NRF_GRTC_DOMAIN_INDEX)) ? true : false;
1746 #else
1747 return (p_reg->KEEPRUNNING &
1748 (GRTC_KEEPRUNNING_REQUEST0_Active << NRF_GRTC_DOMAIN_INDEX)) ? true : false;
1749 #endif
1750 }
1751
1752 NRF_STATIC_INLINE
nrf_grtc_sys_counter_active_state_request_get(NRF_GRTC_Type const * p_reg,uint32_t mask)1753 uint32_t nrf_grtc_sys_counter_active_state_request_get(NRF_GRTC_Type const * p_reg,
1754 uint32_t mask)
1755 {
1756 return p_reg->KEEPRUNNING & mask;
1757 }
1758 #endif // NRF_GRTC_HAS_KEEPRUNNING
1759
1760 #if NRF_GRTC_HAS_EXTENDED
nrf_grtc_sys_counter_interval_set(NRF_GRTC_Type * p_reg,uint32_t value)1761 NRF_STATIC_INLINE void nrf_grtc_sys_counter_interval_set(NRF_GRTC_Type * p_reg, uint32_t value)
1762 {
1763 p_reg->INTERVAL = value;
1764 }
1765
nrf_grtc_sys_counter_interval_get(NRF_GRTC_Type const * p_reg)1766 NRF_STATIC_INLINE uint32_t nrf_grtc_sys_counter_interval_get(NRF_GRTC_Type const * p_reg)
1767 {
1768 return p_reg->INTERVAL;
1769 }
1770
nrf_grtc_timeout_set(NRF_GRTC_Type * p_reg,uint32_t value)1771 NRF_STATIC_INLINE void nrf_grtc_timeout_set(NRF_GRTC_Type * p_reg, uint32_t value)
1772 {
1773 NRFX_ASSERT(value <= NRF_GRTC_TIMEOUT_MAX_VALUE);
1774 p_reg->TIMEOUT = (value << GRTC_TIMEOUT_VALUE_Pos);
1775 }
1776
nrf_grtc_timeout_get(NRF_GRTC_Type const * p_reg)1777 NRF_STATIC_INLINE uint32_t nrf_grtc_timeout_get(NRF_GRTC_Type const * p_reg)
1778 {
1779 return (p_reg->TIMEOUT >> GRTC_TIMEOUT_VALUE_Pos);
1780 }
1781
nrf_grtc_waketime_set(NRF_GRTC_Type * p_reg,uint32_t value)1782 NRF_STATIC_INLINE void nrf_grtc_waketime_set(NRF_GRTC_Type * p_reg, uint32_t value)
1783 {
1784 NRFX_ASSERT(value <= NRF_GRTC_WAKETIME_MAX_VALUE);
1785 p_reg->WAKETIME = (value << GRTC_WAKETIME_VALUE_Pos);
1786 }
1787
nrf_grtc_waketime_get(NRF_GRTC_Type const * p_reg)1788 NRF_STATIC_INLINE uint32_t nrf_grtc_waketime_get(NRF_GRTC_Type const * p_reg)
1789 {
1790 return (p_reg->WAKETIME >> GRTC_WAKETIME_VALUE_Pos);
1791 }
1792 #endif // NRF_GRTC_HAS_EXTENDED
1793
1794 #if NRF_GRTC_HAS_PWM
nrf_grtc_pwm_compare_set(NRF_GRTC_Type * p_reg,uint32_t value)1795 NRF_STATIC_INLINE void nrf_grtc_pwm_compare_set(NRF_GRTC_Type * p_reg, uint32_t value)
1796 {
1797 p_reg->PWMCONFIG = (value << GRTC_PWMCONFIG_COMPAREVALUE_Pos) & GRTC_PWMCONFIG_COMPAREVALUE_Msk;
1798 }
1799
nrf_grtc_pwm_compare_get(NRF_GRTC_Type const * p_reg)1800 NRF_STATIC_INLINE uint32_t nrf_grtc_pwm_compare_get(NRF_GRTC_Type const * p_reg)
1801 {
1802 return (p_reg->PWMCONFIG >> GRTC_PWMCONFIG_COMPAREVALUE_Pos);
1803 }
1804 #endif // NRF_GRTC_HAS_PWM
1805
1806 #if NRF_GRTC_HAS_CLKOUT
nrf_grtc_clkout_set(NRF_GRTC_Type * p_reg,nrf_grtc_clkout_t clkout,bool enable)1807 NRF_STATIC_INLINE void nrf_grtc_clkout_set(NRF_GRTC_Type * p_reg,
1808 nrf_grtc_clkout_t clkout,
1809 bool enable)
1810 {
1811 if (enable)
1812 {
1813 p_reg->CLKOUT |= (uint32_t)clkout;
1814 }
1815 else
1816 {
1817 p_reg->CLKOUT &= ~((uint32_t)clkout);
1818 }
1819 }
1820
nrf_grtc_clkout_enable_check(NRF_GRTC_Type const * p_reg,nrf_grtc_clkout_t clkout)1821 NRF_STATIC_INLINE bool nrf_grtc_clkout_enable_check(NRF_GRTC_Type const * p_reg,
1822 nrf_grtc_clkout_t clkout)
1823 {
1824 return p_reg->CLKOUT == (uint32_t)clkout;
1825 }
1826
nrf_grtc_clkout_divider_set(NRF_GRTC_Type * p_reg,uint32_t value)1827 NRF_STATIC_INLINE void nrf_grtc_clkout_divider_set(NRF_GRTC_Type * p_reg, uint32_t value)
1828 {
1829 NRFX_ASSERT(value <= NRF_GRTC_CLKCFG_CLKFASTDIV_MAX_VALUE);
1830 p_reg->CLKCFG = (p_reg->CLKCFG & ~GRTC_CLKCFG_CLKFASTDIV_Msk) |
1831 ((value & GRTC_CLKCFG_CLKFASTDIV_Msk) << GRTC_CLKCFG_CLKFASTDIV_Pos);
1832 }
1833
nrf_grtc_clkout_divider_get(NRF_GRTC_Type const * p_reg)1834 NRF_STATIC_INLINE uint32_t nrf_grtc_clkout_divider_get(NRF_GRTC_Type const * p_reg)
1835 {
1836 return (p_reg->CLKCFG & GRTC_CLKCFG_CLKFASTDIV_Msk) >> GRTC_CLKCFG_CLKFASTDIV_Pos;
1837 }
1838 #endif // NRF_GRTC_HAS_CLKOUT
1839
1840 #if NRF_GRTC_HAS_CLKSEL
nrf_grtc_clksel_set(NRF_GRTC_Type * p_reg,nrf_grtc_clksel_t clksel)1841 NRF_STATIC_INLINE void nrf_grtc_clksel_set(NRF_GRTC_Type * p_reg, nrf_grtc_clksel_t clksel)
1842 {
1843 p_reg->CLKCFG = (p_reg->CLKCFG & ~GRTC_CLKCFG_CLKSEL_Msk) |
1844 (clksel << GRTC_CLKCFG_CLKSEL_Pos);
1845 }
1846
nrf_grtc_clksel_get(NRF_GRTC_Type const * p_reg)1847 NRF_STATIC_INLINE nrf_grtc_clksel_t nrf_grtc_clksel_get(NRF_GRTC_Type const * p_reg)
1848 {
1849 return (nrf_grtc_clksel_t)((p_reg->CLKCFG & GRTC_CLKCFG_CLKSEL_Msk) >> GRTC_CLKCFG_CLKSEL_Pos);
1850 }
1851 #endif // NRF_GRTC_HAS_CLKSEL
1852
1853 #endif // NRF_DECLARE_ONLY
1854
1855 /** @} */
1856
1857 #ifdef __cplusplus
1858 }
1859 #endif
1860
1861 #endif /* NRF_GRTC_H */
1862
