1 /*
2 * Copyright (c) 2019 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <nrfx.h>
35
36 #if NRFX_CHECK(NRFX_EGU_ENABLED)
37
38 #if !NRFX_FEATURE_PRESENT(NRFX_EGU, _ENABLED)
39 #error "No enabled EGU instances. Check <nrfx_config.h>."
40 #endif
41
42 #if NRFX_CHECK(NRFX_EGU0_ENABLED) && ((1 << 0) & NRFX_EGUS_USED)
43 #error "EGU instance 0 is reserved for use outside of nrfx."
44 #endif
45 #if NRFX_CHECK(NRFX_EGU1_ENABLED) && ((1 << 1) & NRFX_EGUS_USED)
46 #error "EGU instance 1 is reserved for use outside of nrfx."
47 #endif
48 #if NRFX_CHECK(NRFX_EGU2_ENABLED) && ((1 << 2) & NRFX_EGUS_USED)
49 #error "EGU instance 2 is reserved for use outside of nrfx."
50 #endif
51 #if NRFX_CHECK(NRFX_EGU3_ENABLED) && ((1 << 3) & NRFX_EGUS_USED)
52 #error "EGU instance 3 is reserved for use outside of nrfx."
53 #endif
54 #if NRFX_CHECK(NRFX_EGU4_ENABLED) && ((1 << 4) & NRFX_EGUS_USED)
55 #error "EGU instance 4 is reserved for use outside of nrfx."
56 #endif
57 #if NRFX_CHECK(NRFX_EGU5_ENABLED) && ((1 << 5) & NRFX_EGUS_USED)
58 #error "EGU instance 5 is reserved for use outside of nrfx."
59 #endif
60
61 #include <nrfx_egu.h>
62
63 typedef struct
64 {
65 nrfx_egu_event_handler_t handler;
66 void * p_context;
67 nrfx_drv_state_t state;
68 } egu_control_block_t;
69
70 static egu_control_block_t m_cb[NRFX_EGU_ENABLED_COUNT];
71
72 /*
73 * `-Warray-bounds` warning is disabled for the `egu_event_mask_get_and_clear`
74 * function because GCC 12 and above may report a false positive due to accessing
75 * event registers.
76 */
77 #if defined(__GNUC__)
78 #pragma GCC diagnostic push
79 #pragma GCC diagnostic ignored "-Warray-bounds"
80 #endif
81
egu_event_mask_get_and_clear(NRF_EGU_Type * p_reg,uint32_t int_mask)82 static uint32_t egu_event_mask_get_and_clear(NRF_EGU_Type * p_reg, uint32_t int_mask)
83 {
84 uint32_t event_mask = 0;
85 while (int_mask)
86 {
87 uint8_t event_idx = (uint8_t)NRF_CTZ(int_mask);
88 int_mask &= ~(1UL << event_idx);
89
90 nrf_egu_event_t event = nrf_egu_triggered_event_get(event_idx);
91 if (nrf_egu_event_check(p_reg, event))
92 {
93 nrf_egu_event_clear(p_reg, event);
94 event_mask |= (1UL << event_idx);
95 }
96 }
97 return event_mask;
98 }
99
100 #if defined(__GNUC__)
101 #pragma GCC diagnostic pop
102 #endif
103
nrfx_egu_init(nrfx_egu_t const * p_instance,uint8_t interrupt_priority,nrfx_egu_event_handler_t event_handler,void * p_context)104 nrfx_err_t nrfx_egu_init(nrfx_egu_t const * p_instance,
105 uint8_t interrupt_priority,
106 nrfx_egu_event_handler_t event_handler,
107 void * p_context)
108 {
109 egu_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
110
111 if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
112 {
113 #if NRFX_API_VER_AT_LEAST(3, 2, 0)
114 return NRFX_ERROR_ALREADY;
115 #else
116 return NRFX_ERROR_INVALID_STATE;
117 #endif
118 }
119
120 p_cb->state = NRFX_DRV_STATE_INITIALIZED;
121 p_cb->p_context = p_context;
122 p_cb->handler = event_handler;
123 if (event_handler)
124 {
125 NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg));
126 NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg), interrupt_priority);
127 }
128
129 return NRFX_SUCCESS;
130 }
131
nrfx_egu_int_enable(nrfx_egu_t const * p_instance,uint32_t mask)132 void nrfx_egu_int_enable(nrfx_egu_t const * p_instance, uint32_t mask)
133 {
134 NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED);
135 NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].handler);
136
137 (void)egu_event_mask_get_and_clear(p_instance->p_reg, mask);
138 nrf_egu_int_enable(p_instance->p_reg, mask);
139 }
140
nrfx_egu_int_disable(nrfx_egu_t const * p_instance,uint32_t mask)141 void nrfx_egu_int_disable(nrfx_egu_t const * p_instance, uint32_t mask)
142 {
143 NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED);
144
145 nrf_egu_int_disable(p_instance->p_reg, mask);
146 }
147
nrfx_egu_trigger(nrfx_egu_t const * p_instance,uint8_t event_idx)148 void nrfx_egu_trigger(nrfx_egu_t const * p_instance, uint8_t event_idx)
149 {
150 NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED);
151 NRFX_ASSERT(event_idx < nrf_egu_channel_count(p_instance->p_reg));
152
153 nrf_egu_task_trigger(p_instance->p_reg, nrf_egu_trigger_task_get(event_idx));
154 }
155
nrfx_egu_uninit(nrfx_egu_t const * p_instance)156 void nrfx_egu_uninit(nrfx_egu_t const * p_instance)
157 {
158 egu_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
159
160 nrf_egu_int_disable(p_instance->p_reg, ~0UL);
161 NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg));
162
163 p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
164 }
165
nrfx_egu_init_check(nrfx_egu_t const * p_instance)166 bool nrfx_egu_init_check(nrfx_egu_t const * p_instance)
167 {
168 egu_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
169
170 return (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
171 }
172
irq_handler(NRF_EGU_Type * p_reg,egu_control_block_t * p_cb)173 static void irq_handler(NRF_EGU_Type * p_reg, egu_control_block_t * p_cb)
174 {
175 uint32_t int_mask = nrf_egu_int_enable_check(p_reg, ~0UL);
176
177 /* Check (and clear) only the events that are set to generate interrupts.
178 Leave the other ones untouched. */
179 uint32_t event_mask = egu_event_mask_get_and_clear(p_reg, int_mask);
180 while (event_mask)
181 {
182 uint8_t event_idx = (uint8_t)NRF_CTZ(event_mask);
183 event_mask &= ~(1UL << event_idx);
184 p_cb->handler(event_idx, p_cb->p_context);
185 }
186 }
187
188 NRFX_INSTANCE_IRQ_HANDLERS(EGU, egu)
189
190 #endif // NRFX_CHECK(NRFX_EGU_ENABLED)
191
