1 /*
2 * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_SAADC_H_
35 #define NRF_SAADC_H_
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_saadc_hal SAADC HAL
45 * @{
46 * @ingroup nrf_saadc
47 * @brief Hardware access layer for managing the SAADC peripheral.
48 */
49
50 /** @brief Symbol specifying the offset of interrupt bitmask for limits of all channels. */
51 #define NRF_SAADC_LIMITS_INT_OFFSET \
52 NRFX_MIN(SAADC_INTENSET_CH0LIMITH_Pos, SAADC_INTENSET_CH0LIMITL_Pos)
53
54 /** @brief Symbol specifying the interrupt bitmask for limits of all channels. */
55 #define NRF_SAADC_ALL_CHANNELS_LIMITS_INT_MASK \
56 ((uint32_t)(((1 << SAADC_CH_NUM) - 1) << NRF_SAADC_LIMITS_INT_OFFSET))
57
58 #if defined(SAADC_CH_CONFIG_TACQ_3us) || defined(__NRFX_DOXYGEN__)
59 /** @brief Symbol indicating whether the configuration of acquisition time using predefined values is present. */
60 #define NRF_SAADC_HAS_ACQTIME_ENUM 1
61 #else
62 #define NRF_SAADC_HAS_ACQTIME_ENUM 0
63 #endif
64
65 #if defined(SAADC_CH_CONFIG_TCONV_Msk) || defined(__NRFX_DOXYGEN__)
66 /** @brief Symbol indicating whether the configuration of conversion time is present. */
67 #define NRF_SAADC_HAS_CONVTIME 1
68 #else
69 #define NRF_SAADC_HAS_CONVTIME 0
70 #endif
71
72 #if defined(SAADC_TRIM_LINCALCOEFF_VAL_Msk) || defined(__NRFX_DOXYGEN__)
73 /** @brief Symbol indicating whether the configuration of linearity calibration coefficients is present. */
74 #define NRF_SAADC_HAS_LIN_CAL 1
75 #else
76 #define NRF_SAADC_HAS_LIN_CAL 0
77 #endif
78
79 #if defined(SAADC_CH_PSELP_PIN_Msk) || defined(__NRFX_DOXYGEN__)
80 /** @brief Symbol indicating whether configuration of analog input using pin number is present. */
81 #define NRF_SAADC_HAS_AIN_AS_PIN 1
82 #else
83 #define NRF_SAADC_HAS_AIN_AS_PIN 0
84 #endif
85
86 #if defined(SAADC_DMA_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
87 /** @brief Symbol indicating whether dedicated DMA register is present. */
88 #define NRF_SAADC_HAS_DMA_REG 1
89 #else
90 #define NRF_SAADC_HAS_DMA_REG 0
91 #endif
92
93 #if defined(SAADC_EVENTS_DMA_END_END_Msk) || defined(__NRFX_DOXYGEN__)
94 /** @brief Symbol indicating whether SAADC DMA events are present. */
95 #define NRF_SAADC_HAS_DMA_EVENTS 1
96 #else
97 #define NRF_SAADC_HAS_DMA_EVENTS 0
98 #endif
99
100 #if defined(SAADC_CH_CONFIG_RESP_Msk) || defined(__NRFX_DOXYGEN__)
101 /** @brief Symbol indicating whether SAADC channel resistor control is present. */
102 #define NRF_SAADC_HAS_CH_CONFIG_RES 1
103 #else
104 #define NRF_SAADC_HAS_CH_CONFIG_RES 0
105 #endif
106
107 #if !NRF_SAADC_HAS_ACQTIME_ENUM
108 /** @brief Maximum value of acquire time. */
109 #define NRF_SAADC_ACQTIME_MAX SAADC_CH_CONFIG_TACQ_Max
110 #endif
111
112 #if NRF_SAADC_HAS_CONVTIME
113 /** @brief Symbol specifying maximum value of conversion time. */
114 #define NRF_SAADC_CONVTIME_MAX SAADC_CH_CONFIG_TCONV_Max
115 #endif
116
117 #if NRF_SAADC_HAS_LIN_CAL
118 /** @brief Symbol specifying maximum count of linearity calibration coefficients. */
119 #define NRF_SAADC_LIN_CAL_MAX_COUNT SAADC_TRIM_LINCALCOEFF_MaxCount
120
121 /** @brief Symbol specifying maximum value of linearity calibration coefficient. */
122 #define NRF_SAADC_LIN_CAL_MAX SAADC_TRIM_LINCALCOEFF_VAL_Max
123 #endif
124
125 #if defined(NRF54H20_ENGA_XXAA) || defined(NRF54L15_ENGA_XXAA) || defined(__NRFX_DOXYGEN__)
126 /** @brief Symbol specifying width of the 8-bit sample in bits. */
127 #define NRF_SAADC_8BIT_SAMPLE_WIDTH 8
128 #else
129 #define NRF_SAADC_8BIT_SAMPLE_WIDTH 16
130 #endif
131
132 /** @brief Resolution of the analog-to-digital converter. */
133 typedef enum
134 {
135 NRF_SAADC_RESOLUTION_8BIT = SAADC_RESOLUTION_VAL_8bit, ///< 8 bit resolution.
136 NRF_SAADC_RESOLUTION_10BIT = SAADC_RESOLUTION_VAL_10bit, ///< 10 bit resolution.
137 NRF_SAADC_RESOLUTION_12BIT = SAADC_RESOLUTION_VAL_12bit, ///< 12 bit resolution.
138 NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit ///< 14 bit resolution.
139 } nrf_saadc_resolution_t;
140
141 #if NRF_SAADC_HAS_AIN_AS_PIN
142 /** @brief Analog input type. */
143 typedef uint32_t nrf_saadc_input_t;
144
145 /** @brief Symbol specifying disconnected analog input. */
146 #define NRF_SAADC_INPUT_DISABLED ((nrf_saadc_input_t)UINT32_MAX)
147 #else
148 /** @brief Input selection for the analog-to-digital converter. */
149 typedef enum
150 {
151 NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC, ///< Not connected.
152 NRF_SAADC_INPUT_AIN0 = SAADC_CH_PSELP_PSELP_AnalogInput0, ///< Analog input 0 (AIN0).
153 NRF_SAADC_INPUT_AIN1 = SAADC_CH_PSELP_PSELP_AnalogInput1, ///< Analog input 1 (AIN1).
154 NRF_SAADC_INPUT_AIN2 = SAADC_CH_PSELP_PSELP_AnalogInput2, ///< Analog input 2 (AIN2).
155 NRF_SAADC_INPUT_AIN3 = SAADC_CH_PSELP_PSELP_AnalogInput3, ///< Analog input 3 (AIN3).
156 NRF_SAADC_INPUT_AIN4 = SAADC_CH_PSELP_PSELP_AnalogInput4, ///< Analog input 4 (AIN4).
157 NRF_SAADC_INPUT_AIN5 = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5).
158 NRF_SAADC_INPUT_AIN6 = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6).
159 NRF_SAADC_INPUT_AIN7 = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7).
160 #if defined(SAADC_CH_PSELP_PSELP_VDD) || defined(__NRFX_DOXYGEN__)
161 NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD, ///< VDD as input.
162 #endif
163 #if defined(SAADC_CH_PSELP_PSELP_VDDHDIV5) || defined(__NRFX_DOXYGEN__)
164 NRF_SAADC_INPUT_VDDHDIV5 = SAADC_CH_PSELP_PSELP_VDDHDIV5 ///< VDDH/5 as input.
165 #endif
166 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput8) || defined(__NRFX_DOXYGEN__)
167 NRF_SAADC_INPUT_AIN8 = SAADC_CH_PSELP_PSELP_AnalogInput8, ///< Analog input 8 (AIN8).
168 #endif
169 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput9) || defined(__NRFX_DOXYGEN__)
170 NRF_SAADC_INPUT_AIN9 = SAADC_CH_PSELP_PSELP_AnalogInput9, ///< Analog input 9 (AIN9).
171 #endif
172 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput10) || defined(__NRFX_DOXYGEN__)
173 NRF_SAADC_INPUT_AIN10 = SAADC_CH_PSELP_PSELP_AnalogInput10, ///< Analog input 10 (AIN10).
174 #endif
175 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput11) || defined(__NRFX_DOXYGEN__)
176 NRF_SAADC_INPUT_AIN11 = SAADC_CH_PSELP_PSELP_AnalogInput11, ///< Analog input 11 (AIN11).
177 #endif
178 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput12) || defined(__NRFX_DOXYGEN__)
179 NRF_SAADC_INPUT_AIN12 = SAADC_CH_PSELP_PSELP_AnalogInput12, ///< Analog input 12 (AIN12).
180 #endif
181 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput13) || defined(__NRFX_DOXYGEN__)
182 NRF_SAADC_INPUT_AIN13 = SAADC_CH_PSELP_PSELP_AnalogInput13, ///< Analog input 13 (AIN13).
183 #endif
184 } nrf_saadc_input_t;
185 #endif
186
187 /** @brief Analog-to-digital converter oversampling mode. */
188 typedef enum
189 {
190 NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass, ///< No oversampling.
191 NRF_SAADC_OVERSAMPLE_2X = SAADC_OVERSAMPLE_OVERSAMPLE_Over2x, ///< Oversample 2x.
192 NRF_SAADC_OVERSAMPLE_4X = SAADC_OVERSAMPLE_OVERSAMPLE_Over4x, ///< Oversample 4x.
193 NRF_SAADC_OVERSAMPLE_8X = SAADC_OVERSAMPLE_OVERSAMPLE_Over8x, ///< Oversample 8x.
194 NRF_SAADC_OVERSAMPLE_16X = SAADC_OVERSAMPLE_OVERSAMPLE_Over16x, ///< Oversample 16x.
195 NRF_SAADC_OVERSAMPLE_32X = SAADC_OVERSAMPLE_OVERSAMPLE_Over32x, ///< Oversample 32x.
196 NRF_SAADC_OVERSAMPLE_64X = SAADC_OVERSAMPLE_OVERSAMPLE_Over64x, ///< Oversample 64x.
197 NRF_SAADC_OVERSAMPLE_128X = SAADC_OVERSAMPLE_OVERSAMPLE_Over128x, ///< Oversample 128x.
198 NRF_SAADC_OVERSAMPLE_256X = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x ///< Oversample 256x.
199 } nrf_saadc_oversample_t;
200
201 #if NRF_SAADC_HAS_CH_CONFIG_RES
202 /** @brief Analog-to-digital converter channel resistor control. */
203 typedef enum
204 {
205 NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass, ///< Bypass resistor ladder.
206 NRF_SAADC_RESISTOR_PULLDOWN = SAADC_CH_CONFIG_RESP_Pulldown, ///< Pull-down to GND.
207 NRF_SAADC_RESISTOR_PULLUP = SAADC_CH_CONFIG_RESP_Pullup, ///< Pull-up to VDD.
208 #if defined(SAADC_CH_CONFIG_RESP_VDD1_2) || defined(__NRFX_DOXYGEN__)
209 NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDD1_2, ///< Set input at VDD/2.
210 #endif
211 #if defined(SAADC_CH_CONFIG_RESP_VDDAO1V8div2)
212 NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDDAO1V8div2, ///< Set input at VDD/2.
213 #endif
214 } nrf_saadc_resistor_t;
215 #endif
216
217 /** @brief Gain factor of the analog-to-digital converter input. */
218 typedef enum
219 {
220 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_6) || defined(__NRFX_DOXYGEN__)
221 NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6.
222 #endif
223 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_5) || defined(__NRFX_DOXYGEN__)
224 NRF_SAADC_GAIN1_5 = SAADC_CH_CONFIG_GAIN_Gain1_5, ///< Gain factor 1/5.
225 #endif
226 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_4) || defined(__NRFX_DOXYGEN__)
227 NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4.
228 #endif
229 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_3) || defined(__NRFX_DOXYGEN__)
230 NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3.
231 #endif
232 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_2) || defined(__NRFX_DOXYGEN__)
233 NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2.
234 #endif
235 #if defined(SAADC_CH_CONFIG_GAIN_Gain2_3) || defined(__NRFX_DOXYGEN__)
236 NRF_SAADC_GAIN2_3 = SAADC_CH_CONFIG_GAIN_Gain2_3, ///< Gain factor 2/3.
237 #endif
238 NRF_SAADC_GAIN1 = SAADC_CH_CONFIG_GAIN_Gain1, ///< Gain factor 1.
239 NRF_SAADC_GAIN2 = SAADC_CH_CONFIG_GAIN_Gain2, ///< Gain factor 2.
240 #if defined(SAADC_CH_CONFIG_GAIN_Gain4) || defined(__NRFX_DOXYGEN__)
241 NRF_SAADC_GAIN4 = SAADC_CH_CONFIG_GAIN_Gain4, ///< Gain factor 4.
242 #endif
243 } nrf_saadc_gain_t;
244
245 /** @brief Reference selection for the analog-to-digital converter. */
246 typedef enum
247 {
248 #if defined(SAADC_CH_CONFIG_REFSEL_Internal) || defined(__NRFX_DOXYGEN__)
249 NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference.
250 #endif
251 #if defined(SAADC_CH_CONFIG_REFSEL_VDD1_4) || defined(__NRFX_DOXYGEN__)
252 NRF_SAADC_REFERENCE_VDD4 = SAADC_CH_CONFIG_REFSEL_VDD1_4 ///< VDD/4 as reference.
253 #endif
254 #if defined(SAADC_CH_CONFIG_REFSEL_External) || defined(__NRFX_DOXYGEN__)
255 NRF_SAADC_REFERENCE_EXTERNAL = SAADC_CH_CONFIG_REFSEL_External, ///< External reference.
256 #endif
257 } nrf_saadc_reference_t;
258
259 #if NRF_SAADC_HAS_ACQTIME_ENUM
260 /** @brief Analog-to-digital converter acquisition time. */
261 typedef enum
262 {
263 NRF_SAADC_ACQTIME_3US = SAADC_CH_CONFIG_TACQ_3us, ///< 3 us.
264 NRF_SAADC_ACQTIME_5US = SAADC_CH_CONFIG_TACQ_5us, ///< 5 us.
265 NRF_SAADC_ACQTIME_10US = SAADC_CH_CONFIG_TACQ_10us, ///< 10 us.
266 NRF_SAADC_ACQTIME_15US = SAADC_CH_CONFIG_TACQ_15us, ///< 15 us.
267 NRF_SAADC_ACQTIME_20US = SAADC_CH_CONFIG_TACQ_20us, ///< 20 us.
268 NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us ///< 40 us.
269 } nrf_saadc_acqtime_t;
270 #else
271 typedef uint16_t nrf_saadc_acqtime_t;
272 #endif
273
274 /** @brief Analog-to-digital converter channel mode. */
275 typedef enum
276 {
277 NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE, ///< Single-ended mode. PSELN will be ignored, negative input to ADC shorted to GND.
278 NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode.
279 } nrf_saadc_mode_t;
280
281 /** @brief Analog-to-digital converter channel burst mode. */
282 typedef enum
283 {
284 NRF_SAADC_BURST_DISABLED = SAADC_CH_CONFIG_BURST_Disabled, ///< Burst mode is disabled (normal operation).
285 NRF_SAADC_BURST_ENABLED = SAADC_CH_CONFIG_BURST_Enabled ///< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.
286 } nrf_saadc_burst_t;
287
288 /** @brief Analog-to-digital converter tasks. */
289 typedef enum
290 {
291 NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_START), ///< Start the ADC and prepare the result buffer in RAM.
292 NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any ongoing conversion.
293 NRF_SAADC_TASK_SAMPLE = offsetof(NRF_SAADC_Type, TASKS_SAMPLE), ///< Take one ADC sample. If scan is enabled, all channels are sampled.
294 NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration.
295 } nrf_saadc_task_t;
296
297 /** @brief Analog-to-digital converter events. */
298 typedef enum
299 {
300 NRF_SAADC_EVENT_STARTED = offsetof(NRF_SAADC_Type, EVENTS_STARTED), ///< The ADC has started.
301 #if NRF_SAADC_HAS_DMA_EVENTS
302 NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_DMA.END), ///< The ADC has filled up the result buffer.
303 #else
304 NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_END), ///< The ADC has filled up the result buffer.
305 #endif
306 NRF_SAADC_EVENT_DONE = offsetof(NRF_SAADC_Type, EVENTS_DONE), ///< A conversion task has been completed.
307 NRF_SAADC_EVENT_RESULTDONE = offsetof(NRF_SAADC_Type, EVENTS_RESULTDONE), ///< A result is ready to get transferred to RAM.
308 NRF_SAADC_EVENT_CALIBRATEDONE = offsetof(NRF_SAADC_Type, EVENTS_CALIBRATEDONE), ///< Calibration is complete.
309 NRF_SAADC_EVENT_STOPPED = offsetof(NRF_SAADC_Type, EVENTS_STOPPED), ///< The ADC has stopped.
310 NRF_SAADC_EVENT_CH0_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITH), ///< Last result is equal or above CH[0].LIMIT.HIGH.
311 NRF_SAADC_EVENT_CH0_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITL), ///< Last result is equal or below CH[0].LIMIT.LOW.
312 NRF_SAADC_EVENT_CH1_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITH), ///< Last result is equal or above CH[1].LIMIT.HIGH.
313 NRF_SAADC_EVENT_CH1_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITL), ///< Last result is equal or below CH[1].LIMIT.LOW.
314 NRF_SAADC_EVENT_CH2_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITH), ///< Last result is equal or above CH[2].LIMIT.HIGH.
315 NRF_SAADC_EVENT_CH2_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL), ///< Last result is equal or below CH[2].LIMIT.LOW.
316 NRF_SAADC_EVENT_CH3_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH), ///< Last result is equal or above CH[3].LIMIT.HIGH.
317 NRF_SAADC_EVENT_CH3_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL), ///< Last result is equal or below CH[3].LIMIT.LOW.
318 NRF_SAADC_EVENT_CH4_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH), ///< Last result is equal or above CH[4].LIMIT.HIGH.
319 NRF_SAADC_EVENT_CH4_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL), ///< Last result is equal or below CH[4].LIMIT.LOW.
320 NRF_SAADC_EVENT_CH5_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH), ///< Last result is equal or above CH[5].LIMIT.HIGH.
321 NRF_SAADC_EVENT_CH5_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITL), ///< Last result is equal or below CH[5].LIMIT.LOW.
322 NRF_SAADC_EVENT_CH6_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITH), ///< Last result is equal or above CH[6].LIMIT.HIGH.
323 NRF_SAADC_EVENT_CH6_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL), ///< Last result is equal or below CH[6].LIMIT.LOW.
324 NRF_SAADC_EVENT_CH7_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH), ///< Last result is equal or above CH[7].LIMIT.HIGH.
325 NRF_SAADC_EVENT_CH7_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL) ///< Last result is equal or below CH[7].LIMIT.LOW.
326 } nrf_saadc_event_t;
327
328 /** @brief Analog-to-digital converter interrupt masks. */
329 typedef enum
330 {
331 NRF_SAADC_INT_STARTED = SAADC_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
332 #if NRF_SAADC_HAS_DMA_EVENTS
333 NRF_SAADC_INT_END = SAADC_INTENSET_DMAEND_Msk, ///< Interrupt on EVENTS_END event.
334 #else
335 NRF_SAADC_INT_END = SAADC_INTENSET_END_Msk, ///< Interrupt on EVENTS_END event.
336 #endif
337 NRF_SAADC_INT_DONE = SAADC_INTENSET_DONE_Msk, ///< Interrupt on EVENTS_DONE event.
338 NRF_SAADC_INT_RESULTDONE = SAADC_INTENSET_RESULTDONE_Msk, ///< Interrupt on EVENTS_RESULTDONE event.
339 NRF_SAADC_INT_CALIBRATEDONE = SAADC_INTENSET_CALIBRATEDONE_Msk, ///< Interrupt on EVENTS_CALIBRATEDONE event.
340 NRF_SAADC_INT_STOPPED = SAADC_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event.
341 NRF_SAADC_INT_CH0LIMITH = SAADC_INTENSET_CH0LIMITH_Msk, ///< Interrupt on EVENTS_CH[0].LIMITH event.
342 NRF_SAADC_INT_CH0LIMITL = SAADC_INTENSET_CH0LIMITL_Msk, ///< Interrupt on EVENTS_CH[0].LIMITL event.
343 NRF_SAADC_INT_CH1LIMITH = SAADC_INTENSET_CH1LIMITH_Msk, ///< Interrupt on EVENTS_CH[1].LIMITH event.
344 NRF_SAADC_INT_CH1LIMITL = SAADC_INTENSET_CH1LIMITL_Msk, ///< Interrupt on EVENTS_CH[1].LIMITL event.
345 NRF_SAADC_INT_CH2LIMITH = SAADC_INTENSET_CH2LIMITH_Msk, ///< Interrupt on EVENTS_CH[2].LIMITH event.
346 NRF_SAADC_INT_CH2LIMITL = SAADC_INTENSET_CH2LIMITL_Msk, ///< Interrupt on EVENTS_CH[2].LIMITL event.
347 NRF_SAADC_INT_CH3LIMITH = SAADC_INTENSET_CH3LIMITH_Msk, ///< Interrupt on EVENTS_CH[3].LIMITH event.
348 NRF_SAADC_INT_CH3LIMITL = SAADC_INTENSET_CH3LIMITL_Msk, ///< Interrupt on EVENTS_CH[3].LIMITL event.
349 NRF_SAADC_INT_CH4LIMITH = SAADC_INTENSET_CH4LIMITH_Msk, ///< Interrupt on EVENTS_CH[4].LIMITH event.
350 NRF_SAADC_INT_CH4LIMITL = SAADC_INTENSET_CH4LIMITL_Msk, ///< Interrupt on EVENTS_CH[4].LIMITL event.
351 NRF_SAADC_INT_CH5LIMITH = SAADC_INTENSET_CH5LIMITH_Msk, ///< Interrupt on EVENTS_CH[5].LIMITH event.
352 NRF_SAADC_INT_CH5LIMITL = SAADC_INTENSET_CH5LIMITL_Msk, ///< Interrupt on EVENTS_CH[5].LIMITL event.
353 NRF_SAADC_INT_CH6LIMITH = SAADC_INTENSET_CH6LIMITH_Msk, ///< Interrupt on EVENTS_CH[6].LIMITH event.
354 NRF_SAADC_INT_CH6LIMITL = SAADC_INTENSET_CH6LIMITL_Msk, ///< Interrupt on EVENTS_CH[6].LIMITL event.
355 NRF_SAADC_INT_CH7LIMITH = SAADC_INTENSET_CH7LIMITH_Msk, ///< Interrupt on EVENTS_CH[7].LIMITH event.
356 NRF_SAADC_INT_CH7LIMITL = SAADC_INTENSET_CH7LIMITL_Msk, ///< Interrupt on EVENTS_CH[7].LIMITL event.
357 NRF_SAADC_INT_ALL = 0x7FFFFFFFUL ///< Mask of all interrupts.
358 } nrf_saadc_int_mask_t;
359
360 /** @brief Analog-to-digital converter value limit type. */
361 typedef enum
362 {
363 NRF_SAADC_LIMIT_LOW = 0, ///< Low limit type.
364 NRF_SAADC_LIMIT_HIGH = 1 ///< High limit type.
365 } nrf_saadc_limit_t;
366
367 #if NRFX_API_VER_AT_LEAST(3, 2, 0) || defined(__NRFX_DOXYGEN__)
368 /** @brief Type of a single ADC conversion result. */
369 typedef void nrf_saadc_value_t;
370 #else
371 typedef uint16_t nrf_saadc_value_t;
372 #endif
373
374 /** @brief Analog-to-digital converter configuration structure. */
375 typedef struct
376 {
377 nrf_saadc_resolution_t resolution; ///< Resolution of samples.
378 nrf_saadc_oversample_t oversample; ///< Oversampling configuration.
379 nrf_saadc_value_t * buffer; ///< Pointer to sample buffer.
380 uint32_t buffer_size; ///< Size of the sample buffer.
381 } nrf_saadc_config_t;
382
383 /** @brief Analog-to-digital converter channel configuration structure. */
384 typedef struct
385 {
386 #if NRF_SAADC_HAS_CH_CONFIG_RES
387 nrf_saadc_resistor_t resistor_p; ///< Resistor value on positive input.
388 nrf_saadc_resistor_t resistor_n; ///< Resistor value on negative input.
389 #endif
390 nrf_saadc_gain_t gain; ///< Gain control value.
391 nrf_saadc_reference_t reference; ///< Reference control value.
392 nrf_saadc_acqtime_t acq_time; ///< Acquisition time.
393 nrf_saadc_mode_t mode; ///< SAADC mode. Single-ended or differential.
394 nrf_saadc_burst_t burst; ///< Burst mode configuration.
395 #if NRF_SAADC_HAS_CONVTIME
396 uint8_t conv_time; ///< Conversion time.
397 #endif
398 } nrf_saadc_channel_config_t;
399
400
401 /**
402 * @brief Function for triggering the specified SAADC task.
403 *
404 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
405 * @param[in] task SAADC task.
406 */
407 NRF_STATIC_INLINE void nrf_saadc_task_trigger(NRF_SAADC_Type * p_reg,
408 nrf_saadc_task_t task);
409
410 /**
411 * @brief Function for getting the address of the specified SAADC task register.
412 *
413 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
414 * @param[in] task SAADC task.
415 *
416 * @return Address of the specified SAADC task.
417 */
418 NRF_STATIC_INLINE uint32_t nrf_saadc_task_address_get(NRF_SAADC_Type const * p_reg,
419 nrf_saadc_task_t task);
420
421 /**
422 * @brief Function for retrieving the state of the SAADC event.
423 *
424 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
425 * @param[in] event Event to be checked.
426 *
427 * @retval true The event has been generated.
428 * @retval false The event has not been generated.
429 */
430 NRF_STATIC_INLINE bool nrf_saadc_event_check(NRF_SAADC_Type const * p_reg,
431 nrf_saadc_event_t event);
432
433 /**
434 * @brief Function for clearing the specific SAADC event.
435 *
436 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
437 * @param[in] event SAADC event.
438 */
439 NRF_STATIC_INLINE void nrf_saadc_event_clear(NRF_SAADC_Type * p_reg,
440 nrf_saadc_event_t event);
441
442 /**
443 * @brief Function for getting the address of the specified SAADC event register.
444 *
445 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
446 * @param[in] event SAADC event.
447 *
448 * @return Address of the specified SAADC event.
449 */
450 NRF_STATIC_INLINE uint32_t nrf_saadc_event_address_get(NRF_SAADC_Type const * p_reg,
451 nrf_saadc_event_t event);
452
453 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
454 /**
455 * @brief Function for setting the subscribe configuration for a given
456 * SAADC task.
457 *
458 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
459 * @param[in] task Task for which to set the configuration.
460 * @param[in] channel Channel through which to subscribe events.
461 */
462 NRF_STATIC_INLINE void nrf_saadc_subscribe_set(NRF_SAADC_Type * p_reg,
463 nrf_saadc_task_t task,
464 uint8_t channel);
465
466 /**
467 * @brief Function for clearing the subscribe configuration for a given
468 * SAADC task.
469 *
470 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
471 * @param[in] task Task for which to clear the configuration.
472 */
473 NRF_STATIC_INLINE void nrf_saadc_subscribe_clear(NRF_SAADC_Type * p_reg,
474 nrf_saadc_task_t task);
475
476 /**
477 * @brief Function for setting the publish configuration for a given
478 * SAADC event.
479 *
480 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
481 * @param[in] event Event for which to set the configuration.
482 * @param[in] channel Channel through which to publish the event.
483 */
484 NRF_STATIC_INLINE void nrf_saadc_publish_set(NRF_SAADC_Type * p_reg,
485 nrf_saadc_event_t event,
486 uint8_t channel);
487
488 /**
489 * @brief Function for clearing the publish configuration for a given
490 * SAADC event.
491 *
492 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
493 * @param[in] event Event for which to clear the configuration.
494 */
495 NRF_STATIC_INLINE void nrf_saadc_publish_clear(NRF_SAADC_Type * p_reg,
496 nrf_saadc_event_t event);
497 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
498
499 /**
500 * @brief Function for getting the SAADC channel monitoring limit events.
501 *
502 * @param[in] channel Channel number.
503 * @param[in] limit_type Low limit or high limit.
504 *
505 * @return The SAADC channel monitoring limit event.
506 */
507 NRF_STATIC_INLINE nrf_saadc_event_t nrf_saadc_limit_event_get(uint8_t channel,
508 nrf_saadc_limit_t limit_type);
509
510 /**
511 * @brief Function for configuring the input pins for the specified SAADC channel.
512 *
513 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
514 * @param[in] channel Channel number.
515 * @param[in] pselp Positive input.
516 * @param[in] pseln Negative input. Set to @ref NRF_SAADC_INPUT_DISABLED in single ended mode.
517 */
518 NRF_STATIC_INLINE void nrf_saadc_channel_input_set(NRF_SAADC_Type * p_reg,
519 uint8_t channel,
520 nrf_saadc_input_t pselp,
521 nrf_saadc_input_t pseln);
522
523 /**
524 * @brief Function for configuring the positive input pin for the specified SAADC channel.
525 *
526 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
527 * @param[in] channel Channel number.
528 * @param[in] pselp Positive input.
529 */
530 NRF_STATIC_INLINE void nrf_saadc_channel_pos_input_set(NRF_SAADC_Type * p_reg,
531 uint8_t channel,
532 nrf_saadc_input_t pselp);
533
534 /**
535 * @brief Function for setting the SAADC channel monitoring limits.
536 *
537 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
538 * @param[in] channel Channel number.
539 * @param[in] low Low limit.
540 * @param[in] high High limit.
541 */
542 NRF_STATIC_INLINE void nrf_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,
543 uint8_t channel,
544 int16_t low,
545 int16_t high);
546
547 /**
548 * @brief Function for setting the configuration of SAADC interrupts.
549 *
550 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
551 * @param[in] mask Interrupts configuration to be set.
552 * Use @ref nrf_saadc_int_mask_t values for bit masking.
553 */
554 NRF_STATIC_INLINE void nrf_saadc_int_set(NRF_SAADC_Type * p_reg, uint32_t mask);
555
556 /**
557 * @brief Function for enabling specified SAADC interrupts.
558 *
559 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
560 * @param[in] mask Mask of interrupts to be enabled.
561 * Use @ref nrf_saadc_int_mask_t values for bit masking.
562 */
563 NRF_STATIC_INLINE void nrf_saadc_int_enable(NRF_SAADC_Type * p_reg, uint32_t mask);
564
565 /**
566 * @brief Function for checking if the specified interrupts are enabled.
567 *
568 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
569 * @param[in] mask Mask of interrupts to be checked.
570 * Use @ref nrf_saadc_int_mask_t values for bit masking.
571 *
572 * @return Mask of enabled interrupts.
573 */
574 NRF_STATIC_INLINE uint32_t nrf_saadc_int_enable_check(NRF_SAADC_Type const * p_reg, uint32_t mask);
575
576 /**
577 * @brief Function for disabling specified interrupts.
578 *
579 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
580 * @param[in] mask Mask of interrupts to be disabled.
581 * Use @ref nrf_saadc_int_mask_t values for bit masking.
582 */
583 NRF_STATIC_INLINE void nrf_saadc_int_disable(NRF_SAADC_Type * p_reg, uint32_t mask);
584
585 /**
586 * @brief Function for generating masks for SAADC channel limit interrupts.
587 *
588 * @param[in] channel SAADC channel number.
589 * @param[in] limit_type Limit type.
590 *
591 * @return Interrupt mask.
592 */
593 NRF_STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel,
594 nrf_saadc_limit_t limit_type);
595
596 /**
597 * @brief Function for checking whether the SAADC is busy.
598 *
599 * This function checks whether the analog-to-digital converter is busy with a conversion.
600 *
601 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
602 *
603 * @retval true The SAADC is busy.
604 * @retval false The SAADC is not busy.
605 */
606 NRF_STATIC_INLINE bool nrf_saadc_busy_check(NRF_SAADC_Type const * p_reg);
607
608 /**
609 * @brief Function for enabling the SAADC.
610 *
611 * The analog-to-digital converter must be enabled before use.
612 *
613 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
614 */
615 NRF_STATIC_INLINE void nrf_saadc_enable(NRF_SAADC_Type * p_reg);
616
617 /**
618 * @brief Function for disabling the SAADC.
619 *
620 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
621 */
622 NRF_STATIC_INLINE void nrf_saadc_disable(NRF_SAADC_Type * p_reg);
623
624 /**
625 * @brief Function for checking if the SAADC is enabled.
626 *
627 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
628 *
629 * @retval true The SAADC is enabled.
630 * @retval false The SAADC is not enabled.
631 */
632 NRF_STATIC_INLINE bool nrf_saadc_enable_check(NRF_SAADC_Type const * p_reg);
633
634 /**
635 * @brief Function for initializing the SAADC result buffer.
636 *
637 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
638 * @param[in] p_buffer Pointer to the result buffer.
639 * @param[in] size Size of the buffer (in 8-bit or 16-bit samples).
640 */
641 NRF_STATIC_INLINE void nrf_saadc_buffer_init(NRF_SAADC_Type * p_reg,
642 nrf_saadc_value_t * p_buffer,
643 uint32_t size);
644
645 /**
646 * @brief Function for setting the SAADC result buffer pointer.
647 *
648 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
649 * @param[in] p_buffer Pointer to the result buffer.
650 */
651 NRF_STATIC_INLINE void nrf_saadc_buffer_pointer_set(NRF_SAADC_Type * p_reg,
652 nrf_saadc_value_t * p_buffer);
653
654 /**
655 * @brief Function for getting the SAADC result buffer pointer.
656 *
657 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
658 *
659 * @return Pointer to the result buffer.
660 */
661 NRF_STATIC_INLINE nrf_saadc_value_t * nrf_saadc_buffer_pointer_get(NRF_SAADC_Type const * p_reg);
662
663 /**
664 * @brief Function for getting the number of samples written to the result
665 * buffer since the previous START task.
666 *
667 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
668 *
669 * @return Number of 8-bit or 16-bit samples written to the buffer.
670 */
671 NRF_STATIC_INLINE uint16_t nrf_saadc_amount_get(NRF_SAADC_Type const * p_reg);
672
673 /**
674 * @brief Function for setting the SAADC sample resolution.
675 *
676 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
677 * @param[in] resolution Bit resolution.
678 */
679 NRF_STATIC_INLINE void nrf_saadc_resolution_set(NRF_SAADC_Type * p_reg,
680 nrf_saadc_resolution_t resolution);
681
682 /**
683 * @brief Function for getting the SAADC sample resolution.
684 *
685 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
686 *
687 * @return Sample resolution.
688 */
689 NRF_STATIC_INLINE nrf_saadc_resolution_t nrf_saadc_resolution_get(NRF_SAADC_Type const * p_reg);
690
691 /**
692 * @brief Function for configuring the oversampling feature.
693 *
694 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
695 * @param[in] oversample Oversampling mode.
696 */
697 NRF_STATIC_INLINE void nrf_saadc_oversample_set(NRF_SAADC_Type * p_reg,
698 nrf_saadc_oversample_t oversample);
699
700 /**
701 * @brief Function for getting the oversampling feature configuration.
702 *
703 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
704 *
705 * @return Oversampling configuration.
706 */
707 NRF_STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(NRF_SAADC_Type const * p_reg);
708
709 /**
710 * @brief Function for getting the sample count needed for one averaged result for a given
711 * oversampling configuration.
712 *
713 * @param[in] oversample Oversampling configuration.
714 *
715 * @return Sample count.
716 */
717 NRF_STATIC_INLINE uint32_t nrf_saadc_oversample_sample_count_get(nrf_saadc_oversample_t oversample);
718
719 /**
720 * @brief Function for enabling the continuous sampling.
721 *
722 * This function configures the SAADC internal timer to automatically take new samples at a fixed
723 * sample rate. Trigger the START task to begin continuous sampling. To stop the sampling, trigger
724 * the STOP task.
725 *
726 * @note The internal timer can only be used when a single input channel is enabled.
727 *
728 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
729 * @param[in] cc Capture and compare value. Sample rate is 16 MHz/cc.
730 * Valid @c CC range is from 80 to 2047.
731 */
732 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_enable(NRF_SAADC_Type * p_reg,
733 uint16_t cc);
734
735 /**
736 * @brief Function for checking if the continuous sampling is enabled.
737 *
738 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
739 *
740 * @retval true The continuous sampling is enabled.
741 * @retval false The continuous sampling is disabled.
742 */
743 NRF_STATIC_INLINE bool nrf_saadc_continuous_mode_enable_check(NRF_SAADC_Type const * p_reg);
744
745 /**
746 * @brief Function for disabling the continuous sampling.
747 *
748 * New samples can still be acquired by manually triggering the SAMPLE task or by PPI.
749 *
750 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
751 */
752 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_disable(NRF_SAADC_Type * p_reg);
753
754 #if NRF_SAADC_HAS_LIN_CAL
755 /**
756 * @brief Function for setting linearity calibration coefficient.
757 *
758 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
759 * @param[in] index Coefficient number.
760 * @param[in] coeff Value of the coefficient.
761 */
762 NRF_STATIC_INLINE void nrf_saadc_linearity_calibration_coeff_set(NRF_SAADC_Type * p_reg,
763 uint8_t index,
764 uint32_t coeff);
765
766 /**
767 * @brief Function for getting linearity calibration coefficient.
768 *
769 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
770 * @param[in] index Coefficient number.
771 *
772 * @return Value of the coefficient.
773 */
774 NRF_STATIC_INLINE uint32_t nrf_saadc_linearity_calibration_coeff_get(NRF_SAADC_Type const * p_reg,
775 uint8_t index);
776 #endif
777
778 /**
779 * @brief Function for initializing the SAADC channel.
780 *
781 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
782 * @param[in] channel Channel number.
783 * @param[in] config Pointer to the channel configuration structure.
784 */
785 NRF_STATIC_INLINE void nrf_saadc_channel_init(NRF_SAADC_Type * p_reg,
786 uint8_t channel,
787 nrf_saadc_channel_config_t const * config);
788
789 /**
790 * @brief Function for configuring the burst mode for the specified channel.
791 *
792 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
793 * @param[in] channel Channel number.
794 * @param[in] burst Burst mode setting.
795 */
796 NRF_STATIC_INLINE void nrf_saadc_burst_set(NRF_SAADC_Type * p_reg,
797 uint8_t channel,
798 nrf_saadc_burst_t burst);
799
800 /**
801 * @brief Function for getting the minimum value of the conversion result.
802 *
803 * The minimum value of the conversion result depends on the configured resolution.
804 *
805 * @param[in] resolution Bit resolution.
806 *
807 * @return Minimum value of the conversion result.
808 */
809 NRF_STATIC_INLINE int16_t nrf_saadc_value_min_get(nrf_saadc_resolution_t resolution);
810
811 /**
812 * @brief Function for getting the maximum value of the conversion result.
813 *
814 * The maximum value of the conversion result depends on the configured resolution.
815 *
816 * @param[in] resolution Bit resolution.
817 *
818 * @return Maximum value of the conversion result.
819 */
820 NRF_STATIC_INLINE int16_t nrf_saadc_value_max_get(nrf_saadc_resolution_t resolution);
821
822 #ifndef NRF_DECLARE_ONLY
823
nrf_saadc_task_trigger(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task)824 NRF_STATIC_INLINE void nrf_saadc_task_trigger(NRF_SAADC_Type * p_reg, nrf_saadc_task_t task)
825 {
826 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
827 }
828
nrf_saadc_task_address_get(NRF_SAADC_Type const * p_reg,nrf_saadc_task_t task)829 NRF_STATIC_INLINE uint32_t nrf_saadc_task_address_get(NRF_SAADC_Type const * p_reg,
830 nrf_saadc_task_t task)
831 {
832 return nrf_task_event_address_get(p_reg, task);
833 }
834
nrf_saadc_event_check(NRF_SAADC_Type const * p_reg,nrf_saadc_event_t event)835 NRF_STATIC_INLINE bool nrf_saadc_event_check(NRF_SAADC_Type const * p_reg, nrf_saadc_event_t event)
836 {
837 return nrf_event_check(p_reg, event);
838 }
839
nrf_saadc_event_clear(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event)840 NRF_STATIC_INLINE void nrf_saadc_event_clear(NRF_SAADC_Type * p_reg, nrf_saadc_event_t event)
841 {
842 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
843 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
844 }
845
nrf_saadc_event_address_get(NRF_SAADC_Type const * p_reg,nrf_saadc_event_t event)846 NRF_STATIC_INLINE uint32_t nrf_saadc_event_address_get(NRF_SAADC_Type const * p_reg,
847 nrf_saadc_event_t event)
848 {
849 return nrf_task_event_address_get(p_reg, event);
850 }
851
852 #if defined(DPPI_PRESENT)
nrf_saadc_subscribe_set(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task,uint8_t channel)853 NRF_STATIC_INLINE void nrf_saadc_subscribe_set(NRF_SAADC_Type * p_reg,
854 nrf_saadc_task_t task,
855 uint8_t channel)
856 {
857 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
858 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
859 }
860
nrf_saadc_subscribe_clear(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task)861 NRF_STATIC_INLINE void nrf_saadc_subscribe_clear(NRF_SAADC_Type * p_reg, nrf_saadc_task_t task)
862 {
863 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
864 }
865
nrf_saadc_publish_set(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event,uint8_t channel)866 NRF_STATIC_INLINE void nrf_saadc_publish_set(NRF_SAADC_Type * p_reg,
867 nrf_saadc_event_t event,
868 uint8_t channel)
869 {
870 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
871 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
872 }
873
nrf_saadc_publish_clear(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event)874 NRF_STATIC_INLINE void nrf_saadc_publish_clear(NRF_SAADC_Type * p_reg, nrf_saadc_event_t event)
875 {
876 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
877 }
878 #endif // defined(DPPI_PRESENT)
879
nrf_saadc_limit_event_get(uint8_t channel,nrf_saadc_limit_t limit_type)880 NRF_STATIC_INLINE nrf_saadc_event_t nrf_saadc_limit_event_get(uint8_t channel,
881 nrf_saadc_limit_t limit_type)
882 {
883 if (limit_type == NRF_SAADC_LIMIT_HIGH)
884 {
885 return (nrf_saadc_event_t)NRFX_OFFSETOF(NRF_SAADC_Type, EVENTS_CH[channel].LIMITH);
886 }
887 else
888 {
889 return (nrf_saadc_event_t)NRFX_OFFSETOF(NRF_SAADC_Type, EVENTS_CH[channel].LIMITL);
890 }
891 }
892
nrf_saadc_channel_input_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_input_t pselp,nrf_saadc_input_t pseln)893 NRF_STATIC_INLINE void nrf_saadc_channel_input_set(NRF_SAADC_Type * p_reg,
894 uint8_t channel,
895 nrf_saadc_input_t pselp,
896 nrf_saadc_input_t pseln)
897 {
898 #if NRF_SAADC_HAS_AIN_AS_PIN
899 p_reg->CH[channel].PSELN = (pseln != NRF_SAADC_INPUT_DISABLED) ?
900 ((NRF_PIN_NUMBER_TO_PIN(pseln) << SAADC_CH_PSELN_PIN_Pos)
901 | (NRF_PIN_NUMBER_TO_PORT(pseln) << SAADC_CH_PSELN_PORT_Pos)
902 | (SAADC_CH_PSELN_CONNECT_AnalogInput << SAADC_CH_PSELN_CONNECT_Pos)
903 ) : 0;
904 p_reg->CH[channel].PSELP = (pselp != NRF_SAADC_INPUT_DISABLED) ?
905 ((NRF_PIN_NUMBER_TO_PIN(pselp) << SAADC_CH_PSELP_PIN_Pos)
906 | (NRF_PIN_NUMBER_TO_PORT(pselp) << SAADC_CH_PSELP_PORT_Pos)
907 | (SAADC_CH_PSELP_CONNECT_AnalogInput << SAADC_CH_PSELP_CONNECT_Pos)
908 ) : 0;
909 #else
910 p_reg->CH[channel].PSELN = pseln;
911 p_reg->CH[channel].PSELP = pselp;
912 #endif
913 }
914
nrf_saadc_channel_pos_input_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_input_t pselp)915 NRF_STATIC_INLINE void nrf_saadc_channel_pos_input_set(NRF_SAADC_Type * p_reg,
916 uint8_t channel,
917 nrf_saadc_input_t pselp)
918 {
919 #if NRF_SAADC_HAS_AIN_AS_PIN
920 p_reg->CH[channel].PSELP = (pselp != NRF_SAADC_INPUT_DISABLED) ?
921 ((NRF_PIN_NUMBER_TO_PIN(pselp) << SAADC_CH_PSELP_PIN_Pos)
922 | (NRF_PIN_NUMBER_TO_PORT(pselp) << SAADC_CH_PSELP_PORT_Pos)
923 | (SAADC_CH_PSELP_CONNECT_AnalogInput << SAADC_CH_PSELP_CONNECT_Pos)
924 ) : 0;
925 #else
926 p_reg->CH[channel].PSELP = pselp;
927 #endif
928 }
929
nrf_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,uint8_t channel,int16_t low,int16_t high)930 NRF_STATIC_INLINE void nrf_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,
931 uint8_t channel,
932 int16_t low,
933 int16_t high)
934 {
935 p_reg->CH[channel].LIMIT = (
936 (((uint32_t) low << SAADC_CH_LIMIT_LOW_Pos) & SAADC_CH_LIMIT_LOW_Msk)
937 | (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk));
938 }
939
nrf_saadc_int_set(NRF_SAADC_Type * p_reg,uint32_t mask)940 NRF_STATIC_INLINE void nrf_saadc_int_set(NRF_SAADC_Type * p_reg, uint32_t mask)
941 {
942 p_reg->INTEN = mask;
943 }
944
nrf_saadc_int_enable(NRF_SAADC_Type * p_reg,uint32_t mask)945 NRF_STATIC_INLINE void nrf_saadc_int_enable(NRF_SAADC_Type * p_reg, uint32_t mask)
946 {
947 p_reg->INTENSET = mask;
948 }
949
nrf_saadc_int_enable_check(NRF_SAADC_Type const * p_reg,uint32_t mask)950 NRF_STATIC_INLINE uint32_t nrf_saadc_int_enable_check(NRF_SAADC_Type const * p_reg, uint32_t mask)
951 {
952 return p_reg->INTENSET & mask;
953 }
954
nrf_saadc_int_disable(NRF_SAADC_Type * p_reg,uint32_t mask)955 NRF_STATIC_INLINE void nrf_saadc_int_disable(NRF_SAADC_Type * p_reg, uint32_t mask)
956 {
957 p_reg->INTENCLR = mask;
958 }
959
nrf_saadc_limit_int_get(uint8_t channel,nrf_saadc_limit_t limit_type)960 NRF_STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel,
961 nrf_saadc_limit_t limit_type)
962 {
963 NRFX_ASSERT(channel < SAADC_CH_NUM);
964 uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ?
965 NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH;
966 return mask << (channel * 2);
967 }
968
nrf_saadc_busy_check(NRF_SAADC_Type const * p_reg)969 NRF_STATIC_INLINE bool nrf_saadc_busy_check(NRF_SAADC_Type const * p_reg)
970 {
971 return (p_reg->STATUS == (SAADC_STATUS_STATUS_Busy << SAADC_STATUS_STATUS_Pos));
972 }
973
nrf_saadc_enable(NRF_SAADC_Type * p_reg)974 NRF_STATIC_INLINE void nrf_saadc_enable(NRF_SAADC_Type * p_reg)
975 {
976 p_reg->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos);
977 }
978
nrf_saadc_disable(NRF_SAADC_Type * p_reg)979 NRF_STATIC_INLINE void nrf_saadc_disable(NRF_SAADC_Type * p_reg)
980 {
981 p_reg->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos);
982 }
983
nrf_saadc_enable_check(NRF_SAADC_Type const * p_reg)984 NRF_STATIC_INLINE bool nrf_saadc_enable_check(NRF_SAADC_Type const * p_reg)
985 {
986 return (p_reg->ENABLE == (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos));
987 }
988
nrf_saadc_buffer_init(NRF_SAADC_Type * p_reg,nrf_saadc_value_t * p_buffer,uint32_t size)989 NRF_STATIC_INLINE void nrf_saadc_buffer_init(NRF_SAADC_Type * p_reg,
990 nrf_saadc_value_t * p_buffer,
991 uint32_t size)
992 {
993 #if (NRF_SAADC_8BIT_SAMPLE_WIDTH == 8)
994 if (nrf_saadc_resolution_get(p_reg) != NRF_SAADC_RESOLUTION_8BIT)
995 {
996 size = size * 2;
997 }
998 #endif
999
1000 #if NRF_SAADC_HAS_DMA_REG
1001 p_reg->DMA.PTR = (uint32_t)p_buffer;
1002 p_reg->DMA.MAXCNT = size;
1003 #else
1004 p_reg->RESULT.PTR = (uint32_t)p_buffer;
1005 p_reg->RESULT.MAXCNT = size;
1006 #endif
1007 }
1008
nrf_saadc_buffer_pointer_set(NRF_SAADC_Type * p_reg,nrf_saadc_value_t * p_buffer)1009 NRF_STATIC_INLINE void nrf_saadc_buffer_pointer_set(NRF_SAADC_Type * p_reg,
1010 nrf_saadc_value_t * p_buffer)
1011 {
1012 #if NRF_SAADC_HAS_DMA_REG
1013 p_reg->DMA.PTR = (uint32_t)p_buffer;
1014 #else
1015 p_reg->RESULT.PTR = (uint32_t)p_buffer;
1016 #endif
1017 }
1018
nrf_saadc_buffer_pointer_get(NRF_SAADC_Type const * p_reg)1019 NRF_STATIC_INLINE nrf_saadc_value_t * nrf_saadc_buffer_pointer_get(NRF_SAADC_Type const * p_reg)
1020 {
1021 #if NRF_SAADC_HAS_DMA_REG
1022 return (nrf_saadc_value_t *)p_reg->DMA.PTR;
1023 #else
1024 return (nrf_saadc_value_t *)p_reg->RESULT.PTR;
1025 #endif
1026 }
1027
nrf_saadc_amount_get(NRF_SAADC_Type const * p_reg)1028 NRF_STATIC_INLINE uint16_t nrf_saadc_amount_get(NRF_SAADC_Type const * p_reg)
1029 {
1030 #if NRF_SAADC_HAS_DMA_REG
1031 uint16_t result = (uint16_t)p_reg->DMA.AMOUNT;
1032 #else
1033 uint16_t result = (uint16_t)p_reg->RESULT.AMOUNT;
1034 #endif
1035
1036 #if (NRF_SAADC_8BIT_SAMPLE_WIDTH == 8)
1037 if (nrf_saadc_resolution_get(p_reg) != NRF_SAADC_RESOLUTION_8BIT)
1038 {
1039 result = result / 2;
1040 }
1041 #endif
1042
1043 return result;
1044 }
1045
nrf_saadc_resolution_set(NRF_SAADC_Type * p_reg,nrf_saadc_resolution_t resolution)1046 NRF_STATIC_INLINE void nrf_saadc_resolution_set(NRF_SAADC_Type * p_reg,
1047 nrf_saadc_resolution_t resolution)
1048 {
1049 p_reg->RESOLUTION = resolution;
1050 }
1051
nrf_saadc_resolution_get(NRF_SAADC_Type const * p_reg)1052 NRF_STATIC_INLINE nrf_saadc_resolution_t nrf_saadc_resolution_get(NRF_SAADC_Type const * p_reg)
1053 {
1054 return (nrf_saadc_resolution_t)p_reg->RESOLUTION;
1055 }
1056
nrf_saadc_oversample_set(NRF_SAADC_Type * p_reg,nrf_saadc_oversample_t oversample)1057 NRF_STATIC_INLINE void nrf_saadc_oversample_set(NRF_SAADC_Type * p_reg,
1058 nrf_saadc_oversample_t oversample)
1059 {
1060 p_reg->OVERSAMPLE = oversample;
1061 }
1062
nrf_saadc_oversample_get(NRF_SAADC_Type const * p_reg)1063 NRF_STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(NRF_SAADC_Type const * p_reg)
1064 {
1065 return (nrf_saadc_oversample_t)p_reg->OVERSAMPLE;
1066 }
1067
nrf_saadc_oversample_sample_count_get(nrf_saadc_oversample_t oversample)1068 NRF_STATIC_INLINE uint32_t nrf_saadc_oversample_sample_count_get(nrf_saadc_oversample_t oversample)
1069 {
1070 return (1 << (uint32_t)oversample);
1071 }
1072
nrf_saadc_continuous_mode_enable(NRF_SAADC_Type * p_reg,uint16_t cc)1073 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_enable(NRF_SAADC_Type * p_reg, uint16_t cc)
1074 {
1075 NRFX_ASSERT((cc >= 80) && (cc <= 2047));
1076 p_reg->SAMPLERATE = (SAADC_SAMPLERATE_MODE_Timers << SAADC_SAMPLERATE_MODE_Pos)
1077 | ((uint32_t)cc << SAADC_SAMPLERATE_CC_Pos);
1078 }
1079
nrf_saadc_continuous_mode_enable_check(NRF_SAADC_Type const * p_reg)1080 NRF_STATIC_INLINE bool nrf_saadc_continuous_mode_enable_check(NRF_SAADC_Type const * p_reg)
1081 {
1082 return (bool)((p_reg->SAMPLERATE & SAADC_SAMPLERATE_MODE_Msk)
1083 == (SAADC_SAMPLERATE_MODE_Timers << SAADC_SAMPLERATE_MODE_Pos));
1084 }
1085
nrf_saadc_continuous_mode_disable(NRF_SAADC_Type * p_reg)1086 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_disable(NRF_SAADC_Type * p_reg)
1087 {
1088 p_reg->SAMPLERATE = SAADC_SAMPLERATE_MODE_Task << SAADC_SAMPLERATE_MODE_Pos;
1089 }
1090
1091 #if NRF_SAADC_HAS_LIN_CAL
nrf_saadc_linearity_calibration_coeff_set(NRF_SAADC_Type * p_reg,uint8_t index,uint32_t coeff)1092 NRF_STATIC_INLINE void nrf_saadc_linearity_calibration_coeff_set(NRF_SAADC_Type * p_reg,
1093 uint8_t index,
1094 uint32_t coeff)
1095 {
1096 NRFX_ASSERT(index < NRF_SAADC_LIN_CAL_MAX_COUNT);
1097 NRFX_ASSERT(coeff <= NRF_SAADC_LIN_CAL_MAX);
1098 p_reg->TRIM.LINCALCOEFF[index] = coeff;
1099 }
1100
nrf_saadc_linearity_calibration_coeff_get(NRF_SAADC_Type const * p_reg,uint8_t index)1101 NRF_STATIC_INLINE uint32_t nrf_saadc_linearity_calibration_coeff_get(NRF_SAADC_Type const * p_reg,
1102 uint8_t index)
1103 {
1104 NRFX_ASSERT(index < NRF_SAADC_LIN_CAL_MAX_COUNT);
1105 return p_reg->TRIM.LINCALCOEFF[index];
1106 }
1107 #endif
1108
nrf_saadc_channel_init(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_channel_config_t const * config)1109 NRF_STATIC_INLINE void nrf_saadc_channel_init(NRF_SAADC_Type * p_reg,
1110 uint8_t channel,
1111 nrf_saadc_channel_config_t const * config)
1112 {
1113 #if !NRF_SAADC_HAS_ACQTIME_ENUM
1114 NRFX_ASSERT(config->acq_time <= NRF_SAADC_ACQTIME_MAX);
1115 #endif
1116 #if NRF_SAADC_HAS_CONVTIME
1117 NRFX_ASSERT(config->conv_time <= NRF_SAADC_CONVTIME_MAX);
1118 #endif
1119 p_reg->CH[channel].CONFIG =
1120 ((config->gain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk)
1121 | ((config->reference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk)
1122 | ((config->acq_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk)
1123 #if NRF_SAADC_HAS_CH_CONFIG_RES
1124 | ((config->resistor_p << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk)
1125 | ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk)
1126 #endif
1127 #if NRF_SAADC_HAS_CONVTIME
1128 | ((config->conv_time << SAADC_CH_CONFIG_TCONV_Pos) & SAADC_CH_CONFIG_TCONV_Msk)
1129 #endif
1130 | ((config->mode << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk)
1131 | ((config->burst << SAADC_CH_CONFIG_BURST_Pos) & SAADC_CH_CONFIG_BURST_Msk);
1132 }
1133
nrf_saadc_burst_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_burst_t burst)1134 NRF_STATIC_INLINE void nrf_saadc_burst_set(NRF_SAADC_Type * p_reg,
1135 uint8_t channel,
1136 nrf_saadc_burst_t burst)
1137 {
1138 p_reg->CH[channel].CONFIG = (p_reg->CH[channel].CONFIG & ~SAADC_CH_CONFIG_BURST_Msk) |
1139 (burst << SAADC_CH_CONFIG_BURST_Pos);
1140 }
1141
nrf_saadc_value_min_get(nrf_saadc_resolution_t resolution)1142 NRF_STATIC_INLINE int16_t nrf_saadc_value_min_get(nrf_saadc_resolution_t resolution)
1143 {
1144 uint8_t res_bits = 0;
1145 switch (resolution)
1146 {
1147 case NRF_SAADC_RESOLUTION_8BIT:
1148 res_bits = 8;
1149 break;
1150 case NRF_SAADC_RESOLUTION_10BIT:
1151 res_bits = 10;
1152 break;
1153 case NRF_SAADC_RESOLUTION_12BIT:
1154 res_bits = 12;
1155 break;
1156 case NRF_SAADC_RESOLUTION_14BIT:
1157 res_bits = 14;
1158 break;
1159 default:
1160 NRFX_ASSERT(false);
1161 }
1162 return (int16_t)(-(1 << res_bits));
1163 }
1164
nrf_saadc_value_max_get(nrf_saadc_resolution_t resolution)1165 NRF_STATIC_INLINE int16_t nrf_saadc_value_max_get(nrf_saadc_resolution_t resolution)
1166 {
1167 uint8_t res_bits = 0;
1168 switch (resolution)
1169 {
1170 case NRF_SAADC_RESOLUTION_8BIT:
1171 res_bits = 8;
1172 break;
1173 case NRF_SAADC_RESOLUTION_10BIT:
1174 res_bits = 10;
1175 break;
1176 case NRF_SAADC_RESOLUTION_12BIT:
1177 res_bits = 12;
1178 break;
1179 case NRF_SAADC_RESOLUTION_14BIT:
1180 res_bits = 14;
1181 break;
1182 default:
1183 NRFX_ASSERT(false);
1184 }
1185 return (int16_t)((1 << res_bits) - 1);
1186 }
1187
1188 #endif // NRF_DECLARE_ONLY
1189
1190 /** @} */
1191
1192 #ifdef __cplusplus
1193 }
1194 #endif
1195
1196 #endif // NRF_SAADC_H_
1197
