1 /*
2 * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_GPIO_H__
35 #define NRF_GPIO_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #ifndef NRF_P0
44 #define NRF_P0 NRF_GPIO
45 #endif
46
47 #define GPIO_PORT_NUM(periph_name, prefix, i, _) i,
48 #define GPIO_REG(periph_name, prefix, i, _) NRFX_CONCAT(NRF_, periph_name, prefix, i),
49 #define GPIO_NUM_OF_PINS(periph_name, prefix, i, _) \
50 NRFX_CONCAT(periph_name, prefix, i, _PIN_NUM)
51
52 #define GPIO_PORT_NUM_LIST {NRFX_FOREACH_PRESENT(P, GPIO_PORT_NUM, (), (), _)}
53 #define GPIO_REG_LIST {NRFX_FOREACH_PRESENT(P, GPIO_REG, (), (), _)}
54 #define NUMBER_OF_PINS (NRFX_FOREACH_PRESENT(P, GPIO_NUM_OF_PINS, (+), (0), _))
55
56 #if !defined(GPIO_REG_LIST)
57 #error "Not supported."
58 #endif
59
60 #if defined(GPIO_PIN_CNF_DRIVE0_Msk)
61 #define GPIO_PIN_CNF_DRIVE1_OFFSET (GPIO_PIN_CNF_DRIVE1_Pos - GPIO_PIN_CNF_DRIVE0_Pos)
62 #endif
63
64 #if defined(NRF52820_XXAA)
65 #include <nrf_erratas.h>
66 #endif
67
68 /*
69 * Macro for generating case code blocks that return token NRF_<periph_name><prefix><i>
70 * for case value equal to <i>.
71 *
72 * Used by NRF_INTERNAL_GPIO_PORT_EXTRACT.
73 */
74 #define NRF_INTERNAL_GPIO_PORT_EXTRACT_1(periph_name, prefix, i, port) \
75 case i: \
76 port = NRFX_CONCAT(NRF_, periph_name, prefix, i); \
77 break;
78
79 /*
80 * Macro for generating case code blocks for switch statement used in function nrf_gpio_pin_port_decode.
81 * It allows extracting the port number relative to the decoded pin.
82 */
83 #define NRF_INTERNAL_GPIO_PORT_EXTRACT(port) \
84 NRFX_FOREACH_PRESENT(P, NRF_INTERNAL_GPIO_PORT_EXTRACT_1, (), (), port)
85
86 /*
87 * Macro for generating case code blocks that set mask to <periph_name><prefix><i>_FEATURE_PINS_PRESENT
88 * for case value equal to <i>.
89 *
90 * Used by NRF_INTERNAL_GPIO_PORT_MASK_SET.
91 */
92 #define NRF_INTERNAL_GPIO_PORT_MASK_SET_1(periph_name, prefix, i, mask) \
93 case i: \
94 mask = NRFX_CONCAT(periph_name, prefix, i, _FEATURE_PINS_PRESENT); \
95 break;
96
97 /*
98 * Macro for generating case code blocks for switch statement used in function nrf_gpio_pin_present_check.
99 * It allows setting the mask to a value associated with the specific port.
100 */
101 #define NRF_INTERNAL_GPIO_PORT_MASK_SET(mask) \
102 NRFX_FOREACH_PRESENT(P, NRF_INTERNAL_GPIO_PORT_MASK_SET_1, (), (), mask)
103
104 /**
105 * @defgroup nrf_gpio_hal GPIO HAL
106 * @{
107 * @ingroup nrf_gpio
108 * @brief Hardware access layer for managing the GPIO peripheral.
109 */
110
111 #if defined(GPIO_LATCH_PIN0_Msk) || defined(__NRFX_DOXYGEN__)
112 /** @brief Symbol indicating whether the functionality of latching GPIO state change is present. */
113 #define NRF_GPIO_LATCH_PRESENT
114 #endif
115
116 #if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(GPIO_PIN_CNF_CTRLSEL_Msk) \
117 || defined(__NRFX_DOXYGEN__)
118 /** @brief Presence of MCU/Subsystem control selection. */
119 #define NRF_GPIO_HAS_SEL 1
120 #else
121 #define NRF_GPIO_HAS_SEL 0
122 #endif
123
124 #if defined(GPIO_PIN_CNF_CTRLSEL_Msk) || defined(__NRFX_DOXYGEN__)
125 /** @brief Presence of MCU/Subsystem control selection for multiple peripherals. */
126 #define NRF_GPIO_HAS_MULTIPERIPH_SEL 1
127 #else
128 #define NRF_GPIO_HAS_MULTIPERIPH_SEL 0
129 #endif
130
131 #if defined(GPIO_PIN_CNF_CLOCKPIN_Msk) || defined(__NRFX_DOXYGEN__)
132 /** @brief Presence of clock pin enable. */
133 #define NRF_GPIO_HAS_CLOCKPIN 1
134 #else
135 #define NRF_GPIO_HAS_CLOCKPIN 0
136 #endif
137
138 #if defined(GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk) || defined(__NRFX_DOXYGEN__)
139 /** @brief Presence of drive control for impedance. */
140 #define NRF_GPIO_HAS_PORT_IMPEDANCE 1
141 #else
142 #define NRF_GPIO_HAS_PORT_IMPEDANCE 0
143 #endif
144
145 #if defined(GPIO_RETAIN_ResetValue) || defined(__NRFX_DOXYGEN__)
146 /** @brief Presence of register retention. */
147 #define NRF_GPIO_HAS_RETENTION 1
148 #else
149 #define NRF_GPIO_HAS_RETENTION 0
150 #endif
151
152 #if defined(GPIO_DETECTMODE_DETECTMODE_Msk) || defined(__NRFX_DOXYGEN__)
153 /** @brief Presence of detect mode. */
154 #define NRF_GPIO_HAS_DETECT_MODE 1
155 #else
156 #define NRF_GPIO_HAS_DETECT_MODE 0
157 #endif
158
159 /** @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. */
160 #define NRF_GPIO_PIN_MAP(port, pin) NRF_PIN_PORT_TO_PIN_NUMBER(pin, port)
161
162 #if NRF_GPIO_HAS_PORT_IMPEDANCE
163 /** @brief Mask of all impedances. */
164 #define NRF_GPIO_PORT_IMPEDANCE_ALL_MASK (GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk | \
165 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk | \
166 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk | \
167 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk | \
168 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk | \
169 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk)
170 #endif
171
172 /** @brief Pin direction definitions. */
173 typedef enum
174 {
175 NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input.
176 NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output.
177 } nrf_gpio_pin_dir_t;
178
179 /** @brief Connection of input buffer. */
180 typedef enum
181 {
182 NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer.
183 NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer.
184 } nrf_gpio_pin_input_t;
185
186 /**
187 * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin
188 * configuration.
189 */
190 typedef enum
191 {
192 NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled.
193 NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled.
194 NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled.
195 } nrf_gpio_pin_pull_t;
196
197 /** @brief Enumerator used for selecting output drive mode. */
198 typedef enum
199 {
200 #if defined(GPIO_PIN_CNF_DRIVE_Msk) || defined(__NRFX_DOXYGEN__)
201 NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< Standard '0', standard '1'.
202 NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< High drive '0', standard '1'.
203 NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< Standard '0', high drive '1'.
204 NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< High drive '0', high drive '1'.
205 NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< Disconnect '0' standard '1'.
206 NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< Disconnect '0', high drive '1'.
207 NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< Standard '0', disconnect '1'.
208 NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< High drive '0', disconnect '1'.
209 #if defined(GPIO_PIN_CNF_DRIVE_E0S1) || defined(__NRFX_DOXYGEN__)
210 NRF_GPIO_PIN_E0S1 = GPIO_PIN_CNF_DRIVE_E0S1, ///< Extra high drive '0', standard '1'.
211 #endif
212 #if defined(GPIO_PIN_CNF_DRIVE_S0E1) || defined(__NRFX_DOXYGEN__)
213 NRF_GPIO_PIN_S0E1 = GPIO_PIN_CNF_DRIVE_S0E1, ///< Standard '0', extra high drive '1'.
214 #endif
215 #if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(__NRFX_DOXYGEN__)
216 NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE_E0E1, ///< Extra high drive '0', extra high drive '1'.
217 #endif
218 #if defined(GPIO_PIN_CNF_DRIVE_E0H1) || defined(__NRFX_DOXYGEN__)
219 NRF_GPIO_PIN_E0H1 = GPIO_PIN_CNF_DRIVE_E0H1, ///< Extra high drive '0', high drive '1'.
220 #endif
221 #if defined(GPIO_PIN_CNF_DRIVE_H0E1) || defined(__NRFX_DOXYGEN__)
222 NRF_GPIO_PIN_H0E1 = GPIO_PIN_CNF_DRIVE_H0E1, ///< High drive '0', extra high drive '1'.
223 #endif
224 #if defined(GPIO_PIN_CNF_DRIVE_D0E1) || defined(__NRFX_DOXYGEN__)
225 NRF_GPIO_PIN_D0E1 = GPIO_PIN_CNF_DRIVE_D0E1, ///< Disconnect '0', extra high drive '1'.
226 #endif
227 #if defined(GPIO_PIN_CNF_DRIVE_E0D1) || defined(__NRFX_DOXYGEN__)
228 NRF_GPIO_PIN_E0D1 = GPIO_PIN_CNF_DRIVE_E0D1, ///< Extra high drive '0', disconnect '1'.
229 #endif
230 #else
231 NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE0_S0 |
232 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
233 NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE0_H0 |
234 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
235 NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE0_S0 |
236 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
237 NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE0_H0 |
238 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
239 NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE0_D0 |
240 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
241 NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE0_D0 |
242 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
243 NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE0_S0 |
244 (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
245 NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE0_H0 |
246 (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
247 NRF_GPIO_PIN_E0S1 = GPIO_PIN_CNF_DRIVE0_E0 |
248 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
249 NRF_GPIO_PIN_S0E1 = GPIO_PIN_CNF_DRIVE0_S0 |
250 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
251 NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE0_E0 |
252 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
253 NRF_GPIO_PIN_E0H1 = GPIO_PIN_CNF_DRIVE0_E0 |
254 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
255 NRF_GPIO_PIN_H0E1 = GPIO_PIN_CNF_DRIVE0_H0 |
256 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
257 NRF_GPIO_PIN_D0E1 = GPIO_PIN_CNF_DRIVE0_D0 |
258 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
259 NRF_GPIO_PIN_E0D1 = GPIO_PIN_CNF_DRIVE0_E0 |
260 (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
261 #endif // defined(GPIO_PIN_CNF_DRIVE_Msk) || defined(__NRFX_DOXYGEN__)
262 } nrf_gpio_pin_drive_t;
263
264 /** @brief Enumerator used for selecting the pin to sense high or low level on the pin input. */
265 typedef enum
266 {
267 NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled.
268 NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level.
269 NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level.
270 } nrf_gpio_pin_sense_t;
271
272 #if NRF_GPIO_HAS_SEL
273 /** @brief Enumerator used for selecting the MCU/Subsystem to control the specified pin. */
274 typedef enum
275 {
276 #if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__)
277 NRF_GPIO_PIN_SEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU.
278 NRF_GPIO_PIN_SEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU.
279 NRF_GPIO_PIN_SEL_PERIPHERAL = GPIO_PIN_CNF_MCUSEL_Peripheral, ///< Pin controlled by dedicated peripheral.
280 #endif
281 #if defined(GPIO_PIN_CNF_MCUSEL_TND) || defined(__NRFX_DOXYGEN__)
282 NRF_GPIO_PIN_SEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
283 #elif defined(GPIO_PIN_CNF_CTRLSEL_TND)
284 NRF_GPIO_PIN_SEL_TND = GPIO_PIN_CNF_CTRLSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
285 #endif
286 #if defined(GPIO_PIN_CNF_CTRLSEL_GPIO) || defined(__NRFX_DOXYGEN__)
287 NRF_GPIO_PIN_SEL_GPIO = GPIO_PIN_CNF_CTRLSEL_GPIO, ///< Pin controlled by GPIO or peripherals with configurable pins.
288 #endif
289 #if defined(GPIO_PIN_CNF_CTRLSEL_VPR) || defined(__NRFX_DOXYGEN__)
290 NRF_GPIO_PIN_SEL_VPR = GPIO_PIN_CNF_CTRLSEL_VPR, ///< Pin controlled by VPR.
291 #endif
292 #if defined(GPIO_PIN_CNF_CTRLSEL_GRTC) || defined(__NRFX_DOXYGEN__)
293 NRF_GPIO_PIN_SEL_GRTC = GPIO_PIN_CNF_CTRLSEL_GRTC, ///< Pin controlled by GRTC peripheral.
294 #endif
295 #if defined(NRF_GPIO_PIN_SEL_EXT)
296 NRF_GPIO_PIN_SEL_EXT
297 #endif
298 } nrf_gpio_pin_sel_t;
299 #endif // NRF_GPIO_HAS_SEL
300
301 #if NRF_GPIO_HAS_PORT_IMPEDANCE
302 /** @brief Port impedance enable mask. */
303 typedef enum
304 {
305 NRF_GPIO_PORT_IMPEDANCE_50_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk, ///< Enable 50 Ohm impedance.
306 NRF_GPIO_PORT_IMPEDANCE_100_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk, ///< Enable 100 Ohm impedance.
307 NRF_GPIO_PORT_IMPEDANCE_200_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk, ///< Enable 200 Ohm impedance.
308 NRF_GPIO_PORT_IMPEDANCE_400_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk, ///< Enable 400 Ohm impedance.
309 NRF_GPIO_PORT_IMPEDANCE_800_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk, ///< Enable 800 Ohm impedance.
310 NRF_GPIO_PORT_IMPEDANCE_1600_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk, ///< Enable 1600 Ohm impedance.
311 } nrf_gpio_port_impedance_mask_t;
312 #endif
313
314 #if NRF_GPIO_HAS_RETENTION
315 /** @brief Retention enable mask. */
316 typedef enum
317 {
318 #if defined(GPIO_RETAIN_APPLICAION_Msk) || defined(__NRFX_DOXYGEN__)
319 NRF_GPIO_RETAIN_APPLICATION_MASK = GPIO_RETAIN_APPLICAION_Msk, ///< Enable retention for GPIO registers for Application domain
320 #endif
321 #if defined(GPIO_RETAIN_RADIOCORE_Msk) || defined(__NRFX_DOXYGEN__)
322 NRF_GPIO_RETAIN_NETWORK_MASK = GPIO_RETAIN_RADIOCORE_Msk, ///< Enable retention for GPIO registers for Radio core
323 #endif
324 #if defined(NRF_GPIO_RETAIN_EXT)
325 NRF_GPIO_RETAIN_EXT
326 #endif
327 } nrf_gpio_retain_mask_t;
328 #endif
329
330 /**
331 * @brief Function for configuring the GPIO pin range as output pins with normal drive strength.
332 * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
333 *
334 * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output.
335 * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
336 *
337 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured.
338 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured.
339 */
340 NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
341
342 /**
343 * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details.
344 * This function can be used to configure pin range as simple input.
345 *
346 * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input.
347 * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
348 *
349 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured.
350 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured.
351 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
352 */
353 NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
354 uint32_t pin_range_end,
355 nrf_gpio_pin_pull_t pull_config);
356
357 /**
358 * @brief Pin configuration function.
359 *
360 * The main pin configuration function.
361 * This function allows to set any aspect in PIN_CNF register.
362 *
363 * @param pin_number Specifies the pin number.
364 * @param dir Pin direction.
365 * @param input Connect or disconnect the input buffer.
366 * @param pull Pull configuration.
367 * @param drive Drive configuration.
368 * @param sense Pin sensing mechanism.
369 */
370 NRF_STATIC_INLINE void nrf_gpio_cfg(
371 uint32_t pin_number,
372 nrf_gpio_pin_dir_t dir,
373 nrf_gpio_pin_input_t input,
374 nrf_gpio_pin_pull_t pull,
375 nrf_gpio_pin_drive_t drive,
376 nrf_gpio_pin_sense_t sense);
377
378 /**
379 * @brief Function for reconfiguring pin.
380 *
381 * @note This function selectively updates fields in PIN_CNF register. Reconfiguration
382 * is performed in single register write. Fields for which new configuration is
383 * not provided remain unchanged.
384 *
385 * @param pin_number Specifies the pin number.
386 * @param p_dir Pin direction. If NULL, previous setting remains.
387 * @param p_input Connect or disconnect the input buffer. If NULL, previous setting remains.
388 * @param p_pull Pull configuration. If NULL, previous setting remains.
389 * @param p_drive Drive configuration. If NULL, previous setting remains.
390 * @param p_sense Pin sensing mechanism. If NULL, previous setting remains.
391 */
392 NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number,
393 const nrf_gpio_pin_dir_t * p_dir,
394 const nrf_gpio_pin_input_t * p_input,
395 const nrf_gpio_pin_pull_t * p_pull,
396 const nrf_gpio_pin_drive_t * p_drive,
397 const nrf_gpio_pin_sense_t * p_sense);
398
399 /**
400 * @brief Function for configuring the given GPIO pin number as output, hiding inner details.
401 * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
402 *
403 * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
404 *
405 * @param pin_number Specifies the pin number.
406 */
407 NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
408
409 /**
410 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
411 * This function can be used to configure a pin as simple input.
412 *
413 * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
414 *
415 * @param pin_number Specifies the pin number.
416 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
417 */
418 NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
419
420 /**
421 * @brief Function for resetting pin configuration to its default state.
422 *
423 * @param pin_number Specifies the pin number.
424 */
425 NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number);
426
427 /**
428 * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected.
429 *
430 * @param pin_number Specifies the pin number.
431 *
432 */
433 NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
434
435 /**
436 * @brief Function for disconnecting input for the given GPIO.
437 *
438 * @param pin_number Specifies the pin number.
439 */
440 NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
441
442 /**
443 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
444 * This function can be used to configure pin range as simple input.
445 * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable.
446 *
447 * @param pin_number Specifies the pin number.
448 * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high).
449 * @param sense_config Sense level of the pin (no sense, sense low, or sense high).
450 */
451 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
452 nrf_gpio_pin_pull_t pull_config,
453 nrf_gpio_pin_sense_t sense_config);
454
455 /**
456 * @brief Function for configuring sense level for the given GPIO.
457 *
458 * @param pin_number Specifies the pin number.
459 * @param sense_config Sense configuration.
460 */
461 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
462 nrf_gpio_pin_sense_t sense_config);
463
464 /**
465 * @brief Function for setting the direction for a GPIO pin.
466 *
467 * @param pin_number Specifies the pin number for which to set the direction.
468 * @param direction Specifies the direction.
469 */
470 NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
471
472 /**
473 * @brief Function for setting a GPIO pin.
474 *
475 * @param pin_number Specifies the pin number to be set.
476 */
477 NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
478
479 /**
480 * @brief Function for clearing a GPIO pin.
481 *
482 * @param pin_number Specifies the pin number to clear.
483 */
484 NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
485
486 /**
487 * @brief Function for toggling a GPIO pin.
488 *
489 * @param pin_number Specifies the pin number to toggle.
490 */
491 NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
492
493 /**
494 * @brief Function for writing a value to a GPIO pin.
495 *
496 * @param pin_number Specifies the pin number to write.
497 * @param value Specifies the value to be written to the pin.
498 * @arg 0 Clears the pin.
499 * @arg >=1 Sets the pin.
500 */
501 NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
502
503 /**
504 * @brief Function for reading the input level of a GPIO pin.
505 *
506 * If the value returned by this function is to be valid, the pin's input buffer must be connected.
507 *
508 * @param pin_number Specifies the pin number to read.
509 *
510 * @return 0 if the pin input level is low. Positive value if the pin is high.
511 */
512 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number);
513
514 /**
515 * @brief Function for reading the output level of a GPIO pin.
516 *
517 * @param pin_number Specifies the pin number to read.
518 *
519 * @return 0 if the pin output level is low. Positive value if pin output is high.
520 */
521 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number);
522
523 /**
524 * @brief Function for reading the sense configuration of a GPIO pin.
525 *
526 * @param pin_number Specifies the pin number to read.
527 *
528 * @return Sense configuration.
529 */
530 NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
531
532 /**
533 * @brief Function for reading the direction configuration of a GPIO pin.
534 *
535 * @param pin_number Specifies the pin number to read.
536 *
537 * @return Direction configuration.
538 */
539 NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number);
540
541 /**
542 * @brief Function for reading the status of GPIO pin input buffer.
543 *
544 * @param pin_number Pin number to be read.
545 *
546 * @retval Input buffer configuration.
547 */
548 NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number);
549
550 /**
551 * @brief Function for reading the pull configuration of a GPIO pin.
552 *
553 * @param pin_number Specifies the pin number to read.
554 *
555 * @retval Pull configuration.
556 */
557 NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number);
558
559 /**
560 * @brief Function for setting output direction on the selected pins on the given port.
561 *
562 * @param p_reg Pointer to the structure of registers of the peripheral.
563 * @param out_mask Mask specifying the pins to set as output.
564 */
565 NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask);
566
567 /**
568 * @brief Function for setting input direction on selected pins on a given port.
569 *
570 * @param p_reg Pointer to the structure of registers of the peripheral.
571 * @param in_mask Mask that specifies the pins to be set as input.
572 */
573 NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask);
574
575 /**
576 * @brief Function for writing the direction configuration of the GPIO pins in the given port.
577 *
578 * @warning This register is retained when retention is enabled.
579 *
580 * @param p_reg Pointer to the structure of registers of the peripheral.
581 * @param dir_mask Mask that specifies the direction of pins. Bit set means that the given pin is configured as output.
582 */
583 NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask);
584
585 /**
586 * @brief Function for reading the direction configuration of a GPIO port.
587 *
588 * @warning This register is retained when retention is enabled.
589 *
590 * @param p_reg Pointer to the structure of registers of the peripheral.
591 *
592 * @return Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
593 */
594 NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg);
595
596 /**
597 * @brief Function for reading the input signals of the GPIO pins on the given port.
598 *
599 * @param p_reg Pointer to the peripheral registers structure.
600 *
601 * @return Port input values.
602 */
603 NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg);
604
605 /**
606 * @brief Function for reading the output signals of the GPIO pins on the given port.
607 *
608 * @warning This register is retained when retention is enabled.
609 *
610 * @param p_reg Pointer to the peripheral registers structure.
611 *
612 * @return Port output values.
613 */
614 NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg);
615
616 /**
617 * @brief Function for writing the GPIO pins output on a given port.
618 *
619 * @warning This register is retained when retention is enabled.
620 *
621 * @param p_reg Pointer to the structure of registers of the peripheral.
622 * @param value Output port mask.
623 */
624 NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value);
625
626 /**
627 * @brief Function for setting high level on selected the GPIO pins on the given port.
628 *
629 * @param p_reg Pointer to the structure of registers of the peripheral.
630 * @param set_mask Mask with pins to be set as logical high level.
631 */
632 NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask);
633
634 /**
635 * @brief Function for setting low level on selected the GPIO pins on the given port.
636 *
637 * @param p_reg Pointer to the structure of registers of the peripheral.
638 * @param clr_mask Mask with pins to be set as logical low level.
639 */
640 NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask);
641
642 /**
643 * @brief Function for reading pin state of multiple consecutive ports.
644 *
645 * @param start_port Index of the first port to read.
646 * @param length Number of ports to read.
647 * @param p_masks Pointer to output array where port states will be stored.
648 */
649 NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
650 uint32_t length,
651 uint32_t * p_masks);
652
653 #if NRF_GPIO_HAS_PORT_IMPEDANCE
654 /**
655 * @brief Function for setting the impedance matching of the pins on the given port.
656 *
657 * @note Each bit sets certain impedance and have them in parallel when more than one bit is set.
658 * High impedance is set for the pin when all bits are disabled.
659 * When all bits are enabled, the resulting impedance is about 25 Ohm.
660 *
661 * @warning This register is retained when retention is enabled.
662 *
663 * @param p_reg Pointer to the structure of registers of the peripheral.
664 * @param mask Mask of impedances to be set, created using @ref nrf_gpio_port_impedance_mask_t.
665 */
666 NRF_STATIC_INLINE void nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg, uint32_t mask);
667
668 /**
669 * @brief Function for geting the impedance matching of the pins on the given port.
670 *
671 * @warning This register is retained when retention is enabled.
672 *
673 * @param p_reg Pointer to the structure of registers of the peripheral.
674 *
675 * @return Mask of impedances set, created using @ref nrf_gpio_port_impedance_mask_t.
676 */
677 NRF_STATIC_INLINE uint32_t nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg);
678 #endif
679
680 #if NRF_GPIO_HAS_RETENTION
681 /**
682 * @brief Function for setting the retention of the registers.
683 *
684 * @param p_reg Pointer to the structure of registers of the peripheral.
685 * @param mask Mask of retention domains to be enabled, created using @ref nrf_gpio_retain_mask_t.
686 */
687 NRF_STATIC_INLINE void nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg, uint32_t mask);
688
689 /**
690 * @brief Function for geting the retention setting of the registers.
691 *
692 * @param p_reg Pointer to the structure of registers of the peripheral.
693 *
694 * @return Mask of retention domains set, created using @ref nrf_gpio_retain_mask_t.
695 */
696 NRF_STATIC_INLINE uint32_t nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg);
697 #endif
698
699 #if NRF_GPIO_HAS_DETECT_MODE
700 /**
701 * @brief Function for setting the latched detect behaviour.
702 *
703 * @param p_reg Pointer to the structure of registers of the peripheral.
704 * @param enable True if the latched LDETECT behaviour is to be used, false if DETECT is to be
705 * directly connected to PIN DETECT signals.
706 */
707 NRF_STATIC_INLINE void nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg, bool enable);
708
709 /**
710 * @brief Function for checking the latched detect behaviour.
711 *
712 * @param p_reg Pointer to the structure of registers of the peripheral.
713 *
714 * @retval true Latched LDETECT behaviour is used.
715 * @retval false DETECT is directly connected to PIN DETECT signals.
716 */
717 NRF_STATIC_INLINE bool nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg);
718 #endif
719
720 #if defined(NRF_GPIO_LATCH_PRESENT)
721 /**
722 * @brief Function for reading latch state of multiple consecutive ports.
723 *
724 * @warning This register is retained when retention is enabled.
725 *
726 * @param start_port Index of the first port to read.
727 * @param length Number of ports to read.
728 * @param p_masks Pointer to output array where latch states will be stored.
729 */
730 NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
731 uint32_t length,
732 uint32_t * p_masks);
733
734 /**
735 * @brief Function for reading and immediate clearing latch state of multiple consecutive ports.
736 *
737 * @warning This register is retained when retention is enabled.
738 *
739 * @param start_port Index of the first port to read and clear.
740 * @param length Number of ports to read and clear.
741 * @param p_masks Pointer to output array where latch states will be stored.
742 */
743 NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
744 uint32_t length,
745 uint32_t * p_masks);
746
747 /**
748 * @brief Function for reading latch state of single pin.
749 *
750 * @warning This register is retained when retention is enabled.
751 *
752 * @param pin_number Pin number.
753 *
754 * @return 0 if latch is not set. Positive value otherwise.
755 */
756 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
757
758 /**
759 * @brief Function for clearing latch state of a single pin.
760 *
761 * @warning This register is retained when retention is enabled.
762 *
763 * @param pin_number Pin number.
764 */
765 NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
766 #endif // defined(NRF_GPIO_LATCH_PRESENT)
767
768 #if NRF_GPIO_HAS_SEL
769 /**
770 * @brief Function for selecting the MCU or Subsystem to control a GPIO pin.
771 *
772 * @warning This register is retained when retention is enabled.
773 *
774 * @param pin_number Pin_number.
775 * @param ctrl MCU/Subsystem to control the pin.
776 */
777 NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl);
778 #endif
779
780 #if NRF_GPIO_HAS_CLOCKPIN
781 /**
782 * @brief Function for setting whether the clock should be enabled for the specified GPIO pin.
783 *
784 * @warning This register is retained when retention is enabled.
785 *
786 * @param[in] pin_number Pin number.
787 * @param[in] enable True if clock is to be enabled, false otherwise.
788 */
789 NRF_STATIC_INLINE void nrf_gpio_pin_clock_set(uint32_t pin_number, bool enable);
790
791 /**
792 * @brief Function for getting the clock enable setting for the specified GPIO pin.
793 *
794 * @warning This register is retained when retention is enabled.
795 *
796 * @param[in] pin_number Pin number.
797 *
798 * @retval true Clock is enabled.
799 * @retval false Clock is disabled.
800 */
801 NRF_STATIC_INLINE bool nrf_gpio_pin_clock_check(uint32_t pin_number);
802 #endif
803
804 /**
805 * @brief Function for checking if provided pin is present on the MCU.
806 *
807 * @param[in] pin_number Number of the pin to be checked.
808 *
809 * @retval true Pin is present.
810 * @retval false Pin is not present.
811 */
812 NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number);
813
814 /**
815 * @brief Function for extracting port number and the relative pin number
816 * from the absolute pin number.
817 *
818 * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
819 * that is relative to the port.
820 *
821 * @return Port number.
822 */
823 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin);
824
825 #ifndef NRF_DECLARE_ONLY
826
827 /**
828 * @brief Function for extracting port and the relative pin number from the absolute pin number.
829 *
830 * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
831 * that is relative to the port.
832 *
833 * @return Pointer to port register set.
834 */
nrf_gpio_pin_port_decode(uint32_t * p_pin)835 NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
836 {
837 NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
838
839 NRF_GPIO_Type * p_port = NULL;
840
841 switch (nrf_gpio_pin_port_number_extract(p_pin))
842 {
843 NRF_INTERNAL_GPIO_PORT_EXTRACT(p_port);
844
845 default:
846 NRFX_ASSERT(0);
847 }
848 return p_port;
849 }
850
851
nrf_gpio_range_cfg_output(uint32_t pin_range_start,uint32_t pin_range_end)852 NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
853 {
854 for (; pin_range_start <= pin_range_end; pin_range_start++)
855 {
856 nrf_gpio_cfg_output(pin_range_start);
857 }
858 }
859
860
nrf_gpio_range_cfg_input(uint32_t pin_range_start,uint32_t pin_range_end,nrf_gpio_pin_pull_t pull_config)861 NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
862 uint32_t pin_range_end,
863 nrf_gpio_pin_pull_t pull_config)
864 {
865 for (; pin_range_start <= pin_range_end; pin_range_start++)
866 {
867 nrf_gpio_cfg_input(pin_range_start, pull_config);
868 }
869 }
870
871
nrf_gpio_cfg(uint32_t pin_number,nrf_gpio_pin_dir_t dir,nrf_gpio_pin_input_t input,nrf_gpio_pin_pull_t pull,nrf_gpio_pin_drive_t drive,nrf_gpio_pin_sense_t sense)872 NRF_STATIC_INLINE void nrf_gpio_cfg(
873 uint32_t pin_number,
874 nrf_gpio_pin_dir_t dir,
875 nrf_gpio_pin_input_t input,
876 nrf_gpio_pin_pull_t pull,
877 nrf_gpio_pin_drive_t drive,
878 nrf_gpio_pin_sense_t sense)
879 {
880 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
881 uint32_t cnf = reg->PIN_CNF[pin_number];
882
883 uint32_t to_update = GPIO_PIN_CNF_DIR_Msk |
884 GPIO_PIN_CNF_INPUT_Msk |
885 GPIO_PIN_CNF_PULL_Msk |
886 #if defined(GPIO_PIN_CNF_DRIVE_Msk)
887 GPIO_PIN_CNF_DRIVE_Msk |
888 #else
889 GPIO_PIN_CNF_DRIVE0_Msk |
890 GPIO_PIN_CNF_DRIVE1_Msk |
891 #endif
892 GPIO_PIN_CNF_SENSE_Msk;
893
894 /* Clear fields that will be updated. */
895 cnf &= ~to_update;
896 cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) |
897 ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) |
898 ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) |
899 #if defined(GPIO_PIN_CNF_DRIVE_Pos)
900 ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
901 #else
902 ((uint32_t)drive << GPIO_PIN_CNF_DRIVE0_Pos) |
903 #endif
904 ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
905
906 reg->PIN_CNF[pin_number] = cnf;
907 }
908
nrf_gpio_reconfigure(uint32_t pin_number,const nrf_gpio_pin_dir_t * p_dir,const nrf_gpio_pin_input_t * p_input,const nrf_gpio_pin_pull_t * p_pull,const nrf_gpio_pin_drive_t * p_drive,const nrf_gpio_pin_sense_t * p_sense)909 NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number,
910 const nrf_gpio_pin_dir_t * p_dir,
911 const nrf_gpio_pin_input_t * p_input,
912 const nrf_gpio_pin_pull_t * p_pull,
913 const nrf_gpio_pin_drive_t * p_drive,
914 const nrf_gpio_pin_sense_t * p_sense)
915 {
916 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
917 uint32_t cnf = reg->PIN_CNF[pin_number];
918 uint32_t to_update = (p_dir ? GPIO_PIN_CNF_DIR_Msk : 0) |
919 (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
920 (p_pull ? GPIO_PIN_CNF_PULL_Msk : 0) |
921 #if defined(GPIO_PIN_CNF_DRIVE_Msk)
922 (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
923 #else
924 (p_drive ? (GPIO_PIN_CNF_DRIVE0_Msk | GPIO_PIN_CNF_DRIVE1_Msk) : 0) |
925 #endif
926 (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
927
928 /* Clear fields that will be updated. */
929 cnf &= ~to_update;
930 cnf |= ((uint32_t)(p_dir ? *p_dir : 0) << GPIO_PIN_CNF_DIR_Pos) |
931 ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
932 ((uint32_t)(p_pull ? *p_pull : 0) << GPIO_PIN_CNF_PULL_Pos) |
933 #if defined(GPIO_PIN_CNF_DRIVE_Pos)
934 ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
935 #else
936 ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE0_Pos) |
937 #endif
938 ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos);
939
940 reg->PIN_CNF[pin_number] = cnf;
941 }
942
nrf_gpio_cfg_output(uint32_t pin_number)943 NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
944 {
945 nrf_gpio_cfg(
946 pin_number,
947 NRF_GPIO_PIN_DIR_OUTPUT,
948 NRF_GPIO_PIN_INPUT_DISCONNECT,
949 NRF_GPIO_PIN_NOPULL,
950 NRF_GPIO_PIN_S0S1,
951 NRF_GPIO_PIN_NOSENSE);
952 }
953
954
nrf_gpio_cfg_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config)955 NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
956 {
957 nrf_gpio_cfg(
958 pin_number,
959 NRF_GPIO_PIN_DIR_INPUT,
960 NRF_GPIO_PIN_INPUT_CONNECT,
961 pull_config,
962 NRF_GPIO_PIN_S0S1,
963 NRF_GPIO_PIN_NOSENSE);
964 }
965
966
nrf_gpio_cfg_default(uint32_t pin_number)967 NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
968 {
969 nrf_gpio_cfg(
970 pin_number,
971 NRF_GPIO_PIN_DIR_INPUT,
972 NRF_GPIO_PIN_INPUT_DISCONNECT,
973 NRF_GPIO_PIN_NOPULL,
974 NRF_GPIO_PIN_S0S1,
975 NRF_GPIO_PIN_NOSENSE);
976 }
977
978
nrf_gpio_cfg_watcher(uint32_t pin_number)979 NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
980 {
981 nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_CONNECT;
982
983 nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL);
984 }
985
986
nrf_gpio_input_disconnect(uint32_t pin_number)987 NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
988 {
989 nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_DISCONNECT;
990
991 nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL);
992 }
993
994
nrf_gpio_cfg_sense_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config,nrf_gpio_pin_sense_t sense_config)995 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
996 nrf_gpio_pin_pull_t pull_config,
997 nrf_gpio_pin_sense_t sense_config)
998 {
999 nrf_gpio_cfg(
1000 pin_number,
1001 NRF_GPIO_PIN_DIR_INPUT,
1002 NRF_GPIO_PIN_INPUT_CONNECT,
1003 pull_config,
1004 NRF_GPIO_PIN_S0S1,
1005 sense_config);
1006 }
1007
1008
nrf_gpio_cfg_sense_set(uint32_t pin_number,nrf_gpio_pin_sense_t sense_config)1009 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
1010 nrf_gpio_pin_sense_t sense_config)
1011 {
1012 nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
1013 }
1014
nrf_gpio_pin_dir_set(uint32_t pin_number,nrf_gpio_pin_dir_t direction)1015 NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
1016 {
1017 if (direction == NRF_GPIO_PIN_DIR_INPUT)
1018 {
1019 nrf_gpio_cfg(
1020 pin_number,
1021 NRF_GPIO_PIN_DIR_INPUT,
1022 NRF_GPIO_PIN_INPUT_CONNECT,
1023 NRF_GPIO_PIN_NOPULL,
1024 NRF_GPIO_PIN_S0S1,
1025 NRF_GPIO_PIN_NOSENSE);
1026 }
1027 else
1028 {
1029 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1030 reg->DIRSET = (1UL << pin_number);
1031 }
1032 }
1033
1034
nrf_gpio_pin_set(uint32_t pin_number)1035 NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
1036 {
1037 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1038
1039 nrf_gpio_port_out_set(reg, 1UL << pin_number);
1040 }
1041
1042
nrf_gpio_pin_clear(uint32_t pin_number)1043 NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
1044 {
1045 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1046
1047 nrf_gpio_port_out_clear(reg, 1UL << pin_number);
1048 }
1049
1050
nrf_gpio_pin_toggle(uint32_t pin_number)1051 NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
1052 {
1053 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1054 uint32_t pins_state = reg->OUT;
1055
1056 reg->OUTSET = (~pins_state & (1UL << pin_number));
1057 reg->OUTCLR = (pins_state & (1UL << pin_number));
1058 }
1059
1060
nrf_gpio_pin_write(uint32_t pin_number,uint32_t value)1061 NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
1062 {
1063 if (value == 0)
1064 {
1065 nrf_gpio_pin_clear(pin_number);
1066 }
1067 else
1068 {
1069 nrf_gpio_pin_set(pin_number);
1070 }
1071 }
1072
1073
nrf_gpio_pin_read(uint32_t pin_number)1074 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
1075 {
1076 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1077
1078 return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
1079 }
1080
1081
nrf_gpio_pin_out_read(uint32_t pin_number)1082 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number)
1083 {
1084 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1085
1086 return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL);
1087 }
1088
1089
nrf_gpio_pin_sense_get(uint32_t pin_number)1090 NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
1091 {
1092 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1093
1094 return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
1095 GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
1096 }
1097
1098
nrf_gpio_pin_dir_get(uint32_t pin_number)1099 NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number)
1100 {
1101 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1102
1103 return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
1104 GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos);
1105 }
1106
nrf_gpio_pin_input_get(uint32_t pin_number)1107 NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number)
1108 {
1109 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1110
1111 return (nrf_gpio_pin_input_t)((reg->PIN_CNF[pin_number] &
1112 GPIO_PIN_CNF_INPUT_Msk) >> GPIO_PIN_CNF_INPUT_Pos);
1113 }
1114
nrf_gpio_pin_pull_get(uint32_t pin_number)1115 NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number)
1116 {
1117 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1118
1119 return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] &
1120 GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos);
1121 }
1122
1123
nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg,uint32_t out_mask)1124 NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask)
1125 {
1126 p_reg->DIRSET = out_mask;
1127 }
1128
1129
nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg,uint32_t in_mask)1130 NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask)
1131 {
1132 p_reg->DIRCLR = in_mask;
1133 }
1134
1135
nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg,uint32_t value)1136 NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value)
1137 {
1138 p_reg->DIR = value;
1139 }
1140
1141
nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)1142 NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)
1143 {
1144 return p_reg->DIR;
1145 }
1146
1147
nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)1148 NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)
1149 {
1150 return p_reg->IN;
1151 }
1152
1153
nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)1154 NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)
1155 {
1156 return p_reg->OUT;
1157 }
1158
1159
nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg,uint32_t value)1160 NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value)
1161 {
1162 p_reg->OUT = value;
1163 }
1164
1165
nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg,uint32_t set_mask)1166 NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
1167 {
1168 p_reg->OUTSET = set_mask;
1169 }
1170
1171
nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg,uint32_t clr_mask)1172 NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask)
1173 {
1174 p_reg->OUTCLR = clr_mask;
1175 }
1176
1177
nrf_gpio_ports_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)1178 NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
1179 uint32_t length,
1180 uint32_t * p_masks)
1181 {
1182 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1183
1184 NRFX_ASSERT(start_port + length <= GPIO_COUNT);
1185 uint32_t i;
1186
1187 for (i = start_port; i < (start_port + length); i++)
1188 {
1189 *p_masks = nrf_gpio_port_in_read(gpio_regs[i]);
1190 p_masks++;
1191 }
1192 }
1193
1194 #if NRF_GPIO_HAS_PORT_IMPEDANCE
nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg,uint32_t mask)1195 NRF_STATIC_INLINE void nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg, uint32_t mask)
1196 {
1197 p_reg->PORTCNF.DRIVECTRL = ((p_reg->PORTCNF.DRIVECTRL & ~NRF_GPIO_PORT_IMPEDANCE_ALL_MASK) |
1198 (mask & NRF_GPIO_PORT_IMPEDANCE_ALL_MASK));
1199 }
1200
nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg)1201 NRF_STATIC_INLINE uint32_t nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg)
1202 {
1203 return p_reg->PORTCNF.DRIVECTRL & NRF_GPIO_PORT_IMPEDANCE_ALL_MASK;
1204 }
1205 #endif
1206
1207 #if NRF_GPIO_HAS_RETENTION
nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg,uint32_t mask)1208 NRF_STATIC_INLINE void nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg, uint32_t mask)
1209 {
1210 p_reg->RETAIN = mask;
1211 }
1212
nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg)1213 NRF_STATIC_INLINE uint32_t nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg)
1214 {
1215 return p_reg->RETAIN;
1216 }
1217 #endif
1218
1219 #if NRF_GPIO_HAS_DETECT_MODE
nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg,bool enable)1220 NRF_STATIC_INLINE void nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg, bool enable)
1221 {
1222 p_reg->DETECTMODE = (enable ? GPIO_DETECTMODE_DETECTMODE_LDETECT :
1223 GPIO_DETECTMODE_DETECTMODE_Default);
1224 }
1225
nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg)1226 NRF_STATIC_INLINE bool nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg)
1227 {
1228 return (p_reg->DETECTMODE == GPIO_DETECTMODE_DETECTMODE_LDETECT);
1229 }
1230 #endif
1231
1232 #if defined(NRF_GPIO_LATCH_PRESENT)
nrf_gpio_latches_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)1233 NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
1234 uint32_t length,
1235 uint32_t * p_masks)
1236 {
1237 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1238 uint32_t i;
1239
1240 for (i = start_port; i < (start_port + length); i++)
1241 {
1242 *p_masks = gpio_regs[i]->LATCH;
1243 p_masks++;
1244 }
1245 }
1246
nrf_gpio_latches_read_and_clear(uint32_t start_port,uint32_t length,uint32_t * p_masks)1247 NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
1248 uint32_t length,
1249 uint32_t * p_masks)
1250 {
1251 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1252 uint32_t i;
1253
1254 for (i = start_port; i < (start_port + length); i++)
1255 {
1256 *p_masks = gpio_regs[i]->LATCH;
1257
1258 // The LATCH register is cleared by writing a '1' to the bit that shall be cleared.
1259 gpio_regs[i]->LATCH = *p_masks;
1260
1261 p_masks++;
1262 }
1263 }
1264
nrf_gpio_pin_latch_get(uint32_t pin_number)1265 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number)
1266 {
1267 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1268
1269 return (reg->LATCH & (1 << pin_number)) ? 1 : 0;
1270 }
1271
1272
nrf_gpio_pin_latch_clear(uint32_t pin_number)1273 NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number)
1274 {
1275 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1276
1277 reg->LATCH = (1 << pin_number);
1278 }
1279 #endif // defined(NRF_GPIO_LATCH_PRESENT)
1280
1281 #if NRF_GPIO_HAS_SEL
nrf_gpio_pin_control_select(uint32_t pin_number,nrf_gpio_pin_sel_t ctrl)1282 NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl)
1283 {
1284 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1285 #if defined(GPIO_PIN_CNF_MCUSEL_Msk)
1286 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_MCUSEL_Msk;
1287 reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_MCUSEL_Pos);
1288 #else
1289 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_CTRLSEL_Msk;
1290 reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_CTRLSEL_Pos);
1291 #endif
1292 }
1293 #endif // NRF_GPIO_HAS_SEL
1294
1295 #if NRF_GPIO_HAS_CLOCKPIN
nrf_gpio_pin_clock_set(uint32_t pin_number,bool enable)1296 NRF_STATIC_INLINE void nrf_gpio_pin_clock_set(uint32_t pin_number, bool enable)
1297 {
1298 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1299
1300 reg->PIN_CNF[pin_number] = ((reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_CLOCKPIN_Msk) |
1301 ((enable ? GPIO_PIN_CNF_CLOCKPIN_Enabled :
1302 GPIO_PIN_CNF_CLOCKPIN_Disabled) << GPIO_PIN_CNF_CLOCKPIN_Pos));
1303 }
1304
nrf_gpio_pin_clock_check(uint32_t pin_number)1305 NRF_STATIC_INLINE bool nrf_gpio_pin_clock_check(uint32_t pin_number)
1306 {
1307 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1308
1309 return (((reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_CLOCKPIN_Msk) >> GPIO_PIN_CNF_CLOCKPIN_Pos)
1310 == GPIO_PIN_CNF_CLOCKPIN_Enabled);
1311 }
1312 #endif
1313
nrf_gpio_pin_present_check(uint32_t pin_number)1314 NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number)
1315 {
1316 uint32_t port = pin_number >> 5;
1317 uint32_t mask = 0;
1318
1319 switch (port)
1320 {
1321 NRF_INTERNAL_GPIO_PORT_MASK_SET(mask);
1322
1323 default:
1324 return false;
1325 }
1326
1327 #ifdef P0_FEATURE_PINS_PRESENT
1328 #if defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
1329 /* Allow use of the following additional GPIOs that are connected to LEDs and buttons
1330 * on the nRF52833 DK:
1331 * - P0.11 - Button 1
1332 * - P0.12 - Button 2
1333 * - P0.13 - LED 1
1334 * - P0.24 - Button 3
1335 * - P0.25 - Button 4
1336 */
1337 mask |= 0x03003800;
1338 #endif // defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
1339 #endif
1340
1341 pin_number &= 0x1F;
1342
1343 return (mask & (1UL << pin_number)) ? true : false;
1344 }
1345
nrf_gpio_pin_port_number_extract(uint32_t * p_pin)1346 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
1347 {
1348 uint32_t pin_number = *p_pin;
1349 *p_pin = NRF_PIN_NUMBER_TO_PIN(pin_number);
1350
1351 return NRF_PIN_NUMBER_TO_PORT(pin_number);
1352 }
1353
1354 #endif // NRF_DECLARE_ONLY
1355
1356 /** @} */
1357
1358 #ifdef __cplusplus
1359 }
1360 #endif
1361
1362 #endif // NRF_GPIO_H__
1363
