1 /*
2  * Copyright 2024 Microchip Technology Inc. and its subsidiaries.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _MEC_KBC_API_H
7 #define _MEC_KBC_API_H
8 
9 #include <stdbool.h>
10 #include <stddef.h>
11 #include <stdint.h>
12 
13 #include "mec_defs.h"
14 #include "mec_retval.h"
15 
16 /* Interfaces to any C modules */
17 #ifdef __cplusplus
18 extern "C"
19 {
20 #endif
21 
22 /* EM8042 Keyboard Controller with GATEA20 support and Port92h fast reset.
23  * NOTE: Port92h is a separate hardware block including its own I/O BAR.
24  */
25 
26 #define MEC_KBC_NUM_INSTANCES 1
27 #define MEC_KBC_NUM_IRQS 2 /* number of IRQ sources per instance */
28 
29 struct mec_kbc_regs;
30 
31 enum mec_kbc_flags {
32     MEC_KBC_IBF_IRQ        = MEC_BIT(0),
33     MEC_KBC_OBE_IRQ        = MEC_BIT(1),
34     MEC_KBC_PCOBF_EN       = MEC_BIT(2),
35     MEC_KBC_AUXOBF_EN      = MEC_BIT(3),
36     MEC_KBC_PORT92_EN      = MEC_BIT(4),
37     MEC_KBC_GATEA20_FWC_EN = MEC_BIT(5),
38     MEC_KBC_RESET          = MEC_BIT(7),
39     MEC_KBC_UD0_SET        = MEC_BIT(8),
40     MEC_KBC_UD1_SET        = MEC_BIT(9),
41     MEC_KBC_UD2_SET        = MEC_BIT(10),
42     MEC_KBC_UD3_SET        = MEC_BIT(11),
43     MEC_KBC_UD4_SET        = MEC_BIT(12),
44     MEC_KBC_UD5_SET        = MEC_BIT(13),
45     MEC_KBC_UD0_ONE        = MEC_BIT(16),
46     MEC_KBC_UD1_ONE        = MEC_BIT(17),
47     MEC_KBC_UD2_0_ONE      = MEC_BIT(18),
48     MEC_KBC_UD2_1_ONE      = MEC_BIT(19),
49     MEC_KBC_UD3_ONE        = MEC_BIT(20),
50     MEC_KBC_UD4_0_ONE      = MEC_BIT(21),
51     MEC_KBC_UD4_1_ONE      = MEC_BIT(22),
52     MEC_KBC_UD5_ONE        = MEC_BIT(23),
53 };
54 
55 enum mec_kbc_status_pos {
56     MEC_KBC_STS_OBF_POS = 0,
57     MEC_KBC_STS_IBF_POS,
58     MEC_KBC_STS_UD0_POS,
59     MEC_KBC_STS_CMD_POS,
60     MEC_KBC_STS_UD1_POS,
61     MEC_KBC_STS_AUXOBF_POS,
62     MEC_KBC_STS_UD2_B0_POS,
63     MEC_KBC_STS_UD2_B1_POS,
64 };
65 
66 enum mec_kbc_status {
67     MEC_KBC_STS_OBF    = MEC_BIT(0),
68     MEC_KBC_STS_IBF    = MEC_BIT(1),
69     MEC_KBC_STS_UD0    = MEC_BIT(2),
70     MEC_KBC_STS_CMD    = MEC_BIT(3),
71     MEC_KBC_STS_UD1    = MEC_BIT(4),
72     MEC_KBC_STS_AUXOBF = MEC_BIT(5),
73     MEC_KBC_STS_UD2_B0 = MEC_BIT(6),
74     MEC_KBC_STS_UD2_B1 = MEC_BIT(7),
75 };
76 
77 int mec_hal_kbc_init(struct mec_kbc_regs *base, uint32_t flags);
78 
79 #define MEC_KBC_ACTV_KBC 0x1u
80 #define MEC_KBC_ACTV_P92 0x2u
81 #define MEC_KBC_ACT_ALL (MEC_KBC_ACTV_KBC | MEC_KBC_ACTV_P92)
82 int mec_hal_kbc_activate(struct mec_kbc_regs *base, uint8_t enable, uint8_t flags);
83 
84 int mec_hal_kbc_girq_en(struct mec_kbc_regs *base, uint32_t flags);
85 int mec_hal_kbc_girq_dis(struct mec_kbc_regs *base, uint32_t flags);
86 int mec_hal_kbc_girq_clr(struct mec_kbc_regs *base, uint32_t flags);
87 uint32_t mec_hal_kbc_girq_result(struct mec_kbc_regs *base);
88 int mec_hal_kbc_is_enabled(struct mec_kbc_regs *base);
89 int mec_hal_kbc_is_irq_gen_enabled(struct mec_kbc_regs *base);
90 uint8_t mec_hal_kbc_status(struct mec_kbc_regs *base);
91 
92 #define MEC_KBC_DATA_KB 0
93 #define MEC_KBC_DATA_AUX 1
94 #define MEC_KBC_DATA_HOST 2
95 
96 void mec_hal_kbc_wr_data(struct mec_kbc_regs *base, uint8_t data, uint8_t data_is_aux);
97 void mec_hal_kbc_status_wr(struct mec_kbc_regs *base, uint8_t val, uint8_t msk);
98 
99 /* Set bits in msk to 1 preserving other bits */
100 void mec_hal_kbc_status_set(struct mec_kbc_regs *base, uint8_t msk);
101 
102 /* Clear bits in msk to 0 preserving other bits */
103 void mec_hal_kbc_status_clear(struct mec_kbc_regs *base, uint8_t msk);
104 
105 uint8_t mec_hal_kbc_rd_host_data(struct mec_kbc_regs *base, uint8_t is_host_data_reg);
106 
107 #ifdef __cplusplus
108 }
109 #endif
110 
111 #endif /* #ifndef _MEC_KBC_API_H */
112