1 /*
2  * Copyright 2024 Microchip Technology Inc. and its subsidiaries.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _MEC_I3C_PVT_H_
7 #define _MEC_I3C_PVT_H_
8 
9 #include <stdint.h>
10 #include <stdbool.h>
11 #include "mec_defs.h"
12 
13 struct mec_i3c_DCT_info {
14 
15     /* 64 bit provisional id */
16     uint64_t pid;
17 
18     /* Bus Characteristics Register */
19     uint8_t bcr;
20 
21     /* Device Characteristics Register */
22     uint8_t dcr;
23 
24     /* 7-bit dynamic address */
25     uint8_t dynamic_addr;
26 };
27 
28 struct mec_i3c_SDCT_info {
29 
30     /* 7-bit dynamic address */
31     uint8_t dynamic_addr;
32 
33     /* Device Characteristics Register Value */
34     uint8_t dcr;
35 
36     /* Bus Characteristics Register Value */
37     uint8_t bcr;
38 
39     /* 7-bit static address */
40     uint8_t static_addr;
41 
42 };
43 
44 /* Enter Dynamic Address Assignment (Broadcast) */
45 #define MEC_I3C_CCC_ENTDAA                      0x07U
46 
47 #define DO_CCC_SHORT_CMD_DATA_SIZE_MAX          3U
48 
49 #define I3C_PUSH_PULL_SCL_MIN_LOW_PERIOD_NS     33U
50 #define I3C_PUSH_PULL_SCL_MIN_HIGH_PERIOD_NS    41U
51 
52 #define I3C_OPEN_DRAIN_SCL_MIN_LOW_PERIOD_NS     200U
53 #define I3C_OPEN_DRAIN_SCL_MIN_HIGH_PERIOD_NS    41U
54 
55 #define I3C_BUS_SDR1_SCL_PERIOD_NS              2000U
56 #define I3C_BUS_SDR2_SCL_PERIOD_NS              2625U
57 #define I3C_BUS_SDR3_SCL_PERIOD_NS              4000U
58 #define I3C_BUS_SDR4_SCL_PERIOD_NS              8000U
59 
60 #define I3C_BUS_SDR1_SCL_PERIOD_BITPOS          0U
61 #define I3C_BUS_SDR2_SCL_PERIOD_BITPOS          8U
62 #define I3C_BUS_SDR3_SCL_PERIOD_BITPOS          16U
63 #define I3C_BUS_SDR4_SCL_PERIOD_BITPOS          24U
64 
65 #define I3C_BUS_MAX_SKEW_PERIOD_NS              12.8F
66 
67 #define I3C_BUS_READ_TERM_LCNT_BITPOS           0U
68 #define I3C_BUS_HDR_TS_SKEW_CNT_BITPOS          16U
69 #define I3C_BUS_STOP_HOLD_CNT                   28U
70 
71 #define I3C_SCL_TIMING_COUNT_MIN                7U
72 #define I3C_SCL_12_5MHZ_PERIOD_NS               80U
73 
74 /* Need to review and tweak */
75 #define I2C_FM_SCL_MIN_LOW_PERIOD_NS            1300U
76 #define I2C_FM_SCL_MIN_HIGH_PERIOD_NS           680U
77 
78 #define I2C_FMP_SCL_MIN_LOW_PERIOD_NS           500U
79 #define I2C_FMP_SCL_MIN_HIGH_PERIOD_NS          260U
80 
81 #define I3C_RESPONSE_BUFFER_DEPTH               32U
82 
83 
84 /*----------------------------------TIMING PARAMETERS------------------*/
85 #define TGT_MAX_RD_DATA_SPEED  MAX_DATA_SPEED_RD_12_5_MHZ
86 
87 #define TGT_MAX_WR_DATA_SPEED  MAX_DATA_SPEED_WR_12_5_MHZ
88 
89 #define TGT_CLK_TO_DATA_TURN  MAX_CLK_DATA_TURN_8_ns
90 
91 #define TGT_BUS_AVAIL_COND_ns  (13*1000)
92 #define TGT_BUS_IDLE_COND_ns   (13*1000)
93 #define TGT_BUS_FREE_DURATION_ns   (13*1000)
94 
95 
96 
97 /*----------------------------DEVICE CONTROL----------------------------------*/
98 
99 enum device_control_reg_bits
100 {
101     sbit_IBA_INCLUDE            = (1U << 0)  // BIT_0_MASK
102    ,sbit_I2C_TGT_PRESENT        = (1U << 7)  // BIT_7_MASK
103    ,sbit_HOT_JOIN_CTRL          = (1U << 8)  // BIT_8_MASK
104    ,sbit_IDLE_CNT_MULTIPLIER    = (1U << 24) // BIT_24_MASK
105    ,sbit_ADAPTIVE_I2C_I3C       = (1U << 27) // BIT_27_MASK
106    ,sbit_DMA_ENABLE             = (1U << 28) // BIT_28_MASK
107    ,sbit_ABORT                  = (1U << 29) // BIT_29_MASK
108    ,sbit_RESUME                 = (1U << 30) // BIT_30_MASK
109    ,sbit_ENABLE                 = (1U << 31) // BIT_31_MASK
110 };
111 
112 /*----------------------------Target Event Status----------------------------------*/
113 
114 enum tgt_evt_sts_reg_bits
115 {
116     sbit_SIR_ENABLE             = (1U << 0)
117    ,sbit_MR_ENABLE              = (1U << 1)
118    ,sbit_HJ_ENABLE              = (1U << 3)
119 };
120 
121 /*----------------------------FIFO LIMITS----------------------------------*/
122 #define Q_CAP_TX_FIFO_DEPTH_BITPOS      0U
123 #define Q_CAP_RX_FIFO_DEPTH_BITPOS      4U
124 #define Q_CAP_CMD_FIFO_DEPTH_BITPOS     8U
125 #define Q_CAP_RESP_FIFO_DEPTH_BITPOS    12U
126 #define Q_CAP_IBI_FIFO_DEPTH_BITPOS     16U
127 
128 #define FIFO_DEPTH_MIN_DWORD            2U // minimum 2 DWORDS for each FIFO
129 /*----------------------------DEVICE ADDRESS----------------------------------*/
130 
131 #define sbit_DEVICE_ADDR_STATIC_ADDR_VALID      (1U << 15) // BIT_15_MASK
132 #define sbit_DEVICE_ADDR_DYNAMIC_ADDR_VALID     (1U << 31) // BIT_31_MASK
133 #define DEVICE_ADDR_DYNAMIC_ADDR_BITPOS         16U
134 
135 /*--------------------------------COMMAND QUEUE--------------------------------*/
136 
137 #define COMMAND_TID_BITPOS                      3U
138 #define COMMAND_CMD_BITPOS                      7U
139 #define COMMAND_DEV_IDX_BITPOS                  16U
140 #define COMMAND_SPEED_BITPOS                    21U
141 
142 #define COMMAND_HDR_DDR_READ_BITPOS           (1U << 14)
143 #define COMMAND_HDR_DDR_WRITE_BITPOS          (1U << 13)
144 
145 #define COMMAND_CMD_PRESENT                    (1U << 15) // BIT_15_MASK
146 #define COMMAND_DEF_BYTE_PRESENT               (1U << 25) // BIT_25_MASK
147 #define COMMAND_RESPONSE_ON_COMPLETION         (1U << 26) // BIT_26_MASK
148 #define COMMAND_READ_XFER                      (1U << 28) // BIT_28_MASK
149 #define COMMAND_STOP_ON_COMPLETION             (1U << 30) // BIT_30_MASK
150 #define COMMAND_PACKET_ERROR_CHECK             (1U << 31) // BIT_30_MASK
151 
152 #define COMMAND_XFER_ARG_DATA_LEN_BITPOS        16U
153 #define COMMAND_XFER_DEF_BYTE_BITPOS            8U
154 
155 #define COMMAND_AA_TID_BITPOS                   3U
156 #define COMMAND_AA_CMD_BITPOS                   7U
157 #define COMMAND_AA_DEV_IDX_BITPOS               16U
158 #define COMMAND_AA_DEV_CNT_BITPOS               21U
159 
160 #define COMMAND_AA_RESPONSE_ON_COMPLETION       (1U << 26) // BIT_26_MASK
161 #define COMMAND_AA_STOP_ON_COMPLETION           (1U << 30) // BIT_30_MASK
162 
163 #define COMMAND_ATTR_XFER_CMD                   0U
164 #define COMMAND_ATTR_XFER_ARG                   1U
165 #define COMMAND_ATTR_SHORT_DATA_ARG             2U
166 #define COMMAND_ATTR_ADDR_ASSGN_CMD             3U
167 
168 /*--------------------------------RESPONSE QUEUE------------------------------*/
169 
170 #define RESPONSE_TID_BITPOS             24U
171 #define RESPONSE_TID_BITMASK            0x0FFFFFFF // Bits 24:27
172 
173 #define RESPONSE_ERR_STS_BITPOS         28U
174 #define RESPONSE_ERR_STS_BITMASK        0xF0FFFFFF
175 
176 /* For Target Response */
177 #define RESPONSE_TID_TGT_BITMASK        0x07FFFFFF // Bits 24:26
178 #define RESPONSE_RX_RESP_BITPOS          27U
179 #define RESPONSE_RX_RESP_BITMASK        0x0FFFFFFF // Bit 27
180 
181 #define RESPONSE_TID_DEFTGTS            0x7 /* TID 26:24 all 1 indicate DEFTGTS response */
182 
183 /*************************TARGET RESPONSE ERROR STATUS-------------------------*/
184 
185 #define TARGET_RESP_ERR_NO_ERROR                0U
186 #define TARGET_RESP_ERR_CRC                     1U
187 #define TARGET_RESP_ERR_PARITY                  2U
188 #define TARGET_RESP_ERR_FRAME                   3U
189 #define TARGET_RESP_ERR_UNDERFLOW_OVERFLOW      6U
190 #define TARGET_RESP_ERR_EARLY_TERM              10U
191 
192 
193 /*----------------------------IBI QUEUE STATUS---------------------------------*/
194 
195 #define IBI_QUEUE_STS_IBI_STS_BITPOS    28U
196 #define IBI_QUEUE_STS_IBI_ID            8U
197 
198 /*----------------------------IBI QUEUE CONTROL-------------------------------*/
199 
200 #define IBI_QUEUE_CTRL_SIR_REJ_BITPOS   3U
201 #define IBI_QUEUE_CTRL_MR_REJ_BITPOS    1U
202 #define IBI_QUEUE_CTRL_HJ_REJ_BITPOS    0U
203 
204 /*----------------------------QUEUE THRESHOLD---------------------------------*/
205 
206 /* 1 empty location in command queue to trigger CMD_QUEUE_READY_STAT Interrupt*/
207 #define QUEUE_THLD_CMD_QUEUE_EMPTY_1        1U
208 #define QUEUE_THLD_CMD_QUEUE_BITPOS         0U
209 
210 /* 1 entry in the Response Queue to trigger RESP_READY_STAT_INTR Interrupt */
211 #define QUEUE_THLD_RES_QUEUE_1              0U
212 #define QUEUE_THLD_RESP_QUEUE_BITPOS        8U
213 
214 /* 1 entry in the Response Queue to trigger RESP_READY_STAT_INTR Interrupt */
215 #define QUEUE_THLD_IBI_DATA_1               0U
216 #define QUEUE_THLD_IBI_DATA_BITPOS          16U
217 
218 /* 1 entry in the Response Queue to trigger RESP_READY_STAT_INTR Interrupt */
219 #define QUEUE_THLD_IBI_STATUS_1             0U
220 #define QUEUE_THLD_IBI_STATUS_BITPOS        24U
221 
222 /*----------------------------DATA BUFFER THRESHOLD---------------------------*/
223 /* Transmit FIFO Threshold values
224  * - Number of empty locations (or above) in the Transmit FIFO that
225  *   triggers the TX_THLD_STAT Interrupt */
226 #define DATA_BUF_THLD_TX_FIFO_EMPTY_1       0U
227 #define DATA_BUF_THLD_TX_FIFO_EMPTY_4       1U
228 #define DATA_BUF_THLD_TX_FIFO_EMPTY_8       2U
229 #define DATA_BUF_THLD_TX_FIFO_EMPTY_16      3U
230 #define DATA_BUF_THLD_TX_FIFO_EMPTY_32      4U
231 #define DATA_BUF_THLD_TX_FIFO_EMPTY_64      5U
232 
233 #define DATA_BUF_THLD_TX_FIFO_EMPTY_BITPOS  0U
234 
235 /* Receive FIFO Threshold values
236  * - Number of empty locations (or above) in the Receive FIFO that
237  *   triggers the RX_THLD_STAT Interrupt */
238 #define DATA_BUF_THLD_RX_FIFO_1             0U
239 #define DATA_BUF_THLD_RX_FIFO_4             1U
240 #define DATA_BUF_THLD_RX_FIFO_8             2U
241 #define DATA_BUF_THLD_RX_FIFO_16            3U
242 #define DATA_BUF_THLD_RX_FIFO_32            4U
243 #define DATA_BUF_THLD_RX_FIFO_64            5U
244 
245 #define DATA_BUF_THLD_RX_FIFO_BITPOS        8U
246 
247 /* Transfer Start Threshold values
248  * - Minimum number of entries in the Transmit FIFO for
249  *   controller mode write transfer or target to ACK read request */
250 #define DATA_BUF_THLD_TX_FIFO_START_1       0U
251 #define DATA_BUF_THLD_TX_FIFO_START_4       1U
252 #define DATA_BUF_THLD_TX_FIFO_START_8       2U
253 #define DATA_BUF_THLD_TX_FIFO_START_16      3U
254 #define DATA_BUF_THLD_TX_FIFO_START_32      4U
255 #define DATA_BUF_THLD_TX_FIFO_START_64      5U
256 
257 #define DATA_BUF_THLD_TX_FIFO_START_BITPOS  16U
258 
259 /* Receive Start Threshold values
260  * - Minimum number of entries in the Receive FIFO for
261  *   controller mode read transfer or target to ACK write request */
262 #define DATA_BUF_THLD_RX_FIFO_START_1       0U
263 #define DATA_BUF_THLD_RX_FIFO_START_4       1U
264 #define DATA_BUF_THLD_RX_FIFO_START_8       2U
265 #define DATA_BUF_THLD_RX_FIFO_START_16      3U
266 #define DATA_BUF_THLD_RX_FIFO_START_32      4U
267 #define DATA_BUF_THLD_RX_FIFO_START_64      5U
268 
269 #define DATA_BUF_THLD_RX_FIFO_START_BITPOS  24U
270 
271 /*--------------------------------RESET CONTROL-------------------------------*/
272 
273 #define RESET_CTRL_SOFT_RST                 (1U << 0)
274 #define RESET_CTRL_CMD_Q_RST                (1U << 1)
275 #define RESET_CTRL_RES_Q_RST                (1U << 2)
276 #define RESET_CTRL_TX_FIFO_RST              (1U << 3)
277 #define RESET_CTRL_RX_FIFO_RST              (1U << 4)
278 #define RESET_CTRL_IBI_Q_RST                (1U << 5)
279 #define RESET_CTRL_BUS_RST_TYPE_EXIT        (0)
280 #define RESET_CTRL_BUS_RST_TYPE_SCL_LOW_RST (3U << 29)
281 #define RESET_CTRL_BUS_RST                  (1U << 31)
282 
283 /*-----------------------------TARGET EVENT STATUS-----------------------------*/
284 
285 #define TGT_EVT_STS_SIR_EN                (1U << 0)
286 #define TGT_EVT_STS_MIR_EN                (1U << 1)
287 #define TGT_EVT_STS_HJEN                  (1U << 3)
288 #define TGT_EVT_STS_MRL_UPDATED           (1U << 6)
289 #define TGT_EVT_STS_MWL_UPDATED           (1U << 7)
290 
291 
292 /*---------------------------TARGET INTERRUPT REQUEST--------------------------*/
293 
294 #define TGT_INTR_REQ_SIR                  (1U << 0)
295 
296 #define TGT_INTR_REQ_MR                   (1U << 3)
297 #define TGT_INTR_REQ_TS                   (1U << 4)
298 
299 #define TGT_INTR_REQ_SIR_CTRL_BITPOS       1U
300 #define TGT_INTR_REQ_MDB_BITPOS            8U
301 #define TGT_INTR_REQ_SIR_DATALEN_BITPOS    16U
302 
303 /*-----------------------------TARGET IBI RESPONSE-----------------------------*/
304 
305 #define TGT_IBI_RESP_SUCCESS                  0x01
306 #define TGT_IBI_RESP_EARLY_TERMINATE          0x10
307 #define TGT_IBI_RESP_NOT_ATTEMPTED            0x11
308 
309 #define TGT_IBI_RESP_DATALEN_BITPOS           8U
310 
311 
312 /*-------------------------------QUEUE STATUS LEVEL---------------------------*/
313 
314 #define Q_STS_LVL_RESP_BUFFER_BIT_POS       8U
315 #define Q_STS_LVL_IBI_STS_CNT_BIT_POS       24U
316 
317 /*----------------------------DEVICE CONTROL EXTENDED-------------------------*/
318 
319 #define DEV_OPERATION_MODE_CTL          0U
320 #define DEV_OPERATION_MODE_TGT          1U
321 
322 #define DEV_REQMST_ACK_CTRL_NACK        (1U << 3)
323 
324 /*----------------------------HOST REGISTER CONFIGS---------------------------*/
325 #define HOST_CFG_PORT_SEL_I3C0                      0U
326 #define HOST_CFG_PORT_SEL_I3C1                      1U
327 #define HOST_CFG_PORT_SEL_I3C2                      2U
328 #define HOST_CFG_PORT_SEL_I2C0                      3U
329 #define HOST_CFG_PORT_SEL_BIT_POS                   0U
330 
331 #define HOST_CFG_DMA_TX_BURST_LENGTH_1              0U
332 #define HOST_CFG_DMA_TX_BURST_LENGTH_4              1U
333 #define HOST_CFG_DMA_TX_BURST_LENGTH_8              2U
334 #define HOST_CFG_DMA_TX_BURST_LENGTH_16             3U
335 #define HOST_CFG_DMA_TX_BURST_LENGTH_BIT_POS        8U
336 
337 #define HOST_CFG_TX_DMA_TOUT_DISABLE                0U
338 #define HOST_CFG_TX_DMA_TOUT_ENABLE                 1U
339 #define HOST_CFG_TX_DMA_TOUT_BITPOS                 12U
340 
341 #define HOST_CFG_TX_DMA_CONT_TX                     0U
342 #define HOST_CFG_TX_DMA_ABORT_TX                    1U
343 #define HOST_CFG_TX_DMA_ABORT_BITPOS                13U
344 
345 #define HOST_CFG_DMA_RX_BURST_LENGTH_1              0U
346 #define HOST_CFG_DMA_RX_BURST_LENGTH_4              1U
347 #define HOST_CFG_DMA_RX_BURST_LENGTH_8              2U
348 #define HOST_CFG_DMA_RX_BURST_LENGTH_16             3U
349 #define HOST_CFG_DMA_RX_BURST_LENGTH_BIT_POS        16U
350 
351 #define HOST_CFG_RX_DMA_TOUT_DISABLE                0U
352 #define HOST_CFG_RX_DMA_TOUT_ENABLE                 1U
353 #define HOST_CFG_RX_DMA_TOUT_BITPOS                 20U
354 
355 #define HOST_CFG_RX_DMA_CONT_TX                     0U
356 #define HOST_CFG_RX_DMA_ABORT_TX                    1U
357 #define HOST_CFG_RX_DMA_ABORT_BITPOS                21U
358 
359 #define HOST_CFG_STUCK_SDA_DISABLE                  0U
360 #define HOST_CFG_STUCK_SDA_ENABLE                   1U
361 #define HOST_CFG_STUCK_SDA_EN_BIT_POS               24U
362 
363 #define HOST_RST_SOFT_RESET                         1U
364 #define HOST_RST_SOFT_RESET_BITPOS                  0U
365 
366 #define HOST_RST_DMA_TX_IF_RESET                    1U
367 #define HOST_RST_DMA_TX_IF_RESET_BITPOS             4U
368 
369 #define HOST_RST_DMA_RX_IF_RESET                    1U
370 #define HOST_RST_DMA_RX_IF_RESET_BITPOS             5U
371 /************************************************************************/
372 #define SEC_HOST_CFG_PORT_SEL_I3C0                      0U
373 #define SEC_HOST_CFG_PORT_SEL_I3C1                      1U
374 #define SEC_HOST_CFG_PORT_SEL_I3C2                      2U
375 #define SEC_HOST_CFG_PORT_SEL_BIT_POS                   0U
376 
377 #define SEC_HOST_CFG_DMA_TX_BURST_LENGTH_1              0U
378 #define SEC_HOST_CFG_DMA_TX_BURST_LENGTH_4              1U
379 #define SEC_HOST_CFG_DMA_TX_BURST_LENGTH_8              2U
380 #define SEC_HOST_CFG_DMA_TX_BURST_LENGTH_16             3U
381 #define SEC_HOST_CFG_DMA_TX_BURST_LENGTH_32             4U
382 #define SEC_HOST_CFG_DMA_TX_BURST_LENGTH_64             5U
383 #define SEC_HOST_CFG_DMA_TX_BURST_LENGTH_BIT_POS        8U
384 
385 #define SEC_HOST_CFG_TX_DMA_FSM_DISABLE                 0U
386 #define SEC_HOST_CFG_TX_DMA_FSM_ENABLE                  1U
387 #define SEC_HOST_CFG_TX_DMA_FSM_BITPOS                 11U
388 
389 #define SEC_HOST_CFG_TX_DMA_CONT_TX                     0U
390 #define SEC_HOST_CFG_TX_DMA_ABORT_TX                    1U
391 #define SEC_HOST_CFG_TX_DMA_ABORT_BITPOS                13U
392 
393 #define SEC_HOST_CFG_DMA_RX_BURST_LENGTH_1              0U
394 #define SEC_HOST_CFG_DMA_RX_BURST_LENGTH_4              1U
395 #define SEC_HOST_CFG_DMA_RX_BURST_LENGTH_8              2U
396 #define SEC_HOST_CFG_DMA_RX_BURST_LENGTH_16             3U
397 #define SEC_HOST_CFG_DMA_RX_BURST_LENGTH_32             4U
398 #define SEC_HOST_CFG_DMA_RX_BURST_LENGTH_64             5U
399 #define SEC_HOST_CFG_DMA_RX_BURST_LENGTH_BIT_POS        16U
400 
401 #define SEC_HOST_CFG_RX_DMA_FSM_DISABLE                 0U
402 #define SEC_HOST_CFG_RX_DMA_FSM_ENABLE                  1U
403 #define SEC_HOST_CFG_RX_DMA_FSM_BITPOS                 19U
404 
405 #define SEC_HOST_CFG_RX_DMA_CONT_TX                     0U
406 #define SEC_HOST_CFG_RX_DMA_ABORT_TX                    1U
407 #define SEC_HOST_CFG_RX_DMA_ABORT_BITPOS                21U
408 
409 #define SEC_HOST_CFG_STUCK_SDA_SCL_DISABLE              0U
410 #define SEC_HOST_CFG_STUCK_SDA_SCL_ENABLE               1U
411 #define SEC_HOST_CFG_STUCK_SDA_EN_BIT_POS               24U
412 
413 #define SEC_HOST_CFG_STUCK_SDA_CLK_SEL_2MHZ             0U
414 #define SEC_HOST_CFG_STUCK_SDA_CLK_SEL_32KHZ            1U
415 #define SEC_HOST_CFG_STUCK_SDA_CLK_SEL_BITPOS           25U
416 
417 #define SEC_HOST_CFG_SCL_LOW_DET_DISABLE                0U
418 #define SEC_HOST_CFG_SCL_LOW_DET_ENABLE                 1U
419 #define SEC_HOST_CFG_SCL_LOW_DET_EN_BITPOS              28U
420 
421 #define SEC_HOST_RST_SOFT_RESET                         1U
422 #define SEC_HOST_RST_SOFT_RESET_BITPOS                  0U
423 
424 #define SEC_HOST_RST_DMA_TX_IF_RESET                    1U
425 #define SEC_HOST_RST_DMA_TX_IF_RESET_BITPOS             4U
426 
427 #define SEC_HOST_RST_DMA_RX_IF_RESET                    1U
428 #define SEC_HOST_RST_DMA_RX_IF_RESET_BITPOS             5U
429 
430 #define SEC_HOST_CFG_STUCK_SDA_TOUT_BITPOS              0U
431 #define SEC_HOST_CFG_STUCK_SCL_TOUT_BITPOS              16U
432 /******************************************************************************/
433 
434 
435 #define RD_TERM_BIT_LCNT_0                              0U
436 #define RD_TERM_BIT_LCNT_1                              1U
437 #define RD_TERM_BIT_LCNT_2                              2U
438 #define RD_TERM_BIT_LCNT_3                              3U
439 #define RD_TERM_BIT_LCNT_4                              4U
440 #define RD_TERM_BIT_LCNT_5                              5U
441 #define RD_TERM_BIT_LCNT_6                              6U
442 #define RD_TERM_BIT_LCNT_7                              7U
443 
444 /*-------------------SDA HOLD SWITCH DLY TIMING-----------------*/
445 #define SDA_OD_PP_SWITCH_DLY_0                          0U
446 #define SDA_OD_PP_SWITCH_DLY_1                          1U
447 #define SDA_OD_PP_SWITCH_DLY_2                          2U
448 #define SDA_OD_PP_SWITCH_DLY_3                          3U
449 #define SDA_OD_PP_SWITCH_DLY_4                          4U
450 #define SDA_OD_PP_SWITCH_DLY_BITPOS                     0U
451 
452 #define SDA_PP_OD_SWITCH_DLY_0                          0U
453 #define SDA_PP_OD_SWITCH_DLY_1                          1U
454 #define SDA_PP_OD_SWITCH_DLY_2                          2U
455 #define SDA_PP_OD_SWITCH_DLY_3                          3U
456 #define SDA_PP_OD_SWITCH_DLY_4                          4U
457 #define SDA_PP_OD_SWITCH_DLY_BITPOS                     8U
458 
459 #define SDA_TX_HOLD_1                                   1U
460 #define SDA_TX_HOLD_2                                   2U
461 #define SDA_TX_HOLD_3                                   3U
462 #define SDA_TX_HOLD_4                                   4U
463 #define SDA_TX_HOLD_5                                   5U
464 #define SDA_TX_HOLD_6                                   6U
465 #define SDA_TX_HOLD_7                                   7U
466 #define SDA_TX_HOLD_BITPOS                              16U
467 
468 /*-------------------SCL HOLD SWITCH DLY TIMING-----------------*/
469 
470 /*--------------TGT_PID_VALUE and TGT_MIPI_ID_VALUE-------------*/
471 #define TGT_PID_DCR_BITPOS                              0U
472 #define TGT_INST_ID_BITPOS                              12U
473 #define TGT_PART_ID_BITPOS                              16U
474 
475 #define TGT_PROV_ID_SEL_BITPOS                          0U
476 #define TGT_MIPI_MFG_ID_BITPOS                          1U
477 /*--------------TGT_PID_VALUE and TGT_MIPI_ID_VALUE-------------*/
478 
479 /*------------------------------MXDS----------------------------*/
480 #define MXDS_MAX_WR_SPEED_12P5_MHZ                       0U
481 #define MXDS_MAX_WR_SPEED_8_MHZ                          1U
482 #define MXDS_MAX_WR_SPEED_6_MHZ                          2U
483 #define MXDS_MAX_WR_SPEED_4_MHZ                          3U
484 #define MXDS_MAX_WR_SPEED_2_MHZ                          4U
485 #define MXDS_MAX_WR_SPEED_BITPOS                         0U
486 
487 #define MXDS_MAX_RD_SPEED_12P5_MHZ                       0U
488 #define MXDS_MAX_RD_SPEED_8_MHZ                          1U
489 #define MXDS_MAX_RD_SPEED_6_MHZ                          2U
490 #define MXDS_MAX_RD_SPEED_4_MHZ                          3U
491 #define MXDS_MAX_RD_SPEED_2_MHZ                          4U
492 #define MXDS_MAX_RD_SPEED_BITPOS                         8U
493 
494 #define MXDS_TSCO_8_NS                                   0U
495 #define MXDS_TSCO_9_NS                                   1U
496 #define MXDS_TSCO_10_NS                                  2U
497 #define MXDS_TSCO_11_NS                                  3U
498 #define MXDS_TSCO_12_NS                                  4U
499 #define MXDS_TSCO_BITPOS                                 16U
500 
501 #define MXDS_MAX_RD_TURN_MASK(x)                        (x & MEC_GENMASK(23, 0))
502 /*------------------------------MXDS----------------------------*/
503 
504 /*------------------------------MRL AND MWL----------------------------*/
505 #define MWL_BITPOS                                         0U
506 #define MRL_BITPOS                                         16U
507 /*------------------------------MRL AND MWL----------------------------*/
508 
509 /*-------------------Device Address Table Location of Device1-----------------*/
510 
511 #define DEV_ADDR_TABLE1_LOC1_DEVICE_I2C             (1U << 31) // BIT_31_MASK
512 #define DEV_ADDR_TABLE1_LOC1_NACK_RETRY_COUNT(n)    ((uint32_t)(n & 0x3) << 29)
513 #define DEV_ADDR_TABLE1_LOC1_PARITY                 (1U << 23) // BIT_23_MASK
514 #define DEV_ADDR_TABLE1_LOC1_DYNAMIC_ADDR(addr)     ((uint32_t)(addr & 0x7F) << 16)
515 #define DEV_ADDR_TABLE1_LOC1_MR_REJECT              (1U << 14) // BIT_14_MASK
516 #define DEV_ADDR_TABLE1_LOC1_SIR_REJECT             (1U << 13) // BIT_13_MASK
517 #define DEV_ADDR_TABLE1_LOC1_IBI_WITH_DATA          (1U << 12) // BIT_12_MASK
518 #define DEV_ADDR_TABLE1_LOC1_IBI_PEC_EN             (1U << 11) // BIT_11_MASK
519 #define DEV_ADDR_TABLE1_LOC1_STATIC_ADDR(addr)      (uint32_t)(addr & 0x7F)
520 
521 /*----------------------------INTERRUPT STATUS BITS---------------------------*/
522 
523 enum interrupt_status_reg_bits
524 {
525     sbit_TX_THLD_STS            = (1U << 0)  // BIT_0_MASK
526    ,sbit_RX_THLD_STS            = (1U << 1)  // BIT_1_MASK
527    ,sbit_IBI_THLD_STS           = (1U << 2)  // BIT_2_MASK
528    ,sbit_CMD_QUEUE_READY_STS    = (1U << 3)  // BIT_3_MASK
529    ,sbit_RESP_READY_STS         = (1U << 4)  // BIT_4_MASK
530    ,sbit_TRANSFER_ABORT_STS     = (1U << 5)  // BIT_5_MASK
531    ,sbit_CCC_UPDATED_STS        = (1U << 6)  // BIT_6_MASK
532    ,sbit_DYN_ADDR_ASSIGN_STS    = (1U << 8)  // BIT_8_MASK
533    ,sbit_TRANSFER_ERR_STS       = (1U << 9)  // BIT_9_MASK
534    ,sbit_DEFTGT_STS             = (1U << 10) // BIT_10_MASK
535    ,sbit_READ_REQ_RECV_STS      = (1U << 11) // BIT_11_MASK
536    ,sbit_IBI_UPDATED_STS        = (1U << 12) // BIT_12_MASK
537    ,sbit_BUSOWNER_UPDATED_STS   = (1U << 13) // BIT_13_MASK
538    ,sbit_BUS_RESET_DONE_STS     = (1U << 15) // BIT_15_MASK
539 };
540 
541 //MAX_DATA_SPEED register
542 #define TGT_MAX_WR_DATA_SPEED_POS 0
543 #define TGT_MAX_RD_DATA_SPEED_POS 8
544 #define TGT_CLK_TO_DATA_TURN_POS 16
545 
546 #define TGT_MAX_WR_DATA_SPEED_MASK 7
547 #define TGT_MAX_RD_DATA_SPEED_MASK 7
548 #define TGT_CLK_TO_DATA_TURN_MASK 7
549 
550 /*------------------------------MXDS_MAX_RD_SPEED----------------------*/
551 #define MAX_DATA_SPEED_RD_12_5_MHZ    0U
552 #define MAX_DATA_SPEED_RD_8_MHZ       1U
553 #define MAX_DATA_SPEED_RD_6_MHZ       2U
554 #define MAX_DATA_SPEED_RD_4_MHZ       3U
555 #define MAX_DATA_SPEED_RD_2_MHZ       4U
556 /*------------------------------MXDS_MAX_RD_SPEED----------------------*/
557 
558 /*------------------------------MXDS_MAX_WR_SPEED----------------------*/
559 #define MAX_DATA_SPEED_WR_12_5_MHZ    0U
560 #define MAX_DATA_SPEED_WR_8_MHZ       1U
561 #define MAX_DATA_SPEED_WR_6_MHZ       2U
562 #define MAX_DATA_SPEED_WR_4_MHZ       3U
563 #define MAX_DATA_SPEED_WR_2_MHZ       4U
564 /*------------------------------MXDS_MAX_WR_SPEED----------------------*/
565 
566 /*------------------------------MXDS_CLK_DATA_TURN----------------------*/
567 #define MAX_CLK_DATA_TURN_8_ns    0U
568 #define MAX_CLK_DATA_TURN_9_ns    1U
569 #define MAX_CLK_DATA_TURN_10_ns   2U
570 #define MAX_CLK_DATA_TURN_11_ns   3U
571 #define MAX_CLK_DATA_TURN_12_ns   4U
572 /*------------------------------MXDS_CLK_DATA_TURN----------------------*/
573 
574 /* forward declarations */
575 struct mec_i3c_host_regs;
576 struct mec_i3c_sec_regs;
577 
578 uint32_t _i3c_intr_sts_get(struct mec_i3c_host_regs *regs);
579 void _i3c_intr_sts_clear(struct mec_i3c_host_regs *regs, uint32_t mask);
580 void _i3c_intr_sts_enable(struct mec_i3c_host_regs *regs, uint32_t mask);
581 void _i3c_intr_sgnl_enable(struct mec_i3c_host_regs *regs, uint32_t mask);
582 void _i3c_intr_IBI_enable(struct mec_i3c_host_regs *regs);
583 void _i3c_intr_IBI_disable(struct mec_i3c_host_regs *regs);
584 
585 void _i3c_resp_buf_threshold_set(struct mec_i3c_host_regs *regs, uint8_t threshold);
586 void _i3c_cmd_queue_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
587 void _i3c_tx_fifo_empty_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
588 void _i3c_rx_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
589 void _i3c_tx_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
590 void _i3c_tx_start_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
591 void _i3c_rx_start_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
592 
593 void _i3c_notify_sir_reject(struct mec_i3c_host_regs *regs, bool opt);
594 void _i3c_notify_mr_reject(struct mec_i3c_host_regs *regs, bool opt);
595 void _i3c_notify_hj_reject(struct mec_i3c_host_regs *regs, bool opt);
596 
597 void _i3c_resp_queue_threshold_set(struct mec_i3c_host_regs *regs, uint8_t threshold);
598 void _i3c_cmd_queue_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
599 void _i3c_ibi_data_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
600 void _i3c_ibi_status_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
601 uint32_t _i3c_ibi_queue_status_get(struct mec_i3c_host_regs *regs);
602 
603 void _i3c_dynamic_addr_set(struct mec_i3c_host_regs *regs, uint8_t address);
604 void _i3c_static_addr_set(struct mec_i3c_host_regs *regs, uint8_t address);
605 
606 void _i3c_operation_mode_set(struct mec_i3c_host_regs *regs, uint8_t mode);
607 
608 void _i3c_hot_join_disable(struct mec_i3c_host_regs *regs);
609 void _i3c_hot_join_enable(struct mec_i3c_host_regs *regs);
610 
611 /* controller mode (cm) or target mode (tm) request reject internal API */
612 void _i3c_ibi_cm_req_reject(struct mec_i3c_host_regs *regs);
613 void _i3c_ibi_tm_intr_req_reject(struct mec_i3c_host_regs *regs);
614 
615 void _i3c_enable(struct mec_i3c_host_regs *regs, uint8_t mode, bool enable_dma);
616 void _i3c_disable(struct mec_i3c_host_regs *regs);
617 void _i3c_resume(struct mec_i3c_host_regs *regs);
618 
619 void _i3c_push_pull_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns,
620                                uint32_t i3c_freq_ns);
621 
622 void _i3c_open_drain_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns,
623                                 uint32_t i3c_freq_ns);
624 
625 void _i3c_bus_free_timing_set(struct mec_i3c_sec_regs *regs, uint32_t core_clk_freq_ns);
626 void _i3c_bus_available_timing_set(struct mec_i3c_sec_regs *regs, uint32_t core_clk_freq_ns);
627 void _i3c_bus_idle_timing_set(struct mec_i3c_sec_regs *regs, uint32_t core_clk_freq_ns);
628 void _i3c_read_term_bit_low_count_set(struct mec_i3c_host_regs *regs,
629                                             uint8_t read_term_low_count);
630 void _i3c_sda_hld_timing_set(struct mec_i3c_host_regs *regs,
631                                             uint8_t sda_tx_hold);
632 void _i3c_sda_hld_switch_delay_timing_set(struct mec_i3c_sec_regs *regs,
633                                             uint8_t sda_od_pp_switch_dly,
634                                             uint8_t sda_pp_od_switch_dly,
635                                             uint8_t sda_tx_hold);
636 void _i3c_scl_low_mst_tout_set(struct mec_i3c_sec_regs *regs, uint32_t tout_val);
637 
638 void _i2c_fm_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns);
639 void _i2c_fmp_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns);
640 void _i2c_target_present_set (struct mec_i3c_host_regs *regs);
641 void _i2c_target_present_reset (struct mec_i3c_host_regs *regs);
642 
643 void _i3c_host_dma_tx_burst_length_set(struct mec_i3c_host_regs *regs, uint32_t val);
644 void _i3c_host_dma_rx_burst_length_set(struct mec_i3c_host_regs *regs, uint32_t val);
645 void _i3c_host_port_set(struct mec_i3c_host_regs *regs, uint32_t val);
646 void _i3c_host_stuck_sda_config(struct mec_i3c_host_regs *regs, uint32_t val,
647                                 uint32_t tout_val);
648 void _i3c_host_tx_dma_tout_config(struct mec_i3c_host_regs *regs, uint32_t val,
649                                   uint32_t tout_val);
650 void _i3c_host_rx_dma_tout_config(struct mec_i3c_host_regs *regs, uint32_t val,
651                                   uint32_t tout_val);
652 
653 void _i3c_sec_host_dma_tx_burst_length_set(struct mec_i3c_sec_regs *regs, uint32_t val);
654 void _i3c_sec_host_dma_rx_burst_length_set(struct mec_i3c_sec_regs *regs, uint32_t val);
655 void _i3c_sec_host_port_set(struct mec_i3c_sec_regs *regs, uint32_t val);
656 void _i3c_sec_host_stuck_sda_scl_config(struct mec_i3c_sec_regs *regs, uint32_t en,
657                                         uint32_t sda_tout_val, uint32_t scl_tout_val);
658 void _i3c_sec_host_tx_dma_tout_config(struct mec_i3c_sec_regs *regs, uint32_t val,
659                                       uint32_t tout_val);
660 void _i3c_sec_host_rx_dma_tout_config(struct mec_i3c_sec_regs *regs, uint32_t val,
661                                       uint32_t tout_val);
662 void _i3c_sec_host_dma_fsm_enable(struct mec_i3c_sec_regs *regs);
663 
664 void _i3c_dev_addr_table_ptr_get(struct mec_i3c_host_regs *regs, uint16_t *start_addr,
665                                  uint16_t *depth);
666 void _i3c_dev_char_table_ptr_get(struct mec_i3c_host_regs *regs, uint16_t *start_addr,
667                                  uint16_t *depth);
668 
669 uint8_t _i3c_dev_operation_mode_get(struct mec_i3c_host_regs *regs);
670 
671 uint8_t _i3c_dev_controller_role_get(struct mec_i3c_host_regs *regs);
672 
673 uint8_t _i3c_dev_role_config_get(struct mec_i3c_host_regs *regs);
674 
675 void _i3c_DAT_write(struct mec_i3c_host_regs *regs, uint16_t DAT_start, uint8_t DAT_idx,
676                     uint32_t val);
677 uint32_t _i3c_DAT_read(struct mec_i3c_host_regs *regs, uint16_t DAT_start, uint8_t DAT_idx);
678 void _i3c_DCT_read(struct mec_i3c_host_regs *regs, uint16_t DCT_start, uint8_t DCT_idx,
679                    struct mec_i3c_DCT_info *info);
680 
681 void _i3c_fifo_write(struct mec_i3c_host_regs *regs, uint8_t *buffer, uint16_t len);
682 void _i3c_command_write(struct mec_i3c_host_regs *regs, uint32_t cmd);
683 
684 uint8_t _i3c_resp_buf_level_get(struct mec_i3c_host_regs *regs);
685 uint8_t _i3c_ibi_status_count_get(struct mec_i3c_host_regs *regs);
686 
687 uint8_t _i3c_response_sts_get(struct mec_i3c_host_regs *regs, uint16_t *len, uint8_t *tid);
688 void _i3c_fifo_read(struct mec_i3c_host_regs *regs, uint8_t *buffer, uint16_t len);
689 void _i3c_ibi_data_read(struct mec_i3c_host_regs *regs, uint8_t *buffer, uint16_t len);
690 
691 void _i3c_xfers_reset(struct mec_i3c_host_regs *regs);
692 void _i3c_soft_reset(struct mec_i3c_host_regs *regs);
693 
694 void _i3c_xfer_err_sts_clr(struct mec_i3c_host_regs *regs);
695 
696 uint8_t _i3c_cmd_fifo_depth_get(struct mec_i3c_host_regs *regs);
697 uint8_t _i3c_tx_fifo_depth_get(struct mec_i3c_host_regs *regs);
698 uint8_t _i3c_rx_fifo_depth_get(struct mec_i3c_host_regs *regs);
699 uint8_t _i3c_resp_fifo_depth_get(struct mec_i3c_host_regs *regs);
700 uint8_t _i3c_ibi_fifo_depth_get(struct mec_i3c_host_regs *regs);
701 
702 
703 void _i3c_tx_fifo_rst(struct mec_i3c_host_regs *regs);
704 void _i3c_rx_fifo_rst(struct mec_i3c_host_regs *regs);
705 void _i3c_cmd_queue_rst(struct mec_i3c_host_regs *regs);
706 
707 void _i3c_SDCT_read(struct mec_i3c_host_regs *regs, uint16_t DCT_start, uint8_t DCT_idx,
708                     struct mec_i3c_SDCT_info *info);
709 
710 void _i3c_intr_thresholds_tx_enable(struct mec_i3c_host_regs *regs);
711 void _i3c_intr_thresholds_tx_disable(struct mec_i3c_host_regs *regs);
712 void _i3c_intr_thresholds_rx_enable(struct mec_i3c_host_regs *regs);
713 void _i3c_intr_thresholds_rx_disable(struct mec_i3c_host_regs *regs);
714 
715 /* Secondary Controller specific functions */
716 
717 void _i3c_tgt_pid_set(struct mec_i3c_sec_regs *regs,
718                         uint16_t tgt_mipi_mfg_id,
719                         bool is_random_prov_id,
720                         uint16_t tgt_part_id,
721                         uint8_t tgt_inst_id,
722                         uint16_t tgt_pid_dcr);
723 bool _i3c_tgt_dyn_addr_valid_get(struct mec_i3c_sec_regs *regs);
724 uint8_t _i3c_tgt_dyn_addr_get(struct mec_i3c_sec_regs *regs);
725 void _i3c_tgt_mrl_set(struct mec_i3c_sec_regs *regs, uint16_t mrl);
726 void _i3c_tgt_mwl_set(struct mec_i3c_sec_regs *regs, uint16_t mwl);
727 void _i3c_tgt_mxds_set(struct mec_i3c_sec_regs *regs,
728                         uint8_t wr_speed,
729                         uint8_t rd_speed,
730                         uint8_t tsco,
731                         uint32_t rd_trnd_us);
732 bool _i3c_tgt_SIR_enabled(struct mec_i3c_sec_regs *regs);
733 bool _i3c_tgt_MR_enabled(struct mec_i3c_sec_regs *regs);
734 void _i3c_tgt_raise_ibi_SIR(struct mec_i3c_sec_regs *regs, uint8_t *sir_data, uint8_t sir_datalen,
735                             uint8_t mdb);
736 void _i3c_tgt_raise_ibi_MR(struct mec_i3c_sec_regs *regs);
737 bool _i3c_tgt_ibi_resp_get(struct mec_i3c_sec_regs *regs, uint8_t *sir_rem_datalen);
738 
739 uint8_t _i3c_tgt_response_sts_get(struct mec_i3c_sec_regs *regs, uint16_t *len, uint8_t *tid,
740                                   bool *rx_response);
741 
742 void _i3c_tgt_MRL_get(struct mec_i3c_sec_regs *regs, uint16_t *max_rd_len);
743 void _i3c_tgt_MWL_get(struct mec_i3c_sec_regs *regs, uint16_t *max_wr_len);
744 void _i3c_tgt_MRL_MWL_set(struct mec_i3c_sec_regs *regs, uint16_t max_rd_len,
745                           uint16_t max_wr_len);
746 
747 bool _i3c_tgt_MRL_updated(struct mec_i3c_sec_regs *regs);
748 bool _i3c_tgt_MWL_updated(struct mec_i3c_sec_regs *regs);
749 void _i3c_tgt_hot_join_disable(struct mec_i3c_sec_regs *regs);
750 
751 void _i3c_tgt_max_speed_update(struct mec_i3c_sec_regs *regs, uint8_t max_rd_speed,
752                                uint8_t max_wr_speed);
753 void _i3c_tgt_clk_to_data_turn_update(struct mec_i3c_sec_regs *regs, uint8_t clk_data_turn_time);
754 
755 
756 #endif /* _MEC_I3C_PVT_H_ */
757