1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_PS2_V1_H 7 #define _MEC5_PS2_V1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief PS/2 controller 0 (MEC_PS2CTL) 15 */ 16 17 typedef struct mec_ps2_regs { /*!< (@ 0x40009000) MEC_PS2CTL Structure */ 18 __IOM uint8_t RTXB; /*!< (@ 0x00000000) PS2 receive buffer(RO), transmit buffer(WO) */ 19 __IM uint8_t RESERVED[3]; 20 __IOM uint8_t CTRL; /*!< (@ 0x00000004) PS2 control */ 21 __IM uint8_t RESERVED1[3]; 22 __IOM uint8_t STATUS; /*!< (@ 0x00000008) PS2 status */ 23 } MEC_PS2_Type; /*!< Size = 9 (0x9) */ 24 25 /** @} */ /* End of group Device_Peripheral_peripherals */ 26 27 /** @addtogroup PosMask_peripherals 28 * @{ 29 */ 30 /* ========================================================= CTRL ========================================================== */ 31 #define MEC_PS2_CTRL_TREN_Pos (0UL) /*!< TREN (Bit 0) */ 32 #define MEC_PS2_CTRL_TREN_Msk (0x1UL) /*!< TREN (Bitfield-Mask: 0x01) */ 33 #define MEC_PS2_CTRL_ENABLE_Pos (1UL) /*!< ENABLE (Bit 1) */ 34 #define MEC_PS2_CTRL_ENABLE_Msk (0x2UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ 35 #define MEC_PS2_CTRL_PARITY_Pos (2UL) /*!< PARITY (Bit 2) */ 36 #define MEC_PS2_CTRL_PARITY_Msk (0xcUL) /*!< PARITY (Bitfield-Mask: 0x03) */ 37 #define MEC_PS2_CTRL_STOP_Pos (4UL) /*!< STOP (Bit 4) */ 38 #define MEC_PS2_CTRL_STOP_Msk (0x30UL) /*!< STOP (Bitfield-Mask: 0x03) */ 39 /* ======================================================== STATUS ========================================================= */ 40 #define MEC_PS2_STATUS_RDRDY_Pos (0UL) /*!< RDRDY (Bit 0) */ 41 #define MEC_PS2_STATUS_RDRDY_Msk (0x1UL) /*!< RDRDY (Bitfield-Mask: 0x01) */ 42 #define MEC_PS2_STATUS_RXTMO_Pos (1UL) /*!< RXTMO (Bit 1) */ 43 #define MEC_PS2_STATUS_RXTMO_Msk (0x2UL) /*!< RXTMO (Bitfield-Mask: 0x01) */ 44 #define MEC_PS2_STATUS_PE_Pos (2UL) /*!< PE (Bit 2) */ 45 #define MEC_PS2_STATUS_PE_Msk (0x4UL) /*!< PE (Bitfield-Mask: 0x01) */ 46 #define MEC_PS2_STATUS_FE_Pos (3UL) /*!< FE (Bit 3) */ 47 #define MEC_PS2_STATUS_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */ 48 #define MEC_PS2_STATUS_TXIDLE_Pos (4UL) /*!< TXIDLE (Bit 4) */ 49 #define MEC_PS2_STATUS_TXIDLE_Msk (0x10UL) /*!< TXIDLE (Bitfield-Mask: 0x01) */ 50 #define MEC_PS2_STATUS_TXTMO_Pos (5UL) /*!< TXTMO (Bit 5) */ 51 #define MEC_PS2_STATUS_TXTMO_Msk (0x20UL) /*!< TXTMO (Bitfield-Mask: 0x01) */ 52 #define MEC_PS2_STATUS_RXBUSY_Pos (6UL) /*!< RXBUSY (Bit 6) */ 53 #define MEC_PS2_STATUS_RXBUSY_Msk (0x40UL) /*!< RXBUSY (Bitfield-Mask: 0x01) */ 54 #define MEC_PS2_STATUS_TXSTTMO_Pos (7UL) /*!< TXSTTMO (Bit 7) */ 55 #define MEC_PS2_STATUS_TXSTTMO_Msk (0x80UL) /*!< TXSTTMO (Bitfield-Mask: 0x01) */ 56 57 /** @} */ /* End of group PosMask_peripherals */ 58 59 /** @addtogroup EnumValue_peripherals 60 * @{ 61 */ 62 /* ========================================================= CTRL ========================================================== */ 63 /* ============================================= MEC_PS2CTL CTRL TREN [0..0] ============================================== */ 64 typedef enum { /*!< MEC_PS2CTL_CTRL_TREN */ 65 MEC_PS2CTL_CTRL_TREN_ON = 1, /*!< ON : Enable */ 66 } MEC_PS2CTL_CTRL_TREN_Enum; 67 68 /* ============================================ MEC_PS2CTL CTRL ENABLE [1..1] ============================================= */ 69 typedef enum { /*!< MEC_PS2CTL_CTRL_ENABLE */ 70 MEC_PS2CTL_CTRL_ENABLE_ON = 1, /*!< ON : Enable */ 71 } MEC_PS2CTL_CTRL_ENABLE_Enum; 72 73 /* ============================================ MEC_PS2CTL CTRL PARITY [2..3] ============================================= */ 74 typedef enum { /*!< MEC_PS2CTL_CTRL_PARITY */ 75 MEC_PS2CTL_CTRL_PARITY_ODD = 0, /*!< ODD : Odd parity */ 76 MEC_PS2CTL_CTRL_PARITY_EVEN = 1, /*!< EVEN : Even parity */ 77 MEC_PS2CTL_CTRL_PARITY_IGNORE = 2, /*!< IGNORE : 10th bit is not intepreted as parity */ 78 } MEC_PS2CTL_CTRL_PARITY_Enum; 79 80 /* ============================================= MEC_PS2CTL CTRL STOP [4..5] ============================================== */ 81 typedef enum { /*!< MEC_PS2CTL_CTRL_STOP */ 82 MEC_PS2CTL_CTRL_STOP_HI = 0, /*!< HI : Receiver expects active High STOP bit */ 83 MEC_PS2CTL_CTRL_STOP_LO = 1, /*!< LO : Receiver expects active Low STOP bit */ 84 MEC_PS2CTL_CTRL_STOP_IGNORE = 2, /*!< IGNORE : Receiver ignores STOP(11th bit not interpreted as STOP) */ 85 } MEC_PS2CTL_CTRL_STOP_Enum; 86 87 /* ======================================================== STATUS ========================================================= */ 88 /* ============================================ MEC_PS2CTL STATUS RDRDY [0..0] ============================================ */ 89 typedef enum { /*!< MEC_PS2CTL_STATUS_RDRDY */ 90 MEC_PS2CTL_STATUS_RDRDY_ACTIVE = 1, /*!< ACTIVE : Active */ 91 } MEC_PS2CTL_STATUS_RDRDY_Enum; 92 93 /* ============================================ MEC_PS2CTL STATUS RXTMO [1..1] ============================================ */ 94 typedef enum { /*!< MEC_PS2CTL_STATUS_RXTMO */ 95 MEC_PS2CTL_STATUS_RXTMO_ACTIVE = 1, /*!< ACTIVE : Active */ 96 } MEC_PS2CTL_STATUS_RXTMO_Enum; 97 98 /* ============================================= MEC_PS2CTL STATUS PE [2..2] ============================================== */ 99 typedef enum { /*!< MEC_PS2CTL_STATUS_PE */ 100 MEC_PS2CTL_STATUS_PE_ACTIVE = 1, /*!< ACTIVE : Active */ 101 } MEC_PS2CTL_STATUS_PE_Enum; 102 103 /* ============================================= MEC_PS2CTL STATUS FE [3..3] ============================================== */ 104 typedef enum { /*!< MEC_PS2CTL_STATUS_FE */ 105 MEC_PS2CTL_STATUS_FE_ACTIVE = 1, /*!< ACTIVE : Active */ 106 } MEC_PS2CTL_STATUS_FE_Enum; 107 108 /* =========================================== MEC_PS2CTL STATUS TXIDLE [4..4] ============================================ */ 109 typedef enum { /*!< MEC_PS2CTL_STATUS_TXIDLE */ 110 MEC_PS2CTL_STATUS_TXIDLE_ACTIVE = 1, /*!< ACTIVE : Active */ 111 } MEC_PS2CTL_STATUS_TXIDLE_Enum; 112 113 /* ============================================ MEC_PS2CTL STATUS TXTMO [5..5] ============================================ */ 114 typedef enum { /*!< MEC_PS2CTL_STATUS_TXTMO */ 115 MEC_PS2CTL_STATUS_TXTMO_ACTIVE = 1, /*!< ACTIVE : Active */ 116 } MEC_PS2CTL_STATUS_TXTMO_Enum; 117 118 /* =========================================== MEC_PS2CTL STATUS RXBUSY [6..6] ============================================ */ 119 typedef enum { /*!< MEC_PS2CTL_STATUS_RXBUSY */ 120 MEC_PS2CTL_STATUS_RXBUSY_ACTIVE = 1, /*!< ACTIVE : Active */ 121 } MEC_PS2CTL_STATUS_RXBUSY_Enum; 122 123 /* =========================================== MEC_PS2CTL STATUS TXSTTMO [7..7] =========================================== */ 124 typedef enum { /*!< MEC_PS2CTL_STATUS_TXSTTMO */ 125 MEC_PS2CTL_STATUS_TXSTTMO_ACTIVE = 1, /*!< ACTIVE : Active */ 126 } MEC_PS2CTL_STATUS_TXSTTMO_Enum; 127 128 /** @} */ /* End of group EnumValue_peripherals */ 129 130 #endif /* _MEC5_PS2_V1_H */ 131
