1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_CTMR_V1_H 7 #define _MEC5_CTMR_V1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief 16-bit Event Counter/Timer (MEC_CTMR0) 15 */ 16 17 typedef struct mec_ctmr_regs { /*!< (@ 0x40000D00) MEC_CTMR0 Structure */ 18 __IOM uint32_t CTRL; /*!< (@ 0x00000000) 16-bit Event Counter/Timer Control */ 19 __IOM uint32_t CEV_CTRL; /*!< (@ 0x00000004) 16-bit Event Counter/Timer clock and event control */ 20 __IOM uint16_t RELOAD; /*!< (@ 0x00000008) 16-bit Event Counter/Timer reload */ 21 __IM uint16_t RESERVED; 22 __IOM uint16_t COUNT; /*!< (@ 0x0000000C) 16-bit Event Counter/Timer counter(RO) */ 23 __IM uint16_t RESERVED1; 24 } MEC_CTMR_Type; /*!< Size = 16 (0x10) */ 25 26 /** @} */ /* End of group Device_Peripheral_peripherals */ 27 28 /** @addtogroup PosMask_peripherals 29 * @{ 30 */ 31 /* ========================================================= CTRL ========================================================== */ 32 #define MEC_CTMR_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ 33 #define MEC_CTMR_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ 34 #define MEC_CTMR_CTRL_RESET_Pos (1UL) /*!< RESET (Bit 1) */ 35 #define MEC_CTMR_CTRL_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ 36 #define MEC_CTMR_CTRL_MODE_Pos (2UL) /*!< MODE (Bit 2) */ 37 #define MEC_CTMR_CTRL_MODE_Msk (0xcUL) /*!< MODE (Bitfield-Mask: 0x03) */ 38 #define MEC_CTMR_CTRL_INPOL_Pos (4UL) /*!< INPOL (Bit 4) */ 39 #define MEC_CTMR_CTRL_INPOL_Msk (0x10UL) /*!< INPOL (Bitfield-Mask: 0x01) */ 40 #define MEC_CTMR_CTRL_CNT_DIR_Pos (5UL) /*!< CNT_DIR (Bit 5) */ 41 #define MEC_CTMR_CTRL_CNT_DIR_Msk (0x20UL) /*!< CNT_DIR (Bitfield-Mask: 0x01) */ 42 #define MEC_CTMR_CTRL_TOUT_EN_Pos (6UL) /*!< TOUT_EN (Bit 6) */ 43 #define MEC_CTMR_CTRL_TOUT_EN_Msk (0x40UL) /*!< TOUT_EN (Bitfield-Mask: 0x01) */ 44 #define MEC_CTMR_CTRL_RLOAD_Pos (7UL) /*!< RLOAD (Bit 7) */ 45 #define MEC_CTMR_CTRL_RLOAD_Msk (0x80UL) /*!< RLOAD (Bitfield-Mask: 0x01) */ 46 #define MEC_CTMR_CTRL_FILT_BYP_Pos (8UL) /*!< FILT_BYP (Bit 8) */ 47 #define MEC_CTMR_CTRL_FILT_BYP_Msk (0x100UL) /*!< FILT_BYP (Bitfield-Mask: 0x01) */ 48 #define MEC_CTMR_CTRL_PD_Pos (9UL) /*!< PD (Bit 9) */ 49 #define MEC_CTMR_CTRL_PD_Msk (0x200UL) /*!< PD (Bitfield-Mask: 0x01) */ 50 #define MEC_CTMR_CTRL_TOUT_POL_Pos (10UL) /*!< TOUT_POL (Bit 10) */ 51 #define MEC_CTMR_CTRL_TOUT_POL_Msk (0x400UL) /*!< TOUT_POL (Bitfield-Mask: 0x01) */ 52 #define MEC_CTMR_CTRL_SLP_EN_Pos (11UL) /*!< SLP_EN (Bit 11) */ 53 #define MEC_CTMR_CTRL_SLP_EN_Msk (0x800UL) /*!< SLP_EN (Bitfield-Mask: 0x01) */ 54 #define MEC_CTMR_CTRL_CLK_REQ_Pos (12UL) /*!< CLK_REQ (Bit 12) */ 55 #define MEC_CTMR_CTRL_CLK_REQ_Msk (0x1000UL) /*!< CLK_REQ (Bitfield-Mask: 0x01) */ 56 /* ======================================================= CEV_CTRL ======================================================== */ 57 #define MEC_CTMR_CEV_CTRL_TCLK_FREQ_Pos (0UL) /*!< TCLK_FREQ (Bit 0) */ 58 #define MEC_CTMR_CEV_CTRL_TCLK_FREQ_Msk (0xfUL) /*!< TCLK_FREQ (Bitfield-Mask: 0x0f) */ 59 #define MEC_CTMR_CEV_CTRL_EDGE_Pos (5UL) /*!< EDGE (Bit 5) */ 60 #define MEC_CTMR_CEV_CTRL_EDGE_Msk (0x60UL) /*!< EDGE (Bitfield-Mask: 0x03) */ 61 #define MEC_CTMR_CEV_CTRL_EVENT_SRC_Pos (7UL) /*!< EVENT_SRC (Bit 7) */ 62 #define MEC_CTMR_CEV_CTRL_EVENT_SRC_Msk (0x80UL) /*!< EVENT_SRC (Bitfield-Mask: 0x01) */ 63 #define MEC_CTMR_CEV_CTRL_FCLK_FREQ_Pos (8UL) /*!< FCLK_FREQ (Bit 8) */ 64 #define MEC_CTMR_CEV_CTRL_FCLK_FREQ_Msk (0xf00UL) /*!< FCLK_FREQ (Bitfield-Mask: 0x0f) */ 65 /** @} */ /* End of group PosMask_peripherals */ 66 67 /** @addtogroup EnumValue_peripherals 68 * @{ 69 */ 70 /* ========================================================= CTRL ========================================================== */ 71 /* ============================================= MEC_CTMR CTRL ENABLE [0..0] ============================================== */ 72 typedef enum { /*!< MEC_CTMR_CTRL_ENABLE */ 73 MEC_CTMR_CTRL_ENABLE_OFF = 0, /*!< OFF : Timer block is off and clocks are gated */ 74 MEC_CTMR_CTRL_ENABLE_ON = 1, /*!< ON : Timer block is off and clocks are ungated */ 75 } MEC_CTMR_CTRL_ENABLE_Enum; 76 77 /* ============================================== MEC_CTMR CTRL RESET [1..1] ============================================== */ 78 typedef enum { /*!< MEC_CTMR_CTRL_RESET */ 79 MEC_CTMR_CTRL_RESET_OFF = 0, /*!< OFF : Self-reset not active */ 80 MEC_CTMR_CTRL_RESET_ON = 1, /*!< ON : Enable timer self-reset */ 81 } MEC_CTMR_CTRL_RESET_Enum; 82 83 /* ============================================== MEC_CTMR CTRL MODE [2..3] =============================================== */ 84 typedef enum { /*!< MEC_CTMR_CTRL_MODE */ 85 MEC_CTMR_CTRL_MODE_TIMER = 0, /*!< TIMER : Timer mode selected */ 86 MEC_CTMR_CTRL_MODE_EVENT = 1, /*!< EVENT : Event mode selected */ 87 MEC_CTMR_CTRL_MODE_ONE_SHOT = 2, /*!< ONE_SHOT : One shot mode selected */ 88 MEC_CTMR_CTRL_MODE_MEAS = 3, /*!< MEAS : Measurement mode selected */ 89 } MEC_CTMR_CTRL_MODE_Enum; 90 91 /* ============================================== MEC_CTMR CTRL INPOL [4..4] ============================================== */ 92 typedef enum { /*!< MEC_CTMR_CTRL_INPOL */ 93 MEC_CTMR_CTRL_INPOL_INVERTED = 1, /*!< INVERTED : TIN input signa polarity is inverted */ 94 } MEC_CTMR_CTRL_INPOL_Enum; 95 96 /* ============================================= MEC_CTMR CTRL CNT_DIR [5..5] ============================================= */ 97 typedef enum { /*!< MEC_CTMR_CTRL_CNT_DIR */ 98 MEC_CTMR_CTRL_CNT_DIR_UP = 1, /*!< UP : Event mode(Count up). Timer mode(pause when TIN de-asserted) */ 99 } MEC_CTMR_CTRL_CNT_DIR_Enum; 100 101 /* ============================================= MEC_CTMR CTRL TOUT_EN [6..6] ============================================= */ 102 typedef enum { /*!< MEC_CTMR_CTRL_TOUT_EN */ 103 MEC_CTMR_CTRL_TOUT_EN_ON = 1, /*!< ON : TOU pin function enabled */ 104 } MEC_CTMR_CTRL_TOUT_EN_Enum; 105 106 /* ============================================== MEC_CTMR CTRL RLOAD [7..7] ============================================== */ 107 typedef enum { /*!< MEC_CTMR_CTRL_RLOAD */ 108 MEC_CTMR_CTRL_RLOAD_EN = 1, /*!< EN : Reload timer from preload register on over/under flow */ 109 } MEC_CTMR_CTRL_RLOAD_Enum; 110 111 /* ============================================ MEC_CTMR CTRL FILT_BYP [8..8] ============================================= */ 112 typedef enum { /*!< MEC_CTMR_CTRL_FILT_BYP */ 113 MEC_CTMR_CTRL_FILT_BYP_EN = 1, /*!< EN : Bypass TIN input filter */ 114 } MEC_CTMR_CTRL_FILT_BYP_Enum; 115 116 /* =============================================== MEC_CTMR CTRL PD [9..9] ================================================ */ 117 typedef enum { /*!< MEC_CTMR_CTRL_PD */ 118 MEC_CTMR_CTRL_PD_EN = 1, /*!< EN : Power down (clock gate) timer */ 119 } MEC_CTMR_CTRL_PD_Enum; 120 121 /* =========================================== MEC_CTMR CTRL TOUT_POL [10..10] ============================================ */ 122 typedef enum { /*!< MEC_CTMR_CTRL_TOUT_POL */ 123 MEC_CTMR_CTRL_TOUT_POL_INVERT = 1, /*!< INVERT : Invert TOUT signal(active low) */ 124 } MEC_CTMR_CTRL_TOUT_POL_Enum; 125 126 /* ============================================ MEC_CTMR CTRL SLP_EN [11..11] ============================================= */ 127 typedef enum { /*!< MEC_CTMR_CTRL_SLP_EN */ 128 MEC_CTMR_CTRL_SLP_EN_ACTIVE = 1, /*!< ACTIVE : Read-only state of Timer's PCR Sleep Enable bit */ 129 } MEC_CTMR_CTRL_SLP_EN_Enum; 130 131 /* ============================================ MEC_CTMR CTRL CLK_REQ [12..12] ============================================ */ 132 typedef enum { /*!< MEC_CTMR_CTRL_CLK_REQ */ 133 MEC_CTMR_CTRL_CLK_REQ_ACTIVE = 1, /*!< ACTIVE : Read-only state of Timer's PCR Clock Required bit */ 134 } MEC_CTMR_CTRL_CLK_REQ_Enum; 135 136 /* ======================================================= CEV_CTRL ======================================================== */ 137 /* ========================================== MEC_CTMR CEV_CTRL TCLK_FREQ [0..3] ========================================== */ 138 typedef enum { /*!< MEC_CTMR_CEV_CTRL_TCLK_FREQ */ 139 MEC_CTMR_CEV_CTRL_TCLK_FREQ_48M = 0, /*!< 48M : Select 48MHz timer clock */ 140 MEC_CTMR_CEV_CTRL_TCLK_FREQ_24M = 1, /*!< 24M : Select 24MHz timer clock */ 141 MEC_CTMR_CEV_CTRL_TCLK_FREQ_12M = 2, /*!< 12M : Select 12MHz timer clock */ 142 MEC_CTMR_CEV_CTRL_TCLK_FREQ_6M = 3, /*!< 6M : Select 6MHz timer clock */ 143 MEC_CTMR_CEV_CTRL_TCLK_FREQ_3M = 4, /*!< 3M : Select 3MHz timer clock */ 144 MEC_CTMR_CEV_CTRL_TCLK_FREQ_1500K = 5, /*!< 1500K : Select 1500KHz timer clock */ 145 MEC_CTMR_CEV_CTRL_TCLK_FREQ_750K = 6, /*!< 750K : Select 750KHz timer clock */ 146 MEC_CTMR_CEV_CTRL_TCLK_FREQ_375K = 7, /*!< 375K : Select 375KHz timer clock */ 147 } MEC_CTMR_CEV_CTRL_TCLK_FREQ_Enum; 148 149 /* ============================================ MEC_CTMR CEV_CTRL EDGE [5..6] ============================================= */ 150 typedef enum { /*!< MEC_CTMR_CEV_CTRL_EDGE */ 151 MEC_CTMR_CEV_CTRL_EDGE_FALLING = 0, /*!< FALLING : Falling edge trigger */ 152 MEC_CTMR_CEV_CTRL_EDGE_RISING = 1, /*!< RISING : Rising edge trigger */ 153 MEC_CTMR_CEV_CTRL_EDGE_BOTH = 2, /*!< BOTH : Trigger on both edges */ 154 MEC_CTMR_CEV_CTRL_EDGE_ONE_SHOT_EN = 3, /*!< ONE_SHOT_EN : Only for One shot mode: trigger when timer enable 155 set */ 156 } MEC_CTMR_CEV_CTRL_EDGE_Enum; 157 158 /* ========================================== MEC_CTMR CEV_CTRL EVENT_SRC [7..7] ========================================== */ 159 typedef enum { /*!< MEC_CTMR_CEV_CTRL_EVENT_SRC */ 160 MEC_CTMR_CEV_CTRL_EVENT_SRC_OVERFLOW = 0, /*!< OVERFLOW : Event mode count source is overflow */ 161 MEC_CTMR_CEV_CTRL_EVENT_SRC_TIN = 1, /*!< TIN : Event mode count source in TIN pin */ 162 } MEC_CTMR_CEV_CTRL_EVENT_SRC_Enum; 163 164 /* ========================================= MEC_CTMR CEV_CTRL FCLK_FREQ [8..11] ========================================== */ 165 typedef enum { /*!< MEC_CTMR_CEV_CTRL_FCLK_FREQ */ 166 MEC_CTMR_CEV_CTRL_FCLK_FREQ_48M = 0, /*!< 48M : Select 48MHz timer clock */ 167 MEC_CTMR_CEV_CTRL_FCLK_FREQ_24M = 1, /*!< 24M : Select 24MHz timer clock */ 168 MEC_CTMR_CEV_CTRL_FCLK_FREQ_12M = 2, /*!< 12M : Select 12MHz timer clock */ 169 MEC_CTMR_CEV_CTRL_FCLK_FREQ_6M = 3, /*!< 6M : Select 6MHz timer clock */ 170 MEC_CTMR_CEV_CTRL_FCLK_FREQ_3M = 4, /*!< 3M : Select 3MHz timer clock */ 171 MEC_CTMR_CEV_CTRL_FCLK_FREQ_1500K = 5, /*!< 1500K : Select 1500KHz timer clock */ 172 MEC_CTMR_CEV_CTRL_FCLK_FREQ_750K = 6, /*!< 750K : Select 750KHz timer clock */ 173 MEC_CTMR_CEV_CTRL_FCLK_FREQ_375K = 7, /*!< 375K : Select 375KHz timer clock */ 174 } MEC_CTMR_CEV_CTRL_FCLK_FREQ_Enum; 175 176 /** @} */ /* End of group EnumValue_peripherals */ 177 178 #endif /* _MEC5_CTMR_V1_H */ 179
