1 /***************************************************************************//**
2 * \file cy_syspm_v4.c
3 * \version 5.150
4 *
5 * This driver provides the source code for API power management.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27 #include "cy_sysclk.h"
28
29 #if defined (CY_IP_MXS22SRSS)
30
31 #include "cy_syspm.h"
32
33 #include "cy_syspm_ppu.h"
34
35 #include "cy_rram.h"
36 #include "cy_ipc_sema.h"
37
38 #include "cy_secure_services.h"
39
40 /*******************************************************************************
41 * Internal Functions
42 *******************************************************************************/
43
44
45 /*******************************************************************************
46 * Internal Defines
47 *******************************************************************************/
48
49 /* The define for number of callback roots */
50 #define CALLBACK_ROOT_NR (8U)
51
52 /* The mask to unlock the Hibernate power mode */
53 #define HIBERNATE_UNLOCK_VAL ((uint32_t) 0x3Au << SRSS_PWR_HIBERNATE_UNLOCK_Pos)
54
55 /* The mask to set the Hibernate power mode */
56 #define SET_HIBERNATE_MODE ((HIBERNATE_UNLOCK_VAL |\
57 SRSS_PWR_HIBERNATE_FREEZE_Msk |\
58 SRSS_PWR_HIBERNATE_HIBERNATE_Msk))
59
60 /* The mask to retain the Hibernate power mode status */
61 #define HIBERNATE_RETAIN_STATUS_MASK ((SRSS_PWR_HIBERNATE_TOKEN_Msk |\
62 SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\
63 SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\
64 SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\
65 SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk))
66
67 /** The mask for the Hibernate wakeup sources */
68 #define HIBERNATE_WAKEUP_MASK ((SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_SRC_Msk |\
69 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_CSV_BAK_Msk |\
70 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_RTC_Msk |\
71 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_WDT_Msk))
72
73 /** The define to update the token to indicate the transition into Hibernate */
74 #define HIBERNATE_TOKEN ((uint32_t) 0x1BU << SRSS_PWR_HIBERNATE_TOKEN_Pos)
75
76 /* The wait time for transition into the minimum regulator current mode
77 */
78 #define SET_MIN_CURRENT_MODE_DELAY_US (1U)
79
80 /* The wait delay time that occurs before the active reference is settled.
81 * Intermediate delay is used in transition into the normal regulator current
82 * mode, it should be two IHO cycles, which is (2 x 1/50000000)
83 * = 1 micro second(Approximated)
84 */
85 #define ACT_REF_SETTLE_DELAY_US (1U)
86
87 /* The wait delay time that occurs after the active reference is settled.
88 * Final delay is used in transition into the normal regulator current mode
89 */
90 #define SET_NORMAL_CURRENT_MODE_DELAY_US (1U)
91
92 /* The internal define of the tries number in the
93 * Cy_SysPm_SystemSetMinRegulatorCurrent() function
94 */
95 #define WAIT_DELAY_TRIES (100U)
96
97 /* The internal define of the tries number in the
98 * Cy_SysPm_SystemSetMinRegulatorCurrent() function
99 */
100 #define CY_SYSPM_CBUCK_BUSY_RETRY_COUNT (100U)
101 #define CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS (1U)
102
103 /* SRAM TRIM Values
104 */
105 #define RAM_TRIM_VAL_A 0x0000000AU
106 #define RAM_TRIM_VAL_B 0x0000000BU
107 #define RAM_TRIM_VAL_C 0x0000000CU
108 #define RAM_TRIM_VAL_F 0x0000000FU
109 #define RAM_TRIM_VAL_1B 0x0000001BU
110 #define RAM_TRIM_VAL_2D 0x0000002DU
111 #define RAM_TRIM_VAL_3F 0x0000003FU
112 #define RAM_TRIM_VAL_202 0x00000202U
113 #define RAM_TRIM_VAL_203 0x00000203U
114 #define RAM_TRIM_VAL_204 0x00000204U
115 #define RAM_TRIM_VAL_206 0x00000206U
116 #define RAM_TRIM_VAL_207 0x00000207U
117 #define RAM_TRIM_VAL_20A 0x0000020AU
118 #define RAM_TRIM_VAL_20B 0x0000020BU
119 #define RAM_TRIM_VAL_20C 0x0000020CU
120 #define RAM_TRIM_VAL_20F 0x0000020FU
121 #define RAM_TRIM_VAL_21A 0x0000021AU
122 #define RAM_TRIM_VAL_21B 0x0000021BU
123 #define RAM_TRIM_VAL_21F 0x0000021FU
124 #define RAM_TRIM_VAL_22D 0x0000022DU
125 #define RAM_TRIM_VAL_23D 0x0000023DU
126 #define RAM_TRIM_VAL_23F 0x0000023FU
127 #define RAM_TRIM_VAL_342 0x00000342U
128 #define RAM_TRIM_VAL_343 0x00000343U
129 #define RAM_TRIM_VAL_603 0x00000603U
130 #define RAM_TRIM_VAL_604 0x00000604U
131 #define RAM_TRIM_VAL_605 0x00000605U
132 #define RAM_TRIM_VAL_606 0x00000606U
133 #define RAM_TRIM_VAL_607 0x00000607U
134 #define RAM_TRIM_VAL_60B 0x0000060BU
135 #define RAM_TRIM_VAL_60C 0x0000060CU
136 #define RAM_TRIM_VAL_60D 0x0000060DU
137 #define RAM_TRIM_VAL_60F 0x0000060FU
138 #define RAM_TRIM_VAL_61B 0x0000061BU
139 #define RAM_TRIM_VAL_61C 0x0000061CU
140 #define RAM_TRIM_VAL_61D 0x0000061DU
141 #define RAM_TRIM_VAL_61F 0x0000061FU
142 #define RAM_TRIM_VAL_62D 0x0000062DU
143 #define RAM_TRIM_VAL_63D 0x0000063DU
144 #define RAM_TRIM_VAL_63F 0x0000063FU
145 #define RAM_TRIM_VAL_743 0x00000743U
146 #define RAM_TRIM_VAL_E1F 0x00000E1FU
147 #define RAM_TRIM_VAL_E3F 0x00000E3FU
148 #define RAM_TRIM_VAL_1E3F 0x00001E3FU
149
150 /* Clock HF macros */
151 #define SYSPM_CLOCK_HF0_INDEX 0U
152 #define SYSPM_CLOCK_HF1_INDEX 1U
153 #define SYSPM_CLOCK_HF10_INDEX 10U
154
155 /*******************************************************************************
156 * Internal Variables
157 *******************************************************************************/
158
159 /* Array of the callback roots */
160 static cy_stc_syspm_callback_t* pmCallbackRoot[CALLBACK_ROOT_NR] = {(void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U};
161
162 /* The array of the pointers to failed callback */
163 static cy_stc_syspm_callback_t* failedCallback[CALLBACK_ROOT_NR] = {(void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U};
164
165
Cy_SysPm_Init(void)166 void Cy_SysPm_Init(void)
167 {
168 if(CY_SYSPM_WARM_BOOT_MODE != Cy_SysPm_GetBootMode())
169 {
170 /* Set Default mode to DEEPSLEEP */
171 (void)Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP);
172 }
173
174 /* Initialize IP Semaphore */
175 CY_ASSERT_L2(CY_IPC_SEMA_SUCCESS == Cy_IPC_Sema_Init(IPC0_SEMA_CH_NUM, 0UL, NULL));
176 }
177
Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor)178 cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor)
179 {
180 uint32_t interruptState;
181 uint32_t cbSleepRootIdx = (uint32_t) CY_SYSPM_SLEEP;
182 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
183
184 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
185
186 /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
187 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
188 {
189 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_READY);
190 }
191
192 /* The CPU can switch into the Sleep power mode only when
193 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
194 * parameter return CY_SYSPM_SUCCESS.
195 */
196 if(retVal == CY_SYSPM_SUCCESS)
197 {
198 /* Call the registered callback functions with
199 * CY_SYSPM_BEFORE_TRANSITION parameter
200 */
201 interruptState = Cy_SysLib_EnterCriticalSection();
202 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
203 {
204 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_BEFORE_TRANSITION);
205 }
206
207 /* The CPU enters the Sleep power mode upon execution of WFI/WFE */
208 SCB_SCR &= (uint32_t) ~SCB_SCR_SLEEPDEEP_Msk;
209
210 if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
211 {
212 __WFI();
213 }
214 else
215 {
216 __WFE();
217 }
218 Cy_SysLib_ExitCriticalSection(interruptState);
219
220 /* Call the registered callback functions with the
221 * CY_SYSPM_AFTER_TRANSITION parameter
222 */
223 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
224 {
225 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_AFTER_TRANSITION);
226 }
227 }
228 else
229 {
230 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
231 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
232 * parameter
233 */
234 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_FAIL);
235 retVal = CY_SYSPM_FAIL;
236 }
237 return retVal;
238 }
239
240
Cy_SysPm_SetSysDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)241 cy_en_syspm_status_t Cy_SysPm_SetSysDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)
242 {
243 cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
244
245 switch(deepSleepMode)
246 {
247 case CY_SYSPM_MODE_DEEPSLEEP:
248 {
249 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE, (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
250 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM0_BASE, (uint32_t)CY_SYSTEM_SRAM0_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
251 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM1_BASE, (uint32_t)CY_SYSTEM_SRAM1_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
252 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SYSCPU_BASE, (uint32_t)CY_SYSTEM_SYSCPU_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
253 #if !defined (CY_PDL_TZ_ENABLED)
254 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_PD1_BASE, (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
255 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPUSS_BASE, (uint32_t)CY_SYSTEM_APPCPUSS_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
256
257 if(cy_pd_ppu_get_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE) == PPU_V1_MODE_ON)
258 {
259 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE, (uint32_t)CY_SYSTEM_SOCMEM_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
260 }
261
262 #endif
263 #if (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
264 SCS_CPPWR &= ~(SCS_CPPWR_SU10_Msk);
265 #endif
266
267 retVal = CY_SYSPM_SUCCESS;
268 }
269 break;
270
271 case CY_SYSPM_MODE_DEEPSLEEP_RAM:
272 {
273 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE, (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
274 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM0_BASE, (uint32_t)CY_SYSTEM_SRAM0_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
275 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM1_BASE, (uint32_t)CY_SYSTEM_SRAM1_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
276 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SYSCPU_BASE, (uint32_t)CY_SYSTEM_SYSCPU_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
277
278 #if !defined (CY_PDL_TZ_ENABLED)
279 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_PD1_BASE, (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
280 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPUSS_BASE, (uint32_t)CY_SYSTEM_APPCPUSS_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
281
282 if(cy_pd_ppu_get_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE) == PPU_V1_MODE_ON)
283 {
284 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE, (uint32_t)CY_SYSTEM_SOCMEM_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
285 }
286
287 #endif
288
289 #if (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
290 SCS_CPPWR |= SCS_CPPWR_SU10_Msk;
291 #endif
292
293
294 #if (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
295 MEM_CTL_MSCR &= ~(MEMSYSCTL_MSCR_ICACTIVE_Msk);
296 MEM_CTL_MSCR &= ~(MEMSYSCTL_MSCR_DCACTIVE_Msk);
297 EWIC_EWCI_ASCR &= ~(EWIC_EWIC_ASCR_ASPU_Msk);
298 #endif
299
300 retVal = CY_SYSPM_SUCCESS;
301 }
302
303 break;
304
305 case CY_SYSPM_MODE_DEEPSLEEP_OFF:
306 {
307 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE, (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
308 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM0_BASE, (uint32_t)CY_SYSTEM_SRAM0_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
309 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM1_BASE, (uint32_t)CY_SYSTEM_SRAM1_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
310 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SYSCPU_BASE, (uint32_t)CY_SYSTEM_SYSCPU_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
311 #if !defined (CY_PDL_TZ_ENABLED)
312 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_PD1_BASE, (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
313 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPUSS_BASE, (uint32_t)CY_SYSTEM_APPCPUSS_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
314
315 if(cy_pd_ppu_get_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE) == PPU_V1_MODE_ON)
316 {
317 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE, (uint32_t)CY_SYSTEM_SOCMEM_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
318 }
319
320 #endif
321
322 #if (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
323 SCS_CPPWR |= SCS_CPPWR_SU10_Msk;
324 #endif
325 #if (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
326 MEM_CTL_MSCR &= ~(MEMSYSCTL_MSCR_ICACTIVE_Msk);
327 MEM_CTL_MSCR &= ~(MEMSYSCTL_MSCR_DCACTIVE_Msk);
328 EWIC_EWCI_ASCR &= ~(EWIC_EWIC_ASCR_ASPU_Msk);
329 #endif
330
331 retVal = CY_SYSPM_SUCCESS;
332 }
333 break;
334
335 default:
336 retVal = CY_SYSPM_BAD_PARAM;
337 break;
338 }
339 return retVal;
340 }
341
Cy_SysPm_GetSysDeepSleepMode(void)342 cy_en_syspm_deep_sleep_mode_t Cy_SysPm_GetSysDeepSleepMode(void)
343 {
344 uint32_t mode;
345 cy_en_syspm_deep_sleep_mode_t deepSleepMode;
346
347 mode = (uint32_t)cy_pd_ppu_get_programmed_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE);
348
349 switch(mode)
350 {
351 case (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_MODE:
352 {
353 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP;
354 }
355 break;
356
357 case (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_RAM_MODE:
358 {
359 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_RAM;
360 }
361 break;
362
363 case (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_OFF_MODE:
364 {
365 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_OFF;
366 }
367 break;
368
369 default:
370 {
371 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_NONE;
372 }
373 break;
374 }
375
376 return deepSleepMode;
377 }
378
Cy_SysPm_SetAppDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)379 cy_en_syspm_status_t Cy_SysPm_SetAppDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)
380 {
381 cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
382
383 switch(deepSleepMode)
384 {
385 case CY_SYSPM_MODE_DEEPSLEEP:
386 {
387 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_PD1_BASE, (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
388 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPU_BASE, (uint32_t)CY_SYSTEM_APPCPU_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
389 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPUSS_BASE, (uint32_t)CY_SYSTEM_APPCPUSS_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
390
391 #if (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
392 SCS_CPPWR &= ~(SCS_CPPWR_SU10_Msk);
393 #endif
394 retVal = CY_SYSPM_SUCCESS;
395 }
396 break;
397
398 case CY_SYSPM_MODE_DEEPSLEEP_RAM:
399 {
400 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_PD1_BASE, (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
401 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPU_BASE, (uint32_t)CY_SYSTEM_APPCPU_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
402 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPUSS_BASE, (uint32_t)CY_SYSTEM_APPCPUSS_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
403
404 #if (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
405 SCS_CPPWR |= SCS_CPPWR_SU10_Msk;
406 #endif
407
408
409 #if (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
410 MEM_CTL_MSCR &= ~(MEMSYSCTL_MSCR_ICACTIVE_Msk);
411 MEM_CTL_MSCR &= ~(MEMSYSCTL_MSCR_DCACTIVE_Msk);
412 EWIC_EWCI_ASCR &= ~(EWIC_EWIC_ASCR_ASPU_Msk);
413 #endif
414
415 retVal = CY_SYSPM_SUCCESS;
416 }
417 break;
418
419 case CY_SYSPM_MODE_DEEPSLEEP_OFF:
420 {
421 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_PD1_BASE, (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
422 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPU_BASE, (uint32_t)CY_SYSTEM_APPCPU_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
423 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPUSS_BASE, (uint32_t)CY_SYSTEM_APPCPUSS_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
424
425 #if (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
426 SCS_CPPWR |= SCS_CPPWR_SU10_Msk;
427 #endif
428 #if (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
429 MEM_CTL_MSCR &= ~(MEMSYSCTL_MSCR_ICACTIVE_Msk);
430 MEM_CTL_MSCR &= ~(MEMSYSCTL_MSCR_DCACTIVE_Msk);
431 EWIC_EWCI_ASCR &= ~(EWIC_EWIC_ASCR_ASPU_Msk);
432 #endif
433
434 retVal = CY_SYSPM_SUCCESS;
435 }
436 break;
437
438 default:
439 retVal = CY_SYSPM_BAD_PARAM;
440 break;
441 }
442 return retVal;
443 }
444
Cy_SysPm_GetAppDeepSleepMode(void)445 cy_en_syspm_deep_sleep_mode_t Cy_SysPm_GetAppDeepSleepMode(void)
446 {
447 uint32_t mode;
448 cy_en_syspm_deep_sleep_mode_t deepSleepMode;
449
450 mode = (uint32_t)cy_pd_ppu_get_programmed_power_mode((struct ppu_v1_reg *)CY_PPU_PD1_BASE);
451
452 switch(mode)
453 {
454 case (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_MODE:
455 {
456 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP;
457 }
458 break;
459
460 case (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_RAM_MODE:
461 {
462 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_RAM;
463 }
464 break;
465
466 case (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_OFF_MODE:
467 {
468 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_OFF;
469 }
470 break;
471
472 default:
473 {
474 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_NONE;
475 }
476 break;
477 }
478
479 return deepSleepMode;
480 }
481
Cy_SysPm_SetDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)482 cy_en_syspm_status_t Cy_SysPm_SetDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)
483 {
484
485 #if defined(NO_RPC_CALL)|| defined (COMPONENT_SECURE_DEVICE)
486 #if (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33)
487 return Cy_SysPm_SetSysDeepSleepMode(deepSleepMode);
488 #elif (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
489 return Cy_SysPm_SetAppDeepSleepMode(deepSleepMode);
490 #else
491 return Cy_SysPm_SetSysDeepSleepMode(deepSleepMode);
492 #endif
493 #else
494 cy_rpc_args_t rpcArgs;
495 rpcArgs.argc = 1;
496 rpcArgs.argv[0] = (uint32_t)deepSleepMode;
497 return (cy_en_syspm_status_t)Cy_Send_RPC(CY_SECURE_SERVICE_TYPE_PM,
498 (uint32_t)CY_SECURE_SERVICE_PM_SET_DS_MODE, &rpcArgs);
499 #endif
500 }
501
Cy_SysPm_SetSOCMEMDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)502 cy_en_syspm_status_t Cy_SysPm_SetSOCMEMDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)
503 {
504 cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
505
506 switch(deepSleepMode)
507 {
508 case CY_SYSPM_MODE_DEEPSLEEP:
509 {
510 if(cy_pd_ppu_get_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE) == PPU_V1_MODE_ON)
511 {
512 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE, (uint32_t)CY_SYSTEM_SOCMEM_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
513 }
514 retVal = CY_SYSPM_SUCCESS;
515 }
516 break;
517
518 case CY_SYSPM_MODE_DEEPSLEEP_RAM:
519 {
520 if(cy_pd_ppu_get_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE) == PPU_V1_MODE_ON)
521 {
522 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE, (uint32_t)CY_SYSTEM_SOCMEM_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
523 }
524 retVal = CY_SYSPM_SUCCESS;
525 }
526 break;
527
528 case CY_SYSPM_MODE_DEEPSLEEP_OFF:
529 {
530 if(cy_pd_ppu_get_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE) == PPU_V1_MODE_ON)
531 {
532 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE, (uint32_t)CY_SYSTEM_SOCMEM_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
533 }
534 retVal = CY_SYSPM_SUCCESS;
535 }
536 break;
537
538 default:
539 retVal = CY_SYSPM_BAD_PARAM;
540 break;
541 }
542 return retVal;
543 }
544
545
Cy_SysPm_GetDeepSleepMode(void)546 cy_en_syspm_deep_sleep_mode_t Cy_SysPm_GetDeepSleepMode(void)
547 {
548 cy_en_syspm_deep_sleep_mode_t deepSleepMode;
549 #if defined(NO_RPC_CALL) || defined (COMPONENT_SECURE_DEVICE)
550
551 uint32_t mode;
552
553 mode = (uint32_t)cy_pd_ppu_get_programmed_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE);
554
555 #if (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
556 mode |= ((uint32_t)cy_pd_ppu_get_programmed_power_mode((struct ppu_v1_reg *)CY_PPU_PD1_BASE) << 8U);
557 #endif
558
559 switch(mode)
560 {
561 case CY_SYSTEM_DEEPSLEEP_PPU_MODES:
562 {
563 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP;
564 }
565 break;
566
567 case CY_SYSTEM_DEEPSLEEP_RAM_PPU_MODES:
568 {
569 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_RAM;
570 }
571 break;
572
573 case CY_SYSTEM_DEEPSLEEP_OFF_PPU_MODES:
574 {
575 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_OFF;
576 }
577 break;
578
579 default:
580 {
581 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_NONE;
582 }
583 break;
584 }
585
586 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_deep_sleep_mode_t enum.');
587 #else
588 cy_rpc_args_t rpcArgs;
589 rpcArgs.argc = 0;
590 deepSleepMode = (cy_en_syspm_deep_sleep_mode_t)Cy_Send_RPC(CY_SECURE_SERVICE_TYPE_PM,
591 (uint32_t)CY_SECURE_SERVICE_PM_GET_DS_MODE, &rpcArgs);
592 #endif
593 return ((cy_en_syspm_deep_sleep_mode_t)deepSleepMode);
594 }
595
Cy_SysPm_GetBootMode(void)596 cy_en_syspm_boot_mode_t Cy_SysPm_GetBootMode(void)
597 {
598 uint32_t resCause, resCause2;
599 cy_en_syspm_boot_mode_t deepSleepWakeMode = CY_SYSPM_POR_BOOT_MODE;
600
601 resCause = SRSS_RES_CAUSE;
602 resCause2 = SRSS_RES_CAUSE2;
603
604 if((resCause == 0UL) || (resCause2 == 0UL))
605 {
606 switch(Cy_SysPm_GetDeepSleepMode())
607 {
608 case CY_SYSPM_MODE_DEEPSLEEP_RAM:
609 {
610 deepSleepWakeMode = CY_SYSPM_WARM_BOOT_MODE;
611 }
612 break;
613
614 case CY_SYSPM_MODE_DEEPSLEEP_OFF:
615 {
616 deepSleepWakeMode = CY_SYSPM_COLD_BOOT_MODE;
617 }
618 break;
619
620 default:
621 {
622 deepSleepWakeMode = CY_SYSPM_POR_BOOT_MODE;
623 }
624 break;
625 }
626
627 }
628
629 return ((cy_en_syspm_boot_mode_t)deepSleepWakeMode);
630 }
631
Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor)632 cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor)
633 {
634 uint32_t interruptState;
635 uint32_t cbDeepSleepRootIdx = (uint32_t) Cy_SysPm_GetDeepSleepMode();
636 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
637
638 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
639 CY_ASSERT_L3(CY_SYSPM_IS_DEEPSLEEP_MODE_VALID(cbDeepSleepRootIdx));
640
641 //Check if LPM is ready
642 if(!Cy_SysPm_IsLpmReady())
643 {
644 retVal = CY_SYSPM_FAIL;
645 }
646 else
647 {
648 /* Call the registered callback functions with the CY_SYSPM_CHECK_READY
649 * parameter
650 */
651 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
652 {
653 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_READY);
654 }
655
656 /* The CPU can switch into the Deep Sleep power mode only when
657 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
658 * parameter return CY_SYSPM_SUCCESS
659 */
660 if (retVal == CY_SYSPM_SUCCESS)
661 {
662 /* Call the registered callback functions with the
663 * CY_SYSPM_BEFORE_TRANSITION parameter
664 */
665 interruptState = Cy_SysLib_EnterCriticalSection();
666 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
667 {
668 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION);
669 }
670
671 /* The CPU enters Deep Sleep mode upon execution of WFI/WFE
672 * use Cy_SysPm_SetDeepSleepMode to set various deepsleep modes */
673 SCB_SCR |= SCB_SCR_SLEEPDEEP_Msk;
674
675 #if defined (CORE_NAME_CM33_0)
676 /* Disable FPU for CM33-NS for DS-RAM/DS-OFF Entry to work*/
677 if(((uint32_t)CY_SYSPM_MODE_DEEPSLEEP_RAM == cbDeepSleepRootIdx) || ((uint32_t)CY_SYSPM_MODE_DEEPSLEEP_OFF == cbDeepSleepRootIdx))
678 {
679 SCB_CPACR &= ~(SCB_NS_CPACR_CP10_CP11_ENABLE);
680 }
681 #endif
682 Cy_SysPm_SetRamTrimsPreDs();
683 if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
684 {
685 __WFI();
686 }
687 else
688 {
689 __WFE();
690 }
691 Cy_SysPm_SetRamTrimsPostDs();
692
693 Cy_SysLib_ExitCriticalSection(interruptState);
694 }
695
696 if (retVal == CY_SYSPM_SUCCESS)
697 {
698 /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION
699 * parameter
700 */
701 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
702 {
703 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_AFTER_TRANSITION);
704 }
705 }
706 else
707 {
708 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
709 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
710 * parameter
711 */
712 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
713 {
714 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_FAIL);
715 }
716 }
717 }
718 return retVal;
719 }
720
Cy_SysPm_SystemEnterHibernate(void)721 cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void)
722 {
723 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
724 uint32_t cbHibernateRootIdx = (uint32_t) CY_SYSPM_HIBERNATE;
725 /* Call the registered callback functions with the
726 * CY_SYSPM_CHECK_READY parameter
727 */
728 if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
729 {
730 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_READY);
731 }
732
733 /* The system can switch into Hibernate power mode only when
734 * all executed registered callback functions with CY_SYSPM_CHECK_READY
735 * parameter return CY_SYSPM_SUCCESS.
736 */
737 if(retVal == CY_SYSPM_SUCCESS)
738 {
739 /* Call registered callback functions with CY_SYSPM_BEFORE_TRANSITION
740 * parameter
741 */
742 (void) Cy_SysLib_EnterCriticalSection();
743 if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
744 {
745 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_BEFORE_TRANSITION);
746 }
747
748 /* Preserve the token that will be retained through a wakeup sequence.
749 * This could be used by Cy_SysLib_GetResetReason() to differentiate
750 * Wakeup from a general reset event.
751 * Preserve the wakeup source(s) configuration.
752 */
753 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE | HIBERNATE_TOKEN);
754
755 /* Clear Previous Wakeup Reasons */
756 Cy_SysPm_ClearHibernateWakeupCause();
757
758 /* Disable overriding by the peripherals the next pin-freeze command */
759 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
760
761 /* The second write causes freezing of I/O cells to save the I/O-cell state */
762 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
763
764 /* Third write cause system to enter Hibernate */
765 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
766
767 /* Read register to make sure it is settled */
768 (void) SRSS_PWR_HIBERNATE;
769
770 /* Wait for transition */
771 __WFI();
772
773 /* The callback function calls with the CY_SYSPM_AFTER_TRANSITION
774 * parameter in the Hibernate power mode are not applicable as system
775 * wake-up was made on system reboot.
776 */
777
778 /* A wakeup from Hibernate is performed by toggling of the wakeup
779 * pins, or WDT matches, or Backup domain alarm expires. This depends on
780 * what item is configured in the Hibernate register. After a wakeup
781 * event, a normal Boot procedure occurs.
782 * There is no need to exit from the critical section.
783 */
784 }
785 else
786 {
787 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
788 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
789 * parameter. The return value should be CY_SYSPM_SUCCESS.
790 */
791 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_FAIL);
792 retVal = CY_SYSPM_FAIL;
793 }
794 return retVal;
795 }
796
Cy_SysPm_SystemSetMinRegulatorCurrent(void)797 cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void)
798 {
799 cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
800
801 /* Check if the power circuits are ready to enter into regulator minimum
802 * current mode
803 */
804 if (Cy_SysPm_IsLpmReady())
805 {
806 SRSS_PWR_CTL2 |= (SRSS_PWR_CTL2_BGREF_LPMODE_Msk |
807 SRSS_PWR_CTL2_PORBOD_LPMODE_Msk);
808
809 /* This wait time allows the circuits to remove their dependence on
810 * the Active mode circuits, such as active Reference
811 */
812 Cy_SysLib_DelayUs(SET_MIN_CURRENT_MODE_DELAY_US);
813
814 /* Disable active reference */
815 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_REFSYS_VBUF_DIS_Msk;
816
817 retVal = CY_SYSPM_SUCCESS;
818 }
819
820 return retVal;
821
822
823 }
824
Cy_SysPm_SystemSetNormalRegulatorCurrent(void)825 cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void)
826 {
827 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
828
829 uint32_t timeOut = WAIT_DELAY_TRIES;
830
831 /* Configure the regulator normal current mode for the POR/BOD circuits
832 * and for the Voltage References
833 */
834
835 /* Bring Regulators Power Circuit out of LPMODE */
836 SRSS_PWR_CTL2 &= (uint32_t)~(SRSS_PWR_CTL2_REFSYS_VBUF_DIS_Msk |
837 SRSS_PWR_CTL2_PORBOD_LPMODE_Msk);
838
839 /* This wait time allows setting active Reference */
840 Cy_SysLib_DelayUs(ACT_REF_SETTLE_DELAY_US);
841
842 while ((0U == _FLD2VAL(SRSS_PWR_CTL2_REFSYS_VREF_OK, SRSS_PWR_CTL2)) && (0U != timeOut))
843 {
844 timeOut--;
845 }
846
847 if (0U != timeOut)
848 {
849 /* Disable the low-power for Bandgap reference circuit */
850 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_BGREF_LPMODE_Msk;
851
852 /* Delay to finally set the normal current mode */
853 Cy_SysLib_DelayUs(SET_NORMAL_CURRENT_MODE_DELAY_US);
854
855 retVal= CY_SYSPM_SUCCESS;
856 }
857
858 return retVal;
859
860 }
861
862
Cy_SysPm_SystemIsMinRegulatorCurrentSet(void)863 bool Cy_SysPm_SystemIsMinRegulatorCurrentSet(void)
864 {
865 return ((0U == _FLD2VAL(SRSS_PWR_CTL2_REFSYS_VBUF_DIS, SRSS_PWR_CTL2)) ? false : true);
866 }
867
868
Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode)869 cy_en_syspm_status_t Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode)
870 {
871 CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode));
872
873 cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
874
875 switch (mode)
876 {
877 case CY_SYSPM_LDO_MODE_NORMAL:
878 {
879 retVal = Cy_SysPm_SystemSetNormalRegulatorCurrent();
880 }
881 break;
882
883 case CY_SYSPM_LDO_MODE_MIN:
884 {
885 retVal = Cy_SysPm_SystemSetMinRegulatorCurrent();
886 }
887 break;
888
889 default:
890 retVal = CY_SYSPM_FAIL;
891 break;
892 }
893
894 return retVal;
895 }
896
Cy_SysPm_LdoGetMode(void)897 cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void)
898 {
899 cy_en_syspm_ldo_mode_t retVal;
900
901 if (Cy_SysPm_SystemIsMinRegulatorCurrentSet())
902 {
903 retVal = CY_SYSPM_LDO_MODE_MIN;
904 }
905 else
906 {
907 retVal = CY_SYSPM_LDO_MODE_NORMAL;
908 }
909
910 return retVal;
911 }
912
Cy_SysPm_CpuSleepOnExit(bool enable)913 void Cy_SysPm_CpuSleepOnExit(bool enable)
914 {
915 if(enable)
916 {
917 /* Enable sleep-on-exit feature */
918 SCB_SCR |= SCB_SCR_SLEEPONEXIT_Msk;
919 }
920 else
921 {
922 /* Disable sleep-on-exit feature */
923 SCB_SCR &= (uint32_t) ~(SCB_SCR_SLEEPONEXIT_Msk);
924 }
925 }
926
Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)927 void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)
928 {
929 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
930
931 uint32_t polarityMask = 0U;
932 uint32_t wakeSrcMask = 0U;
933
934 /* LPCOMP0 & LPCOMP1 */
935 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH)))
936 {
937 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK;
938 }
939
940 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH)))
941 {
942 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK;
943 }
944
945 /* PIN0 & PIN1 */
946 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH)))
947 {
948 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN0_MASK;
949 }
950
951 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH)))
952 {
953 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN1_MASK;
954 }
955
956 /* RTC */
957 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM))
958 {
959 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_RTC_MASK;
960 }
961
962 /* WDT */
963 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_WDT))
964 {
965 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_WDT_MASK;
966 }
967
968 /* Polarity Mask */
969 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH))
970 {
971 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
972 }
973
974 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH))
975 {
976 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
977 }
978
979 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH))
980 {
981 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
982 }
983
984 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH))
985 {
986 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
987 }
988
989 SRSS_PWR_HIB_WAKE_CTL = (SRSS_PWR_HIB_WAKE_CTL | wakeSrcMask);
990 SRSS_PWR_HIB_WAKE_CTL2 = (SRSS_PWR_HIB_WAKE_CTL2 | polarityMask);
991
992 /* Read registers to make sure it is settled */
993 (void) SRSS_PWR_HIB_WAKE_CTL;
994 (void) SRSS_PWR_HIB_WAKE_CTL2;
995
996 }
997
Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)998 void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)
999 {
1000 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
1001
1002 uint32_t polarityMask = 0U;
1003 uint32_t wakeSrcMask = 0U;
1004
1005 /* LPCOMP0 & LPCOMP1 */
1006 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH)))
1007 {
1008 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK;
1009 }
1010
1011 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH)))
1012 {
1013 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK;
1014 }
1015
1016 /* PIN0 & PIN1 */
1017 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH)))
1018 {
1019 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN0_MASK;
1020 }
1021
1022 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH)))
1023 {
1024 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN1_MASK;
1025 }
1026
1027 /* RTC */
1028 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM))
1029 {
1030 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_RTC_MASK;
1031 }
1032
1033 /* WDT */
1034 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_WDT))
1035 {
1036 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_WDT_MASK;
1037 }
1038
1039 /* Polarity Mask */
1040 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH))
1041 {
1042 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
1043 }
1044
1045 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH))
1046 {
1047 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
1048 }
1049
1050 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH))
1051 {
1052 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
1053 }
1054
1055 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH))
1056 {
1057 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
1058 }
1059
1060 SRSS_PWR_HIB_WAKE_CTL = (SRSS_PWR_HIB_WAKE_CTL & (~wakeSrcMask));
1061 SRSS_PWR_HIB_WAKE_CTL2 = (SRSS_PWR_HIB_WAKE_CTL2 & (~polarityMask));
1062
1063 /* Read registers to make sure it is settled */
1064 (void) SRSS_PWR_HIB_WAKE_CTL;
1065 (void) SRSS_PWR_HIB_WAKE_CTL2;
1066 }
1067
Cy_SysPm_GetHibernateWakeupCause(void)1068 cy_en_syspm_hibernate_wakeup_source_t Cy_SysPm_GetHibernateWakeupCause(void)
1069 {
1070 uint32_t wakeupCause;
1071 uint32_t wakeupCausePolarity;
1072
1073 wakeupCause = SRSS_PWR_HIB_WAKE_CAUSE;
1074
1075 wakeupCausePolarity = (wakeupCause & (uint32_t)(CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK |
1076 CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK |
1077 CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK |
1078 CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK ));
1079
1080 switch(wakeupCause)
1081 {
1082 case CY_SYSPM_HIB_WAKEUP_PIN0_POS:
1083 {
1084 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK))
1085 {
1086 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH);
1087 }
1088 else
1089 {
1090 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW);
1091 }
1092 }
1093 break;
1094
1095 case CY_SYSPM_HIB_WAKEUP_PIN1_POS:
1096 {
1097 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK))
1098 {
1099 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH);
1100 }
1101 else
1102 {
1103 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW);
1104 }
1105 }
1106 break;
1107
1108 case CY_SYSPM_HIB_WAKEUP_LPCOMP0_POS:
1109 {
1110 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK))
1111 {
1112 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH);
1113 }
1114 else
1115 {
1116 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_LOW);
1117 }
1118 }
1119 break;
1120
1121 case CY_SYSPM_HIB_WAKEUP_LPCOMP1_POS:
1122 {
1123 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK))
1124 {
1125 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH);
1126 }
1127 else
1128 {
1129 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_LOW);
1130 }
1131 }
1132 break;
1133
1134 case CY_SYSPM_HIB_WAKEUP_RTC_MASK:
1135 {
1136 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM);
1137 }
1138 break;
1139
1140 case CY_SYSPM_HIB_WAKEUP_WDT_MASK:
1141 {
1142 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_WDT);
1143 }
1144 break;
1145
1146 default:
1147 CY_ASSERT_L2(false);
1148 break;
1149 }
1150
1151 return (cy_en_syspm_hibernate_wakeup_source_t)wakeupCause;
1152 }
1153
Cy_SysPm_ClearHibernateWakeupCause(void)1154 void Cy_SysPm_ClearHibernateWakeupCause(void)
1155 {
1156 uint32_t temp = SRSS_PWR_HIB_WAKE_CAUSE;
1157 SRSS_PWR_HIB_WAKE_CAUSE = temp;
1158 }
1159
Cy_SysPm_CoreBuckSetVoltage(cy_en_syspm_core_buck_voltage_t voltage)1160 cy_en_syspm_status_t Cy_SysPm_CoreBuckSetVoltage(cy_en_syspm_core_buck_voltage_t voltage)
1161 {
1162 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(voltage));
1163
1164 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL, SRSS_PWR_CBUCK_CTL_CBUCK_VSEL, voltage);
1165
1166 return Cy_SysPm_CoreBuckStatus();
1167 }
1168
Cy_SysPm_CoreBuckGetVoltage(void)1169 cy_en_syspm_core_buck_voltage_t Cy_SysPm_CoreBuckGetVoltage(void)
1170 {
1171 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_voltage_t enum.');
1172 return (cy_en_syspm_core_buck_voltage_t)(_FLD2VAL(SRSS_PWR_CBUCK_CTL_CBUCK_VSEL, SRSS_PWR_CBUCK_CTL));
1173 }
1174
Cy_SysPm_CoreBuckSetMode(cy_en_syspm_core_buck_mode_t mode)1175 void Cy_SysPm_CoreBuckSetMode(cy_en_syspm_core_buck_mode_t mode)
1176 {
1177 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(mode));
1178
1179 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL, SRSS_PWR_CBUCK_CTL_CBUCK_MODE, mode);
1180 }
1181
Cy_SysPm_CoreBuckGetMode(void)1182 cy_en_syspm_core_buck_mode_t Cy_SysPm_CoreBuckGetMode(void)
1183 {
1184 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_mode_t enum.');
1185 return (cy_en_syspm_core_buck_mode_t)(_FLD2VAL(SRSS_PWR_CBUCK_CTL_CBUCK_MODE, SRSS_PWR_CBUCK_CTL));
1186 }
1187
Cy_SysPm_CoreBuckDpslpSetVoltage(cy_en_syspm_core_buck_voltage_t voltage)1188 cy_en_syspm_status_t Cy_SysPm_CoreBuckDpslpSetVoltage(cy_en_syspm_core_buck_voltage_t voltage)
1189 {
1190 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(voltage));
1191
1192 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_DPSLP_CTL, SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_VSEL, voltage);
1193
1194 return Cy_SysPm_CoreBuckStatus();
1195 }
1196
Cy_SysPm_CoreBuckDpslpGetVoltage(void)1197 cy_en_syspm_core_buck_voltage_t Cy_SysPm_CoreBuckDpslpGetVoltage(void)
1198 {
1199 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_voltage_t enum.');
1200 return (cy_en_syspm_core_buck_voltage_t)(_FLD2VAL(SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_VSEL, SRSS_PWR_CBUCK_DPSLP_CTL));
1201 }
1202
Cy_SysPm_CoreBuckDpslpSetMode(cy_en_syspm_core_buck_mode_t mode)1203 void Cy_SysPm_CoreBuckDpslpSetMode(cy_en_syspm_core_buck_mode_t mode)
1204 {
1205 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(mode));
1206
1207 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_DPSLP_CTL, SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_MODE, mode);
1208 }
1209
Cy_SysPm_CoreBuckDpslpGetMode(void)1210 cy_en_syspm_core_buck_mode_t Cy_SysPm_CoreBuckDpslpGetMode(void)
1211 {
1212 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_mode_t enum.');
1213 return (cy_en_syspm_core_buck_mode_t)(_FLD2VAL(SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_MODE, SRSS_PWR_CBUCK_DPSLP_CTL));
1214 }
1215
Cy_SysPm_CoreBuckDpslpEnableOverride(bool enable)1216 void Cy_SysPm_CoreBuckDpslpEnableOverride(bool enable)
1217 {
1218 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_DPSLP_CTL, SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_OVERRIDE, ((enable) ? 1UL : 0UL));
1219 }
1220
Cy_SysPm_CoreBuckDpslpIsOverrideEnabled(void)1221 bool Cy_SysPm_CoreBuckDpslpIsOverrideEnabled(void)
1222 {
1223 return (_FLD2BOOL(SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_OVERRIDE, SRSS_PWR_CBUCK_DPSLP_CTL)? true : false);
1224 }
1225
1226
Cy_SysPm_CoreBuckSetProfile(cy_en_syspm_core_buck_profile_t profile)1227 void Cy_SysPm_CoreBuckSetProfile(cy_en_syspm_core_buck_profile_t profile)
1228 {
1229 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_PROFILE_VALID(profile));
1230
1231 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL2, SRSS_PWR_CBUCK_CTL2_CBUCK_PROFILE, profile);
1232 }
1233
Cy_SysPm_CoreBuckGetProfile(void)1234 cy_en_syspm_core_buck_profile_t Cy_SysPm_CoreBuckGetProfile(void)
1235 {
1236 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_profile_t enum.');
1237 return (cy_en_syspm_core_buck_profile_t)(_FLD2VAL(SRSS_PWR_CBUCK_CTL2_CBUCK_PROFILE, SRSS_PWR_CBUCK_CTL2));
1238 }
1239
Cy_SysPm_CoreBuckStatus(void)1240 cy_en_syspm_status_t Cy_SysPm_CoreBuckStatus(void)
1241 {
1242 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
1243 uint32_t syspmCbuckRetry = CY_SYSPM_CBUCK_BUSY_RETRY_COUNT;
1244
1245 while((_FLD2VAL(SRSS_PWR_CBUCK_STATUS_PMU_DONE, SRSS_PWR_CBUCK_STATUS) == 0U) && (syspmCbuckRetry != 0U))
1246 {
1247 syspmCbuckRetry--;
1248 Cy_SysLib_Delay(CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS);
1249 }
1250
1251 if(syspmCbuckRetry != 0UL)
1252 {
1253 retVal = CY_SYSPM_SUCCESS;
1254 }
1255
1256 return retVal;
1257 }
1258
Cy_SysPm_RetLdoStatus(void)1259 cy_en_syspm_status_t Cy_SysPm_RetLdoStatus(void)
1260 {
1261 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
1262 uint32_t syspmCbuckRetry = CY_SYSPM_CBUCK_BUSY_RETRY_COUNT;
1263
1264 while((_FLD2VAL(SRSS_PWR_CBUCK_STATUS_RETLDO_DONE, SRSS_PWR_CBUCK_STATUS) == 0U) && (syspmCbuckRetry != 0U))
1265 {
1266 syspmCbuckRetry--;
1267 Cy_SysLib_Delay(CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS);
1268 }
1269
1270 if(syspmCbuckRetry != 0UL)
1271 {
1272 retVal = CY_SYSPM_SUCCESS;
1273 }
1274
1275 return retVal;
1276 }
1277
Cy_SysPm_RetLdoConfigure(cy_stc_syspm_retldo_params_t * retLdoParam)1278 cy_en_syspm_status_t Cy_SysPm_RetLdoConfigure(cy_stc_syspm_retldo_params_t *retLdoParam)
1279 {
1280 CY_ASSERT_L2(CY_SYSPM_IS_RETLDO_VOLTAGE_VALID(retLdoParam->activeVoltSel));
1281 CY_ASSERT_L2(CY_SYSPM_IS_RETLDO_VOLTAGE_VALID(retLdoParam->deepsleepVoltSel));
1282 CY_ASSERT_L2(CY_SYSPM_IS_RETLDO_GAIN_VALID(retLdoParam->activeGain));
1283 CY_ASSERT_L2(CY_SYSPM_IS_RETLDO_GAIN_VALID(retLdoParam->deepsleepGain));
1284
1285 CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_LVL, retLdoParam->activeVoltSel);
1286 CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_GAIN, retLdoParam->activeGain);
1287
1288 CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_LVL_DPSLP, retLdoParam->deepsleepVoltSel);
1289 CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_GAIN_DPSLP, retLdoParam->deepsleepGain);
1290
1291 return Cy_SysPm_RetLdoStatus();
1292 }
1293
Cy_SysPm_SramLdoStatus(void)1294 cy_en_syspm_status_t Cy_SysPm_SramLdoStatus(void)
1295 {
1296 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
1297 uint32_t syspmCbuckRetry = CY_SYSPM_CBUCK_BUSY_RETRY_COUNT;
1298
1299 while((_FLD2VAL(SRSS_PWR_CBUCK_STATUS_SRAMLDO_DONE, SRSS_PWR_CBUCK_STATUS) == 0U) && (syspmCbuckRetry != 0U))
1300 {
1301 syspmCbuckRetry--;
1302 Cy_SysLib_Delay(CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS);
1303 }
1304
1305 if(syspmCbuckRetry != 0UL)
1306 {
1307 retVal = CY_SYSPM_SUCCESS;
1308 }
1309
1310 return retVal;
1311 }
1312
Cy_SysPm_SramLdoEnable(bool enable)1313 cy_en_syspm_status_t Cy_SysPm_SramLdoEnable(bool enable)
1314 {
1315 CY_REG32_CLR_SET(SRSS_PWR_SRAMLDO_CTL, SRSS_PWR_SRAMLDO_CTL_SRAMLDO_EN, (enable ? 1U : 0U));
1316
1317 return Cy_SysPm_SramLdoStatus();
1318 }
1319
Cy_SysPm_SramLdoSetVoltage(cy_en_syspm_sramldo_voltage_t voltage)1320 void Cy_SysPm_SramLdoSetVoltage(cy_en_syspm_sramldo_voltage_t voltage)
1321 {
1322 CY_ASSERT_L2(CY_SYSPM_IS_SRAMLDO_VOLTAGE_VALID(voltage));
1323
1324 CY_REG32_CLR_SET(SRSS_PWR_SRAMLDO_CTL, SRSS_PWR_SRAMLDO_CTL_SRAMLDO_VOUT, voltage);
1325 }
1326
Cy_SysPm_SramLdoGetVoltage(void)1327 cy_en_syspm_sramldo_voltage_t Cy_SysPm_SramLdoGetVoltage(void)
1328 {
1329 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_sramldo_voltage_t enum.');
1330 return (cy_en_syspm_sramldo_voltage_t)(_FLD2VAL(SRSS_PWR_SRAMLDO_CTL_SRAMLDO_VOUT, SRSS_PWR_SRAMLDO_CTL));
1331 }
1332
Cy_SysPm_SramLdoConfigure(cy_stc_syspm_sramldo_params_t * sramLdoParam)1333 cy_en_syspm_status_t Cy_SysPm_SramLdoConfigure(cy_stc_syspm_sramldo_params_t *sramLdoParam)
1334 {
1335 CY_ASSERT_L2(CY_SYSPM_IS_SRAMLDO_VOLTAGE_VALID(sramLdoParam->sramLdoVoltSel));
1336
1337 CY_REG32_CLR_SET(SRSS_PWR_SRAMLDO_CTL, SRSS_PWR_SRAMLDO_CTL_SRAMLDO_EN, (sramLdoParam->sramLdoEnable ? 1U : 0U));
1338
1339 CY_REG32_CLR_SET(SRSS_PWR_SRAMLDO_CTL, SRSS_PWR_SRAMLDO_CTL_SRAMLDO_DPSLP_EN, (sramLdoParam->deepsleepSramLdoEnable ? 1U : 0U));
1340
1341 CY_REG32_CLR_SET(SRSS_PWR_SRAMLDO_CTL, SRSS_PWR_SRAMLDO_CTL_SRAMLDO_VOUT, sramLdoParam->sramLdoVoltSel);
1342
1343 return Cy_SysPm_SramLdoStatus();
1344 }
1345
Cy_SysPm_MiscLdoStatus(void)1346 cy_en_syspm_status_t Cy_SysPm_MiscLdoStatus(void)
1347 {
1348 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
1349 uint32_t syspmCbuckRetry = CY_SYSPM_CBUCK_BUSY_RETRY_COUNT;
1350
1351 while((_FLD2VAL(SRSS_PWR_CBUCK_STATUS_MISCLDO_DONE, SRSS_PWR_CBUCK_STATUS) == 0U) && (syspmCbuckRetry != 0U))
1352 {
1353 syspmCbuckRetry--;
1354 Cy_SysLib_Delay(CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS);
1355 }
1356
1357 if(syspmCbuckRetry != 0UL)
1358 {
1359 retVal = CY_SYSPM_SUCCESS;
1360 }
1361
1362 return retVal;
1363 }
1364
Cy_SysPm_MiscLdoConfigure(cy_stc_syspm_miscldo_params_t * miscLdoParam)1365 cy_en_syspm_status_t Cy_SysPm_MiscLdoConfigure(cy_stc_syspm_miscldo_params_t *miscLdoParam)
1366 {
1367 CY_ASSERT_L2(CY_SYSPM_IS_MISCLDO_VOLTAGE_VALID(miscLdoParam->miscLdoVoltSel));
1368 CY_ASSERT_L2(CY_SYSPM_IS_MISCLDO_VCCACT_TRIM_VALID(miscLdoParam->miscLdoVaccActTrimSel));
1369 CY_ASSERT_L2(CY_SYSPM_IS_MISCLDO_MODE_VALID(miscLdoParam->miscLdoMode));
1370
1371 CY_REG32_CLR_SET(SRSS_PWR_MISCLDO_CTL, SRSS_PWR_MISCLDO_CTL_MISCLDO_EN, (miscLdoParam->miscLdoEnable ? 1U : 0U));
1372
1373 CY_REG32_CLR_SET(SRSS_PWR_MISCLDO_CTL, SRSS_PWR_MISCLDO_CTL_MISCLDO_MODE, miscLdoParam->miscLdoMode);
1374
1375 CY_REG32_CLR_SET(SRSS_PWR_MISCLDO_CTL, SRSS_PWR_MISCLDO_CTL_MISCLDO_VOUT, miscLdoParam->miscLdoVoltSel);
1376
1377 CY_REG32_CLR_SET(SRSS_PWR_MISCLDO_CTL, SRSS_PWR_MISCLDO_CTL_MISCLDO_VCCACT_TRIM, miscLdoParam->miscLdoVaccActTrimSel);
1378
1379 return Cy_SysPm_MiscLdoStatus();
1380 }
1381
Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t * handler)1382 bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler)
1383 {
1384 bool retVal = false;
1385
1386 /* Verify the input parameters. */
1387 if ((handler != NULL) && (handler->callbackParams != NULL) && (handler->callback != NULL))
1388 {
1389 uint32_t callbackRootIdx = (uint32_t) handler->type;
1390
1391 /* If the callback list is not empty. */
1392 if (pmCallbackRoot[callbackRootIdx] != NULL)
1393 {
1394 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
1395 cy_stc_syspm_callback_t* insertPos = curCallback;
1396
1397 /* Find the callback after which the new callback is to be
1398 * inserted. Ensure the given callback has not been registered.
1399 */
1400 while ((NULL != curCallback->nextItm) && (curCallback != handler))
1401 {
1402 curCallback = curCallback->nextItm;
1403 /* Callbacks with the same order value are stored in the order
1404 * they are registered.
1405 */
1406 if (curCallback->order <= handler->order)
1407 {
1408 insertPos = curCallback;
1409 }
1410 }
1411 /* If the callback has not been registered. */
1412 if (curCallback != handler)
1413 {
1414 /* If the callback is to be inserted at the beginning of the list. */
1415 if ((insertPos->prevItm == NULL) && (handler->order < insertPos->order))
1416 {
1417 handler->nextItm = insertPos;
1418 handler->prevItm = NULL;
1419 handler->nextItm->prevItm = handler;
1420 pmCallbackRoot[callbackRootIdx] = handler;
1421 }
1422 else
1423 {
1424 handler->nextItm = insertPos->nextItm;
1425 handler->prevItm = insertPos;
1426
1427 /* If the callback is not inserted at the end of the list. */
1428 if (handler->nextItm != NULL)
1429 {
1430 handler->nextItm->prevItm = handler;
1431 }
1432 insertPos->nextItm = handler;
1433 }
1434 retVal = true;
1435 }
1436 }
1437 else
1438 {
1439 /* The callback list is empty. */
1440 pmCallbackRoot[callbackRootIdx] = handler;
1441 handler->nextItm = NULL;
1442 handler->prevItm = NULL;
1443 retVal = true;
1444 }
1445 }
1446 return retVal;
1447 }
1448
Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const * handler)1449 bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler)
1450 {
1451 bool retVal = false;
1452
1453 if (handler != NULL)
1454 {
1455 uint32_t callbackRootIdx = (uint32_t) handler->type;
1456 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
1457
1458 /* Search requested callback item in the linked list */
1459 while (curCallback != NULL)
1460 {
1461 /* Requested callback is found */
1462 if (curCallback == handler)
1463 {
1464 retVal = true;
1465 break;
1466 }
1467
1468 /* Go to next callback item in the linked list */
1469 curCallback = curCallback->nextItm;
1470 }
1471
1472 if (retVal)
1473 {
1474 /* Requested callback is first in the list */
1475 if (pmCallbackRoot[callbackRootIdx] == handler)
1476 {
1477 /* Check whether this the only callback registered */
1478 if (pmCallbackRoot[callbackRootIdx]->nextItm != NULL)
1479 {
1480 pmCallbackRoot[callbackRootIdx] = pmCallbackRoot[callbackRootIdx]->nextItm;
1481 pmCallbackRoot[callbackRootIdx]->prevItm = NULL;
1482 }
1483 else
1484 {
1485 /* We had only one callback */
1486 pmCallbackRoot[callbackRootIdx] = NULL;
1487 }
1488 }
1489 else
1490 {
1491 /* Update links of related to unregistered callback items */
1492 curCallback->prevItm->nextItm = curCallback->nextItm;
1493
1494 if (curCallback->nextItm != NULL)
1495 {
1496 curCallback->nextItm->prevItm = curCallback->prevItm;
1497 }
1498 }
1499 }
1500 }
1501
1502 return retVal;
1503 }
1504
Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type,cy_en_syspm_callback_mode_t mode)1505 cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode)
1506 {
1507 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type));
1508 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode));
1509
1510 static cy_stc_syspm_callback_t* lastExecutedCallback = NULL;
1511 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
1512 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[(uint32_t) type];
1513 cy_stc_syspm_callback_params_t curParams;
1514
1515 if ((mode == CY_SYSPM_BEFORE_TRANSITION) || (mode == CY_SYSPM_CHECK_READY))
1516 {
1517 /* Execute registered callbacks with order from first registered to the
1518 * last registered. Stop executing if CY_SYSPM_FAIL was returned in
1519 * CY_SYSPM_CHECK_READY mode
1520 */
1521 while ((curCallback != NULL) && ((retVal != CY_SYSPM_FAIL) || (mode != CY_SYSPM_CHECK_READY)))
1522 {
1523 /* The modes defined in the .skipMode element are not executed */
1524 if (0UL == ((uint32_t) mode & curCallback->skipMode))
1525 {
1526 /* Update elements for local callback parameter values */
1527 curParams.base = curCallback->callbackParams->base;
1528 curParams.context = curCallback->callbackParams->context;
1529
1530 retVal = curCallback->callback(&curParams, mode);
1531
1532 /* Update callback pointer with value of executed callback.
1533 * Such update is required to execute further callbacks in
1534 * backward order after exit from LP mode or to undo
1535 * configuration after callback returned fail: from last called
1536 * to first registered.
1537 */
1538 lastExecutedCallback = curCallback;
1539 }
1540 curCallback = curCallback->nextItm;
1541 }
1542
1543 if (mode == CY_SYSPM_CHECK_READY)
1544 {
1545 /* Update the pointer to the failed callback with the result of the callback execution.
1546 * If the callback fails, the value of the pointer will be updated
1547 * with the address of the callback which returned CY_SYSPM_FAIL, else,
1548 * it will be updated with NULL.
1549 */
1550 if(retVal == CY_SYSPM_FAIL)
1551 {
1552 failedCallback[(uint32_t) type] = lastExecutedCallback;
1553 }
1554 else
1555 {
1556 failedCallback[(uint32_t) type] = NULL;
1557 }
1558 }
1559 }
1560 else
1561 {
1562 /* Execute registered callbacks with order from lastCallback or last
1563 * executed to the first registered callback. Such a flow is required if
1564 * a previous callback function returned CY_SYSPM_FAIL or a previous
1565 * callback mode was CY_SYSPM_BEFORE_TRANSITION. Such an order is
1566 * required to undo configurations in correct backward order.
1567 */
1568 if (mode != CY_SYSPM_CHECK_FAIL)
1569 {
1570 while (curCallback->nextItm != NULL)
1571 {
1572 curCallback = curCallback->nextItm;
1573 }
1574 }
1575 else
1576 {
1577 /* Skip last executed callback that returns CY_SYSPM_FAIL, as this
1578 * callback already knows that it failed.
1579 */
1580 curCallback = lastExecutedCallback;
1581
1582 if (curCallback != NULL)
1583 {
1584 curCallback = curCallback->prevItm;
1585 }
1586 }
1587
1588 /* Execute callback functions with required type and mode */
1589 while (curCallback != NULL)
1590 {
1591 /* The modes defined in the .skipMode element are not executed */
1592 if (0UL == ((uint32_t) mode & curCallback->skipMode))
1593 {
1594 /* Update elements for local callback parameter values */
1595 curParams.base = curCallback->callbackParams->base;
1596 curParams.context = curCallback->callbackParams->context;
1597
1598 retVal = curCallback->callback(&curParams, mode);
1599 }
1600 curCallback = curCallback->prevItm;
1601 }
1602 }
1603
1604 return retVal;
1605 }
1606
Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type)1607 cy_stc_syspm_callback_t* Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type)
1608 {
1609 return failedCallback[(uint32_t) type];
1610 }
1611
Cy_SysPm_IoUnfreeze(void)1612 void Cy_SysPm_IoUnfreeze(void)
1613 {
1614 uint32_t interruptState;
1615 interruptState = Cy_SysLib_EnterCriticalSection();
1616
1617 /* Preserve the last reset reason and wakeup polarity. Then, unfreeze I/O:
1618 * write PWR_HIBERNATE.FREEZE=0, .UNLOCK=0x3A, .HIBERANTE=0
1619 */
1620 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_RETAIN_STATUS_MASK) | HIBERNATE_UNLOCK_VAL;
1621
1622 /* Lock the Hibernate mode:
1623 * write PWR_HIBERNATE.HIBERNATE=0, UNLOCK=0x00, HIBERANTE=0
1624 */
1625 SRSS_PWR_HIBERNATE &= HIBERNATE_RETAIN_STATUS_MASK;
1626
1627 /* Read register to make sure it is settled */
1628 (void) SRSS_PWR_HIBERNATE;
1629
1630 Cy_SysLib_ExitCriticalSection(interruptState);
1631 }
1632
Cy_SysPm_IoIsFrozen(void)1633 bool Cy_SysPm_IoIsFrozen(void)
1634 {
1635 return (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_FREEZE, SRSS_PWR_HIBERNATE));
1636 }
1637
Cy_SysPm_DeepSleepIoUnfreeze(void)1638 void Cy_SysPm_DeepSleepIoUnfreeze(void)
1639 {
1640 uint32_t interruptState;
1641 interruptState = Cy_SysLib_EnterCriticalSection();
1642
1643 /* Unfreeze IO's which are frozen during DEEPSLEEP-RAM/OFF
1644 * Entry
1645 */
1646 /* For PD0 */
1647 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_FREEZE_DPSLP_Msk;
1648
1649 /* For PD1 */
1650 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_FREEZE_DPSLP_PD1_Msk;
1651
1652 Cy_SysLib_ExitCriticalSection(interruptState);
1653 }
1654
Cy_SysPm_DeepSleepIoIsFrozen(void)1655 bool Cy_SysPm_DeepSleepIoIsFrozen(void)
1656 {
1657 return ((0U != _FLD2VAL(SRSS_PWR_CTL2_FREEZE_DPSLP, SRSS_PWR_CTL2)) || (0U != _FLD2VAL(SRSS_PWR_CTL2_FREEZE_DPSLP_PD1, SRSS_PWR_CTL2)));
1658 }
1659
Cy_SysPm_CpuSendWakeupEvent(void)1660 void Cy_SysPm_CpuSendWakeupEvent(void)
1661 {
1662 __SEV();
1663 }
1664
Cy_SysPm_IsLpmReady(void)1665 bool Cy_SysPm_IsLpmReady(void)
1666 {
1667 return (_FLD2BOOL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL)? true : false);
1668 }
1669
Cy_SysPm_SetSOCMemPartActivePwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum,cy_en_syspm_socmem_sram_pwr_mode_t socmemSramPwrMode)1670 cy_en_syspm_status_t Cy_SysPm_SetSOCMemPartActivePwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum, cy_en_syspm_socmem_sram_pwr_mode_t socmemSramPwrMode)
1671 {
1672 CY_ASSERT_L3((socmemSramPwrMode == CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_ON) || (socmemSramPwrMode == CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_OFF));
1673 CY_ASSERT_L3(socmemSramPartNum < CY_SOCMEM_PARTITION_NR);
1674
1675 /* Unlock PWR Partition Control */
1676 /* Clear bit 0(CLR0)*/
1677 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR0;
1678 /* Clear bit 1(CLR1)*/
1679 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR1;
1680
1681 switch(socmemSramPwrMode)
1682 {
1683 case CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_ON:
1684 {
1685 CY_REG32_CLR_SET(SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum), SOCMEM_PWR_PARTITION_CTL_ACT_OFF, 0UL);
1686 }
1687 break;
1688
1689 case CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_OFF:
1690 {
1691 CY_REG32_CLR_SET(SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum), SOCMEM_PWR_PARTITION_CTL_ACT_OFF, 1UL);
1692 }
1693 break;
1694
1695 default:
1696 {
1697 CY_ASSERT_L3(false);
1698 }
1699 break;
1700 }
1701
1702 /* Wait for the PWR_DONE status */
1703 while(!_FLD2BOOL(SOCMEM_PWR_STATUS_PWR_DONE, SOCMEM_PWR_STATUS)){}
1704
1705 /* Lock PWR Partition Control(Set SET01) */
1706 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_SET01;
1707
1708 return CY_SYSPM_SUCCESS;
1709 }
1710
Cy_SysPm_SetSOCMemPartDsPwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum,cy_en_syspm_socmem_sram_pwr_mode_t socmemSramPwrMode)1711 cy_en_syspm_status_t Cy_SysPm_SetSOCMemPartDsPwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum, cy_en_syspm_socmem_sram_pwr_mode_t socmemSramPwrMode)
1712 {
1713 CY_ASSERT_L3((socmemSramPwrMode == CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_ON) || (socmemSramPwrMode == CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_OFF));
1714 CY_ASSERT_L3(socmemSramPartNum < CY_SOCMEM_PARTITION_NR);
1715
1716 /* Unlock PWR Partition Control */
1717 /* Clear bit 0(CLR0)*/
1718 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR0;
1719 /* Clear bit 1(CLR1)*/
1720 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR1;
1721
1722 switch(socmemSramPwrMode)
1723 {
1724 case CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_ON:
1725 {
1726 CY_REG32_CLR_SET(SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum), SOCMEM_PWR_PARTITION_CTL_RET_OFF, 0UL);
1727 }
1728 break;
1729
1730 case CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_OFF:
1731 {
1732 CY_REG32_CLR_SET(SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum), SOCMEM_PWR_PARTITION_CTL_RET_OFF, 1UL);
1733 }
1734 break;
1735
1736 default:
1737 {
1738 CY_ASSERT_L3(false);
1739 }
1740 break;
1741 }
1742
1743 /* Lock PWR Partition Control(Set SET01) */
1744 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_SET01;
1745
1746 return CY_SYSPM_SUCCESS;
1747 }
1748
1749
Cy_SysPm_GetSOCMemSramPartActivePwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum)1750 cy_en_syspm_socmem_sram_pwr_mode_t Cy_SysPm_GetSOCMemSramPartActivePwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum)
1751 {
1752 cy_en_syspm_socmem_sram_pwr_mode_t value;
1753
1754 CY_ASSERT_L3(socmemSramPartNum < CY_SOCMEM_PARTITION_NR);
1755
1756 /* Unlock PWR Partition Control */
1757 /* Clear bit 0(CLR0)*/
1758 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR0;
1759 /* Clear bit 1(CLR1)*/
1760 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR1;
1761
1762
1763 value = (((SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum) & (SOCMEM_PWR_PARTITION_CTL_ACT_OFF_Msk)) != 0UL) ? CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_OFF:CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_ON);
1764
1765 /* Lock PWR Partition Control(Set SET01) */
1766 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_SET01;
1767
1768 return value;
1769 }
1770
Cy_SysPm_GetSOCMemSramPartDsPwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum)1771 cy_en_syspm_socmem_sram_pwr_mode_t Cy_SysPm_GetSOCMemSramPartDsPwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum)
1772 {
1773 cy_en_syspm_socmem_sram_pwr_mode_t value;
1774
1775 CY_ASSERT_L3(socmemSramPartNum < CY_SOCMEM_PARTITION_NR);
1776
1777 /* Unlock PWR Partition Control */
1778 /* Clear bit 0(CLR0)*/
1779 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR0;
1780 /* Clear bit 1(CLR1)*/
1781 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR1;
1782
1783
1784 value = (((SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum) & (SOCMEM_PWR_PARTITION_CTL_RET_OFF_Msk)) != 0UL) ? CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_OFF:CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_ON);
1785
1786 /* Lock PWR Partition Control(Set SET01) */
1787 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_SET01;
1788
1789 return value;
1790 }
1791
1792
1793 /* This API is an inline version of Cy_SysPm_SetSRAMMacroPwrMode */
Cy_SysPm_SetSRAMMacroPwrModeInline(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)1794 __STATIC_FORCEINLINE cy_en_syspm_status_t Cy_SysPm_SetSRAMMacroPwrModeInline(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
1795 {
1796 CY_ASSERT_L3((sramNum == CY_SYSPM_SRAM0_MEMORY) || (sramNum == CY_SYSPM_SRAM1_MEMORY));
1797 CY_ASSERT_L3((sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_ON) || (sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_OFF));
1798 CY_ASSERT_L3(sramMacroNum < CY_CPUSS_RAMC_MACRO_NR(sramNum));
1799
1800 /* Unlock PWR MACRO Control */
1801 /* Clear bit 0(CLR0)*/
1802 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0;
1803 /* Clear bit 1(CLR1)*/
1804 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR1;
1805
1806 if(sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_ON)
1807 {
1808 /* Enable the Macro Number */
1809 MXSRAMC_PWR_MACRO_CTL(sramNum) &= ~(0x1UL << (uint32_t)sramMacroNum);
1810 }
1811 else
1812 {
1813 /* Disable the Macro Number */
1814 MXSRAMC_PWR_MACRO_CTL(sramNum) |= (0x1UL << (uint32_t)sramMacroNum);
1815 }
1816 /* Wait for the PWR_DONE status */
1817 while(!_FLD2BOOL(RAMC_STATUS_PWR_DONE, MXSRAMC_STATUS(sramNum))){}
1818
1819 /* Lock PWR MACRO Control(Set SET01) */
1820 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_SET01;
1821
1822 return CY_SYSPM_SUCCESS;
1823 }
1824
Cy_SysPm_SetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)1825 cy_en_syspm_status_t Cy_SysPm_SetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
1826 {
1827 return Cy_SysPm_SetSRAMMacroPwrModeInline(sramNum, sramMacroNum, sramPwrMode);
1828 }
1829
Cy_SysPm_GetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum)1830 cy_en_syspm_sram_pwr_mode_t Cy_SysPm_GetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum)
1831 {
1832 cy_en_syspm_sram_pwr_mode_t value;
1833
1834 CY_ASSERT_L3((sramNum == CY_SYSPM_SRAM0_MEMORY) || (sramNum == CY_SYSPM_SRAM1_MEMORY));
1835 CY_ASSERT_L3(sramMacroNum < CY_CPUSS_RAMC_MACRO_NR(sramNum));
1836
1837 /* Unlock PWR MACRO Control */
1838 /* Clear bit 0(CLR0)*/
1839 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0;
1840 /* Clear bit 1(CLR1)*/
1841 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR1;
1842
1843 value = (((MXSRAMC_PWR_MACRO_CTL(sramNum) & (0x1UL << (uint32_t)sramMacroNum)) != 0UL) ? CY_SYSPM_SRAM_PWR_MODE_OFF:CY_SYSPM_SRAM_PWR_MODE_ON);
1844
1845 /* Lock PWR MACRO Control(Set SET01) */
1846 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_SET01;
1847
1848 return value;
1849
1850 }
1851
1852
Cy_SysPm_SetSRAMPwrMode(cy_en_syspm_sram_index_t sramNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)1853 cy_en_syspm_status_t Cy_SysPm_SetSRAMPwrMode(cy_en_syspm_sram_index_t sramNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
1854 {
1855 uint8_t macroNum;
1856 CY_ASSERT_L3((sramNum == CY_SYSPM_SRAM0_MEMORY) || (sramNum == CY_SYSPM_SRAM1_MEMORY));
1857 CY_ASSERT_L3((sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_ON) || (sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_OFF));
1858
1859 for(macroNum = 0; (macroNum < CY_CPUSS_RAMC_MACRO_NR(sramNum));macroNum++)
1860 {
1861 (void)Cy_SysPm_SetSRAMMacroPwrMode(sramNum, (uint32_t)macroNum, sramPwrMode);
1862 }
1863
1864 return CY_SYSPM_SUCCESS;
1865 }
1866
Cy_SysPm_TriggerSoftReset(void)1867 void Cy_SysPm_TriggerSoftReset(void)
1868 {
1869 SRSS_RES_SOFT_CTL = SRSS_RES_SOFT_CTL_TRIGGER_SOFT_Msk;
1870 }
1871
Cy_SysPm_TriggerXRes(void)1872 void Cy_SysPm_TriggerXRes(void)
1873 {
1874 SRSS_RES_PXRES_CTL = SRSS_RES_PXRES_CTL_PXRES_TRIGGER_Msk;
1875 }
1876
Cy_SysPm_IsSystemLp(void)1877 bool Cy_SysPm_IsSystemLp(void)
1878 {
1879 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_LP) != 0U);
1880 }
1881
Cy_SysPm_IsSystemUlp(void)1882 bool Cy_SysPm_IsSystemUlp(void)
1883 {
1884 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_ULP) != 0U);
1885 }
1886
Cy_SysPm_IsSystemHp(void)1887 bool Cy_SysPm_IsSystemHp(void)
1888 {
1889 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_HP) != 0U);
1890 }
1891
Cy_SysPm_SetTrimRamCtl(uint8_t index,uint32_t trimValue)1892 static void Cy_SysPm_SetTrimRamCtl(uint8_t index, uint32_t trimValue)
1893 {
1894 SRSS_TRIM_RAM_CTL(index) = trimValue;
1895 }
1896
Cy_SysPm_SystemEnterHpToDs(void)1897 static void Cy_SysPm_SystemEnterHpToDs(void)
1898 {
1899 uint32_t clkHfMask = Cy_SysClk_ClkHfAllGetMask();
1900 /* HP to DS Sequence */
1901 /* HP->DS(1) */
1902 /* Change HP frequency to 50MHz */
1903 Cy_SysClk_ClkHfEnableDirectMuxWithMask(clkHfMask, true);
1904
1905 /* HP->DS(2) */
1906 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_60B);
1907
1908 /* HP->DS(3) */
1909 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_E1F);
1910 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_61F);
1911
1912 /* HP->DS(4) */
1913 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_1E3F);
1914 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_E3F);
1915
1916 /* HP->DS(5) */
1917 /* Change frequency to 4MHz */
1918 /* Revisit this code during B0 */
1919 /* Cy_SysClk_ClkHfEnableDividerWithMask(clkHfMask, CY_SYSCLK_CLKHF_DIVIDE_BY_12); */
1920 }
1921
Cy_SysPm_SystemEnterDsToHp(void)1922 static void Cy_SysPm_SystemEnterDsToHp(void)
1923 {
1924 uint32_t clkHfMask = Cy_SysClk_ClkHfAllGetMask();
1925 /* DS to HP Sequence */
1926 /* DS->HP(2) */
1927 /* Change frequency to 50MHz */
1928 /* Revisit this code during B0 */
1929 /* Cy_SysClk_ClkHfEnableDividerWithMask(clkHfMask, CY_SYSCLK_CLKHF_NO_DIVIDE); */
1930
1931 /* DS->HP(3) */
1932 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_E1F);
1933 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_61F);
1934
1935 /* DS->HP(4) */
1936 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_60B);
1937 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_20B);
1938
1939 /* DS->HP(5) */
1940 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_202);
1941
1942 /* DS->HP(6) */
1943 /* Change frequency to HP Frequency */
1944 Cy_SysClk_ClkHfEnableDirectMuxWithMask(clkHfMask, false);
1945 }
1946
Cy_SysPm_SystemEnterLpToDs(void)1947 static void Cy_SysPm_SystemEnterLpToDs(void)
1948 {
1949 uint32_t clkHfMask = Cy_SysClk_ClkHfAllGetMask();
1950 /* LP to DS Sequence */
1951 /* LP->DS(1) */
1952 /* Change LP frequency to 50MHz */
1953 Cy_SysClk_ClkHfEnableDirectMuxWithMask(clkHfMask, true);
1954
1955 /* LP->DS(2) */
1956 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_60D);
1957 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_60D);
1958
1959 /* LP->DS(3) */
1960 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_E1F);
1961 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_61F);
1962
1963 /* LP->DS(4) */
1964 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_1E3F);
1965 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_E3F);
1966
1967 /* LP->DS(5) */
1968 /* Change frequency to 4MHz */
1969 /* Revisit this code during B0 */
1970 /* Cy_SysClk_ClkHfEnableDividerWithMask(clkHfMask, CY_SYSCLK_CLKHF_DIVIDE_BY_12); */
1971 }
1972
Cy_SysPm_SystemEnterDsToLp(void)1973 static void Cy_SysPm_SystemEnterDsToLp(void)
1974 {
1975 uint32_t clkHfMask = Cy_SysClk_ClkHfAllGetMask();
1976 /* DS to LP Sequence */
1977 /* DS->LP(2) */
1978 /* Change frequency to 50MHz */
1979 /* Revisit this code during B0 */
1980 /* Cy_SysClk_ClkHfEnableDividerWithMask(clkHfMask, CY_SYSCLK_CLKHF_NO_DIVIDE); */
1981
1982 /* DS->LP(3) */
1983 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_E1F);
1984 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_61F);
1985
1986 /* DS->LP(4) */
1987 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_60D);
1988 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_60D);
1989
1990 /* DS->LP(5) */
1991 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_604);
1992 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_604);
1993
1994 /* DS->LP(6) */
1995 /* Change frequency to LP Frequency */
1996 Cy_SysClk_ClkHfEnableDirectMuxWithMask(clkHfMask, false);
1997 }
1998
1999
Cy_SysPm_SystemEnterUlpToDs(void)2000 static void Cy_SysPm_SystemEnterUlpToDs(void)
2001 {
2002 uint32_t clkHfMask = Cy_SysClk_ClkHfAllGetMask();
2003
2004 /* ULP to DS Sequence */
2005 /* ULP->DS(1) */
2006 /* Change ULP frequency to 25MHz */
2007 Cy_SysClk_ClkHfEnableDirectMuxWithMask(clkHfMask, true);
2008 /* Revisit this code during B0 */
2009 /* Cy_SysClk_ClkHfEnableDividerWithMask(clkHfMask, CY_SYSCLK_CLKHF_DIVIDE_BY_2); */
2010
2011 /* ULP->DS(2) */
2012 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_60F);
2013 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_60F);
2014
2015 /* ULP->DS(3) */
2016 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_E1F);
2017 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_61F);
2018
2019 /* ULP->DS(4) */
2020 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_1E3F);
2021 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_E3F);
2022
2023 /* ULP->DS(5) */
2024 /* Change frequency to 4MHz */
2025 /* Revisit this code during B0 */
2026 /* Cy_SysClk_ClkHfEnableDividerWithMask(clkHfMask, CY_SYSCLK_CLKHF_DIVIDE_BY_12); */
2027 }
2028
Cy_SysPm_SystemEnterDsToUlp(void)2029 static void Cy_SysPm_SystemEnterDsToUlp(void)
2030 {
2031 uint32_t clkHfMask = Cy_SysClk_ClkHfAllGetMask();
2032 /* DS to ULP Sequence */
2033 /* DS->ULP(2) */
2034 /* Change frequency to 25MHz */
2035 /* Revisit this code during B0 */
2036 /* Cy_SysClk_ClkHfEnableDividerWithMask(clkHfMask, CY_SYSCLK_CLKHF_DIVIDE_BY_2); */
2037
2038 /* DS->ULP(3) */
2039 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_E1F);
2040 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_61F);
2041
2042 /* DS->ULP(4) */
2043 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_60B);
2044 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_60B);
2045
2046 /* DS->ULP(5) */
2047 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_603);
2048 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_603);
2049
2050 /* DS->ULP(6) */
2051 /* Change frequency to ULP Frequency */
2052 /* Revisit this code during B0 */
2053 /* Cy_SysClk_ClkHfEnableDividerWithMask(clkHfMask, CY_SYSCLK_CLKHF_NO_DIVIDE); */
2054 Cy_SysClk_ClkHfEnableDirectMuxWithMask(clkHfMask, false);
2055 }
2056
Cy_SysPm_SetRamTrimsPreDs(void)2057 void Cy_SysPm_SetRamTrimsPreDs(void)
2058 {
2059 while (CY_IPC_SEMA_STATUS_LOCKED == Cy_IPC_Sema_Status(CY_SYSPM_SEMA_NUM_MULTI_CORE)){}
2060 (void)Cy_IPC_Sema_Set(CY_SYSPM_SEMA_NUM_MULTI_CORE, false);
2061
2062 #if (CY_CPU_CORTEX_M33)
2063 if(Cy_SysPm_Cm55IsDeepSleep())
2064 #endif
2065 #if (CY_CPU_CORTEX_M55)
2066 if(Cy_SysPm_Cm33IsDeepSleep())
2067 #endif
2068 {
2069 if(Cy_SysPm_IsSystemHp())
2070 {
2071 Cy_SysPm_SystemEnterHpToDs();
2072 }
2073 else if(Cy_SysPm_IsSystemLp())
2074 {
2075 Cy_SysPm_SystemEnterLpToDs();
2076 }
2077 else if(Cy_SysPm_IsSystemUlp())
2078 {
2079 Cy_SysPm_SystemEnterUlpToDs();
2080 }
2081 else
2082 {
2083 /* Do Nothing */
2084 }
2085 }
2086
2087 (void)Cy_IPC_Sema_Clear(CY_SYSPM_SEMA_POST_TRIM_STATUS, false);
2088
2089 (void)Cy_IPC_Sema_Clear(CY_SYSPM_SEMA_NUM_MULTI_CORE, false);
2090 }
2091
Cy_SysPm_SetRamTrimsPostDs(void)2092 void Cy_SysPm_SetRamTrimsPostDs(void)
2093 {
2094 while (CY_IPC_SEMA_STATUS_LOCKED == Cy_IPC_Sema_Status(CY_SYSPM_SEMA_NUM_MULTI_CORE)){}
2095 (void)Cy_IPC_Sema_Set(CY_SYSPM_SEMA_NUM_MULTI_CORE, false);
2096
2097 if (CY_IPC_SEMA_STATUS_UNLOCKED == Cy_IPC_Sema_Status(CY_SYSPM_SEMA_POST_TRIM_STATUS)){}
2098 {
2099 if(Cy_SysPm_IsSystemHp())
2100 {
2101 Cy_SysPm_SystemEnterDsToHp();
2102 }
2103 else if(Cy_SysPm_IsSystemLp())
2104 {
2105 Cy_SysPm_SystemEnterDsToLp();
2106 }
2107 else if(Cy_SysPm_IsSystemUlp())
2108 {
2109 Cy_SysPm_SystemEnterDsToUlp();
2110 }
2111 else
2112 {
2113 /* Do Nothing */
2114 }
2115
2116 (void)Cy_IPC_Sema_Set(CY_SYSPM_SEMA_POST_TRIM_STATUS, false);
2117 }
2118
2119 (void)Cy_IPC_Sema_Clear(CY_SYSPM_SEMA_NUM_MULTI_CORE, false);
2120 }
2121
Cy_SysPm_SystemEnterHpToLp(void)2122 static cy_en_syspm_status_t Cy_SysPm_SystemEnterHpToLp(void)
2123 {
2124 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2125
2126 /* HP to LP Sequence */
2127
2128 /* 1) M33 send IPC to m0seccpuss - Operating mode change target */
2129 //TBD
2130
2131 /* 2) Retention Level change */
2132 //TBD
2133
2134 /* 3) Reduce the frequency so it is at least ??% (400MHz to <=75MHz) below the static timing closure limits at the new voltage setting for SRAM timing margin */
2135 /* Frequency Reduction needs to be done before calling this API */
2136
2137
2138 /* 4) SRAM trim updates - HP->LP(2) through HP->LP(5) */
2139 /* HP->LP(2) */
2140 Cy_SysPm_SetTrimRamCtl(0U, RAM_TRIM_VAL_343);
2141 Cy_SysPm_SetTrimRamCtl(1U, RAM_TRIM_VAL_343);
2142
2143 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_206);
2144 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_206);
2145
2146 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_20F);
2147 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_20F);
2148
2149 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_3F);
2150 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_3F);
2151
2152 Cy_SysPm_SetTrimRamCtl(8U, RAM_TRIM_VAL_B);
2153
2154 /* HP->LP(3) */
2155 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_204);
2156 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_204);
2157
2158 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_20C);
2159 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_20C);
2160
2161 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_2D);
2162 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_2D);
2163
2164 /* HP->LP(4) */
2165 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_204);
2166 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_204);
2167
2168 /* HP->LP(5) */
2169 Cy_SysPm_SetTrimRamCtl(0U, RAM_TRIM_VAL_743);
2170 Cy_SysPm_SetTrimRamCtl(1U, RAM_TRIM_VAL_743);
2171
2172 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_604);
2173 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_604);
2174
2175 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_22D);
2176 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_22D);
2177
2178 /* 5) Change the voltage */
2179 Cy_SysPm_CoreBuckSetProfile(CY_SYSPM_CORE_BUCK_PROFILE_LP);
2180
2181 if(CY_SYSPM_SUCCESS != Cy_SysPm_CoreBuckStatus())
2182 {
2183 retVal = CY_SYSPM_FAIL;
2184 }
2185 else
2186 {
2187 Cy_SysPm_SramLdoSetVoltage(CY_SYSPM_SRAMLDO_VOLTAGE_0_80V);
2188 retVal = Cy_SysPm_SramLdoEnable(true);
2189
2190 if(CY_SYSPM_SUCCESS != retVal)
2191 {
2192 retVal = CY_SYSPM_FAIL;
2193 }
2194 else
2195 {
2196 /* 6) SRAM trim updates - HP->LP(7) */
2197 /* HP->LP(7) */
2198 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_604);
2199 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_604);
2200
2201 /* 7) M33 send IPC to m0seccpuss - Voltage at target level */
2202 //TBD
2203
2204 /* 8) Change RRAM to LP mode */
2205 Cy_RRAM_SetVoltageMode(RRAMC0, CY_RRAM_VMODE_LP);
2206
2207 /* 9) Change Frequency */
2208 /* Frequency Change needs to be done after calling this API */
2209
2210 /* 10) M33 sends IPC to m0seccpuss - Frequency at target level */
2211 //TBD
2212 }
2213 }
2214
2215
2216 return retVal;
2217 }
2218
Cy_SysPm_SystemEnterLpToHp(void)2219 static cy_en_syspm_status_t Cy_SysPm_SystemEnterLpToHp(void)
2220 {
2221 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2222
2223 /* LP to HP Sequence */
2224
2225 /* 1) M33 send IPC to m0seccpuss - Operating mode change target */
2226 //TBD
2227
2228 /* 2) Retention Level change */
2229 //TBD
2230
2231 /* 3) Reduce frequency by at least 38% (120MHz to <=75MHz) for SRAM timing margin */
2232 /* Frequency Reduction needs to be done before calling this API */
2233
2234 /* 4) SRAM trim updates - LP->HP(2) through LP->HP(5) */
2235 /* LP->HP(2) */
2236 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_606);
2237 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_606);
2238
2239 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_606);
2240 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_606);
2241
2242 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_23F);
2243 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_23F);
2244
2245 /* LP->HP(3) */
2246 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_607);
2247 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_607);
2248
2249 /* LP->HP(4) */
2250 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_60F);
2251 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_60F);
2252
2253 /* LP->HP(5) */
2254 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_20F);
2255 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_20F);
2256
2257 /* 5) Change the voltage */
2258 Cy_SysPm_CoreBuckSetProfile(CY_SYSPM_CORE_BUCK_PROFILE_HP);
2259
2260 if(CY_SYSPM_SUCCESS != Cy_SysPm_CoreBuckStatus())
2261 {
2262 retVal = CY_SYSPM_FAIL;
2263 }
2264 else
2265 {
2266 Cy_SysPm_SramLdoSetVoltage(CY_SYSPM_SRAMLDO_VOLTAGE_0_90V);
2267 retVal = Cy_SysPm_SramLdoEnable(true);
2268
2269 if(CY_SYSPM_SUCCESS != retVal)
2270 {
2271 retVal = CY_SYSPM_FAIL;
2272 }
2273 else
2274 {
2275 /* 6) SRAM trim updates - LP->HP(7) & LP->HP(8) */
2276 /* LP->HP(7) */
2277 Cy_SysPm_SetTrimRamCtl(0U, RAM_TRIM_VAL_343);
2278 Cy_SysPm_SetTrimRamCtl(1U, RAM_TRIM_VAL_343);
2279
2280 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_206);
2281 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_206);
2282
2283 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_3F);
2284 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_3F);
2285
2286 Cy_SysPm_SetTrimRamCtl(8U, RAM_TRIM_VAL_A);
2287
2288 /* LP->HP(8) */
2289 Cy_SysPm_SetTrimRamCtl(0U, RAM_TRIM_VAL_342);
2290 Cy_SysPm_SetTrimRamCtl(1U, RAM_TRIM_VAL_342);
2291
2292 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_202);
2293 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_202);
2294
2295 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_20B);
2296 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_20B);
2297
2298 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_1B);
2299 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_1B);
2300
2301 /* 7) M33 send IPC to m0seccpuss - Voltage at target level */
2302 //TBD
2303
2304 /* 8) Change RRAM to LP mode */
2305 Cy_RRAM_SetVoltageMode(RRAMC0, CY_RRAM_VMODE_HP);
2306
2307 /* 9) Change Frequency */
2308 /* Frequency Change needs to be done after calling this API */
2309
2310 /* 10) M33 sends IPC to m0seccpuss - Frequency at target level */
2311 //TBD
2312 }
2313 }
2314
2315
2316 return retVal;
2317 }
2318
Cy_SysPm_SystemEnterUlpToLp(void)2319 static cy_en_syspm_status_t Cy_SysPm_SystemEnterUlpToLp(void)
2320 {
2321 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2322
2323 /* ULP to LP Sequence */
2324
2325 /* 1) M33 send IPC to m0seccpuss - Operating mode change target */
2326 //TBD
2327
2328 /* 2) Retention Level change */
2329 //TBD
2330
2331 /* 3) ULP->LP(1), Reduce frequency by at least 18% (50MHz to <= 41MHz) for SRAM timing margin */
2332 /* Frequency Reduction needs to be done before calling this API */
2333
2334 /* 4) SRAM trim updates - ULP->LP(3) through ULP->LP(5) */
2335 /* ULP->LP(3) */
2336 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_607);
2337 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_607);
2338
2339 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_607);
2340 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_607);
2341
2342 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_63D);
2343 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_63D);
2344
2345 Cy_SysPm_SetTrimRamCtl(8U, RAM_TRIM_VAL_F);
2346
2347 /* ULP->LP(4) */
2348 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_606);
2349 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_606);
2350
2351 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_606);
2352 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_606);
2353
2354 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_62D);
2355 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_62D);
2356
2357 Cy_SysPm_SetTrimRamCtl(8U, RAM_TRIM_VAL_B);
2358
2359 /* ULP->LP(5) */
2360 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_604);
2361 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_604);
2362
2363 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_604);
2364 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_604);
2365
2366 /* 5) Change the voltage */
2367 Cy_SysPm_CoreBuckSetProfile(CY_SYSPM_CORE_BUCK_PROFILE_LP);
2368
2369 if(CY_SYSPM_SUCCESS != Cy_SysPm_CoreBuckStatus())
2370 {
2371 retVal = CY_SYSPM_FAIL;
2372 }
2373 else
2374 {
2375 /* 5.1 Disable the SRAMLDO allowing CBUCK to supply SRAM Core */
2376 retVal = Cy_SysPm_SramLdoEnable(false);
2377
2378 if(CY_SYSPM_SUCCESS != retVal)
2379 {
2380 retVal = CY_SYSPM_FAIL;
2381 }
2382 else
2383 {
2384 /* 6) SRAM trim updates - ULP->LP(7) */
2385 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_22D);
2386 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_22D);
2387
2388 /* 7) M33 send IPC to m0seccpuss - Voltage at target level */
2389 //TBD
2390
2391 /* 8) Change RRAM to LP mode */
2392 Cy_RRAM_SetVoltageMode(RRAMC0, CY_RRAM_VMODE_LP);
2393
2394 /* 9) Change Frequency */
2395 /* Frequency Change needs to be done after calling this API */
2396
2397 /* 10) M33 sends IPC to m0seccpuss - Frequency at target level */
2398 //TBD
2399 }
2400 }
2401 return retVal;
2402 }
2403
Cy_SysPm_SystemEnterLpToUlp(void)2404 static cy_en_syspm_status_t Cy_SysPm_SystemEnterLpToUlp(void)
2405 {
2406 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2407
2408 /* LP to ULP Sequence */
2409
2410 /* 1) M33 send IPC to m0seccpuss - Operating mode change target */
2411 //TBD
2412
2413 /* 2) Retention Level change */
2414 //TBD
2415
2416 /* 3) Reduce the operating frequency so it is at least 66% (120MHz to 41MHz) */
2417 /* Frequency Reduction needs to be done before calling this API */
2418
2419 /* LP->ULP(2) */
2420 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_23D);
2421 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_23D);
2422
2423 Cy_SysPm_SetTrimRamCtl(8U, RAM_TRIM_VAL_F);
2424
2425 /* LP->ULP(3) */
2426 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_63D);
2427 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_63D);
2428
2429 /* 5) Change the voltage */
2430 /* 5.1 Enable the SRAMLDO to supply SRAM Core */
2431 retVal = Cy_SysPm_SramLdoEnable(true);
2432
2433 if(CY_SYSPM_SUCCESS != retVal)
2434 {
2435 retVal = CY_SYSPM_FAIL;
2436 }
2437 else
2438 {
2439 /* 5.2 Select the ULP voltage profile */
2440 Cy_SysPm_CoreBuckSetProfile(CY_SYSPM_CORE_BUCK_PROFILE_ULP);
2441
2442 if(CY_SYSPM_SUCCESS != Cy_SysPm_CoreBuckStatus())
2443 {
2444 retVal = CY_SYSPM_FAIL;
2445 }
2446 else
2447 {
2448 /* 6) SRAM trim updates - LP->ULP(5) & LP->ULP(7) */
2449 /* LP->ULP(5) */
2450 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_606);
2451 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_606);
2452
2453 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_606);
2454 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_606);
2455
2456 Cy_SysPm_SetTrimRamCtl(6U, RAM_TRIM_VAL_61D);
2457 Cy_SysPm_SetTrimRamCtl(7U, RAM_TRIM_VAL_61D);
2458
2459 Cy_SysPm_SetTrimRamCtl(8U, RAM_TRIM_VAL_C);
2460
2461 /* LP->ULP(6) */
2462 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_607);
2463 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_607);
2464
2465 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_607);
2466 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_607);
2467
2468 /* LP->ULP(7) */
2469 Cy_SysPm_SetTrimRamCtl(2U, RAM_TRIM_VAL_603);
2470 Cy_SysPm_SetTrimRamCtl(3U, RAM_TRIM_VAL_603);
2471
2472 Cy_SysPm_SetTrimRamCtl(4U, RAM_TRIM_VAL_603);
2473 Cy_SysPm_SetTrimRamCtl(5U, RAM_TRIM_VAL_603);
2474
2475 /* 7) M33 send IPC to m0seccpuss - Voltage at target level */
2476 //TBD
2477
2478 /* 8) Change RRAM to ULP mode */
2479 Cy_RRAM_SetVoltageMode(RRAMC0, CY_RRAM_VMODE_ULP);
2480
2481 /* 9) Change Frequency */
2482 /* Frequency Change needs to be done after calling this API */
2483
2484 /* 10) M33 sends IPC to m0seccpuss - Frequency at target level */
2485 //TBD
2486 }
2487 }
2488
2489 return retVal;
2490 }
2491
Cy_SysPm_SystemEnterHp(void)2492 cy_en_syspm_status_t Cy_SysPm_SystemEnterHp(void)
2493 {
2494 uint32_t interruptState;
2495 uint32_t cbLpRootIdx = (uint32_t) CY_SYSPM_HP;
2496 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2497
2498 /* Call the registered callback functions with the
2499 * CY_SYSPM_CHECK_READY parameter
2500 */
2501 if (pmCallbackRoot[cbLpRootIdx] != NULL)
2502 {
2503 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_HP, CY_SYSPM_CHECK_READY);
2504 }
2505
2506 /* The system can switch into LP only when
2507 * all executed registered callback functions with the
2508 * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
2509 */
2510 if (retVal == CY_SYSPM_SUCCESS)
2511 {
2512
2513 /* Call the registered callback functions with the
2514 * CY_SYSPM_BEFORE_TRANSITION parameter
2515 */
2516 interruptState = Cy_SysLib_EnterCriticalSection();
2517 if (pmCallbackRoot[cbLpRootIdx] != NULL)
2518 {
2519 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HP, CY_SYSPM_BEFORE_TRANSITION);
2520 }
2521
2522 if(Cy_SysPm_IsSystemLp())
2523 {
2524 (void) Cy_SysPm_SystemEnterLpToHp();
2525 }
2526 else if(Cy_SysPm_IsSystemUlp())
2527 {
2528 (void) Cy_SysPm_SystemEnterUlpToLp();
2529 (void) Cy_SysPm_SystemEnterLpToHp();
2530 }
2531 else
2532 {
2533 /*Block added to avoid MISRA errors */
2534 }
2535
2536 Cy_SysLib_ExitCriticalSection(interruptState);
2537
2538 /* Call the registered callback functions with the
2539 * CY_SYSPM_AFTER_TRANSITION parameter
2540 */
2541 if (pmCallbackRoot[cbLpRootIdx] != NULL)
2542 {
2543 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HP, CY_SYSPM_AFTER_TRANSITION);
2544 }
2545 }
2546 else
2547 {
2548 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
2549 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
2550 * parameter
2551 */
2552 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HP, CY_SYSPM_CHECK_FAIL);
2553 retVal = CY_SYSPM_FAIL;
2554 }
2555
2556 return retVal;
2557 }
2558
2559
Cy_SysPm_SystemEnterUlp(void)2560 cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void)
2561 {
2562 uint32_t interruptState;
2563 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2564 uint32_t cbUlpRootIdx = (uint32_t) CY_SYSPM_ULP;
2565
2566 /* Call the registered callback functions with the
2567 * CY_SYSPM_CHECK_READY parameter
2568 */
2569 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2570 {
2571 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_CHECK_READY);
2572 }
2573
2574 /* The system can switch into the ULP only when
2575 * all executed registered callback functions with the
2576 * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
2577 */
2578 if (retVal == CY_SYSPM_SUCCESS)
2579 {
2580 /* Call the registered callback functions with the
2581 * CY_SYSPM_BEFORE_TRANSITION parameter
2582 */
2583 interruptState = Cy_SysLib_EnterCriticalSection();
2584 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2585 {
2586 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_BEFORE_TRANSITION);
2587 }
2588
2589 if(Cy_SysPm_IsSystemLp())
2590 {
2591 (void) Cy_SysPm_SystemEnterLpToUlp();
2592 }
2593 else if(Cy_SysPm_IsSystemHp())
2594 {
2595 (void) Cy_SysPm_SystemEnterHpToLp();
2596 (void) Cy_SysPm_SystemEnterLpToUlp();
2597 }
2598 else
2599 {
2600 /*Block added to avoid MISRA errors */
2601 }
2602
2603 Cy_SysLib_ExitCriticalSection(interruptState);
2604
2605 /* Call the registered callback functions with the
2606 * CY_SYSPM_AFTER_TRANSITION parameter
2607 */
2608 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2609 {
2610 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_AFTER_TRANSITION);
2611 }
2612 }
2613 else
2614 {
2615 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
2616 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
2617 * parameter
2618 */
2619 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_CHECK_FAIL);
2620 retVal = CY_SYSPM_FAIL;
2621 }
2622
2623 return retVal;
2624 }
2625
2626
Cy_SysPm_SystemEnterLp(void)2627 cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void)
2628 {
2629 uint32_t interruptState;
2630 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2631 uint32_t cbUlpRootIdx = (uint32_t) CY_SYSPM_LP;
2632
2633 /* Call the registered callback functions with the
2634 * CY_SYSPM_CHECK_READY parameter
2635 */
2636 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2637 {
2638 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_CHECK_READY);
2639 }
2640
2641 /* The system can switch into the ULP only when
2642 * all executed registered callback functions with the
2643 * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
2644 */
2645 if (retVal == CY_SYSPM_SUCCESS)
2646 {
2647 /* Call the registered callback functions with the
2648 * CY_SYSPM_BEFORE_TRANSITION parameter
2649 */
2650 interruptState = Cy_SysLib_EnterCriticalSection();
2651 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2652 {
2653 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_BEFORE_TRANSITION);
2654 }
2655
2656 if(Cy_SysPm_IsSystemHp())
2657 {
2658 (void) Cy_SysPm_SystemEnterHpToLp();
2659 }
2660 else if(Cy_SysPm_IsSystemUlp())
2661 {
2662 (void) Cy_SysPm_SystemEnterUlpToLp();
2663 }
2664 else
2665 {
2666 /*Block added to avoid MISRA errors */
2667 }
2668
2669 Cy_SysLib_ExitCriticalSection(interruptState);
2670
2671 /* Call the registered callback functions with the
2672 * CY_SYSPM_AFTER_TRANSITION parameter
2673 */
2674 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2675 {
2676 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_AFTER_TRANSITION);
2677 }
2678 }
2679 else
2680 {
2681 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
2682 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
2683 * parameter
2684 */
2685 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_CHECK_FAIL);
2686 retVal = CY_SYSPM_FAIL;
2687 }
2688
2689 return retVal;
2690 }
2691
2692
Cy_SysPm_ReadStatus(void)2693 uint32_t Cy_SysPm_ReadStatus(void)
2694 {
2695 uint32_t pmStatus = 0UL;
2696
2697 /* Check whether the device is in ULP/LP/HP mode by reading
2698 * the core buck profile:
2699 * - 0.7V (nominal) - System ULP mode
2700 * - 0.8V (nominal) - System LP mode
2701 * - 0.9V (nominal) - System HP mode
2702 */
2703
2704 /* Read current active regulator */
2705 /* Current active regulator is LDO */
2706 if (Cy_SysPm_CoreBuckGetProfile() == CY_SYSPM_CORE_BUCK_PROFILE_LP)
2707 {
2708 pmStatus |= CY_SYSPM_STATUS_SYSTEM_LP;
2709 }
2710 else if (Cy_SysPm_CoreBuckGetProfile() == CY_SYSPM_CORE_BUCK_PROFILE_ULP)
2711 {
2712 pmStatus |= CY_SYSPM_STATUS_SYSTEM_ULP;
2713 }
2714 else
2715 {
2716 pmStatus |= CY_SYSPM_STATUS_SYSTEM_HP;
2717 }
2718
2719 /* Check whether CM33 is in the deep sleep mode*/
2720 if((0u != _FLD2VAL(MXCM33_CM33_STATUS_SLEEPING, MXCM33_CM33_STATUS)) &&
2721 (0u != _FLD2VAL(MXCM33_CM33_STATUS_SLEEPDEEP, MXCM33_CM33_STATUS)))
2722 {
2723 pmStatus |= (uint32_t) CY_SYSPM_STATUS_CM33_DEEPSLEEP;
2724 }
2725 /* Check whether CM33 is in the sleep mode*/
2726 else if (0u != _FLD2VAL(MXCM33_CM33_STATUS_SLEEPING, MXCM33_CM33_STATUS))
2727 {
2728 pmStatus |= CY_SYSPM_STATUS_CM33_SLEEP;
2729 }
2730 else
2731 {
2732 pmStatus |= CY_SYSPM_STATUS_CM33_ACTIVE;
2733 }
2734
2735 /* Check whether CM55 is in the deep sleep mode*/
2736 if((0u != _FLD2VAL(MXCM55_CM55_STATUS_SLEEPING, MXCM55_CM55_STATUS)) &&
2737 (0u != _FLD2VAL(MXCM55_CM55_STATUS_SLEEPDEEP, MXCM55_CM55_STATUS)))
2738 {
2739 pmStatus |= (uint32_t) CY_SYSPM_STATUS_CM55_DEEPSLEEP;
2740 }
2741 /* Check whether CM33 is in the sleep mode*/
2742 else if (0u != _FLD2VAL(MXCM55_CM55_STATUS_SLEEPING, MXCM55_CM55_STATUS))
2743 {
2744 pmStatus |= CY_SYSPM_STATUS_CM55_SLEEP;
2745 }
2746 else
2747 {
2748 pmStatus |= CY_SYSPM_STATUS_CM55_ACTIVE;
2749 }
2750
2751 return pmStatus;
2752 }
2753
Cy_SysPm_Cm33IsActive(void)2754 bool Cy_SysPm_Cm33IsActive(void)
2755 {
2756 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM33_ACTIVE) != 0u);
2757 }
2758
Cy_SysPm_Cm33IsSleep(void)2759 bool Cy_SysPm_Cm33IsSleep(void)
2760 {
2761 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM33_SLEEP) != 0u);
2762 }
2763
Cy_SysPm_Cm33IsDeepSleep(void)2764 bool Cy_SysPm_Cm33IsDeepSleep(void)
2765 {
2766 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM33_DEEPSLEEP) != 0u);
2767 }
2768
Cy_SysPm_Cm55IsActive(void)2769 bool Cy_SysPm_Cm55IsActive(void)
2770 {
2771 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM55_ACTIVE) != 0u);
2772 }
2773
Cy_SysPm_Cm55IsSleep(void)2774 bool Cy_SysPm_Cm55IsSleep(void)
2775 {
2776 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM55_SLEEP) != 0u);
2777 }
2778
Cy_SysPm_Cm55IsDeepSleep(void)2779 bool Cy_SysPm_Cm55IsDeepSleep(void)
2780 {
2781 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM55_DEEPSLEEP) != 0u);
2782 }
2783
2784
2785 #endif /* CY_IP_MXS22SRSS */
2786 /* [] END OF FILE */
2787
