1 /***************************************************************************//**
2 * \file cy_syspm_v3.c
3 * \version 5.150
4 *
5 * This driver provides the source code for API power management.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27 #include "cy_sysclk.h"
28
29 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)
30
31 #include "cy_syspm.h"
32
33 /*******************************************************************************
34 * Internal Functions
35 *******************************************************************************/
36
37 /*******************************************************************************
38 * Internal Defines
39 *******************************************************************************/
40
41 /* The define for number of callback roots */
42 #define CALLBACK_ROOT_NR (5U)
43
44 /* The mask to unlock the Hibernate power mode */
45 #define HIBERNATE_UNLOCK_VAL ((uint32_t) 0x3Au << SRSS_PWR_HIBERNATE_UNLOCK_Pos)
46
47 /* The mask to set the Hibernate power mode */
48 #define SET_HIBERNATE_MODE ((HIBERNATE_UNLOCK_VAL |\
49 SRSS_PWR_HIBERNATE_FREEZE_Msk |\
50 SRSS_PWR_HIBERNATE_HIBERNATE_Msk))
51
52 /* The mask to retain the Hibernate power mode status */
53 #define HIBERNATE_RETAIN_STATUS_MASK ((SRSS_PWR_HIBERNATE_TOKEN_Msk |\
54 SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\
55 SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\
56 SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\
57 SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk))
58
59 /** The mask for the Hibernate wakeup sources */
60 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION == 3u) && defined (CY_IP_MXS40SRSS_VERSION_MINOR) && (CY_IP_MXS40SRSS_VERSION_MINOR >= 3u)
61 /** The mask for the Hibernate wakeup sources, for SRSSv3p3 and above */
62 #define HIBERNATE_WAKEUP_MASK ((SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_SRC_Msk |\
63 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_CSV_BAK_Msk |\
64 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_RTC_Msk |\
65 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_WDT_Msk))
66 #else
67 /** The mask for the Hibernate wakeup sources */
68 #define HIBERNATE_WAKEUP_MASK ((SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\
69 SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\
70 SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\
71 SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk))
72 #endif
73
74 /** The define to update the token to indicate the transition into Hibernate */
75 #define HIBERNATE_TOKEN ((uint32_t) 0x1BU << SRSS_PWR_HIBERNATE_TOKEN_Pos)
76
77 /* The wait time for transition into the minimum regulator current mode
78 */
79 #define SET_MIN_CURRENT_MODE_DELAY_US (1U)
80
81 /* The wait delay time that occurs before the active reference is settled.
82 * Intermediate delay is used in transition into the normal regulator current
83 * mode
84 */
85 #define ACT_REF_SETTLE_DELAY_US (6U)
86
87 /* The wait delay time that occurs after the active reference is settled.
88 * Final delay is used in transition into the normal regulator current mode
89 */
90 #define SET_NORMAL_CURRENT_MODE_DELAY_US (1U)
91
92 /* The internal define of the tries number in the
93 * Cy_SysPm_SystemSetMinRegulatorCurrent() function
94 */
95 #define WAIT_DELAY_TRIES (100U)
96
97 /* The internal define of the tries number in the
98 * Cy_Syspm_ReghcConfigure(), Cy_Syspm_ReghcDeConfigure() functions
99 */
100 #define REGHC_WAIT_DELAY_TRIES_US (20U)
101
102
103 /* The internal define of the tries number in the
104 * Cy_SysPm_SystemSetMinRegulatorCurrent() function
105 */
106 #define CY_SYSPM_CBUCK_BUSY_RETRY_COUNT (100U)
107 #define CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS (1U)
108
109 /* Mask for checking the CM4 Deep Sleep status */
110 #define CM4_DEEPSLEEP_MASK (CPUSS_CM4_STATUS_SLEEPING_Msk | CPUSS_CM4_STATUS_SLEEPDEEP_Msk)
111
112
113 /*******************************************************************************
114 * Internal Variables
115 *******************************************************************************/
116
117 /* Array of the callback roots */
118 static cy_stc_syspm_callback_t* pmCallbackRoot[CALLBACK_ROOT_NR] = {(void *)0, (void *)0, (void *)0, (void *)0, (void *)0};
119
120 /* The array of the pointers to failed callback */
121 static cy_stc_syspm_callback_t* failedCallback[CALLBACK_ROOT_NR] = {(void *)0, (void *)0, (void *)0, (void *)0, (void *)0};
122
Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor)123 cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor)
124 {
125 uint32_t interruptState;
126 uint32_t cbSleepRootIdx = (uint32_t) CY_SYSPM_SLEEP;
127 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
128
129 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
130
131 /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
132 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
133 {
134 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_READY);
135 }
136
137 /* The CPU can switch into the Sleep power mode only when
138 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
139 * parameter return CY_SYSPM_SUCCESS.
140 */
141 if(retVal == CY_SYSPM_SUCCESS)
142 {
143 /* Call the registered callback functions with
144 * CY_SYSPM_BEFORE_TRANSITION parameter
145 */
146 interruptState = Cy_SysLib_EnterCriticalSection();
147 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
148 {
149 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_BEFORE_TRANSITION);
150 }
151
152 /* The CPU enters the Sleep power mode upon execution of WFI/WFE */
153 SCB_SCR &= (uint32_t) ~SCB_SCR_SLEEPDEEP_Msk;
154
155 if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
156 {
157 __WFI();
158 }
159 else
160 {
161 __WFE();
162 }
163 Cy_SysLib_ExitCriticalSection(interruptState);
164
165 /* Call the registered callback functions with the
166 * CY_SYSPM_AFTER_TRANSITION parameter
167 */
168 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
169 {
170 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_AFTER_TRANSITION);
171 }
172 }
173 else
174 {
175 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
176 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
177 * parameter
178 */
179 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_FAIL);
180 retVal = CY_SYSPM_FAIL;
181 }
182 return retVal;
183 }
184
Cy_SysPm_SystemLpActiveEnter(void)185 cy_en_syspm_status_t Cy_SysPm_SystemLpActiveEnter(void)
186 {
187 uint32_t interruptState;
188 uint32_t cbSleepRootIdx = (uint32_t)CY_SYSPM_LPACTIVE_ENTER;
189 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
190
191 /* Step-1: Wait until PWR_CTL.LPM_READY==1 to indicate low power circuits are ready. */
192 if(!Cy_SysPm_IsLpmReady())
193 {
194 retVal = CY_SYSPM_FAIL;
195 }
196 else
197 {
198 /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
199 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
200 {
201 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_READY);
202 }
203
204 if (retVal == CY_SYSPM_SUCCESS)
205 {
206 /* The CPU can switch into the LPACTIVE power mode only when
207 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
208 * parameter return CY_SYSPM_SUCCESS.
209 */
210 /* Call the registered callback functions with
211 * CY_SYSPM_BEFORE_TRANSITION parameter
212 */
213 interruptState = Cy_SysLib_EnterCriticalSection();
214 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
215 {
216 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION); /* Suppress a compiler warning about unused return value */
217 }
218
219 /* Configure the low-power operating mode for Linear Core regulator */
220 if(Cy_SysPm_LdoIsEnabled())
221 {
222 SRSS_PWR_CTL2 |= _VAL2FLD(SRSS_PWR_CTL2_BGREF_LPMODE, 1u);
223 }
224
225 /* This wait time allows the circuits to remove their dependence on
226 * the Active mode circuits, such as Active Reference
227 */
228 Cy_SysLib_DelayUs(CY_SYSPM_ACTIVE_TO_LP_WAIT_US);
229
230 Cy_SysLib_ExitCriticalSection(interruptState);
231
232 /* Call the registered callback functions with the
233 * CY_SYSPM_AFTER_TRANSITION parameter
234 */
235 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
236 {
237 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_AFTER_TRANSITION); /* Suppress a compiler warning about unused return value */
238 }
239 }
240 else
241 {
242 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
243 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
244 * parameter
245 */
246 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_FAIL); /* Suppress a compiler warning about unused return value */
247 retVal = CY_SYSPM_FAIL;
248 }
249 }
250 return retVal;
251 }
252
Cy_SysPm_SystemLpActiveExit(void)253 cy_en_syspm_status_t Cy_SysPm_SystemLpActiveExit(void)
254 {
255 uint32_t interruptState;
256 uint32_t cbSleepRootIdx = (uint32_t)CY_SYSPM_LPACTIVE_EXIT;
257 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
258
259 /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
260 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
261 {
262 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_READY);
263 }
264
265 if (retVal == CY_SYSPM_SUCCESS)
266 {
267 /* The CPU can switch into the LPACTIVE power mode only when
268 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
269 * parameter return CY_SYSPM_SUCCESS.
270 */
271 /* Call the registered callback functions with
272 * CY_SYSPM_BEFORE_TRANSITION parameter
273 */
274 interruptState = Cy_SysLib_EnterCriticalSection();
275 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
276 {
277 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION); /* Suppress a compiler warning about unused return value */
278 }
279
280 /* This wait time allows setting Active Reference */
281 Cy_SysLib_DelayUs(CY_SYSPM_LP_TO_ACTIVE_WAIT_BEFORE_US);
282
283 /* Configure the normal operation mode */
284 SRSS_PWR_CTL2 &= ((uint32_t) (~SRSS_PWR_CTL2_BGREF_LPMODE_Msk));
285
286 /* This wait time allows setting Active Reference */
287 Cy_SysLib_DelayUs(CY_SYSPM_LP_TO_ACTIVE_WAIT_AFTER_US);
288
289 Cy_SysLib_ExitCriticalSection(interruptState);
290
291 /* Call the registered callback functions with the
292 * CY_SYSPM_AFTER_TRANSITION parameter
293 */
294 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
295 {
296 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_AFTER_TRANSITION); /* Suppress a compiler warning about unused return value */
297 }
298 }
299 else
300 {
301 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
302 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
303 * parameter
304 */
305 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_FAIL); /* Suppress a compiler warning about unused return value */
306 retVal = CY_SYSPM_FAIL;
307 }
308 return retVal;
309 }
310
Cy_SysPm_IsSystemLpActiveEnabled(void)311 bool Cy_SysPm_IsSystemLpActiveEnabled(void)
312 {
313 return (_FLD2BOOL(SRSS_PWR_CTL2_BGREF_LPMODE, SRSS_PWR_CTL2)? true : false);
314 }
315
Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor)316 cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor)
317 {
318 uint32_t interruptState;
319 uint32_t cbDeepSleepRootIdx = (uint32_t) CY_SYSPM_DEEPSLEEP;
320 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
321
322 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
323
324 //Check if LPM is ready
325 if(!Cy_SysPm_IsLpmReady())
326 {
327 retVal = CY_SYSPM_FAIL;
328 }
329 else
330 {
331 /* Call the registered callback functions with the CY_SYSPM_CHECK_READY
332 * parameter
333 */
334 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
335 {
336 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_READY);
337 }
338
339 /* The CPU can switch into the Deep Sleep power mode only when
340 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
341 * parameter return CY_SYSPM_SUCCESS
342 */
343 if (retVal == CY_SYSPM_SUCCESS)
344 {
345 /* Call the registered callback functions with the
346 * CY_SYSPM_BEFORE_TRANSITION parameter
347 */
348 interruptState = Cy_SysLib_EnterCriticalSection();
349 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
350 {
351 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION);
352 }
353 /* The CPU enters Deep Sleep mode upon execution of WFI/WFE
354 * use Cy_SysPm_SetDeepSleepMode to set various deepsleep modes TBD*/
355 SCB_SCR |= SCB_SCR_SLEEPDEEP_Msk;
356
357 if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
358 {
359 __WFI();
360 }
361 else
362 {
363 __WFE();
364 }
365
366 Cy_SysLib_ExitCriticalSection(interruptState);
367 }
368 if (retVal == CY_SYSPM_SUCCESS)
369 {
370 /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION
371 * parameter
372 */
373 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
374 {
375 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_AFTER_TRANSITION);
376 }
377 }
378 else
379 {
380 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
381 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
382 * parameter
383 */
384 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
385 {
386 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_FAIL);
387 }
388 }
389 }
390 return retVal;
391 }
392
Cy_SysPm_SystemEnterHibernate(void)393 cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void)
394 {
395 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
396 uint32_t cbHibernateRootIdx = (uint32_t) CY_SYSPM_HIBERNATE;
397 /* Call the registered callback functions with the
398 * CY_SYSPM_CHECK_READY parameter
399 */
400 if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
401 {
402 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_READY);
403 }
404
405 /* The system can switch into Hibernate power mode only when
406 * all executed registered callback functions with CY_SYSPM_CHECK_READY
407 * parameter return CY_SYSPM_SUCCESS.
408 */
409 if(retVal == CY_SYSPM_SUCCESS)
410 {
411 /* Call registered callback functions with CY_SYSPM_BEFORE_TRANSITION
412 * parameter
413 */
414 (void) Cy_SysLib_EnterCriticalSection();
415 if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
416 {
417 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_BEFORE_TRANSITION);
418 }
419
420 /* Preserve the token that will be retained through a wakeup sequence.
421 * This could be used by Cy_SysLib_GetResetReason() to differentiate
422 * Wakeup from a general reset event.
423 * Preserve the wakeup source(s) configuration.
424 */
425 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_WAKEUP_MASK) | HIBERNATE_TOKEN;
426
427 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION == 3u) && defined (CY_IP_MXS40SRSS_VERSION_MINOR) && (CY_IP_MXS40SRSS_VERSION_MINOR >= 3u)
428 /* Clear Previous Wakeup Reasons */
429 Cy_SysPm_ClearHibernateWakeupCause();
430 #endif
431
432 /* Disable overriding by the peripherals the next pin-freeze command */
433 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
434
435 /* The second write causes freezing of I/O cells to save the I/O-cell state */
436 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
437
438 /* Third write cause system to enter Hibernate */
439 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
440
441 /* Read register to make sure it is settled */
442 (void) SRSS_PWR_HIBERNATE;
443
444 /* Wait for transition */
445 __WFI();
446
447 /* The callback function calls with the CY_SYSPM_AFTER_TRANSITION
448 * parameter in the Hibernate power mode are not applicable as system
449 * wake-up was made on system reboot.
450 */
451
452 /* A wakeup from Hibernate is performed by toggling of the wakeup
453 * pins, or WDT matches, or Backup domain alarm expires. This depends on
454 * what item is configured in the Hibernate register. After a wakeup
455 * event, a normal Boot procedure occurs.
456 * There is no need to exit from the critical section.
457 */
458 }
459 else
460 {
461 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
462 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
463 * parameter. The return value should be CY_SYSPM_SUCCESS.
464 */
465 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_FAIL);
466 retVal = CY_SYSPM_FAIL;
467 }
468 return retVal;
469 }
470
Cy_SysPm_SystemSetMinRegulatorCurrent(void)471 cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void)
472 {
473 cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
474
475 /* Check if the power circuits are ready to enter into regulator minimum
476 * current mode
477 */
478 if (Cy_SysPm_IsLpmReady())
479 {
480 SRSS_PWR_CTL2 |= (SRSS_PWR_CTL2_BGREF_LPMODE_Msk);
481
482 /* This wait time allows the circuits to remove their dependence on
483 * the Active mode circuits, such as active Reference
484 */
485 Cy_SysLib_DelayUs(SET_MIN_CURRENT_MODE_DELAY_US);
486
487 retVal = CY_SYSPM_SUCCESS;
488 }
489
490 return retVal;
491 }
492
Cy_SysPm_SystemSetNormalRegulatorCurrent(void)493 cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void)
494 {
495 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
496
497 /* Disable the low-power for Bandgap reference circuit */
498 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_BGREF_LPMODE_Msk;
499
500 /* This wait time allows setting active Reference */
501 Cy_SysLib_DelayUs(ACT_REF_SETTLE_DELAY_US);
502
503 retVal= CY_SYSPM_SUCCESS;
504
505 return retVal;
506 }
507
Cy_SysPm_IsBgRefCtrl(void)508 bool Cy_SysPm_IsBgRefCtrl(void)
509 {
510 return (0U != _FLD2VAL(SRSS_PWR_CTL2_BGREF_LPMODE, SRSS_PWR_CTL2));
511 }
512
Cy_SysPm_BgRefCtrl(bool enable)513 void Cy_SysPm_BgRefCtrl(bool enable)
514 {
515 if(enable)
516 {
517 SRSS_PWR_CTL2 |= (uint32_t) SRSS_PWR_CTL2_BGREF_LPMODE_Msk;
518 }
519 else
520 {
521 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_BGREF_LPMODE_Msk;
522 }
523 }
524
Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode)525 cy_en_syspm_status_t Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode)
526 {
527 CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode));
528
529 cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
530
531 switch (mode)
532 {
533 case CY_SYSPM_LDO_MODE_NORMAL:
534 {
535 retVal = Cy_SysPm_SystemSetNormalRegulatorCurrent();
536 }
537 break;
538
539 case CY_SYSPM_LDO_MODE_MIN:
540 {
541 retVal = Cy_SysPm_SystemSetMinRegulatorCurrent();
542 }
543 break;
544
545 case CY_SYSPM_LDO_MODE_DISABLED:
546 {
547 /* Disable the LDO, Deep Sleep, nWell, and Retention regulators */
548 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_LINREG_DIS_Msk;
549 #if ((defined (SRSS_ULP_VARIANT)) && (SRSS_ULP_VARIANT == 1u))
550 /* Only set this bit if the deep sleep regulator is supported. */
551 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk;
552 #endif
553
554 retVal = CY_SYSPM_SUCCESS;
555 }
556 break;
557
558 default:
559 retVal = CY_SYSPM_FAIL;
560 break;
561 }
562
563 return retVal;
564 }
565
Cy_SysPm_LdoGetMode(void)566 cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void)
567 {
568 cy_en_syspm_ldo_mode_t retVal;
569
570 if (!Cy_SysPm_LdoIsEnabled())
571 {
572 retVal = CY_SYSPM_LDO_MODE_DISABLED;
573 }
574 else if (Cy_SysPm_SystemIsMinRegulatorCurrentSet())
575 {
576 retVal = CY_SYSPM_LDO_MODE_MIN;
577 }
578 else
579 {
580 retVal = CY_SYSPM_LDO_MODE_NORMAL;
581 }
582
583 return retVal;
584 }
585
Cy_SysPm_LdoIsEnabled(void)586 bool Cy_SysPm_LdoIsEnabled(void)
587 {
588 return ((0U != _FLD2VAL(SRSS_PWR_CTL2_LINREG_DIS, SRSS_PWR_CTL2)) ? false : true);
589 }
590
591
Cy_SysPm_CpuSleepOnExit(bool enable)592 void Cy_SysPm_CpuSleepOnExit(bool enable)
593 {
594 if(enable)
595 {
596 /* Enable sleep-on-exit feature */
597 SCB_SCR |= SCB_SCR_SLEEPONEXIT_Msk;
598 }
599 else
600 {
601 /* Disable sleep-on-exit feature */
602 SCB_SCR &= (uint32_t) ~(SCB_SCR_SLEEPONEXIT_Msk);
603 }
604 }
605
Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)606 void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)
607 {
608 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
609
610 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION == 3u) && defined (CY_IP_MXS40SRSS_VERSION_MINOR) && (CY_IP_MXS40SRSS_VERSION_MINOR >= 3u)
611 uint32_t polarityMask = 0U;
612 uint32_t wakeSrcMask = 0U;
613
614 /* PIN0 */
615 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW))
616 {
617 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW;
618 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 0)))
619 {
620 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW;
621 }
622 }
623
624 /* PIN1 */
625 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW))
626 {
627 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW;
628 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 1)))
629 {
630 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW;
631 }
632 }
633
634 /* PIN2 */
635 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN2_LOW))
636 {
637 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN2_LOW;
638 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 2)))
639 {
640 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN2_LOW;
641 }
642 }
643
644 /* PIN3 */
645 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN3_LOW))
646 {
647 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN3_LOW;
648 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 3)))
649 {
650 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN3_LOW;
651 }
652 }
653
654 /* PIN4 */
655 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN4_LOW))
656 {
657 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN4_LOW;
658 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 4)))
659 {
660 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN4_LOW;
661 }
662 }
663
664 /* PIN5 */
665 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN5_LOW))
666 {
667 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN5_LOW;
668 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 5)))
669 {
670 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN5_LOW;
671 }
672 }
673
674 /* PIN6 */
675 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN6_LOW))
676 {
677 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN6_LOW;
678 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 6)))
679 {
680 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN6_LOW;
681 }
682 }
683
684 /* PIN7 */
685 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN7_LOW))
686 {
687 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN7_LOW;
688 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 7)))
689 {
690 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN7_LOW;
691 }
692 }
693
694 /* PIN8 */
695 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN8_LOW))
696 {
697 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN8_LOW;
698 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 8)))
699 {
700 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN8_LOW;
701 }
702 }
703
704 /* PIN9 */
705 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN9_LOW))
706 {
707 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN9_LOW;
708 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 9)))
709 {
710 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN9_LOW;
711 }
712 }
713
714 /* CSV_BAK */
715 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_CSV_BAK))
716 {
717 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_CSV_BAK;
718 }
719
720 /* RTC */
721 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM))
722 {
723 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM;
724 }
725
726 /* WDT */
727 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_WDT))
728 {
729 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_WDT;
730 }
731
732 SRSS_PWR_HIB_WAKE_CTL = (SRSS_PWR_HIB_WAKE_CTL | wakeSrcMask);
733 SRSS_PWR_HIB_WAKE_CTL2 = (SRSS_PWR_HIB_WAKE_CTL2 | polarityMask);
734
735 /* Read registers to make sure it is settled */
736 (void) SRSS_PWR_HIB_WAKE_CTL;
737 (void) SRSS_PWR_HIB_WAKE_CTL2;
738 #else
739 uint32_t polarityMask = 0U;
740
741 if (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, wakeupSource))
742 {
743 /* Reconfigure the wakeup pins and LPComp polarity based on the input */
744 if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK))
745 {
746 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
747 }
748
749 if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK))
750 {
751 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
752 }
753
754 if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_PIN0_MASK))
755 {
756 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
757 }
758
759 if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_PIN1_MASK))
760 {
761 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
762 }
763 }
764
765 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & (uint32_t) ~polarityMask) | wakeupSource;
766
767 /* Read register to make sure it is settled */
768 (void) SRSS_PWR_HIBERNATE;
769 #endif
770
771 }
772
Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)773 void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)
774 {
775 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
776
777 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION == 3u) && defined (CY_IP_MXS40SRSS_VERSION_MINOR) && (CY_IP_MXS40SRSS_VERSION_MINOR >= 3u)
778
779 uint32_t polarityMask = 0U;
780 uint32_t wakeSrcMask = 0U;
781
782 /* PIN0 */
783 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW))
784 {
785 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW;
786 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 0)))
787 {
788 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW;
789 }
790 }
791
792 /* PIN1 */
793 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW))
794 {
795 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW;
796 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 1)))
797 {
798 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW;
799 }
800 }
801
802 /* PIN2 */
803 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN2_LOW))
804 {
805 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN2_LOW;
806 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 2)))
807 {
808 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN2_LOW;
809 }
810 }
811
812 /* PIN3 */
813 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN3_LOW))
814 {
815 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN3_LOW;
816 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 3)))
817 {
818 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN3_LOW;
819 }
820 }
821
822 /* PIN4 */
823 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN4_LOW))
824 {
825 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN4_LOW;
826 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 4)))
827 {
828 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN4_LOW;
829 }
830 }
831
832 /* PIN5 */
833 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN5_LOW))
834 {
835 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN5_LOW;
836 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 5)))
837 {
838 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN5_LOW;
839 }
840 }
841
842 /* PIN6 */
843 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN6_LOW))
844 {
845 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN6_LOW;
846 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 6)))
847 {
848 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN6_LOW;
849 }
850 }
851
852 /* PIN7 */
853 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN7_LOW))
854 {
855 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN7_LOW;
856 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 7)))
857 {
858 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN7_LOW;
859 }
860 }
861
862 /* PIN8 */
863 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN8_LOW))
864 {
865 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN8_LOW;
866 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 8)))
867 {
868 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN8_LOW;
869 }
870 }
871
872 /* PIN9 */
873 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN9_LOW))
874 {
875 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN9_LOW;
876 if (0U != (wakeupSource & (CY_SYSPM_HIBERNATE_POLARITY_HIGH_FLAG << 9)))
877 {
878 polarityMask |= (uint32_t)CY_SYSPM_HIBERNATE_PIN9_LOW;
879 }
880 }
881
882 /* CSV_BAK */
883 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_CSV_BAK))
884 {
885 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_CSV_BAK;
886 }
887
888 /* RTC */
889 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM))
890 {
891 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM;
892 }
893
894 /* WDT */
895 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_WDT))
896 {
897 wakeSrcMask |= (uint32_t)CY_SYSPM_HIBERNATE_WDT;
898 }
899
900 SRSS_PWR_HIB_WAKE_CTL = (SRSS_PWR_HIB_WAKE_CTL & (~wakeSrcMask));
901 SRSS_PWR_HIB_WAKE_CTL2 = (SRSS_PWR_HIB_WAKE_CTL2 & (~polarityMask));
902
903 /* Read registers to make sure it is settled */
904 (void) SRSS_PWR_HIB_WAKE_CTL;
905 (void) SRSS_PWR_HIB_WAKE_CTL2;
906 #else
907 uint32_t clearWakeupSourceMask = wakeupSource & (uint32_t) ~SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk;
908
909 if (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, wakeupSource))
910 {
911 /* Clear the high active level of the requested sources */
912 if ((uint32_t) CY_SYSPM_HIBERNATE_LPCOMP0_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_LPCOMP0_HIGH))
913 {
914 clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
915 }
916
917 if ((uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH))
918 {
919 clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
920 }
921
922 if ((uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH))
923 {
924 clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
925 }
926
927 if ((uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH))
928 {
929 clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
930 }
931 }
932
933 SRSS_PWR_HIBERNATE &= (uint32_t) ~clearWakeupSourceMask;
934
935 /* Read register to make sure it is settled */
936 (void) SRSS_PWR_HIBERNATE;
937 #endif
938 }
939
940 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION == 3u) && defined (CY_IP_MXS40SRSS_VERSION_MINOR) && (CY_IP_MXS40SRSS_VERSION_MINOR >= 3u)
941 /* These functions are available for SRSSv3p3 and above. */
Cy_SysPm_GetHibernateWakeupCause(void)942 cy_en_syspm_hibernate_wakeup_source_t Cy_SysPm_GetHibernateWakeupCause(void)
943 {
944 cy_en_syspm_hibernate_wakeup_source_t wakeupSource = CY_SYSPM_HIBERNATE_NO_SRC;
945 uint32_t wakeupCause;
946 uint32_t wakeupCausePolarity;
947
948 wakeupCause = SRSS_PWR_HIB_WAKE_CAUSE;
949 wakeupCausePolarity = SRSS_PWR_HIB_WAKE_CTL2;
950
951 if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_CSV_BAK))
952 {
953 wakeupSource = CY_SYSPM_HIBERNATE_CSV_BAK;
954 }
955 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM))
956 {
957 wakeupSource = CY_SYSPM_HIBERNATE_RTC_ALARM;
958 }
959 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_WDT))
960 {
961 wakeupSource = CY_SYSPM_HIBERNATE_WDT;
962 }
963 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW))
964 {
965 if (0UL != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW))
966 {
967 wakeupSource = CY_SYSPM_HIBERNATE_PIN0_HIGH;
968 }
969 else
970 {
971 wakeupSource = CY_SYSPM_HIBERNATE_PIN0_LOW;
972 }
973 }
974 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW))
975 {
976 if (0UL != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW))
977 {
978 wakeupSource = CY_SYSPM_HIBERNATE_PIN1_HIGH;
979 }
980 else
981 {
982 wakeupSource = CY_SYSPM_HIBERNATE_PIN1_LOW;
983 }
984 }
985 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_PIN2_LOW))
986 {
987 if (0UL != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIBERNATE_PIN2_LOW))
988 {
989 wakeupSource = CY_SYSPM_HIBERNATE_PIN2_HIGH;
990 }
991 else
992 {
993 wakeupSource = CY_SYSPM_HIBERNATE_PIN2_LOW;
994 }
995 }
996 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_PIN3_LOW))
997 {
998 if (0UL != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIBERNATE_PIN3_LOW))
999 {
1000 wakeupSource = CY_SYSPM_HIBERNATE_PIN3_HIGH;
1001 }
1002 else
1003 {
1004 wakeupSource = CY_SYSPM_HIBERNATE_PIN3_LOW;
1005 }
1006 }
1007 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_PIN4_LOW))
1008 {
1009 if (0UL != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIBERNATE_PIN4_LOW))
1010 {
1011 wakeupSource = CY_SYSPM_HIBERNATE_PIN4_HIGH;
1012 }
1013 else
1014 {
1015 wakeupSource = CY_SYSPM_HIBERNATE_PIN4_LOW;
1016 }
1017 }
1018 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_PIN5_LOW))
1019 {
1020 if (0UL != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIBERNATE_PIN5_LOW))
1021 {
1022 wakeupSource = CY_SYSPM_HIBERNATE_PIN5_HIGH;
1023 }
1024 else
1025 {
1026 wakeupSource = CY_SYSPM_HIBERNATE_PIN5_LOW;
1027 }
1028 }
1029 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_PIN6_LOW))
1030 {
1031 if (0UL != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIBERNATE_PIN6_LOW))
1032 {
1033 wakeupSource = CY_SYSPM_HIBERNATE_PIN6_HIGH;
1034 }
1035 else
1036 {
1037 wakeupSource = CY_SYSPM_HIBERNATE_PIN6_LOW;
1038 }
1039 }
1040 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_PIN7_LOW))
1041 {
1042 if (0UL != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIBERNATE_PIN7_LOW))
1043 {
1044 wakeupSource = CY_SYSPM_HIBERNATE_PIN7_HIGH;
1045 }
1046 else
1047 {
1048 wakeupSource = CY_SYSPM_HIBERNATE_PIN7_LOW;
1049 }
1050 }
1051 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_PIN8_LOW))
1052 {
1053 if (0UL != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIBERNATE_PIN8_LOW))
1054 {
1055 wakeupSource = CY_SYSPM_HIBERNATE_PIN8_HIGH;
1056 }
1057 else
1058 {
1059 wakeupSource = CY_SYSPM_HIBERNATE_PIN8_LOW;
1060 }
1061 }
1062 else if (0UL != (wakeupCause & (uint32_t)CY_SYSPM_HIBERNATE_PIN9_LOW))
1063 {
1064 if (0UL != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIBERNATE_PIN9_LOW))
1065 {
1066 wakeupSource = CY_SYSPM_HIBERNATE_PIN9_HIGH;
1067 }
1068 else
1069 {
1070 wakeupSource = CY_SYSPM_HIBERNATE_PIN9_LOW;
1071 }
1072 }
1073 else
1074 {
1075 /* No wakeup source found */
1076 }
1077
1078 return wakeupSource;
1079 }
1080
Cy_SysPm_ClearHibernateWakeupCause(void)1081 void Cy_SysPm_ClearHibernateWakeupCause(void)
1082 {
1083 uint32_t temp = SRSS_PWR_HIB_WAKE_CAUSE;
1084 SRSS_PWR_HIB_WAKE_CAUSE = temp;
1085 }
1086 #endif
1087
Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t * handler)1088 bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler)
1089 {
1090 bool retVal = false;
1091
1092 /* Verify the input parameters. */
1093 if ((handler != NULL) && (handler->callbackParams != NULL) && (handler->callback != NULL))
1094 {
1095 uint32_t callbackRootIdx = (uint32_t) handler->type;
1096
1097 /* If the callback list is not empty. */
1098 if (pmCallbackRoot[callbackRootIdx] != NULL)
1099 {
1100 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
1101 cy_stc_syspm_callback_t* insertPos = curCallback;
1102
1103 /* Find the callback after which the new callback is to be
1104 * inserted. Ensure the given callback has not been registered.
1105 */
1106 while ((NULL != curCallback->nextItm) && (curCallback != handler))
1107 {
1108 curCallback = curCallback->nextItm;
1109 /* Callbacks with the same order value are stored in the order
1110 * they are registered.
1111 */
1112 if (curCallback->order <= handler->order)
1113 {
1114 insertPos = curCallback;
1115 }
1116 }
1117 /* If the callback has not been registered. */
1118 if (curCallback != handler)
1119 {
1120 /* If the callback is to be inserted at the beginning of the list. */
1121 if ((insertPos->prevItm == NULL) && (handler->order < insertPos->order))
1122 {
1123 handler->nextItm = insertPos;
1124 handler->prevItm = NULL;
1125 handler->nextItm->prevItm = handler;
1126 pmCallbackRoot[callbackRootIdx] = handler;
1127 }
1128 else
1129 {
1130 handler->nextItm = insertPos->nextItm;
1131 handler->prevItm = insertPos;
1132
1133 /* If the callback is not inserted at the end of the list. */
1134 if (handler->nextItm != NULL)
1135 {
1136 handler->nextItm->prevItm = handler;
1137 }
1138 insertPos->nextItm = handler;
1139 }
1140 retVal = true;
1141 }
1142 }
1143 else
1144 {
1145 /* The callback list is empty. */
1146 pmCallbackRoot[callbackRootIdx] = handler;
1147 handler->nextItm = NULL;
1148 handler->prevItm = NULL;
1149 retVal = true;
1150 }
1151 }
1152 return retVal;
1153 }
1154
Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const * handler)1155 bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler)
1156 {
1157 bool retVal = false;
1158
1159 if (handler != NULL)
1160 {
1161 uint32_t callbackRootIdx = (uint32_t) handler->type;
1162 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
1163
1164 /* Search requested callback item in the linked list */
1165 while (curCallback != NULL)
1166 {
1167 /* Requested callback is found */
1168 if (curCallback == handler)
1169 {
1170 retVal = true;
1171 break;
1172 }
1173
1174 /* Go to next callback item in the linked list */
1175 curCallback = curCallback->nextItm;
1176 }
1177
1178 if (retVal)
1179 {
1180 /* Requested callback is first in the list */
1181 if (pmCallbackRoot[callbackRootIdx] == handler)
1182 {
1183 /* Check whether this the only callback registered */
1184 if (pmCallbackRoot[callbackRootIdx]->nextItm != NULL)
1185 {
1186 pmCallbackRoot[callbackRootIdx] = pmCallbackRoot[callbackRootIdx]->nextItm;
1187 pmCallbackRoot[callbackRootIdx]->prevItm = NULL;
1188 }
1189 else
1190 {
1191 /* We had only one callback */
1192 pmCallbackRoot[callbackRootIdx] = NULL;
1193 }
1194 }
1195 else
1196 {
1197 /* Update links of related to unregistered callback items */
1198 curCallback->prevItm->nextItm = curCallback->nextItm;
1199
1200 if (curCallback->nextItm != NULL)
1201 {
1202 curCallback->nextItm->prevItm = curCallback->prevItm;
1203 }
1204 }
1205 }
1206 }
1207
1208 return retVal;
1209 }
1210
Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type,cy_en_syspm_callback_mode_t mode)1211 cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode)
1212 {
1213 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type));
1214 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode));
1215
1216 static cy_stc_syspm_callback_t* lastExecutedCallback = NULL;
1217 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
1218 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[(uint32_t) type];
1219 cy_stc_syspm_callback_params_t curParams;
1220
1221 if ((mode == CY_SYSPM_BEFORE_TRANSITION) || (mode == CY_SYSPM_CHECK_READY))
1222 {
1223 /* Execute registered callbacks with order from first registered to the
1224 * last registered. Stop executing if CY_SYSPM_FAIL was returned in
1225 * CY_SYSPM_CHECK_READY mode
1226 */
1227 while ((curCallback != NULL) && ((retVal != CY_SYSPM_FAIL) || (mode != CY_SYSPM_CHECK_READY)))
1228 {
1229 /* The modes defined in the .skipMode element are not executed */
1230 if (0UL == ((uint32_t) mode & curCallback->skipMode))
1231 {
1232 /* Update elements for local callback parameter values */
1233 curParams.base = curCallback->callbackParams->base;
1234 curParams.context = curCallback->callbackParams->context;
1235
1236 retVal = curCallback->callback(&curParams, mode);
1237
1238 /* Update callback pointer with value of executed callback.
1239 * Such update is required to execute further callbacks in
1240 * backward order after exit from LP mode or to undo
1241 * configuration after callback returned fail: from last called
1242 * to first registered.
1243 */
1244 lastExecutedCallback = curCallback;
1245 }
1246 curCallback = curCallback->nextItm;
1247 }
1248
1249 if (mode == CY_SYSPM_CHECK_READY)
1250 {
1251 /* Update the pointer to the failed callback with the result of the callback execution.
1252 * If the callback fails, the value of the pointer will be updated
1253 * with the address of the callback which returned CY_SYSPM_FAIL, else,
1254 * it will be updated with NULL.
1255 */
1256 if(retVal == CY_SYSPM_FAIL)
1257 {
1258 failedCallback[(uint32_t) type] = lastExecutedCallback;
1259 }
1260 else
1261 {
1262 failedCallback[(uint32_t) type] = NULL;
1263 }
1264 }
1265 }
1266 else
1267 {
1268 /* Execute registered callbacks with order from lastCallback or last
1269 * executed to the first registered callback. Such a flow is required if
1270 * a previous callback function returned CY_SYSPM_FAIL or a previous
1271 * callback mode was CY_SYSPM_BEFORE_TRANSITION. Such an order is
1272 * required to undo configurations in correct backward order.
1273 */
1274 if (mode != CY_SYSPM_CHECK_FAIL)
1275 {
1276 while (curCallback->nextItm != NULL)
1277 {
1278 curCallback = curCallback->nextItm;
1279 }
1280 }
1281 else
1282 {
1283 /* Skip last executed callback that returns CY_SYSPM_FAIL, as this
1284 * callback already knows that it failed.
1285 */
1286 curCallback = lastExecutedCallback;
1287
1288 if (curCallback != NULL)
1289 {
1290 curCallback = curCallback->prevItm;
1291 }
1292 }
1293
1294 /* Execute callback functions with required type and mode */
1295 while (curCallback != NULL)
1296 {
1297 /* The modes defined in the .skipMode element are not executed */
1298 if (0UL == ((uint32_t) mode & curCallback->skipMode))
1299 {
1300 /* Update elements for local callback parameter values */
1301 curParams.base = curCallback->callbackParams->base;
1302 curParams.context = curCallback->callbackParams->context;
1303
1304 retVal = curCallback->callback(&curParams, mode);
1305 }
1306 curCallback = curCallback->prevItm;
1307 }
1308 }
1309
1310 return retVal;
1311 }
1312
Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type)1313 cy_stc_syspm_callback_t* Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type)
1314 {
1315 return failedCallback[(uint32_t) type];
1316 }
1317
1318 /*******************************************************************************
1319 * Function Name: Cy_SysPm_IoFreeze
1320 ****************************************************************************//**
1321 *
1322 * Freezes IOs.
1323 *
1324 * Freezes the IO cells directly to save the IO-cell state on a wakeup from the
1325 * Hibernate. Do not call this function before entering the
1326 * Hibernate mode, because Cy_SysPm_Hibernate() function freezes the IO cells.
1327 *
1328 ******************************************************************************/
Cy_SysPm_IoFreeze(void)1329 void Cy_SysPm_IoFreeze(void)
1330 {
1331 uint32_t interruptState;
1332 uint32_t regValue;
1333
1334 interruptState = Cy_SysLib_EnterCriticalSection();
1335
1336 /* Check the FREEZE state to avoid a recurrent IO-cells freeze attempt,
1337 * because the second call to this function will cause an accidental switch
1338 * to the hibernate mode (the system will enter the hibernate mode immediately
1339 * after writing to the hibernate bit because both UNLOCK and FREEZE were set
1340 * correctly in the previous call to this function).
1341 */
1342 if(!Cy_SysPm_IoIsFrozen())
1343 {
1344 /* Clear the unlock field for correct freeze of the IO cells */
1345 SRSS_PWR_HIBERNATE = _CLR_SET_FLD32U((SRSS_PWR_HIBERNATE), SRSS_PWR_HIBERNATE_UNLOCK, 0u);
1346
1347 /* Disable overriding by the peripherals the next pin-freeze command */
1348 SRSS_PWR_HIBERNATE |= CY_SYSPM_PWR_HIBERNATE_UNLOCK |
1349 _VAL2FLD(SRSS_PWR_HIBERNATE_FREEZE, 1u) |
1350 _VAL2FLD(SRSS_PWR_HIBERNATE_HIBERNATE, 1u);
1351
1352 /* If Read is after Write, read this register two times to delay
1353 * enough time for internal settling.
1354 */
1355 (void) SRSS_PWR_HIBERNATE;
1356 (void) SRSS_PWR_HIBERNATE;
1357
1358 /* The second Write causes freeze of IO cells to save the IO-cell state */
1359 regValue = SRSS_PWR_HIBERNATE;
1360 SRSS_PWR_HIBERNATE = regValue;
1361 }
1362 Cy_SysLib_ExitCriticalSection(interruptState);
1363 }
1364
Cy_SysPm_IoUnfreeze(void)1365 void Cy_SysPm_IoUnfreeze(void)
1366 {
1367 uint32_t interruptState;
1368 interruptState = Cy_SysLib_EnterCriticalSection();
1369
1370 /* Preserve the last reset reason and wakeup polarity. Then, unfreeze I/O:
1371 * write PWR_HIBERNATE.FREEZE=0, .UNLOCK=0x3A, .HIBERANTE=0
1372 */
1373 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_RETAIN_STATUS_MASK) | HIBERNATE_UNLOCK_VAL;
1374
1375 /* Lock the Hibernate mode:
1376 * write PWR_HIBERNATE.HIBERNATE=0, UNLOCK=0x00, HIBERANTE=0
1377 */
1378 SRSS_PWR_HIBERNATE &= HIBERNATE_RETAIN_STATUS_MASK;
1379
1380 /* Read register to make sure it is settled */
1381 (void) SRSS_PWR_HIBERNATE;
1382
1383 Cy_SysLib_ExitCriticalSection(interruptState);
1384 }
1385
Cy_SysPm_IoIsFrozen(void)1386 bool Cy_SysPm_IoIsFrozen(void)
1387 {
1388 return (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_FREEZE, SRSS_PWR_HIBERNATE));
1389 }
1390
Cy_SysPm_CpuSendWakeupEvent(void)1391 void Cy_SysPm_CpuSendWakeupEvent(void)
1392 {
1393 __SEV();
1394 }
1395
Cy_SysPm_IsLpmReady(void)1396 bool Cy_SysPm_IsLpmReady(void)
1397 {
1398 return (_FLD2BOOL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL)? true : false);
1399 }
1400
Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl)1401 void Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl)
1402 {
1403 CY_UNUSED_PARAMETER(vddBackControl);
1404
1405 #if (SRSS_BACKUP_VBCK_PRESENT)
1406 CY_ASSERT_L3(CY_SYSPM_IS_VDDBACKUP_VALID(vddBackControl));
1407
1408 BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_VDDBAK_CTL, (uint32_t) vddBackControl);
1409 #endif
1410 }
1411
1412
Cy_SysPm_BackupGetSupply(void)1413 cy_en_syspm_vddbackup_control_t Cy_SysPm_BackupGetSupply(void)
1414 {
1415 #if (SRSS_BACKUP_VBCK_PRESENT)
1416 uint32_t retVal;
1417 retVal = _FLD2VAL(BACKUP_CTL_VDDBAK_CTL, BACKUP_CTL);
1418
1419 return ((cy_en_syspm_vddbackup_control_t) retVal);
1420 #else
1421 return (CY_SYSPM_VDDBACKUP_DEFAULT);
1422 #endif
1423 }
1424
1425
Cy_SysPm_BackupEnableVoltageMeasurement(void)1426 void Cy_SysPm_BackupEnableVoltageMeasurement(void)
1427 {
1428 #if (SRSS_BACKUP_VBCK_PRESENT)
1429 BACKUP_CTL |= BACKUP_CTL_VBACKUP_MEAS_Msk;
1430 #endif
1431 }
1432
1433
Cy_SysPm_BackupDisableVoltageMeasurement(void)1434 void Cy_SysPm_BackupDisableVoltageMeasurement(void)
1435 {
1436 /* The MXS40SRSSv2 does have VBCK present, but is not compatible with the VBACKUP_MEAS register bit. */
1437 #if (SRSS_BACKUP_VBCK_PRESENT && (CY_IP_MXS40SRSS_VERSION != 2u))
1438 BACKUP_CTL &= ((uint32_t) ~BACKUP_CTL_VBACKUP_MEAS_Msk);
1439 #endif
1440 }
1441
1442
Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key)1443 void Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key)
1444 {
1445 CY_UNUSED_PARAMETER(key);
1446
1447 #if (SRSS_BACKUP_VBCK_PRESENT)
1448 CY_ASSERT_L3(CY_SYSPM_IS_SC_CHARGE_KEY_VALID(key));
1449
1450 if(key == CY_SYSPM_SC_CHARGE_ENABLE)
1451 {
1452 BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_EN_CHARGE_KEY, (uint32_t) CY_SYSPM_SC_CHARGE_ENABLE);
1453 }
1454 else
1455 {
1456 BACKUP_CTL &= ((uint32_t) ~BACKUP_CTL_EN_CHARGE_KEY_Msk);
1457 }
1458 #endif
1459 }
1460
1461 /* These functions are only available for devices that contain the SRSS_BACKUP IP. */
1462 #if defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (defined (SRSS_BACKUP_PRESENT) && (SRSS_BACKUP_PRESENT == 1u)))
Cy_SysPm_BackupWordStore(uint32_t wordIndex,uint32_t * wordSrcPointer,uint32_t wordSize)1463 void Cy_SysPm_BackupWordStore(uint32_t wordIndex, uint32_t *wordSrcPointer, uint32_t wordSize)
1464 {
1465 CY_ASSERT_L3(CY_SYSPM_IS_WORD_INDEX_VALID(wordIndex));
1466 CY_ASSERT_L3(CY_SYSPM_IS_WORD_SIZE_VALID(wordSize + wordIndex));
1467
1468 while(wordSize != 0UL)
1469 {
1470 BACKUP_BREG[wordIndex] = *wordSrcPointer;
1471
1472 wordIndex++;
1473 wordSrcPointer++;
1474 wordSize--;
1475 }
1476 }
1477
Cy_SysPm_BackupWordReStore(uint32_t wordIndex,uint32_t * wordDstPointer,uint32_t wordSize)1478 void Cy_SysPm_BackupWordReStore(uint32_t wordIndex, uint32_t *wordDstPointer, uint32_t wordSize)
1479 {
1480 CY_ASSERT_L3(CY_SYSPM_IS_WORD_INDEX_VALID(wordIndex));
1481 CY_ASSERT_L3(CY_SYSPM_IS_WORD_SIZE_VALID(wordSize + wordIndex));
1482
1483 while(wordSize != 0UL)
1484 {
1485 *wordDstPointer = BACKUP_BREG[wordIndex];
1486
1487 wordIndex++;
1488 wordDstPointer++;
1489 wordSize--;
1490 }
1491 }
1492 #endif /* defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (defined (SRSS_BACKUP_PRESENT) && (SRSS_BACKUP_PRESENT == 1u))) */
1493
Cy_SysPm_SetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)1494 cy_en_syspm_status_t Cy_SysPm_SetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
1495 {
1496 cy_en_syspm_status_t status = CY_SYSPM_BAD_PARAM;
1497
1498 CY_ASSERT_L1( sramNum < CPUSS_SRAM_COUNT );
1499
1500 if(sramNum == CY_SYSPM_SRAM0_MEMORY)
1501 {
1502 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR );
1503 if (sramMacroNum < CPUSS_RAMC0_MACRO_NR)
1504 {
1505 CPUSS_RAM0_PWR_MACRO_CTL(sramMacroNum) = _VAL2FLD(CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1506 _VAL2FLD(CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE, sramPwrMode);
1507 status = CY_SYSPM_SUCCESS;
1508 }
1509 }
1510 else if(sramNum == CY_SYSPM_SRAM1_MEMORY)
1511 {
1512 CY_ASSERT_L1( CPUSS_RAMC1_PRESENT );
1513 CY_ASSERT_L1( sramMacroNum == 0UL );
1514
1515 CPUSS_RAM1_PWR_CTL = _VAL2FLD(CPUSS_RAM1_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1516 _VAL2FLD(CPUSS_RAM1_PWR_CTL_PWR_MODE, sramPwrMode);
1517 status = CY_SYSPM_SUCCESS;
1518 }
1519 else if(sramNum == CY_SYSPM_SRAM2_MEMORY)
1520 {
1521 CY_ASSERT_L1( CPUSS_RAMC2_PRESENT );
1522 CY_ASSERT_L1( sramMacroNum == 0UL );
1523
1524 CPUSS_RAM2_PWR_CTL = _VAL2FLD(CPUSS_RAM2_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1525 _VAL2FLD(CPUSS_RAM2_PWR_CTL_PWR_MODE, sramPwrMode);
1526 status = CY_SYSPM_SUCCESS;
1527 }
1528 else
1529 {
1530 /* Invalid SRAM Number */
1531 }
1532
1533 return status;
1534 }
1535
1536
Cy_SysPm_GetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum)1537 cy_en_syspm_sram_pwr_mode_t Cy_SysPm_GetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum)
1538 {
1539 uint32_t retVal = (uint32_t)CY_SYSPM_SRAM_PWR_MODE_INVALID;
1540
1541 CY_ASSERT_L1( sramNum < CPUSS_SRAM_COUNT );
1542
1543 if(sramNum == CY_SYSPM_SRAM0_MEMORY)
1544 {
1545 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR );
1546 if (sramMacroNum < CPUSS_RAMC0_MACRO_NR)
1547 {
1548 retVal = _FLD2VAL(CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE, CPUSS_RAM0_PWR_MACRO_CTL(sramMacroNum));
1549 }
1550 }
1551 else if(sramNum == CY_SYSPM_SRAM1_MEMORY)
1552 {
1553 CY_ASSERT_L1( sramMacroNum == 0UL );
1554 retVal = _FLD2VAL(CPUSS_RAM1_PWR_CTL_PWR_MODE, CPUSS_RAM1_PWR_CTL);
1555 }
1556 else if(sramNum == CY_SYSPM_SRAM2_MEMORY)
1557 {
1558 CY_ASSERT_L1( sramMacroNum == 0UL );
1559 retVal = _FLD2VAL(CPUSS_RAM2_PWR_CTL_PWR_MODE, CPUSS_RAM2_PWR_CTL);
1560 }
1561 else
1562 {
1563 /* Invalid SRAM Number */
1564 }
1565 return (cy_en_syspm_sram_pwr_mode_t)retVal;
1566 }
1567
1568
Cy_SysPm_SetSRAMPwrMode(cy_en_syspm_sram_index_t sramNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)1569 cy_en_syspm_status_t Cy_SysPm_SetSRAMPwrMode(cy_en_syspm_sram_index_t sramNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
1570 {
1571 uint32 idx;
1572
1573 cy_en_syspm_status_t status = CY_SYSPM_BAD_PARAM;
1574 CY_ASSERT_L1( sramNum < CPUSS_SRAM_COUNT );
1575
1576 if(sramNum == CY_SYSPM_SRAM0_MEMORY)
1577 {
1578 for(idx = 0UL; idx < CPUSS_RAMC0_MACRO_NR; idx++)
1579 {
1580 CPUSS_RAM0_PWR_MACRO_CTL(idx) = _VAL2FLD(CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1581 _VAL2FLD(CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE, sramPwrMode);
1582 }
1583 status = CY_SYSPM_SUCCESS;
1584 }
1585 else if(sramNum == CY_SYSPM_SRAM1_MEMORY)
1586 {
1587 CY_ASSERT_L1( CPUSS_RAMC1_PRESENT );
1588 CPUSS_RAM1_PWR_CTL = _VAL2FLD(CPUSS_RAM1_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1589 _VAL2FLD(CPUSS_RAM1_PWR_CTL_PWR_MODE, sramPwrMode);
1590 status = CY_SYSPM_SUCCESS;
1591
1592 }
1593 else if(sramNum == CY_SYSPM_SRAM2_MEMORY)
1594 {
1595 CY_ASSERT_L1( CPUSS_RAMC2_PRESENT );
1596 CPUSS_RAM2_PWR_CTL = _VAL2FLD(CPUSS_RAM2_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1597 _VAL2FLD(CPUSS_RAM2_PWR_CTL_PWR_MODE, sramPwrMode);
1598 status = CY_SYSPM_SUCCESS;
1599
1600 }
1601 else
1602 {
1603 /* Invalid SRAM Number */
1604 }
1605
1606 return status;
1607 }
1608
1609
1610 /*******************************************************************************
1611 * Function Name: Cy_SysPm_ReadStatus
1612 ****************************************************************************//**
1613 *
1614 * Reads the status of the core(s).
1615 *
1616 * \return The current power mode. See \ref group_syspm_return_status.
1617 *
1618 *******************************************************************************/
Cy_SysPm_ReadStatus(void)1619 uint32_t Cy_SysPm_ReadStatus(void)
1620 {
1621 uint32_t interruptState;
1622 uint32_t pmStatus = 0u;
1623 interruptState = Cy_SysLib_EnterCriticalSection();
1624
1625 #if defined (CY_CPU_CORTEX_M7) && (CY_CPU_CORTEX_M7)
1626 /* Check whether CM7_0 is in the deep sleep mode*/
1627 if((0u != _FLD2VAL(CPUSS_CM7_0_STATUS_SLEEPING, CPUSS_CM7_0_STATUS)) &&
1628 (0u != _FLD2VAL(CPUSS_CM7_0_STATUS_SLEEPDEEP, CPUSS_CM7_0_STATUS)))
1629 {
1630 pmStatus |= CY_SYSPM_STATUS_CM7_0_DEEPSLEEP;
1631 }
1632 /* Check whether CM7_0 is in the sleep mode*/
1633 else if(0u != _FLD2VAL(CPUSS_CM7_0_STATUS_SLEEPING, CPUSS_CM7_0_STATUS))
1634 {
1635 pmStatus |= CY_SYSPM_STATUS_CM7_0_SLEEP;
1636 }
1637 else
1638 {
1639 pmStatus |= CY_SYSPM_STATUS_CM7_0_ACTIVE;
1640 }
1641
1642 /* Check whether CM7_1 is in the deep sleep mode*/
1643 if((0u != _FLD2VAL(CPUSS_CM7_1_STATUS_SLEEPING, CPUSS_CM7_1_STATUS)) &&
1644 (0u != _FLD2VAL(CPUSS_CM7_1_STATUS_SLEEPDEEP, CPUSS_CM7_1_STATUS)))
1645 {
1646 pmStatus |= CY_SYSPM_STATUS_CM7_1_DEEPSLEEP;
1647 }
1648 /* Check whether CM7_1 is in the sleep mode*/
1649 else if(0u != _FLD2VAL(CPUSS_CM7_1_STATUS_SLEEPING, CPUSS_CM7_1_STATUS))
1650 {
1651 pmStatus |= CY_SYSPM_STATUS_CM7_1_SLEEP;
1652 }
1653 else
1654 {
1655 pmStatus |= CY_SYSPM_STATUS_CM7_1_ACTIVE;
1656 }
1657 #elif defined (CY_CPU_CORTEX_M4) && (CY_CPU_CORTEX_M4)
1658 /* Check whether CM4 is in Deep Sleep mode */
1659 if ((CPUSS_CM4_STATUS & CM4_DEEPSLEEP_MASK) == CM4_DEEPSLEEP_MASK)
1660 {
1661 pmStatus |= CY_SYSPM_STATUS_CM4_DEEPSLEEP;
1662 }
1663 /* Check whether CM4 is in Sleep mode */
1664 else if(0U != _FLD2VAL(CPUSS_CM4_STATUS_SLEEPING, CPUSS_CM4_STATUS))
1665 {
1666 pmStatus |= CY_SYSPM_STATUS_CM4_SLEEP;
1667 }
1668 else
1669 {
1670 pmStatus |= CY_SYSPM_STATUS_CM4_ACTIVE;
1671 }
1672 #endif
1673
1674
1675 /* Check whether CM0p is in the sleep or deep sleep mode*/
1676 if (0u != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPING, CPUSS_CM0_STATUS))
1677 {
1678 if (0u != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPDEEP, CPUSS_CM0_STATUS))
1679 {
1680 pmStatus |= (uint32_t) CY_SYSPM_STATUS_CM0_DEEPSLEEP;
1681 }
1682 else
1683 {
1684 pmStatus |= (uint32_t) CY_SYSPM_STATUS_CM0_SLEEP;
1685 }
1686 }
1687 else
1688 {
1689 pmStatus |= (uint32_t) CY_SYSPM_STATUS_CM0_ACTIVE;
1690 }
1691
1692 /* Check whether the device is in LPACTIVE mode or not */
1693 if(Cy_SysPm_IsSystemLpActiveEnabled())
1694 {
1695 pmStatus |= (uint32_t) CY_SYSPM_STATUS_SYSTEM_LOWPOWER;
1696 }
1697
1698 Cy_SysLib_ExitCriticalSection(interruptState);
1699
1700 return(pmStatus);
1701 }
1702
1703 #if defined(CY_IP_M7CPUSS) && (CY_IP_M7CPUSS == 1u)
Cy_SysPm_Cm7IsActive(uint8_t core)1704 bool Cy_SysPm_Cm7IsActive(uint8_t core)
1705 {
1706 bool status = false;
1707
1708 if(core == CORE_CM7_0)
1709 {
1710 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_0_ACTIVE) != 0u);
1711 }
1712 else if(core == CORE_CM7_1)
1713 {
1714 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_1_ACTIVE) != 0u);
1715 }
1716 else
1717 {
1718 /* CM7 Not active */
1719 }
1720
1721 return status;
1722 }
1723
Cy_SysPm_Cm7IsSleep(uint8_t core)1724 bool Cy_SysPm_Cm7IsSleep(uint8_t core)
1725 {
1726 bool status = false;
1727
1728 if(core == CORE_CM7_0)
1729 {
1730 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_0_SLEEP) != 0u);
1731 }
1732 else if(core == CORE_CM7_1)
1733 {
1734 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_1_SLEEP) != 0u);
1735 }
1736 else
1737 {
1738 /* CM7 Not active */
1739 }
1740
1741 return status;
1742 }
1743
Cy_SysPm_Cm7IsDeepSleep(uint8_t core)1744 bool Cy_SysPm_Cm7IsDeepSleep(uint8_t core)
1745 {
1746 bool status = false;
1747
1748 if(core == CORE_CM7_0)
1749 {
1750 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_0_DEEPSLEEP) != 0u);
1751 }
1752 else if(core == CORE_CM7_1)
1753 {
1754 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_1_DEEPSLEEP) != 0u);
1755 }
1756 else
1757 {
1758 /* CM7 Not active */
1759 }
1760
1761 return status;
1762 }
1763
1764
1765 #endif // defined(CY_IP_M7CPUSS) && (CY_IP_M7CPUSS == 1u)
1766
1767 #if defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS == 1u)
Cy_SysPm_Cm4IsActive(void)1768 bool Cy_SysPm_Cm4IsActive(void)
1769 {
1770 return ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_ACTIVE) != 0U);
1771 }
1772
1773
Cy_SysPm_Cm4IsSleep(void)1774 bool Cy_SysPm_Cm4IsSleep(void)
1775 {
1776 return ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_SLEEP) != 0U);
1777 }
1778
1779
Cy_SysPm_Cm4IsDeepSleep(void)1780 bool Cy_SysPm_Cm4IsDeepSleep(void)
1781 {
1782 return ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_DEEPSLEEP) != 0U);
1783 }
1784
1785 #endif // defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS == 1u)
1786
Cy_SysPm_Cm0IsActive(void)1787 bool Cy_SysPm_Cm0IsActive(void)
1788 {
1789 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_ACTIVE) != 0u);
1790 }
1791
Cy_SysPm_Cm0IsSleep(void)1792 bool Cy_SysPm_Cm0IsSleep(void)
1793 {
1794 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_SLEEP) != 0u);
1795 }
1796
Cy_SysPm_Cm0IsDeepSleep(void)1797 bool Cy_SysPm_Cm0IsDeepSleep(void)
1798 {
1799 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_DEEPSLEEP) != 0u);
1800 }
1801
Cy_SysPm_IsSystemLp(void)1802 bool Cy_SysPm_IsSystemLp(void)
1803 {
1804 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_LOWPOWER) != 0u);
1805 }
1806
1807 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2u)) || \
1808 ((defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2u)) && (defined (SRSS_BACKUP_VBCK_PRESENT) && (SRSS_BACKUP_VBCK_PRESENT == 1u)))
Cy_SysPm_PmicEnable(void)1809 void Cy_SysPm_PmicEnable(void)
1810 {
1811 if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
1812 {
1813 BACKUP_PMIC_CTL =
1814 _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) |
1815 _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1u) |
1816 _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1u);
1817 }
1818 }
1819
1820
Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity)1821 void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity)
1822 {
1823 if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
1824 {
1825 BACKUP_PMIC_CTL =
1826 (_VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) |
1827 _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_POLARITY, polarity)) &
1828 ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1u));
1829 }
1830 }
1831
1832
Cy_SysPm_PmicAlwaysEnable(void)1833 void Cy_SysPm_PmicAlwaysEnable(void)
1834 {
1835 BACKUP_PMIC_CTL |= _VAL2FLD(BACKUP_PMIC_CTL_PMIC_ALWAYSEN, 1u);
1836 }
1837
1838
Cy_SysPm_PmicEnableOutput(void)1839 void Cy_SysPm_PmicEnableOutput(void)
1840 {
1841 if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
1842 {
1843 BACKUP_PMIC_CTL |=
1844 _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) | _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1u);
1845 }
1846 }
1847
1848
Cy_SysPm_PmicDisableOutput(void)1849 void Cy_SysPm_PmicDisableOutput(void)
1850 {
1851 if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
1852 {
1853 BACKUP_PMIC_CTL =
1854 (BACKUP_PMIC_CTL | _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY)) &
1855 ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1u));
1856 }
1857 }
1858
1859
Cy_SysPm_PmicLock(void)1860 void Cy_SysPm_PmicLock(void)
1861 {
1862 BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, 0u);
1863 }
1864
1865
Cy_SysPm_PmicUnlock(void)1866 void Cy_SysPm_PmicUnlock(void)
1867 {
1868 BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY);
1869 }
1870
1871
Cy_SysPm_PmicIsEnabled(void)1872 bool Cy_SysPm_PmicIsEnabled(void)
1873 {
1874 return(0u != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN, BACKUP_PMIC_CTL));
1875 }
1876
1877
Cy_SysPm_PmicIsOutputEnabled(void)1878 bool Cy_SysPm_PmicIsOutputEnabled(void)
1879 {
1880 return (0U != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, BACKUP_PMIC_CTL));
1881 }
1882
1883
Cy_SysPm_PmicIsLocked(void)1884 bool Cy_SysPm_PmicIsLocked(void)
1885 {
1886 return((_FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL) == CY_SYSPM_PMIC_UNLOCK_KEY) ? false : true);
1887 }
1888 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2u)) || \
1889 ((defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2u)) && (defined (SRSS_BACKUP_VBCK_PRESENT) && (SRSS_BACKUP_VBCK_PRESENT == 1u))) */
1890
Cy_SysPm_OvdEnable(cy_en_syspm_ovd_sel_t ovdSel)1891 void Cy_SysPm_OvdEnable(cy_en_syspm_ovd_sel_t ovdSel)
1892 {
1893 switch(ovdSel)
1894 {
1895 case CY_SYSPM_OVD_ON_VDDD:
1896 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk;
1897 break;
1898
1899 case CY_SYSPM_OVD_ON_VDDA:
1900 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk;
1901 break;
1902
1903 case CY_SYSPM_OVD_ON_VCCD:
1904 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk;
1905 break;
1906
1907 default:
1908 (void)SRSS_PWR_SSV_STATUS; /* To Fix Coverity */
1909 break;
1910 }
1911 }
1912
1913
Cy_SysPm_OvdDisable(cy_en_syspm_ovd_sel_t ovdSel)1914 void Cy_SysPm_OvdDisable(cy_en_syspm_ovd_sel_t ovdSel)
1915 {
1916 switch(ovdSel)
1917 {
1918 case CY_SYSPM_OVD_ON_VDDD:
1919 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk;
1920 break;
1921
1922 case CY_SYSPM_OVD_ON_VDDA:
1923 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk;
1924 break;
1925
1926 case CY_SYSPM_OVD_ON_VCCD:
1927 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk;
1928 break;
1929
1930 default:
1931 (void)SRSS_PWR_SSV_STATUS; /* To Fix Coverity */
1932 break;
1933 }
1934 }
1935
1936
Cy_SysPm_OvdVdddSelect(cy_en_syspm_ovd_vddd_sel_t ovdVdddSel)1937 void Cy_SysPm_OvdVdddSelect(cy_en_syspm_ovd_vddd_sel_t ovdVdddSel)
1938 {
1939 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_OVDVDDD_VSEL, ovdVdddSel);
1940 }
1941
1942
Cy_SysPm_OvdVddaSelect(cy_en_syspm_ovd_vdda_sel_t ovdVddaSel)1943 void Cy_SysPm_OvdVddaSelect(cy_en_syspm_ovd_vdda_sel_t ovdVddaSel)
1944 {
1945 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_OVDVDDA_VSEL, ovdVddaSel);
1946 }
1947
1948
Cy_SysPm_OvdActionSelect(cy_en_syspm_ovd_action_select_t ovdActionSelect)1949 void Cy_SysPm_OvdActionSelect(cy_en_syspm_ovd_action_select_t ovdActionSelect)
1950 {
1951 CY_ASSERT(CY_OVD_CHECK_ACTION_CFG(ovdActionSelect));
1952
1953 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_OVDVDDA_ACTION, ovdActionSelect);
1954 }
1955
1956
Cy_SysPm_BodEnable(cy_en_syspm_bod_sel_t bodSel)1957 void Cy_SysPm_BodEnable(cy_en_syspm_bod_sel_t bodSel)
1958 {
1959 switch(bodSel)
1960 {
1961 case CY_SYSPM_BOD_ON_VDDD:
1962 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk;
1963 break;
1964
1965 case CY_SYSPM_BOD_ON_VDDA:
1966 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk;
1967 break;
1968
1969 case CY_SYSPM_BOD_ON_VCCD:
1970 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk;
1971 break;
1972
1973 default:
1974 (void)SRSS_PWR_SSV_STATUS; /* To Fix Coverity */
1975 break;
1976 }
1977 }
1978
1979
Cy_SysPm_BodDisable(cy_en_syspm_bod_sel_t bodSel)1980 void Cy_SysPm_BodDisable(cy_en_syspm_bod_sel_t bodSel)
1981 {
1982 switch(bodSel)
1983 {
1984 case CY_SYSPM_BOD_ON_VDDD:
1985 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk;
1986 break;
1987
1988 case CY_SYSPM_BOD_ON_VDDA:
1989 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk;
1990 break;
1991
1992 case CY_SYSPM_BOD_ON_VCCD:
1993 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk;
1994 break;
1995
1996 default:
1997 (void)SRSS_PWR_SSV_STATUS; /* To Fix Coverity */
1998 break;
1999 }
2000 }
2001
2002
Cy_SysPm_BodVdddSelect(cy_en_syspm_bod_vddd_sel_t bodVdddSel)2003 void Cy_SysPm_BodVdddSelect(cy_en_syspm_bod_vddd_sel_t bodVdddSel)
2004 {
2005 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_BODVDDD_VSEL, bodVdddSel);
2006 }
2007
2008
Cy_SysPm_BodVddaSelect(cy_en_syspm_bod_vdda_sel_t bodVddaSel)2009 void Cy_SysPm_BodVddaSelect(cy_en_syspm_bod_vdda_sel_t bodVddaSel)
2010 {
2011 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_BODVDDA_VSEL, bodVddaSel);
2012 }
2013
2014
Cy_SysPm_BodActionSelect(cy_en_syspm_bod_action_select_t bodActionSelect)2015 void Cy_SysPm_BodActionSelect(cy_en_syspm_bod_action_select_t bodActionSelect)
2016 {
2017 CY_ASSERT(CY_BOD_CHECK_ACTION_CFG(bodActionSelect));
2018
2019 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_BODVDDA_ACTION, bodActionSelect);
2020 }
2021
2022
Cy_SysPm_SupplySupervisionStatus(cy_en_syspm_supply_entity_select_t supplyEntitySelect)2023 bool Cy_SysPm_SupplySupervisionStatus(cy_en_syspm_supply_entity_select_t supplyEntitySelect)
2024 {
2025 bool returnStatus = false;
2026
2027 CY_ASSERT_L3(CY_OVD_CHECK_SUPPLY_ENTITY(supplyEntitySelect));
2028
2029 switch(supplyEntitySelect)
2030 {
2031 case CY_SYSPM_ENTITY_BOD_VDDD:
2032 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_BODVDDD_OK, SRSS_PWR_SSV_STATUS));
2033 break;
2034
2035 case CY_SYSPM_ENTITY_BOD_VDDA:
2036 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_BODVDDA_OK, SRSS_PWR_SSV_STATUS));
2037 break;
2038
2039 case CY_SYSPM_ENTITY_BOD_VCCD:
2040 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_BODVCCD_OK, SRSS_PWR_SSV_STATUS));
2041 break;
2042
2043 case CY_SYSPM_ENTITY_OVD_VDDD:
2044 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_OVDVDDD_OK, SRSS_PWR_SSV_STATUS));
2045 break;
2046
2047 case CY_SYSPM_ENTITY_OVD_VDDA:
2048 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_OVDVDDA_OK, SRSS_PWR_SSV_STATUS));
2049 break;
2050
2051 case CY_SYSPM_ENTITY_OVD_VCCD:
2052 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_OVDVCCD_OK, SRSS_PWR_SSV_STATUS));
2053 break;
2054
2055 default:
2056 (void)SRSS_PWR_SSV_STATUS; /* To Fix Coverity */
2057 break;
2058 }
2059
2060 return (returnStatus);
2061 }
2062
Cy_SysPm_SystemIsMinRegulatorCurrentSet(void)2063 bool Cy_SysPm_SystemIsMinRegulatorCurrentSet(void)
2064 {
2065 uint32_t regMask = Cy_SysPm_LdoIsEnabled() ? CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_LDO_MASK : CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_BUCK_MASK;
2066
2067 return ((SRSS_PWR_CTL & regMask) == regMask);
2068 }
2069
Cy_SysPm_LinearRegDisable(void)2070 void Cy_SysPm_LinearRegDisable(void)
2071 {
2072 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_LINREG_DIS_Msk;
2073 }
2074
Cy_SysPm_LinearRegEnable(void)2075 void Cy_SysPm_LinearRegEnable(void)
2076 {
2077 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_LINREG_DIS_Msk;
2078 }
2079
Cy_SysPm_LinearRegGetStatus(void)2080 bool Cy_SysPm_LinearRegGetStatus(void)
2081 {
2082 return (_FLD2BOOL(SRSS_PWR_CTL2_LINREG_OK, SRSS_PWR_CTL2));
2083 }
2084
Cy_SysPm_DeepSleepRegDisable(void)2085 void Cy_SysPm_DeepSleepRegDisable(void)
2086 {
2087 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk;
2088 }
2089
Cy_SysPm_DeepSleepRegEnable(void)2090 void Cy_SysPm_DeepSleepRegEnable(void)
2091 {
2092 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk;
2093 }
2094
Cy_SySPm_IsDeepSleepRegEnabled(void)2095 bool Cy_SySPm_IsDeepSleepRegEnabled(void)
2096 {
2097 return(0u == _FLD2VAL(SRSS_PWR_CTL2_DPSLP_REG_DIS, SRSS_PWR_CTL2));
2098 }
2099
2100 /* High Current Regulator is not available in version 2 of the MXS40SRSS IP block. */
2101 #if (defined (SRSS_S40E_REGHC_PRESENT) && (SRSS_S40E_REGHC_PRESENT == 1u)) || (defined (SRSS_S40E_HTREGHC_PRESENT) && (SRSS_S40E_HTREGHC_PRESENT == 1u))
Cy_SysPm_ReghcSelectMode(cy_en_syspm_reghc_mode_t mode)2102 void Cy_SysPm_ReghcSelectMode(cy_en_syspm_reghc_mode_t mode)
2103 {
2104 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_MODE, mode);
2105 }
2106
Cy_SysPm_ReghcGetMode(void)2107 cy_en_syspm_reghc_mode_t Cy_SysPm_ReghcGetMode(void)
2108 {
2109 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_reghc_mode_t enum.');
2110 return (cy_en_syspm_reghc_mode_t)(_FLD2VAL(SRSS_PWR_REGHC_CTL_REGHC_MODE, SRSS_PWR_REGHC_CTL));
2111 }
2112
Cy_SysPm_ReghcSelectDriveOut(cy_en_syspm_reghc_drive_out_t drvOut)2113 void Cy_SysPm_ReghcSelectDriveOut(cy_en_syspm_reghc_drive_out_t drvOut)
2114 {
2115 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT, drvOut);
2116 }
2117
Cy_SysPm_ReghcGetDriveOut(void)2118 cy_en_syspm_reghc_drive_out_t Cy_SysPm_ReghcGetDriveOut(void)
2119 {
2120 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_reghc_drive_out_t enum.');
2121 return (cy_en_syspm_reghc_drive_out_t)(_FLD2VAL(SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT, SRSS_PWR_REGHC_CTL));
2122 }
2123
Cy_SysPm_ReghcAdjustOutputVoltage(cy_en_syspm_reghc_vadj_t trim)2124 void Cy_SysPm_ReghcAdjustOutputVoltage(cy_en_syspm_reghc_vadj_t trim)
2125 {
2126 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_VADJ, trim);
2127 }
2128
Cy_SysPm_ReghcDisableIntSupplyWhileExtActive(void)2129 void Cy_SysPm_ReghcDisableIntSupplyWhileExtActive(void)
2130 {
2131 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk;
2132 }
2133
Cy_SysPm_ReghcEnableIntSupplyWhileExtActive(void)2134 void Cy_SysPm_ReghcEnableIntSupplyWhileExtActive(void)
2135 {
2136 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk;
2137 }
2138
2139
Cy_SysPm_ReghcDisablePmicEnableOutput(void)2140 void Cy_SysPm_ReghcDisablePmicEnableOutput(void)
2141 {
2142 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk;
2143 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk;
2144 }
2145
Cy_SysPm_ReghcEnablePmicEnableOutput(bool polarity)2146 void Cy_SysPm_ReghcEnablePmicEnableOutput(bool polarity)
2147 {
2148 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk;
2149
2150 if(polarity)
2151 {
2152 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk;
2153 }
2154 else
2155 {
2156 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk;
2157 }
2158 }
2159
Cy_SysPm_ReghcEnablePmicStatusInput(bool polarity)2160 void Cy_SysPm_ReghcEnablePmicStatusInput(bool polarity)
2161 {
2162 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk;
2163
2164 if(polarity)
2165 {
2166 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk;
2167 }
2168 else
2169 {
2170 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk;
2171 }
2172
2173 }
2174
Cy_SysPm_ReghcDisablePmicStatusInput(void)2175 void Cy_SysPm_ReghcDisablePmicStatusInput(void)
2176 {
2177 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk;
2178 }
2179
Cy_SysPm_ReghcSetPmicStatusWaitTime(uint16_t waitTime)2180 void Cy_SysPm_ReghcSetPmicStatusWaitTime(uint16_t waitTime)
2181 {
2182 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT, waitTime);
2183 }
2184
Cy_SysPm_ReghcIsConfigured(void)2185 bool Cy_SysPm_ReghcIsConfigured(void)
2186 {
2187 return (_FLD2BOOL(SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED, SRSS_PWR_REGHC_CTL));
2188 }
2189
Cy_SysPm_ReghcSetConfigured(void)2190 void Cy_SysPm_ReghcSetConfigured(void)
2191 {
2192 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Msk;
2193 }
2194
Cy_SysPm_ReghcDisable(void)2195 void Cy_SysPm_ReghcDisable(void)
2196 {
2197 SRSS_PWR_REGHC_CTL2 &= (uint32_t) ~SRSS_PWR_REGHC_CTL2_REGHC_EN_Msk;
2198 }
2199
Cy_SysPm_ReghcEnable(void)2200 void Cy_SysPm_ReghcEnable(void)
2201 {
2202 SRSS_PWR_REGHC_CTL2 |= SRSS_PWR_REGHC_CTL2_REGHC_EN_Msk;
2203 }
2204
Cy_SysPm_ReghcDisablePmicStatusTimeout(void)2205 void Cy_SysPm_ReghcDisablePmicStatusTimeout(void)
2206 {
2207 SRSS_PWR_REGHC_CTL2 &= (uint32_t) ~SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Msk;
2208 }
2209
Cy_SysPm_ReghcEnablePmicStatusTimeout(uint8_t timeout)2210 void Cy_SysPm_ReghcEnablePmicStatusTimeout(uint8_t timeout)
2211 {
2212 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL2, SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT, timeout);
2213 }
2214
Cy_SysPm_ReghcIsEnabled(void)2215 bool Cy_SysPm_ReghcIsEnabled(void)
2216 {
2217 return (_FLD2BOOL(SRSS_PWR_REGHC_STATUS_REGHC_ENABLED, SRSS_PWR_REGHC_STATUS));
2218 }
2219
Cy_SysPm_ReghcIsStatusOk(void)2220 bool Cy_SysPm_ReghcIsStatusOk(void)
2221 {
2222 return (_FLD2BOOL(SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK, SRSS_PWR_REGHC_STATUS));
2223 }
2224
Cy_SysPm_ReghcIsSequencerBusy(void)2225 bool Cy_SysPm_ReghcIsSequencerBusy(void)
2226 {
2227 return (_FLD2BOOL(SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY, SRSS_PWR_REGHC_STATUS));
2228 }
2229
Cy_SysPm_ReghcDisableVAdj(void)2230 void Cy_SysPm_ReghcDisableVAdj(void)
2231 {
2232 SRSS_PWR_REGHC_CTL4 |= SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Msk;
2233 }
2234
Cy_SysPm_ReghcEnableVAdj(void)2235 void Cy_SysPm_ReghcEnableVAdj(void)
2236 {
2237 SRSS_PWR_REGHC_CTL4 &= (uint32_t) ~SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Msk;
2238 }
2239
Cy_SysPm_ReghcDisablePmicInDeepSleep(void)2240 void Cy_SysPm_ReghcDisablePmicInDeepSleep(void)
2241 {
2242 SRSS_PWR_REGHC_CTL4 &= (uint32_t) ~SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Msk;
2243 }
2244
Cy_SysPm_ReghcEnablePmicInDeepSleep(void)2245 void Cy_SysPm_ReghcEnablePmicInDeepSleep(void)
2246 {
2247 SRSS_PWR_REGHC_CTL4 |= SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Msk;
2248 }
2249
Cy_SysPm_ReghcIsOcdWithinLimits(void)2250 bool Cy_SysPm_ReghcIsOcdWithinLimits(void)
2251 {
2252 return (_FLD2BOOL(SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK, SRSS_PWR_REGHC_STATUS));
2253 }
2254
Cy_SysPm_ReghcIsCircuitEnabledAndOperating(void)2255 bool Cy_SysPm_ReghcIsCircuitEnabledAndOperating(void)
2256 {
2257 return (_FLD2BOOL(SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK, SRSS_PWR_REGHC_STATUS));
2258 }
2259
Cy_SysPm_ReghcConfigure(cy_en_syspm_reghc_mode_t mode,cy_en_syspm_reghc_vadj_t vadj)2260 cy_en_syspm_status_t Cy_SysPm_ReghcConfigure(cy_en_syspm_reghc_mode_t mode, cy_en_syspm_reghc_vadj_t vadj)
2261 {
2262 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
2263 uint32_t timeOut = REGHC_WAIT_DELAY_TRIES_US;
2264
2265 /* Current support is for External Transistor mode only */
2266 CY_ASSERT_L3(mode == CY_SYSPM_REGHC_MODE_TRANSISTOR);
2267
2268 /* a. Write PWR_REGHC_CTL.REGHC_MODE = 0 to configure the external transistor mode. */
2269 Cy_SysPm_ReghcSelectMode(mode);
2270
2271 /* b. Write PWR_REGHC_CTL.REGHC_TRANS_USE_OCD = 1 */
2272 //HW default is "1"
2273
2274 /* c. Write PWR_REGHC_CTL.REGHC_VADJ to the required feedback setting.*/
2275 Cy_SysPm_ReghcAdjustOutputVoltage(vadj);
2276
2277 /* d. Write PWR_REGHC_CTL.REGHC_CONFIGURED = 1. */
2278 Cy_SysPm_ReghcSetConfigured();
2279
2280 /* e. Execute the system call (LoadRegulatorTrims) to change internal regulator trims. */
2281 //HW takes care
2282
2283 /* f. Write PWR_REGHC_CTL2.REGHC_EN = 1. */
2284 Cy_SysPm_ReghcEnable();
2285
2286 /* g. Wait until PWR_REGHC_STATUS.REGHC_SEQ_BUSY = 0 and PWR_REGHC_STATUS.REGHC_ENABLED = 1.
2287 * This should occur within 15us.
2288 */
2289 while (((true == Cy_SysPm_ReghcIsSequencerBusy()) || (false == Cy_SysPm_ReghcIsEnabled())) && (0U != timeOut))
2290 {
2291 Cy_SysLib_DelayUs(1U);
2292 timeOut--;
2293 }
2294
2295 if (0U != timeOut)
2296 {
2297 retVal= CY_SYSPM_SUCCESS;
2298 }
2299
2300 return retVal;
2301 }
2302
Cy_SysPm_ReghcDeConfigure(void)2303 cy_en_syspm_status_t Cy_SysPm_ReghcDeConfigure(void)
2304 {
2305 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
2306 uint32_t timeOut = REGHC_WAIT_DELAY_TRIES_US;
2307
2308 /* a. Write PWR_REGHC_CTL2.REGHC_EN = 0. */
2309 Cy_SysPm_ReghcDisable();
2310
2311 /* b. Wait until PWR_REGHC_STATUS.REGHC_SEQ_BUSY = 0 and PWR_REGHC_STATUS.REGHC_ENABLED = 0.
2312 * This should occur within 10 us.
2313 */
2314 while (((true == Cy_SysPm_ReghcIsSequencerBusy()) || (true == Cy_SysPm_ReghcIsEnabled())) && (0U != timeOut))
2315 {
2316 Cy_SysLib_DelayUs(1U);
2317 timeOut--;
2318 }
2319
2320 if (0U != timeOut)
2321 {
2322 retVal= CY_SYSPM_SUCCESS;
2323 }
2324
2325 return retVal;
2326 }
2327
2328
2329 #endif /* (SRSS_S40E_REGHC_PRESENT == 1u) || (SRSS_S40E_HTREGHC_PRESENT == 1u) */
2330
2331
2332 #endif /* (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2) */
2333
2334 /* [] END OF FILE */
2335
