1 /***************************************************************************//**
2 * \file cy_syspm_v2.c
3 * \version 5.150
4 *
5 * This driver provides the source code for API power management.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27 #include "cy_sysclk.h"
28
29 #if defined (CY_IP_MXS40SSRSS)
30
31 #include "cy_syspm.h"
32 #if defined (CY_IP_MXS40SSRSS)
33 #include "cy_syspm_ppu.h"
34 #endif
35
36
37 /*******************************************************************************
38 * Internal Functions
39 *******************************************************************************/
40 __WEAK void Cy_SysPm_Dsramoff_Entry(void);
41 static bool IsVoltageChangePossible(void);
42
43 #ifdef ENABLE_MEM_VOLTAGE_TRIMS
44 /* RAM and ROM Voltage TRIM functions */
45 static void SetMemoryVoltageTrims(cy_en_syspm_sdr_voltage_t voltage);
46 #endif /* ENABLE_MEM_VOLTAGE_TRIMS */
47
48 #if defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)
49 static void SetReadMarginTrimUlp(void);
50 static void SetReadMarginTrimLp(void);
51 static void SetReadMarginTrimMf(void);
52 static void SetReadMarginTrimOd(void);
53 static void SetWriteAssistTrimUlp(void);
54 static void SetWriteAssistTrimLp(void);
55 static void SetWriteAssistTrimMf(void);
56 static void SetWriteAssistTrimOd(void);
57 #endif
58
59 /*******************************************************************************
60 * Internal Defines
61 *******************************************************************************/
62
63
64 #if defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)
65 /* The define for number of callback roots */
66 #define CALLBACK_ROOT_NR (9U)
67
68 /* Define for transitional 1.0 V for the LDO regulator */
69 #define LDO_OUT_VOLTAGE_1_0V (0x0CU)
70
71 /* Define for transitional 1.2 V for the LDO regulator */
72 #define LDO_OUT_VOLTAGE_1_2V (0x1CU)
73
74 /* Define for transitional 1.1 V for the LDO regulator */
75 #define LDO_OUT_VOLTAGE_1_1V (0x14U)
76
77 /* Define for an LDO stabilization delay to 1.0 V */
78 #define LDO_TO_1_0V_DELAY_US (3U)
79
80 /* Define for an LDO regulator stabilization delay to 1.1 V */
81 #define LDO_TO_1_1V_DELAY_US (3U)
82
83 /* Define for an LDO stabilization delay 1.2 V */
84 #define LDO_TO_1_2V_DELAY_US (3U)
85
86 /* Mask for the RAM read assist bits */
87 #define SRSS_TRIM_RAM_CTL_RA_MASK ((uint32_t) 0x3U << 8U)
88
89 /* Wake up delay for LP mode */
90 #define SRSS_PWR_TRIM_WAKE_LP (0x50U)
91
92 /* Wake up delay for MF mode */
93 #define SRSS_PWR_TRIM_WAKE_MF (0x50U)
94
95 /* Wake up delay for OD mode*/
96 #define SRSS_PWR_TRIM_WAKE_OD (0x50U)
97
98 /* Mask for the RAM write check bits */
99 #define SRSS_TRIM_RAM_CTL_WC_MASK (0x3UL << 10U)
100
101 #else
102 /* The define for number of callback roots */
103 #define CALLBACK_ROOT_NR (7U)
104 #endif
105
106 /* The mask to unlock the Hibernate power mode */
107 #define HIBERNATE_UNLOCK_VAL ((uint32_t) 0x3Au << SRSS_PWR_HIBERNATE_UNLOCK_Pos)
108
109 /* The mask to set the Hibernate power mode */
110 #define SET_HIBERNATE_MODE ((HIBERNATE_UNLOCK_VAL |\
111 SRSS_PWR_HIBERNATE_FREEZE_Msk |\
112 SRSS_PWR_HIBERNATE_HIBERNATE_Msk))
113
114 /* The mask to retain the Hibernate power mode status */
115 #define HIBERNATE_RETAIN_STATUS_MASK ((SRSS_PWR_HIBERNATE_TOKEN_Msk |\
116 SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\
117 SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\
118 SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\
119 SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk))
120
121 /** The mask for the Hibernate wakeup sources */
122 #define HIBERNATE_WAKEUP_MASK ((SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_SRC_Msk |\
123 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_CSV_BAK_Msk |\
124 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_RTC_Msk |\
125 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_WDT_Msk))
126
127 /** The define to update the token to indicate the transition into Hibernate */
128 #define HIBERNATE_TOKEN ((uint32_t) 0x1BU << SRSS_PWR_HIBERNATE_TOKEN_Pos)
129
130 /* The wait time for transition into the minimum regulator current mode
131 */
132 #define SET_MIN_CURRENT_MODE_DELAY_US (1U)
133
134 /* The wait delay time that occurs before the active reference is settled.
135 * Intermediate delay is used in transition into the normal regulator current
136 * mode
137 */
138 #define ACT_REF_SETTLE_DELAY_US (6U)
139
140 /* The wait delay time that occurs after the active reference is settled.
141 * Final delay is used in transition into the normal regulator current mode
142 */
143 #define SET_NORMAL_CURRENT_MODE_DELAY_US (1U)
144
145 /* The internal define of the tries number in the
146 * Cy_SysPm_SystemSetMinRegulatorCurrent() function
147 */
148 #define WAIT_DELAY_TRIES (100U)
149
150 /* The internal define of the tries number in the
151 * Cy_SysPm_SystemSetMinRegulatorCurrent() function
152 */
153 #define CY_SYSPM_CBUCK_BUSY_RETRY_COUNT (100U)
154 #define CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS (1U)
155
156 /* Define for ROM trim for 0.9V */
157 #define CPUSS_TRIM_ROM_VOLT_0_900 (0x00000012U)
158
159 /* Define for ROM trim for 1.0V */
160 #define CPUSS_TRIM_ROM_VOLT_1_000 (0x00000012U)
161
162 /* Define for ROM trim for 1.1V */
163 #define CPUSS_TRIM_ROM_VOLT_1_100 (0x00000013U)
164
165 /* Define for RAM trim for 0.9V */
166 #define CPUSS_TRIM_RAM_VOLT_0_900 (0x00006012U)
167
168 /* Define for RAM trim for 1.0V */
169 #define CPUSS_TRIM_RAM_VOLT_1_000 (0x00005012U)
170
171 /* Define for RAM trim for 1.1V */
172 #define CPUSS_TRIM_RAM_VOLT_1_100 (0x00004013U)
173
174 /* Mask for the RAM write check bits */
175 #define CPUSS_TRIM_RAM_CTL_WC_MASK (0x3UL << 10U)
176
177 /* Define for transitional 0.95 V for the LDO regulator */
178 #define LDO_OUT_VOLTAGE_0_95V (0x0BU)
179
180 /*******************************************************************************
181 * Internal Variables
182 *******************************************************************************/
183 #if defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)
184 /* Array of the callback roots */
185 static cy_stc_syspm_callback_t* pmCallbackRoot[CALLBACK_ROOT_NR] = {(void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0};
186
187 /* The array of the pointers to failed callback */
188 static cy_stc_syspm_callback_t* failedCallback[CALLBACK_ROOT_NR] = {(void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0};
189 #else
190 /* Array of the callback roots */
191 static cy_stc_syspm_callback_t* pmCallbackRoot[CALLBACK_ROOT_NR] = {(void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0};
192
193 /* The array of the pointers to failed callback */
194 static cy_stc_syspm_callback_t* failedCallback[CALLBACK_ROOT_NR] = {(void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0, (void *)0};
195 #endif
196
Cy_SysPm_Init(void)197 void Cy_SysPm_Init(void)
198 {
199 if(CY_SYSPM_WARM_BOOT_MODE != Cy_SysPm_GetBootMode())
200 {
201 (void)cy_pd_ppu_init((struct ppu_v1_reg *)CY_PPU_MAIN_BASE); /* Suppress a compiler warning about unused return value */
202 (void)cy_pd_ppu_init((struct ppu_v1_reg *)CY_PPU_CPUSS_BASE); /* Suppress a compiler warning about unused return value */
203 (void)cy_pd_ppu_init((struct ppu_v1_reg *)CY_PPU_SRAM_BASE); /* Suppress a compiler warning about unused return value */
204
205 /* Set Default mode to DEEPSLEEP */
206 (void)Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP);
207 }
208 }
209
Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor)210 cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor)
211 {
212 uint32_t interruptState;
213 uint32_t cbSleepRootIdx = (uint32_t) CY_SYSPM_SLEEP;
214 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
215
216 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
217
218 /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
219 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
220 {
221 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_READY);
222 }
223
224 /* The CPU can switch into the Sleep power mode only when
225 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
226 * parameter return CY_SYSPM_SUCCESS.
227 */
228 if(retVal == CY_SYSPM_SUCCESS)
229 {
230 /* Call the registered callback functions with
231 * CY_SYSPM_BEFORE_TRANSITION parameter
232 */
233 interruptState = Cy_SysLib_EnterCriticalSection();
234 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
235 {
236 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_BEFORE_TRANSITION);
237 }
238
239 /* The CPU enters the Sleep power mode upon execution of WFI/WFE */
240 SCB_SCR &= (uint32_t) ~SCB_SCR_SLEEPDEEP_Msk;
241
242 if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
243 {
244 __WFI();
245 }
246 else
247 {
248 __WFE();
249 }
250 Cy_SysLib_ExitCriticalSection(interruptState);
251
252 /* Call the registered callback functions with the
253 * CY_SYSPM_AFTER_TRANSITION parameter
254 */
255 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
256 {
257 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_AFTER_TRANSITION);
258 }
259 }
260 else
261 {
262 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
263 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
264 * parameter
265 */
266 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_FAIL);
267 retVal = CY_SYSPM_FAIL;
268 }
269 return retVal;
270 }
271
Cy_SysPm_SystemLpActiveEnter(void)272 cy_en_syspm_status_t Cy_SysPm_SystemLpActiveEnter(void)
273 {
274 uint32_t interruptState;
275 uint32_t cbSleepRootIdx = (uint32_t)CY_SYSPM_LPACTIVE_ENTER;
276 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
277
278 /* Step-1: Wait until PWR_CTL.LPM_READY==1 to indicate low power circuits are ready. */
279 if(!Cy_SysPm_IsLpmReady())
280 {
281 retVal = CY_SYSPM_FAIL;
282 }
283 else
284 {
285 /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
286 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
287 {
288 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_READY);
289 }
290
291 if (retVal == CY_SYSPM_SUCCESS)
292 {
293 /* The CPU can switch into the LPACTIVE power mode only when
294 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
295 * parameter return CY_SYSPM_SUCCESS.
296 */
297 /* Call the registered callback functions with
298 * CY_SYSPM_BEFORE_TRANSITION parameter
299 */
300 interruptState = Cy_SysLib_EnterCriticalSection();
301 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
302 {
303 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION); /* Suppress a compiler warning about unused return value */
304 }
305
306 //Enabling Low Power Profile
307 /* Step-2: Clock for clk_hf0 is selected as IMO, which runs at 8MHz Nominal. */
308 (void)Cy_SysClk_ClkHfDirectSel(0U, true);
309
310 //Disable FLL if enabled
311 if(Cy_SysClk_FllIsEnabled())
312 {
313 (void)Cy_SysClk_FllDisable(); /* Suppress a compiler warning about unused return value */
314 }
315
316 //Disable PLL if enabled
317 #if (defined (SRSS_NUM_TOTAL_PLL) && (SRSS_NUM_TOTAL_PLL > 0UL))
318 if(Cy_SysClk_PllIsEnabled(1U))
319 {
320 (void)Cy_SysClk_PllDisable(1U); /* Suppress a compiler warning about unused return value */
321 }
322
323 if(Cy_SysClk_PllIsEnabled(2U))
324 {
325 (void)Cy_SysClk_PllDisable(2U); /* Suppress a compiler warning about unused return value */
326 }
327 #endif
328
329 /* Step-3: If reducing the regulator output voltage for RegSetA, perform the extra requester sequence.
330 * Call API-Cy_SysPm_LdoExtraRequesterConfig before calling this if the voltage needs to be reduced
331 */
332
333 /* Step-4: If lowest power is required; perform the following writes to PWR_CTL2 */
334 retVal = Cy_SysPm_SystemSetMinRegulatorCurrent();
335
336 Cy_SysLib_ExitCriticalSection(interruptState);
337
338 /* Call the registered callback functions with the
339 * CY_SYSPM_AFTER_TRANSITION parameter
340 */
341 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
342 {
343 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_AFTER_TRANSITION); /* Suppress a compiler warning about unused return value */
344 }
345 }
346 else
347 {
348 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
349 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
350 * parameter
351 */
352 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_FAIL); /* Suppress a compiler warning about unused return value */
353 retVal = CY_SYSPM_FAIL;
354 }
355 }
356 return retVal;
357 }
358
Cy_SysPm_SystemLpActiveExit(void)359 cy_en_syspm_status_t Cy_SysPm_SystemLpActiveExit(void)
360 {
361 uint32_t interruptState;
362 uint32_t cbSleepRootIdx = (uint32_t)CY_SYSPM_LPACTIVE_EXIT;
363 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
364
365 /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
366 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
367 {
368 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_READY);
369 }
370
371 if (retVal == CY_SYSPM_SUCCESS)
372 {
373 /* The CPU can switch into the LPACTIVE power mode only when
374 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
375 * parameter return CY_SYSPM_SUCCESS.
376 */
377 /* Call the registered callback functions with
378 * CY_SYSPM_BEFORE_TRANSITION parameter
379 */
380 interruptState = Cy_SysLib_EnterCriticalSection();
381 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
382 {
383 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION); /* Suppress a compiler warning about unused return value */
384 }
385
386 /* Step-1: Reverse the writes to PWR_CTL2 which are done in Cy_SysPm_SystemLpActiveEnter*/
387 retVal = Cy_SysPm_SystemSetNormalRegulatorCurrent();
388
389 /* Step-2: If increasing the regulator output voltage for RegSetB, perform the extra requester sequence.
390 * Call API-Cy_SysPm_LdoExtraRequesterConfig before calling this if the voltage needs to be increased
391 */
392
393 /* Step-3: High Frequency clocks could be enabled */
394 if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(0UL))
395 {
396 retVal = CY_SYSPM_FAIL;
397 }
398
399 #if (defined (SRSS_NUM_TOTAL_PLL) && (SRSS_NUM_TOTAL_PLL > 0UL))
400 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 10000u))
401 {
402 retVal = CY_SYSPM_FAIL;
403 }
404 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2UL, 10000u))
405 {
406 retVal = CY_SYSPM_FAIL;
407 }
408 #endif
409
410 (void)Cy_SysClk_ClkHfDirectSel(0U, false);
411
412 Cy_SysLib_ExitCriticalSection(interruptState);
413
414 /* Call the registered callback functions with the
415 * CY_SYSPM_AFTER_TRANSITION parameter
416 */
417 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
418 {
419 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_AFTER_TRANSITION); /* Suppress a compiler warning about unused return value */
420 }
421 }
422 else
423 {
424 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
425 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
426 * parameter
427 */
428 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_FAIL); /* Suppress a compiler warning about unused return value */
429 retVal = CY_SYSPM_FAIL;
430 }
431 return retVal;
432 }
433
Cy_SysPm_IsSystemLpActiveEnabled(void)434 bool Cy_SysPm_IsSystemLpActiveEnabled(void)
435 {
436 return (_FLD2BOOL(SRSS_PWR_CTL2_REFV_DIS, SRSS_PWR_CTL2)? true : false);
437 }
438
Cy_SysPm_SetDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)439 cy_en_syspm_status_t Cy_SysPm_SetDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)
440 {
441 cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
442
443 switch(deepSleepMode)
444 {
445 case CY_SYSPM_MODE_DEEPSLEEP:
446 {
447 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE, (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
448 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_CPUSS_BASE, (uint32_t)CY_SYSTEM_CPUSS_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
449 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM_BASE, (uint32_t)CY_SYSTEM_SRAM_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
450 retVal = CY_SYSPM_SUCCESS;
451 }
452 break;
453
454 case CY_SYSPM_MODE_DEEPSLEEP_RAM:
455 {
456 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE, (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
457 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_CPUSS_BASE, (uint32_t)CY_SYSTEM_CPUSS_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
458 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM_BASE, (uint32_t)CY_SYSTEM_SRAM_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
459 retVal = CY_SYSPM_SUCCESS;
460 }
461 break;
462
463 case CY_SYSPM_MODE_DEEPSLEEP_OFF:
464 {
465 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE, (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
466 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_CPUSS_BASE, (uint32_t)CY_SYSTEM_CPUSS_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
467 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM_BASE, (uint32_t)CY_SYSTEM_SRAM_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
468 retVal = CY_SYSPM_SUCCESS;
469 }
470 break;
471
472 default:
473 retVal = CY_SYSPM_BAD_PARAM;
474 break;
475 }
476 return retVal;
477 }
478
Cy_SysPm_GetDeepSleepMode(void)479 cy_en_syspm_deep_sleep_mode_t Cy_SysPm_GetDeepSleepMode(void)
480 {
481 uint32_t mode;
482 cy_en_syspm_deep_sleep_mode_t deepSleepMode;
483
484 mode = (uint32_t)cy_pd_ppu_get_programmed_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE);
485
486 switch(mode)
487 {
488 case CY_SYSTEM_DEEPSLEEP_PPU_MODES:
489 {
490 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP;
491 }
492 break;
493
494 case CY_SYSTEM_DEEPSLEEP_RAM_PPU_MODES:
495 {
496 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_RAM;
497 }
498 break;
499
500 case CY_SYSTEM_DEEPSLEEP_OFF_PPU_MODES:
501 {
502 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_OFF;
503 }
504 break;
505
506 default:
507 {
508 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_NONE;
509 }
510 break;
511 }
512
513 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_deep_sleep_mode_t enum.');
514 return ((cy_en_syspm_deep_sleep_mode_t)deepSleepMode);
515 }
516
Cy_SysPm_GetBootMode(void)517 cy_en_syspm_boot_mode_t Cy_SysPm_GetBootMode(void)
518 {
519 uint32_t resCause, resCause2;
520 cy_en_syspm_boot_mode_t deepSleepWakeMode = CY_SYSPM_POR_BOOT_MODE;
521
522 resCause = SRSS_RES_CAUSE;
523 resCause2 = SRSS_RES_CAUSE2;
524
525 if((resCause == 0UL) || (resCause2 == 0UL))
526 {
527 switch(Cy_SysPm_GetDeepSleepMode())
528 {
529 case CY_SYSPM_MODE_DEEPSLEEP_RAM:
530 {
531 deepSleepWakeMode = CY_SYSPM_WARM_BOOT_MODE;
532 }
533 break;
534
535 case CY_SYSPM_MODE_DEEPSLEEP_OFF:
536 {
537 deepSleepWakeMode = CY_SYSPM_COLD_BOOT_MODE;
538 }
539 break;
540
541 default:
542 {
543 deepSleepWakeMode = CY_SYSPM_POR_BOOT_MODE;
544 }
545 break;
546 }
547
548 }
549
550 return ((cy_en_syspm_boot_mode_t)deepSleepWakeMode);
551 }
552
553 /*Weak declaration allows for both RTOS and non-RTOS based
554 * implementation to handle any context store before WFI
555 * This PDL implements a weak handler for non-RTOS based deep sleep */
Cy_SysPm_StoreDSContext_Wfi(void)556 __WEAK void Cy_SysPm_StoreDSContext_Wfi(void)
557 {
558 __WFI();
559 }
560
Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor)561 cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor)
562 {
563 uint32_t interruptState;
564 uint32_t cbDeepSleepRootIdx = (uint32_t) Cy_SysPm_GetDeepSleepMode();
565 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
566
567 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
568 CY_ASSERT_L3(CY_SYSPM_IS_DEEPSLEEP_MODE_VALID(cbDeepSleepRootIdx));
569
570 //Check if LPM is ready
571 if(!Cy_SysPm_IsLpmReady())
572 {
573 retVal = CY_SYSPM_FAIL;
574 }
575 else
576 {
577 /* Call the registered callback functions with the CY_SYSPM_CHECK_READY
578 * parameter
579 */
580 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
581 {
582 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_READY);
583 }
584
585 /* The CPU can switch into the Deep Sleep power mode only when
586 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
587 * parameter return CY_SYSPM_SUCCESS
588 */
589 if (retVal == CY_SYSPM_SUCCESS)
590 {
591 /* Call the registered callback functions with the
592 * CY_SYSPM_BEFORE_TRANSITION parameter
593 */
594 interruptState = Cy_SysLib_EnterCriticalSection();
595 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
596 {
597 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION);
598 }
599 /* The CPU enters Deep Sleep mode upon execution of WFI/WFE
600 * use Cy_SysPm_SetDeepSleepMode to set various deepsleep modes TBD*/
601 SCB_SCR |= SCB_SCR_SLEEPDEEP_Msk;
602
603 if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
604 {
605 if (cbDeepSleepRootIdx == (uint32_t)CY_SYSPM_MODE_DEEPSLEEP_RAM)
606 {
607 Cy_SysPm_StoreDSContext_Wfi();
608 }
609 else
610 {
611 __WFI();
612 }
613 }
614 else
615 {
616 __WFE();
617 }
618
619 /* Call the registered callback functions with the CY_SYSPM_AFTER_DS_WFI_TRANSITION
620 * parameter
621 */
622 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
623 {
624 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_AFTER_DS_WFI_TRANSITION);
625 }
626
627 Cy_SysLib_ExitCriticalSection(interruptState);
628 }
629 if (retVal == CY_SYSPM_SUCCESS)
630 {
631 /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION
632 * parameter
633 */
634 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
635 {
636 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_AFTER_TRANSITION);
637 }
638 }
639 else
640 {
641 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
642 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
643 * parameter
644 */
645 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
646 {
647 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_FAIL);
648 }
649 }
650 }
651 return retVal;
652 }
653
Cy_SysPm_SetupDeepSleepRAM(cy_en_syspm_dsram_checks_t dsramCheck,uint32_t * dsramIntState)654 cy_en_syspm_status_t Cy_SysPm_SetupDeepSleepRAM(cy_en_syspm_dsram_checks_t dsramCheck, uint32_t *dsramIntState)
655 {
656 uint32_t cbDeepSleepRootIdx = (uint32_t) Cy_SysPm_GetDeepSleepMode();
657 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
658
659 CY_ASSERT_L3(CY_SYSPM_IS_DSRAM_CHECK_VALID(dsramCheck));
660 CY_ASSERT_L3(CY_SYSPM_IS_DEEPSLEEP_MODE_VALID(cbDeepSleepRootIdx));
661
662 //Check if LPM is ready
663 if(!Cy_SysPm_IsLpmReady())
664 {
665 retVal = CY_SYSPM_FAIL;
666 }
667 else
668 {
669 if(dsramCheck == CY_SYSPM_PRE_DSRAM)
670 {
671 /* Clear the Warm Boot Entry status Flag */
672 Cy_SysLib_ClearDSRAMWarmBootEntryStatus();
673
674 /* Call the registered callback functions with the CY_SYSPM_CHECK_READY
675 * parameter
676 */
677 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
678 {
679 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_READY);
680 }
681
682 /* The CPU can switch into the Deep Sleep power mode only when
683 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
684 * parameter return CY_SYSPM_SUCCESS
685 */
686 if (retVal == CY_SYSPM_SUCCESS)
687 {
688 /* Call the registered callback functions with the
689 * CY_SYSPM_BEFORE_TRANSITION parameter
690 */
691 *dsramIntState = Cy_SysLib_EnterCriticalSection();
692
693 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
694 {
695 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION);
696 }
697 /* The CPU enters Deep Sleep mode upon execution of WFI/WFE
698 * use Cy_SysPm_SetDeepSleepMode to set various deepsleep modes TBD*/
699 SCB_SCR |= SCB_SCR_SLEEPDEEP_Msk;
700
701 }
702 else
703 {
704 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
705 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
706 * parameter
707 */
708 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
709 {
710 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_FAIL);
711 }
712 }
713 }
714 else
715 {
716 /* Call the registered callback functions with the CY_SYSPM_AFTER_DS_WFI_TRANSITION
717 * parameter
718 */
719 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
720 {
721 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_AFTER_DS_WFI_TRANSITION);
722 }
723
724 Cy_SysLib_ExitCriticalSection(*dsramIntState);
725
726 /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION
727 * parameter
728 */
729 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
730 {
731 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_AFTER_TRANSITION);
732 }
733 }
734 }
735 return retVal;
736 }
737
Cy_SysPm_SystemEnterHibernate(void)738 cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void)
739 {
740 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
741 uint32_t cbHibernateRootIdx = (uint32_t) CY_SYSPM_HIBERNATE;
742 /* Call the registered callback functions with the
743 * CY_SYSPM_CHECK_READY parameter
744 */
745 if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
746 {
747 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_READY);
748 }
749
750 /* The system can switch into Hibernate power mode only when
751 * all executed registered callback functions with CY_SYSPM_CHECK_READY
752 * parameter return CY_SYSPM_SUCCESS.
753 */
754 if(retVal == CY_SYSPM_SUCCESS)
755 {
756 /* Call registered callback functions with CY_SYSPM_BEFORE_TRANSITION
757 * parameter
758 */
759 (void) Cy_SysLib_EnterCriticalSection();
760 if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
761 {
762 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_BEFORE_TRANSITION);
763 }
764
765 /* Preserve the token that will be retained through a wakeup sequence.
766 * This could be used by Cy_SysLib_GetResetReason() to differentiate
767 * Wakeup from a general reset event.
768 * Preserve the wakeup source(s) configuration.
769 */
770 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE | HIBERNATE_TOKEN);
771
772 /* Clear Previous Wakeup Reasons */
773 Cy_SysPm_ClearHibernateWakeupCause();
774
775 /* Disable overriding by the peripherals the next pin-freeze command */
776 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
777
778 /* The second write causes freezing of I/O cells to save the I/O-cell state */
779 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
780
781 /* Third write cause system to enter Hibernate */
782 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
783
784 /* Read register to make sure it is settled */
785 (void) SRSS_PWR_HIBERNATE;
786
787 /* Wait for transition */
788 __WFI();
789
790 /* The callback function calls with the CY_SYSPM_AFTER_TRANSITION
791 * parameter in the Hibernate power mode are not applicable as system
792 * wake-up was made on system reboot.
793 */
794
795 /* A wakeup from Hibernate is performed by toggling of the wakeup
796 * pins, or WDT matches, or Backup domain alarm expires. This depends on
797 * what item is configured in the Hibernate register. After a wakeup
798 * event, a normal Boot procedure occurs.
799 * There is no need to exit from the critical section.
800 */
801 }
802 else
803 {
804 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
805 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
806 * parameter. The return value should be CY_SYSPM_SUCCESS.
807 */
808 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_FAIL);
809 retVal = CY_SYSPM_FAIL;
810 }
811 return retVal;
812 }
813
Cy_SysPm_SystemSetMinRegulatorCurrent(void)814 cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void)
815 {
816 cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
817
818 /* Check if the power circuits are ready to enter into regulator minimum
819 * current mode
820 */
821 if (Cy_SysPm_IsLpmReady())
822 {
823 SRSS_PWR_CTL2 |= (SRSS_PWR_CTL2_LINREG_LPMODE_Msk |
824 SRSS_PWR_CTL2_PORBOD_LPMODE_Msk |
825 SRSS_PWR_CTL2_BGREF_LPMODE_Msk |
826 SRSS_PWR_CTL2_REFI_LPMODE_Msk);
827
828 /* This wait time allows the circuits to remove their dependence on
829 * the Active mode circuits, such as active Reference
830 */
831 Cy_SysLib_DelayUs(SET_MIN_CURRENT_MODE_DELAY_US);
832
833 /* Disable active reference */
834 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_REFV_DIS_Msk;
835
836 retVal = CY_SYSPM_SUCCESS;
837 }
838
839 return retVal;
840 }
841
Cy_SysPm_SystemSetNormalRegulatorCurrent(void)842 cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void)
843 {
844 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
845
846 uint32_t timeOut = WAIT_DELAY_TRIES;
847
848 /* Configure the regulator normal current mode for the POR/BOD circuits
849 * and for the Voltage References
850 */
851
852 /* Bring Regulators Power Circuit out of LPMODE */
853 SRSS_PWR_CTL2 &= (uint32_t)~(SRSS_PWR_CTL2_REFV_DIS_Msk |
854 SRSS_PWR_CTL2_LINREG_LPMODE_Msk |
855 SRSS_PWR_CTL2_PORBOD_LPMODE_Msk |
856 SRSS_PWR_CTL2_REFI_LPMODE_Msk);
857
858 /* This wait time allows setting active Reference */
859 Cy_SysLib_DelayUs(ACT_REF_SETTLE_DELAY_US);
860
861 while ((0U == _FLD2VAL(SRSS_PWR_CTL2_REFV_OK, SRSS_PWR_CTL2)) && (0U != timeOut))
862 {
863 timeOut--;
864 }
865
866 if (0U != timeOut)
867 {
868 /* Disable the low-power for Bandgap reference circuit */
869 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_BGREF_LPMODE_Msk;
870
871 /* Delay to finally set the normal current mode */
872 Cy_SysLib_DelayUs(SET_NORMAL_CURRENT_MODE_DELAY_US);
873
874 retVal= CY_SYSPM_SUCCESS;
875 }
876
877 return retVal;
878 }
879
Cy_SysPm_SystemIsMinRegulatorCurrentSet(void)880 bool Cy_SysPm_SystemIsMinRegulatorCurrentSet(void)
881 {
882 #if (defined (CY_IP_MXS40SSRSS) && (SRSS_S40S_REGSETB_PRESENT == 1UL))
883 uint32_t regMask = Cy_SysPm_LdoIsEnabled() ? CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_LDO_MASK : CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_BUCK_MASK;
884
885 return ((SRSS_PWR_CTL & regMask) == regMask);
886 #else
887 return ((0U == _FLD2VAL(SRSS_PWR_CTL2_REFV_DIS, SRSS_PWR_CTL2)) ? false : true);
888 #endif
889 }
890
Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode)891 cy_en_syspm_status_t Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode)
892 {
893 CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode));
894
895 cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
896
897 switch (mode)
898 {
899 case CY_SYSPM_LDO_MODE_NORMAL:
900 {
901 retVal = Cy_SysPm_SystemSetNormalRegulatorCurrent();
902 }
903 break;
904
905 case CY_SYSPM_LDO_MODE_MIN:
906 {
907 retVal = Cy_SysPm_SystemSetMinRegulatorCurrent();
908 }
909 break;
910
911 case CY_SYSPM_LDO_MODE_DISABLED:
912 {
913 /* Disable the LDO, Deep Sleep and Retention regulators */
914 SRSS_PWR_CTL2 |= (_VAL2FLD(SRSS_PWR_CTL2_DPSLP_REG_DIS, 1U) |
915 _VAL2FLD(SRSS_PWR_CTL2_RET_REG_DIS, 1U) |
916 _VAL2FLD(SRSS_PWR_CTL2_LINREG_DIS, 1U));
917
918 retVal = CY_SYSPM_SUCCESS;
919 }
920 break;
921
922 default:
923 retVal = CY_SYSPM_FAIL;
924 break;
925 }
926
927 return retVal;
928 }
929
Cy_SysPm_LdoGetMode(void)930 cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void)
931 {
932 cy_en_syspm_ldo_mode_t retVal;
933
934 if (!Cy_SysPm_LdoIsEnabled())
935 {
936 retVal = CY_SYSPM_LDO_MODE_DISABLED;
937 }
938 else if (Cy_SysPm_SystemIsMinRegulatorCurrentSet())
939 {
940 retVal = CY_SYSPM_LDO_MODE_MIN;
941 }
942 else
943 {
944 retVal = CY_SYSPM_LDO_MODE_NORMAL;
945 }
946
947 return retVal;
948 }
949
Cy_SysPm_LdoIsEnabled(void)950 bool Cy_SysPm_LdoIsEnabled(void)
951 {
952 return ((0U != _FLD2VAL(SRSS_PWR_CTL2_LINREG_DIS, SRSS_PWR_CTL2)) ? false : true);
953 }
954
955 #if defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)
956
Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage)957 cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage)
958 {
959 CY_ASSERT_L1(CY_SYSPM_IS_LDO_VOLTAGE_VALID(voltage));
960
961 cy_en_syspm_status_t retVal = CY_SYSPM_INVALID_STATE;
962
963 /* Voltage change is possible only when the specific device revision
964 * support registers modification.
965 */
966 if (IsVoltageChangePossible())
967 {
968 uint32_t interruptState;
969 uint32_t trimVoltage;
970 cy_en_syspm_ldo_voltage_t currVoltage = Cy_SysPm_LdoGetVoltage();
971
972 interruptState = Cy_SysLib_EnterCriticalSection();
973
974 if (CY_SYSPM_LDO_VOLTAGE_0_9V == voltage)
975 {
976 SRSS_PWR_TRIM_WAKE_CTL = 0UL;
977
978 trimVoltage = SFLASH_LDO_0P9V_TRIM;
979
980 /* Update read-write margin value for the ULP mode */
981 SetReadMarginTrimUlp();
982 }
983 else if(CY_SYSPM_LDO_VOLTAGE_1_0V == voltage)
984 {
985 if (Cy_SysPm_SystemIsMinRegulatorCurrentSet())
986 {
987 SRSS_PWR_TRIM_WAKE_CTL = SRSS_PWR_TRIM_WAKE_MF;
988 }
989 else
990 {
991 SRSS_PWR_TRIM_WAKE_CTL = SFLASH_PWR_TRIM_WAKE_CTL;
992 }
993
994 trimVoltage = SFLASH_LDO_1P0V_TRIM;
995
996 /* A delay for the supply to stabilize at the new higher voltage */
997 Cy_SysLib_DelayUs(LDO_TO_1_0V_DELAY_US);
998
999 if(currVoltage > CY_SYSPM_LDO_VOLTAGE_1_0V)
1000 {
1001 /* Update read-write margin value for the MF mode */
1002 SetReadMarginTrimMf();
1003 }
1004 else
1005 {
1006 /* Update write assist value for the MF mode */
1007 SetWriteAssistTrimMf();
1008 }
1009 }
1010 else if(CY_SYSPM_LDO_VOLTAGE_1_1V == voltage)
1011 {
1012 if (Cy_SysPm_SystemIsMinRegulatorCurrentSet())
1013 {
1014 SRSS_PWR_TRIM_WAKE_CTL = SRSS_PWR_TRIM_WAKE_LP;
1015 }
1016 else
1017 {
1018 SRSS_PWR_TRIM_WAKE_CTL = SFLASH_PWR_TRIM_WAKE_CTL;
1019 }
1020
1021 trimVoltage = SFLASH_LDO_1P1V_TRIM;
1022 /* A delay for the supply to stabilize at the new higher voltage */
1023 Cy_SysLib_DelayUs(LDO_TO_1_1V_DELAY_US);
1024
1025 if(currVoltage < CY_SYSPM_LDO_VOLTAGE_1_1V)
1026 {
1027 /* Update read-write margin value for the LP mode */
1028 SetReadMarginTrimLp();
1029 }
1030 else
1031 {
1032 /* Update write assist value for the LP mode */
1033 SetWriteAssistTrimLp();
1034 }
1035 }
1036 else
1037 {
1038 if (Cy_SysPm_SystemIsMinRegulatorCurrentSet())
1039 {
1040 SRSS_PWR_TRIM_WAKE_CTL = SRSS_PWR_TRIM_WAKE_OD;
1041 }
1042 else
1043 {
1044 SRSS_PWR_TRIM_WAKE_CTL = SFLASH_PWR_TRIM_WAKE_CTL;
1045 }
1046
1047 trimVoltage = SFLASH_LDO_1P2V_TRIM;
1048
1049 /* A delay for the supply to stabilize at the new higher voltage */
1050 Cy_SysLib_DelayUs(LDO_TO_1_2V_DELAY_US);
1051
1052 /* Update write assist value for the OD mode */
1053 SetWriteAssistTrimOd();
1054 }
1055
1056 /* The system may continue operating while the voltage on Vccd
1057 * discharges to the new voltage. The time it takes to reach the
1058 * new voltage depends on the conditions, including the load current
1059 * on Vccd and the external capacitor size.
1060 */
1061 SRSS_PWR_TRIM_PWRSYS_CTL =
1062 _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, trimVoltage);
1063
1064 if (CY_SYSPM_LDO_VOLTAGE_0_9V == voltage)
1065 {
1066 /* Update write assist value for the ULP mode */
1067 SetWriteAssistTrimUlp();
1068 }
1069 else if(CY_SYSPM_LDO_VOLTAGE_1_0V == voltage)
1070 {
1071 /* A delay for the supply to stabilize at the new intermediate voltage */
1072 Cy_SysLib_DelayUs(LDO_TO_1_0V_DELAY_US);
1073
1074 if(currVoltage > CY_SYSPM_LDO_VOLTAGE_1_1V)
1075 {
1076 /* Update write assist value for the MF mode */
1077 SetWriteAssistTrimMf();
1078 }
1079 else
1080 {
1081 /* Update read-write margin value for the MF mode */
1082 SetReadMarginTrimMf();
1083 }
1084 }
1085 else if(CY_SYSPM_LDO_VOLTAGE_1_1V == voltage)
1086 {
1087 /* A delay for the supply to stabilize at the new intermediate voltage */
1088 Cy_SysLib_DelayUs(LDO_TO_1_1V_DELAY_US);
1089 if(currVoltage > CY_SYSPM_LDO_VOLTAGE_1_1V)
1090 {
1091 /* Update write assist value for the LP mode */
1092 SetWriteAssistTrimLp();
1093 }
1094 else
1095 {
1096 /* Update read-write margin value for the LP mode */
1097 SetReadMarginTrimLp();
1098 }
1099 }
1100 else
1101 {
1102 /* A delay for the supply to stabilize at the new intermediate voltage */
1103 Cy_SysLib_DelayUs(LDO_TO_1_2V_DELAY_US);
1104
1105 /* Update read-write margin value for the OD mode */
1106 SetReadMarginTrimOd();
1107 }
1108
1109 Cy_SysLib_ExitCriticalSection(interruptState);
1110 retVal = CY_SYSPM_SUCCESS;
1111 }
1112 return retVal;
1113 }
1114
Cy_SysPm_LdoGetVoltage(void)1115 cy_en_syspm_ldo_voltage_t Cy_SysPm_LdoGetVoltage(void)
1116 {
1117 uint32_t curVoltage;
1118
1119 curVoltage = _FLD2VAL(SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, SRSS_PWR_TRIM_PWRSYS_CTL);
1120
1121 return ((curVoltage == (SFLASH_LDO_0P9V_TRIM)) ? CY_SYSPM_LDO_VOLTAGE_ULP :
1122 (curVoltage == (SFLASH_LDO_1P1V_TRIM)) ? CY_SYSPM_LDO_VOLTAGE_MF :
1123 (curVoltage == (SFLASH_LDO_1P2V_TRIM)) ? CY_SYSPM_LDO_VOLTAGE_OD :
1124 CY_SYSPM_LDO_VOLTAGE_LP);
1125
1126 }
1127 #endif
1128
Cy_SysPm_CpuSleepOnExit(bool enable)1129 void Cy_SysPm_CpuSleepOnExit(bool enable)
1130 {
1131 if(enable)
1132 {
1133 /* Enable sleep-on-exit feature */
1134 SCB_SCR |= SCB_SCR_SLEEPONEXIT_Msk;
1135 }
1136 else
1137 {
1138 /* Disable sleep-on-exit feature */
1139 SCB_SCR &= (uint32_t) ~(SCB_SCR_SLEEPONEXIT_Msk);
1140 }
1141 }
1142
Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)1143 void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)
1144 {
1145 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
1146
1147 uint32_t polarityMask = 0U;
1148 uint32_t wakeSrcMask = 0U;
1149
1150 /* LPCOMP0 & LPCOMP1 */
1151 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH)))
1152 {
1153 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK;
1154 }
1155
1156 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH)))
1157 {
1158 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK;
1159 }
1160
1161 /* PIN0 & PIN1 */
1162 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH)))
1163 {
1164 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN0_MASK;
1165 }
1166
1167 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH)))
1168 {
1169 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN1_MASK;
1170 }
1171
1172 /* RTC */
1173 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM))
1174 {
1175 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_RTC_MASK;
1176 }
1177
1178 /* WDT */
1179 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_WDT))
1180 {
1181 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_WDT_MASK;
1182 }
1183
1184 /* Polarity Mask */
1185 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH))
1186 {
1187 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
1188 }
1189
1190 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH))
1191 {
1192 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
1193 }
1194
1195 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH))
1196 {
1197 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
1198 }
1199
1200 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH))
1201 {
1202 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
1203 }
1204
1205 SRSS_PWR_HIB_WAKE_CTL = (SRSS_PWR_HIB_WAKE_CTL | wakeSrcMask);
1206 SRSS_PWR_HIB_WAKE_CTL2 = (SRSS_PWR_HIB_WAKE_CTL2 | polarityMask);
1207
1208 /* Read registers to make sure it is settled */
1209 (void) SRSS_PWR_HIB_WAKE_CTL;
1210 (void) SRSS_PWR_HIB_WAKE_CTL2;
1211
1212 }
1213
Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)1214 void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)
1215 {
1216 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
1217
1218 uint32_t polarityMask = 0U;
1219 uint32_t wakeSrcMask = 0U;
1220
1221 /* LPCOMP0 & LPCOMP1 */
1222 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH)))
1223 {
1224 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK;
1225 }
1226
1227 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH)))
1228 {
1229 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK;
1230 }
1231
1232 /* PIN0 & PIN1 */
1233 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH)))
1234 {
1235 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN0_MASK;
1236 }
1237
1238 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH)))
1239 {
1240 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN1_MASK;
1241 }
1242
1243 /* RTC */
1244 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM))
1245 {
1246 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_RTC_MASK;
1247 }
1248
1249 /* WDT */
1250 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_WDT))
1251 {
1252 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_WDT_MASK;
1253 }
1254
1255 /* Polarity Mask */
1256 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH))
1257 {
1258 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
1259 }
1260
1261 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH))
1262 {
1263 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
1264 }
1265
1266 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH))
1267 {
1268 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
1269 }
1270
1271 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH))
1272 {
1273 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
1274 }
1275
1276 SRSS_PWR_HIB_WAKE_CTL = (SRSS_PWR_HIB_WAKE_CTL & (~wakeSrcMask));
1277 SRSS_PWR_HIB_WAKE_CTL2 = (SRSS_PWR_HIB_WAKE_CTL2 & (~polarityMask));
1278
1279 /* Read registers to make sure it is settled */
1280 (void) SRSS_PWR_HIB_WAKE_CTL;
1281 (void) SRSS_PWR_HIB_WAKE_CTL2;
1282 }
1283
Cy_SysPm_GetHibernateWakeupCause(void)1284 cy_en_syspm_hibernate_wakeup_source_t Cy_SysPm_GetHibernateWakeupCause(void)
1285 {
1286 uint32_t wakeupCause;
1287 uint32_t wakeupCausePolarity;
1288
1289 wakeupCause = SRSS_PWR_HIB_WAKE_CAUSE;
1290
1291 wakeupCausePolarity = (wakeupCause & (uint32_t)(CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK |
1292 CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK |
1293 CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK |
1294 CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK ));
1295
1296 switch(wakeupCause)
1297 {
1298 case CY_SYSPM_HIB_WAKEUP_PIN0_POS:
1299 {
1300 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK))
1301 {
1302 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH);
1303 }
1304 else
1305 {
1306 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW);
1307 }
1308 }
1309 break;
1310
1311 case CY_SYSPM_HIB_WAKEUP_PIN1_POS:
1312 {
1313 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK))
1314 {
1315 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH);
1316 }
1317 else
1318 {
1319 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW);
1320 }
1321 }
1322 break;
1323
1324 case CY_SYSPM_HIB_WAKEUP_LPCOMP0_POS:
1325 {
1326 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK))
1327 {
1328 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH);
1329 }
1330 else
1331 {
1332 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_LOW);
1333 }
1334 }
1335 break;
1336
1337 case CY_SYSPM_HIB_WAKEUP_LPCOMP1_POS:
1338 {
1339 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK))
1340 {
1341 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH);
1342 }
1343 else
1344 {
1345 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_LOW);
1346 }
1347 }
1348 break;
1349
1350 case CY_SYSPM_HIB_WAKEUP_RTC_MASK:
1351 {
1352 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM);
1353 }
1354 break;
1355
1356 case CY_SYSPM_HIB_WAKEUP_WDT_MASK:
1357 {
1358 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_WDT);
1359 }
1360 break;
1361
1362 default:
1363 CY_ASSERT_L2(false);
1364 break;
1365 }
1366
1367 return (cy_en_syspm_hibernate_wakeup_source_t)wakeupCause;
1368 }
1369
Cy_SysPm_ClearHibernateWakeupCause(void)1370 void Cy_SysPm_ClearHibernateWakeupCause(void)
1371 {
1372 uint32_t temp = SRSS_PWR_HIB_WAKE_CAUSE;
1373 SRSS_PWR_HIB_WAKE_CAUSE = temp;
1374 }
1375
Cy_SysPm_CoreBuckSetVoltage(cy_en_syspm_core_buck_voltage_t voltage)1376 cy_en_syspm_status_t Cy_SysPm_CoreBuckSetVoltage(cy_en_syspm_core_buck_voltage_t voltage)
1377 {
1378 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(voltage));
1379
1380 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL, SRSS_PWR_CBUCK_CTL_CBUCK_VSEL, voltage);
1381
1382 /* Since voltage is changed , use it for the CBUCK setting decision */
1383 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL2, SRSS_PWR_CBUCK_CTL2_CBUCK_USE_SETTINGS, 1UL);
1384
1385 return Cy_SysPm_CoreBuckStatus();
1386 }
1387
Cy_SysPm_CoreBuckGetVoltage(void)1388 cy_en_syspm_core_buck_voltage_t Cy_SysPm_CoreBuckGetVoltage(void)
1389 {
1390 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_voltage_t enum.');
1391 return (cy_en_syspm_core_buck_voltage_t)(_FLD2VAL(SRSS_PWR_CBUCK_CTL_CBUCK_VSEL, SRSS_PWR_CBUCK_CTL));
1392 }
1393
Cy_SysPm_CoreBuckSetMode(cy_en_syspm_core_buck_mode_t mode)1394 void Cy_SysPm_CoreBuckSetMode(cy_en_syspm_core_buck_mode_t mode)
1395 {
1396 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(mode));
1397
1398 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL, SRSS_PWR_CBUCK_CTL_CBUCK_MODE, mode);
1399 }
1400
Cy_SysPm_CoreBuckGetMode(void)1401 cy_en_syspm_core_buck_mode_t Cy_SysPm_CoreBuckGetMode(void)
1402 {
1403 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_mode_t enum.');
1404 return (cy_en_syspm_core_buck_mode_t)(_FLD2VAL(SRSS_PWR_CBUCK_CTL_CBUCK_MODE, SRSS_PWR_CBUCK_CTL));
1405 }
1406
Cy_SysPm_CoreBuckSetInrushLimit(cy_en_syspm_core_inrush_limit_t inrushLimit)1407 void Cy_SysPm_CoreBuckSetInrushLimit(cy_en_syspm_core_inrush_limit_t inrushLimit)
1408 {
1409 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_INRUSH_LIMIT_VALID(inrushLimit));
1410
1411 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL3, SRSS_PWR_CBUCK_CTL3_CBUCK_INRUSH_SEL, inrushLimit);
1412 }
1413
Cy_SysPm_CoreBuckGetInrushLimit(void)1414 cy_en_syspm_core_inrush_limit_t Cy_SysPm_CoreBuckGetInrushLimit(void)
1415 {
1416 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_inrush_limit_t enum.');
1417 return (cy_en_syspm_core_inrush_limit_t)(_FLD2VAL(SRSS_PWR_CBUCK_CTL3_CBUCK_INRUSH_SEL, SRSS_PWR_CBUCK_CTL3));
1418 }
1419
Cy_SysPm_CoreBuckConfig(cy_stc_syspm_core_buck_params_t * config)1420 cy_en_syspm_status_t Cy_SysPm_CoreBuckConfig(cy_stc_syspm_core_buck_params_t *config)
1421 {
1422 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(config->voltageSel));
1423 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(config->mode));
1424 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_INRUSH_LIMIT_VALID(config->inRushLimitSel));
1425
1426 SRSS_PWR_CBUCK_CTL = _VAL2FLD(SRSS_PWR_CBUCK_CTL_CBUCK_VSEL, config->voltageSel) |
1427 _VAL2FLD(SRSS_PWR_CBUCK_CTL_CBUCK_MODE, config->mode);
1428
1429 SRSS_PWR_CBUCK_CTL2 = _VAL2FLD(SRSS_PWR_CBUCK_CTL2_CBUCK_OVERRIDE, ((config->override) ? 1UL : 0UL)) |
1430 _VAL2FLD(SRSS_PWR_CBUCK_CTL2_CBUCK_COPY_SETTINGS, ((config->copySettings) ? 1UL : 0UL)) |
1431 _VAL2FLD(SRSS_PWR_CBUCK_CTL2_CBUCK_USE_SETTINGS, ((config->useSettings) ? 1UL : 0UL));
1432
1433 SRSS_PWR_CBUCK_CTL3 = _VAL2FLD(SRSS_PWR_CBUCK_CTL3_CBUCK_INRUSH_SEL, config->inRushLimitSel);
1434
1435 /* Check if the CBUCK transition is Successful */
1436 return Cy_SysPm_CoreBuckStatus();
1437 }
1438
Cy_SysPm_CoreBuckStatus(void)1439 cy_en_syspm_status_t Cy_SysPm_CoreBuckStatus(void)
1440 {
1441 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
1442 uint32_t syspmCbuckRetry = CY_SYSPM_CBUCK_BUSY_RETRY_COUNT;
1443
1444 while((_FLD2VAL(SRSS_PWR_CBUCK_STATUS_PMU_DONE, SRSS_PWR_CBUCK_STATUS) == 0U) && (syspmCbuckRetry != 0U))
1445 {
1446 syspmCbuckRetry--;
1447 Cy_SysLib_Delay(CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS);
1448 }
1449
1450 if(syspmCbuckRetry != 0UL)
1451 {
1452 retVal = CY_SYSPM_SUCCESS;
1453 }
1454
1455 return retVal;
1456 }
1457
1458 #ifdef ENABLE_MEM_VOLTAGE_TRIMS
Cy_SysPm_SdrConfigure(cy_en_syspm_sdr_t sdr,cy_stc_syspm_sdr_params_t * config)1459 void Cy_SysPm_SdrConfigure(cy_en_syspm_sdr_t sdr, cy_stc_syspm_sdr_params_t *config)
1460 {
1461 CY_ASSERT_L2(CY_SYSPM_IS_SDR_NUM_VALID(sdr));
1462 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(config->coreBuckVoltSel));
1463 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(config->coreBuckMode));
1464 CY_ASSERT_L2(CY_SYSPM_IS_SDR_VOLTAGE_VALID(config->sdrVoltSel));
1465
1466 CY_SYSPM_CORE_BUCK_PAUSE_ENABLE(1U);
1467
1468 if(sdr == CY_SYSPM_SDR_0)
1469 {
1470 cy_en_syspm_sdr_voltage_t currSdr0Volt = Cy_SysPm_SdrGetVoltage(CY_SYSPM_SDR_0);
1471
1472 CY_ASSERT_L2(CY_SYSPM_IS_SDR_VOLTAGE_VALID(config->sdr0DpSlpVoltSel));
1473 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(config->coreBuckDpSlpVoltSel));
1474 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(config->coreBuckDpSlpMode));
1475
1476 /* High to Low voltage --> TRIM first , Set Voltage next */
1477 if(config->sdrVoltSel < ((uint8_t)currSdr0Volt))
1478 {
1479 if(IsVoltageChangePossible())
1480 {
1481 SetMemoryVoltageTrims((cy_en_syspm_sdr_voltage_t)config->sdrVoltSel);
1482 }
1483
1484 SRSS_PWR_SDR0_CTL = _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_VSEL, config->coreBuckVoltSel) |
1485 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_MODE, config->coreBuckMode) |
1486 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_VSEL, config->sdrVoltSel) |
1487 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_VSEL, config->coreBuckDpSlpVoltSel) |
1488 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_MODE, config->coreBuckDpSlpMode) |
1489 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_DPSLP_VSEL, config->sdr0DpSlpVoltSel) |
1490 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_ALLOW_BYPASS, ((config->sdr0Allowbypass) ? 1UL : 0UL));
1491
1492 }
1493 else if(config->sdrVoltSel > ((uint8_t)currSdr0Volt)) /* Low to High voltage --> Set Voltage first , Trim next */
1494 {
1495 SRSS_PWR_SDR0_CTL = _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_VSEL, config->coreBuckVoltSel) |
1496 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_MODE, config->coreBuckMode) |
1497 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_VSEL, config->sdrVoltSel) |
1498 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_VSEL, config->coreBuckDpSlpVoltSel) |
1499 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_MODE, config->coreBuckDpSlpMode) |
1500 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_DPSLP_VSEL, config->sdr0DpSlpVoltSel) |
1501 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_ALLOW_BYPASS, ((config->sdr0Allowbypass) ? 1UL : 0UL));
1502
1503 if(IsVoltageChangePossible())
1504 {
1505 SetMemoryVoltageTrims((cy_en_syspm_sdr_voltage_t)config->sdrVoltSel);
1506 }
1507 }
1508 else
1509 {
1510 SRSS_PWR_SDR0_CTL = _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_VSEL, config->coreBuckVoltSel) |
1511 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_MODE, config->coreBuckMode) |
1512 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_VSEL, config->sdrVoltSel) |
1513 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_VSEL, config->coreBuckDpSlpVoltSel) |
1514 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_MODE, config->coreBuckDpSlpMode) |
1515 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_DPSLP_VSEL, config->sdr0DpSlpVoltSel) |
1516 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_ALLOW_BYPASS, ((config->sdr0Allowbypass) ? 1UL : 0UL));
1517 }
1518 }
1519 else
1520 {
1521 SRSS_PWR_SDR1_CTL = _VAL2FLD(SRSS_PWR_SDR1_CTL_SDR1_CBUCK_VSEL, config->coreBuckVoltSel) |
1522 _VAL2FLD(SRSS_PWR_SDR1_CTL_SDR1_CBUCK_MODE, config->coreBuckMode) |
1523 _VAL2FLD(SRSS_PWR_SDR1_CTL_SDR1_VSEL, config->sdrVoltSel) |
1524 _VAL2FLD(SRSS_PWR_SDR1_CTL_SDR1_HW_SEL, ((config->sdr1HwControl) ? 1UL : 0UL)) |
1525 _VAL2FLD(SRSS_PWR_SDR1_CTL_SDR1_ENABLE, ((config->sdr1Enable) ? 1UL : 0UL));
1526 }
1527
1528 CY_SYSPM_CORE_BUCK_PAUSE_ENABLE(0U);
1529 }
1530
Cy_SysPm_SdrSetVoltage(cy_en_syspm_sdr_t sdr,cy_en_syspm_sdr_voltage_t voltage)1531 void Cy_SysPm_SdrSetVoltage(cy_en_syspm_sdr_t sdr, cy_en_syspm_sdr_voltage_t voltage)
1532 {
1533 CY_ASSERT_L2(CY_SYSPM_IS_SDR_NUM_VALID(sdr));
1534 CY_ASSERT_L2(CY_SYSPM_IS_SDR_VOLTAGE_VALID(voltage));
1535
1536 CY_SYSPM_CORE_BUCK_PAUSE_ENABLE(1U);
1537
1538 if(sdr == CY_SYSPM_SDR_0)
1539 {
1540 cy_en_syspm_sdr_voltage_t currSdr0Volt = Cy_SysPm_SdrGetVoltage(CY_SYSPM_SDR_0);
1541 /* High to Low voltage --> Set TRIM's first , Set Voltage next */
1542 if(voltage < currSdr0Volt)
1543 {
1544 if(IsVoltageChangePossible())
1545 {
1546 SetMemoryVoltageTrims(voltage);
1547 }
1548
1549 CY_REG32_CLR_SET(SRSS_PWR_SDR0_CTL, SRSS_PWR_SDR0_CTL_SDR0_VSEL, voltage);
1550 }
1551 /* Low to High voltage --> Set Voltage first , Set TRIM's next */
1552 else if (voltage > currSdr0Volt)
1553 {
1554 CY_REG32_CLR_SET(SRSS_PWR_SDR0_CTL, SRSS_PWR_SDR0_CTL_SDR0_VSEL, voltage);
1555
1556 if(IsVoltageChangePossible())
1557 {
1558 SetMemoryVoltageTrims(voltage);
1559 }
1560 }
1561 else
1562 {
1563 }
1564 }
1565 else
1566 {
1567 CY_REG32_CLR_SET(SRSS_PWR_SDR1_CTL, SRSS_PWR_SDR1_CTL_SDR1_VSEL, voltage);
1568 }
1569
1570 CY_SYSPM_CORE_BUCK_PAUSE_ENABLE(0U);
1571 }
1572 #endif /* ENABLE_MEM_VOLTAGE_TRIMS */
1573
Cy_SysPm_SdrGetVoltage(cy_en_syspm_sdr_t sdr)1574 cy_en_syspm_sdr_voltage_t Cy_SysPm_SdrGetVoltage(cy_en_syspm_sdr_t sdr)
1575 {
1576 CY_ASSERT_L2(CY_SYSPM_IS_SDR_NUM_VALID(sdr));
1577
1578 if(sdr == CY_SYSPM_SDR_0)
1579 {
1580 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_sdr_voltage_t enum.');
1581 return (cy_en_syspm_sdr_voltage_t)(_FLD2VAL(SRSS_PWR_SDR0_CTL_SDR0_VSEL, SRSS_PWR_SDR0_CTL));
1582 }
1583 else
1584 {
1585 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_sdr_voltage_t enum.');
1586 return (cy_en_syspm_sdr_voltage_t)(_FLD2VAL(SRSS_PWR_SDR1_CTL_SDR1_VSEL, SRSS_PWR_SDR1_CTL));
1587 }
1588 }
1589
Cy_SysPm_SdrEnable(cy_en_syspm_sdr_t sdr,bool enable)1590 void Cy_SysPm_SdrEnable(cy_en_syspm_sdr_t sdr, bool enable)
1591 {
1592 CY_ASSERT_L2(CY_SYSPM_IS_SDR_NUM_VALID(sdr));
1593
1594 if(sdr == CY_SYSPM_SDR_1)
1595 {
1596 CY_REG32_CLR_SET(SRSS_PWR_SDR1_CTL, SRSS_PWR_SDR1_CTL_SDR1_ENABLE, ((enable) ? 1UL : 0UL));
1597 }
1598 }
1599
Cy_SysPm_IsSdrEnabled(cy_en_syspm_sdr_t sdr)1600 bool Cy_SysPm_IsSdrEnabled(cy_en_syspm_sdr_t sdr)
1601 {
1602 CY_ASSERT_L2(CY_SYSPM_IS_SDR_NUM_VALID(sdr));
1603 if(sdr == CY_SYSPM_SDR_0)
1604 {
1605 return (_FLD2BOOL(SRSS_PWR_SDR0_CTL_SDR0_ALLOW_BYPASS, SRSS_PWR_SDR0_CTL)? false : true);
1606 }
1607 else
1608 {
1609 return (_FLD2BOOL(SRSS_PWR_SDR1_CTL_SDR1_ENABLE, SRSS_PWR_SDR1_CTL)? true : false);
1610 }
1611 }
1612
Cy_SysPm_HvLdoConfigure(cy_stc_syspm_hvldo_params_t * config)1613 void Cy_SysPm_HvLdoConfigure(cy_stc_syspm_hvldo_params_t *config)
1614 {
1615 CY_ASSERT_L2(CY_SYSPM_IS_HVLDO_VOLTAGE_VALID(config->voltageSel));
1616
1617 SRSS_PWR_HVLDO0_CTL = _VAL2FLD(SRSS_PWR_HVLDO0_CTL_HVLDO0_VSEL, config->voltageSel) |
1618 _VAL2FLD(SRSS_PWR_HVLDO0_CTL_HVLDO0_HW_SEL, ((config->hwSel) ? 1UL : 0UL)) |
1619 _VAL2FLD(SRSS_PWR_HVLDO0_CTL_HVLDO0_ENABLE, ((config->hvldoEnable) ? 1UL : 0UL));
1620 }
1621
Cy_SysPm_HvLdoEnable(bool enable)1622 void Cy_SysPm_HvLdoEnable(bool enable)
1623 {
1624 CY_REG32_CLR_SET(SRSS_PWR_HVLDO0_CTL, SRSS_PWR_HVLDO0_CTL_HVLDO0_ENABLE, ((enable) ? 1UL : 0UL));
1625 }
1626
Cy_SysPm_IsHvLdoEnabled(void)1627 bool Cy_SysPm_IsHvLdoEnabled(void)
1628 {
1629 return (_FLD2BOOL(SRSS_PWR_HVLDO0_CTL_HVLDO0_ENABLE, SRSS_PWR_HVLDO0_CTL)? true : false);
1630 }
1631
Cy_SysPm_HvLdoSetVoltage(cy_en_syspm_hvldo_voltage_t voltage)1632 void Cy_SysPm_HvLdoSetVoltage(cy_en_syspm_hvldo_voltage_t voltage)
1633 {
1634 CY_ASSERT_L2(CY_SYSPM_IS_HVLDO_VOLTAGE_VALID(voltage));
1635
1636 CY_REG32_CLR_SET(SRSS_PWR_HVLDO0_CTL, SRSS_PWR_HVLDO0_CTL_HVLDO0_VSEL, voltage);
1637 }
1638
Cy_SysPm_HvLdoGetVoltage(void)1639 cy_en_syspm_hvldo_voltage_t Cy_SysPm_HvLdoGetVoltage(void)
1640 {
1641 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_hvldo_voltage_t enum.');
1642 return (cy_en_syspm_hvldo_voltage_t)(_FLD2VAL(SRSS_PWR_HVLDO0_CTL_HVLDO0_VSEL, SRSS_PWR_HVLDO0_CTL));
1643 }
1644
1645
Cy_SysPm_LdoExtraRequesterConfig(cy_stc_syspm_extraReq_params_t * extraReqConfig)1646 cy_en_syspm_status_t Cy_SysPm_LdoExtraRequesterConfig(cy_stc_syspm_extraReq_params_t *extraReqConfig)
1647 {
1648 cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
1649
1650 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(extraReqConfig->coreBuckVoltSel));
1651 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(extraReqConfig->sdr0Config->coreBuckVoltSel));
1652 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(extraReqConfig->sdr0Config->coreBuckMode));
1653 CY_ASSERT_L2(CY_SYSPM_IS_SDR_VOLTAGE_VALID(extraReqConfig->sdr0Config->sdrVoltSel));
1654 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(extraReqConfig->sdr1Config->coreBuckVoltSel));
1655 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(extraReqConfig->sdr1Config->coreBuckMode));
1656 CY_ASSERT_L2(CY_SYSPM_IS_SDR_VOLTAGE_VALID(extraReqConfig->sdr1Config->sdrVoltSel));
1657
1658
1659 /* Extra Requester Sequence */
1660
1661 /* 1. Prevent dynamic setting changes by writing PWR_CBUCK_CTL.CBUCK_PAUSE=1. */
1662 CY_SYSPM_CORE_BUCK_PAUSE_ENABLE(1U);
1663
1664 /* 2. Enable PWR_CBUCK_CTL.CBUCK_COPY_SETTINGS */
1665 CY_SYSPM_CORE_BUCK_COPY_SETTINGS_ENABLE(1U);
1666
1667 /* 3. If the intention is to request higher operational state
1668 * (eg. higher CBUCK target voltage or higher CBUCK mode), load the
1669 * desired settings into the extra requester
1670 * (PWR_CBUCK_CTL.CBUCK_VSEL/MODE). Do not reduce any of the
1671 * settings, because the intention is that the eventual
1672 * composite CBUCK mode matches the extra requester
1673 */
1674 (void)Cy_SysPm_CoreBuckSetVoltage((cy_en_syspm_core_buck_voltage_t)extraReqConfig->coreBuckVoltSel);
1675
1676 (void)Cy_SysPm_CoreBuckSetMode((cy_en_syspm_core_buck_mode_t)extraReqConfig->coreBuckMode);
1677
1678 /* 4. Override the normal harmonization logic which internally selects the
1679 * scratch profile using PWR_CBUCK_CTL.CBUCK_OVERRIDE).
1680 */
1681 CY_SYSPM_CORE_BUCK_OVERRRIDE_ENABLE(1U);
1682
1683 /* 5. Wait until the status register indicates the transition is completed.
1684 * See PWR_CBUCK_STATUS.PMU_DONE.
1685 */
1686 retVal = Cy_SysPm_CoreBuckStatus();
1687
1688 if(retVal == CY_SYSPM_SUCCESS)
1689 {
1690 /* 6. Update the desired SDR requester. This is safe to do, because it is
1691 * not the selected profile and there is no transition in progress, so it
1692 * will not have any effect on a CBUCK profile.
1693 */
1694
1695 SRSS_PWR_SDR0_CTL = _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_VSEL, extraReqConfig->sdr0Config->coreBuckVoltSel) |
1696 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_CBUCK_MODE, extraReqConfig->sdr0Config->coreBuckMode) |
1697 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_VSEL, extraReqConfig->sdr0Config->sdrVoltSel) |
1698 _VAL2FLD(SRSS_PWR_SDR0_CTL_SDR0_ALLOW_BYPASS, ((extraReqConfig->sdr0Config->sdr0Allowbypass) ? 1UL : 0UL));
1699
1700 SRSS_PWR_SDR1_CTL = _VAL2FLD(SRSS_PWR_SDR1_CTL_SDR1_CBUCK_VSEL, extraReqConfig->sdr1Config->coreBuckVoltSel) |
1701 _VAL2FLD(SRSS_PWR_SDR1_CTL_SDR1_CBUCK_MODE, extraReqConfig->sdr1Config->coreBuckMode) |
1702 _VAL2FLD(SRSS_PWR_SDR1_CTL_SDR1_VSEL, extraReqConfig->sdr1Config->sdrVoltSel) |
1703 _VAL2FLD(SRSS_PWR_SDR1_CTL_SDR1_HW_SEL, ((extraReqConfig->sdr1Config->sdr1HwControl) ? 1UL : 0UL)) |
1704 _VAL2FLD(SRSS_PWR_SDR1_CTL_SDR1_ENABLE, ((extraReqConfig->sdr1Config->sdr1Enable) ? 1UL : 0UL));
1705
1706 }
1707
1708 /* 7. Remove overrides by clearing CBUCK_OVERRIDE and CBUCK_PAUSE */
1709 CY_SYSPM_CORE_BUCK_OVERRRIDE_ENABLE(0U);
1710 CY_SYSPM_CORE_BUCK_PAUSE_ENABLE(0U);
1711
1712 /* 8. Wait until the status register indicates the transition is
1713 * completed. See PWR_CBUCK_STATUS.PMU_DONE.
1714 */
1715 retVal = Cy_SysPm_CoreBuckStatus();
1716
1717 return retVal;
1718 }
1719
1720
Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t * handler)1721 bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler)
1722 {
1723 bool retVal = false;
1724
1725 /* Verify the input parameters. */
1726 if ((handler != NULL) && (handler->callbackParams != NULL) && (handler->callback != NULL))
1727 {
1728 uint32_t callbackRootIdx = (uint32_t) handler->type;
1729
1730 /* If the callback list is not empty. */
1731 if (pmCallbackRoot[callbackRootIdx] != NULL)
1732 {
1733 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
1734 cy_stc_syspm_callback_t* insertPos = curCallback;
1735
1736 /* Find the callback after which the new callback is to be
1737 * inserted. Ensure the given callback has not been registered.
1738 */
1739 while ((NULL != curCallback->nextItm) && (curCallback != handler))
1740 {
1741 curCallback = curCallback->nextItm;
1742 /* Callbacks with the same order value are stored in the order
1743 * they are registered.
1744 */
1745 if (curCallback->order <= handler->order)
1746 {
1747 insertPos = curCallback;
1748 }
1749 }
1750 /* If the callback has not been registered. */
1751 if (curCallback != handler)
1752 {
1753 /* If the callback is to be inserted at the beginning of the list. */
1754 if ((insertPos->prevItm == NULL) && (handler->order < insertPos->order))
1755 {
1756 handler->nextItm = insertPos;
1757 handler->prevItm = NULL;
1758 handler->nextItm->prevItm = handler;
1759 pmCallbackRoot[callbackRootIdx] = handler;
1760 }
1761 else
1762 {
1763 handler->nextItm = insertPos->nextItm;
1764 handler->prevItm = insertPos;
1765
1766 /* If the callback is not inserted at the end of the list. */
1767 if (handler->nextItm != NULL)
1768 {
1769 handler->nextItm->prevItm = handler;
1770 }
1771 insertPos->nextItm = handler;
1772 }
1773 retVal = true;
1774 }
1775 }
1776 else
1777 {
1778 /* The callback list is empty. */
1779 pmCallbackRoot[callbackRootIdx] = handler;
1780 handler->nextItm = NULL;
1781 handler->prevItm = NULL;
1782 retVal = true;
1783 }
1784 }
1785 return retVal;
1786 }
1787
Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const * handler)1788 bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler)
1789 {
1790 bool retVal = false;
1791
1792 if (handler != NULL)
1793 {
1794 uint32_t callbackRootIdx = (uint32_t) handler->type;
1795 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
1796
1797 /* Search requested callback item in the linked list */
1798 while (curCallback != NULL)
1799 {
1800 /* Requested callback is found */
1801 if (curCallback == handler)
1802 {
1803 retVal = true;
1804 break;
1805 }
1806
1807 /* Go to next callback item in the linked list */
1808 curCallback = curCallback->nextItm;
1809 }
1810
1811 if (retVal)
1812 {
1813 /* Requested callback is first in the list */
1814 if (pmCallbackRoot[callbackRootIdx] == handler)
1815 {
1816 /* Check whether this the only callback registered */
1817 if (pmCallbackRoot[callbackRootIdx]->nextItm != NULL)
1818 {
1819 pmCallbackRoot[callbackRootIdx] = pmCallbackRoot[callbackRootIdx]->nextItm;
1820 pmCallbackRoot[callbackRootIdx]->prevItm = NULL;
1821 }
1822 else
1823 {
1824 /* We had only one callback */
1825 pmCallbackRoot[callbackRootIdx] = NULL;
1826 }
1827 }
1828 else
1829 {
1830 /* Update links of related to unregistered callback items */
1831 curCallback->prevItm->nextItm = curCallback->nextItm;
1832
1833 if (curCallback->nextItm != NULL)
1834 {
1835 curCallback->nextItm->prevItm = curCallback->prevItm;
1836 }
1837 }
1838 }
1839 }
1840
1841 return retVal;
1842 }
1843
Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type,cy_en_syspm_callback_mode_t mode)1844 cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode)
1845 {
1846 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type));
1847 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode));
1848
1849 static cy_stc_syspm_callback_t* lastExecutedCallback = NULL;
1850 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
1851 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[(uint32_t) type];
1852 cy_stc_syspm_callback_params_t curParams;
1853
1854 if ((mode == CY_SYSPM_BEFORE_TRANSITION) || (mode == CY_SYSPM_CHECK_READY))
1855 {
1856 /* Execute registered callbacks with order from first registered to the
1857 * last registered. Stop executing if CY_SYSPM_FAIL was returned in
1858 * CY_SYSPM_CHECK_READY mode
1859 */
1860 while ((curCallback != NULL) && ((retVal != CY_SYSPM_FAIL) || (mode != CY_SYSPM_CHECK_READY)))
1861 {
1862 /* The modes defined in the .skipMode element are not executed */
1863 if (0UL == ((uint32_t) mode & curCallback->skipMode))
1864 {
1865 /* Update elements for local callback parameter values */
1866 curParams.base = curCallback->callbackParams->base;
1867 curParams.context = curCallback->callbackParams->context;
1868
1869 retVal = curCallback->callback(&curParams, mode);
1870
1871 /* Update callback pointer with value of executed callback.
1872 * Such update is required to execute further callbacks in
1873 * backward order after exit from LP mode or to undo
1874 * configuration after callback returned fail: from last called
1875 * to first registered.
1876 */
1877 lastExecutedCallback = curCallback;
1878 }
1879 curCallback = curCallback->nextItm;
1880 }
1881
1882 if (mode == CY_SYSPM_CHECK_READY)
1883 {
1884 /* Update the pointer to the failed callback with the result of the callback execution.
1885 * If the callback fails, the value of the pointer will be updated
1886 * with the address of the callback which returned CY_SYSPM_FAIL, else,
1887 * it will be updated with NULL.
1888 */
1889 if(retVal == CY_SYSPM_FAIL)
1890 {
1891 failedCallback[(uint32_t) type] = lastExecutedCallback;
1892 }
1893 else
1894 {
1895 failedCallback[(uint32_t) type] = NULL;
1896 }
1897 }
1898 }
1899 else
1900 {
1901 /* Execute registered callbacks with order from lastCallback or last
1902 * executed to the first registered callback. Such a flow is required if
1903 * a previous callback function returned CY_SYSPM_FAIL or a previous
1904 * callback mode was CY_SYSPM_BEFORE_TRANSITION. Such an order is
1905 * required to undo configurations in correct backward order.
1906 */
1907 if (mode != CY_SYSPM_CHECK_FAIL)
1908 {
1909 while (curCallback->nextItm != NULL)
1910 {
1911 curCallback = curCallback->nextItm;
1912 }
1913 }
1914 else
1915 {
1916 /* Skip last executed callback that returns CY_SYSPM_FAIL, as this
1917 * callback already knows that it failed.
1918 */
1919 curCallback = lastExecutedCallback;
1920
1921 if (curCallback != NULL)
1922 {
1923 curCallback = curCallback->prevItm;
1924 }
1925 }
1926
1927 /* Execute callback functions with required type and mode */
1928 while (curCallback != NULL)
1929 {
1930 /* The modes defined in the .skipMode element are not executed */
1931 if (0UL == ((uint32_t) mode & curCallback->skipMode))
1932 {
1933 /* Update elements for local callback parameter values */
1934 curParams.base = curCallback->callbackParams->base;
1935 curParams.context = curCallback->callbackParams->context;
1936
1937 retVal = curCallback->callback(&curParams, mode);
1938 }
1939 curCallback = curCallback->prevItm;
1940 }
1941 }
1942
1943 return retVal;
1944 }
1945
Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type)1946 cy_stc_syspm_callback_t* Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type)
1947 {
1948 return failedCallback[(uint32_t) type];
1949 }
1950
Cy_SysPm_IoUnfreeze(void)1951 void Cy_SysPm_IoUnfreeze(void)
1952 {
1953 uint32_t interruptState;
1954 interruptState = Cy_SysLib_EnterCriticalSection();
1955
1956 /* Preserve the last reset reason and wakeup polarity. Then, unfreeze I/O:
1957 * write PWR_HIBERNATE.FREEZE=0, .UNLOCK=0x3A, .HIBERANTE=0
1958 */
1959 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_RETAIN_STATUS_MASK) | HIBERNATE_UNLOCK_VAL;
1960
1961 /* Lock the Hibernate mode:
1962 * write PWR_HIBERNATE.HIBERNATE=0, UNLOCK=0x00, HIBERANTE=0
1963 */
1964 SRSS_PWR_HIBERNATE &= HIBERNATE_RETAIN_STATUS_MASK;
1965
1966 /* Read register to make sure it is settled */
1967 (void) SRSS_PWR_HIBERNATE;
1968
1969 Cy_SysLib_ExitCriticalSection(interruptState);
1970 }
1971
Cy_SysPm_IoIsFrozen(void)1972 bool Cy_SysPm_IoIsFrozen(void)
1973 {
1974 return (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_FREEZE, SRSS_PWR_HIBERNATE));
1975 }
1976
Cy_SysPm_DeepSleepIoUnfreeze(void)1977 void Cy_SysPm_DeepSleepIoUnfreeze(void)
1978 {
1979 uint32_t interruptState;
1980 interruptState = Cy_SysLib_EnterCriticalSection();
1981
1982 /* Unfreeze IO's which are frozen during DEEPSLEEP-RAM/OFF
1983 * Entry
1984 */
1985 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_FREEZE_DPSLP_Msk;
1986
1987 Cy_SysLib_ExitCriticalSection(interruptState);
1988 }
1989
Cy_SysPm_DeepSleepIoIsFrozen(void)1990 bool Cy_SysPm_DeepSleepIoIsFrozen(void)
1991 {
1992 return (0U != _FLD2VAL(SRSS_PWR_CTL2_FREEZE_DPSLP, SRSS_PWR_CTL2));
1993 }
1994
1995
Cy_SysPm_CpuSendWakeupEvent(void)1996 void Cy_SysPm_CpuSendWakeupEvent(void)
1997 {
1998 __SEV();
1999 }
2000
Cy_SysPm_IsLpmReady(void)2001 bool Cy_SysPm_IsLpmReady(void)
2002 {
2003 return (_FLD2BOOL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL)? true : false);
2004 }
2005
Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl)2006 void Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl)
2007 {
2008 CY_ASSERT_L3(CY_SYSPM_IS_VDDBACKUP_VALID(vddBackControl));
2009
2010 BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_VDDBAK_CTL, (uint32_t) vddBackControl);
2011 }
2012
2013
Cy_SysPm_BackupGetSupply(void)2014 cy_en_syspm_vddbackup_control_t Cy_SysPm_BackupGetSupply(void)
2015 {
2016 uint32_t retVal;
2017 retVal = _FLD2VAL(BACKUP_CTL_VDDBAK_CTL, BACKUP_CTL);
2018
2019 return ((cy_en_syspm_vddbackup_control_t) retVal);
2020 }
2021
2022
Cy_SysPm_BackupEnableVoltageMeasurement(void)2023 void Cy_SysPm_BackupEnableVoltageMeasurement(void)
2024 {
2025 BACKUP_CTL |= BACKUP_CTL_VBACKUP_MEAS_Msk;
2026 }
2027
2028
Cy_SysPm_BackupDisableVoltageMeasurement(void)2029 void Cy_SysPm_BackupDisableVoltageMeasurement(void)
2030 {
2031 BACKUP_CTL &= ((uint32_t) ~BACKUP_CTL_VBACKUP_MEAS_Msk);
2032 }
2033
2034
Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key)2035 void Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key)
2036 {
2037 CY_ASSERT_L3(CY_SYSPM_IS_SC_CHARGE_KEY_VALID(key));
2038
2039 if(key == CY_SYSPM_SC_CHARGE_ENABLE)
2040 {
2041 BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_EN_CHARGE_KEY, (uint32_t) CY_SYSPM_SC_CHARGE_ENABLE);
2042 }
2043 else
2044 {
2045 BACKUP_CTL &= ((uint32_t) ~BACKUP_CTL_EN_CHARGE_KEY_Msk);
2046 }
2047 }
2048
Cy_SysPm_BackupWordStore(uint32_t wordIndex,uint32_t * wordSrcPointer,uint32_t wordSize)2049 void Cy_SysPm_BackupWordStore(uint32_t wordIndex, uint32_t *wordSrcPointer, uint32_t wordSize)
2050 {
2051 CY_ASSERT_L3(CY_SYSPM_IS_WORD_INDEX_VALID(wordIndex));
2052 CY_ASSERT_L3(CY_SYSPM_IS_WORD_SIZE_VALID(wordSize + wordIndex));
2053
2054 while(wordSize != 0UL)
2055 {
2056 if(wordIndex < CY_SRSS_BACKUP_BREG1_START_POS)
2057 {
2058 BACKUP_BREG_SET0[wordIndex] = *wordSrcPointer;
2059 }
2060 else if(wordIndex < CY_SRSS_BACKUP_BREG2_START_POS)
2061 {
2062 BACKUP_BREG_SET1[wordIndex - CY_SRSS_BACKUP_BREG1_START_POS] = *wordSrcPointer;
2063 }
2064 else if(wordIndex < CY_SRSS_BACKUP_BREG3_START_POS)
2065 {
2066 BACKUP_BREG_SET2[wordIndex - CY_SRSS_BACKUP_BREG2_START_POS] = *wordSrcPointer;
2067 }
2068 else
2069 {
2070 BACKUP_BREG_SET3[wordIndex - CY_SRSS_BACKUP_BREG3_START_POS] = *wordSrcPointer;
2071 }
2072
2073 wordIndex++;
2074 wordSrcPointer++;
2075 wordSize--;
2076 }
2077 }
2078
Cy_SysPm_BackupWordReStore(uint32_t wordIndex,uint32_t * wordDstPointer,uint32_t wordSize)2079 void Cy_SysPm_BackupWordReStore(uint32_t wordIndex, uint32_t *wordDstPointer, uint32_t wordSize)
2080 {
2081 CY_ASSERT_L3(CY_SYSPM_IS_WORD_INDEX_VALID(wordIndex));
2082 CY_ASSERT_L3(CY_SYSPM_IS_WORD_SIZE_VALID(wordSize + wordIndex));
2083
2084 while(wordSize != 0UL)
2085 {
2086
2087 if(wordIndex < CY_SRSS_BACKUP_BREG1_START_POS)
2088 {
2089 *wordDstPointer = BACKUP_BREG_SET0[wordIndex];
2090 }
2091 else if(wordIndex < CY_SRSS_BACKUP_BREG2_START_POS)
2092 {
2093 *wordDstPointer = BACKUP_BREG_SET1[wordIndex - CY_SRSS_BACKUP_BREG1_START_POS];
2094 }
2095 else if(wordIndex < CY_SRSS_BACKUP_BREG3_START_POS)
2096 {
2097 *wordDstPointer = BACKUP_BREG_SET2[wordIndex - CY_SRSS_BACKUP_BREG2_START_POS];
2098 }
2099 else
2100 {
2101 *wordDstPointer = BACKUP_BREG_SET3[wordIndex - CY_SRSS_BACKUP_BREG3_START_POS];
2102 }
2103
2104 wordIndex++;
2105 wordDstPointer++;
2106 wordSize--;
2107 }
2108 }
2109
2110 /* This API is an inline version of Cy_SysPm_SetSRAMMacroPwrMode */
Cy_SysPm_SetSRAMMacroPwrModeInline(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)2111 __STATIC_FORCEINLINE cy_en_syspm_status_t Cy_SysPm_SetSRAMMacroPwrModeInline(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
2112 {
2113 CY_ASSERT_L3(sramNum == CY_SYSPM_SRAM0_MEMORY);
2114 CY_ASSERT_L3((sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_ON) || (sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_OFF));
2115 CY_ASSERT_L3(sramMacroNum < CY_CPUSS_RAMC0_MACRO_NR);
2116
2117 CY_UNUSED_PARAM(sramNum);
2118
2119 /* Unlock PWR MACRO Control */
2120 /* Clear bit 0(CLR0)*/
2121 MXSRAMC_PWR_MACRO_CTL_LOCK = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0;
2122 /* Clear bit 1(CLR1)*/
2123 MXSRAMC_PWR_MACRO_CTL_LOCK = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR1;
2124
2125 if(sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_ON)
2126 {
2127 /* Enable the Macro Number */
2128 MXSRAMC_PWR_MACRO_CTL &= ~(0x1UL << (uint32_t)sramMacroNum);
2129 }
2130 else
2131 {
2132 /* Disable the Macro Number */
2133 MXSRAMC_PWR_MACRO_CTL |= (0x1UL << (uint32_t)sramMacroNum);
2134 }
2135 /* Wait for the PWR_DONE status */
2136 while(!_FLD2BOOL(RAMC_STATUS_PWR_DONE, MXSRAMC_STATUS)){}
2137
2138 /* Lock PWR MACRO Control(Set SET01) */
2139 MXSRAMC_PWR_MACRO_CTL_LOCK = MXSRAMC_PWR_MACRO_CTL_LOCK_SET01;
2140
2141 return CY_SYSPM_SUCCESS;
2142 }
2143
Cy_SysPm_SetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)2144 cy_en_syspm_status_t Cy_SysPm_SetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
2145 {
2146 return Cy_SysPm_SetSRAMMacroPwrModeInline(sramNum, sramMacroNum, sramPwrMode);
2147 }
2148
Cy_SysPm_GetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum)2149 cy_en_syspm_sram_pwr_mode_t Cy_SysPm_GetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum)
2150 {
2151 cy_en_syspm_sram_pwr_mode_t value;
2152
2153 CY_ASSERT_L3(sramNum == CY_SYSPM_SRAM0_MEMORY);
2154 CY_ASSERT_L3(sramMacroNum < CY_CPUSS_RAMC0_MACRO_NR);
2155
2156 CY_UNUSED_PARAM(sramNum);
2157
2158 /* Unlock PWR MACRO Control */
2159 /* Clear bit 0(CLR0)*/
2160 MXSRAMC_PWR_MACRO_CTL_LOCK = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0;
2161 /* Clear bit 1(CLR1)*/
2162 MXSRAMC_PWR_MACRO_CTL_LOCK = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR1;
2163
2164 value = ((MXSRAMC_PWR_MACRO_CTL & (0x1UL << (uint32_t)sramMacroNum)) != 0UL) ? CY_SYSPM_SRAM_PWR_MODE_OFF:CY_SYSPM_SRAM_PWR_MODE_ON;
2165
2166 /* Lock PWR MACRO Control(Set SET01) */
2167 MXSRAMC_PWR_MACRO_CTL_LOCK = MXSRAMC_PWR_MACRO_CTL_LOCK_SET01;
2168
2169 return value;
2170
2171 }
2172
2173
Cy_SysPm_SetSRAMPwrMode(cy_en_syspm_sram_index_t sramNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)2174 cy_en_syspm_status_t Cy_SysPm_SetSRAMPwrMode(cy_en_syspm_sram_index_t sramNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
2175 {
2176 CY_ASSERT_L3(sramNum == CY_SYSPM_SRAM0_MEMORY);
2177 CY_ASSERT_L3((sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_ON) || (sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_OFF));
2178
2179 CY_UNUSED_PARAM(sramNum);
2180
2181 (void)Cy_SysPm_SetSRAMMacroPwrMode(CY_SYSPM_SRAM0_MEMORY, (uint32_t)CY_SYSPM_SRAM0_MACRO_0, sramPwrMode);
2182 (void)Cy_SysPm_SetSRAMMacroPwrMode(CY_SYSPM_SRAM0_MEMORY, (uint32_t)CY_SYSPM_SRAM0_MACRO_1, sramPwrMode);
2183
2184 return CY_SYSPM_SUCCESS;
2185 }
2186
2187 /*This reset handler will be implemented as part of HCI ROM app*/
Cy_SysPm_Dsramoff_Entry(void)2188 __WEAK void Cy_SysPm_Dsramoff_Entry(void)
2189 {
2190 while(true) {}
2191 }
2192
Cy_SysPm_CpuEnterRAMOffDeepSleep(void)2193 cy_en_syspm_status_t Cy_SysPm_CpuEnterRAMOffDeepSleep(void)
2194 {
2195 uint32_t interruptState;
2196 uint32_t cbDeepSleepRootIdx = (uint32_t) Cy_SysPm_GetDeepSleepMode();
2197 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2198
2199 CY_ASSERT_L3(CY_SYSPM_IS_DEEPSLEEP_MODE_VALID(cbDeepSleepRootIdx));
2200
2201 //Check if LPM is ready
2202 if(!Cy_SysPm_IsLpmReady())
2203 {
2204 retVal = CY_SYSPM_FAIL;
2205 }
2206 else
2207 {
2208 //TBD Check if PDCM Dependencies are set properly
2209
2210 /* Call the registered callback functions with the CY_SYSPM_CHECK_READY
2211 * parameter
2212 */
2213 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
2214 {
2215 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_READY);
2216 }
2217
2218 /* The CPU can switch into the Deep Sleep power mode only when
2219 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
2220 * parameter return CY_SYSPM_SUCCESS
2221 */
2222 if (retVal == CY_SYSPM_SUCCESS)
2223 {
2224 /* Call the registered callback functions with the
2225 * CY_SYSPM_BEFORE_TRANSITION parameter
2226 */
2227 interruptState = Cy_SysLib_EnterCriticalSection();
2228 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
2229 {
2230 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION);
2231 }
2232 /* The CPU enters Deep Sleep mode upon execution of WFI/WFE
2233 * use Cy_SysPm_SetDeepSleepMode to set various deepsleep modes TBD*/
2234 SCB_SCR |= SCB_SCR_SLEEPDEEP_Msk;
2235
2236 /* Disable SRAM Macros to save power */
2237 (void)Cy_SysPm_SetSRAMMacroPwrModeInline(CY_SYSPM_SRAM0_MEMORY, (uint32_t)CY_SYSPM_SRAM0_MACRO_0, CY_SYSPM_SRAM_PWR_MODE_OFF);
2238
2239 __WFI();
2240
2241 /* Enable SRAM Macros as DEEPSLEEP_RAM might have failed if we reach this point */
2242 (void)Cy_SysPm_SetSRAMMacroPwrModeInline(CY_SYSPM_SRAM0_MEMORY, (uint32_t)CY_SYSPM_SRAM0_MACRO_0, CY_SYSPM_SRAM_PWR_MODE_ON);
2243
2244 /* Jump to HCI ROM app Reset handler */
2245 Cy_SysPm_Dsramoff_Entry();
2246
2247 Cy_SysLib_ExitCriticalSection(interruptState);
2248 }
2249 else
2250 {
2251 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
2252 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
2253 * parameter
2254 */
2255 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
2256 {
2257 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_FAIL);
2258 }
2259 }
2260 }
2261 return retVal;
2262 }
2263
Cy_SysPm_TriggerSoftReset(void)2264 void Cy_SysPm_TriggerSoftReset(void)
2265 {
2266 SRSS_RES_SOFT_CTL = SRSS_RES_SOFT_CTL_TRIGGER_SOFT_Msk;
2267 }
2268
Cy_SysPm_TriggerXRes(void)2269 void Cy_SysPm_TriggerXRes(void)
2270 {
2271 SRSS_RES_PXRES_CTL = SRSS_RES_PXRES_CTL_PXRES_TRIGGER_Msk;
2272 }
2273
2274
2275 #ifdef ENABLE_MEM_VOLTAGE_TRIMS
2276 /*******************************************************************************
2277 * Function Name: SetMemoryVoltageTrims
2278 ****************************************************************************//**
2279 *
2280 * This is the internal function that updates the trim values for the
2281 * RAM and ROM. The trim update is done during transition of regulator voltage
2282 * from higher to a lower one.
2283 *
2284 *******************************************************************************/
SetMemoryVoltageTrims(cy_en_syspm_sdr_voltage_t voltage)2285 static void SetMemoryVoltageTrims(cy_en_syspm_sdr_voltage_t voltage)
2286 {
2287 uint32_t ramVoltgeTrim = CPUSS_TRIM_RAM_CTL;
2288 uint32_t romVoltgeTrim = CPUSS_TRIM_ROM_CTL;
2289
2290 CY_ASSERT_L3(CY_SYSPM_IS_SDR_TRIM_VOLTAGE_VALID(voltage));
2291
2292 switch(voltage)
2293 {
2294 case CY_SYSPM_SDR_VOLTAGE_0_900V:
2295 {
2296 ramVoltgeTrim = CPUSS_TRIM_RAM_VOLT_0_900;
2297 romVoltgeTrim = CPUSS_TRIM_ROM_VOLT_0_900;
2298 }
2299 break;
2300
2301 case CY_SYSPM_SDR_VOLTAGE_1_000V:
2302 {
2303 ramVoltgeTrim = CPUSS_TRIM_RAM_VOLT_1_000;
2304 romVoltgeTrim = CPUSS_TRIM_ROM_VOLT_1_000;
2305 }
2306 break;
2307
2308 case CY_SYSPM_SDR_VOLTAGE_1_100V:
2309 {
2310 ramVoltgeTrim = CPUSS_TRIM_RAM_VOLT_1_100;
2311 romVoltgeTrim = CPUSS_TRIM_ROM_VOLT_1_100;
2312 }
2313 break;
2314
2315 default:
2316 {
2317 CY_ASSERT_L2(false);
2318 }
2319 break;
2320 }
2321
2322 CPUSS_TRIM_RAM_CTL = ramVoltgeTrim;
2323 CPUSS_TRIM_ROM_CTL = romVoltgeTrim;
2324
2325 }
2326 #endif /* ENABLE_MEM_VOLTAGE_TRIMS */
2327
2328 #if defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)
2329
2330 /*******************************************************************************
2331 * Function Name: SetReadMarginTrimUlp
2332 ****************************************************************************//**
2333 *
2334 * This is the internal function that updates the read-margin trim values for the
2335 * RAM and ROM. The trim update is done during transition of regulator voltage
2336 * from higher to a lower one.
2337 *
2338 *******************************************************************************/
SetReadMarginTrimUlp(void)2339 static void SetReadMarginTrimUlp(void)
2340 {
2341 SRSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP & ((uint32_t) ~SRSS_TRIM_RAM_CTL_RA_MASK)) |
2342 (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_RA_MASK);
2343
2344 SRSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP;
2345 }
2346
2347
2348 /*******************************************************************************
2349 * Function Name: SetReadMarginTrimLp
2350 ****************************************************************************//**
2351 *
2352 * The internal function that updates the read-margin trim values for the
2353 * RAM and ROM. The trim update is done during transition of regulator voltage
2354 * from a lower to a higher one.
2355 *
2356 *******************************************************************************/
SetReadMarginTrimLp(void)2357 static void SetReadMarginTrimLp(void)
2358 {
2359 SRSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_LP & ((uint32_t) ~SRSS_TRIM_RAM_CTL_RA_MASK)) |
2360 (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_RA_MASK);
2361
2362 SRSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_LP;
2363
2364 }
2365
2366
2367 /*******************************************************************************
2368 * Function Name: SetReadMarginTrimMf
2369 ****************************************************************************//**
2370 *
2371 * The internal function that updates the read-margin trim values for the
2372 * RAM and ROM. The trim update is done during transition of regulator voltage
2373 * from a lower to a higher one.
2374 *
2375 *******************************************************************************/
SetReadMarginTrimMf(void)2376 static void SetReadMarginTrimMf(void)
2377 {
2378 SRSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_LP & ((uint32_t) ~SRSS_TRIM_RAM_CTL_RA_MASK)) |
2379 (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_RA_MASK);
2380
2381 SRSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_LP;
2382 }
2383
2384
2385 /*******************************************************************************
2386 * Function Name: SetReadMarginTrimOd
2387 ****************************************************************************//**
2388 *
2389 * The internal function that updates the read-margin trim values for the
2390 * RAM and ROM. The trim update is done during transition of regulator voltage
2391 * from a lower to a higher one.
2392 *
2393 *******************************************************************************/
SetReadMarginTrimOd(void)2394 static void SetReadMarginTrimOd(void)
2395 {
2396 SRSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_LP & ((uint32_t) ~SRSS_TRIM_RAM_CTL_RA_MASK)) |
2397 (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_RA_MASK);
2398
2399 SRSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_LP;
2400 }
2401
2402
2403 /*******************************************************************************
2404 * Function Name: SetWriteAssistTrimUlp
2405 ****************************************************************************//**
2406 *
2407 * The internal function that updates the write assistant trim value for the
2408 * RAM. The trim update is done during transition of regulator voltage
2409 * from higher to a lower.
2410 *
2411 *******************************************************************************/
SetWriteAssistTrimUlp(void)2412 static void SetWriteAssistTrimUlp(void)
2413 {
2414 SRSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_ULP & ((uint32_t) ~SRSS_TRIM_RAM_CTL_RA_MASK)) |
2415 (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_RA_MASK);
2416 }
2417
2418
2419 /*******************************************************************************
2420 * Function Name: SetWriteAssistTrimLp
2421 ****************************************************************************//**
2422 *
2423 * The internal function that updates the write assistant trim value for the
2424 * RAM. The trim update is done during transition of regulator voltage
2425 * from lower to a higher one.
2426 *
2427 *******************************************************************************/
SetWriteAssistTrimLp(void)2428 static void SetWriteAssistTrimLp(void)
2429 {
2430 SRSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP & ((uint32_t) ~SRSS_TRIM_RAM_CTL_RA_MASK)) |
2431 (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_RA_MASK);
2432
2433 SRSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP;
2434 }
2435
2436
2437 /*******************************************************************************
2438 * Function Name: SetWriteAssistTrimMf
2439 ****************************************************************************//**
2440 *
2441 * The internal function that updates the write assistant trim value for the
2442 * RAM. The trim update is done during transition of regulator voltage
2443 * from lower to a higher one.
2444 *
2445 *******************************************************************************/
SetWriteAssistTrimMf(void)2446 static void SetWriteAssistTrimMf(void)
2447 {
2448 SRSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP & ((uint32_t) ~SRSS_TRIM_RAM_CTL_RA_MASK)) |
2449 (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_RA_MASK);
2450
2451 SRSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP;
2452 }
2453
2454
2455 /*******************************************************************************
2456 * Function Name: SetWriteAssistTrimOd
2457 ****************************************************************************//**
2458 *
2459 * The internal function that updates the write assistant trim value for the
2460 * RAM. The trim update is done during transition of regulator voltage
2461 * from lower to a higher one.
2462 *
2463 *******************************************************************************/
SetWriteAssistTrimOd(void)2464 static void SetWriteAssistTrimOd(void)
2465 {
2466 SRSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP & ((uint32_t) ~SRSS_TRIM_RAM_CTL_RA_MASK)) |
2467 (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_RA_MASK);
2468
2469 SRSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP;
2470 }
2471 #endif
2472
2473 /*******************************************************************************
2474 * Function Name: IsVoltageChangePossible
2475 ****************************************************************************//**
2476 *
2477 * The internal function that checks wherever it is possible to change the core
2478 * voltage. Voltage change is possible only when the specific device revision
2479 * support registers modification.
2480 *
2481 *******************************************************************************/
IsVoltageChangePossible(void)2482 static bool IsVoltageChangePossible(void)
2483 {
2484
2485 bool retVal = false;
2486 #if defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)
2487
2488 uint32_t trimRamCheckVal = (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_WC_MASK);
2489
2490 SRSS_TRIM_RAM_CTL &= ~SRSS_TRIM_RAM_CTL_WC_MASK;
2491 SRSS_TRIM_RAM_CTL |= ((~trimRamCheckVal) & SRSS_TRIM_RAM_CTL_WC_MASK);
2492
2493 retVal = (trimRamCheckVal != (SRSS_TRIM_RAM_CTL & SRSS_TRIM_RAM_CTL_WC_MASK));
2494
2495 #elif (CY_SYSLIB_GET_SILICON_REV_ID != CY_SYSLIB_20829A0_SILICON_REV)
2496 {
2497 uint32_t trimRamCheckVal = (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK);
2498
2499 CPUSS_TRIM_RAM_CTL &= ~CPUSS_TRIM_RAM_CTL_WC_MASK;
2500 CPUSS_TRIM_RAM_CTL |= ((~trimRamCheckVal) & CPUSS_TRIM_RAM_CTL_WC_MASK);
2501
2502 retVal = (trimRamCheckVal != (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK));
2503 }
2504 #endif
2505
2506 return retVal;
2507 }
2508
2509
2510 #if (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL))
2511
Cy_SysPm_ReadStatus(void)2512 uint32_t Cy_SysPm_ReadStatus(void)
2513 {
2514 uint32_t pmStatus = 0UL;
2515
2516 /* Check whether the device is in LP, MF, ULP, OD mode by reading
2517 * the core voltage:
2518 * - 0.9V (nominal) - System ULP mode
2519 * - 1.0V (nominal) - System MF mode
2520 * - 1.1V (nominal) - System LP mode
2521 * - 1.2V (nominal) - System OD mode
2522 */
2523
2524 /* Read current active regulator */
2525 if (Cy_SysPm_LdoIsEnabled())
2526 {
2527 /* Current active regulator is LDO */
2528 if (Cy_SysPm_LdoGetVoltage() == CY_SYSPM_LDO_VOLTAGE_LP)
2529 {
2530 pmStatus |= CY_SYSPM_STATUS_SYSTEM_LP;
2531 }
2532 else if (Cy_SysPm_LdoGetVoltage() == CY_SYSPM_LDO_VOLTAGE_ULP)
2533 {
2534 pmStatus |= CY_SYSPM_STATUS_SYSTEM_ULP;
2535 }
2536 else if (Cy_SysPm_LdoGetVoltage() == CY_SYSPM_LDO_VOLTAGE_MF)
2537 {
2538 pmStatus |= CY_SYSPM_STATUS_SYSTEM_MF;
2539 }
2540 else
2541 {
2542 pmStatus |= CY_SYSPM_STATUS_SYSTEM_OD;
2543 }
2544 }
2545 return pmStatus;
2546 }
2547
2548
Cy_SysPm_IsSystemLp(void)2549 bool Cy_SysPm_IsSystemLp(void)
2550 {
2551 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_LP) != 0U);
2552 }
2553
2554
Cy_SysPm_IsSystemUlp(void)2555 bool Cy_SysPm_IsSystemUlp(void)
2556 {
2557 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_ULP) != 0U);
2558 }
2559
2560
Cy_SysPm_IsSystemMf(void)2561 bool Cy_SysPm_IsSystemMf(void)
2562 {
2563 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_MF) != 0U);
2564 }
2565
2566
Cy_SysPm_IsSystemOd(void)2567 bool Cy_SysPm_IsSystemOd(void)
2568 {
2569 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_OD) != 0U);
2570 }
2571
2572
Cy_SysPm_SystemEnterLp(void)2573 cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void)
2574 {
2575 uint32_t interruptState;
2576 uint32_t cbLpRootIdx = (uint32_t) CY_SYSPM_LP;
2577 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2578
2579 /* Call the registered callback functions with the
2580 * CY_SYSPM_CHECK_READY parameter
2581 */
2582 if (pmCallbackRoot[cbLpRootIdx] != NULL)
2583 {
2584 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_CHECK_READY);
2585 }
2586
2587 /* The system can switch into LP only when
2588 * all executed registered callback functions with the
2589 * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
2590 */
2591 if (retVal == CY_SYSPM_SUCCESS)
2592 {
2593
2594 /* Call the registered callback functions with the
2595 * CY_SYSPM_BEFORE_TRANSITION parameter
2596 */
2597 interruptState = Cy_SysLib_EnterCriticalSection();
2598 if (pmCallbackRoot[cbLpRootIdx] != NULL)
2599 {
2600 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_BEFORE_TRANSITION);
2601 }
2602
2603 /* Read current active regulator and set LP voltage*/
2604 if (Cy_SysPm_LdoIsEnabled()) // Comment : Is this check req for PSoC C3 (CAT1B)
2605 {
2606 /* Current active regulator is LDO */
2607 if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_LP)
2608 {
2609 retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
2610 }
2611 }
2612
2613 Cy_SysLib_ExitCriticalSection(interruptState);
2614
2615 /* Call the registered callback functions with the
2616 * CY_SYSPM_AFTER_TRANSITION parameter
2617 */
2618 if (pmCallbackRoot[cbLpRootIdx] != NULL)
2619 {
2620 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_AFTER_TRANSITION);
2621 }
2622 }
2623 else
2624 {
2625 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
2626 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
2627 * parameter
2628 */
2629 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_CHECK_FAIL);
2630 retVal = CY_SYSPM_FAIL;
2631 }
2632
2633 return retVal;
2634 }
2635
Cy_SysPm_SystemEnterUlp(void)2636 cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void)
2637 {
2638 uint32_t interruptState;
2639 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2640 uint32_t cbUlpRootIdx = (uint32_t) CY_SYSPM_ULP;
2641
2642 /* Call the registered callback functions with the
2643 * CY_SYSPM_CHECK_READY parameter
2644 */
2645 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2646 {
2647 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_CHECK_READY);
2648 }
2649
2650 /* The system can switch into the ULP only when
2651 * all executed registered callback functions with the
2652 * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
2653 */
2654 if (retVal == CY_SYSPM_SUCCESS)
2655 {
2656 /* Call the registered callback functions with the
2657 * CY_SYSPM_BEFORE_TRANSITION parameter
2658 */
2659 interruptState = Cy_SysLib_EnterCriticalSection();
2660 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2661 {
2662 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_BEFORE_TRANSITION);
2663 }
2664
2665 /* Read current active regulator and set ULP voltage*/
2666 if (Cy_SysPm_LdoIsEnabled())
2667 {
2668 /* Current active regulator is LDO */
2669 if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_ULP)
2670 {
2671 retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_ULP);
2672 }
2673 }
2674
2675 Cy_SysLib_ExitCriticalSection(interruptState);
2676
2677 /* Call the registered callback functions with the
2678 * CY_SYSPM_AFTER_TRANSITION parameter
2679 */
2680 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2681 {
2682 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_AFTER_TRANSITION);
2683 }
2684 }
2685 else
2686 {
2687 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
2688 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
2689 * parameter
2690 */
2691 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_CHECK_FAIL);
2692 retVal = CY_SYSPM_FAIL;
2693 }
2694
2695 return retVal;
2696 }
2697
Cy_SysPm_SystemEnterMf(void)2698 cy_en_syspm_status_t Cy_SysPm_SystemEnterMf(void)
2699 {
2700 uint32_t interruptState;
2701 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2702 uint32_t cbUlpRootIdx = (uint32_t) CY_SYSPM_MF;
2703
2704 /* Call the registered callback functions with the
2705 * CY_SYSPM_CHECK_READY parameter
2706 */
2707 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2708 {
2709 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_MF, CY_SYSPM_CHECK_READY);
2710 }
2711
2712 /* The system can switch into the MF only when
2713 * all executed registered callback functions with the
2714 * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
2715 */
2716 if (retVal == CY_SYSPM_SUCCESS)
2717 {
2718 /* Call the registered callback functions with the
2719 * CY_SYSPM_BEFORE_TRANSITION parameter
2720 */
2721 interruptState = Cy_SysLib_EnterCriticalSection();
2722 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2723 {
2724 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_MF, CY_SYSPM_BEFORE_TRANSITION);
2725 }
2726
2727 /* Read current active regulator and set ULP voltage*/
2728 if (Cy_SysPm_LdoIsEnabled())
2729 {
2730 /* Current active regulator is LDO */
2731 if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_MF)
2732 {
2733 retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_MF);
2734 }
2735 }
2736
2737 Cy_SysLib_ExitCriticalSection(interruptState);
2738
2739 /* Call the registered callback functions with the
2740 * CY_SYSPM_AFTER_TRANSITION parameter
2741 */
2742 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2743 {
2744 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_MF, CY_SYSPM_AFTER_TRANSITION);
2745 }
2746 }
2747 else
2748 {
2749 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
2750 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
2751 * parameter
2752 */
2753 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_MF, CY_SYSPM_CHECK_FAIL);
2754 retVal = CY_SYSPM_FAIL;
2755 }
2756
2757 return retVal;
2758 }
2759
Cy_SysPm_SystemEnterOd(void)2760 cy_en_syspm_status_t Cy_SysPm_SystemEnterOd(void)
2761 {
2762 uint32_t interruptState;
2763 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2764 uint32_t cbUlpRootIdx = (uint32_t) CY_SYSPM_OD;
2765
2766 /* Call the registered callback functions with the
2767 * CY_SYSPM_CHECK_READY parameter
2768 */
2769 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2770 {
2771 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_OD, CY_SYSPM_CHECK_READY);
2772 }
2773
2774 /* The system can switch into the OD only when
2775 * all executed registered callback functions with the
2776 * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
2777 */
2778 if (retVal == CY_SYSPM_SUCCESS)
2779 {
2780 /* Call the registered callback functions with the
2781 * CY_SYSPM_BEFORE_TRANSITION parameter
2782 */
2783 interruptState = Cy_SysLib_EnterCriticalSection();
2784 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2785 {
2786 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_OD, CY_SYSPM_BEFORE_TRANSITION);
2787 }
2788
2789 /* Read current active regulator and set ULP voltage*/
2790 if (Cy_SysPm_LdoIsEnabled())
2791 {
2792 /* Current active regulator is LDO */
2793 if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_OD)
2794 {
2795 retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_OD);
2796 }
2797 }
2798
2799 Cy_SysLib_ExitCriticalSection(interruptState);
2800
2801 /* Call the registered callback functions with the
2802 * CY_SYSPM_AFTER_TRANSITION parameter
2803 */
2804 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2805 {
2806 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_OD, CY_SYSPM_AFTER_TRANSITION);
2807 }
2808 }
2809 else
2810 {
2811 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
2812 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
2813 * parameter
2814 */
2815 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_OD, CY_SYSPM_CHECK_FAIL);
2816 retVal = CY_SYSPM_FAIL;
2817 }
2818
2819 return retVal;
2820 }
2821 #endif
2822
2823 #if ((defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2u)) || \
2824 ((defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2u)) && (defined (SRSS_BACKUP_VBCK_PRESENT) && (SRSS_BACKUP_VBCK_PRESENT == 1u)))) || \
2825 defined (CY_DOXYGEN)
2826
Cy_SysPm_PmicEnable(void)2827 void Cy_SysPm_PmicEnable(void)
2828 {
2829 if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
2830 {
2831 BACKUP_PMIC_CTL =
2832 _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) |
2833 _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U) |
2834 _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1U);
2835 }
2836 }
2837
2838
Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity)2839 void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity)
2840 {
2841 CY_ASSERT_L3(CY_SYSPM_IS_POLARITY_VALID(polarity));
2842
2843 if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
2844 {
2845 BACKUP_PMIC_CTL =
2846 (_VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) |
2847 _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_POLARITY, (uint32_t) polarity)) &
2848 ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1U));
2849 }
2850 }
2851
2852
Cy_SysPm_PmicAlwaysEnable(void)2853 void Cy_SysPm_PmicAlwaysEnable(void)
2854 {
2855 BACKUP_PMIC_CTL |= _VAL2FLD(BACKUP_PMIC_CTL_PMIC_ALWAYSEN, 1U);
2856 }
2857
2858
Cy_SysPm_PmicEnableOutput(void)2859 void Cy_SysPm_PmicEnableOutput(void)
2860 {
2861 if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
2862 {
2863 BACKUP_PMIC_CTL |=
2864 _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) | _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U);
2865 }
2866 }
2867
2868
Cy_SysPm_PmicDisableOutput(void)2869 void Cy_SysPm_PmicDisableOutput(void)
2870 {
2871 if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
2872 {
2873 BACKUP_PMIC_CTL =
2874 (BACKUP_PMIC_CTL | _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY)) &
2875 ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U));
2876 }
2877 }
2878
2879
Cy_SysPm_PmicLock(void)2880 void Cy_SysPm_PmicLock(void)
2881 {
2882 BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, 0U);
2883 }
2884
2885
Cy_SysPm_PmicUnlock(void)2886 void Cy_SysPm_PmicUnlock(void)
2887 {
2888 BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY);
2889 }
2890
2891
Cy_SysPm_PmicIsEnabled(void)2892 bool Cy_SysPm_PmicIsEnabled(void)
2893 {
2894 return (0U != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN, BACKUP_PMIC_CTL));
2895 }
2896
2897
Cy_SysPm_PmicIsOutputEnabled(void)2898 bool Cy_SysPm_PmicIsOutputEnabled(void)
2899 {
2900 return (0U != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, BACKUP_PMIC_CTL));
2901 }
2902
2903
Cy_SysPm_PmicIsLocked(void)2904 bool Cy_SysPm_PmicIsLocked(void)
2905 {
2906 return ((_FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL) == CY_SYSPM_PMIC_UNLOCK_KEY) ? false : true);
2907 }
2908 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || ((CY_IP_MXS40SRSS_VERSION >= 2u) && (SRSS_BACKUP_VBCK_PRESENT)) */
2909
2910 #if (defined (CY_IP_MXS40SSRSS) && (SRSS_S40S_REGSETA_PRESENT == 1UL))
2911
Cy_SysPm_LinearRegDisable(void)2912 void Cy_SysPm_LinearRegDisable(void)
2913 {
2914 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_LINREG_DIS_Msk;
2915 }
2916
Cy_SysPm_LinearRegEnable(void)2917 void Cy_SysPm_LinearRegEnable(void)
2918 {
2919 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_LINREG_DIS_Msk;
2920 }
2921
Cy_SysPm_LinearRegGetStatus(void)2922 bool Cy_SysPm_LinearRegGetStatus(void)
2923 {
2924 return (_FLD2BOOL(SRSS_PWR_CTL2_LINREG_OK, SRSS_PWR_CTL2));
2925 }
2926
Cy_SysPm_DeepSleepRegDisable(void)2927 void Cy_SysPm_DeepSleepRegDisable(void)
2928 {
2929 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk;
2930 }
2931
Cy_SysPm_DeepSleepRegEnable(void)2932 void Cy_SysPm_DeepSleepRegEnable(void)
2933 {
2934 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk;
2935 }
2936
Cy_SySPm_IsDeepSleepRegEnabled(void)2937 bool Cy_SySPm_IsDeepSleepRegEnabled(void)
2938 {
2939 return(0u == _FLD2VAL(SRSS_PWR_CTL2_DPSLP_REG_DIS, SRSS_PWR_CTL2));
2940 }
2941 #endif /* Linear Regulator */
2942
2943 #endif
2944 /* [] END OF FILE */
2945
