1 /***************************************************************************//**
2 * \file cy_flash_srom.c
3 * \version 3.110
4 *
5 * \brief
6 * Provides functions for controlling the SROM APIs.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2021, Cypress Semiconductor Corporation. All rights reserved.
11 * You may use this file only in accordance with the license, terms, conditions,
12 * disclaimers, and limitations in the end user license agreement accompanying
13 * the software package with which this file was provided.
14 *******************************************************************************/
15 #include "cy_device.h"
16 #if defined (CY_IP_MXFLASHC_VERSION_ECT)
17 #include "cy_flash_srom.h"
18 #include "cy_ipc_drv.h"
19 
20 CY_SECTION_SHAREDMEM
21 CY_ALIGN(32) static un_srom_api_scrach_sram_t g_scratch; // This must locate on SRAM.
22 CY_SECTION_SHAREDMEM
23 CY_ALIGN(32) static un_srom_api_args_2_t      g_scratch2; // This must locate on SRAM.
24 static uint32_t message[2];
25 static cy_srom_handler gp_srom_resp_handler = NULL;
26 
27 static void Cy_Srom_ISR_ResponseIPC(void);
28 #if (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)
29 static uint32_t Cy_Srom_Get_DataSize(cy_en_programrow_datasize_t size);
30 #endif /* (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE) */
31 /*******************************************************************************
32 * Function Name: Cy_Srom_CallApi
33 ****************************************************************************//**
34 *
35 * This function calls SROM API. CPU will wait for API completed inside this
36 * function by checking IPC released. Even after checking 0x00FFFFFF times, if it
37 * is still not released, this function will return timeout status.
38 * If IPC was busy when this function was called, it would return busy status
39 * immediately.
40 * If SROM API returned error status, this function would return error status.
41 * But actual message is still in first word of memory pointed by second input
42 * parameter "resp" (if not NULL).
43 * All messages will be passed via SRAM pointed to scratch address. The SRAM area
44 * is reserved in this file as a variable named "g_scratch".
45 * This function is not re-entrant.
46 *
47 * \param params
48 * Pointer to memory which contains SROM API arguments. The contents of arguments
49 * will be copied to "g_scratch". \ref un_srom_api_args_t
50 *
51 * \param resp
52 * Pointer to memory which SROM API response message will be copied to. Even if
53 * this function return error status, response message will be copied to the
54 * memory. If pointer is NULL, response will not be copied \ref un_srom_api_resps_t
55 *
56 * \return
57 * \ref cy_en_srom_driver_status_t
58 *
59 *******************************************************************************/
Cy_Srom_CallApi(const un_srom_api_args_t * params,un_srom_api_resps_t * resp)60 cy_en_srom_driver_status_t Cy_Srom_CallApi(const un_srom_api_args_t* params, un_srom_api_resps_t* resp)
61 {
62     if(params == NULL)
63     {
64         return CY_SROM_DR_INVALID_INPUT;
65     }
66 
67     IPC_STRUCT_Type* syscall_ipc_struct = Cy_IPC_Drv_GetIpcBaseAddress((uint32_t)CY_IPC_CHAN_SYSCALL);
68     uint32_t timeOut = 0x0FFFFFFFUL;
69 
70     // Copy input contents to SRAM reserved
71     g_scratch.args = *params;
72 
73     // Make Bit[0] to 0, it indicates all arguments are passed through scratch address
74     g_scratch.u32[0] = g_scratch.u32[0] & 0xFFFFFFFEUL;
75 
76 #if (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)
77     uint32_t size_in_bytes = Cy_Srom_Get_DataSize((cy_en_programrow_datasize_t)(params->ProgramRow.arg1.dataSize));
78     CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 11.3', 3, \
79 'Checked manually. Intentional expression The object pointer of type non "uint32_t *" is cast to type "uint32_t *".')
80 
81     SCB_CleanDCache_by_Addr((uint32_t*)&g_scratch, (int32_t)sizeof(g_scratch));
82     SCB_CleanDCache_by_Addr((uint32_t*)params->ProgramRow.arg3.srcAddr, (int32_t)size_in_bytes);
83 
84     CY_MISRA_BLOCK_END('MISRA C-2012 Rule 11.3')
85 #endif /* (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE) */
86     // Send message by IPC
87     if (Cy_IPC_Drv_SendMsgWord(syscall_ipc_struct, CY_SROM_DR_IPC_NOTIFY_STRUCT, (uint32_t)&g_scratch) != CY_IPC_DRV_SUCCESS)
88     {
89         // The IPC structure is already locked by another process
90         return CY_SROM_DR_IPC_BUSY;
91     }
92     while(true)
93     {
94         // Checks if the IPC structure is not locked
95         if (Cy_IPC_Drv_IsLockAcquired(syscall_ipc_struct) == false)
96         {
97             // The result of SROM API calling is in the SRAM reserved.
98             // Copy the contents to the memory pointed by input pointer
99             if(resp != NULL)
100             {
101 #if (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)
102                 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 11.3', 1, \
103 'Checked manually. Intentional expression The object pointer of type non "uint32_t *" is cast to type "uint32_t *".')
104                 SCB_InvalidateDCache_by_Addr ((uint32_t*)&g_scratch, (int32_t)sizeof(g_scratch));
105                 SCB_InvalidateDCache_by_Addr ((uint32_t*)params->ProgramRow.arg2.dstAddr, (int32_t)size_in_bytes);
106                 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 11.3')
107 #endif /* (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE) */
108                 *resp = g_scratch.resps;
109             }
110             break;
111         }
112 
113         // Decrement time out counter value
114         timeOut--;
115 
116         // If time out counter is "0" return time out status
117         if(timeOut == 0U)
118         {
119             return CY_SROM_DR_TIMEOUT;
120         }
121     }
122 
123     if(Cy_Srom_GetResponseType() == CY_SROM_RESPONSE_FAIL)
124     {
125         // If the SROM API returned an error in the scratch RAM, return error
126         return CY_SROM_DR_API_ERROR;
127     }
128     else if(Cy_Srom_GetResponseType() == CY_SROM_RESPONSE_SUCCESS)
129     {
130         // If the SROM API returned "OK", return success
131         return CY_SROM_DR_SUCCEEDED;
132     }
133     else
134     {
135         // Return unknown status
136         return CY_SROM_DR_API_UNKNOWN;
137     }
138 }
139 
140 /*******************************************************************************
141 * Function Name: Cy_Srom_CallApi_NonBlock
142 ****************************************************************************//**
143 *
144 * This function calls SROM API. CPU "won't" wait for API completed inside this
145 * function by checking IPC released.
146 * If IPC was busy when this function was called, it would return busy status
147 * immediately.
148 * Please call "Cy_Srom_Get_Api_Response" to retrieve API response.
149 * All messages will be passed via SRAM pointed to scratch address. The SRAM area
150 * is reserved in this file as a variable named "g_scratch".
151 * This function is not re-entrant.
152 * Once user called this function, this function and also "Cy_Srom_CallApi"
153 * must not called until SROM API finished.
154 *
155 * \param params
156 * Pointer to memory which contains SROM API arguments. The contents of arguments
157 * will be copied to "g_scratch". \ref un_srom_api_args_t
158 *
159 * \return
160 * \ref cy_en_srom_driver_status_t
161 *
162 *******************************************************************************/
Cy_Srom_CallApi_NonBlock(const un_srom_api_args_t * params)163 cy_en_srom_driver_status_t Cy_Srom_CallApi_NonBlock(const un_srom_api_args_t* params)
164 {
165     if(params == NULL)
166     {
167         return CY_SROM_DR_INVALID_INPUT;
168     }
169     IPC_STRUCT_Type* syscall_ipc_struct = Cy_IPC_Drv_GetIpcBaseAddress((uint32_t)CY_IPC_CHAN_SYSCALL);
170     uint32_t timeOut = 0x0FFFFFFFUL;
171 
172     // Copy input contents to SRAM reserved
173     g_scratch.args = *params;
174 
175     // Make Bit[0] to 0, it indicates all arguments are passed through scratch address
176     g_scratch.u32[0] = g_scratch.u32[0] & 0xFFFFFFFEUL;
177 
178 #if (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)
179     uint32_t size_in_bytes = Cy_Srom_Get_DataSize((cy_en_programrow_datasize_t)(params->ProgramRow.arg1.dataSize));
180     CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 11.3', 3, \
181 'Checked manually. Intentional expression The object pointer of type non "uint32_t *" is cast to type "uint32_t *".')
182     SCB_CleanDCache_by_Addr((uint32_t*)&g_scratch, (int32_t)sizeof(g_scratch));
183     SCB_CleanDCache_by_Addr((uint32_t*)params->ProgramRow.arg3.srcAddr, (int32_t)size_in_bytes);
184 
185     CY_MISRA_BLOCK_END('MISRA C-2012 Rule 11.3')
186 #endif /* (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE) */
187     // Send message by IPC
188     if (Cy_IPC_Drv_SendMsgWord(syscall_ipc_struct, CY_SROM_DR_IPC_NOTIFY_STRUCT, (uint32_t)&g_scratch) != CY_IPC_DRV_SUCCESS)
189     {
190         // The IPC structure is already locked by another process
191         return CY_SROM_DR_IPC_BUSY;
192     }
193     while(true)
194    {
195        // Checks if the IPC structure is not locked
196        if (Cy_IPC_Drv_IsLockAcquired(syscall_ipc_struct) == false)
197        {
198            // The result of SROM API calling is in the SRAM reserved.
199            // Copy the contents to the memory pointed by input pointer
200 #if (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)
201                 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 11.3', 1, \
202 'Checked manually. Intentional expression The object pointer of type non "uint32_t *" is cast to type "uint32_t *".')
203                 SCB_InvalidateDCache_by_Addr ((uint32_t*)params->ProgramRow.arg2.dstAddr, (int32_t)size_in_bytes);
204                 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 11.3')
205 #endif /* (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE) */
206            break;
207        }
208        // Decrement time out counter value
209        timeOut--;
210 
211        // If time out counter is "0" return time out status
212        if(timeOut == 0U)
213        {
214            return CY_SROM_DR_TIMEOUT;
215        }
216    }
217     // Return succeeded status
218     return CY_SROM_DR_SUCCEEDED;
219 }
220 
221 /*******************************************************************************
222 * Function Name: Cy_Srom_CallApi_2
223 ****************************************************************************//**
224 *
225 * This function calls SROM API which need also IPC DATA1. Other is same as
226 * "Cy_SROM_CallApi"
227 *
228 * \param params
229 * Pointer to memory which contains SROM API arguments. The contents of arguments
230 * will be copied to "g_scratch". \ref un_srom_api_args_t
231 *
232 * \param params
233 * Pointer to memory which contains SROM API arguments 2. The contents of arguments
234 * will be copied to "g_scratch2". \ref un_srom_api_args_2_t
235 *
236 * \param resp
237 * Pointer to memory which SROM API response message will be copied to. Even if
238 * this function return error status, response message will be copied to the
239 * memory. If pointer is NULL, response will not be copied \ref un_srom_api_resps_t
240 *
241 * \return
242 * \ref cy_en_srom_driver_status_t
243 *
244 *******************************************************************************/
Cy_Srom_CallApi_2(const un_srom_api_args_t * params,const un_srom_api_args_2_t * params2,un_srom_api_resps_t * resp)245 cy_en_srom_driver_status_t Cy_Srom_CallApi_2(const un_srom_api_args_t* params, const un_srom_api_args_2_t* params2, un_srom_api_resps_t* resp)
246 {
247     if((params == NULL) || (params2 == NULL))
248     {
249         return CY_SROM_DR_INVALID_INPUT;
250     }
251 //    CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.1','Checked manually. Intentional Non boolean type is interpreted as boolean.');
252     IPC_STRUCT_Type* syscall_ipc_struct = Cy_IPC_Drv_GetIpcBaseAddress((uint32_t)CY_IPC_CHAN_SYSCALL);
253     uint32_t timeOut = 0x00FFFFFFUL;
254 
255     // Copy input contents to SRAM reserved
256     g_scratch.args = *params;
257     g_scratch2     = *params2;
258 
259     // Make Bit[0] to 0, it indicates all arguments are passed through scratch address
260     g_scratch.u32[0]  = g_scratch.u32[0]  & 0xFFFFFFFEUL;
261     g_scratch2.arg[0] = g_scratch2.arg[0] & 0xFFFFFFFEUL;
262 
263 
264     message[0] = (uint32_t)&g_scratch;
265     message[1] = (uint32_t)&g_scratch2;
266     // Send message by IPC
267     if (Cy_IPC_Drv_SendMsgDWord(syscall_ipc_struct, CY_SROM_DR_IPC_NOTIFY_STRUCT, message) != CY_IPC_DRV_SUCCESS)
268     {
269         // The IPC structure is already locked by another process
270         return CY_SROM_DR_IPC_BUSY;
271     }
272     while(true)
273     {
274         // Checks if the IPC structure is not locked
275         if (Cy_IPC_Drv_IsLockAcquired(syscall_ipc_struct) == false)
276         {
277             // The result of SROM API calling is in the SRAM reserved.
278             // Copy the contents to the memory pointed by input pointer
279             if(resp != NULL)
280             {
281                 *resp = g_scratch.resps;
282             }
283             break;
284         }
285 
286         // Decrement time out counter value
287         timeOut--;
288 
289         // If time out counter is "0" return time out status
290         if(timeOut == 0u)
291         {
292             return CY_SROM_DR_TIMEOUT;
293         }
294     }
295 
296     if(Cy_Srom_GetResponseType() == CY_SROM_RESPONSE_FAIL)
297     {
298         // If the SROM API returned an error in the scratch RAM, return error
299         return CY_SROM_DR_API_ERROR;
300     }
301     else if(Cy_Srom_GetResponseType() == CY_SROM_RESPONSE_SUCCESS)
302     {
303         // If the SROM API returned "OK", return success
304         return CY_SROM_DR_SUCCEEDED;
305     }
306     else
307     {
308         // Return unknown status
309         return CY_SROM_DR_API_UNKNOWN;
310     }
311 }
312 
313 /*******************************************************************************
314 * Function Name: Cy_Srom_CallApi_NonBlock_2
315 ****************************************************************************//**
316 *
317 * This function calls SROM API which need also IPC DATA1. Other is same as
318 * "Cy_SROM_CallApi_NonBlock_2"
319 *
320 * \param params
321 * Pointer to memory which contains SROM API arguments. The contents of arguments
322 * will be copied to "g_scratch". \ref un_srom_api_args_t
323 *
324 * \param params
325 * Pointer to memory which contains SROM API arguments 2. The contents of arguments
326 * will be copied to "g_scratch2". \ref un_srom_api_args_2_t
327 *
328 * \return
329 * \ref cy_en_srom_driver_status_t
330 *
331 *******************************************************************************/
Cy_Srom_CallApi_NonBlock_2(const un_srom_api_args_t * params,const un_srom_api_args_2_t * params2)332 cy_en_srom_driver_status_t Cy_Srom_CallApi_NonBlock_2(const un_srom_api_args_t* params, const un_srom_api_args_2_t* params2)
333 {
334     if((params == NULL) || (params2 == NULL))
335     {
336         return CY_SROM_DR_INVALID_INPUT;
337     }
338 //    CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.1','Checked manually. Intentional Non boolean type is interpreted as boolean.');
339     IPC_STRUCT_Type* syscall_ipc_struct = Cy_IPC_Drv_GetIpcBaseAddress((uint32_t)CY_IPC_CHAN_SYSCALL);
340 
341     // Copy input contents to SRAM reserved
342     g_scratch.args = *params;
343     g_scratch2     = *params2;
344 
345     // Make Bit[0] to 0, it indicates all arguments are passed through scratch address
346     g_scratch.u32[0]  = g_scratch.u32[0]  & 0xFFFFFFFEUL;
347     g_scratch2.arg[0] = g_scratch2.arg[0] & 0xFFFFFFFEUL;
348 
349     message[0] = (uint32_t)&g_scratch;
350     message[1] = (uint32_t)&g_scratch2;
351     // Send message by IPC
352     if (Cy_IPC_Drv_SendMsgDWord(syscall_ipc_struct, CY_SROM_DR_IPC_NOTIFY_STRUCT, message) != CY_IPC_DRV_SUCCESS)
353     {
354         // The IPC structure is already locked by another process
355         return CY_SROM_DR_IPC_BUSY;
356     }
357     // Return succeeded status
358     return CY_SROM_DR_SUCCEEDED;
359 }
360 
361 
362 /*******************************************************************************
363 * Function Name: Cy_Srom_GetResponseType
364 ****************************************************************************//**
365 *
366 * This function returns status of SROM API response defined by \ref
367 * cy_en_srom_response_type_t
368 * Please call this function after "Cy_Srom_CallApi_NonBlock" was called.
369 *
370 * \return
371 * \ref cy_en_srom_response_type_t
372 *
373 *******************************************************************************/
Cy_Srom_GetResponseType(void)374 cy_en_srom_response_type_t Cy_Srom_GetResponseType(void)
375 {
376     if((g_scratch.u32[0] & 0xF0000000UL) == 0xA0000000UL)
377     {
378         return CY_SROM_RESPONSE_SUCCESS;
379     }
380     else if((g_scratch.u32[0] & 0xF0000000UL) == 0xF0000000UL)
381     {
382         return CY_SROM_RESPONSE_FAIL;
383     }
384     else
385     {
386         return CY_SROM_NOT_RESPONSE;
387     }
388 }
389 
390 /*******************************************************************************
391 * Function Name: Cy_Srom_Get_Api_Response
392 ****************************************************************************//**
393 *
394 * This function returns g_scratch value as a response of SROM API.
395 * Please call this function after "Cy_Srom_CallApi_NonBlock" was called.
396 * "resp" is raw response data from SROM API on the other hands, return value
397 * indicate status of the response data like as invalid, succeeded, or failed.
398 * (if failed return value is same as resp.u32[0])
399 *
400 * \param resp
401 * Pointer to memory into which SROM API response to be copied if not NULL.
402 *  \ref un_srom_api_resps_t
403 *
404 * \return
405 * \ref cy_en_srom_api_status_t
406 *
407 *******************************************************************************/
Cy_Srom_GetApiResponse(un_srom_api_resps_t * resp)408 cy_en_srom_api_status_t Cy_Srom_GetApiResponse(un_srom_api_resps_t* resp)
409 {
410 #if (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)
411     CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 11.3', 3, \
412 'Checked manually. Intentional expression The object pointer of type non "uint32_t *" is cast to type "uint32_t *".')
413     SCB_InvalidateDCache_by_Addr ((uint32_t*)&g_scratch, (int32_t)sizeof(g_scratch));
414     CY_MISRA_BLOCK_END('MISRA C-2012 Rule 11.3')
415 #endif /* (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE) */
416     cy_en_srom_response_type_t type = Cy_Srom_GetResponseType();
417     if(type == CY_SROM_NOT_RESPONSE)
418     {
419         return CY_SROM_STATUS_INVALID;
420     }
421     else
422     {
423         if(resp != NULL)
424         {
425             *resp = g_scratch.resps;
426         }
427 
428         if(type == CY_SROM_RESPONSE_SUCCESS)
429         {
430             return CY_SROM_STATUS_SUCCESS;
431         }
432         else // CY_SROM_RESPONSE_FAIL
433         {
434             // return error code.
435             return (cy_en_srom_api_status_t)g_scratch.u32[0];
436         }
437     }
438 }
439 
440 /*******************************************************************************
441 * Function Name: Cy_Srom_ConvertRespToStatus
442 ****************************************************************************//**
443 *
444 * This function returns g_scratch value as a response of SROM API.
445 * Please call this function after "Cy_Srom_CallApi_NonBlock" was called.
446 * "resp" is raw response data from SROM API on the other hands, return value
447 * indicate status of the response data like as invalid, succeeded, or failed.
448 * (if failed return value is same as resp.u32[0])
449 *
450 * \param resp
451 * Pointer to memory into which SROM API response to be copied if not NULL.
452 *  \ref un_srom_api_resps_t
453 *
454 * \return
455 * \ref cy_en_srom_api_status_t
456 *
457 *******************************************************************************/
Cy_Srom_ConvertRespToStatus(uint32_t resp0)458 cy_en_srom_api_status_t Cy_Srom_ConvertRespToStatus(uint32_t resp0)
459 {
460     if((resp0 & 0xF0000000UL) == 0xA0000000UL)
461     {
462         return CY_SROM_STATUS_SUCCESS;
463     }
464     else if((resp0 & 0xF0000000UL) == 0xF0000000UL)
465     {
466         // Error Code
467         return (cy_en_srom_api_status_t)resp0;
468     }
469     else
470     {
471         return CY_SROM_STATUS_INVALID;
472     }
473 }
474 
475 /*******************************************************************************
476 * Function Name: Cy_Srom_SetResponseHandler
477 ****************************************************************************//**
478 *
479 * This function sets response handler which is supposed to be called when SROM
480 * API is complete.
481 *
482 * \param handler
483 * This will be invoked when SROM API finished and the IPC released.
484 *
485 *******************************************************************************/
Cy_Srom_SetResponseHandler(cy_srom_handler handler)486 void Cy_Srom_SetResponseHandler(cy_srom_handler handler)
487 {
488 
489 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 10.1', 3, \
490 'Checked manually. Intentional  expression "NvicMux3_IRQn" of type enum is used as an operand to the arithmetic operator "<<".')
491 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 10.4', 1, \
492 'Checked manually. Intentional  expression "NvicMux3_IRQn" of type enum is used as an operand to the arithmetic operator "<<".')
493     const cy_stc_sysint_t irq_cfg = {
494 #if defined (CY_IP_M7CPUSS)
495         /* Shift the interrupt source to the upper INTRSRC bits. */
496         .intrSrc = ((NvicMux3_IRQn << CY_SYSINT_INTRSRC_MUXIRQ_SHIFT) | CY_SROM_DR_IPC_INTR_NO),
497 #elif (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION == 2) && (CPUSS_SYSTEM_IRQ_PRESENT))
498         /* Shift the interrupt source to the upper INTRSRC bits. */
499         .intrSrc = (IRQn_Type)((NvicMux3_IRQn << CY_SYSINT_INTRSRC_MUXIRQ_SHIFT) | CY_SROM_DR_IPC_INTR_NO),
500 #else
501         .intrSrc = (IRQn_Type)(CY_SROM_DR_IPC_INTR_NO),
502         #if (CY_CPU_CORTEX_M0P) && defined (CY_IP_M4CPUSS)
503         .cm0pSrc = (uint32_t) NvicMux3_IRQn,
504         #endif
505 #endif
506         .intrPriority = 2UL,
507     };
508 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 10.4')
509 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 10.1')
510     /* set response handler */
511     gp_srom_resp_handler = handler;
512 
513     /*  Set CPUSS interrupt    */
514     cy_en_sysint_status_t sysStatus = Cy_SysInt_Init(&irq_cfg, Cy_Srom_ISR_ResponseIPC);
515     if(CY_SYSINT_SUCCESS != sysStatus)
516     {
517         NVIC_EnableIRQ((IRQn_Type) NvicMux3_IRQn);
518     }
519 
520     /*  Set IPC interrupt mask    */
521     IPC_INTR_STRUCT_Type* sromRespIntrStr = Cy_IPC_Drv_GetIntrBaseAddr(CY_SROM_DR_IPC_INTR_STRUCT);
522 
523     CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.1','Checked manually. Intentional Non boolean type is interpreted as boolean.');
524     Cy_IPC_Drv_SetInterruptMask(sromRespIntrStr, (uint32_t)(1UL << (uint32_t)CY_IPC_CHAN_SYSCALL), 0UL);
525 }
526 
527 /*******************************************************************************
528 * Function Cy_Srom_ISR_ResponseIPC
529 ****************************************************************************//**
530 *
531 * This is interrupt handler called when SROM API was finished by CM0+ via IPC
532 * This function will be assigned in "Cy_Srom_SetResponseHandler".
533 *
534 *******************************************************************************/
Cy_Srom_ISR_ResponseIPC(void)535 static void Cy_Srom_ISR_ResponseIPC(void)
536 {
537     uint32_t masked = 0;
538 
539     IPC_INTR_STRUCT_Type* sromRespIntrStr = Cy_IPC_Drv_GetIntrBaseAddr(CY_SROM_DR_IPC_INTR_STRUCT);
540     masked = Cy_IPC_Drv_GetInterruptStatusMasked(sromRespIntrStr);
541 
542 //    CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.1','Checked manually. Intentional Non boolean type is interpreted as boolean.');
543     if((uint32_t)(masked & (uint32_t)(1UL << (uint32_t)CY_IPC_CHAN_SYSCALL)) != 0UL)
544     {
545         if(gp_srom_resp_handler != NULL)
546         {
547             gp_srom_resp_handler();
548         }
549     }
550 
551     Cy_IPC_Drv_ClearInterrupt(
552                                 sromRespIntrStr,
553                                 (masked & 0x0000FFFFUL),
554                                 (masked & 0xFFFF0000UL) >> 16UL
555                               );
556 }
557 #if (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)
558 /*******************************************************************************
559 * Function Cy_Srom_Get_DataSize
560 ****************************************************************************//**
561 *
562 * This returns the actual size in bytes based on the enumeration value passed.
563 *
564 *******************************************************************************/
Cy_Srom_Get_DataSize(cy_en_programrow_datasize_t size)565 static uint32_t Cy_Srom_Get_DataSize(cy_en_programrow_datasize_t size)
566 {
567     uint32_t data_size;
568     switch(size)
569     {
570         case CY_SROM_PROGRAMROW_DATA_SIZE_8BIT:
571             data_size = 1u;
572             break;
573         case CY_SROM_PROGRAMROW_DATA_SIZE_16BIT:
574             data_size = 2u;
575             break;
576         case CY_SROM_PROGRAMROW_DATA_SIZE_32BIT:
577             data_size = 4u;
578             break;
579         case CY_SROM_PROGRAMROW_DATA_SIZE_64BIT:
580             data_size = 8u;
581             break;
582         case CY_SROM_PROGRAMROW_DATA_SIZE_128BIT:
583             data_size = 16u;
584             break;
585         case CY_SROM_PROGRAMROW_DATA_SIZE_256BIT:
586             data_size = 32u;
587             break;
588         case CY_SROM_PROGRAMROW_DATA_SIZE_512BIT:
589             data_size = 64u;
590             break;
591         case CY_SROM_PROGRAMROW_DATA_SIZE_1024BIT:
592             data_size = 128u;
593             break;
594         case CY_SROM_PROGRAMROW_DATA_SIZE_2048BIT:
595             data_size = 256u;
596             break;
597         case CY_SROM_PROGRAMROW_DATA_SIZE_4096BIT:
598             data_size = 512u;
599             break;
600         default:
601             data_size = 0u;
602             break;
603     }
604     return data_size;
605 }
606 
607 #endif /* (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE) */
608 #endif /* CY_IP_M4CPUSS  CY_IP_M7CPUSS*/
609