1 /***************************************************************************//**
2 * \file cy_wdt.h
3 * \version 1.80
4 *
5 *  This file provides constants and parameter values for the WDT driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 *     http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *
25 *******************************************************************************/
26 
27 /**
28 * \addtogroup group_wdt
29 * \{
30 *
31 * The Watchdog timer (WDT) has a 16-bit free-running up-counter.
32 *
33 * The functions and other declarations used in this driver are in cy_wdt.h.
34 * You can include cy_pdl.h to get access to all functions
35 * and declarations in the PDL.
36 *
37 * The WDT can issue counter match interrupts, and a device reset if its interrupts are not
38 * handled. Use the Watchdog timer for two main purposes:
39 *
40 * The <b> First use case </b> is recovering from a CPU or firmware failure.
41 * A timeout period is set up in the Watchdog timer, and if a timeout occurs, the
42 * device is reset (WRES). <br>
43 * The <b>Second use case</b> is to generate periodic interrupts.
44 * It is strongly recommended not to use the WDT for periodic interrupt
45 * generation. However, if absolutely required, see information below.
46 *
47 * A "reset cause" register(RES_CAUSE, Part of SRSS IP) exists, and the firmware should
48 * check this register at a start-up. An appropriate action can be taken if a WRES
49 * reset is detected.
50 *
51 * The user's firmware periodically resets the timeout period (clears or "feeds"
52 * the watchdog) before a timeout occurs. If the firmware fails to do so, that is
53 * considered to be a CPU crash or a firmware failure, and the reason for a
54 * device reset.
55 * The WDT can generate an interrupt instead of a device reset. The Interrupt
56 * Service Routine (ISR) can handle the interrupt either as a periodic interrupt,
57 * or as an early indication of a firmware failure and respond accordingly.
58 * However, it is not recommended to use the WDT for periodic interrupt
59 * generation. The Multi-counter Watchdog Timers (MCWDT) can be used to generate
60 * periodic interrupts if such are presented in the device.
61 *
62 * <b> Functional Description </b>
63 *
64 * The WDT generates an interrupt when the count value in the counter equals the
65 * configured match value.
66 *
67 * Note that the counter is not reset on a match. In such case the WDT
68 * reset period is:
69 * WDT_Reset_Period = ILO_Period * (2*2^(16-IgnoreBits) + MatchValue);
70 * When the counter reaches a match value, it generates an interrupt and then
71 * keeps counting up until it overflows and rolls back to zero and reaches the
72 * match value again, at which point another interrupt is generated.
73 *
74 * To use a WDT to generate a periodic interrupt, the match value should be
75 * incremented in the ISR. As a result, the next WDT interrupt is generated when
76 * the counter reaches a new match value.
77 *
78 * You can also reduce the entire WDT counter period by
79 * specifying the number of most significant bits that are ignored in the WDT
80 * counter. For example, if the Cy_WDT_SetIgnoreBits() function is called with
81 * parameter 3, the WDT counter becomes a 13-bit free-running up-counter.
82 *
83 * <b> Power Modes </b>
84 *
85 * WDT can operate in all possible low power modes.
86 * Operation during Hibernate mode is possible because the logic and
87 * high-voltage internal low oscillator (ILO) are supplied by the external
88 * high-voltage supply (Vddd). The WDT can be configured to wake the device from
89 * Hibernate mode.
90 *
91 * In CPU Active mode, an interrupt request from the WDT is sent to the
92 * CPU. In CPU Sleep, CPU Deep Sleep mode, the CPU subsystem
93 * is powered down, so the interrupt request from the WDT is sent directly to the
94 * WakeUp Interrupt Controller (WIC) which will then wake up the CPU. The
95 * CPU then acknowledges the interrupt request and executes the ISR.
96 *
97 * <b> Clock Source </b>
98 *
99 * The WDT is clocked by the ILO. The WDT must be disabled before disabling
100 * the ILO. According to the device datasheet, the ILO accuracy is +/-30% over
101 * voltage and temperature. This means that the timeout period may vary by 30%
102 * from the configured value. Appropriate margins should be added while
103 * configuring WDT intervals to make sure that unwanted device resets do not
104 * occur on some devices.
105 *
106 * Refer to the device datasheet for more information on the oscillator accuracy.
107 *
108 * <b> Register Locking </b>
109 *
110 * You can prevent accidental corruption of the WDT configuration by calling
111 * the Cy_WDT_Lock() function. When the WDT is locked, any writing to the WDT_*,
112 * CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers is
113 * ignored.
114 * Call the Cy_WDT_Unlock() function to allow registers modification, mentioned
115 * above.
116 *
117 * Note that the WDT lock state is not retained during system Deep Sleep. After
118 * the wakeup from system Deep Sleep the WDT is locked.
119 *
120 * <b> Clearing WDT </b>
121 *
122 * The ILO clock is asynchronous to the SysClk. Therefore it generally
123 * takes three ILO cycles for WDT register changes to come into effect. It is
124 * important to remember that a WDT should be cleared at least four cycles
125 * (3 + 1 for sure) before a timeout occurs, especially when small
126 * match values / low-toggle bit numbers are used.
127 *
128 * \warning It may happen that a WDT reset can be generated
129 * faster than a device start-up. To prevent this, calculate the
130 * start-up time and WDT reset time. The WDT reset time should be always greater
131 * than device start-up time.
132 *
133 * <b> Reset Detection </b>
134 *
135 * Use the Cy_SysLib_GetResetReason() function to detect whether the WDT has
136 * triggered a device reset.
137 *
138 * <b> Interrupt Configuration </b>
139 *
140 * If the WDT is configured to generate an interrupt, pending
141 * interrupts must be cleared within the ISR (otherwise, the interrupt will be
142 * generated continuously).
143 * A pending interrupt to the WDT block must be cleared by calling the
144 * Cy_WDT_ClearInterrupt() function. The call to the function will clear the
145 * unhandled WDT interrupt counter.
146 *
147 * Use the WDT ISR as a timer to trigger certain actions
148 * and to change a next WDT match value.
149 *
150 * Ensure that the interrupts from the WDT are passed to the CPU to avoid
151 * unregistered interrupts. Unregistered WDT interrupts result in a continuous
152 * device reset. To avoid this, call Cy_WDT_UnmaskInterrupt().
153 * After that, call the WDT API functions for interrupt
154 * handling/clearing.
155 *
156 * \section group_wdt_configuration Configuration Considerations
157 *
158 * To start the WDT, make sure that ILO is enabled.
159 * After the ILO is enabled, ensure that the WDT is unlocked and disabled by
160 * calling the Cy_WDT_Unlock() and Cy_WDT_Disable() functions. Set the WDT match
161 * value by calling Cy_WDT_SetMatch() with the required match value. If needed,
162 * set the ignore bits for reducing the WDT counter period by calling
163 * Cy_WDT_SetIgnoreBits() function. After the WDT configuration is set,
164 * call Cy_WDT_Enable().
165 *
166 * \note Enable a WDT if the power supply can produce
167 * sudden brownout events that may compromise the CPU functionality. This
168 * ensures that the system can recover after a brownout.
169 *
170 * When the WDT is used to protect against system crashes, the
171 * WDT interrupt should be cleared by a portion of the code that is not directly
172 * associated with the WDT interrupt.
173 * Otherwise, it is possible that the main firmware loop has crashed or is in an
174 * endless loop, but the WDT interrupt vector continues to operate and service
175 * the WDT. The user should:
176 * * Feed the watchdog by clearing the interrupt bit regularly in the main body
177 * of the firmware code.
178 *
179 * * Guarantee that the interrupt is cleared at least once every WDT period.
180 *
181 * * Use the WDT ISR only as a timer to trigger certain actions and to change the
182 * next match value.
183 *
184 * \section group_wdt_section_more_information More Information
185 *
186 * For more information on the WDT peripheral, refer to the technical reference
187 * manual (TRM).
188 *
189 * \section group_wdt_changelog Changelog
190 * <table class="doxtable">
191 *   <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
192 *   <tr>
193 *     <td>1.80</td>
194 *     <td>Added support for TRAVEO&trade; II Body Entry devices.<br>
195 *          MXS40SRSS_VERSION compares now expect &lt; or &gt;= 2, previously 3.</td>
196 *     <td>Code enhancement and support for new devices.</td>
197 *   </tr>
198 *   <tr>
199 *     <td>1.70</td>
200 *     <td>Modified Cy_WDT_SetIgnoreBits() API to work correctly with CAT1B.<br>
201 *         Newly Added API : Cy_WDT_ResetCounter() for resetting counter to zero.</td>
202 *     <td>Code Enhancements for CAT1B.</td>
203 *     <td>Added \ref Cy_WDT_ResetCounter new API and few macros.</td>
204 *     <td>Usability enhancement.</td>
205 *   </tr>
206 *   <tr>
207 *     <td>1.60</td>
208 *     <td>Updated \ref cy_en_wdt_clk_sources_t enum and added support for CAT1D.</td>
209 *     <td>Code Enhancement and new device support added.</td>
210 *   </tr>
211 *   <tr>
212 *     <td>1.50</td>
213 *     <td>Added WDT_B type support required for CAT1C devices.<br>Newly added APIs:
214 *         \n Cy_WDT_SetLowerLimit(),
215 *         \n Cy_WDT_SetUpperLimit(),
216 *         \n Cy_WDT_SetWarnLimit(),
217 *         \n Cy_WDT_SetLowerAction(),
218 *         \n Cy_WDT_SetUpperAction(),
219 *         \n Cy_WDT_SetWarnAction(),
220 *         \n Cy_WDT_SetAutoService(),
221 *         \n Cy_WDT_SetDeepSleepPause(),
222 *         \n Cy_WDT_SetHibernatePause(),
223 *         \n Cy_WDT_SetDebugRun(),
224 *         \n Cy_WDT_SetService(),
225 *     <td>Support for new devices.</td>
226 *   </tr>
227 *   <tr>
228 *     <td>1.40</td>
229 *     <td>CAT1B, CAT1C devices support.<br>
230 *         Newly added API's Cy_WDT_SetClkSource() to configure the WDT clock source, Cy_WDT_GetClkSource() to get the WDT clock source configured,
231 *         Cy_WDT_SetMatchBits() to configure the bit position above which the bits will be ignored for match, Cy_WDT_GetMatchBits() to get the bit position above which the bits will be ignored for match.</td>
232 *     <td>Support for new devices.</td>
233 *   </tr>
234 *   <tr>
235 *     <td>1.30.1</td>
236 *     <td>Minor documentation updates.</td>
237 *     <td>Removed MISRA 2004 compliance details and verified MISRA 2012 compliance.</td>
238 *   </tr>
239 *   <tr>
240 *     <td rowspan="2">1.30</td>
241 *     <td>Updated the following functions for the PSoC 64 devices: \ref Cy_WDT_ClearInterrupt(),
242 *         \ref Cy_WDT_MaskInterrupt(), and \ref Cy_WDT_UnmaskInterrupt().</td>
243 *     <td>Added PSoC 64 device support.</td>
244 *   </tr>
245 *   <tr>
246 *     <td>Minor documentation updates.</td>
247 *     <td>Documentation enhancement.</td>
248 *   </tr>
249 *   <tr>
250 *     <td>1.20</td>
251 *     <td>Added a new API function \ref Cy_WDT_IsEnabled() </td>
252 *     <td>Enhancement based on usability feedback.</td>
253 *   </tr>
254 *   <tr>
255 *     <td>1.10.1</td>
256 *     <td>Added info that the WDT lock state is not retained during
257 *        system Deep Sleep power mode.
258 *     </td>
259 *     <td>Documentation updates.</td>
260 *   </tr>
261 *   <tr>
262 *     <td rowspan="4">1.10</td>
263 *     <td>Flattened the organization of the driver source code into the single
264 *         source directory and the single include directory.
265 *     </td>
266 *     <td>Driver library directory-structure simplification.</td>
267 *   </tr>
268 *   <tr>
269 *     <td> Removed critical section usage in the following functions:
270 *           - \ref Cy_WDT_Init()
271 *           - \ref Cy_WDT_Lock()
272 *           - \ref Cy_WDT_Unlock()
273 *     </td>
274 *   <td>Driver functions simplification</td>
275 *   </tr>
276 *   <tr>
277 *     <td>Updated the \ref Cy_WDT_Init(), \ref Cy_WDT_Enable() to clear WDT interrupt.</td>
278 *     <td>Corner case reliability improvements</td>
279 *   </tr>
280 *   <tr>
281 *     <td>Added register access layer. Use register access macros instead
282 *         of direct register access using dereferenced pointers.</td>
283 *     <td>Makes register access device-independent, so that the PDL does
284 *         not need to be recompiled for each supported part number.</td>
285 *   </tr>
286 *   <tr>
287 *     <td>1.0.2</td>
288 *     <td>Minor documentation updates</td>
289 *     <td>Corrected info about a reset generation</td>
290 *   </tr>
291 *   <tr>
292 *     <td>1.0.1</td>
293 *     <td>General documentation updates</td>
294 *     <td>Added info about periodic interrupt generation use case</td>
295 *   </tr>
296 *   <tr>
297 *     <td>1.0</td>
298 *     <td>Initial version</td>
299 *     <td></td>
300 *   </tr>
301 * </table>
302 *
303 * \defgroup group_wdt_macros Macros
304 * \defgroup group_wdt_clk_src_enums Enums
305 * \defgroup group_wdt_functions Functions
306 *
307 */
308 
309 #if !defined(CY_WDT_H)
310 #define CY_WDT_H
311 
312 #include "cy_device.h"
313 
314 #if defined (CY_IP_MXS28SRSS)|| defined (CY_IP_MXS40SSRSS ) || defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS)
315 
316 #include <stdint.h>
317 #include <stdbool.h>
318 #include "cy_syslib.h"
319 #if defined(CY_DEVICE_SECURE)
320     #include "cy_pra.h"
321 #endif /* defined(CY_DEVICE_SECURE) */
322 
323 
324 #if defined(__cplusplus)
325 extern "C" {
326 #endif
327 
328 
329 /*******************************************************************************
330 *       Function Constants
331 *******************************************************************************/
332 
333 /**
334 * \addtogroup group_wdt_macros
335 * \{
336 */
337 
338 /** The driver major version */
339 #define CY_WDT_DRV_VERSION_MAJOR                       1
340 
341 /** The driver minor version */
342 #define CY_WDT_DRV_VERSION_MINOR                       80
343 
344 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
345 /** The internal define for the first iteration of WDT unlocking */
346 #define CY_SRSS_WDT_LOCK_BIT0                           ((uint32_t)0x01U)
347 
348 /** The internal define for the second iteration of WDT unlocking */
349 #define CY_SRSS_WDT_LOCK_BIT1                           ((uint32_t)0x02U)
350 #else
351 /** The internal define for the first iteration of WDT unlocking */
352 #define CY_SRSS_WDT_LOCK_BIT0                           ((uint32_t)0x01U << 30U)
353 
354 /** The internal define for the second iteration of WDT unlocking */
355 #define CY_SRSS_WDT_LOCK_BIT1                           ((uint32_t)0x01U << 31U)
356 #endif
357 
358 /** The WDT default match value */
359 #define CY_SRSS_WDT_DEFAULT_MATCH_VALUE                 ((uint32_t) 4096U)
360 
361 /** The default match value of the WDT ignore bits */
362 #define CY_SRSS_WDT_DEFAULT_IGNORE_BITS                 (0U)
363 
364 /** The default match value of the WDT ignore bits */
365 #define CY_SRSS_WDT_LOCK_BITS                           (3U)
366 
367 /** The WDT driver identifier */
368 #define CY_WDT_ID                                       CY_PDL_DRV_ID(0x34U)
369 
370 /** \cond Internal */
371 
372 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
373 /** The WDT maximum match value */
374 #define WDT_MAX_MATCH_VALUE                      ((0xFFFFFFFFuL) >> (32 - SRSS_NUM_WDT_A_BITS))
375 /* Internal macro to validate match value */
376 #define CY_WDT_IS_IGNORE_BITS_ABOVE_VALID(bitPos)     ((bitPos) < SRSS_NUM_WDT_A_BITS)
377 
378 /** The WDT maximum Ignore Bits */
379 #define WDT_MAX_IGNORE_BITS                      (SRSS_NUM_WDT_A_BITS - 1U)
380 
381 #else
382 /** The WDT maximum match value */
383 #define WDT_MAX_MATCH_VALUE                      (0xFFFFuL)
384 
385  /** The WDT maximum Ignore Bits */
386 #define WDT_MAX_IGNORE_BITS                      (0xFuL)
387 #endif
388 
389 
390  /* Internal macro to validate match value */
391  #define CY_WDT_IS_MATCH_VAL_VALID(match)        ((match) <= WDT_MAX_MATCH_VALUE)
392 
393 /* Internal macro to validate match value */
394 #define CY_WDT_IS_IGNORE_BITS_VALID(bitsNum)     ((bitsNum) <= WDT_MAX_IGNORE_BITS)
395 
396 /* The WDT needs 4 cycles to switch away from existing source.
397  * The source clock of wdt is fixed to 32KHz. So 4 cycles become 122us */
398 #define CY_WDT_SRC_CLK_SWITCH_DELAY              (122UL)
399 
400 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
401 /** The WDT default match value */
402 /**
403 * \note
404 * This Macro is available for CAT1C devices.
405 **/
406 #define CY_WDT_DEFAULT_MATCH_VALUE                     (32000UL) // 1 sec when clk_lf = 32KHz
407 
408 /** The WDT default LOWER_LIMIT value */
409 /**
410 * \note
411 * This Macro is available for CAT1C devices.
412 **/
413 #define CY_WDT_DEFAULT_LOWER_LIMIT                     (0U)
414 
415 /** The WDT default UPPER_LIMIT value */
416 /**
417 * \note
418 * This Macro is available for CAT1C devices.
419 **/
420 #define CY_WDT_DEFAULT_UPPER_LIMIT                     CY_WDT_DEFAULT_MATCH_VALUE
421 
422 /** The WDT default WARN_LIMIT value */
423 /**
424 * \note
425 * This Macro is available for CAT1C devices.
426 **/
427 #define CY_WDT_DEFAULT_WARN_LIMIT                     (0U)
428 #endif
429 
430 /**
431 * \note
432 * This Macro is available for CAT1B and CAT1D devices.
433 **/
434 #if defined (CY_IP_MXS22SRSS)
435 /* Internal macro to validate match value */
436 #define CY_WDT_IS_CLK_SRC_VALID(src)         (((src) == CY_WDT_CLK_SOURCE_PILO)  || \
437                                               ((src) == CY_WDT_CLK_SOURCE_BAK))
438 #elif defined (CY_IP_MXS40SSRSS)
439 /* Internal macro to validate match value */
440 #define CY_WDT_IS_CLK_SRC_VALID(src)         (((src) == CY_WDT_CLK_SOURCE_ILO)  || \
441                                               ((src) == CY_WDT_CLK_SOURCE_PILO) || \
442                                               ((src) == CY_WDT_CLK_SOURCE_BAK))
443 #endif
444 
445 /** \endcond */
446 /** \} group_wdt_macros */
447 /**
448 * \addtogroup group_wdt_clk_src_enums
449 * \{
450 */
451 
452 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) ||defined (CY_DOXYGEN)
453 /**
454 * \note
455 * This enum is available for CAT1B and CAT1D devices.
456 **/
457 
458 typedef enum
459 {
460 #if defined (CY_IP_MXS40SSRSS)
461     CY_WDT_CLK_SOURCE_ILO       =     0U, /**< Select the ILO as clock source to WDT */
462 #endif
463     CY_WDT_CLK_SOURCE_PILO      =     1U, /**< Select the PILO as clock source to WDT */
464     CY_WDT_CLK_SOURCE_BAK       =     2U, /**< Select the clk_bak as clock source to WDT */
465 } cy_en_wdt_clk_sources_t;
466 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) ||defined (CY_DOXYGEN) */
467 
468 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
469 /** The wdt lower/upper limit actions. */
470 /**
471 * \note
472 * This Enum is available for CAT1C devices.
473 **/
474 typedef enum
475 {
476     CY_WDT_LOW_UPPER_LIMIT_ACTION_NONE,
477     CY_WDT_LOW_UPPER_LIMIT_ACTION_RESET
478 } cy_en_wdt_lower_upper_action_t;
479 
480 /** The wdt lower/upper limit actions. */
481 /**
482 * \note
483 * This Enum is available for CAT1C devices.
484 **/
485 typedef enum
486 {
487     CY_WDT_WARN_ACTION_NONE,
488     CY_WDT_WARN_ACTION_INT
489 } cy_en_wdt_warn_action_t;
490 
491 /** The wdt Disable/Enable Macros. */
492 /**
493 * \note
494 * This Enum is available for CAT1C devices.
495 **/
496 typedef enum
497 {
498     CY_WDT_DISABLE,
499     CY_WDT_ENABLE
500 } cy_en_wdt_enable_t;
501 #endif
502 
503 /** \} group_wdt_clk_src_enums */
504 
505 
506 /*******************************************************************************
507 *        Function Prototypes
508 *******************************************************************************/
509 /**
510 * \addtogroup group_wdt_functions
511 * @{
512 */
513 /* WDT API */
514 void Cy_WDT_Init(void);
515 void Cy_WDT_Lock(void);
516 void Cy_WDT_Unlock(void);
517 bool Cy_WDT_Locked(void);
518 void Cy_WDT_ClearInterrupt(void);
519 void Cy_WDT_ClearWatchdog(void);
520 
521 __STATIC_INLINE void Cy_WDT_Enable(void);
522 __STATIC_INLINE void Cy_WDT_Disable(void);
523 __STATIC_INLINE bool Cy_WDT_IsEnabled(void);
524 __STATIC_INLINE uint32_t Cy_WDT_GetCount(void);
525 __STATIC_INLINE void Cy_WDT_ResetCounter(void);
526 __STATIC_INLINE void Cy_WDT_MaskInterrupt(void);
527 __STATIC_INLINE void Cy_WDT_UnmaskInterrupt(void);
528 
529 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2) || defined (CY_IP_MXS22SRSS)
530 void Cy_WDT_SetMatch(uint32_t match);
531 void Cy_WDT_SetIgnoreBits(uint32_t bitsNum);
532 __STATIC_INLINE uint32_t Cy_WDT_GetMatch(void);
533 __STATIC_INLINE uint32_t Cy_WDT_GetIgnoreBits(void);
534 
535 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) ||defined (CY_DOXYGEN)
536 void Cy_WDT_SetMatchBits(uint32_t bitPos);
537 __STATIC_INLINE void Cy_WDT_SetClkSource(cy_en_wdt_clk_sources_t src);
538 __STATIC_INLINE cy_en_wdt_clk_sources_t Cy_WDT_GetClkSource(void);
539 __STATIC_INLINE uint32_t Cy_WDT_GetMatchBits(void);
540 #endif
541 
542 #endif
543 
544 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
545 void Cy_WDT_SetLowerLimit(uint32_t match);
546 void Cy_WDT_SetUpperLimit(uint32_t match);
547 void Cy_WDT_SetWarnLimit(uint32_t match);
548 void Cy_WDT_SetLowerAction(cy_en_wdt_lower_upper_action_t action);
549 void Cy_WDT_SetUpperAction(cy_en_wdt_lower_upper_action_t action);
550 void Cy_WDT_SetWarnAction(cy_en_wdt_warn_action_t action);
551 void Cy_WDT_SetAutoService(cy_en_wdt_enable_t enable);
552 void Cy_WDT_SetDeepSleepPause(cy_en_wdt_enable_t enable);
553 void Cy_WDT_SetHibernatePause(cy_en_wdt_enable_t enable);
554 void Cy_WDT_SetDebugRun(cy_en_wdt_enable_t enable);
555 void Cy_WDT_SetService(void);
556 #endif
557 
558 
559 /*******************************************************************************
560 * Function Name: Cy_WDT_Enable
561 ****************************************************************************//**
562 *
563 * Enables the Watchdog timer.
564 *
565 * \sideeffect
566 * This function clears the WDT interrupt.
567 *
568 *******************************************************************************/
Cy_WDT_Enable(void)569 __STATIC_INLINE void Cy_WDT_Enable(void)
570 {
571 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
572     SRSS_WDT_CTL |= WDT_CTL_ENABLE_Msk;
573 #else
574     SRSS_WDT_CTL |= _VAL2FLD(SRSS_WDT_CTL_WDT_EN, 1U);
575 #endif
576 
577     Cy_WDT_ClearInterrupt();
578 }
579 
580 
581 /*******************************************************************************
582 * Function Name: Cy_WDT_Disable
583 ****************************************************************************//**
584 *
585 * Disables the Watchdog timer. The Watchdog timer should be unlocked before being
586 * disabled. Call the Cy_WDT_Unlock() API to unlock the WDT.
587 *
588 *******************************************************************************/
Cy_WDT_Disable(void)589 __STATIC_INLINE void Cy_WDT_Disable(void)
590 {
591 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
592     SRSS_WDT_CTL &= ((uint32_t) ~(_VAL2FLD(WDT_CTL_ENABLE, 1U)));
593 #else
594     SRSS_WDT_CTL &= ((uint32_t) ~(_VAL2FLD(SRSS_WDT_CTL_WDT_EN, 1U)));
595 #endif
596 }
597 
598 
599 /*******************************************************************************
600 * Function Name: Cy_WDT_IsEnabled
601 ****************************************************************************//**
602 *
603 * Reports an enable/disable state of the Watchdog timer.
604 *
605 * \return
606 * - true - if the timer is enabled
607 * - false - if the timer is disabled
608 *
609 *******************************************************************************/
Cy_WDT_IsEnabled(void)610 __STATIC_INLINE bool Cy_WDT_IsEnabled(void)
611 {
612 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
613     return _FLD2BOOL(WDT_CTL_ENABLE, SRSS_WDT_CTL);
614 #else
615     return _FLD2BOOL(SRSS_WDT_CTL_WDT_EN, SRSS_WDT_CTL);
616 #endif
617 }
618 
619 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2) || defined (CY_IP_MXS22SRSS)
620 
621 /*******************************************************************************
622 * Function Name: Cy_WDT_GetMatch
623 ****************************************************************************//**
624 *
625 * Reads the WDT counter match comparison value.
626 *
627 * \return The counter match value.
628 *
629 * \note
630 * This API is available for CAT1A, CAT1B and CAT1D devices.
631 *
632 *******************************************************************************/
Cy_WDT_GetMatch(void)633 __STATIC_INLINE uint32_t Cy_WDT_GetMatch(void)
634 {
635     return ((uint32_t) _FLD2VAL(SRSS_WDT_MATCH_MATCH, SRSS_WDT_MATCH));
636 }
637 
638 /*******************************************************************************
639 * Function Name: Cy_WDT_GetIgnoreBits
640 ****************************************************************************//**
641 *
642 * Reads the number of the most significant bits of the Watchdog timer that are
643 * not checked against the match.
644 *
645 * \return The number of the most significant bits.
646 *
647 * \note
648 * This API is available for CAT1A, CAT1B and CAT1D devices.
649 *
650 *******************************************************************************/
Cy_WDT_GetIgnoreBits(void)651 __STATIC_INLINE uint32_t Cy_WDT_GetIgnoreBits(void)
652 {
653 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
654     return((uint32_t) (WDT_MAX_IGNORE_BITS - _FLD2VAL(SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE, SRSS_WDT_MATCH2)));
655 #else
656     return((uint32_t) _FLD2VAL(SRSS_WDT_MATCH_IGNORE_BITS, SRSS_WDT_MATCH));
657 #endif
658 }
659 
660 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)
661 /*******************************************************************************
662 * Function Name: Cy_WDT_SetClkSource
663 ****************************************************************************//**
664 *
665 * Configures the WDT clock source
666 *
667 * \param src
668 * \ref cy_en_wdt_clk_sources_t
669 *
670 * \note
671 * This API is available for CAT1B and CAT1D devices.
672 *
673 * \note  It takes four cycles of the originally selected clock to switch away
674 * from it.  Do not disable the original clock during this time.
675 *
676 *******************************************************************************/
Cy_WDT_SetClkSource(cy_en_wdt_clk_sources_t src)677 __STATIC_INLINE void Cy_WDT_SetClkSource(cy_en_wdt_clk_sources_t src)
678 {
679     CY_ASSERT_L2(CY_WDT_IS_CLK_SRC_VALID(src));
680 
681     if (false == Cy_WDT_Locked())
682     {
683         SRSS_WDT_CTL = _CLR_SET_FLD32U((SRSS_WDT_CTL), SRSS_WDT_CTL_WDT_CLK_SEL, src);
684         /** Adding 4 cycle delay */
685         Cy_SysLib_DelayUs((uint16_t)CY_WDT_SRC_CLK_SWITCH_DELAY);
686     }
687 }
688 
689 /*******************************************************************************
690 * Function Name: Cy_WDT_GetClkSource
691 ****************************************************************************//**
692 *
693 * Gets the WDT clock source configured.
694 *
695 * \return The Clock source enum \ref cy_en_wdt_clk_sources_t
696 *
697 * \note
698 * This API is available for CAT1B and CAT1D devices.
699 *
700 *******************************************************************************/
Cy_WDT_GetClkSource(void)701 __STATIC_INLINE cy_en_wdt_clk_sources_t Cy_WDT_GetClkSource(void)
702 {
703     CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_wdt_clk_sources_t enum.');
704     return ((cy_en_wdt_clk_sources_t) _FLD2VAL(SRSS_WDT_CTL_WDT_CLK_SEL, SRSS_WDT_CTL));
705 }
706 
707 /*******************************************************************************
708 * Function Name: Cy_WDT_GetMatchBits
709 ****************************************************************************//**
710 *
711 * Gets the bit position above which the bits will be ignored for match.
712 *
713 * \return The bit position above which the bits will be ignored for match.
714 *
715 * \note
716 * This API is available for CAT1B and CAT1D devices.
717 *
718 *******************************************************************************/
Cy_WDT_GetMatchBits(void)719 __STATIC_INLINE uint32_t Cy_WDT_GetMatchBits(void)
720 {
721     return((uint32_t) (_FLD2VAL(SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE, SRSS_WDT_MATCH2)));
722 }
723 #endif
724 
725 #endif /*defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2) */
726 
727 
728 /*******************************************************************************
729 * Function Name: Cy_WDT_GetCount
730 ****************************************************************************//**
731 *
732 * Reads the current WDT counter value.
733 *
734 * \return A live counter value.
735 *
736 *******************************************************************************/
Cy_WDT_GetCount(void)737 __STATIC_INLINE uint32_t Cy_WDT_GetCount(void)
738 {
739 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
740     return ((uint32_t) _FLD2VAL(WDT_CNT_CNT, SRSS_WDT_CNT));
741 #else
742     return ((uint32_t) _FLD2VAL(SRSS_WDT_CNT_COUNTER, SRSS_WDT_CNT));
743 #endif
744 }
745 
746 /*******************************************************************************
747 * Function Name: Cy_WDT_ResetCounter
748 ****************************************************************************//**
749 *
750 * Resets the WDT counter value.
751 *
752 * \note
753 * This API must be called only after WDT is disabled, else the writes will be
754 * ignored if WDT is enabled.
755 *
756 *
757 *******************************************************************************/
Cy_WDT_ResetCounter(void)758 __STATIC_INLINE void Cy_WDT_ResetCounter(void)
759 {
760     SRSS_WDT_CNT = 0x0U;
761 }
762 
763 /*******************************************************************************
764 * Function Name: Cy_WDT_MaskInterrupt
765 ****************************************************************************//**
766 *
767 * After masking interrupts from the WDT, they are not passed to the CPU.
768 * This function does not disable the WDT-reset generation.
769 *
770 *******************************************************************************/
Cy_WDT_MaskInterrupt(void)771 __STATIC_INLINE void Cy_WDT_MaskInterrupt(void)
772 {
773 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
774     SRSS_WDT_INTR_MASK &= ~WDT_INTR_MASK_WDT_Msk;
775 #else
776     #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE)
777         CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_MASK_WDT_MATCH, 0U);
778     #else
779         SRSS_SRSS_INTR_MASK &= (uint32_t)(~ _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U));
780     #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */
781 #endif
782 }
783 
784 
785 /*******************************************************************************
786 * Function Name: Cy_WDT_UnmaskInterrupt
787 ****************************************************************************//**
788 *
789 * After unmasking interrupts from the WDT, they are passed to CPU.
790 * This function does not impact the reset generation.
791 *
792 *******************************************************************************/
Cy_WDT_UnmaskInterrupt(void)793 __STATIC_INLINE void Cy_WDT_UnmaskInterrupt(void)
794 {
795 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
796     SRSS_WDT_INTR_MASK |= WDT_INTR_MASK_WDT_Msk;
797 #else
798     #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE)
799         CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U);
800     #else
801         SRSS_SRSS_INTR_MASK |= _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U);
802     #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */
803 #endif
804 }
805 /** \} group_wdt_functions */
806 
807 #if defined(__cplusplus)
808 }
809 #endif
810 
811 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SRSS */
812 
813 #endif /* CY_WDT_H */
814 
815 /** \} group_wdt */
816 
817 
818 /* [] END OF FILE */
819