1 /***************************************************************************//** 2 * \file cy_ethif.h 3 * \version 1.20 4 * 5 * Provides an API declaration of the Ethernet Interface driver 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2020 Cypress Semiconductor Corporation 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 *******************************************************************************/ 24 25 /** 26 * \addtogroup group_ethif 27 * \{ 28 * 29 * Ethernet is a well-defined industry specification. Ethernet MAC module 30 * transmits and receives IEEE 802.3 frames by connecting with the PHY device 31 * using MII/RMII/GMII or RGMII interface. Ethernet MAC also supports 10/100/1000 32 * Transfer rates and IEEE 1588 time stamp feature. Infineon uses a third-party 33 * Ethernet MAC IP from Cadence GEM_GXL, which is a Gigabit Ethernet MAC. 34 * 35 * \note Ethernet MAC does not support "Wake on Lan" feature. So when the system is 36 * in deep sleep, it can't receive any Rx frames. 37 * 38 * Below block diagram shows the hardware and software partition inside the MCU. 39 * Ethernet MAC IP hardware directly interface with external ethernet PHY via MII 40 * or RMII or GMII or RGMII interface and MDIO interface is for configuring the 41 * Ethernet PHY chip/device. The software section consists of three major layers 42 * Ethernet PDL (Peripheral Driver Library), Connectivity Middleware, and 43 * Applications. Ethernet PDL implements low level driver for Ethernet MAC and a 44 * generic driver for the external Ethernet PHY chips. 45 * 46 * \image html ethernet_system.png "Ethernet Block Diagram" 47 * 48 * The ETHIF driver is wrapper around Cadence's EMAC core driver. This is a 49 * network interface driver to Cadence core EMAC driver. It provides APIs to 50 * communicate with Ethernet IP. The PHY driver also uses this driver to 51 * communicate with PHY chip (via application). This driver has internal buffer 52 * management, handling callbacks from Cadence EMAC during transport, etc. 53 * 54 * The functions and other declarations used in this driver are in cy_ethif.h. 55 * You can include cy_pdl.h (ModusToolbox only) to get access to all functions 56 * and declarations in the PDL. 57 * 58 * \section group_ethif_tx_rx_programming Tx/Rx Programming 59 * 60 * 1. Make sure all the pins connected between MAC and PHY is configured properly. 61 * 2. Enable Interrupts for Ethernet queues. This is used to receive events from driver. 62 * 3. Initialize MAC using \ref Cy_ETHIF_Init() API. 63 * 4. Optionally set filters. 64 * 5. PHY chip is outside of silicon. Initialize PHY using EPHY driver. Some PHY chip 65 * needs configuration using it's proprietary(extended) registers. Fo this 66 * refer to PHY data sheet. 67 * 6. Wait for link to be up. This can be done using EPHY APIs. 68 * 7. Once is link is up, then transmit frame using \ref Cy_ETHIF_TransmitFrame() API. 69 * 8. The receive callback is called when there is any frame received by MAC. The 70 * receive callback is registered during \ref Cy_ETHIF_Init() API call. 71 * 72 * \section group_ethif_more_information More Information 73 * 74 * Refer to the technical reference manual (TRM) and the device datasheet. 75 * 76 * \section group_ethif_MISRA MISRA-C Compliance 77 * The Ethernet driver has no specific deviations 78 * 79 * \section group_ethif_changelog Changelog 80 * <table class="doxtable"> 81 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> 82 * <tr> 83 * <td>1.20</td> 84 * <td>updated documentation and pre-processor check for CM55.</td> 85 * <td>Code enhancement.</td> 86 * </tr> 87 * <tr> 88 * <td>1.10.1</td> 89 * <td>Build warning fixes due to redefinitions.</td> 90 * <td>Bug fixes.</td> 91 * </tr> 92 * <tr> 93 * <td>1.10</td> 94 * <td>Updated an internal API and fixed MISRA 2012 violations.</td> 95 * <td>MISRA 2012 compliance and code enhancement.</td> 96 * </tr> 97 * <tr> 98 * <td>1.0</td> 99 * <td>Initial version</td> 100 * <td></td> 101 * </tr> 102 * </table> 103 * 104 * \defgroup group_ethif_macros Macros 105 * \defgroup group_ethif_functions Functions 106 * \defgroup group_ethif_data_structures Data Structures 107 * \defgroup group_ethif_enums Enumerated Types 108 */ 109 110 #if !defined (CY_ETHIF_H) 111 #define CY_ETHIF_H 112 113 #include "cy_device.h" 114 115 #if defined (CY_IP_MXETH) 116 117 #include <stddef.h> 118 #include "cy_syslib.h" 119 120 #if defined(__cplusplus) 121 extern "C" { 122 #endif 123 124 /** \addtogroup group_ethif_macros 125 * \{ 126 */ 127 128 /** Driver major version */ 129 #define CY_ETHIF_DRV_VERSION_MAJOR 1 130 131 /** Driver minor version */ 132 #define CY_ETHIF_DRV_VERSION_MINOR 20 133 134 /** Eth driver ID */ 135 #define CY_ETHIF_ID CY_PDL_DRV_ID(0x71U) 136 137 /** \} group_ethif_macros */ 138 139 /*************************************** 140 * Constants 141 ***************************************/ 142 143 /** \cond INTERNAL */ 144 145 /*############################################################################## 146 * USER DEFINES 147 *#############################################################################*/ 148 /** Ethernet configurations constants */ 149 #define CY_ETH_STANDARD_BD (0U) /* Standard Buffer Descriptor Mode */ 150 #define CY_ETH_EXTENDED_BD (1U) /* Extended Buffer Descriptor Mode */ 151 152 /* DMA operational mode */ 153 #define CY_ETH_TX_FSFM (0U) /* Full Store and Forward Mode [FSFM] for Tx */ 154 #define CY_ETH_TX_PSFM (1U) /* Partial Store and Forward Mode [PSFM] for Tx */ 155 #define CY_ETH_RX_FSFM (2U) /* Full Store and Forward Mode for Rx */ 156 #define CY_ETH_RX_PSFM (3U) /* Partial Store and Forward Mode for Rx */ 157 158 /** Ethernet channel */ 159 #define CY_ETH_DEFINE_NUM_IP (CY_IP_MXETH_INSTANCES) /* Number of Ethernet channels intended to use, maximum 2 */ 160 #define CY_ETH_DEFINE_NUM_RXQS (2U) /* Number of queues intended to use, maximum 2 */ 161 #define CY_ETH_DEFINE_NUM_TXQS (3U) /* Number of queues intended to use, maximum 3 */ 162 163 /** Ethernet Operation Mode */ 164 #define CY_ETH_DEFINE_TX_OP_MODE CY_ETH_TX_FSFM /* FSFM OR PSFM */ 165 #define CY_ETH_DEFINE_RX_OP_MODE CY_ETH_RX_FSFM /* FSFM OR PSFM */ 166 #define CY_ETH_DEFINE_TX_WATERMARK (50U) /* Watermark level for Tx */ 167 #define CY_ETH_DEFINE_RX_WATERMARK (50U) /* Watermark level for Rx */ 168 169 /** Buffer Descriptor mode */ 170 #define CY_ETH_DEFINE_BD CY_ETH_EXTENDED_BD /* standard or extended */ 171 172 /** Memory Allocation defines */ /* Frame Buffers are allocated based on number of buffer descriptors */ 173 #define CY_ETH_DEFINE_TOTAL_BD_PER_TXQUEUE (2U) /* Total number of Buffer Descriptors allocated for each transmit queue */ 174 #define CY_ETH_DEFINE_TOTAL_BD_PER_RXQUEUE (4U) /* Total number of Buffer Descriptors allocated for each receive queue */ 175 /*############################################################################*/ 176 177 178 /** Ethernet configurations constants */ 179 #define CY_ETH_TX_PBUF_SIZE (0x1U) /* dma_config[bit-10] 1: Use full configured addressable space (4Kb) */ 180 #define CY_ETH_RX_PBUF_SIZE (0x3U) /* dma_config[bit-8:9]3: Use full configured addressable space (8Kb) */ 181 182 /** Ethernet channel */ 183 #define CY_ETHIF_INSTANCE_0 (0U) /* channel ETH0 considered instance 0 for driver reference */ 184 #define CY_ETHIF_INSTANCE_1 (1U) /* channel ETH1 considered instance 1 for driver reference */ 185 186 #define CY_ETH0_TYPE (ETH0) /* This includes both GEMGXL and Wrapper */ 187 #define CY_ETH0_ADDR_REG_BASE (ETH0_BASE) /* Register area for ETH0 */ 188 #define CY_ETH0_GEMGXL_ADDR_REGBASE (ETH0_BASE + 0x00001000UL) /* Register area for GEMGXL */ 189 190 #if (CY_IP_MXETH_INSTANCES > 1u) 191 #define CY_ETH1_TYPE (ETH1) /* This includes both GEMGXL and Wrapper */ 192 #define CY_ETH1_ADDR_REG_BASE (ETH1_BASE) /* Register area for ETH1 */ 193 #define CY_ETH1_GEMGXL_ADDR_REGBASE (ETH1_BASE + 0x00001000UL) /* Register area for GEMGXL */ 194 #endif /* (CY_IP_MXETH_INSTANCES > 1u) */ 195 196 /** Driver constants */ 197 #define CY_ETH_SIZE_MIN_FRAME (64U) /* Min Frame size */ 198 #define CY_ETH_SIZE_MAX_FRAME (1536U) /* Max Frame size */ 199 #define CY_ETH_SIZE_BUF_TXQ_RXQ (1536U) /* Tx/Rx buffer size */ 200 201 #if (CY_ETH_DEFINE_BD == CY_ETH_EXTENDED_BD) 202 #define CY_ETH_BD_SIZE (16U) /* 16 Bytes */ 203 #else 204 #define CY_ETH_BD_SIZE (8U) /* 8 Bytes */ 205 #endif 206 207 #define CY_ETH_DISABLE_0 (0U) 208 #define CY_ETH_ENABLE_1 (1U) 209 #define CY_ETH_MDIO_BUSY_0 (0U) 210 #define CY_ETH_MDIO_IDLE_1 (1U) 211 #define CY_ETH_QS0_0 (0U) 212 #define CY_ETH_QS1_1 (1U) 213 #define CY_ETH_QS2_2 (2U) 214 #define CY_ETH_QS3_3 (3U) 215 #define CY_ETH_NOT_INITIALIZE_0 (0U) 216 #define CY_ETH_INITIALIZE_1 (1U) 217 #define CY_ETHIF_BUFFER_CLEARED_0 (0U) 218 219 #define CY_ETH_TOTAL_TX_BUF (CY_ETH_DEFINE_NUM_IP * CY_ETH_DEFINE_NUM_TXQS * CY_ETH_DEFINE_TOTAL_BD_PER_TXQUEUE) 220 #define CY_ETH_TOTAL_RX_BUF (CY_ETH_DEFINE_NUM_IP * CY_ETH_DEFINE_NUM_RXQS * CY_ETH_DEFINE_TOTAL_BD_PER_RXQUEUE * 2U) // *2 is to replace the already provided buffer to BDs 221 222 #define CY_ETHIF_NO_BUFFER_AVAILABLE (255U) 223 #define CY_ETHIF_BUFFER_AVAILABLE (254U) 224 225 #define CY_ETHIF_MDIO_READ_FAILED (2U) 226 #define CY_ETHIF_PHY_FLAG (0U) // defines clause 22 227 228 #define CY_ETHIF_TX_STATUS_CLEAR (0x000001FFUL) 229 230 #define CY_EHTIF_EMPTYVALUE (0xBAADF00DUL) 231 232 #define CY_ETHIF_PAUSE_P0 (0U) 233 #define CY_ETHIF_PAUSE_P1 (1U) 234 #define CY_ETHIF_PAUSE_P2 (2U) 235 #define CY_ETHIF_PAUSE_P3 (3U) 236 #define CY_ETHIF_PAUSE_P4 (4U) 237 #define CY_ETHIF_PAUSE_P5 (5U) 238 #define CY_ETHIF_PAUSE_P6 (6U) 239 #define CY_ETHIF_PAUSE_P7 (7U) 240 241 #if (CY_IP_MXETH_INSTANCES > 1u) 242 #define CY_ETHIF_IS_IP_INSTANCE_VALID(base) (((base) == CY_ETH0_TYPE) || ((base) == CY_ETH1_TYPE)) 243 #define CY_ETHIF_IP_INSTANCE(base) (((base) == CY_ETH0_TYPE) ? CY_ETHIF_INSTANCE_0 : CY_ETHIF_INSTANCE_1) 244 #define CY_ETHIF_IP_ADDR_REGBASE(instance) (((instance) == CY_ETHIF_INSTANCE_0) ? CY_ETH0_TYPE : CY_ETH1_TYPE) 245 #define CY_ETHIF_GEMGXL_ADDR_REGBASE(instance) (((instance) == CY_ETHIF_INSTANCE_0) ? CY_ETH0_GEMGXL_ADDR_REGBASE : CY_ETH1_GEMGXL_ADDR_REGBASE) 246 #else 247 #define CY_ETHIF_IS_IP_INSTANCE_VALID(base) ((base) == CY_ETH0_TYPE) 248 #define CY_ETHIF_IP_INSTANCE(base) (((base) == CY_ETH0_TYPE) ? CY_ETHIF_INSTANCE_0 : CY_ETHIF_INSTANCE_0) 249 #define CY_ETHIF_IP_ADDR_REGBASE(instance) (((instance) == CY_ETHIF_INSTANCE_0) ? CY_ETH0_TYPE : CY_ETH0_TYPE) 250 #define CY_ETHIF_GEMGXL_ADDR_REGBASE(instance) (((instance) == CY_ETHIF_INSTANCE_0) ? CY_ETH0_GEMGXL_ADDR_REGBASE : CY_ETH0_GEMGXL_ADDR_REGBASE) 251 #endif 252 253 /** \endcond */ 254 255 /** \addtogroup group_ethif_macros 256 * \{ 257 */ 258 259 /* Bit-flags to specify DMA config register bits 24-27; see EMAC User Guide for details. */ 260 #define CY_ETHIF_CFG_DMA_DISC_RXP (0x01U) /**< The DMA will automatically discard receive packets from the receiver packet buffer memory when no AMBA (AXI) resource is available. */ 261 #define CY_ETHIF_CFG_DMA_FRCE_RX_BRST (0x02U) /**< Force the RX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer) transfers. */ 262 #define CY_ETHIF_CFG_DMA_FRCE_TX_BRST (0x04U) /**< Force the TX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer) transfers. */ 263 264 /** \} group_ethif_macros */ 265 266 /*************************************** 267 * Enumerations 268 ***************************************/ 269 270 /** 271 * \addtogroup group_ethif_enums 272 * \{ 273 */ 274 275 /** 276 ***************************************************************************** 277 ** \brief Ethernet MAC driver error codes. 278 ** 279 *****************************************************************************/ 280 typedef enum 281 { 282 CY_ETHIF_SUCCESS = 0U, /**< Returned successful */ 283 CY_ETHIF_BAD_PARAM, /**< Bad parameter was passed */ 284 CY_ETHIF_MEMORY_NOT_ENOUGH, /**< Assigned memory for BDs not enough */ 285 CY_ETHIF_LINK_DOWN, /**< Link between nodes is not up */ 286 CY_ETHIF_LINK_UP, /**< Link between nodes is up */ 287 CY_ETHIF_BUFFER_NOT_AVAILABLE, /**< No local buffer available to send the frame */ 288 } cy_en_ethif_status_t; 289 290 291 /** 292 ***************************************************************************** 293 ** \brief Ethernet MAC driver buffer status. 294 ** 295 *****************************************************************************/ 296 typedef enum 297 { 298 CY_ETHIF_BUFFER_UNINIT = 0U, /**< Buffer Uninitialized */ 299 CY_ETHIF_BUFFER_FREE, /**< Buffer free and cleared with CY_EHTIF_EMPTYVALUE */ 300 CY_ETHIF_BUFFER_OCCUPIED, /**< Buffer has been allocated to BD or in case of Tx loaded with the source data */ 301 CY_ETHIF_BUFFER_RELEASED, /**< Buffer has been used and can be written with CY_EHTIF_EMPTYVALUE */ 302 } cy_en_ethif_buffer_status_t; 303 304 305 /** 306 ***************************************************************************** 307 ** \brief Ethernet MAC Drive Modes. 308 ** 309 *****************************************************************************/ 310 typedef enum 311 { 312 CY_ETHIF_CTL_MII_10 = 0U, /**< PHY mode MII - 10Mbps */ 313 CY_ETHIF_CTL_MII_100 = 1U, /**< PHY mode MII - 100Mbps */ 314 CY_ETHIF_CTL_GMII_1000 = 2U, /**< PHY mode GMII - 1000Mbps */ 315 CY_ETHIF_CTL_RGMII_10 = 3U, /**< PHY mode RGMII - 10Mbps (4bits/Cycle) */ 316 CY_ETHIF_CTL_RGMII_100 = 4U, /**< PHY mode RGMII - 100Mbps (4bits/Cycle) */ 317 CY_ETHIF_CTL_RGMII_1000 = 5U, /**< PHY mode RGMII - 1000Mbps (8bits/Cycle) */ 318 CY_ETHIF_CTL_RMII_10 = 6U, /**< PHY mode RMII - 10Mbps */ 319 CY_ETHIF_CTL_RMII_100 = 7U, /**< PHY mode RMII - 100Mbps */ 320 } cy_en_ethif_speed_sel_t; 321 322 323 /** 324 ***************************************************************************** 325 ** \brief Reference Clock for RMII/RGMII. 326 ** 327 *****************************************************************************/ 328 typedef enum 329 { 330 CY_ETHIF_EXTERNAL_HSIO = 0U, /**< Clock coming from HSIO */ 331 CY_ETHIF_INTERNAL_PLL, /**< Clock referenced from Internal PLL source */ 332 } cy_en_ethif_clock_ref_t; 333 334 335 /** 336 ***************************************************************************** 337 ** \brief MAC filter types 338 ** 339 *****************************************************************************/ 340 typedef enum 341 { 342 CY_ETHIF_FILTER_TYPE_DESTINATION = 0U, /**< filter on destination address */ 343 CY_ETHIF_FILTER_TYPE_SOURCE = 1U, /**< filter on source address */ 344 } cy_en_ethif_filter_type_t; 345 346 347 /** 348 ***************************************************************************** 349 ** \brief Total number of filters supported 350 ** 351 *****************************************************************************/ 352 typedef enum 353 { 354 CY_ETHIF_FILTER_NUM_1 = 1U, /**< filter 1 */ 355 CY_ETHIF_FILTER_NUM_2 = 2U, /**< filter 2 */ 356 CY_ETHIF_FILTER_NUM_3 = 3U, /**< filter 3 */ 357 CY_ETHIF_FILTER_NUM_4 = 4U, /**< filter 4 */ 358 CY_ETHIF_FILTER_NUM_INV, /**< Invalid Filter */ 359 } cy_en_ethif_filter_num_t; 360 361 362 /** 363 ***************************************************************************** 364 ** \brief Transmit Time stamp modes 365 ** 366 *****************************************************************************/ 367 typedef enum 368 { 369 CY_ETHIF_TX_TS_DISABLED = 0U, 370 CY_ETHIF_TX_TS_PTP_EVENT_ONLY = 1U, 371 CY_ETHIF_TX_TS_PTP_ALL = 2U, 372 CY_ETHIF_TX_TS_ALL = 3U, 373 } cy_en_ethif_TxTs_mode_t; 374 375 376 /** 377 ***************************************************************************** 378 ** \brief Receive Time stamp modes 379 ** 380 *****************************************************************************/ 381 typedef enum 382 { 383 CY_ETHIF_RX_TS_DISABLED = 0U, 384 CY_ETHIF_RX_TS_PTP_EVENT_ONLY = 1U, 385 CY_ETHIF_RX_TS_PTP_ALL = 2U, 386 CY_ETHIF_RX_TS_ALL = 3U, 387 } cy_en_ethif_RxTs_mode_t; 388 389 390 /** 391 ***************************************************************************** 392 ** \brief DMA data buffer length 393 ** 394 *****************************************************************************/ 395 typedef enum 396 { 397 CY_ETHIF_DMA_DBUR_LEN_1 = 0U, /**< Single burst */ 398 CY_ETHIF_DMA_DBUR_LEN_4 = 1U, /**< Burst upto 4 */ 399 CY_ETHIF_DMA_DBUR_LEN_8 = 2U, /**< Burst upto 8 */ 400 CY_ETHIF_DMA_DBUR_LEN_16 = 3U, /**< Burst upto 16 */ 401 } cy_en_ethif_dma_data_buffer_len_t; 402 403 404 /** 405 ***************************************************************************** 406 ** \brief MDC clock divider 407 ** 408 *****************************************************************************/ 409 typedef enum 410 { 411 CY_ETHIF_MDC_DIV_BY_8 = 0U, /**< Divide by 8 */ 412 CY_ETHIF_MDC_DIV_BY_16 = 1U, /**< Divide by 16 */ 413 CY_ETHIF_MDC_DIV_BY_32 = 2U, /**< Divide by 32 */ 414 CY_ETHIF_MDC_DIV_BY_48 = 3U, /**< Divide by 48 */ 415 CY_ETHIF_MDC_DIV_BY_64 = 4U, /**< Divide by 64 */ 416 CY_ETHIF_MDC_DIV_BY_96 = 5U, /**< Divide by 96 */ 417 CY_ETHIF_MDC_DIV_BY_128 = 6U, /**< Divide by 128 */ 418 CY_ETHIF_MDC_DIV_BY_224 = 7U, /**< Divide by 224 */ 419 } cy_en_ethif_dma_mdc_clk_div_t; 420 421 422 /** \} group_ethif_enums */ 423 424 425 /*************************************** 426 * Configuration Structures 427 ***************************************/ 428 /** 429 * \addtogroup group_ethif_data_structures 430 * \{ 431 */ 432 433 434 /** 435 ***************************************************************************** 436 ** \brief Wrapper Configuration 437 *****************************************************************************/ 438 typedef struct 439 { 440 cy_en_ethif_speed_sel_t stcInterfaceSel; /**< Interface selection for ENET */ 441 cy_en_ethif_clock_ref_t bRefClockSource; /**< Reference clock selection */ 442 uint8_t u8RefClkDiv; /**< Actual division would be u8RefClkDiv + 1 */ 443 } cy_stc_ethif_wrapper_config_t; 444 445 446 /** 447 ***************************************************************************** 448 ** \brief Tx/Rx Queue status 449 *****************************************************************************/ 450 typedef struct 451 { 452 bool bTxQueueDisable[CY_ETH_QS2_2+1]; /**< Tx Queue0-2 || 0: Queue Enabled, 1: Queue Disabled */ 453 bool bRxQueueDisable[CY_ETH_QS2_2+1]; /**< Rx Queue0-2 || 0: Queue Enabled, 1: Queue Disabled */ 454 } cy_stc_ethif_queue_disablestatus_t; 455 456 457 /** 458 ***************************************************************************** 459 ** \brief Virtual and physical addresses of DMA-addressable data buffer 460 *****************************************************************************/ 461 typedef struct 462 { 463 uintptr_t vAddr; /**< Virtual address */ 464 uintptr_t pAddr; /**< Physical address */ 465 } cy_stc_ethif_buff_addr_t; 466 467 468 /** 469 ***************************************************************************** 470 ** \brief Buffer status 471 *****************************************************************************/ 472 typedef struct 473 { 474 cy_stc_ethif_buff_addr_t cy_ethif_bufaddr; /**< Buffer address as per requirement by Cadence driver */ 475 cy_en_ethif_buffer_status_t enBufStatus; /**< Buffer status */ 476 } cy_stc_ethif_bufstatus_t; 477 478 479 /** 480 ***************************************************************************** 481 ** \brief 1588 Timer value 482 *****************************************************************************/ 483 typedef struct 484 { 485 /** Upper 16 bits of seconds value */ 486 uint16_t secsUpper; 487 /** Lower 32 bits of seconds value */ 488 uint32_t secsLower; 489 /** Upper Nanoseconds value (30 bits) */ 490 uint32_t nanosecs; 491 } cy_stc_ethif_1588_timer_val_t; 492 493 494 /** 495 ***************************************************************************** 496 ** \brief writing/reading the 1588 timer increment registers 497 *****************************************************************************/ 498 typedef struct 499 { 500 /** Whole nanoseconds to increment timer each clock cycle */ 501 uint8_t nanoSecsInc; 502 /** Sub-nanoseconds to increment the timer (16 bits) */ 503 uint16_t subNsInc; 504 /** Lower 8 bits of sub-nanoseconds to increment the timer */ 505 uint8_t lsbSubNsInc; 506 /** Number of increments before changing to alternative increment. If = 0 then never use alternative increment. */ 507 uint8_t altIncCount; 508 /** Alternative nanoseconds increment to apply */ 509 uint8_t altNanoSInc; 510 } cy_stc_ethif_timer_increment_t; 511 512 513 /** struct for writing/reading 1588 timer */ 514 typedef struct 515 { 516 cy_stc_ethif_1588_timer_val_t * pstcTimerValue; /**< TSU Timer value */ 517 cy_stc_ethif_timer_increment_t * pstcTimerIncValue; /**< TSU Timer increment value */ 518 bool bOneStepTxSyncEnable; /**< One step sync enable */ 519 cy_en_ethif_TxTs_mode_t enTxDescStoreTimeStamp; /**< Store Time stamp value in Tx descriptor */ 520 cy_en_ethif_RxTs_mode_t enRxDescStoreTimeStamp; /**< Store Time stamp value in Rx descriptor */ 521 bool bStoreNSinRxDesc; /**< Store NanoSecond field of TSU in Rx Descriptor */ 522 } cy_stc_ethif_tsu_config_t; 523 524 525 /** 526 ***************************************************************************** 527 ** \brief Frame transmission complete callback function. Signals a successful 528 ** completed transmission. 529 ** 530 ** \param base[IN] Pointer to register area of Ethernet MAC 531 ** \param u8Queue[IN] Queue used for transmitting the frame 532 *****************************************************************************/ 533 typedef void (*cy_ethif_tx_msg_cb_t)(ETH_Type *base, uint8_t u8QueueIndex); 534 535 536 /** 537 ***************************************************************************** 538 ** \brief Frame transmission Error callback function. Signals a transmission 539 ** error. 540 ** 541 ** \param base[IN] Pointer to register area of Ethernet MAC 542 ** \param u8Queue[IN] Queue used for transmitting the frame 543 *****************************************************************************/ 544 typedef void (*cy_ethif_tx_error_cb_t)(ETH_Type *base, uint8_t u8QueueIndex); 545 546 547 /** 548 ***************************************************************************** 549 ** \brief Frame received callback function. Signals a successful reception 550 ** of frame. 551 ** 552 ** \param base[IN] Pointer to register area of Ethernet MAC 553 ** \param u8RxBuffer[IN] Receive frame buffer 554 ** \param u32Length[IN] Frame buffer length 555 *****************************************************************************/ 556 typedef void (*cy_ethif_rx_frame_cb_t)(ETH_Type *base, uint8_t * u8RxBuffer, uint32_t u32Length); 557 558 559 /** 560 ***************************************************************************** 561 ** \brief TSU Second counter increment callback function. Signals a One second 562 ** increment in the TSU. 563 ** 564 ** \param base[IN] Pointer to register area of Ethernet MAC 565 *****************************************************************************/ 566 typedef void (*cy_ethif_tsu_inc_cb_t)(ETH_Type *base); 567 568 /** 569 ***************************************************************************** 570 ** \brief Get Buffer callback function. Driver call this for getting free 571 ** buffer for filling subsequent receive frame. 572 ** 573 ** \param base[IN] Pointer to register area of Ethernet MAC 574 ** \param u8RxBuffer[OUT] 32 bytes aligned Frame buffer 575 ** \param u32Length[OUT] Frame buffer length 576 *****************************************************************************/ 577 typedef void (*cy_ethif_rx_getbuffer_cb_t)(ETH_Type *base, uint8_t **u8RxBuffer, uint32_t *u32Length); 578 579 580 /** 581 ***************************************************************************** 582 ** \brief Pointer to a Buffer pool. 583 *****************************************************************************/ 584 typedef uint8_t* cy_ethif_buffpool_t[CY_ETH_DEFINE_TOTAL_BD_PER_RXQUEUE]; 585 586 /** 587 ***************************************************************************** 588 ** \brief Ethernet MAC call back handlers 589 *****************************************************************************/ 590 typedef struct 591 { 592 cy_ethif_tx_msg_cb_t txcompletecb; /**< Transmit complete */ 593 cy_ethif_tx_error_cb_t txerrorcb; /**< Tx Error */ 594 cy_ethif_rx_frame_cb_t rxframecb; /**< Frame Received */ 595 cy_ethif_tsu_inc_cb_t tsuSecondInccb; /**< TSU timer Second counter incremented */ 596 cy_ethif_rx_getbuffer_cb_t rxgetbuff; /**< Get buffer for Receive Frame */ 597 } cy_stc_ethif_cb_t; 598 599 600 601 /** 602 ***************************************************************************** 603 ** \brief Ethernet MAC detailed configurations 604 *****************************************************************************/ 605 typedef struct 606 { 607 bool bintrEnable; /**< interrupts/events to enable on start */ 608 cy_en_ethif_dma_data_buffer_len_t dmaDataBurstLen; /**< fixed burst length for DMA data transfers */ 609 /**< bit4:0 amba_burst_length */ 610 /**< 1xxxx: attempt use burst up to 16 (CY_ETHIF_DMA_DBUR_LEN_16) */ 611 /**< 01xxx: attempt use burst up to 8 (CY_ETHIF_DMA_DBUR_LEN_8) */ 612 /**< 001xx: attempt use burst up to 4 (CY_ETHIF_DMA_DBUR_LEN_4) */ 613 /**< 0001x: always use single burst */ 614 /**< 00001: always use single burst (CY_ETHIF_AMBD_BURST_LEN_1) */ 615 /**< 00000: best AXI burst up to 256 beats */ 616 uint8_t u8dmaCfgFlags; /**< DMA config register bits 24, 25 & 26. */ 617 /**< OR the following bit-flags to set corresponding bits - */ 618 /**< CY_ETHIF_CFG_DMA_DISC_RXP, */ 619 /**< CY_ETHIF_CFG_DMA_FRCE_RX_BRST, */ 620 /**< CY_ETHIF_CFG_DMA_FRCE_TX_BRST */ 621 cy_en_ethif_dma_mdc_clk_div_t mdcPclkDiv; /**< divisor to generate MDC from pclk */ 622 /**< CY_ETHIF_MDC_DIV_BY_8 = 0 */ 623 /**< CY_ETHIF_MDC_DIV_BY_16 = 1 */ 624 /**< CY_ETHIF_MDC_DIV_BY_32 = 2 */ 625 /**< CY_ETHIF_MDC_DIV_BY_48 = 3 */ 626 /**< CY_ETHIF_MDC_DIV_BY_64 = 4 */ 627 /**< CY_ETHIF_MDC_DIV_BY_96 = 5 */ 628 /**< CY_ETHIF_MDC_DIV_BY_128 = 6 */ 629 /**< CY_ETHIF_MDC_DIV_BY_224 = 7 */ 630 uint8_t u8rxLenErrDisc; /**< enable discard of frames with length field error */ 631 uint8_t u8disCopyPause; /**< disable copying Rx pause frames to memory */ 632 uint8_t u8chkSumOffEn; /**< enable checksum offload operation */ 633 uint8_t u8rx1536ByteEn; /**< enable Rx of frames up to 1536 bytes */ 634 uint8_t u8rxJumboFrEn; /**< enable Rx of jumbo frames */ 635 uint8_t u8enRxBadPreamble; /**< enable Rx frames with non-standard preamble */ 636 uint8_t u8ignoreIpgRxEr; /**< ignore IPG rx_er (NetCfg b30) */ 637 uint8_t u8storeUdpTcpOffset; /**< u8storeUdpTcpOffset */ 638 uint8_t u8aw2wMaxPipeline; /**< Maximum number of outstanding AXI write requests, 639 * that can be issued by DMA via the AW channel. 640 * Must not be = 0 if using AXI as this would disable writes 641 */ 642 uint8_t u8ar2rMaxPipeline; /**< Maximum number of outstanding AXI read requests, 643 * that can be issued by DMA via the AR channel. 644 * Must not be = 0 if using AXI as this would disable reads 645 */ 646 uint8_t u8pfcMultiQuantum; /**< enable pfc multiple quantum (8 different priorities) */ 647 cy_stc_ethif_wrapper_config_t * pstcWrapperConfig; /**< Configuration for Wrapper */ 648 cy_stc_ethif_tsu_config_t * pstcTSUConfig; /**< Configuration for TSU */ 649 bool btxq0enable; /**< Tx Q0 Enable */ 650 bool btxq1enable; /**< Tx Q1 Enable */ 651 bool btxq2enable; /**< Tx Q2 Enable */ 652 bool brxq0enable; /**< Rx Q0 Enable */ 653 bool brxq1enable; /**< Rx Q1 Enable */ 654 bool brxq2enable; /**< Rx Q2 Enable */ 655 cy_ethif_buffpool_t *pRxQbuffPool[CY_ETH_DEFINE_NUM_RXQS]; /**< Rx Queues buffer pool 32 bytes aligned */ 656 } cy_stc_ethif_mac_config_t; 657 658 659 /** 660 ****************************************************************************** 661 ** \brief Interrupt configuration for Ethernet MAC 662 ******************************************************************************/ 663 typedef struct 664 { 665 bool btsu_time_match; /**< Time stamp unit time match event */ 666 bool bwol_rx; /**< Wake on LAN event received */ 667 bool blpi_ch_rx; /**< LPI indication status bit change received */ /* TODO: LPI, wait for conclusion? */ 668 bool btsu_sec_inc; /**< TSU seconds register increment */ 669 bool bptp_tx_pdly_rsp; /**< PTP pdelay_resp frame transmitted */ 670 bool bptp_tx_pdly_req ; /**< PTP pdelay_req frame transmitted */ 671 bool bptp_rx_pdly_rsp; /**< PTP pdelay_resp frame received */ 672 bool bptp_rx_pdly_req; /**< PTP pdelay_req frame received */ 673 bool bptp_tx_sync; /**< PTP sync frame transmitted */ 674 bool bptp_tx_dly_req; /**< PTP delay_req frame transmitted */ 675 bool bptp_rx_sync; /**< PTP sync frame received */ 676 bool bptp_rx_dly_req; /**< PTP delay_req frame received */ 677 // bool bpcs_lp_page_rx; /** PCS auto-negotiation link partner page received */ 678 // bool bpcs_an_complete; /** PCS auto-negotiation has completed */ 679 bool bext_intr; /**< External input interrupt detected */ 680 bool bpause_frame_tx; /**< Pause frame transmitted */ 681 bool bpause_time_zero; /**< Pause time reaches zero or zeroq pause frame received */ 682 bool bpause_nz_qu_rx; /**< Pause frame with non-zero quantum received */ 683 bool bhresp_not_ok; /**< DMA hresp not OK */ 684 bool brx_overrun; /**< Rx overrun error */ 685 bool bpcs_link_change_det; /**< Link status change detected by PCS */ /* TODO: PCS, wait for conclusion */ 686 bool btx_complete; /**< Frame has been transmitted successfully */ 687 bool btx_fr_corrupt; /**< Tx frame corruption */ 688 bool btx_retry_ex_late_coll; /**< Retry limit exceeded or late collision */ 689 bool btx_underrun; /**< Tx underrun */ 690 bool btx_used_read; /**< Used bit set has been read in Tx descriptor list */ 691 bool brx_used_read; /**< Used bit set has been read in Rx descriptor list */ 692 bool brx_complete; /**< Frame received successfully and stored */ 693 bool bman_frame; /**< Management Frame Sent */ 694 } cy_stc_ethif_intr_config_t; 695 696 697 /** 698 ****************************************************************************** 699 ** \brief Ethernet MAC Address 700 ******************************************************************************/ 701 typedef struct 702 { 703 uint8_t byte[6]; /**< 6 bytes MAC Address */ 704 } cy_stc_ethif_mac_address_t; 705 706 707 /** 708 ****************************************************************************** 709 ** \brief filter configuration for Ethernet MAC 710 ******************************************************************************/ 711 typedef struct 712 { 713 cy_en_ethif_filter_type_t typeFilter; /**< typeFilter */ 714 cy_stc_ethif_mac_address_t filterAddr; /**< filterAddr */ 715 uint8_t ignoreBytes; /**< e.g. ignoreBytes = 0x01 implies first byte received should not be compared. 716 * e.g. ignoreBytes = 0x03 implies first and second byte received should not be compared. */ 717 } cy_stc_ethif_filter_config_t; 718 719 720 /** \} group_ethif_data_structures */ 721 722 723 /** \} group_ethif_data_structures */ 724 725 /*************************************** 726 * Function Prototypes 727 ***************************************/ 728 /** 729 * \addtogroup group_ethif_functions 730 * \{ 731 */ 732 733 cy_en_ethif_status_t Cy_ETHIF_MdioInit(ETH_Type *base, cy_stc_ethif_mac_config_t * pstcEthIfConfig); 734 cy_en_ethif_status_t Cy_ETHIF_Init(ETH_Type *base, cy_stc_ethif_mac_config_t *pstcEthIfConfig, cy_stc_ethif_intr_config_t *pstcInterruptList); 735 void Cy_ETHIF_RegisterCallbacks(ETH_Type *base, cy_stc_ethif_cb_t *cbFuncsList); 736 void Cy_ETHIF_DecodeEvent(ETH_Type *base); 737 cy_en_ethif_status_t Cy_ETHIF_TransmitFrame(ETH_Type *base, uint8_t * pu8TxBuffer, uint16_t u16Length, uint8_t u8QueueIndex, bool bEndBuffer); 738 cy_en_ethif_status_t Cy_ETHIF_Get1588TimerValue(ETH_Type *base, cy_stc_ethif_1588_timer_val_t *stcRetTmrValue); 739 cy_en_ethif_status_t Cy_ETHIF_Set1588TimerValue(ETH_Type *base, cy_stc_ethif_1588_timer_val_t * pstcTmrValue); 740 cy_en_ethif_status_t Cy_ETHIF_TxPauseFrame(ETH_Type *base, bool bZeroTQ); 741 cy_en_ethif_status_t Cy_ETHIF_ConfigPause(ETH_Type *base, uint16_t u16PauseQuanta); 742 cy_en_ethif_status_t Cy_ETHIF_PhyRegWrite(ETH_Type *base, uint8_t u8RegNo, uint16_t u16Data, uint8_t u8PHYAddr); 743 uint32_t Cy_ETHIF_PhyRegRead(ETH_Type *base, uint8_t u8RegNo, uint8_t u8PHYAddr); 744 cy_en_ethif_status_t Cy_ETHIF_SetFilterAddress(ETH_Type *base, cy_en_ethif_filter_num_t filterNo, const cy_stc_ethif_filter_config_t* config); 745 void Cy_ETHIF_SetPromiscuousMode(ETH_Type *base, bool toBeEnabled); 746 void Cy_ETHIF_SetNoBroadCast(ETH_Type *base, bool rejectBC); 747 void Cy_ETHIF_DiscardNonVLANFrames(ETH_Type *base, bool enable); 748 749 /** \} group_ethif_functions */ 750 751 #if defined(__cplusplus) 752 } 753 #endif 754 755 #endif /* CY_IP_MXETH */ 756 757 #endif /* CY_ETHIF_H */ 758 759 /** \} group_eth */ 760 761 /* [] END OF FILE */ 762
