1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file i2c.cypersonality 6* \version 4.0 7* 8* \brief 9* I2C personality description file. It Supports CAT1A, CAT1B and CAT1C family of devices. 10* 11******************************************************************************** 12* \copyright 13* Copyright 2022 Cypress Semiconductor Corporation 14* SPDX-License-Identifier: Apache-2.0 15* 16* Licensed under the Apache License, Version 2.0 (the "License"); 17* you may not use this file except in compliance with the License. 18* You may obtain a copy of the License at 19* 20* http://www.apache.org/licenses/LICENSE-2.0 21* 22* Unless required by applicable law or agreed to in writing, software 23* distributed under the License is distributed on an "AS IS" BASIS, 24* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25* See the License for the specific language governing permissions and 26* limitations under the License. 27*****************************************************************************--> 28 29<Personality id="i2c" name="I2C" version="4.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v8"> 30 <Dependencies> 31 <IpBlock name="mxscb,mxscb_ver2_s40e,mxs22scb"> 32 <Version major="1"/> 33 <Version major="2" /> 34 <Version major="4" /> 35 <Param name="I2C" value="1" /> 36 </IpBlock> 37 <Resource name="scb" /> 38 <OperatingMode value="MCU"/> 39 </Dependencies> 40 <ExposedMembers /> 41 <Parameters> 42 <!-- PDL documentation --> 43 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__scb__i2c.html" linkText="Open I2C (SCB) Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 44 45 <ParamBool id="DeepSleepCapable" name="DeepSleepCapable" group="Internal" default="`${DEEPSLEEP eq 1}`" visible="false" editable="false" desc="This parameter specifies if SCB block can wakeup from Deep Sleep." /> 46 <ParamBool id="SlaveCapable" name="SlaveCapable" group="Internal" default="`${I2C_S eq 1}`" visible="false" editable="false" desc="This parameter specifies if SCB block supports Slave mode." /> 47 <ParamBool id="MasterCapable" name="MasterCapable" group="Internal" default="`${I2C_M eq 1}`" visible="false" editable="false" desc="This parameter specifies if SCB block supports Master mode." /> 48 <ParamBool id="MasterSlaveCapable" name="MasterCapable" group="Internal" default="`${I2C_M_S eq 1}`" visible="false" editable="false" desc="This parameter specifies if SCB block supports Master-Slave mode." /> 49 50 <!-- General --> 51 <ParamChoice id="ModeUser" name="Mode" group="General" default="`${SlaveCapable ? "CY_SCB_I2C_SLAVE" : MasterCapable ? "CY_SCB_I2C_MASTER" : "CY_SCB_I2C_MASTER_SLAVE"}`" visible="true" editable="`${SlaveCapable ? (MasterCapable || MasterSlaveCapable) : MasterCapable ? (SlaveCapable || MasterSlaveCapable) : false}`" desc="This parameter defines the I2C operation mode as: the slave, master or master-slave."> 52 <Entry name="Slave" value="CY_SCB_I2C_SLAVE" visible="`${SlaveCapable}`" /> 53 <Entry name="Master" value="CY_SCB_I2C_MASTER" visible="`${MasterCapable}`" /> 54 <Entry name="Master-Slave" value="CY_SCB_I2C_MASTER_SLAVE" visible="`${MasterSlaveCapable}`" /> 55 </ParamChoice> 56 57 <ParamBool id="Slave" name="Slave" group="Internal" default="`${ModeUser eq CY_SCB_I2C_SLAVE}`" visible="false" editable="false" desc="Enables Slave functionality." /> 58 <ParamBool id="Master" name="Master" group="Internal" default="`${ModeUser eq CY_SCB_I2C_MASTER}`" visible="false" editable="false" desc="Enables Master functionality." /> 59 <ParamBool id="MasterSlave" name="Master-Slave" group="Internal" default="`${ModeUser eq CY_SCB_I2C_MASTER_SLAVE}`" visible="false" editable="false" desc="Enables Master-Slave functionality." /> 60 61 <ParamBool id="ManualDataRateCtrl" name="Manual Data Rate Control" group="General" default="false" visible="`${Master}`" editable="true" desc="This parameter enables the user to configure data rate related parameters for the master modes." /> 62 <ParamBool id="ManualDataRate" name="ManualDataRate" group="Internal" default="`${Master && ManualDataRateCtrl}`" visible="false" editable="false" desc="This parameter enables the user to configure data rate related parameters for the master modes." /> 63 64 <ParamBool id="ManualDigitalFilter" name="Enable Digital Filter" group="Manual DataRate Control" default="true" visible="`${ManualDataRate}`" editable="true" desc="This parameter enables digital (3-tap median) filter on I2C input lines. An analog filter is disabled when digital filter is enabled and vice versa." /> 65 <ParamRange id="ManualLowPhaseDutyCycle" name="SCL Low Phase (SCB Clocks)" group="Manual DataRate Control" default="16" min="1" max="16" resolution="1" visible="`${ManualDataRate}`" editable="true" desc="This parameter defines how many SCB clocks are used to generate the SCL low phase (only applicable for the master modes)." /> 66 <ParamRange id="ManualHighPhaseDutyCycle" name="SCL High Phase (SCB Clocks)" group="Manual DataRate Control" default="9" min="1" max="16" resolution="1" visible="`${ManualDataRate}`" editable="true" desc="This parameter defines how many SCB clocks are used to generate the SCL high phase (only applicable for the master modes)." /> 67 68 <ParamRange id="DataRate" name="Data Rate (kbps)" group="General" default="100" min="1" max="1000" resolution="1" visible="`${!ManualDataRate}`" editable="true" desc="Data rate that I2C operates. Maximum data rate is 1000 kbps." /> 69 70 <ParamBool id="EnableTxFifo" name="Use TX FIFO" group="General" default="true" visible="true" editable="true" desc="This parameter defines if the TX FIFO capabilities are used. Usage of the TX FIFO reduces the possibility of clock stretching and interrupt overhead." /> 71 72 <ParamBool id="AcceptAddress" name="Accept Matching Address in RX FIFO" group="General" default="false" visible="`${Slave}`" editable="true" desc="This parameter determines whether to accept the match slave address in the RX FIFO or not. This feature is useful when more than one address support is required. The user has to register the callback function to handle the accepted addresses." /> 73 <ParamBool id="IsEnableRxFifoVisible" name="Is Enable Rx Fifo Visible" group="Internal" default="`${(ModeUser eq CY_SCB_I2C_MASTER) || (ModeUser eq CY_SCB_I2C_MASTER_SLAVE) || !AcceptAddress}`" visible="false" editable="false" desc="This parameter specifies the visibility of EnableRxFifo parameter." /> 74 <ParamBool id="EnableRxFifo" name="Use RX FIFO" group="General" default="true" visible="`${IsEnableRxFifoVisible}`" editable="true" desc="This parameter defines if the RX FIFO capabilities are used. Usage of the RX FIFO reduces the possibility of clock stretching and interrupt overhead." /> 75 76 <ParamBool id="EnableWakeup" name="Enable Wakeup from Deep Sleep Mode" group="General" default="false" visible="`${DeepSleepCapable}`" editable="true" desc="This parameter enables the I2C to wake the system from Deep-Sleep when a slave address match occurs (only applicable for the slave mode)." /> 77 78 <!-- Slave --> 79 <ParamRange id="SlaveAddress" name="Slave Address (7-bit)" group="Slave" default="8" min="8" max="120" resolution="1" visible="`${(Slave) || (MasterSlave)}`" editable="true" desc="This parameter specifies the 7-bit right justified slave address. 80 The range: 0x08-0x78." /> 81 <ParamRange id="SlaveAddressMask" name="Slave Address Mask (8-bit)" group="Slave" default="254" min="0" max="255" resolution="1" visible="`${(Slave) || (MasterSlave)}`" editable="true" desc="This parameter specifies the slave address mask. The range: 0x00-0xFE. 82 - Bit value 0 – excludes the bit from the address comparison. 83 - Bit value 1 – the bit needs to match with the corresponding bit of the I2C slave address." /> 84 85 <ParamBool id="AcceptGeneralCall" name="Accept General Call Address" group="Slave" default="false" visible="`${(Slave) || (MasterSlave)}`" editable="true" desc="This parameter specifies whether to accept the general call address. The general call address is ACKed when accepted and NAKed otherwise (default). The user has to register the callback function to handle the general call address." /> 86 87 <!-- SCB I2C clock constraints --> 88 <ParamString id="ScbClkMinMHz" name="ScbClkMinMHz" group="Internal" default="`${(DataRate <= 100) ? 1.55 : ((DataRate > 100) && (DataRate <= 400)) ? 7.82 : (Master ? 14.32 : 15.84)}`" visible="false" editable="false" desc="Minimum clock frequency to operate with desired data rate." /> 89 <ParamString id="ScbClkMaxMHz" name="ScbClkMaxMHz" group="Internal" default="`${Master ? ((DataRate <= 100) ? 3.2 : ((DataRate > 100) && (DataRate <= 400)) ? 10.0 : 25.8) : ((DataRate <= 100) ? 12.8 : ((DataRate > 100) && (DataRate <= 400)) ? 15.38 : 89.0)}`" visible="false" editable="false" desc="Maximum clock frequency to operate with desired data rate." /> 90 91 <!-- Connections --> 92 <ParamSignal port="clock[0]" name="Clock" group="Connections" visible="`${hasVisibleOption("clock[0]")}`" desc="Clock that operates this block." canBeEmpty="false" > 93 <Constraint type="REQUIRE" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_.*" valid="`${!ManualDataRate}`" > 94 <Parameter id="intDivider" severity="ERROR" reason="The clock frequency must be within the range `${ScbClkMinMHz}` - `${ScbClkMaxMHz}` MHz to operate with Data Rate `${DataRate}` kbps." valid="`${!ManualDataRate}`"> 95 <Range 96 min="`${ceil(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / (ScbClkMaxMHz * 1000000))}`" 97 max="`${floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / (ScbClkMinMHz * 1000000))}`" /> 98 </Parameter> 99 </Constraint> 100 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_(16.5|24.5).*" valid="true" > 101 <Parameter id="fracDivider" severity="ERROR" reason="Fractional divider must be 0 for I2C interface."> 102 <Fixed value= "0" /> 103 </Parameter> 104 </Constraint> 105 <Constraint type="ACCEPT" targetLocation=".*" valid="`${ManualDataRate}`" /> 106 </ParamSignal> 107 108 <ParamSignal port="clock_scb_en[0]" name="Clock" group="Connections" visible="`${hasVisibleOption("clock_scb_en[0]")}`" desc="Clock that operates this block." canBeEmpty="false" > 109 <Constraint type="REQUIRE" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_.*" valid="`${!ManualDataRate}`" > 110 <Parameter id="intDivider" severity="ERROR" reason="The clock frequency must be within the range `${ScbClkMinMHz}` - `${ScbClkMaxMHz}` MHz to operate with Data Rate `${DataRate}` kbps." valid="`${!ManualDataRate}`"> 111 <Range 112 min="`${ceil(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / (ScbClkMaxMHz * 1000000))}`" 113 max="`${floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / (ScbClkMinMHz * 1000000))}`" /> 114 </Parameter> 115 </Constraint> 116 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_(16.5|24.5).*" valid="true" > 117 <Parameter id="fracDivider" severity="ERROR" reason="Fractional divider must be 0 for I2C interface."> 118 <Fixed value= "0" /> 119 </Parameter> 120 </Constraint> 121 <Constraint type="ACCEPT" targetLocation=".*" valid="`${ManualDataRate}`" /> 122 </ParamSignal> 123 124 <ParamSignal port="i2c_scl[0]" name="SCL" group="Connections" visible="true" desc="Serial clock (SCL) is the master-generated I2C clock." canBeEmpty="false"> 125 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 126 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 127 <Fixed value="CY_GPIO_DM_OD_DRIVESLOW" /> 128 </Parameter> 129 </Constraint> 130 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 131 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 132 <Fixed value="CY_GPIO_DM_OD_DRIVESLOW" /> 133 </Parameter> 134 </Constraint> 135 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 136 </ParamSignal> 137 <ParamSignal port="i2c_sda[0]" name="SDA" group="Connections" visible="true" desc="Serial data (SDA) is the I2C data signal." canBeEmpty="false"> 138 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 139 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 140 <Fixed value="CY_GPIO_DM_OD_DRIVESLOW" /> 141 </Parameter> 142 </Constraint> 143 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 144 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 145 <Fixed value="CY_GPIO_DM_OD_DRIVESLOW" /> 146 </Parameter> 147 </Constraint> 148 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 149 </ParamSignal> 150 <ParamSignal port="tr_i2c_scl_filtered[0]" name="SCL Output (scl_trig)" group="Connections" visible="true" desc="This output allows monitoring of the SCL state. The connection capabilities are limited by the trigger mux. The typical connection is to TCPWM, which can be used to monitor the SCL low timeout." canBeEmpty="true" > 151 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 152 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 153 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 154 </Parameter> 155 </Constraint> 156 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 157 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 158 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 159 </Parameter> 160 </Constraint> 161 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 162 </ParamSignal> 163 <ParamSignal port="tr_rx_req[0]" name="RX Trigger Output" group="Connections" visible="true" desc="Connects SCB RX trigger output to the DMA. Configure RX FIFO Level to define this output behavior." canBeEmpty="true" > 164 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 165 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 166 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 167 </Parameter> 168 </Constraint> 169 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 170 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 171 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 172 </Parameter> 173 </Constraint> 174 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 175 </ParamSignal> 176 <ParamSignal port="tr_tx_req[0]" name="TX Trigger Output" group="Connections" visible="true" desc="Connects SCB TX trigger output to the DMA. Configure TX FIFO Level to define this output behavior." canBeEmpty="true" > 177 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 178 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 179 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 180 </Parameter> 181 </Constraint> 182 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 183 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 184 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 185 </Parameter> 186 </Constraint> 187 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 188 </ParamSignal> 189 190 <!-- Clock Frequency --> 191 <ParamString id="sourceClock" name="sourceClock" group="Internal" default="`${(hasVisibleOption("clock[0]")) ? (getBlockFromSignal("clock[0]")) : (getBlockFromSignal("clock_scb_en[0]"))}`" visible="false" editable="false" desc="Source Clock Resource" /> 192 <ParamRange id="scbClkHz" name="scbClkHz" group="Internal" default="`${getExposedMember(sourceClock, "frequency")}`" min="1" max="200000000" resolution="1" visible="false" editable="false" desc="SCB clock frequency in kHz" /> 193 194 <!-- I2C Master Duty Cycle constrains --> 195 <ParamString id="i2c_solver" name="i2c_solver" group="Internal" default="`${runTcl("i2c_solver-2.0.tcl", Master ? "Master" : "Slave", DataRate * 1000, scbClkHz)}`" visible="false" editable="false" desc="I2C master data rate configurator." /> 196 <ParamBool id="AutoDigitalFilter" name="Digital Filter" group="Internal" default="`${getTclVar("digitalFilter", i2c_solver)}`" visible="false" editable="false" desc="This parameter specifies to enable digital (3-tap median) fitler. An analog filter is disabled when digital filter is enabled. It is calculated by i2c_solver." /> 197 <ParamRange id="AutoLowPhaseDutyCycle" name="SCL Low Phase (SCB Clocks)" group="Internal" default="`${getTclVar("lowOversample", i2c_solver)}`" min="0" max="16" resolution="1" visible="false" editable="false" desc="This parameter defines how many SCB clocks are used to generate the SCL low phase (only applicable for the master modes). It is calculated by i2c_solver." /> 198 <ParamRange id="AutoHighPhaseDutyCycle" name="SCL High Phase (SCB Clocks)" group="Internal" default="`${getTclVar("highOversample", i2c_solver)}`" min="0" max="16" resolution="1" visible="false" editable="false" desc="This parameter defines how many SCB clocks are used to generate the SCL high phase (only applicable for the master modes). It is calculated by i2c_solver." /> 199 200 <ParamBool id="DigitalFilter" name="Digital Filter" group="Internal" default="`${ManualDataRate ? ManualDigitalFilter : AutoDigitalFilter}`" visible="false" editable="false" desc="This parameter specifies to enable digital (3-tap median) fitler. An analog filter is disabled when digital filter is enabled." /> 201 <ParamRange id="LowPhaseDutyCycle" name="SCL Low Phase (SCB Clocks)" group="Internal" default="`${ManualDataRate ? ManualLowPhaseDutyCycle : AutoLowPhaseDutyCycle}`" min="0" max="16" resolution="1" visible="false" editable="false" desc="This parameter defines how many SCB clocks are used to generate the SCL low phase (only applicable for the master modes)." /> 202 <ParamRange id="HighPhaseDutyCycle" name="SCL High Phase (SCB Clocks)" group="Internal" default="`${ManualDataRate ? ManualHighPhaseDutyCycle : AutoHighPhaseDutyCycle}`" min="0" max="16" resolution="1" visible="false" editable="false" desc="This parameter defines how many SCB clocks are used to generate the SCL high phase (only applicable for the master modes)." /> 203 204 <!-- Actual Data Rate --> 205 <ParamRange id="actualDataRate" name="Actual Data Rate (kbps)" group="Actual Data Rate" default="`${Master ? (scbClkHz / ((LowPhaseDutyCycle + HighPhaseDutyCycle) * 1000)) : (((DataRate < 100) || (DataRate eq 100)) ? 100 : ((DataRate > 100) && (DataRate < 400) || (DataRate eq 400)) ? 400 : 1000)}`" min="0" max="10000" resolution="1" visible="true" editable="false" desc="The actual data rate displays the data rate at which the I2C operates with current settings. For the master modes actual data rate does not take into account the I2C bus characteristics and may differ from the observed on the bus. If this is the case enable Manual Data Rate Control to configure/adjust data rate related parameters. Refer to the section I2C sub-section Oversampling and Bit Rate in the selected device TRM for more information." /> 206 <ParamRange id="sclLow" name="tLow (ns)" group="Actual Data Rate" default="`${((1000000000.0 / scbClkHz) * LowPhaseDutyCycle)}`" min="0" max="4294967295" resolution="1" visible="`${(Master) || (MasterSlave)}`" editable="false" desc="tLow parameter (the LOW period of the SCL clock, including falling edge)." /> 207 <ParamRange id="sclHigh" name="tHigh (ns)" group="Actual Data Rate" default="`${((1000000000.0 / scbClkHz) * HighPhaseDutyCycle)}`" min="0" max="4294967295" resolution="1" visible="`${(Master) || (MasterSlave)}`" editable="false" desc="tHigh parameter (the HIGH period of the SCL clock, including raising edge). tHigh value might be less than observed on the bus due to clock synchronization in the device. The device resets its internal counter of tHigh when it detects a low level on SCL line while expecting high level." /> 208 209 <ParamString id="ClkFreq" name="Clock Frequency" group="Actual Data Rate" default="`${(scbClkHz < 1000000) ? (scbClkHz / 1000.0) . " kHz" : (scbClkHz / 1000000.0) . " MHz"}`" visible="true" editable="false" desc="Frequency of the connected clock" /> 210 211 <!-- Advanced--> 212 <ParamBool id="inFlash" name="Store Config in Flash" group="Advanced" default="true" visible="true" editable="true" desc="Controls whether the configuration structure is stored in flash (const, true) or SRAM (not const, false)." /> 213 214 <!-- SCB instance number --> 215 <ParamString id="InstNumber" name="InstNumber" group="Internal" default="`${getInstNumber("scb")}`" visible="false" editable="false" desc="SCB Instance name number." /> 216 <ParamString id="version" name="version number" group="Internal" default="`${getVersion()}`" visible="false" editable="false" desc="" /> 217 <ParamString id="ipName" name="IP name" group="Internal" default="`${getIpBlockName()}`" visible="false" editable="false" desc="" /> 218 219 <!-- Peripheral clock divider connection --> 220 <ParamBool id="pclkOk" name="PCLK Valid" group="Internal" default="`${(hasVisibleOption("clock[0]")) ? (hasConnection("clock", 0) && isBlockUsed(sourceClock)) : (hasConnection("clock_scb_en", 0) && isBlockUsed(sourceClock)) }`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." /> 221 222 <ParamString id="pclkSCBClockString" name="PCLK Destination Clock" group="Internal" default="PCLK_SCB`${InstNumber}`_CLOCK" visible="false" editable="false" desc="String variable used for PCLK_SCB_CLOCK." /> 223 <ParamString id="pclkSCBClockSCBENString" name="PCLK Destination Clock" group="Internal" default="PCLK_SCB`${InstNumber}`_CLOCK_SCB_EN" visible="false" editable="false" desc="String variable used only for PCLK_SCB_CLOCK_SCB_EN." /> 224 225 <ParamString id="pclkDst" name="PCLK Destination" group="Internal" default="`${(hasVisibleOption("clock[0]")) ? pclkSCBClockString : pclkSCBClockSCBENString }`" visible="false" editable="false" desc="Generates PCLK connection define." /> 226 227 <ParamRange id="pclkDividerValue" name="Peripheral Clock Divider" group="Internal" default="`${getExposedMember(sourceClock, "divider")}`" min="0" max="`${pow(2, 24)}`" resolution="1.000" 228 visible="false" editable="false" desc="Connected peripheral clock divider value(PCLK)" /> 229 <ParamRange id="reqPCLKDiv" name="Required Divider value" group="Internal" default="`${((scbClkHz * pclkDividerValue) / (DataRate * 1000 * 32))}`" min="0" max="`${pow(2, 24)}`" resolution="1.000" 230 visible="false" editable="false" desc="Required peripheral clock divider value(PCLK)" /> 231 <ParamRange id="reqClk" name="Required Clock Frequency" group="Internal" default="`${((scbClkHz * pclkDividerValue) / (reqPCLKDiv))}`" min="0" max="200000000" resolution="1" 232 visible="false" editable="false" desc="Required SCB clock frequency to operate with desired data rate." /> 233 <ParamBool id="isReqClkPossible" name="Possibility Check" group="Internal" default="`${(DataRate <= 100) ? ((reqClk > 1550000) ? true : false) : ((DataRate > 100) && (DataRate <= 400)) ? ((reqClk > 7820000) ? true : false) : (Master ? ((reqClk > 14320000) ? true : false) : ((reqClk > 15840000) ? true : false))}`" 234 visible="false" editable="false" desc="To check if the required clock frequency is above the minimum clock frequency to operate with the desired data rate." /> 235 236 </Parameters> 237 238 <DRCs> 239 <!--SlaveAddressMask DRCs--> 240 <DRC type="ERROR" paramId="SlaveAddressMask" text="The I2C slave address mask must be even." condition="`${(SlaveAddressMask % 2) ne 0}`" /> 241 <DRC type="ERROR" paramId="clock[0]" text="The actual data rate `${actualDataRate}` kpbs is greater than desired `${DataRate}` kpbs. Increase clock divider to produce lower clock frequency or adjust desired Data Rate." condition="`${Master ? (!ManualDataRate && (actualDataRate > DataRate) && (isReqClkPossible) && (hasVisibleOption("clock[0]"))) : false}`" > 242 <FixIt action="SET_PARAM" target="`${getBlockFromSignalValue(getParamValue("clock[0]")).".intDivider"}`" value="`${reqPCLKDiv}`" valid="`${isReqClkPossible}`" /> 243 </DRC> 244 <DRC type="ERROR" paramId="clock_scb_en[0]" text="The actual data rate `${actualDataRate}` kpbs is greater than desired `${DataRate}` kpbs. Increase clock divider to produce lower clock frequency or adjust desired Data Rate." condition="`${Master ? (!ManualDataRate && (actualDataRate > DataRate) && (isReqClkPossible) && (hasVisibleOption("clock_scb_en[0]"))) : false}`" > 245 <FixIt action="SET_PARAM" target="`${getBlockFromSignalValue(getParamValue("clock_scb_en[0]")).".intDivider"}`" value="`${reqPCLKDiv}`" valid="`${isReqClkPossible}`" /> 246 </DRC> 247 <DRC type="ERROR" paramId="clock[0]" text="The desired data rate cannot be supported with the current Source Clock" condition="`${Master ? (!ManualDataRate && (actualDataRate > DataRate) && !(isReqClkPossible) && (hasVisibleOption("clock[0]"))) : false}`" /> 248 <DRC type="ERROR" paramId="clock_scb_en[0]" text="The desired data rate cannot be supported with the current Source Clock" condition="`${Master ? (!ManualDataRate && (actualDataRate > DataRate) && !(isReqClkPossible) && (hasVisibleOption("clock_scb_en[0]"))) : false}`" /> 249 250 <!--High/Low phase oversampling factor DRCs--> 251 <DRC type="INFO" condition="`${((ModeUser ne CY_SCB_I2C_SLAVE) && ("mxscb" eq getIpBlockName()) && (ManualDigitalFilter eq true))}`" text="Note a possible shift of the actual data rate on the I2C bus. The high phase of the SCL will be extended by: an output wire delay from SCB to I/O pin, an I2C bus tR delay, and an input wire delay (filters and synchronization). This can be avoided by: decreasing the pull-up resistor or decreasing the bus capacitance to reduce tR; reducing the 'SCL High Phase (SCB Clocks)' value." /> 252 </DRCs> 253 254 <ConfigFirmware> 255 <ConfigInclude value="cy_scb_i2c.h" include="true" /> 256 <ConfigInclude value="cy_sysclk.h" include="`${pclkOk}`" /> 257 <ConfigInclude value="cyhal_hwmgr.h" include="true" guard="defined (CY_USING_HAL)" /> 258 <ConfigInclude value="cyhal.h" include="true" guard="defined (CY_USING_HAL)" /> 259 <ConfigInclude value="cyhal_hw_types.h" include="true" guard="defined (CY_USING_HAL_LITE)" /> 260 <ConfigInclude value="cycfg_clocks.h" include="true" guard="defined (CY_USING_HAL_LITE) || defined (CY_USING_HAL)" /> 261 262 <ConfigDefine name="`${INST_NAME}`_HW" value="SCB`${InstNumber}`" public="true" include="true" /> 263 <ConfigDefine name="`${INST_NAME}`_IRQ" value="scb_`${InstNumber}`_interrupt_IRQn" public="true" include="true" /> 264 <ConfigStruct name="`${INST_NAME}`_config" type="cy_stc_scb_i2c_config_t" const="`${inFlash}`" public="true" include="true" > 265 <Member name="i2cMode" value="`${ModeUser}`" /> 266 <Member name="useRxFifo" value="`${IsEnableRxFifoVisible ? (EnableRxFifo ? "true" : "false") : "false"}`" /> 267 <Member name="useTxFifo" value="`${EnableTxFifo ? "true" : "false"}`" /> 268 <Member name="slaveAddress" value="`${Master ? "0U" : SlaveAddress}`" /> 269 <Member name="slaveAddressMask" value="`${Master ? "0U" : SlaveAddressMask}`" /> 270 <Member name="acceptAddrInFifo" value="`${Slave ? (AcceptAddress ? "true" : "false") : "false"}`" /> 271 <Member name="ackGeneralAddr" value="`${Slave ? (AcceptGeneralCall ? "true" : "false") : "false"}`" /> 272 <Member name="enableWakeFromSleep" value="`${EnableWakeup}`" /> 273 <Member name="enableDigitalFilter" value="`${DigitalFilter ? "true" : "false"}`" /> 274 <Member name="lowPhaseDutyCycle" value="`${LowPhaseDutyCycle}`" /> 275 <Member name="highPhaseDutyCycle" value="`${HighPhaseDutyCycle}`" /> 276 </ConfigStruct> 277 278 <ConfigStruct name="`${INST_NAME}`_obj" type="cyhal_resource_inst_t" const="true" public="true" include="true" guard="defined (CY_USING_HAL) || defined(CY_USING_HAL_LITE)"> 279 <Member name="type" value="CYHAL_RSC_SCB" /> 280 <Member name="block_num" value="`${getInstNumber("scb")}`U" /> 281 <Member name="channel_num" value="0U" /> 282 </ConfigStruct> 283 284 <ConfigStruct name="`${INST_NAME}`_clock" type="cyhal_clock_t" const="`${inFlash}`" public="true" include="true" guard="defined(CY_USING_HAL_LITE) || defined (CY_USING_HAL)"> 285 <Member name="block" value="`${getExposedMember(sourceClock, "hal_block")}`" /> 286 <Member name="channel" value="`${getExposedMember(sourceClock, "number")}`" /> 287 <Member name="reserved" value="false" guard="defined (CY_USING_HAL)" /> 288 <Member name="funcs" value="NULL" guard="defined (CY_USING_HAL)" /> 289 </ConfigStruct> 290 291 <ConfigStruct name="`${INST_NAME}`_hal_config" type="cyhal_i2c_configurator_t" const="`${inFlash}`" public="true" include="true" guard="defined (CY_USING_HAL) || defined(CY_USING_HAL_LITE)"> 292 <Member name="resource" value="&`${INST_NAME}`_obj" /> 293 <Member name="config" value="&`${INST_NAME}`_config" /> 294 <Member name="clock" value="&`${INST_NAME}`_clock" /> 295 </ConfigStruct> 296 297 <ConfigInstruction purpose="INITIALIZE" value="Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB`${InstNumber}`_PERI_NR, CY_MMIO_SCB`${InstNumber}`_GROUP_NR, CY_MMIO_SCB`${InstNumber}`_SLAVE_NR, CY_MMIO_SCB`${InstNumber}`_CLK_HF_NR);" include="`${(ipName eq "mxs22scb")}`" /> 298 <ConfigInstruction purpose="INITIALIZE" value="Cy_SysClk_PeriPclkAssignDivider(`${pclkDst}`, `${getExposedMember(sourceClock, "clockSel")}`);" include="`${(((version > 1) || (ipName eq "mxs22scb")) && pclkOk)}`" /> 299 <ConfigInstruction purpose="INITIALIZE" value="Cy_SysClk_PeriphAssignDivider(`${pclkDst}`, `${getExposedMember(sourceClock, "clockSel")}`);" include="`${((version eq 1) && pclkOk && (ipName ne "mxs22scb"))}`" /> 300 301 <ConfigInstruction purpose="RESERVE" value="cyhal_hwmgr_reserve(&`${INST_NAME}`_obj);" include="true" guard="defined (CY_USING_HAL)" /> 302 </ConfigFirmware> 303</Personality> 304
