1 /***************************************************************************//**
2 * \file cy_sysint.c
3 * \version 1.90.1
4 *
5 * \brief
6 * Provides an API implementation of the SysInt driver.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
11 * an affiliate of Cypress Semiconductor Corporation.
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26
27 #include "cy_device.h"
28
29 #if (defined (CY_IP_M33SYSCPUSS) || defined(CY_IP_M55APPCPUSS))
30
31 #include "cy_sysint.h"
32
33 #if (CY_CPU_CORTEX_M0P) || defined(CY_PDL_TZ_ENABLED)
34 static uint32_t *__vector_table_rw_ptr = (uint32_t*)&__s_vector_table_rw;
35 #else
36 static uint32_t *__vector_table_rw_ptr = (uint32_t*)&__ns_vector_table_rw;
37 #endif
38
39 #if ((defined(CY_CPU_CORTEX_M0P) && (CY_CPU_CORTEX_M0P)) && !defined(CY_IP_M0SECCPUSS))
Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum,cy_en_intr_t intrSrc)40 void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, cy_en_intr_t intrSrc)
41 #else
42 void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, IRQn_Type intrSrc)
43 #endif
44 {
45 #if ((defined(CY_CPU_CORTEX_M0P) && (CY_CPU_CORTEX_M0P)) && !defined(CY_IP_M0SECCPUSS))
46 CY_ASSERT_L1(CY_SYSINT_IS_PC_0);
47 (void)nmiNum;
48 (void)intrSrc;
49 #else
50 CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum));
51 #if (CY_CPU_CORTEX_M55)
52 MXCM55_CM55_NMI_CTL((uint32_t)nmiNum - 1UL) = (uint32_t)intrSrc;
53 #else
54 MXCM33_CM33_NMI_CTL((uint32_t)nmiNum - 1UL) = (uint32_t)intrSrc;
55 #endif
56 #endif
57 }
58
59
60 #if ((defined(CY_CPU_CORTEX_M0P) && (CY_CPU_CORTEX_M0P)) && !defined(CY_IP_M0SECCPUSS))
Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum)61 cy_en_intr_t Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum)
62 #else
63 IRQn_Type Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum)
64 #endif
65 {
66 CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum));
67
68 #if ((defined(CY_CPU_CORTEX_M0P) && (CY_CPU_CORTEX_M0P)) && !defined(CY_IP_M0SECCPUSS))
69 return (cy_en_intr_t)nmiNum;
70 #else
71 #if (CY_CPU_CORTEX_M55)
72 return ((IRQn_Type)(MXCM55_CM55_NMI_CTL((uint32_t)nmiNum - 1UL)));
73 #else
74 return ((IRQn_Type)(MXCM33_CM33_NMI_CTL((uint32_t)nmiNum - 1UL)));
75 #endif
76 #endif
77 }
78
79
Cy_SysInt_Init(const cy_stc_sysint_t * config,cy_israddress userIsr)80 cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr)
81 {
82 cy_en_sysint_status_t status = CY_SYSINT_SUCCESS;
83
84 if(NULL != config)
85 {
86 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
87
88 NVIC_SetPriority(config->intrSrc, config->intrPriority);
89
90 if (SCB->VTOR == (uint32_t)__vector_table_rw_ptr)
91 {
92 (void)Cy_SysInt_SetVector(config->intrSrc, userIsr);
93 }
94 }
95 else
96 {
97 status = CY_SYSINT_BAD_PARAM;
98 }
99
100 return(status);
101 }
102
103 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 10.1', 2, \
104 'IRQn of essential type enum is used as an operand to the arithmetic operator +')
Cy_SysInt_SetVector(IRQn_Type IRQn,cy_israddress userIsr)105 cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr)
106 {
107 cy_israddress prevIsr;
108
109 if (SCB->VTOR == (uint32_t)__vector_table_rw_ptr)
110 {
111 CY_ASSERT_L1(CY_SYSINT_IS_VECTOR_VALID(userIsr));
112 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.4','left hand operand 16U is not the same as that of the right operand IRQn(enum)');
113 prevIsr = (cy_israddress)__vector_table_rw_ptr[CY_INT_IRQ_BASE + (uint32_t)IRQn];
114 __vector_table_rw_ptr[CY_INT_IRQ_BASE + (uint32_t)IRQn] = (uint32_t)userIsr;
115 }
116 else
117 {
118 /* vector table is always loaded to non secure SRAM, so there is no need to return
119 the non-secure ROM vector */
120 prevIsr = NULL;
121 }
122
123 return (prevIsr);
124 }
125 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 10.1')
126
Cy_SysInt_GetVector(IRQn_Type IRQn)127 cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn)
128 {
129 cy_israddress currIsr;
130
131 if (SCB->VTOR == (uint32_t)__vector_table_rw_ptr)
132 {
133 currIsr = (cy_israddress)__vector_table_rw_ptr[CY_INT_IRQ_BASE + (uint32_t)IRQn];
134 }
135 else
136 {
137 /* vector table is always loaded to non-secure SRAM, so there is no need to return
138 the non-secure ROM vector */
139 currIsr = NULL;
140 }
141
142 return (currIsr);
143 }
144
145 #if !(defined(CY_CPU_CORTEX_M0P) && (CY_CPU_CORTEX_M0P))
Cy_SysInt_SoftwareTrig(IRQn_Type IRQn)146 void Cy_SysInt_SoftwareTrig(IRQn_Type IRQn)
147 {
148 NVIC->STIR = (uint32_t)IRQn & CY_SYSINT_STIR_MASK;
149 }
150 #endif
151
152 #endif
153
154 /* [] END OF FILE */
155
