1 /**
2 * @file xmc_spi.h
3 * @date 2019-05-07
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial
41 *
42 * 2015-05-20:
43 * - Documentation improved <br>
44 * - Added XMC_SPI_CH_SetSlaveSelectDelay(), XMC_SPI_CH_TriggerServiceRequest() and
45 * XMC_SPI_CH_SelectInterruptNodePointer() <br>
46 * - Added XMC_SPI_CH_SetInterwordDelaySCLK() <br>
47 *
48 * 2015-06-20:
49 * - Removed version macros and declaration of GetDriverVersion API <br>
50 *
51 * 2015-08-24:
52 * - Added APIs for enabling/disabling delay compensation XMC_SPI_CH_DisableDelayCompensation() and
53 * XMC_SPI_CH_EnableDelayCompensation() <br>
54 *
55 * 2015-08-27:
56 * - Added APIs for external input for BRG configuration:XMC_SPI_CH_ConfigExternalInputSignalToBRG() <br>
57 *
58 * 2015-09-01:
59 * - Modified XMC_SPI_CH_SetInputSource() for avoiding complete DXCR register overwriting. <br>
60 * - Modified XMC_SPI_CH_EVENT_t enum for supporting XMC_SPI_CH_EnableEvent() and XMC_SPI_CH_DisableEvent()
61 * for supporting multiple events configuration <br>
62 *
63 * 2015-09-08:
64 * - Adding API for configuring the receiving clock phase in the slave:XMC_SPI_CH_DataLatchedInTrailingEdge() and XMC_SPI_CH_DataLatchedInLeadingEdge() <br>
65 *
66 * 2016-04-10:
67 * - Added an API for configuring the transmit mode:XMC_SPI_CH_SetTransmitMode() <br>
68 *
69 * 2016-05-20:
70 * - Added XMC_SPI_CH_EnableDataTransmission() and XMC_SPI_CH_DisableDataTransmission()
71 *
72 * 2019-03-30:
73 * - Fix XMC_SPI_CH_MODE_STANDARD_HALFDUPLEX macro value
74 *
75 * 2019-05-07:
76 * - Added normal_divider_mode to XMC_SPI_CH_CONFIG_t configuration structure.
77 * It selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection
78 * - Added XMC_SPI_CH_SetBaudrateEx()
79 *
80 * @endcond
81 *
82 */
83
84 #ifndef XMC_SPI_H
85 #define XMC_SPI_H
86
87 /**********************************************************************************************************************
88 * HEADER FILES
89 *********************************************************************************************************************/
90 #include "xmc_usic.h"
91
92 /**
93 * @addtogroup XMClib XMC Peripheral Library
94 * @{
95 */
96
97 /**
98 * @addtogroup SPI
99 * @brief Synchronous serial channel driver for SPI-like communication.
100 *
101 * The SPI driver uses Universal Serial Interface Channel(USIC) module.
102 * The USIC module supports multiple data lines for SPI communication. \n
103 * -# Full duplex communication with 2 separate lines for transmission and reception.
104 * -# Half duplex communication with 1 common line shared for transmission and reception.
105 * -# Dual mode communication with 2 common lines shared for transmission and reception.
106 * -# Quad mode communication with 4 common lines shared for transmission and reception.<br><br>
107 *
108 * SPI driver provides structures, enumerations and APIs for configuring the USIC channel for SPI communication
109 * and also for data transaction.<br>
110 * SPI driver features:
111 * -# Configuration structure XMC_SPI_CH_CONFIG_t and SPI initialization function XMC_SPI_CH_Init()
112 * -# Allows configuration of protocol word and frame length using XMC_SPI_CH_SetWordLength(), XMC_SPI_CH_SetFrameLength()
113 * -# Allows manipulation of data frame at runtime using XMC_SPI_CH_EnableSOF(), XMC_SPI_CH_EnableEOF(),
114 XMC_SPI_CH_EnableSlaveSelect(), XMC_SPI_CH_DisableSlaveSelect()
115 * -# Provides APIs for transmitting data and receiving data using XMC_SPI_CH_Transmit(), XMC_SPI_CH_Receive(), XMC_SPI_CH_GetReceivedData()
116 * -# Allows configuration of shift clock using XMC_SPI_CH_ConfigureShiftClockOutput()
117 * -# Provides enumeration of SPI protocol events using @ref XMC_SPI_CH_STATUS_FLAG_t
118 * @{
119 */
120
121 /***********************************************************************************************************************
122 * MACROS
123 **********************************************************************************************************************/
124
125 #if defined(USIC0)
126 #define XMC_SPI0_CH0 XMC_USIC0_CH0 /**< SPI0 channel 0 base address */
127 #define XMC_SPI0_CH1 XMC_USIC0_CH1 /**< SPI0 channel 1 base address */
128 #endif
129
130 #if defined(USIC1)
131 #define XMC_SPI1_CH0 XMC_USIC1_CH0 /**< SPI1 channel 0 base address */
132 #define XMC_SPI1_CH1 XMC_USIC1_CH1 /**< SPI1 channel 1 base address */
133 #endif
134
135 #if defined(USIC2)
136 #define XMC_SPI2_CH0 XMC_USIC2_CH0 /**< SPI2 channel 0 base address */
137 #define XMC_SPI2_CH1 XMC_USIC2_CH1 /**< SPI2 channel 1 base address */
138 #endif
139
140 /***********************************************************************************************************************
141 * ENUMS
142 ***********************************************************************************************************************/
143
144 /**
145 * Defines return status of SPI driver APIs
146 */
147 typedef enum XMC_SPI_CH_STATUS
148 {
149 XMC_SPI_CH_STATUS_OK, /**< Status of the Module: OK */
150 XMC_SPI_CH_STATUS_ERROR, /**< Status of the Module: ERROR */
151 XMC_SPI_CH_STATUS_BUSY /**< The Module is busy */
152 } XMC_SPI_CH_STATUS_t;
153 /**
154 * Defines the SPI bus mode
155 */
156 typedef enum XMC_SPI_CH_BUS_MODE
157 {
158 XMC_SPI_CH_BUS_MODE_MASTER, /**< SPI Master */
159 XMC_SPI_CH_BUS_MODE_SLAVE /**< SPI Slave */
160 } XMC_SPI_CH_BUS_MODE_t;
161
162 /**
163 * Defines the Polarity of the slave select signals SELO[7:0] in relation to the master slave select signal MSLS.
164 */
165 typedef enum XMC_SPI_CH_SLAVE_SEL_MSLS_INV
166 {
167 XMC_SPI_CH_SLAVE_SEL_SAME_AS_MSLS = 0x0UL, /**< The SELO outputs have the same polarity as the MSLS signal
168 (active high) */
169 XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS = 0x1UL << USIC_CH_PCR_SSCMode_SELINV_Pos /**< The SELO outputs have the inverted
170 polarity to the MSLS signal
171 (active low)*/
172 } XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t;
173
174 /**
175 * Defines the Polarity of the data inputs.
176 */
177 typedef enum XMC_SPI_CH_DATA_POLARITY
178 {
179 XMC_SPI_CH_DATA_POLARITY_DIRECT = 0x0UL, /**< The polarity of the data line is not inverted */
180 XMC_SPI_CH_DATA_POLARITY_INVERT = 0x1UL << USIC_CH_DX2CR_DPOL_Pos /**< The polarity of the data line is inverted */
181 } XMC_SPI_CH_DATA_POLARITY_t;
182
183 /**
184 * Defines Slave Select lines
185 */
186 typedef enum XMC_SPI_CH_SLAVE_SELECT
187 {
188 XMC_SPI_CH_SLAVE_SELECT_0 = 1UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 0 */
189 XMC_SPI_CH_SLAVE_SELECT_1 = 2UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 1 */
190 XMC_SPI_CH_SLAVE_SELECT_2 = 4UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 2 */
191 XMC_SPI_CH_SLAVE_SELECT_3 = 8UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 3 */
192 XMC_SPI_CH_SLAVE_SELECT_4 = 16UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 4 */
193 XMC_SPI_CH_SLAVE_SELECT_5 = 32UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 5 */
194 XMC_SPI_CH_SLAVE_SELECT_6 = 64UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 6 */
195 XMC_SPI_CH_SLAVE_SELECT_7 = 128UL << USIC_CH_PCR_SSCMode_SELO_Pos /**< Slave Select line 7 */
196 } XMC_SPI_CH_SLAVE_SELECT_t;
197
198 /**
199 * Defines SPI specific events
200 */
201 typedef enum XMC_SPI_CH_EVENT
202 {
203 XMC_SPI_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */
204 XMC_SPI_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */
205 XMC_SPI_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */
206 XMC_SPI_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */
207 XMC_SPI_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */
208 XMC_SPI_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */
209 XMC_SPI_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */
210
211 XMC_SPI_CH_EVENT_PARITY_ERROR = USIC_CH_PCR_SSCMode_PARIEN_Msk >> 13U, /**< Parity error event */
212 XMC_SPI_CH_EVENT_MSLS_CHANGE = USIC_CH_PCR_SSCMode_MSLSIEN_Msk >> 13U, /**< Master slave select(MSLS) output transition event*/
213 XMC_SPI_CH_EVENT_DX2TIEN_ACTIVATED = USIC_CH_PCR_SSCMode_DX2TIEN_Msk >> 13U /**< Slave select input signal transition event*/
214 } XMC_SPI_CH_EVENT_t;
215
216 /**
217 * Defines SPI event status
218 */
219 typedef enum XMC_SPI_CH_STATUS_FLAG
220 {
221 XMC_SPI_CH_STATUS_FLAG_MSLS = USIC_CH_PSR_SSCMode_MSLS_Msk, /**< Status of Master slave
222 select(MSLS) signal */
223 XMC_SPI_CH_STATUS_FLAG_DX2S = USIC_CH_PSR_SSCMode_DX2S_Msk, /**< Status of slave select
224 input(DX2) signal*/
225 XMC_SPI_CH_STATUS_FLAG_MSLS_EVENT_DETECTED = USIC_CH_PSR_SSCMode_MSLSEV_Msk, /**< Status for master slave select
226 output signal transition*/
227 XMC_SPI_CH_STATUS_FLAG_DX2T_EVENT_DETECTED = USIC_CH_PSR_SSCMode_DX2TEV_Msk, /**< Status for slave select
228 input signal transition */
229 XMC_SPI_CH_STATUS_FLAG_PARITY_ERROR_EVENT_DETECTED = USIC_CH_PSR_SSCMode_PARERR_Msk, /**< Indicates status of the
230 parity error */
231 XMC_SPI_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_SSCMode_RSIF_Msk, /**< Status for receive start
232 event */
233 XMC_SPI_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_SSCMode_DLIF_Msk, /**< Status for data lost event*/
234 XMC_SPI_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_SSCMode_TSIF_Msk, /**< Status for transmit shift
235 event */
236 XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_SSCMode_TBIF_Msk, /**< Status for transmit buffer
237 event */
238 XMC_SPI_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_SSCMode_RIF_Msk, /**< Status for receive event */
239 XMC_SPI_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_SSCMode_AIF_Msk, /**< Status for alternative
240 receive event */
241 XMC_SPI_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_SSCMode_BRGIF_Msk/**< Status for baud rate
242 generation error event */
243 } XMC_SPI_CH_STATUS_FLAG_t;
244
245 /**
246 * Defines input frequency sources for slave select signal delay configuration.
247 */
248 typedef enum XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY
249 {
250 XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPDIV = 0x0UL, /**< Output of PDIV divider: FPDIV */
251 XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPPP = 0x1UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos, /**< Peripheral clock: FPPP */
252 XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FSCLK = 0x2UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos, /**< Shift clock: FSCLK */
253 XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FMCLK = 0x3UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos /**< Master clock: FMCLK */
254 } XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_t;
255
256 /**
257 * Define data and clock input stages
258 */
259 typedef enum XMC_SPI_CH_INPUT
260 {
261 XMC_SPI_CH_INPUT_DIN0 = 0UL, /**< Data input stage 0 */
262 XMC_SPI_CH_INPUT_SLAVE_SCLKIN = 1UL, /**< Clock input stage */
263 XMC_SPI_CH_INPUT_SLAVE_SELIN = 2UL, /**< Slave select input stage */
264 XMC_SPI_CH_INPUT_DIN1 = 3UL, /**< Data input stage 1 */
265 XMC_SPI_CH_INPUT_DIN2 = 4UL, /**< Data input stage 2 */
266 XMC_SPI_CH_INPUT_DIN3 = 5UL /**< Data input stage 3 */
267 } XMC_SPI_CH_INPUT_t;
268
269 /**
270 * Define SPI data transfer mode
271 */
272 typedef enum XMC_SPI_CH_MODE
273 {
274 XMC_SPI_CH_MODE_STANDARD = 0UL, /**< SPI standard full duplex mode */
275 XMC_SPI_CH_MODE_STANDARD_HALFDUPLEX = 5UL, /**< SPI standard half duplex mode */
276 XMC_SPI_CH_MODE_DUAL= 6UL, /**< SPI half duplex mode with dual data lines */
277 XMC_SPI_CH_MODE_QUAD= 7UL /**< SPI half duplex mode with quad data lines */
278 } XMC_SPI_CH_MODE_t;
279
280
281 /**
282 * SPI Baudrate Generator shift clock passive level
283 */
284 typedef enum XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL
285 {
286 /**< Passive clock level 0, delay disabled */
287 XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED,
288 /**< Passive clock level 1, delay disabled */
289 XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED,
290 /**< Passive clock level 0, delay enabled */
291 XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED,
292 /**< Passive clock level 1, delay enabled */
293 XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED
294 } XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t;
295
296 /**
297 * SPI Baudrate Generator shift clock output
298 */
299 typedef enum XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT
300 {
301 XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK, /**< Baudrate Generator shift clock output: SCLK*/
302 XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 /**< Clock obtained as input from master: DX1*/
303 } XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t;
304
305 /**
306 * SPI channel interrupt node pointers
307 */
308 typedef enum XMC_SPI_CH_INTERRUPT_NODE_POINTER
309 {
310 XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */
311 XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */
312 XMC_SPI_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */
313 XMC_SPI_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */
314 XMC_SPI_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */
315 } XMC_SPI_CH_INTERRUPT_NODE_POINTER_t;
316
317 /**********************************************************************************************************************
318 * DATA STRUCTURES
319 **********************************************************************************************************************/
320
321 /**
322 * Structure for initializing SPI channel.
323 */
324 typedef struct XMC_SPI_CH_CONFIG
325 {
326 uint32_t baudrate; /**< Module baud rate for communication */
327 bool normal_divider_mode; /**< Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection */
328 XMC_SPI_CH_BUS_MODE_t bus_mode; /**< Bus mode: Master/Slave */
329 XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion; /**< Enable inversion of Slave select signal relative to the internal
330 MSLS signal */
331 XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Enable parity check for transmit and received data */
332 } XMC_SPI_CH_CONFIG_t;
333
334 /**********************************************************************************************************************
335 * API PROTOTYPES
336 *********************************************************************************************************************/
337
338 #ifdef __cplusplus
339 extern "C" {
340 #endif
341
342 /**
343 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
344 * @param config pointer to constant SPI channel configuration data structure.\n
345 * Refer data structure @ref XMC_SPI_CH_CONFIG_t for detail.
346 *
347 * @return None
348 *
349 * \par<b>Description:</b><br>
350 * Initializes the selected SPI \a channel with the \a config structure.\n\n
351 * Enable SPI channel by calling XMC_USIC_CH_Enable() and then configures
352 * <ul>
353 * <li>Baudrate,</li>
354 * <li>Passive data level as active high,</li>
355 * <li>Shift control signal as active high,</li>
356 * <li>Frame length as 64U,</li>
357 * <li>Word length as 8U,</li>
358 * <li>Enable Hardware port control mode,</li>
359 * <li>Enable transmission of data TDV(Transmit data valid) bit is set to 1,</li>
360 * <li>Enable invalidation of data in TBUF once loaded into shift register,</li>
361 * <li>Parity mode settings</li>
362 * </ul>
363 * And if master mode is selected,
364 * <ul>
365 * <li>Enables MSLS signal generation,</li>
366 * <li>configures slave selection as normal mode,</li>
367 * <li>Set polarity for the Slave signal,</li>
368 * <li>Enable Frame end mode(MSLS signal is kept active after transmission of a frame)</li>
369 * </ul>
370 */
371 void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config);
372
373 /**
374 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
375 *
376 * @return None
377 *
378 * \par<b>Description:</b><br>
379 * Set the selected USIC channel to operate in SPI mode, by setting CCR.MODE bits.\n\n
380 * It should be executed after XMC_SPI_CH_Init() during initialization. By invoking XMC_SPI_CH_Stop(), the MODE is set
381 * to IDLE state. Call XMC_SPI_CH_Start() to set the SPI mode again, as needed later in the program.
382 *
383 * \par<b>Related APIs:</b><BR>
384 * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop()
385 */
XMC_SPI_CH_Start(XMC_USIC_CH_t * const channel)386 __STATIC_INLINE void XMC_SPI_CH_Start(XMC_USIC_CH_t *const channel)
387 {
388 /* USIC channel in SPI mode */
389 XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_SPI);
390 }
391
392 /**
393 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
394 *
395 * @return XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for stopping is processed. \n
396 * XMC_SPI_CH_STATUS_OK- If the USIC channel is successfully put to IDLE mode. \n
397 * XMC_SPI_CH_STATUS_BUSY- If the USIC channel is busy transmitting data.
398 *
399 * \par<b>Description:</b><br>
400 * Set the selected SPI channel to IDLE mode, by clearing CCR.MODE bits.\n\n
401 * After calling XMC_SPI_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_SPI_CH_Start() has to be
402 * invoked to start the communication again.
403 *
404 * \par<b>Related APIs:</b><BR>
405 * XMC_SPI_CH_Start()
406 */
407 XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel);
408
409 /**
410 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
411 * @param rate Bus speed in bits per second
412 *
413 * @return XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for setting baudrate is processed. \n
414 * XMC_SPI_CH_STATUS_OK- If the baudrate is successfully changed. \n
415 * XMC_SPI_CH_STATUS_ERROR- If the new baudrate value is out of range.
416 *
417 * \par<b>Description:</b><br>
418 * Sets the bus speed in bits per second
419 *
420 * \par<b>Related APIs:</b><BR>
421 * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop(), XMC_USIC_CH_GetSCLKFrequency()
422 */
423 XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate);
424
425 /**
426 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
427 * @param rate Bus speed in bits per second
428 * @param normal_divider_mode Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter of signal at the cost of frequency selection
429 *
430 * @return XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for setting baudrate is processed. \n
431 * XMC_SPI_CH_STATUS_OK- If the baudrate is successfully changed. \n
432 * XMC_SPI_CH_STATUS_ERROR- If the new baudrate value is out of range.
433 *
434 * \par<b>Description:</b><br>
435 * Sets the bus speed in bits per second
436 *
437 * \par<b>Related APIs:</b><BR>
438 * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop(), XMC_USIC_CH_GetSCLKFrequency()
439 */
440 XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, const uint32_t rate, bool normal_divider_mode);
441
442 /**
443 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
444 * @param slave Slave select signal.\n
445 * Refer @ref XMC_SPI_CH_SLAVE_SELECT_t for valid values.
446 *
447 * @return None
448 *
449 * \par<b>Description:</b><br>
450 * Enable the selected slave signal by setting PCR.SELO bits.\n\n
451 * Each slave is connected with one slave select signal. This is not configured in XMC_SPI_CH_Init(). Invoke
452 * XMC_SPI_CH_EnableSlaveSelect() with required \a slave to to start the communication. After finishing the
453 * communication XMC_SPI_CH_DisableSlaveSelect() can be invoked to disable the slaves.
454 *
455 * \par<b>Related APIs:</b><BR>
456 * XMC_SPI_CH_DisableSlaveSelect()
457 */
458 void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SELECT_t slave);
459
460 /**
461 * @param channel A constant ponter to XMC_USIC_CH_t, pointing to the USIC channel base address.
462 *
463 * @return None
464 *
465 * \par<b>Description:</b><br>
466 * Disable all the slave signals by clearing PCR.SELO bits.\n\n
467 * XMC_SPI_CH_EnableSlaveSelect() has to be invoked to start the communication with the desired slave again.
468 *
469 * \par<b>Related APIs:</b><BR>
470 * XMC_SPI_CH_EnableSlaveSelect()
471 */
472 void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel);
473
474 /**
475 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
476 * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated.\n
477 * Refer @ref XMC_SPI_CH_MODE_t for valid values.
478 *
479 * @return None
480 *
481 * \par<b>Description:</b><br>
482 * In Dual and Quad modes, hardware port control(CCR.HPCEN) mode is enabled. \n\n
483 * By enabling this the direction of the data pin is updated by hardware itself. Before transmitting the data set the
484 * mode to ensure the proper communication.
485 *
486 * \par<b>Related APIs:</b><BR>
487 * XMC_SPI_CH_Transmit()
488 */
XMC_SPI_CH_SetTransmitMode(XMC_USIC_CH_t * const channel,const XMC_SPI_CH_MODE_t mode)489 __STATIC_INLINE void XMC_SPI_CH_SetTransmitMode(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_MODE_t mode)
490 {
491 channel->CCR = (channel->CCR & (uint32_t)(~USIC_CH_CCR_HPCEN_Msk)) |
492 (((uint32_t) mode << USIC_CH_CCR_HPCEN_Pos) & (uint32_t)USIC_CH_CCR_HPCEN_Msk);
493 }
494
495 /**
496 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
497 * @param data Data to be transmitted
498 * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated.\n
499 * Refer @ref XMC_SPI_CH_MODE_t for valid values.
500 *
501 * @return None
502 *
503 * \par<b>Description:</b><br>
504 * Puts the data into FIFO, if FIFO mode is enabled or else into standard buffer, by setting the proper mode.\n\n
505 * In Dual and Quad modes, hardware port control(CCR.HPCEN) mode is enabled. By enabling this the direction of the data
506 * pin is updated by hardware itself. TCI(Transmit Control Information) allows dynamic control of both the data shift mode
507 * and pin direction during data transfers by writing to SCTR.DSM and SCTR.HPCDIR bit fields. To support this auto
508 * update, TCSR.HPCMD(Hardware Port control) will be enabled during the initialization using XMC_SPI_CH_Init() for all modes.
509 *
510 *
511 * \par<b>Related APIs:</b><BR>
512 * XMC_SPI_CH_Receive()
513 */
514 void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_SPI_CH_MODE_t mode);
515
516 /**
517 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
518 * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated.\n
519 * Refer @ref XMC_SPI_CH_MODE_t for valid values.
520 *
521 * @return None
522 *
523 * \par<b>Description:</b><br>
524 * Transmits a dummy data(FFFFH) to provide clock for slave and receives the data from the slave.\n\n
525 * XMC_SPI_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data
526 * XMC_SPI_CH_GetReceivedData() can be invoked to read the data from the buffers.
527 *
528 * \par<b>Related APIs:</b><BR>
529 * XMC_SPI_CH_GetReceivedDaa()
530 */
XMC_SPI_CH_Receive(XMC_USIC_CH_t * const channel,const XMC_SPI_CH_MODE_t mode)531 __STATIC_INLINE void XMC_SPI_CH_Receive(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_MODE_t mode)
532 {
533 /* Transmit dummy data */
534 XMC_SPI_CH_Transmit(channel, (uint16_t)0xffffU, (XMC_SPI_CH_MODE_t)((uint16_t)mode & 0xfffbU));
535 }
536
537 /**
538 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
539 *
540 * @return uint16_t Data read from the receive buffer.
541 *
542 * \par<b>Description:</b><br>
543 * Reads data from the receive buffer based on the FIFO selection.\n\n
544 * Invocation of XMC_SPI_CH_Receive() receives the data and place it into receive buffer. After receiving the data
545 * XMC_SPI_CH_GetReceivedData() can be used to read the data from the buffer.
546 *
547 * \par<b>Related APIs:</b><BR>
548 * XMC_SPI_CH_Receive()
549 */
550 uint16_t XMC_SPI_CH_GetReceivedData(XMC_USIC_CH_t *const channel);
551
552 /**
553 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
554 *
555 * @return None
556 *
557 * \par<b>Description:</b><br>
558 * Set the order of data transfer from LSB to MSB, by clearing SCTR.SDIR bit.\n\n
559 * This is typically based on the slave settings. Invoke XMC_SPI_CH_SetBitOrderLsbFirst() to set direction as needed in
560 * the program.
561 *
562 * \par<b>Related APIs:</b><BR>
563 * XMC_SPI_CH_SetBitOrderMsbFirst()
564 */
XMC_SPI_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t * const channel)565 __STATIC_INLINE void XMC_SPI_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t *const channel)
566 {
567 channel->SCTR &= (uint32_t)~USIC_CH_SCTR_SDIR_Msk;
568 }
569
570 /**
571 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
572 *
573 * @return None
574 *
575 * \par<b>Description:</b><br>
576 * Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.\n\n
577 * This is typically based on the slave settings. This is not set during XMC_SPI_CH_Init().
578 * Invoke XMC_SPI_CH_SetBitOrderMsbFirst() to set direction as needed in the program.
579 *
580 * \par<b>Related APIs:</b><BR>
581 * XMC_SPI_CH_SetBitOrderLsbFirst()
582 */
XMC_SPI_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t * const channel)583 __STATIC_INLINE void XMC_SPI_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t *const channel)
584 {
585 channel->SCTR |= (uint32_t)USIC_CH_SCTR_SDIR_Msk;
586 }
587
588 /**
589 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
590 * @param event Protocol events which have to be enabled.
591 * Refer @ XMC_SPI_CH_EVENT_t for valid values. <b>OR</b> combinations of these enum items can be used
592 * as input.
593 *
594 * @return None
595 *
596 * \par<b>Description:</b><br>
597 * Enables the SPI protocol specific events, by configuring PCR register.\n\n
598 * Events can be enabled as needed using XMC_SPI_CH_EnableEvent().
599 * XMC_SPI_CH_DisableEvent() can be used to disable the events.
600 *
601 * \par<b>Related APIs:</b><BR>
602 * XMC_SPI_CH_DisableEvent()
603 */
604 void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
605
606 /**
607 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
608 * @param event Protocol events which have to be disabled.
609 * Refer @ XMC_SPI_CH_EVENT_t for valid values. <b>OR</b> combinations of these enum item can be used
610 * as input.
611 *
612 * @return None
613 *
614 * \par<b>Description:</b><br>
615 * Disables the SPI protocol specific events, by configuring PCR register.\n\n
616 * After disabling the events, XMC_SPI_CH_EnableEvent() has to be invoked to re-enable the events.
617 *
618 * \par<b>Related APIs:</b><BR>
619 * XMC_SPI_CH_EnableEvent()
620 */
621 void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
622
623 /**
624 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
625 *
626 * @return uint32_t Status of SPI protocol events.
627 *
628 * \par<b>Description:</b><br>
629 * Returns the status of the events, by reading PSR register.\n\n
630 * This indicates the status of the all the events, for SPI communication.
631 *
632 * \par<b>Related APIs:</b><BR>
633 * XMC_SPI_CH_ClearStatusFlag()
634 */
XMC_SPI_CH_GetStatusFlag(XMC_USIC_CH_t * const channel)635 __STATIC_INLINE uint32_t XMC_SPI_CH_GetStatusFlag(XMC_USIC_CH_t *const channel)
636 {
637 return channel->PSR_SSCMode;
638 }
639
640 /**
641 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
642 * @param flag Protocol event status to be cleared for detection of next occurence.
643 * Refer @ XMC_SPI_CH_STATUS_FLAG_t for valid values. <b>OR</b> combinations of these enum item can be used
644 * as input.
645 * @return None
646 *
647 * \par<b>Description:</b><br>
648 * Clears the events specified, by setting PSCR register.\n\n
649 * During communication the events occurred have to be cleared to detect their next occurence.\n
650 * e.g: During transmission Transmit buffer event occurs to indicating data word transfer has started. This
651 * event has to be cleared after transmission of each data word. Otherwise next event cannot be recognized.
652 *
653 * \par<b>Related APIs:</b><BR>
654 * XMC_SPI_CH_GetStatusFlag()
655 */
XMC_SPI_CH_ClearStatusFlag(XMC_USIC_CH_t * const channel,const uint32_t flag)656 __STATIC_INLINE void XMC_SPI_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag)
657 {
658 channel->PSCR |= flag;
659 }
660
661 /**
662 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
663 *
664 * @return None
665 *
666 * \par<b>Description:</b><br>
667 * Enables the generation of Master clock by setting PCR.MCLK bit.\n\n
668 * This clock can be used as a clock reference for external devices. This is not enabled during initialization in
669 * XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by
670 * XMC_SPI_CH_DisableMasterClock().
671 *
672 * \par<b>Related APIs:</b><BR>
673 * XMC_SPI_CH_DisableMasterClock()
674 */
XMC_SPI_CH_EnableMasterClock(XMC_USIC_CH_t * const channel)675 __STATIC_INLINE void XMC_SPI_CH_EnableMasterClock(XMC_USIC_CH_t *const channel)
676 {
677 channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_MCLK_Msk;
678 }
679
680 /**
681 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
682 *
683 * @return None
684 *
685 * \par<b>Description:</b><br>
686 * Disables the generation of Master clock by clearing PCR.MCLK bit.\n\n
687 * This clock can be enabled by invoking XMC_SPI_CH_EnableMasterClock() as needed in the program.
688 *
689 * \par<b>Related APIs:</b><BR>
690 * XMC_SPI_CH_EnableMasterClock()
691 */
XMC_SPI_CH_DisableMasterClock(XMC_USIC_CH_t * const channel)692 __STATIC_INLINE void XMC_SPI_CH_DisableMasterClock(XMC_USIC_CH_t *const channel)
693 {
694 channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_MCLK_Msk;
695 }
696 #ifdef USIC_CH_PCR_SSCMode_SLPHSEL_Msk
697 /**
698 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
699 *
700 * @return None
701 *
702 * \par<b>Description:</b><br>
703 * Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge.
704 *
705 * \par<b>Related APIs:</b><BR>
706 * XMC_SPI_CH_DataLatchedInLeadingEdge()
707 */
XMC_SPI_CH_DataLatchedInTrailingEdge(XMC_USIC_CH_t * const channel)708 __STATIC_INLINE void XMC_SPI_CH_DataLatchedInTrailingEdge(XMC_USIC_CH_t *const channel)
709 {
710 channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SLPHSEL_Msk;
711 }
712
713 /**
714 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
715 *
716 * @return None
717 *
718 * \par<b>Description:</b><br>
719 * The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2
720 * stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are
721 * always latched in with the leading edge.
722 *
723 * \par<b>Related APIs:</b><BR>
724 * XMC_SPI_CH_DataLatchedInTrailingEdge()
725 */
XMC_SPI_CH_DataLatchedInLeadingEdge(XMC_USIC_CH_t * const channel)726 __STATIC_INLINE void XMC_SPI_CH_DataLatchedInLeadingEdge(XMC_USIC_CH_t *const channel)
727 {
728 channel->PCR_SSCMode |= USIC_CH_PCR_SSCMode_SLPHSEL_Msk;
729 }
730 #endif
731 /**
732 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
733 *
734 * @return None
735 *
736 * \par<b>Description:</b><br>
737 * Enables the delay after each word, by setting PCR.TIWEN bit.\n\n
738 * The inter word delay starts at the end of last SCLK cycle of data word. During this time no clock pulses are
739 * generated and MSLS signal stays active. If inter word delay is not enabled, last data bit of a data word is directly
740 * followed by the first data bit of the next data word. This is not enabled in XMC_SPI_CH_Init(). To enable
741 * XMC_SPI_CH_EnableInterwordDelay() has to be invoked as needed in the program. And can be disabled by invoking
742 * XMC_SPI_CH_DisableInterwordDelay().
743 *
744 * \par<b>Related APIs:</b><BR>
745 * XMC_SPI_CH_DisableInterwordDelay()
746 */
XMC_SPI_CH_EnableInterwordDelay(XMC_USIC_CH_t * const channel)747 __STATIC_INLINE void XMC_SPI_CH_EnableInterwordDelay(XMC_USIC_CH_t *const channel)
748 {
749 channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_TIWEN_Msk;
750 }
751
752 /**
753 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
754 *
755 * @return None
756 *
757 * \par<b>Description:</b><br>
758 * Disables the delay after after each word, by clearing PCR.TIWEN bit.\n\n
759 * So the last data bit of a data word is directly followed by the first data bit of the next data word. If needed can
760 * be enabled by invoking XMC_SPI_CH_EnableInterwordDelay().
761 *
762 * \par<b>Related APIs:</b><BR>
763 * XMC_SPI_CH_EnableInterwordDelay()
764 */
XMC_SPI_CH_DisableInterwordDelay(XMC_USIC_CH_t * const channel)765 __STATIC_INLINE void XMC_SPI_CH_DisableInterwordDelay(XMC_USIC_CH_t *const channel)
766 {
767 channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_TIWEN_Msk;
768 }
769
770 /**
771 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
772 * @param tinterword_delay_ns delay in terms of nano seconds.
773 *
774 * @return None
775 *
776 * \par<b>Description:</b><br>
777 * Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields.\n\n
778 * The inter word delay is dependent on the peripheral clock. The maximum possible value is calculated by using the
779 * below formula\n
780 * Maximum inter word delay = ((1 + PCTQ1_max)(1 + DCTQ1_max)) / peripheral clock\n
781 * where PCTQ1_max = 3 and DCTQ1_max = 31\n
782 * After configuring the inter word delay, this has to be enabled by invoking XMC_SPI_CH_EnableInterwordDelay().
783 *
784 * \par<b>Related APIs:</b><BR>
785 * XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_SetInterwordDelaySCLK()
786 */
787 void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterword_delay_ns);
788
789 /**
790 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
791 * @param sclk_period in terms of clk cycles.
792 *
793 * @return None
794 *
795 * \par<b>Description:</b><br>
796 * Configures the inter word delay by setting PCR.DCTQ1 bit fields.\n\n
797 * This delay is dependent on the peripheral clock. The maximum possible value supported by this API
798 * is 32 clock cycles.
799 * After configuring the inter word delay, this has to be enabled by invoking XMC_SPI_CH_EnableInterwordDelay().
800 *
801 * \par<b>Related APIs:</b><BR>
802 * XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_EnableInterwordDelay()
803 */
XMC_SPI_CH_SetInterwordDelaySCLK(XMC_USIC_CH_t * const channel,uint32_t sclk_period)804 __STATIC_INLINE void XMC_SPI_CH_SetInterwordDelaySCLK(XMC_USIC_CH_t *const channel,uint32_t sclk_period)
805 {
806 channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode) & (~(USIC_CH_PCR_SSCMode_DCTQ1_Msk |
807 USIC_CH_PCR_SSCMode_PCTQ1_Msk |
808 USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) |
809 (((sclk_period - 1U) << USIC_CH_PCR_SSCMode_DCTQ1_Pos) |
810 (0x02U << USIC_CH_PCR_SSCMode_CTQSEL1_Pos));
811 }
812
813 /**
814 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
815 * @param sclk_period delay in terms of sclk clock cycles.
816 *
817 * @return None
818 *
819 * \par<b>Description:</b><br>
820 * Configures the leading/trailing delay by setting BRG.DCTQ bit field.\n\n
821 * This delay is dependent on the peripheral clock. The maximum possible value supported by this API
822 * is 30 clock cycles.
823 *
824 */
XMC_SPI_CH_SetSlaveSelectDelay(XMC_USIC_CH_t * const channel,uint32_t sclk_period)825 __STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectDelay(XMC_USIC_CH_t *const channel,uint32_t sclk_period)
826 {
827
828 channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk |
829 USIC_CH_BRG_PCTQ_Msk)) |
830 (((sclk_period - 1U) << USIC_CH_BRG_DCTQ_Pos) | (0x01U << USIC_CH_BRG_PCTQ_Pos));
831 }
832
833 /**
834 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
835 *
836 * @return None
837 *
838 * \par<b>Description:</b><br>
839 *
840 * Configure to keep MSLS(Slave select signal) active even after finishing the current data frame,
841 * by setting PCR.FEM bit.\n\n
842 * This is typically used during the transmission of multi-data word frames, where there is possibility of delay in
843 * delivering the data. Frame end mode is enabled in XMC_SPI_CH_Init() during initialization. To disable
844 * XMC_SPI_CH_DisableFEM() can be invoked as needed in the program.
845 *
846 * \par<b>Related APIs:</b><BR>
847 * XMC_SPI_CH_DisableFEM()
848 */
XMC_SPI_CH_EnableFEM(XMC_USIC_CH_t * const channel)849 __STATIC_INLINE void XMC_SPI_CH_EnableFEM(XMC_USIC_CH_t *const channel)
850 {
851 channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_FEM_Msk;
852 }
853
854 /**
855 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
856 *
857 * @return None
858 *
859 * \par<b>Description:</b><br>
860 * Configure to disable the MSLS(Slave select signal) if the current data frame is considered as finished,
861 * by setting PCR.FEM bit.\n\n
862 *
863 * When the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data, is
864 * considered as frame is ended and MSLS(Slave select signal) is disabled.
865 *
866 * \par<b>Related APIs:</b><BR>
867 * XMC_SPI_CH_EnableFEM()
868 */
XMC_SPI_CH_DisableFEM(XMC_USIC_CH_t * const channel)869 __STATIC_INLINE void XMC_SPI_CH_DisableFEM(XMC_USIC_CH_t *const channel)
870 {
871 channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_FEM_Msk;
872 }
873
874 /**
875 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
876 * @param passive_level polarity and delay of the selected shift clock.\n
877 * Refer @ref XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t for valid inputs.
878 * @param clock_output shift clock source.\n
879 * Refer @ref XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t for valid inputs.
880 *
881 * @return None
882 *
883 * \par<b>Description:</b><br>
884 * Configures the shift clock source with the selected polarity and delay by setting BRG.SCLKOSEL and BRG.SCLKCFG.\n\n
885 * In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available
886 * for external slave devices by SCLKOUT signal.\n
887 * In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.\n
888 * The shift clock output(SCLKOUT) signal polarity can be set relative to SCLK, with the delay of half the shift clock
889 * period. These settings are applicable only in master mode.
890 */
XMC_SPI_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t * const channel,const XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level,const XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output)891 __STATIC_INLINE void XMC_SPI_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel,
892 const XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level,
893 const XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output)
894 {
895 XMC_USIC_CH_ConfigureShiftClockOutput(channel, (XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t)passive_level,
896 (XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output);
897 }
898
899 /**
900 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
901 * @param word_length Number of bits to be configured for a data word. \n
902 * \b Range: 1 to 16.
903 *
904 * @return None
905 *
906 * \par<b>Description</b><br>
907 * Defines the data word length.\n\n
908 * Sets the number of bits to represent a data word. Frame length should be a multiple of word length.
909 *
910 * \par<b>Related APIs:</b><BR>
911 * XMC_SPI_CH_SetFrameLength()
912 */
XMC_SPI_CH_SetWordLength(XMC_USIC_CH_t * const channel,const uint8_t word_length)913 __STATIC_INLINE void XMC_SPI_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length)
914 {
915 XMC_USIC_CH_SetWordLength(channel, word_length);
916 }
917
918 /**
919 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
920 * @param frame_length Number of bits in a frame. \n
921 * \b Range: 1 to 64. If the value 64 is configured, then the frame does not
922 * automatically end. User should explicitly end the frame.
923 *
924 * @return None
925 *
926 * \par<b>Description</b><br>
927 * Define the data frame length.\n\n
928 * Set the number of bits to be serially transmitted in a frame.
929 * The frame length should be multiples of word length. If the value is set to 64, the frame does not
930 * automatically end. Use XMC_SPI_CH_DisableSlaveSelect() to end the frame after all the data
931 * is transmitted.
932 *
933 * \par<b>Related APIs:</b><BR>
934 * XMC_USIC_CH_SetWordLength(), XMC_USIC_CH_EnableFrameLengthControl(), XMC_SPI_CH_DisableSlaveSelect()
935 */
XMC_SPI_CH_SetFrameLength(XMC_USIC_CH_t * const channel,const uint8_t frame_length)936 __STATIC_INLINE void XMC_SPI_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length)
937 {
938 XMC_USIC_CH_SetFrameLength(channel, frame_length);
939 }
940
941 /**
942 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
943 *
944 * @return None
945 *
946 * \par<b>Description</b><br>
947 * Configure the handling of start of frame through software, by setting TCSR.SOF bit.\n\n
948 * This can be used if the software handles the TBUF data without FIFO. If SOF is set, a valid content of the TBUF is
949 * considered as first word of a new frame by finishing the currently running frame. For software handling of SOF bit,
950 * it is recommended to configure TCSR.WLEMD as 0. This is not configured during initialization. XMC_SPI_CH_EnableSOF()
951 * can be called as needed in the program and can be disabled by XMC_SPI_CH_DisableSOF().
952 *
953 * \par<b>Related APIs:</b><BR>
954 * XMC_SPI_CH_DisableSOF()
955 */
XMC_SPI_CH_EnableSOF(XMC_USIC_CH_t * const channel)956 __STATIC_INLINE void XMC_SPI_CH_EnableSOF(XMC_USIC_CH_t *const channel)
957 {
958 channel->TCSR |= (uint32_t)USIC_CH_TCSR_SOF_Msk;
959 }
960
961 /**
962 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
963 *
964 * @return None
965 *
966 * \par<b>Description</b><br>
967 * Set the control of the handling start of frame through hardware, by clearing TCSR.SOF bit.\n\n
968 * Typically this can be disabled, where the transmission control is done by the hardware.
969 *
970 * \par<b>Related APIs:</b><BR>
971 * XMC_SPI_CH_EnableSOF()
972 */
XMC_SPI_CH_DisableSOF(XMC_USIC_CH_t * const channel)973 __STATIC_INLINE void XMC_SPI_CH_DisableSOF(XMC_USIC_CH_t *const channel)
974 {
975 channel->TCSR &= (uint32_t)~USIC_CH_TCSR_SOF_Msk;
976 }
977
978 /**
979 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
980 *
981 * @return None
982 *
983 * \par<b>Description</b><br>
984 * Configure the handling of end of frame through software, by setting TCSR.EOF bit.\n\n
985 * This can be used if the software handles the TBUF data without FIFO. If EOF is set, a valid content of the TBUF is
986 * considered as last word of a frame. After transfer of the last word, MSLS signal becomes inactive. For software
987 * handling of EOF bit, it is recommended to configure TCSR.WLEMD as 0. \n
988 * \b Note: The API should be called before putting the last data word of the frame to TBUF.
989 *
990 * \par<b>Related APIs:</b><BR>
991 * XMC_SPI_CH_DisableEOF()
992 */
XMC_SPI_CH_EnableEOF(XMC_USIC_CH_t * const channel)993 __STATIC_INLINE void XMC_SPI_CH_EnableEOF(XMC_USIC_CH_t *const channel)
994 {
995 channel->TCSR |= (uint32_t)USIC_CH_TCSR_EOF_Msk;
996 }
997
998 /**
999 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
1000 *
1001 * @return None
1002 *
1003 * \par<b>Description</b><br>
1004 * Configure the handling of end of frame through hardware, by clearing TCSR.EOF bit.\n\n
1005 * Typically this can be disabled, where the transmission control is done by the hardware.
1006 *
1007 * \par<b>Related APIs:</b><BR>
1008 * XMC_SPI_CH_EnableEOF()
1009 */
XMC_SPI_CH_DisableEOF(XMC_USIC_CH_t * const channel)1010 __STATIC_INLINE void XMC_SPI_CH_DisableEOF(XMC_USIC_CH_t *const channel)
1011 {
1012 channel->TCSR &= (uint32_t)~USIC_CH_TCSR_EOF_Msk;
1013 }
1014
1015 /**
1016 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
1017 * @param input SPI channel input stage.\n
1018 * Refer @ref XMC_SPI_CH_INPUT_t for valid values
1019 * @param source Input source select for the input stage.
1020 * Range : [0 to 7]
1021 *
1022 * @return None
1023 *
1024 * \par<b>Description</b><br>
1025 * Selects the data source for SPI input stage, by configuring DXCR.DSEL bits.\n\n
1026 * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the
1027 * input stages like DX0CR, DX1CR etc. This is not done during initialization. This has to be configured before starting
1028 * the SPI communication.
1029 */
XMC_SPI_CH_SetInputSource(XMC_USIC_CH_t * const channel,const XMC_SPI_CH_INPUT_t input,const uint8_t source)1030 __STATIC_INLINE void XMC_SPI_CH_SetInputSource(XMC_USIC_CH_t *const channel,
1031 const XMC_SPI_CH_INPUT_t input,
1032 const uint8_t source)
1033 {
1034 channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_DSEN_Msk)) | USIC_CH_DX0CR_INSW_Msk;
1035 XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source);
1036 }
1037
1038 /**
1039 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
1040 * @param selo_inversion Polarity of the slave select signal relative to the MSLS signal.\n
1041 * Refer @ref XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t for valid values
1042 *
1043 * @return None
1044 *
1045 * \par<b>Description</b><br>
1046 * Set the polarity of the slave select signal, by configuring PCR.SELINV bit.\n\n
1047 * Normally MSLS signal is active low level signal. SO based on the slave inversion has to be applied. This is configured
1048 * in XMC_SPI_CH_Init() during initialization. Invoke XMC_SPI_CH_SetSlaveSelectPolarity() with desired settings as
1049 * needed later in the program.
1050 */
XMC_SPI_CH_SetSlaveSelectPolarity(XMC_USIC_CH_t * const channel,const XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion)1051 __STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectPolarity(XMC_USIC_CH_t *const channel,
1052 const XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion)
1053 {
1054 /* Configuration of Protocol Control Register */
1055 channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode & (~USIC_CH_PCR_SSCMode_SELINV_Msk)) | (uint32_t)selo_inversion);
1056 }
1057
1058 /**
1059 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
1060 * @param input SPI channel input stage.\n
1061 * Refer @ref XMC_SPI_CH_INPUT_t for valid inputs.
1062 *
1063 * @return None
1064 *
1065 * \par<b>Description</b><br>
1066 * Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y = \a input).\n\n
1067 * This is not set in XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableInputInversion() as needed later in the program. To
1068 * disable the inversion XMC_SPI_CH_DisableInputInversion() can be invoked.
1069 *
1070 * \par<b>Related APIs:</b><BR>
1071 * XMC_SPI_CH_DisableInputInversion()
1072 */
XMC_SPI_CH_EnableInputInversion(XMC_USIC_CH_t * const channel,const XMC_SPI_CH_INPUT_t input)1073 __STATIC_INLINE void XMC_SPI_CH_EnableInputInversion(XMC_USIC_CH_t *const channel,
1074 const XMC_SPI_CH_INPUT_t input)
1075 {
1076 XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
1077 }
1078
1079 /**
1080 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
1081 * @param input SPI channel input stage.\n
1082 * Refer @ref XMC_SPI_CH_INPUT_t for valid inputs.
1083 *
1084 * @return None
1085 *
1086 * \par<b>Description</b><br>
1087 * Disables the polarity inversion of input data signal, by clearing DXyCR.DPOL(where y = \a input).\n\n
1088 * Resets the input data polarity. Invoke XMC_SPI_CH_EnableInputInversion() to apply inversion.
1089 *
1090 * \par<b>Related APIs:</b><BR>
1091 * XMC_SPI_CH_EnableInputInversion()
1092 */
XMC_SPI_CH_DisableInputInversion(XMC_USIC_CH_t * const channel,const XMC_SPI_CH_INPUT_t input)1093 __STATIC_INLINE void XMC_SPI_CH_DisableInputInversion(XMC_USIC_CH_t *const channel,
1094 const XMC_SPI_CH_INPUT_t input)
1095 {
1096 XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
1097 }
1098
1099 /**
1100 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
1101 * @param service_request Service request number.
1102 Range: [0 to 5]
1103 *
1104 * @return None
1105 *
1106 * \par<b>Description</b><br>
1107 * Sets the interrupt node for SPI channel events.\n\n
1108 * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
1109 * The NVIC node gets linked to the interrupt event by doing so. This is not configured in XMC_SPI_CH_Init() during
1110 * initialization.
1111 *
1112 * \par<b>Note::</b><BR>
1113 * 1. NVIC node should be separately enabled to generate the interrupt.
1114 *
1115 * \par<b>Related APIs:</b><BR>
1116 * XMC_USIC_CH_EnableEvent()
1117 */
XMC_SPI_CH_SetInterruptNodePointer(XMC_USIC_CH_t * const channel,const uint8_t service_request)1118 __STATIC_INLINE void XMC_SPI_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
1119 const uint8_t service_request)
1120 {
1121 XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, (uint32_t)service_request);
1122 }
1123
1124
1125 /**
1126 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1127 * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection
1128 * @param interrupt_node Interrupt node pointer to be configured. \n
1129 * \b Range: @ref XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
1130 * @ref XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
1131 * @param service_request Service request number.\n
1132 * \b Range: 0 to 5.
1133 * @return None
1134 *
1135 * \par<b>Description</b><br>
1136 * Sets the interrupt node for USIC channel events. \n\n
1137 * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
1138 * The NVIC node gets linked to the interrupt event by doing so.<br>
1139 * Note: NVIC node should be separately enabled to generate the interrupt.
1140 *
1141 * \par<b>Related APIs:</b><BR>
1142 * XMC_SPI_CH_EnableEvent() \n\n\n
1143 */
XMC_SPI_CH_SelectInterruptNodePointer(XMC_USIC_CH_t * const channel,const XMC_SPI_CH_INTERRUPT_NODE_POINTER_t interrupt_node,const uint32_t service_request)1144 __STATIC_INLINE void XMC_SPI_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel,
1145 const XMC_SPI_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
1146 const uint32_t service_request)
1147 {
1148 XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node,
1149 (uint32_t)service_request);
1150 }
1151
1152 /**
1153 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1154 * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection
1155 * @param service_request_line service request number of the event to be triggered. \n
1156 * \b Range: 0 to 5.
1157 * @return None
1158 *
1159 * \par<b>Description</b><br>
1160 * Trigger a SPI interrupt service request.\n\n
1161 * When the SPI service request is triggered, the NVIC interrupt associated with it will be
1162 * generated if enabled.
1163 *
1164 * \par<b>Related APIs:</b><BR>
1165 * XMC_SPI_CH_SelectInterruptNodePointer() \n\n\n
1166 */
XMC_SPI_CH_TriggerServiceRequest(XMC_USIC_CH_t * const channel,const uint32_t service_request_line)1167 __STATIC_INLINE void XMC_SPI_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line)
1168 {
1169 XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line);
1170 }
1171
1172 /**
1173 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1174 * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection
1175 * @return None
1176 *
1177 * \par<b>Description</b><br>
1178 * Enables delay compensation. \n\n
1179 *
1180 * Delay compensation can be applied to the receive path.
1181 * \par<b>Related APIs:</b><BR>
1182 * XMC_SPI_CH_DisableDelayCompensation()\n\n\n
1183 */
XMC_SPI_CH_EnableDelayCompensation(XMC_USIC_CH_t * const channel)1184 __STATIC_INLINE void XMC_SPI_CH_EnableDelayCompensation(XMC_USIC_CH_t *const channel)
1185 {
1186 XMC_USIC_CH_EnableDelayCompensation(channel);
1187 }
1188
1189 /**
1190 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1191 * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection
1192 * @return None
1193 *
1194 * \par<b>Description</b><br>
1195 * Disables delay compensation.. \n\n
1196 *
1197 * \par<b>Related APIs:</b><BR>
1198 * XMC_SPI_CH_EnableDelayCompensation()\n\n\n
1199 */
XMC_SPI_CH_DisableDelayCompensation(XMC_USIC_CH_t * const channel)1200 __STATIC_INLINE void XMC_SPI_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel)
1201 {
1202 XMC_USIC_CH_DisableDelayCompensation(channel);
1203 }
1204
1205 /**
1206 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1207 * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection
1208 * @param pdiv Desired divider for the external frequency input. \b Range: minimum value = 1, maximum value = 1024 \n
1209 * @param combination_mode USIC channel input combination mode \n
1210 *
1211 * @return None
1212 *
1213 * \par<b>Description</b><br>
1214 * Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and
1215 * the combination mode of the USIC channel. \n\n
1216 *
1217 * \par<b>Related APIs:</b><BR>
1218 * XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n
1219 */
XMC_SPI_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t * const channel,const uint16_t pdiv,const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)1220 __STATIC_INLINE void XMC_SPI_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel,
1221 const uint16_t pdiv,
1222 const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)
1223 {
1224 XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel,pdiv,2U,combination_mode);
1225 }
1226
1227 /**
1228 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
1229 *
1230 * @return None
1231 *
1232 * \par<b>Description</b><br>
1233 * The SELOx lines (with x = 1-7) can be used as addresses for an external address
1234 * decoder to increase the number of external slave devices.
1235 */
XMC_SPI_CH_EnableSlaveSelectCodedMode(XMC_USIC_CH_t * const channel)1236 __STATIC_INLINE void XMC_SPI_CH_EnableSlaveSelectCodedMode(XMC_USIC_CH_t *const channel)
1237 {
1238 /* Configuration of Protocol Control Register */
1239 channel->PCR_SSCMode = (uint32_t)(channel->PCR_SSCMode & (~USIC_CH_PCR_SSCMode_SELCTR_Msk));
1240 }
1241
1242 /**
1243 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
1244 *
1245 * @return None
1246 *
1247 * \par<b>Description</b><br>
1248 * Each SELOx line (with x = 0-7) can be directly connected to an external slave device.
1249 */
XMC_SPI_CH_DisableSlaveSelectCodedMode(XMC_USIC_CH_t * const channel)1250 __STATIC_INLINE void XMC_SPI_CH_DisableSlaveSelectCodedMode(XMC_USIC_CH_t *const channel)
1251 {
1252 /* Configuration of Protocol Control Register */
1253 channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_SELCTR_Msk;
1254 }
1255
1256 /**
1257 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
1258 * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection
1259 * @return None
1260 *
1261 * \par<b>Description</b><br>
1262 * Enable data transmission.\n\n
1263 * Use this function in combination with XMC_SPI_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
1264 * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
1265 * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
1266 *
1267 * \par<b>Related APIs:</b><BR>
1268 * XMC_SPI_CH_DisableDataTransmission()\n\n\n
1269 */
XMC_SPI_CH_EnableDataTransmission(XMC_USIC_CH_t * const channel)1270 __STATIC_INLINE void XMC_SPI_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
1271 {
1272 XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
1273 }
1274
1275 /**
1276 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
1277 * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection
1278 * @return None
1279 *
1280 * \par<b>Description</b><br>
1281 * Disable data transmission.\n\n
1282 * Use this function in combination with XMC_SPI_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
1283 * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
1284 *
1285 * \par<b>Related APIs:</b><BR>
1286 * XMC_SPI_CH_EnableDataTransmission()\n\n\n
1287 */
XMC_SPI_CH_DisableDataTransmission(XMC_USIC_CH_t * const channel)1288 __STATIC_INLINE void XMC_SPI_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
1289 {
1290 XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED);
1291 }
1292
1293 #ifdef __cplusplus
1294 }
1295 #endif
1296
1297 /**
1298 * @}
1299 */
1300
1301 /**
1302 * @}
1303 */
1304
1305 #endif
1306
