1/********************************************************************************************************************* 2 * @file startup_XMC4504.S 3 * @brief CMSIS Core Device Startup File for Infineon XMC4504 Device Series 4 * @version V1.21 5 * @date 01 June 2016 6 * 7 * @cond 8 ********************************************************************************************************************* 9 * Copyright (c) 2011-2016, Infineon Technologies AG 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 13 * following conditions are met: 14 * 15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials provided with the distribution. 20 * 21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 22 * products derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 33 * Infineon Technologies AG dave@infineon.com). 34 ********************************************************************************************************************* 35 * 36 **************************** Change history ******************************** 37 * V1.0,July 2011, First version for XIP profile 38 * V1.1,Oct 2011, Program loading code included (GH: b to main changed) 39 * V1.2,Nov, 01, 2011 GH :Removed second definition of section .Xmc4500.reset 40 * at line 186. 41 * V1.3,Nov, 16, 2011 GH :Removed PMU0_1_IRQHandler and respective weak function 42 * declaration. 43 * V1.4,Dec, 16, 2011 PKB:Jump to __Xmc4500_start_c reinstated for RTOS integration 44 * V1.5,Jan, 10, 2012 PKB:Migrated to GCC from ARM 45 * V1.6,Jan, 16, 2012 PKB:Branch prediction turned off, Parity errors cleared. 46 * V1.7,Apr, 17, 2012 PKB:Added decision function for PLL initialization 47 * V1.8,Apr, 20, 2012 PKB:Handshake with DAVE code engine added 48 * V1.9,Jun, 14, 2012 PKB:Removed the handshake protocol towards simplification 49 * V1.10,Aug, 13, 2012 PKB:Flash Wait states handling 50 * V1.11,Oct, 11, 2012 PKB:C++ support. Call to global constructors 51 * V1.12,Jan, 23, 2013 PKB:XMC4 Prefetch bug workaround 52 * V1.13,Jul, 29, 2013 PKB:AAPCS violation in V1.12 fixed 53 * V1.14,Feb, 05, 2014 PKB:Removed redundant alignment code from copy+clear funcs 54 * V1.15,May, 05, 2014 JFT:Added ram_code section 55 * V1.16,Nov, 25, 2014 JFT:CPU workaround disabled. Single default handler. 56 * Removed DAVE3 dependency 57 * V1.17,June 11, 2015 JFT:Remove SystemCoreClockUpdate call, done in SystemCoreClockSetup 58 * V1.18,Nov 24, 2015 JFT:Remove peripherals not included in device 59 * V1.19,Jan, 05, 2016 JFT:Fix .reset section attributes 60 * V1.20,March,04,2016 JFT:Fix weak definition of Veneers. 61 * Only relevant for AA and AB step, which needs ENABLE_PMU_CM_001_WORKAROUND 62 * V1.21,June ,01,2016 JFT:Rename ENABLE_CPU_CM_001_WORKAROUND to ENABLE_PMU_CM_001_WORKAROUND 63 * Action required: If using AA/AB step, use ENABLE_PMU_CM_001_WORKAROUND instead of ENABLE_CPU_CM_001_WORKAROUND 64 * @endcond 65 */ 66 67/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ 68 69.macro Entry Handler 70#if defined(ENABLE_PMU_CM_001_WORKAROUND) 71 .long \Handler\()_Veneer 72#else 73 .long \Handler 74#endif 75.endm 76 77.macro Insert_ExceptionHandler Handler_Func 78 .weak \Handler_Func 79 .thumb_set \Handler_Func, Default_Handler 80 81#if defined(ENABLE_PMU_CM_001_WORKAROUND) 82 .weak \Handler_Func\()_Veneer 83 .type \Handler_Func\()_Veneer, %function 84\Handler_Func\()_Veneer: 85 push {r0, lr} 86 ldr r0, =\Handler_Func 87 blx r0 88 pop {r0, pc} 89 .size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer 90#endif 91.endm 92 93/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */ 94 95/* ================== START OF VECTOR TABLE DEFINITION ====================== */ 96/* Vector Table - This gets programed into VTOR register by onchip BootROM */ 97 .syntax unified 98 99 .section .reset, "a", %progbits 100 101 .align 2 102 .globl __Vectors 103 .type __Vectors, %object 104__Vectors: 105 .long __initial_sp /* Top of Stack */ 106 .long Reset_Handler /* Reset Handler */ 107 108 Entry NMI_Handler /* NMI Handler */ 109 Entry HardFault_Handler /* Hard Fault Handler */ 110 Entry MemManage_Handler /* MPU Fault Handler */ 111 Entry BusFault_Handler /* Bus Fault Handler */ 112 Entry UsageFault_Handler /* Usage Fault Handler */ 113 .long 0 /* Reserved */ 114 .long 0 /* Reserved */ 115 .long 0 /* Reserved */ 116 .long 0 /* Reserved */ 117 Entry SVC_Handler /* SVCall Handler */ 118 Entry DebugMon_Handler /* Debug Monitor Handler */ 119 .long 0 /* Reserved */ 120 Entry PendSV_Handler /* PendSV Handler */ 121 Entry SysTick_Handler /* SysTick Handler */ 122 123 /* Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals */ 124 Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */ 125 Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */ 126 Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */ 127 Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */ 128 Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */ 129 Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */ 130 Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */ 131 Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */ 132 Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */ 133 .long 0 /* Not Available */ 134 .long 0 /* Not Available */ 135 .long 0 /* Not Available */ 136 Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */ 137 .long 0 /* Not Available */ 138 Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */ 139 Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */ 140 Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */ 141 Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */ 142 Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */ 143 Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */ 144 Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */ 145 Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */ 146 Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */ 147 Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */ 148 Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */ 149 Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */ 150 Entry VADC0_G2_0_IRQHandler /* Handler name for SR VADC0_G2_0 */ 151 Entry VADC0_G2_1_IRQHandler /* Handler name for SR VADC0_G2_1 */ 152 Entry VADC0_G2_2_IRQHandler /* Handler name for SR VADC0_G2_2 */ 153 Entry VADC0_G2_3_IRQHandler /* Handler name for SR VADC0_G2_3 */ 154 Entry VADC0_G3_0_IRQHandler /* Handler name for SR VADC0_G3_0 */ 155 Entry VADC0_G3_1_IRQHandler /* Handler name for SR VADC0_G3_1 */ 156 Entry VADC0_G3_2_IRQHandler /* Handler name for SR VADC0_G3_2 */ 157 Entry VADC0_G3_3_IRQHandler /* Handler name for SR VADC0_G3_3 */ 158 Entry DSD0_0_IRQHandler /* Handler name for SR DSD0_0 */ 159 Entry DSD0_1_IRQHandler /* Handler name for SR DSD0_1 */ 160 Entry DSD0_2_IRQHandler /* Handler name for SR DSD0_2 */ 161 Entry DSD0_3_IRQHandler /* Handler name for SR DSD0_3 */ 162 Entry DSD0_4_IRQHandler /* Handler name for SR DSD0_4 */ 163 Entry DSD0_5_IRQHandler /* Handler name for SR DSD0_5 */ 164 Entry DSD0_6_IRQHandler /* Handler name for SR DSD0_6 */ 165 Entry DSD0_7_IRQHandler /* Handler name for SR DSD0_7 */ 166 Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */ 167 Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_0 */ 168 Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */ 169 Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */ 170 Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */ 171 Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */ 172 Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */ 173 Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */ 174 Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */ 175 Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */ 176 Entry CCU42_0_IRQHandler /* Handler name for SR CCU42_0 */ 177 Entry CCU42_1_IRQHandler /* Handler name for SR CCU42_1 */ 178 Entry CCU42_2_IRQHandler /* Handler name for SR CCU42_2 */ 179 Entry CCU42_3_IRQHandler /* Handler name for SR CCU42_3 */ 180 Entry CCU43_0_IRQHandler /* Handler name for SR CCU43_0 */ 181 Entry CCU43_1_IRQHandler /* Handler name for SR CCU43_1 */ 182 Entry CCU43_2_IRQHandler /* Handler name for SR CCU43_2 */ 183 Entry CCU43_3_IRQHandler /* Handler name for SR CCU43_3 */ 184 Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */ 185 Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */ 186 Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */ 187 Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */ 188 Entry CCU81_0_IRQHandler /* Handler name for SR CCU81_0 */ 189 Entry CCU81_1_IRQHandler /* Handler name for SR CCU81_1 */ 190 Entry CCU81_2_IRQHandler /* Handler name for SR CCU81_2 */ 191 Entry CCU81_3_IRQHandler /* Handler name for SR CCU81_3 */ 192 Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */ 193 Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */ 194 Entry POSIF1_0_IRQHandler /* Handler name for SR POSIF1_0 */ 195 Entry POSIF1_1_IRQHandler /* Handler name for SR POSIF1_1 */ 196 .long 0 /* Not Available */ 197 .long 0 /* Not Available */ 198 .long 0 /* Not Available */ 199 .long 0 /* Not Available */ 200 .long 0 /* Not Available */ 201 .long 0 /* Not Available */ 202 .long 0 /* Not Available */ 203 .long 0 /* Not Available */ 204 .long 0 /* Not Available */ 205 .long 0 /* Not Available */ 206 .long 0 /* Not Available */ 207 .long 0 /* Not Available */ 208 Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */ 209 Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */ 210 Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */ 211 Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */ 212 Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */ 213 Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */ 214 Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */ 215 Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */ 216 Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */ 217 Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */ 218 Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */ 219 Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */ 220 Entry USIC2_0_IRQHandler /* Handler name for SR USIC2_0 */ 221 Entry USIC2_1_IRQHandler /* Handler name for SR USIC2_1 */ 222 Entry USIC2_2_IRQHandler /* Handler name for SR USIC2_2 */ 223 Entry USIC2_3_IRQHandler /* Handler name for SR USIC2_3 */ 224 Entry USIC2_4_IRQHandler /* Handler name for SR USIC2_4 */ 225 Entry USIC2_5_IRQHandler /* Handler name for SR USIC2_5 */ 226 Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */ 227 .long 0 /* Not Available */ 228 Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */ 229 Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */ 230 Entry SDMMC0_0_IRQHandler /* Handler name for SR SDMMC0_0 */ 231 .long 0 /* Not Available */ 232 .long 0 /* Not Available */ 233 .long 0 /* Not Available */ 234 Entry GPDMA1_0_IRQHandler /* Handler name for SR GPDMA1_0 */ 235 .long 0 /* Not Available */ 236 237 .size __Vectors, . - __Vectors 238/* ================== END OF VECTOR TABLE DEFINITION ======================= */ 239 240/* ================== START OF VECTOR ROUTINES ============================= */ 241 242 .align 1 243 .thumb 244 245/* Reset Handler */ 246 .thumb_func 247 .globl Reset_Handler 248 .type Reset_Handler, %function 249Reset_Handler: 250 ldr sp,=__initial_sp 251 252#ifndef __SKIP_SYSTEM_INIT 253 ldr r0, =SystemInit 254 blx r0 255#endif 256 257/* Initialize data 258 * 259 * Between symbol address __copy_table_start__ and __copy_table_end__, 260 * there are array of triplets, each of which specify: 261 * offset 0: LMA of start of a section to copy from 262 * offset 4: VMA of start of a section to copy to 263 * offset 8: size of the section to copy. Must be multiply of 4 264 * 265 * All addresses must be aligned to 4 bytes boundary. 266 */ 267 ldr r4, =__copy_table_start__ 268 ldr r5, =__copy_table_end__ 269 270.L_loop0: 271 cmp r4, r5 272 bge .L_loop0_done 273 ldr r1, [r4] 274 ldr r2, [r4, #4] 275 ldr r3, [r4, #8] 276 277.L_loop0_0: 278 subs r3, #4 279 ittt ge 280 ldrge r0, [r1, r3] 281 strge r0, [r2, r3] 282 bge .L_loop0_0 283 284 adds r4, #12 285 b .L_loop0 286 287.L_loop0_done: 288 289/* Zero initialized data 290 * Between symbol address __zero_table_start__ and __zero_table_end__, 291 * there are array of tuples specifying: 292 * offset 0: Start of a BSS section 293 * offset 4: Size of this BSS section. Must be multiply of 4 294 * 295 * Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup. 296 */ 297#ifndef __SKIP_BSS_CLEAR 298 ldr r3, =__zero_table_start__ 299 ldr r4, =__zero_table_end__ 300 301.L_loop2: 302 cmp r3, r4 303 bge .L_loop2_done 304 ldr r1, [r3] 305 ldr r2, [r3, #4] 306 movs r0, 0 307 308.L_loop2_0: 309 subs r2, #4 310 itt ge 311 strge r0, [r1, r2] 312 bge .L_loop2_0 313 314 adds r3, #8 315 b .L_loop2 316.L_loop2_done: 317#endif /* __SKIP_BSS_CLEAR */ 318 319#ifndef __SKIP_LIBC_INIT_ARRAY 320 ldr r0, =__libc_init_array 321 blx r0 322#endif 323 324 ldr r0, =main 325 blx r0 326 327.align 2 328__copy_table_start__: 329 .long __data_load, __data_start, __data_size 330 .long __data3_load, __data3_start, __data3_size 331 .long __ram_code_load, __ram_code_start, __ram_code_size 332__copy_table_end__: 333 334__zero_table_start__: 335 .long __bss_start, __bss_size 336 .long __bss3_start, __bss3_size 337__zero_table_end__: 338 339 .pool 340 .size Reset_Handler,.-Reset_Handler 341 342/* ======================================================================== */ 343/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ 344 345/* Default exception Handlers - Users may override this default functionality by 346 defining handlers of the same name in their C code */ 347 348 .align 1 349 .thumb_func 350 .weak Default_Handler 351 .type Default_Handler, %function 352Default_Handler: 353 b . 354 .size Default_Handler, . - Default_Handler 355 356 Insert_ExceptionHandler NMI_Handler 357 Insert_ExceptionHandler HardFault_Handler 358 Insert_ExceptionHandler MemManage_Handler 359 Insert_ExceptionHandler BusFault_Handler 360 Insert_ExceptionHandler UsageFault_Handler 361 Insert_ExceptionHandler SVC_Handler 362 Insert_ExceptionHandler DebugMon_Handler 363 Insert_ExceptionHandler PendSV_Handler 364 Insert_ExceptionHandler SysTick_Handler 365 366 Insert_ExceptionHandler SCU_0_IRQHandler 367 Insert_ExceptionHandler ERU0_0_IRQHandler 368 Insert_ExceptionHandler ERU0_1_IRQHandler 369 Insert_ExceptionHandler ERU0_2_IRQHandler 370 Insert_ExceptionHandler ERU0_3_IRQHandler 371 Insert_ExceptionHandler ERU1_0_IRQHandler 372 Insert_ExceptionHandler ERU1_1_IRQHandler 373 Insert_ExceptionHandler ERU1_2_IRQHandler 374 Insert_ExceptionHandler ERU1_3_IRQHandler 375 Insert_ExceptionHandler PMU0_0_IRQHandler 376 Insert_ExceptionHandler VADC0_C0_0_IRQHandler 377 Insert_ExceptionHandler VADC0_C0_1_IRQHandler 378 Insert_ExceptionHandler VADC0_C0_2_IRQHandler 379 Insert_ExceptionHandler VADC0_C0_3_IRQHandler 380 Insert_ExceptionHandler VADC0_G0_0_IRQHandler 381 Insert_ExceptionHandler VADC0_G0_1_IRQHandler 382 Insert_ExceptionHandler VADC0_G0_2_IRQHandler 383 Insert_ExceptionHandler VADC0_G0_3_IRQHandler 384 Insert_ExceptionHandler VADC0_G1_0_IRQHandler 385 Insert_ExceptionHandler VADC0_G1_1_IRQHandler 386 Insert_ExceptionHandler VADC0_G1_2_IRQHandler 387 Insert_ExceptionHandler VADC0_G1_3_IRQHandler 388 Insert_ExceptionHandler VADC0_G2_0_IRQHandler 389 Insert_ExceptionHandler VADC0_G2_1_IRQHandler 390 Insert_ExceptionHandler VADC0_G2_2_IRQHandler 391 Insert_ExceptionHandler VADC0_G2_3_IRQHandler 392 Insert_ExceptionHandler VADC0_G3_0_IRQHandler 393 Insert_ExceptionHandler VADC0_G3_1_IRQHandler 394 Insert_ExceptionHandler VADC0_G3_2_IRQHandler 395 Insert_ExceptionHandler VADC0_G3_3_IRQHandler 396 Insert_ExceptionHandler DSD0_0_IRQHandler 397 Insert_ExceptionHandler DSD0_1_IRQHandler 398 Insert_ExceptionHandler DSD0_2_IRQHandler 399 Insert_ExceptionHandler DSD0_3_IRQHandler 400 Insert_ExceptionHandler DSD0_4_IRQHandler 401 Insert_ExceptionHandler DSD0_5_IRQHandler 402 Insert_ExceptionHandler DSD0_6_IRQHandler 403 Insert_ExceptionHandler DSD0_7_IRQHandler 404 Insert_ExceptionHandler DAC0_0_IRQHandler 405 Insert_ExceptionHandler DAC0_1_IRQHandler 406 Insert_ExceptionHandler CCU40_0_IRQHandler 407 Insert_ExceptionHandler CCU40_1_IRQHandler 408 Insert_ExceptionHandler CCU40_2_IRQHandler 409 Insert_ExceptionHandler CCU40_3_IRQHandler 410 Insert_ExceptionHandler CCU41_0_IRQHandler 411 Insert_ExceptionHandler CCU41_1_IRQHandler 412 Insert_ExceptionHandler CCU41_2_IRQHandler 413 Insert_ExceptionHandler CCU41_3_IRQHandler 414 Insert_ExceptionHandler CCU42_0_IRQHandler 415 Insert_ExceptionHandler CCU42_1_IRQHandler 416 Insert_ExceptionHandler CCU42_2_IRQHandler 417 Insert_ExceptionHandler CCU42_3_IRQHandler 418 Insert_ExceptionHandler CCU43_0_IRQHandler 419 Insert_ExceptionHandler CCU43_1_IRQHandler 420 Insert_ExceptionHandler CCU43_2_IRQHandler 421 Insert_ExceptionHandler CCU43_3_IRQHandler 422 Insert_ExceptionHandler CCU80_0_IRQHandler 423 Insert_ExceptionHandler CCU80_1_IRQHandler 424 Insert_ExceptionHandler CCU80_2_IRQHandler 425 Insert_ExceptionHandler CCU80_3_IRQHandler 426 Insert_ExceptionHandler CCU81_0_IRQHandler 427 Insert_ExceptionHandler CCU81_1_IRQHandler 428 Insert_ExceptionHandler CCU81_2_IRQHandler 429 Insert_ExceptionHandler CCU81_3_IRQHandler 430 Insert_ExceptionHandler POSIF0_0_IRQHandler 431 Insert_ExceptionHandler POSIF0_1_IRQHandler 432 Insert_ExceptionHandler POSIF1_0_IRQHandler 433 Insert_ExceptionHandler POSIF1_1_IRQHandler 434 Insert_ExceptionHandler USIC0_0_IRQHandler 435 Insert_ExceptionHandler USIC0_1_IRQHandler 436 Insert_ExceptionHandler USIC0_2_IRQHandler 437 Insert_ExceptionHandler USIC0_3_IRQHandler 438 Insert_ExceptionHandler USIC0_4_IRQHandler 439 Insert_ExceptionHandler USIC0_5_IRQHandler 440 Insert_ExceptionHandler USIC1_0_IRQHandler 441 Insert_ExceptionHandler USIC1_1_IRQHandler 442 Insert_ExceptionHandler USIC1_2_IRQHandler 443 Insert_ExceptionHandler USIC1_3_IRQHandler 444 Insert_ExceptionHandler USIC1_4_IRQHandler 445 Insert_ExceptionHandler USIC1_5_IRQHandler 446 Insert_ExceptionHandler USIC2_0_IRQHandler 447 Insert_ExceptionHandler USIC2_1_IRQHandler 448 Insert_ExceptionHandler USIC2_2_IRQHandler 449 Insert_ExceptionHandler USIC2_3_IRQHandler 450 Insert_ExceptionHandler USIC2_4_IRQHandler 451 Insert_ExceptionHandler USIC2_5_IRQHandler 452 Insert_ExceptionHandler LEDTS0_0_IRQHandler 453 Insert_ExceptionHandler FCE0_0_IRQHandler 454 Insert_ExceptionHandler GPDMA0_0_IRQHandler 455 Insert_ExceptionHandler SDMMC0_0_IRQHandler 456 Insert_ExceptionHandler GPDMA1_0_IRQHandler 457 458/* ============= END OF INTERRUPT HANDLER DEFINITION ====================== */ 459 460 .end 461
