1/**
2 * @file XMC4502x768.ld
3 * @date 2017-04-20
4 *
5 * @cond
6 *********************************************************************************************************************
7 * Linker file for the GNU C Compiler v1.8
8 * Supported devices: XMC4502-F100x768
9 *
10 * Copyright (c) 2015-2017, Infineon Technologies AG
11 * All rights reserved.
12 *
13 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
14 * following conditions are met:
15 *
16 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials provided with the distribution.
21 *
22 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
23 * products derived from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
26 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
34 * Infineon Technologies AG dave@infineon.com).
35 *********************************************************************************************************************
36 *
37 * Change History
38 * --------------
39 *
40 * 2015-07-07:
41 *     - Product splitting
42 *     - Copyright notice update
43 *
44 * 2015-11-24:
45 *     - Compatibility with GCC 4.9 2015q2
46 *
47 * 2016-03-08:
48 *     - Fix size of BSS and DATA sections to be multiple of 4
49 *     - Add assertion to check that region DSRAM_1_system does not overflowed no_init section
50 *
51 * 2017-04-07:
52 *     - Added new symbols __text_size and eText
53 *
54 * 2017-04-20:
55 *     - Change vtable location to flash area to save ram
56 *
57 * @endcond
58 *
59 */
60
61OUTPUT_FORMAT("elf32-littlearm")
62OUTPUT_ARCH(arm)
63ENTRY(Reset_Handler)
64
65MEMORY
66{
67    FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0xC0000
68    FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0xC0000
69    PSRAM_1(!RX) : ORIGIN = 0x10000000, LENGTH = 0x10000
70    DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x10000
71    DSRAM_2_comm(!RX) : ORIGIN = 0x30000000, LENGTH = 0x8000
72}
73
74stack_size = DEFINED(stack_size) ? stack_size : 2048;
75no_init_size = 64;
76
77SECTIONS
78{
79    /* TEXT section */
80
81    .text :
82    {
83        sText = .;
84        KEEP(*(.reset));
85        *(.text .text.* .gnu.linkonce.t.*);
86
87        /* C++ Support */
88        KEEP(*(.init))
89        KEEP(*(.fini))
90
91        /* .ctors */
92        *crtbegin.o(.ctors)
93        *crtbegin?.o(.ctors)
94        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
95        *(SORT(.ctors.*))
96        *(.ctors)
97
98        /* .dtors */
99        *crtbegin.o(.dtors)
100        *crtbegin?.o(.dtors)
101        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
102        *(SORT(.dtors.*))
103        *(.dtors)
104
105        *(.rodata .rodata.*)
106        *(.gnu.linkonce.r*)
107
108        *(vtable)
109
110        . = ALIGN(4);
111    } > FLASH_1_cached AT > FLASH_1_uncached
112
113    .eh_frame_hdr : ALIGN (4)
114    {
115      KEEP (*(.eh_frame_hdr))
116    } > FLASH_1_cached AT > FLASH_1_uncached
117
118    .eh_frame : ALIGN (4)
119    {
120      KEEP (*(.eh_frame))
121    } > FLASH_1_cached AT > FLASH_1_uncached
122
123    /* Exception handling, exidx needs a dedicated section */
124    .ARM.extab : ALIGN (4)
125    {
126        *(.ARM.extab* .gnu.linkonce.armextab.*)
127    } > FLASH_1_cached AT > FLASH_1_uncached
128
129    . = ALIGN(4);
130    __exidx_start = .;
131    .ARM.exidx : ALIGN (4)
132    {
133        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
134    } > FLASH_1_cached AT > FLASH_1_uncached
135    __exidx_end = .;
136    . = ALIGN(4);
137
138
139    /* DSRAM layout (Lowest to highest)*/
140
141    Stack (NOLOAD) :
142    {
143        __stack_start = .;
144        . = . + stack_size;
145        __stack_end = .;
146        __initial_sp = .;
147    } > PSRAM_1
148
149    /* functions with __attribute__((section(".ram_code"))) */
150    .ram_code :
151    {
152        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
153        __ram_code_start = .;
154        *(.ram_code)
155        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
156        __ram_code_end = .;
157    } > PSRAM_1 AT > FLASH_1_uncached
158    __ram_code_load = LOADADDR (.ram_code);
159    __ram_code_size = __ram_code_end - __ram_code_start;
160
161    PSRAM_DATA :
162    {
163        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
164        __data3_start = .;
165        *(PSRAM_DATA)
166        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
167        __data3_end = .;
168    } > PSRAM_1 AT > FLASH_1_uncached
169    __data3_load = LOADADDR (PSRAM_DATA);
170    __data3_size = __data3_end - __data3_start;
171
172    PSRAM_BSS (NOLOAD) :
173    {
174        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
175        __bss3_start = .;
176        *(PSRAM_BSS)
177        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
178        __bss3_end = .;
179        . = ALIGN(8);
180        Heap_Bank3_Start = .;
181    } > PSRAM_1
182    __bss3_size = __bss3_end - __bss3_start;
183
184    /* Standard DATA and user defined DATA/BSS/CONST sections */
185    .data :
186    {
187        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
188        __data_start = .;
189        * (.data);
190        * (.data*);
191        *(*.data);
192        *(.gnu.linkonce.d*)
193
194        . = ALIGN(4);
195        /* preinit data */
196        PROVIDE_HIDDEN (__preinit_array_start = .);
197        KEEP(*(.preinit_array))
198        PROVIDE_HIDDEN (__preinit_array_end = .);
199
200        . = ALIGN(4);
201        /* init data */
202        PROVIDE_HIDDEN (__init_array_start = .);
203        KEEP(*(SORT(.init_array.*)))
204        KEEP(*(.init_array))
205        PROVIDE_HIDDEN (__init_array_end = .);
206
207        . = ALIGN(4);
208        /* finit data */
209        PROVIDE_HIDDEN (__fini_array_start = .);
210        KEEP(*(SORT(.fini_array.*)))
211        KEEP(*(.fini_array))
212        PROVIDE_HIDDEN (__fini_array_end = .);
213
214        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
215        __data_end = .;
216    } > DSRAM_1_system AT > FLASH_1_uncached
217    __data_load = LOADADDR (.data);
218    __data_size = __data_end - __data_start;
219
220    /* BSS section */
221    .bss (NOLOAD) :
222    {
223        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
224        __bss_start = .;
225        * (.bss);
226        * (.bss*);
227        * (COMMON);
228        *(.gnu.linkonce.b*)
229        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
230        __bss_end = .;
231        . = ALIGN(8);
232        Heap_Bank1_Start = .;
233    } > DSRAM_1_system
234    __bss_size = __bss_end - __bss_start;
235
236    /* .no_init section contains chipid, SystemCoreClock and trimming data. See system.c file*/
237    .no_init ORIGIN(DSRAM_1_system) + LENGTH(DSRAM_1_system) - no_init_size (NOLOAD) :
238    {
239        Heap_Bank1_End = .;
240        * (.no_init);
241    } > DSRAM_1_system
242
243    DSRAM2_DATA :
244    {
245        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
246        __data2_start = .;
247        *(DSRAM2_DATA)
248        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
249        __data2_end = .;
250    } > DSRAM_2_comm AT > FLASH_1_uncached
251    __data2_load = LOADADDR(DSRAM2_DATA);
252    __data2_size = __data2_end - __data2_start;
253
254    __text_size = (__exidx_end - sText) + __data_size + __ram_code_size + __data2_size + __data3_size;
255    eText = sText + __text_size;
256
257    DSRAM2_BSS (NOLOAD) :
258    {
259        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
260        __bss2_start = .;
261        *(USB_RAM)
262        *(DSRAM2_BSS)
263        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
264        __bss2_end = .;
265        . = ALIGN(8);
266        Heap_Bank2_Start = .;
267    } > DSRAM_2_comm
268    __bss2_size = __bss2_end - __bss2_start;
269
270    Heap_Bank1_Size = Heap_Bank1_End - Heap_Bank1_Start;
271    Heap_Bank2_Size = LENGTH(DSRAM_2_comm) - (Heap_Bank2_Start - ORIGIN(DSRAM_2_comm));
272    Heap_Bank3_Size = LENGTH(PSRAM_1) - (Heap_Bank3_Start - ORIGIN(PSRAM_1));
273
274    ASSERT(Heap_Bank1_Start <= Heap_Bank1_End, "region SRAM_combined overflowed no_init section")
275
276    /DISCARD/ :
277    {
278        *(.comment)
279    }
280
281    .stab       0 (NOLOAD) : { *(.stab) }
282    .stabstr    0 (NOLOAD) : { *(.stabstr) }
283
284    /* DWARF 1 */
285    .debug              0 : { *(.debug) }
286    .line               0 : { *(.line) }
287
288    /* GNU DWARF 1 extensions */
289    .debug_srcinfo      0 : { *(.debug_srcinfo) }
290    .debug_sfnames      0 : { *(.debug_sfnames) }
291
292    /* DWARF 1.1 and DWARF 2 */
293    .debug_aranges      0 : { *(.debug_aranges) }
294    .debug_pubnames     0 : { *(.debug_pubnames) }
295    .debug_pubtypes     0 : { *(.debug_pubtypes) }
296
297    /* DWARF 2 */
298    .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
299    .debug_abbrev       0 : { *(.debug_abbrev) }
300    .debug_line         0 : { *(.debug_line) }
301    .debug_frame        0 : { *(.debug_frame) }
302    .debug_str          0 : { *(.debug_str) }
303    .debug_loc          0 : { *(.debug_loc) }
304    .debug_macinfo      0 : { *(.debug_macinfo) }
305
306    /* DWARF 2.1 */
307    .debug_ranges       0 : { *(.debug_ranges) }
308
309    /* SGI/MIPS DWARF 2 extensions */
310    .debug_weaknames    0 : { *(.debug_weaknames) }
311    .debug_funcnames    0 : { *(.debug_funcnames) }
312    .debug_typenames    0 : { *(.debug_typenames) }
313    .debug_varnames     0 : { *(.debug_varnames) }
314
315    /* Build attributes */
316    .build_attributes   0 : { *(.ARM.attributes) }
317}
318