1/**
2 * @file XMC4500x1024.ld
3 * @date 2017-04-20
4 *
5 * @cond
6 *********************************************************************************************************************
7 * Linker file for the GNU C Compiler v1.8
8 * Supported devices: XMC4500-E144x1024
9 *                    XMC4500-F144x1024
10 *                    XMC4500-F100x1024
11 *
12 * Copyright (c) 2015-2017, Infineon Technologies AG
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
16 * following conditions are met:
17 *
18 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials provided with the distribution.
23 *
24 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
25 * products derived from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
36 * Infineon Technologies AG dave@infineon.com).
37 *********************************************************************************************************************
38 *
39 * Change History
40 * --------------
41 *
42 * 2015-07-07:
43 *     - Product splitting
44 *     - Copyright notice update
45 *
46 * 2015-11-24:
47 *     - Compatibility with GCC 4.9 2015q2
48 *
49 * 2016-03-08:
50 *     - Fix size of BSS and DATA sections to be multiple of 4
51 *     - Add assertion to check that region DSRAM_1_system does not overflowed no_init section
52 *
53 * 2017-04-07:
54 *     - Added new symbols __text_size and eText
55 *
56 * 2017-04-20:
57 *     - Change vtable location to flash area to save ram
58 *
59 * @endcond
60 *
61 */
62
63OUTPUT_FORMAT("elf32-littlearm")
64OUTPUT_ARCH(arm)
65ENTRY(Reset_Handler)
66
67MEMORY
68{
69    FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x100000
70    FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x100000
71    PSRAM_1(!RX) : ORIGIN = 0x10000000, LENGTH = 0x10000
72    DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x10000
73    DSRAM_2_comm(!RX) : ORIGIN = 0x30000000, LENGTH = 0x8000
74}
75
76stack_size = DEFINED(stack_size) ? stack_size : 2048;
77no_init_size = 64;
78
79SECTIONS
80{
81    /* TEXT section */
82
83    .text :
84    {
85        sText = .;
86        KEEP(*(.reset));
87        *(.text .text.* .gnu.linkonce.t.*);
88
89        /* C++ Support */
90        KEEP(*(.init))
91        KEEP(*(.fini))
92
93        /* .ctors */
94        *crtbegin.o(.ctors)
95        *crtbegin?.o(.ctors)
96        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
97        *(SORT(.ctors.*))
98        *(.ctors)
99
100        /* .dtors */
101        *crtbegin.o(.dtors)
102        *crtbegin?.o(.dtors)
103        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
104        *(SORT(.dtors.*))
105        *(.dtors)
106
107        *(.rodata .rodata.*)
108        *(.gnu.linkonce.r*)
109
110        *(vtable)
111
112        . = ALIGN(4);
113    } > FLASH_1_cached AT > FLASH_1_uncached
114
115    .eh_frame_hdr : ALIGN (4)
116    {
117      KEEP (*(.eh_frame_hdr))
118    } > FLASH_1_cached AT > FLASH_1_uncached
119
120    .eh_frame : ALIGN (4)
121    {
122      KEEP (*(.eh_frame))
123    } > FLASH_1_cached AT > FLASH_1_uncached
124
125    /* Exception handling, exidx needs a dedicated section */
126    .ARM.extab : ALIGN (4)
127    {
128        *(.ARM.extab* .gnu.linkonce.armextab.*)
129    } > FLASH_1_cached AT > FLASH_1_uncached
130
131    . = ALIGN(4);
132    __exidx_start = .;
133    .ARM.exidx : ALIGN (4)
134    {
135        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
136    } > FLASH_1_cached AT > FLASH_1_uncached
137    __exidx_end = .;
138    . = ALIGN(4);
139
140    /* DSRAM layout (Lowest to highest)*/
141
142    Stack (NOLOAD) :
143    {
144        __stack_start = .;
145        . = . + stack_size;
146        __stack_end = .;
147        __initial_sp = .;
148    } > PSRAM_1
149
150    /* functions with __attribute__((section(".ram_code"))) */
151    .ram_code :
152    {
153        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
154        __ram_code_start = .;
155        *(.ram_code)
156        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
157        __ram_code_end = .;
158    } > PSRAM_1 AT > FLASH_1_uncached
159    __ram_code_load = LOADADDR (.ram_code);
160    __ram_code_size = __ram_code_end - __ram_code_start;
161
162    PSRAM_DATA :
163    {
164        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
165        __data3_start = .;
166        *(PSRAM_DATA)
167        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
168        __data3_end = .;
169    } > PSRAM_1 AT > FLASH_1_uncached
170    __data3_load = LOADADDR (PSRAM_DATA);
171    __data3_size = __data3_end - __data3_start;
172
173    PSRAM_BSS (NOLOAD) :
174    {
175        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
176        __bss3_start = .;
177        *(PSRAM_BSS)
178        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
179       __bss3_end = .;
180        . = ALIGN(8);
181        Heap_Bank3_Start = .;
182    } > PSRAM_1
183    __bss3_size = __bss3_end - __bss3_start;
184
185    /* Standard DATA and user defined DATA/BSS/CONST sections */
186    .data :
187    {
188        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
189        __data_start = .;
190        * (.data);
191        * (.data*);
192        *(*.data);
193        *(.gnu.linkonce.d*)
194
195        . = ALIGN(4);
196        /* preinit data */
197        PROVIDE_HIDDEN (__preinit_array_start = .);
198        KEEP(*(.preinit_array))
199        PROVIDE_HIDDEN (__preinit_array_end = .);
200
201        . = ALIGN(4);
202        /* init data */
203        PROVIDE_HIDDEN (__init_array_start = .);
204        KEEP(*(SORT(.init_array.*)))
205        KEEP(*(.init_array))
206        PROVIDE_HIDDEN (__init_array_end = .);
207
208        . = ALIGN(4);
209        /* finit data */
210        PROVIDE_HIDDEN (__fini_array_start = .);
211        KEEP(*(SORT(.fini_array.*)))
212        KEEP(*(.fini_array))
213        PROVIDE_HIDDEN (__fini_array_end = .);
214
215        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
216        __data_end = .;
217    } > DSRAM_1_system AT > FLASH_1_uncached
218    __data_load = LOADADDR (.data);
219    __data_size = __data_end - __data_start;
220
221    /* BSS section */
222    .bss (NOLOAD) :
223    {
224        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
225        __bss_start = .;
226        * (.bss);
227        * (.bss*);
228        * (COMMON);
229        *(.gnu.linkonce.b*)
230        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
231        __bss_end = .;
232        . = ALIGN(8);
233        Heap_Bank1_Start = .;
234    } > DSRAM_1_system
235    __bss_size = __bss_end - __bss_start;
236
237    /* .no_init section contains chipid, SystemCoreClock and trimming data. See system.c file*/
238    .no_init ORIGIN(DSRAM_1_system) + LENGTH(DSRAM_1_system) - no_init_size (NOLOAD) :
239    {
240        Heap_Bank1_End = .;
241        * (.no_init);
242    } > DSRAM_1_system
243
244    DSRAM2_DATA :
245    {
246        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
247        __data2_start = .;
248        *(DSRAM2_DATA)
249        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
250        __data2_end = .;
251    } > DSRAM_2_comm AT > FLASH_1_uncached
252    __data2_load = LOADADDR(DSRAM2_DATA);
253    __data2_size = __data2_end - __data2_start;
254
255    __text_size = (__exidx_end - sText) + __data_size + __ram_code_size + __data2_size + __data3_size;
256    eText = sText + __text_size;
257
258    DSRAM2_BSS (NOLOAD) :
259    {
260        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
261        __bss2_start = .;
262        *(ETH_RAM)
263        *(USB_RAM)
264        *(DSRAM2_BSS)
265        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
266        __bss2_end = .;
267        . = ALIGN(8);
268        Heap_Bank2_Start = .;
269    } > DSRAM_2_comm
270    __bss2_size = __bss2_end - __bss2_start;
271
272    Heap_Bank1_Size = Heap_Bank1_End - Heap_Bank1_Start;
273    Heap_Bank2_Size = LENGTH(DSRAM_2_comm) - (Heap_Bank2_Start - ORIGIN(DSRAM_2_comm));
274    Heap_Bank3_Size = LENGTH(PSRAM_1) - (Heap_Bank3_Start - ORIGIN(PSRAM_1));
275
276    ASSERT(Heap_Bank1_Start <= Heap_Bank1_End, "region SRAM_combined overflowed no_init section")
277
278    /DISCARD/ :
279    {
280        *(.comment)
281    }
282
283    .stab       0 (NOLOAD) : { *(.stab) }
284    .stabstr    0 (NOLOAD) : { *(.stabstr) }
285
286    /* DWARF 1 */
287    .debug              0 : { *(.debug) }
288    .line               0 : { *(.line) }
289
290    /* GNU DWARF 1 extensions */
291    .debug_srcinfo      0 : { *(.debug_srcinfo) }
292    .debug_sfnames      0 : { *(.debug_sfnames) }
293
294    /* DWARF 1.1 and DWARF 2 */
295    .debug_aranges      0 : { *(.debug_aranges) }
296    .debug_pubnames     0 : { *(.debug_pubnames) }
297    .debug_pubtypes     0 : { *(.debug_pubtypes) }
298
299    /* DWARF 2 */
300    .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
301    .debug_abbrev       0 : { *(.debug_abbrev) }
302    .debug_line         0 : { *(.debug_line) }
303    .debug_frame        0 : { *(.debug_frame) }
304    .debug_str          0 : { *(.debug_str) }
305    .debug_loc          0 : { *(.debug_loc) }
306    .debug_macinfo      0 : { *(.debug_macinfo) }
307
308    /* DWARF 2.1 */
309    .debug_ranges       0 : { *(.debug_ranges) }
310
311    /* SGI/MIPS DWARF 2 extensions */
312    .debug_weaknames    0 : { *(.debug_weaknames) }
313    .debug_funcnames    0 : { *(.debug_funcnames) }
314    .debug_typenames    0 : { *(.debug_typenames) }
315    .debug_varnames     0 : { *(.debug_varnames) }
316
317    /* Build attributes */
318    .build_attributes   0 : { *(.ARM.attributes) }
319}
320