1 #include "GigaDevice/ioGD32VF103.h"
2 #include "intrinsics.h"
3 #include "csr.h"
4 #include "stdlib.h"
5 #include "stdint.h"
6
7 #pragma language=extended
8
9
10 extern __weak void eclic_msip_handler(void);
11 extern __weak void eclic_mtip_handler(void);
12 extern __weak void eclic_bwei_handler(void);
13 extern __weak void eclic_pmovi_handler(void);
14 extern __weak void WWDGT_IRQHandler(void);
15 extern __weak void LVD_IRQHandler(void);
16 extern __weak void TAMPER_IRQHandler(void);
17 extern __weak void RTC_IRQHandler(void);
18 extern __weak void FMC_IRQHandler(void);
19 extern __weak void RCU_IRQHandler(void);
20 extern __weak void EXTI0_IRQHandler(void);
21 extern __weak void EXTI1_IRQHandler(void);
22 extern __weak void EXTI2_IRQHandler(void);
23 extern __weak void EXTI3_IRQHandler(void);
24 extern __weak void EXTI4_IRQHandler(void);
25 extern __weak void DMA0_Channel0_IRQHandler(void);
26 extern __weak void DMA0_Channel1_IRQHandler(void);
27 extern __weak void DMA0_Channel2_IRQHandler(void);
28 extern __weak void DMA0_Channel3_IRQHandler(void);
29 extern __weak void DMA0_Channel4_IRQHandler(void);
30 extern __weak void DMA0_Channel5_IRQHandler(void);
31 extern __weak void DMA0_Channel6_IRQHandler(void);
32 extern __weak void ADC0_1_IRQHandler(void);
33 extern __weak void CAN0_TX_IRQHandler(void);
34 extern __weak void CAN0_RX0_IRQHandler(void);
35 extern __weak void CAN0_RX1_IRQHandler(void);
36 extern __weak void CAN0_EWMC_IRQHandler(void);
37 extern __weak void EXTI5_9_IRQHandler(void);
38 extern __weak void TIMER0_BRK_IRQHandler(void);
39 extern __weak void TIMER0_UP_IRQHandler(void);
40 extern __weak void TIMER0_TRG_CMT_IRQHandler(void);
41 extern __weak void TIMER0_Channel_IRQHandler(void);
42 extern __weak void TIMER1_IRQHandler(void);
43 extern __weak void TIMER2_IRQHandler(void);
44 extern __weak void TIMER3_IRQHandler(void);
45 extern __weak void I2C0_EV_IRQHandler(void);
46 extern __weak void I2C0_ER_IRQHandler(void);
47 extern __weak void I2C1_EV_IRQHandler(void);
48 extern __weak void I2C1_ER_IRQHandler(void);
49 extern __weak void SPI0_IRQHandler(void);
50 extern __weak void SPI1_IRQHandler(void);
51 extern __weak void USART0_IRQHandler(void);
52 extern __weak void USART1_IRQHandler(void);
53 extern __weak void USART2_IRQHandler(void);
54 extern __weak void EXTI10_15_IRQHandler(void);
55 extern __weak void RTC_Alarm_IRQHandler(void);
56 extern __weak void USBFS_WKUP_IRQHandler(void);
57 extern __weak void EXMC_IRQHandler(void);
58 extern __weak void TIMER4_IRQHandler(void);
59 extern __weak void SPI2_IRQHandler(void);
60 extern __weak void UART3_IRQHandler(void);
61 extern __weak void UART4_IRQHandler(void);
62 extern __weak void TIMER5_IRQHandler(void);
63 extern __weak void TIMER6_IRQHandler(void);
64 extern __weak void DMA1_Channel0_IRQHandler(void);
65 extern __weak void DMA1_Channel1_IRQHandler(void);
66 extern __weak void DMA1_Channel2_IRQHandler(void);
67 extern __weak void DMA1_Channel3_IRQHandler(void);
68 extern __weak void DMA1_Channel4_IRQHandler(void);
69 extern __weak void CAN1_TX_IRQHandler(void);
70 extern __weak void CAN1_RX0_IRQHandler(void);
71 extern __weak void CAN1_RX1_IRQHandler(void);
72 extern __weak void CAN1_EWMC_IRQHandler(void);
73 extern __weak void USBFS_IRQHandler(void);
74
75 typedef void(*__fp)(void);
76 const __fp gd_vector_base[96] =
77 {
78 0,
79 0,
80 0,
81 eclic_msip_handler,
82 0,
83 0,
84 0,
85 eclic_mtip_handler,
86 0,
87 0,
88 0,
89 0,
90 0,
91 0,
92 0,
93 0,
94 0,
95 eclic_bwei_handler,
96 eclic_pmovi_handler,
97 WWDGT_IRQHandler,
98 LVD_IRQHandler,
99 TAMPER_IRQHandler,
100 RTC_IRQHandler,
101 FMC_IRQHandler,
102 RCU_IRQHandler,
103 EXTI0_IRQHandler,
104 EXTI1_IRQHandler,
105 EXTI2_IRQHandler,
106 EXTI3_IRQHandler,
107 EXTI4_IRQHandler,
108 DMA0_Channel0_IRQHandler,
109 DMA0_Channel1_IRQHandler,
110 DMA0_Channel2_IRQHandler,
111 DMA0_Channel3_IRQHandler,
112 DMA0_Channel4_IRQHandler,
113 DMA0_Channel5_IRQHandler,
114 DMA0_Channel6_IRQHandler,
115 ADC0_1_IRQHandler,
116 CAN0_TX_IRQHandler,
117 CAN0_RX0_IRQHandler,
118 CAN0_RX1_IRQHandler,
119 CAN0_EWMC_IRQHandler,
120 EXTI5_9_IRQHandler,
121 TIMER0_BRK_IRQHandler,
122 TIMER0_UP_IRQHandler,
123 TIMER0_TRG_CMT_IRQHandler,
124 TIMER0_Channel_IRQHandler,
125 TIMER1_IRQHandler,
126 TIMER2_IRQHandler,
127 TIMER3_IRQHandler,
128 I2C0_EV_IRQHandler,
129 I2C0_ER_IRQHandler,
130 I2C1_EV_IRQHandler,
131 I2C1_ER_IRQHandler,
132 SPI0_IRQHandler,
133 SPI1_IRQHandler,
134 USART0_IRQHandler,
135 USART1_IRQHandler,
136 USART2_IRQHandler,
137 EXTI10_15_IRQHandler,
138 RTC_Alarm_IRQHandler,
139 USBFS_WKUP_IRQHandler,
140 0,
141 0,
142 0,
143 0,
144 0,
145 EXMC_IRQHandler,
146 0,
147 TIMER4_IRQHandler,
148 SPI2_IRQHandler,
149 UART3_IRQHandler,
150 UART4_IRQHandler,
151 TIMER5_IRQHandler,
152 TIMER6_IRQHandler,
153 DMA1_Channel0_IRQHandler,
154 DMA1_Channel1_IRQHandler,
155 DMA1_Channel2_IRQHandler,
156 DMA1_Channel3_IRQHandler,
157 DMA1_Channel4_IRQHandler,
158 0,
159 0,
160 CAN1_TX_IRQHandler,
161 CAN1_RX0_IRQHandler,
162 CAN1_RX1_IRQHandler,
163 CAN1_EWMC_IRQHandler,
164 USBFS_IRQHandler
165
166 };
167
168 extern unsigned int __minterrupt_clic_base;
169 extern __interrupt __machine void __minterrupt_single(void);
170
171 __interrupt __machine void __default_minterrupt_handler(void);
172
__default_minterrupt_handler(void)173 __interrupt __machine void __default_minterrupt_handler(void)
174 {
175 abort();
176 }
177
178 extern uintptr_t handle_trap(uintptr_t mcause, uintptr_t sp);
179
handle_trap(uintptr_t mcause,uintptr_t sp)180 uintptr_t handle_trap(uintptr_t mcause, uintptr_t sp)
181 {
182 __fp fp;
183 mcause &= 0xFFF;
184 fp = gd_vector_base[mcause];
185 if (fp)
186 fp();
187 return 0;
188 }
189
trap_entry()190 __interrupt void trap_entry()
191 {
192 uintptr_t mcause = __read_csr(_CSR_MCAUSE);
193 handle_trap(mcause, 0);
194 }
195
irq_entry()196 __interrupt void irq_entry()
197 {
198 uintptr_t mcause = __read_csr(_CSR_MCAUSE);
199 uintptr_t mepc = __read_csr(_CSR_MEPC);
200 uintptr_t msubm = __read_csr(0x7C4);
201 __enable_interrupt();
202 handle_trap(mcause, 0);
203 //asm("csrrw ra,0x7ED, ra");
204 __disable_interrupt();
205 __write_csr(_CSR_MCAUSE, mcause);
206 __write_csr(_CSR_MEPC, mepc);
207 __write_csr(0x7C4, msubm);
208 }
209
__low_level_init()210 int __low_level_init()
211 {
212 __disable_interrupt();
213 /* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */
214 /* li t0, 0x200 */
215 /* csrs CSR_MMISC_CTL, t0 */
216 __set_bits_csr(/*CSR_MMISC_CTL*/ 0x7D0, 0x200);
217
218 /* Initialize the mtvt */
219 /* la t0, vector_base */
220 /* csrw CSR_MTVT, t0 */
221 __write_csr(_CSR_MTVT, ((unsigned int)&gd_vector_base));
222 /* Initialize the mtvt2 and enable it */
223 /* la t0, irq_entry
224 csrw CSR_MTVT2, t0
225 csrs CSR_MTVT2, 0x1
226 */
227 __write_csr(/*_CSR_MTVT2*/ 0x7EC, 0x1 | ((unsigned int)&irq_entry));
228
229 /* Initialize the CSR MTVEC for the Trap ane NMI base addr*/
230 /* la t0, trap_entry
231 csrw CSR_MTVEC, t0
232 */
233 __write_csr(_CSR_MTVEC, 0x03 | ((unsigned int)&trap_entry));
234
235 /* Enable mycycle_minstret */
236 __clear_bits_csr(/*CSR_MCOUNTINHIBIT*/ 0x320, 0x5);
237 return 1;
238 }
