1 /*! 2 \file gd32f4xx_dbg.h 3 \brief definitions for the DBG 4 5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx 6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx 7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx 8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32F4XX_DBG_H 39 #define GD32F4XX_DBG_H 40 41 #include "gd32f4xx.h" 42 43 /* DBG definitions */ 44 #define DBG DBG_BASE 45 46 /* registers definitions */ 47 #define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ 48 #define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */ 49 #define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */ 50 #define DBG_CTL2 REG32(DBG + 0x0CU) /*!< DBG control register 2 */ 51 52 /* bits definitions */ 53 /* DBG_ID */ 54 #define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ 55 56 /* DBG_CTL0 */ 57 #define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ 58 #define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ 59 #define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ 60 #define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ 61 62 /* DBG_CTL1 */ 63 #define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */ 64 #define DBG_CTL1_TIMER2_HOLD BIT(1) /*!< hold TIMER2 counter when core is halted */ 65 #define DBG_CTL1_TIMER3_HOLD BIT(2) /*!< hold TIMER3 counter when core is halted */ 66 #define DBG_CTL1_TIMER4_HOLD BIT(3) /*!< hold TIMER4 counter when core is halted */ 67 #define DBG_CTL1_TIMER5_HOLD BIT(4) /*!< hold TIMER5 counter when core is halted */ 68 #define DBG_CTL1_TIMER6_HOLD BIT(5) /*!< hold TIMER6 counter when core is halted */ 69 #define DBG_CTL1_TIMER11_HOLD BIT(6) /*!< hold TIMER11 counter when core is halted */ 70 #define DBG_CTL1_TIMER12_HOLD BIT(7) /*!< hold TIMER12 counter when core is halted */ 71 #define DBG_CTL1_TIMER13_HOLD BIT(8) /*!< hold TIMER13 counter when core is halted */ 72 #define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ 73 #define DBG_CTL1_WWDGT_HOLD BIT(11) /*!< debug WWDGT kept when core is halted */ 74 #define DBG_CTL1_FWDGT_HOLD BIT(12) /*!< debug FWDGT kept when core is halted */ 75 #define DBG_CTL1_I2C0_HOLD BIT(21) /*!< hold I2C0 smbus when core is halted */ 76 #define DBG_CTL1_I2C1_HOLD BIT(22) /*!< hold I2C1 smbus when core is halted */ 77 #define DBG_CTL1_I2C2_HOLD BIT(23) /*!< hold I2C2 smbus when core is halted */ 78 #define DBG_CTL1_CAN0_HOLD BIT(25) /*!< debug CAN0 kept when core is halted */ 79 #define DBG_CTL1_CAN1_HOLD BIT(26) /*!< debug CAN1 kept when core is halted */ 80 81 /* DBG_CTL2 */ 82 #define DBG_CTL2_TIMER0_HOLD BIT(0) /*!< hold TIMER0 counter when core is halted */ 83 #define DBG_CTL2_TIMER7_HOLD BIT(1) /*!< hold TIMER7 counter when core is halted */ 84 #define DBG_CTL2_TIMER8_HOLD BIT(16) /*!< hold TIMER8 counter when core is halted */ 85 #define DBG_CTL2_TIMER9_HOLD BIT(17) /*!< hold TIMER9 counter when core is halted */ 86 #define DBG_CTL2_TIMER10_HOLD BIT(18) /*!< hold TIMER10 counter when core is halted */ 87 88 /* constants definitions */ 89 #define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ 90 #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ 91 #define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ 92 93 /* define the peripheral debug hold bit position and its register index offset */ 94 #define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) 95 #define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) 96 #define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 97 98 /* register index */ 99 enum dbg_reg_idx 100 { 101 DBG_IDX_CTL0 = 0x04U, 102 DBG_IDX_CTL1 = 0x08U, 103 DBG_IDX_CTL2 = 0x0CU 104 }; 105 106 typedef enum 107 { 108 DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 0U), /*!< hold TIMER1 counter when core is halted */ 109 DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 1U), /*!< hold TIMER2 counter when core is halted */ 110 DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 2U), /*!< hold TIMER3 counter when core is halted */ 111 DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 3U), /*!< hold TIMER4 counter when core is halted */ 112 DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 4U), /*!< hold TIMER5 counter when core is halted */ 113 DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 5U), /*!< hold TIMER6 counter when core is halted */ 114 DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< hold TIMER11 counter when core is halted */ 115 DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 7U), /*!< hold TIMER12 counter when core is halted */ 116 DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 8U), /*!< hold TIMER13 counter when core is halted */ 117 DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */ 118 DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 11U), /*!< debug WWDGT kept when core is halted */ 119 DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 12U), /*!< debug FWDGT kept when core is halted */ 120 DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 21U), /*!< hold I2C0 smbus when core is halted */ 121 DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 22U), /*!< hold I2C1 smbus when core is halted */ 122 DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */ 123 DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */ 124 DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */ 125 DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */ 126 DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */ 127 DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */ 128 DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */ 129 DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */ 130 }dbg_periph_enum; 131 132 /* function declarations */ 133 /* deinitialize the DBG */ 134 void dbg_deinit(void); 135 /* read DBG_ID code register */ 136 uint32_t dbg_id_get(void); 137 138 /* enable low power behavior when the MCU is in debug mode */ 139 void dbg_low_power_enable(uint32_t dbg_low_power); 140 /* disable low power behavior when the MCU is in debug mode */ 141 void dbg_low_power_disable(uint32_t dbg_low_power); 142 143 /* enable peripheral behavior when the MCU is in debug mode */ 144 void dbg_periph_enable(dbg_periph_enum dbg_periph); 145 /* disable peripheral behavior when the MCU is in debug mode */ 146 void dbg_periph_disable(dbg_periph_enum dbg_periph); 147 148 /* enable trace pin assignment */ 149 void dbg_trace_pin_enable(void); 150 /* disable trace pin assignment */ 151 void dbg_trace_pin_disable(void); 152 153 #endif /* GD32F4XX_DBG_H */ 154
