1 /*! 2 \file gd32f3x0_adc.h 3 \brief definitions for the ADC 4 5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0 6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0 7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F3X0_ADC_H 38 #define GD32F3X0_ADC_H 39 40 #include "gd32f3x0.h" 41 42 /* ADC definitions */ 43 #define ADC ADC_BASE 44 45 /* registers definitions */ 46 #define ADC_STAT REG32(ADC + 0x00000000U) /*!< ADC status register */ 47 #define ADC_CTL0 REG32(ADC + 0x00000004U) /*!< ADC control register 0 */ 48 #define ADC_CTL1 REG32(ADC + 0x00000008U) /*!< ADC control register 1 */ 49 #define ADC_SAMPT0 REG32(ADC + 0x0000000CU) /*!< ADC sampling time register 0 */ 50 #define ADC_SAMPT1 REG32(ADC + 0x00000010U) /*!< ADC sampling time register 1 */ 51 #define ADC_IOFF0 REG32(ADC + 0x00000014U) /*!< ADC inserted channel data offset register 0 */ 52 #define ADC_IOFF1 REG32(ADC + 0x00000018U) /*!< ADC inserted channel data offset register 1 */ 53 #define ADC_IOFF2 REG32(ADC + 0x0000001CU) /*!< ADC inserted channel data offset register 2 */ 54 #define ADC_IOFF3 REG32(ADC + 0x00000020U) /*!< ADC inserted channel data offset register 3 */ 55 #define ADC_WDHT REG32(ADC + 0x00000024U) /*!< ADC watchdog high threshold register */ 56 #define ADC_WDLT REG32(ADC + 0x00000028U) /*!< ADC watchdog low threshold register */ 57 #define ADC_RSQ0 REG32(ADC + 0x0000002CU) /*!< ADC regular sequence register 0 */ 58 #define ADC_RSQ1 REG32(ADC + 0x00000030U) /*!< ADC regular sequence register 1 */ 59 #define ADC_RSQ2 REG32(ADC + 0x00000034U) /*!< ADC regular sequence register 2 */ 60 #define ADC_ISQ REG32(ADC + 0x00000038U) /*!< ADC inserted sequence register */ 61 #define ADC_IDATA0 REG32(ADC + 0x0000003CU) /*!< ADC inserted data register 0 */ 62 #define ADC_IDATA1 REG32(ADC + 0x00000040U) /*!< ADC inserted data register 1 */ 63 #define ADC_IDATA2 REG32(ADC + 0x00000044U) /*!< ADC inserted data register 2 */ 64 #define ADC_IDATA3 REG32(ADC + 0x00000048U) /*!< ADC inserted data register 3 */ 65 #define ADC_RDATA REG32(ADC + 0x0000004CU) /*!< ADC regular data register */ 66 #define ADC_OVSAMPCTL REG32(ADC + 0x00000080U) /*!< ADC oversampling control register */ 67 68 /* bits definitions */ 69 /* ADC_STAT */ 70 #define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ 71 #define ADC_STAT_EOC BIT(1) /*!< end of conversion flag */ 72 #define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion flag */ 73 #define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ 74 #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ 75 76 /* ADC_CTL0 */ 77 #define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ 78 #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ 79 #define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ 80 #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ 81 #define ADC_CTL0_SM BIT(8) /*!< scan mode */ 82 #define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ 83 #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ 84 #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ 85 #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ 86 #define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ 87 #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ 88 #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ 89 #define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ 90 91 /* ADC_CTL1 */ 92 #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ 93 #define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ 94 #define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ 95 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ 96 #define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ 97 #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ 98 #define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ 99 #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ 100 #define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ 101 #define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */ 102 #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ 103 #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ 104 #define ADC_CTL1_TSVREN BIT(23) /*!< enable channel 16 and 17 */ 105 #define ADC_CTL1_VBETEN BIT(24) /*!< VBAT enable */ 106 107 /* ADC_SAMPTx x=0,1 */ 108 #define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n(n=0..18) sample time selection */ 109 110 /* ADC_IOFFx x=0..3 */ 111 #define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ 112 113 /* ADC_WDHT */ 114 #define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ 115 116 /* ADC_WDLT */ 117 #define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ 118 119 /* ADC_RSQx x=0..2 */ 120 #define ADC_RSQX_RSQN BITS(0,4) /*!< n conversion in regular sequence */ 121 #define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ 122 123 /* ADC_ISQ */ 124 #define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */ 125 #define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ 126 127 /* ADC_IDATAx x=0..3 */ 128 #define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */ 129 130 /* ADC_RDATA */ 131 #define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */ 132 133 /* ADC_OVSAMPCTL */ 134 #define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ 135 #define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ 136 #define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ 137 #define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ 138 139 /* constants definitions */ 140 /* ADC flag definitions */ 141 #define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ 142 #define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */ 143 #define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */ 144 #define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted channel group */ 145 #define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of regular channel group */ 146 147 /* adc_ctl0 register value */ 148 #define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */ 149 150 /* ADC special function */ 151 #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ 152 #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ 153 #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ 154 155 /* ADC data alignment */ 156 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< right alignment */ 157 #define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< left alignment */ 158 159 /* external trigger select for regular channel */ 160 #define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) 161 #define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ 162 #define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ 163 #define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ 164 #define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ 165 #define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ 166 #define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< TIMER14 CH0 event select */ 167 #define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ 168 #define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ 169 170 /* external trigger select for inserted channel */ 171 #define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) 172 #define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ 173 #define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ 174 #define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ 175 #define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ 176 #define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ 177 #define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< TIMER14 TRGO event select */ 178 #define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ 179 #define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ 180 181 /* adc_samptx register value */ 182 #define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) 183 #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ 184 #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ 185 #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ 186 #define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ 187 #define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ 188 #define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ 189 #define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ 190 #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ 191 192 /* ADC data offset for inserted channel x */ 193 #define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) 194 195 /* ADC analog watchdog high threshold */ 196 #define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) 197 198 /* ADC analog watchdog low threshold */ 199 #define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) 200 201 /* ADC regular channel group length */ 202 #define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) 203 204 /* ADC inserted channel group length */ 205 #define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) 206 207 /* ADC resolution definitions */ 208 #define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< ADC resolution */ 209 #define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ 210 #define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ 211 #define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ 212 #define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ 213 214 /* ADC oversampling shift */ 215 #define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) 216 #define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ 217 #define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ 218 #define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ 219 #define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ 220 #define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ 221 #define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ 222 #define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ 223 #define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ 224 #define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ 225 226 /* ADC oversampling ratio */ 227 #define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) 228 #define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ 229 #define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ 230 #define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ 231 #define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ 232 #define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ 233 #define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ 234 #define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ 235 #define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ 236 237 /* ADC triggered oversampling */ 238 #define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ 239 #define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ 240 241 /* ADC channel group definitions */ 242 #define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */ 243 #define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */ 244 #define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ 245 #define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ 246 247 /* ADC inserted channel definitions */ 248 #define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */ 249 #define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */ 250 #define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */ 251 #define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */ 252 253 /* ADC channel definitions */ 254 #define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ 255 #define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ 256 #define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ 257 #define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ 258 #define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ 259 #define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ 260 #define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ 261 #define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ 262 #define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ 263 #define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ 264 #define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ 265 #define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ 266 #define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ 267 #define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ 268 #define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ 269 #define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ 270 #define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ 271 #define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ 272 #define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ 273 274 /* ADC interrupt definitions */ 275 #define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ 276 #define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ 277 #define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ 278 279 /* ADC interrupt flag */ 280 #define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ 281 #define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ 282 #define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ 283 284 /* function declarations */ 285 /* reset ADC */ 286 void adc_deinit(void); 287 /* enable ADC interface */ 288 void adc_enable(void); 289 /* disable ADC interface */ 290 void adc_disable(void); 291 292 /* ADC calibration and reset calibration */ 293 void adc_calibration_enable(void); 294 /* enable DMA request */ 295 void adc_dma_mode_enable(void); 296 /* disable DMA request */ 297 void adc_dma_mode_disable(void); 298 299 /* enable the temperature sensor and Vrefint channel */ 300 void adc_tempsensor_vrefint_enable(void); 301 /* disable the temperature sensor and Vrefint channel */ 302 void adc_tempsensor_vrefint_disable(void); 303 /* enable the Vbat channel */ 304 void adc_vbat_enable(void); 305 /* disable the Vbat channel */ 306 void adc_vbat_disable(void); 307 308 /* configure ADC discontinuous mode */ 309 void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length); 310 /* configure ADC special function */ 311 void adc_special_function_config(uint32_t function, ControlStatus newvalue); 312 313 /* configure ADC data alignment */ 314 void adc_data_alignment_config(uint32_t data_alignment); 315 /* configure the length of regular channel group or inserted channel group */ 316 void adc_channel_length_config(uint8_t channel_group, uint32_t length); 317 /* configure ADC regular channel */ 318 void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); 319 /* configure ADC inserted channel */ 320 void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); 321 /* configure ADC inserted channel offset */ 322 void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset); 323 /* enable ADC external trigger */ 324 void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue); 325 /* configure ADC external trigger source */ 326 void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source); 327 /* enable ADC software trigger */ 328 void adc_software_trigger_enable(uint8_t channel_group); 329 330 /* read ADC regular group data register */ 331 uint16_t adc_regular_data_read(void); 332 /* read ADC inserted group data register */ 333 uint16_t adc_inserted_data_read(uint8_t inserted_channel); 334 335 /* get the ADC flag bits */ 336 FlagStatus adc_flag_get(uint32_t flag); 337 /* clear the ADC flag bits */ 338 void adc_flag_clear(uint32_t flag); 339 /* get the ADC interrupt bits */ 340 FlagStatus adc_interrupt_flag_get(uint32_t flag); 341 /* clear the ADC flag */ 342 void adc_interrupt_flag_clear(uint32_t flag); 343 /* enable ADC interrupt */ 344 void adc_interrupt_enable(uint32_t interrupt); 345 /* disable ADC interrupt */ 346 void adc_interrupt_disable(uint32_t interrupt); 347 348 /* configure ADC analog watchdog single channel */ 349 void adc_watchdog_single_channel_enable(uint8_t channel); 350 /* configure ADC analog watchdog group channel */ 351 void adc_watchdog_group_channel_enable(uint8_t channel_group); 352 /* disable ADC analog watchdog */ 353 void adc_watchdog_disable(void); 354 /* configure ADC analog watchdog threshold */ 355 void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold); 356 357 /* configure ADC resolution */ 358 void adc_resolution_config(uint32_t resolution); 359 /* configure ADC oversample mode */ 360 void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio); 361 /* enable ADC oversample mode */ 362 void adc_oversample_mode_enable(void); 363 /* disable ADC oversample mode */ 364 void adc_oversample_mode_disable(void); 365 366 #endif /* GD32F3X0_ADC_H */ 367
