1 /*!
2     \file    gd32a50x_trigsel.c
3     \brief   TRIGSEL driver
4 
5     \version 2022-01-30, V1.0.0, firmware for GD32A50x
6 */
7 
8 /*
9     Copyright (c) 2022, GigaDevice Semiconductor Inc.
10 
11     Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13 
14     1. Redistributions of source code must retain the above copyright notice, this
15        list of conditions and the following disclaimer.
16     2. Redistributions in binary form must reproduce the above copyright notice,
17        this list of conditions and the following disclaimer in the documentation
18        and/or other materials provided with the distribution.
19     3. Neither the name of the copyright holder nor the names of its contributors
20        may be used to endorse or promote products derived from this software without
21        specific prior written permission.
22 
23     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34 
35 #include "gd32a50x_trigsel.h"
36 
37 /* TRIGSEL target register redefine */
38 #define TRIGSEL_TARGET_REG(target_periph)          REG32(TRIGSEL + ((uint8_t)(target_periph) & BITS(2, 7)))                                /*!< target peripheral register */
39 #define TRIGSEL_TARGET_PERIPH_SHIFT(target_periph) (((uint8_t)(target_periph) & BITS(0, 1)) << 3)                                          /*!< bit shift in target peripheral register */
40 #define TRIGSEL_TARGET_PERIPH_MASK(target_periph)  ((uint32_t)(TRIGSEL_TARGET_INSEL0 << TRIGSEL_TARGET_PERIPH_SHIFT(target_periph)))       /*!< bit mask in target peripheral register */
41 
42 /*!
43     \brief      set the trigger input signal for target peripheral
44     \param[in]  target_periph: target peripheral value
45                 only one parameter can be selected which is shown as below:
46       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT0: output target peripheral TRIGSEL_OUT0 pin
47       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT1: output target peripheral TRIGSEL_OUT1 pin
48       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT2: output target peripheral TRIGSEL_OUT2 pin
49       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT3: output target peripheral TRIGSEL_OUT3 pin
50       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT4: output target peripheral TRIGSEL_OUT4 pin
51       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT5: output target peripheral TRIGSEL_OUT5 pin
52       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT6: output target peripheral TRIGSEL_OUT6 pin
53       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT7: output target peripheral TRIGSEL_OUT7 pin
54       \arg        TRIGSEL_OUTPUT_ADC0_RTTRG: output target peripheral ADC0_RTTRG
55       \arg        TRIGSEL_OUTPUT_ADC1_RTTRG: output target peripheral ADC1_RTTRG
56       \arg        TRIGSEL_OUTPUT_DAC_EXTRIG: output target peripheral DAC_EXTRIG
57       \arg        TRIGSEL_OUTPUT_TIMER0_ITI0: output target peripheral TIMER0_ITI0
58       \arg        TRIGSEL_OUTPUT_TIMER0_ITI1: output target peripheral TIMER0_ITI1
59       \arg        TRIGSEL_OUTPUT_TIMER0_ITI2: output target peripheral TIMER0_ITI2
60       \arg        TRIGSEL_OUTPUT_TIMER0_ITI3: output target peripheral TIMER0_ITI3
61       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN0
62       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN1
63       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN2
64       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN3
65       \arg        TRIGSEL_OUTPUT_TIMER7_ITI0: output target peripheral TIMER0_ITI0
66       \arg        TRIGSEL_OUTPUT_TIMER7_ITI1: output target peripheral TIMER0_ITI1
67       \arg        TRIGSEL_OUTPUT_TIMER7_ITI2: output target peripheral TIMER0_ITI2
68       \arg        TRIGSEL_OUTPUT_TIMER7_ITI3: output target peripheral TIMER0_ITI3
69       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN0
70       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN1
71       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN2
72       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN3
73       \arg        TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0
74       \arg        TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER0_ITI1
75       \arg        TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER0_ITI2
76       \arg        TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER0_ITI3
77       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN0
78       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN1
79       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN2
80       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN3
81       \arg        TRIGSEL_OUTPUT_TIMER20_ITI0: output target peripheral TIMER0_ITI0
82       \arg        TRIGSEL_OUTPUT_TIMER20_ITI1: output target peripheral TIMER0_ITI1
83       \arg        TRIGSEL_OUTPUT_TIMER20_ITI2: output target peripheral TIMER0_ITI2
84       \arg        TRIGSEL_OUTPUT_TIMER20_ITI3: output target peripheral TIMER0_ITI3
85       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN0
86       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN1
87       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN2
88       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN3
89       \arg        TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0
90       \arg        TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER1_ITI1
91       \arg        TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER1_ITI2
92       \arg        TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER1_ITI3
93       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER0 output target peripheral MFCOM_TRG_TIMER0
94       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER1 output target peripheral MFCOM_TRG_TIMER1
95       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER2 output target peripheral MFCOM_TRG_TIMER2
96       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER3 output target peripheral MFCOM_TRG_TIMER3
97       \arg        TRIGSEL_OUTPUT_CAN0_EX_TIME_TICK output target peripheral CAN0_EX_TIME_TICK
98       \arg        TRIGSEL_OUTPUT_CAN1_EX_TIME_TICK output target peripheral CAN1_EX_TIME_TICK
99     \param[in]  trigger_source: trigger source value
100                 only one parameter can be selected which is shown as below:
101       \arg        TRIGSEL_INPUT_0: trigger input source 0
102       \arg        TRIGSEL_INPUT_1: trigger input source 1
103       \arg        TRIGSEL_INPUT_TRIGSEL_IN0: trigger input source TRIGSEL_IN0 pin
104       \arg        TRIGSEL_INPUT_TRIGSEL_IN1: trigger input source TRIGSEL_IN1 pin
105       \arg        TRIGSEL_INPUT_TRIGSEL_IN2: trigger input source TRIGSEL_IN2 pin
106       \arg        TRIGSEL_INPUT_TRIGSEL_IN3: trigger input source TRIGSEL_IN3 pin
107       \arg        TRIGSEL_INPUT_TRIGSEL_IN4: trigger input source TRIGSEL_IN4 pin
108       \arg        TRIGSEL_INPUT_TRIGSEL_IN5: trigger input source TRIGSEL_IN5 pin
109       \arg        TRIGSEL_INPUT_TRIGSEL_IN6: trigger input source TRIGSEL_IN6 pin
110       \arg        TRIGSEL_INPUT_TRIGSEL_IN7: trigger input source TRIGSEL_IN7 pin
111       \arg        TRIGSEL_INPUT_TRIGSEL_IN8: trigger input source TRIGSEL_IN8 pin
112       \arg        TRIGSEL_INPUT_TRIGSEL_IN9: trigger input source TRIGSEL_IN9 pin
113       \arg        TRIGSEL_INPUT_TRIGSEL_IN10: trigger input source TRIGSEL_IN10 pin
114       \arg        TRIGSEL_INPUT_TRIGSEL_IN11: trigger input source TRIGSEL_IN11 pin
115       \arg        TRIGSEL_INPUT_CMP_OUT: trigger input source CMP_OUT
116       \arg        TRIGSEL_INPUT_LXTAL_TRG: trigger input source LSE_TRG
117       \arg        TRIGSEL_INPUT_TIMER1_CH0: trigger input source timer1 channel 0
118       \arg        TRIGSEL_INPUT_TIMER1_CH1: trigger input source timer1 channel 1
119       \arg        TRIGSEL_INPUT_TIMER1_CH2: trigger input source timer1 channel 2
120       \arg        TRIGSEL_INPUT_TIMER1_CH3: trigger input source timer1 channel 3
121       \arg        TRIGSEL_INPUT_TIMER1_TRGO: trigger input source timer1 TRGO
122       \arg        TRIGSEL_INPUT_TIMER0_CH0: trigger input source timer0 channel 0
123       \arg        TRIGSEL_INPUT_TIMER0_CH1: trigger input source timer0 channel 1
124       \arg        TRIGSEL_INPUT_TIMER0_CH2: trigger input source timer0 channel 2
125       \arg        TRIGSEL_INPUT_TIMER0_CH3: trigger input source timer0 channel 3
126       \arg        TRIGSEL_INPUT_TIMER0_MCH0: trigger input source timer0 channel 0N
127       \arg        TRIGSEL_INPUT_TIMER0_MCH1: trigger input source timer0 channel 1N
128       \arg        TRIGSEL_INPUT_TIMER0_MCH2: trigger input source timer0 channel 2N
129       \arg        TRIGSEL_INPUT_TIMER0_MCH3: trigger input source timer0 channel 3N
130       \arg        TRIGSEL_INPUT_TIMER0_TRGO: trigger input source timer0 TRGO
131       \arg        TRIGSEL_INPUT_TIMER7_CH0: trigger input source timer7 channel 0
132       \arg        TRIGSEL_INPUT_TIMER7_CH1: trigger input source timer7 channel 1
133       \arg        TRIGSEL_INPUT_TIMER7_CH2: trigger input source timer7 channel 2
134       \arg        TRIGSEL_INPUT_TIMER7_CH3: trigger input source timer7 channel 3
135       \arg        TRIGSEL_INPUT_TIMER7_MCH0: trigger input source timer7 channel 0N
136       \arg        TRIGSEL_INPUT_TIMER7_MCH1: trigger input source timer7 channel 1N
137       \arg        TRIGSEL_INPUT_TIMER7_MCH2: trigger input source timer7 channel 2N
138       \arg        TRIGSEL_INPUT_TIMER7_MCH3: trigger input source timer7 channel 3N
139       \arg        TRIGSEL_INPUT_TIMER7_TRGO: trigger input source timer7 TRGO
140       \arg        TRIGSEL_INPUT_TIMER19_CH0: trigger input source timer19 channel 0
141       \arg        TRIGSEL_INPUT_TIMER19_CH1: trigger input source timer19 channel 1
142       \arg        TRIGSEL_INPUT_TIMER19_CH2: trigger input source timer19 channel 2
143       \arg        TRIGSEL_INPUT_TIMER19_CH3: trigger input source timer19 channel 3
144       \arg        TRIGSEL_INPUT_TIMER19_MCH0: trigger input source timer19 channel 0N
145       \arg        TRIGSEL_INPUT_TIMER19_MCH1: trigger input source timer19 channel 1N
146       \arg        TRIGSEL_INPUT_TIMER19_MCH2: trigger input source timer19 channel 2N
147       \arg        TRIGSEL_INPUT_TIMER19_MCH3: trigger input source timer19 channel 3N
148       \arg        TRIGSEL_INPUT_TIMER19_TRGO: trigger input source timer19 TRGO
149       \arg        TRIGSEL_INPUT_TIMER20_CH0: trigger input source timer20 channel 0
150       \arg        TRIGSEL_INPUT_TIMER20_CH1: trigger input source timer20 channel 1
151       \arg        TRIGSEL_INPUT_TIMER20_CH2: trigger input source timer20 channel 2
152       \arg        TRIGSEL_INPUT_TIMER20_CH3: trigger input source timer20 channel 3
153       \arg        TRIGSEL_INPUT_TIMER20_MCH0: trigger input source timer20 channel 0N
154       \arg        TRIGSEL_INPUT_TIMER20_MCH1: trigger input source timer20 channel 1N
155       \arg        TRIGSEL_INPUT_TIMER20_MCH2: trigger input source timer20 channel 2N
156       \arg        TRIGSEL_INPUT_TIMER20_MCH3: trigger input source timer20 channel 3N
157       \arg        TRIGSEL_INPUT_TIMER20_TRGO: trigger input source timer20 TRGO
158       \arg        TRIGSEL_INPUT_TIMER5_TRGO: trigger input source timer5 TRGO
159       \arg        TRIGSEL_INPUT_TIMER6_TRGO: trigger input source timer6 TRGO
160       \arg        TRIGSEL_INPUT_MFCOM_TRIG0: trigger input source MFCOM TRIG0
161       \arg        TRIGSEL_INPUT_MFCOM_TRIG1: trigger input source MFCOM TRIG1
162       \arg        TRIGSEL_INPUT_MFCOM_TRIG2: trigger input source MFCOM TRIG2
163       \arg        TRIGSEL_INPUT_MFCOM_TRIG3: trigger input source MFCOM TRIG3
164       \arg        TRIGSEL_INPUT_RTC_ALARM: trigger input source RTC alarm
165       \arg        TRIGSEL_INPUT_RTC_SECOND: trigger input source RTC second
166       \arg        TRIGSEL_INPUT_TRIGSEL_IN12: trigger input source TRIGSEL_IN12 pin
167       \arg        TRIGSEL_INPUT_TRIGSEL_IN13: trigger input source TRIGSEL_IN13 pin
168     \param[out] none
169     \retval     none
170 */
trigsel_init(trigsel_periph_enum target_periph,trigsel_source_enum trigger_source)171 void trigsel_init(trigsel_periph_enum target_periph, trigsel_source_enum trigger_source)
172 {
173     /* if register write is enabled, set trigger source to target peripheral */
174     if (RESET == trigsel_register_lock_get(target_periph)){
175         TRIGSEL_TARGET_REG(target_periph) &= ~TRIGSEL_TARGET_PERIPH_MASK(target_periph);
176         TRIGSEL_TARGET_REG(target_periph) |= ((uint32_t)trigger_source << TRIGSEL_TARGET_PERIPH_SHIFT(target_periph)) & TRIGSEL_TARGET_PERIPH_MASK(target_periph);
177     }
178 }
179 
180 /*!
181     \brief      get the trigger input signal for target peripheral
182     \param[in]  target_periph: target peripheral value
183                 only one parameter can be selected which is shown as below:
184       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT0: output target peripheral TRIGSEL_OUT0 pin
185       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT1: output target peripheral TRIGSEL_OUT1 pin
186       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT2: output target peripheral TRIGSEL_OUT2 pin
187       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT3: output target peripheral TRIGSEL_OUT3 pin
188       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT4: output target peripheral TRIGSEL_OUT4 pin
189       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT5: output target peripheral TRIGSEL_OUT5 pin
190       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT6: output target peripheral TRIGSEL_OUT6 pin
191       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT7: output target peripheral TRIGSEL_OUT7 pin
192       \arg        TRIGSEL_OUTPUT_ADC0_RTTRG: output target peripheral ADC0_RTTRG
193       \arg        TRIGSEL_OUTPUT_ADC1_RTTRG: output target peripheral ADC1_RTTRG
194       \arg        TRIGSEL_OUTPUT_DAC_EXTRIG: output target peripheral DAC_EXTRIG
195       \arg        TRIGSEL_OUTPUT_TIMER0_ITI0: output target peripheral TIMER0_ITI0
196       \arg        TRIGSEL_OUTPUT_TIMER0_ITI1: output target peripheral TIMER0_ITI1
197       \arg        TRIGSEL_OUTPUT_TIMER0_ITI2: output target peripheral TIMER0_ITI2
198       \arg        TRIGSEL_OUTPUT_TIMER0_ITI3: output target peripheral TIMER0_ITI3
199       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN0
200       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN1
201       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN2
202       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN3
203       \arg        TRIGSEL_OUTPUT_TIMER7_ITI0: output target peripheral TIMER0_ITI0
204       \arg        TRIGSEL_OUTPUT_TIMER7_ITI1: output target peripheral TIMER0_ITI1
205       \arg        TRIGSEL_OUTPUT_TIMER7_ITI2: output target peripheral TIMER0_ITI2
206       \arg        TRIGSEL_OUTPUT_TIMER7_ITI3: output target peripheral TIMER0_ITI3
207       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN0
208       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN1
209       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN2
210       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN3
211       \arg        TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0
212       \arg        TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER0_ITI1
213       \arg        TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER0_ITI2
214       \arg        TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER0_ITI3
215       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN0
216       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN1
217       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN2
218       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN3
219       \arg        TRIGSEL_OUTPUT_TIMER20_ITI0: output target peripheral TIMER0_ITI0
220       \arg        TRIGSEL_OUTPUT_TIMER20_ITI1: output target peripheral TIMER0_ITI1
221       \arg        TRIGSEL_OUTPUT_TIMER20_ITI2: output target peripheral TIMER0_ITI2
222       \arg        TRIGSEL_OUTPUT_TIMER20_ITI3: output target peripheral TIMER0_ITI3
223       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN0
224       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN1
225       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN2
226       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN3
227       \arg        TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0
228       \arg        TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER1_ITI1
229       \arg        TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER1_ITI2
230       \arg        TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER1_ITI3
231       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER0 output target peripheral MFCOM_TRG_TIMER0
232       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER1 output target peripheral MFCOM_TRG_TIMER1
233       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER2 output target peripheral MFCOM_TRG_TIMER2
234       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER3 output target peripheral MFCOM_TRG_TIMER3
235       \arg        TRIGSEL_OUTPUT_CAN0_EX_TIME_TICK output target peripheral CAN0_EX_TIME_TICK
236       \arg        TRIGSEL_OUTPUT_CAN1_EX_TIME_TICK output target peripheral CAN1_EX_TIME_TICK
237     \param[out] none
238     \retval  trigger_source: trigger source value(0~67)
239 */
trigsel_trigger_source_get(trigsel_periph_enum target_periph)240 uint8_t trigsel_trigger_source_get(trigsel_periph_enum target_periph)
241 {
242     uint8_t trigger_source;
243 
244     trigger_source = (uint8_t)((TRIGSEL_TARGET_REG(target_periph) & TRIGSEL_TARGET_PERIPH_MASK(target_periph)) >> TRIGSEL_TARGET_PERIPH_SHIFT(target_periph));
245 
246     return trigger_source;
247 }
248 
249 /*!
250     \brief      lock the trigger register
251     \param[in]  target_periph: target peripheral value
252                 only one parameter can be selected which is shown as below:
253       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT0: output target peripheral TRIGSEL_OUT0 pin
254       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT1: output target peripheral TRIGSEL_OUT1 pin
255       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT2: output target peripheral TRIGSEL_OUT2 pin
256       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT3: output target peripheral TRIGSEL_OUT3 pin
257       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT4: output target peripheral TRIGSEL_OUT4 pin
258       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT5: output target peripheral TRIGSEL_OUT5 pin
259       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT6: output target peripheral TRIGSEL_OUT6 pin
260       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT7: output target peripheral TRIGSEL_OUT7 pin
261       \arg        TRIGSEL_OUTPUT_ADC0_RTTRG: output target peripheral ADC0_RTTRG
262       \arg        TRIGSEL_OUTPUT_ADC1_RTTRG: output target peripheral ADC1_RTTRG
263       \arg        TRIGSEL_OUTPUT_DAC_EXTRIG: output target peripheral DAC_EXTRIG
264       \arg        TRIGSEL_OUTPUT_TIMER0_ITI0: output target peripheral TIMER0_ITI0
265       \arg        TRIGSEL_OUTPUT_TIMER0_ITI1: output target peripheral TIMER0_ITI1
266       \arg        TRIGSEL_OUTPUT_TIMER0_ITI2: output target peripheral TIMER0_ITI2
267       \arg        TRIGSEL_OUTPUT_TIMER0_ITI3: output target peripheral TIMER0_ITI3
268       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN0
269       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN1
270       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN2
271       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN3
272       \arg        TRIGSEL_OUTPUT_TIMER7_ITI0: output target peripheral TIMER0_ITI0
273       \arg        TRIGSEL_OUTPUT_TIMER7_ITI1: output target peripheral TIMER0_ITI1
274       \arg        TRIGSEL_OUTPUT_TIMER7_ITI2: output target peripheral TIMER0_ITI2
275       \arg        TRIGSEL_OUTPUT_TIMER7_ITI3: output target peripheral TIMER0_ITI3
276       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN0
277       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN1
278       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN2
279       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN3
280       \arg        TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0
281       \arg        TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER0_ITI1
282       \arg        TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER0_ITI2
283       \arg        TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER0_ITI3
284       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN0
285       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN1
286       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN2
287       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN3
288       \arg        TRIGSEL_OUTPUT_TIMER20_ITI0: output target peripheral TIMER0_ITI0
289       \arg        TRIGSEL_OUTPUT_TIMER20_ITI1: output target peripheral TIMER0_ITI1
290       \arg        TRIGSEL_OUTPUT_TIMER20_ITI2: output target peripheral TIMER0_ITI2
291       \arg        TRIGSEL_OUTPUT_TIMER20_ITI3: output target peripheral TIMER0_ITI3
292       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN0
293       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN1
294       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN2
295       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN3
296       \arg        TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0
297       \arg        TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER1_ITI1
298       \arg        TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER1_ITI2
299       \arg        TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER1_ITI3
300       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER0 output target peripheral MFCOM_TRG_TIMER0
301       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER1 output target peripheral MFCOM_TRG_TIMER1
302       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER2 output target peripheral MFCOM_TRG_TIMER2
303       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER3 output target peripheral MFCOM_TRG_TIMER3
304       \arg        TRIGSEL_OUTPUT_CAN0_EX_TIME_TICK output target peripheral CAN0_EX_TIME_TICK
305       \arg        TRIGSEL_OUTPUT_CAN1_EX_TIME_TICK output target peripheral CAN1_EX_TIME_TICK
306     \param[out] none
307     \retval     none
308 */
trigsel_register_lock_set(trigsel_periph_enum target_periph)309 void trigsel_register_lock_set(trigsel_periph_enum target_periph)
310 {
311     /*!< lock target peripheral register */
312     TRIGSEL_TARGET_REG(target_periph) |= TRIGSEL_TARGET_LK;
313 }
314 
315 /*!
316     \brief      get the trigger register lock status
317     \param[in]  target_periph: target peripheral value
318                 only one parameter can be selected which is shown as below:
319       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT0: output target peripheral TRIGSEL_OUT0 pin
320       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT1: output target peripheral TRIGSEL_OUT1 pin
321       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT2: output target peripheral TRIGSEL_OUT2 pin
322       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT3: output target peripheral TRIGSEL_OUT3 pin
323       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT4: output target peripheral TRIGSEL_OUT4 pin
324       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT5: output target peripheral TRIGSEL_OUT5 pin
325       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT6: output target peripheral TRIGSEL_OUT6 pin
326       \arg        TRIGSEL_OUTPUT_TRIGSEL_OUT7: output target peripheral TRIGSEL_OUT7 pin
327       \arg        TRIGSEL_OUTPUT_ADC0_RTTRG: output target peripheral ADC0_RTTRG
328       \arg        TRIGSEL_OUTPUT_ADC1_RTTRG: output target peripheral ADC1_RTTRG
329       \arg        TRIGSEL_OUTPUT_DAC_EXTRIG: output target peripheral DAC_EXTRIG
330       \arg        TRIGSEL_OUTPUT_TIMER0_ITI0: output target peripheral TIMER0_ITI0
331       \arg        TRIGSEL_OUTPUT_TIMER0_ITI1: output target peripheral TIMER0_ITI1
332       \arg        TRIGSEL_OUTPUT_TIMER0_ITI2: output target peripheral TIMER0_ITI2
333       \arg        TRIGSEL_OUTPUT_TIMER0_ITI3: output target peripheral TIMER0_ITI3
334       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN0
335       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN1
336       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN2
337       \arg        TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN3
338       \arg        TRIGSEL_OUTPUT_TIMER7_ITI0: output target peripheral TIMER0_ITI0
339       \arg        TRIGSEL_OUTPUT_TIMER7_ITI1: output target peripheral TIMER0_ITI1
340       \arg        TRIGSEL_OUTPUT_TIMER7_ITI2: output target peripheral TIMER0_ITI2
341       \arg        TRIGSEL_OUTPUT_TIMER7_ITI3: output target peripheral TIMER0_ITI3
342       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN0
343       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN1
344       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN2
345       \arg        TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN3
346       \arg        TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0
347       \arg        TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER0_ITI1
348       \arg        TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER0_ITI2
349       \arg        TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER0_ITI3
350       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN0
351       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN1
352       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN2
353       \arg        TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN3
354       \arg        TRIGSEL_OUTPUT_TIMER20_ITI0: output target peripheral TIMER0_ITI0
355       \arg        TRIGSEL_OUTPUT_TIMER20_ITI1: output target peripheral TIMER0_ITI1
356       \arg        TRIGSEL_OUTPUT_TIMER20_ITI2: output target peripheral TIMER0_ITI2
357       \arg        TRIGSEL_OUTPUT_TIMER20_ITI3: output target peripheral TIMER0_ITI3
358       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN0
359       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN1
360       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN2
361       \arg        TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN3
362       \arg        TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0
363       \arg        TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER1_ITI1
364       \arg        TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER1_ITI2
365       \arg        TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER1_ITI3
366       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER0 output target peripheral MFCOM_TRG_TIMER0
367       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER1 output target peripheral MFCOM_TRG_TIMER1
368       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER2 output target peripheral MFCOM_TRG_TIMER2
369       \arg        TRIGSEL_OUTPUT_MFCOM_TRG_TIMER3 output target peripheral MFCOM_TRG_TIMER3
370       \arg        TRIGSEL_OUTPUT_CAN0_EX_TIME_TICK output target peripheral CAN0_EX_TIME_TICK
371       \arg        TRIGSEL_OUTPUT_CAN1_EX_TIME_TICK output target peripheral CAN1_EX_TIME_TICK
372     \param[out] none
373     \retval     SET or RESET
374 */
trigsel_register_lock_get(trigsel_periph_enum target_periph)375 FlagStatus trigsel_register_lock_get(trigsel_periph_enum target_periph)
376 {
377     if(0U != (TRIGSEL_TARGET_REG(target_periph) & TRIGSEL_TARGET_LK)){
378         return SET;
379     }else{
380         return RESET;
381     }
382 }
383