1 /*! 2 \file gd32a50x_timer.h 3 \brief definitions for the TIMER 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_TIMER_H 36 #define GD32A50X_TIMER_H 37 38 #include "gd32a50x.h" 39 40 /* TIMERx(x=0,1,5,6,7,19,20) definitions */ 41 #define TIMER0 (TIMER_BASE + 0x00012C00U) /*!< TIMER0 base address */ 42 #define TIMER1 TIMER_BASE /*!< TIMER1 base address */ 43 #define TIMER5 (TIMER_BASE + 0x00001000U) /*!< TIMER5 base address */ 44 #define TIMER6 (TIMER_BASE + 0x00001400U) /*!< TIMER6 base address */ 45 #define TIMER7 (TIMER_BASE + 0x00013400U) /*!< TIMER7 base address */ 46 #define TIMER19 (TIMER_BASE + 0x00015000U) /*!< TIMER19 base address */ 47 #define TIMER20 (TIMER_BASE + 0x00015400U) /*!< TIMER20 base address */ 48 49 /* registers definitions */ 50 #define TIMER_CTL0(timerx) REG32((timerx) + 0x00000000U) /*!< TIMER control register 0 */ 51 #define TIMER_CTL1(timerx) REG32((timerx) + 0x00000004U) /*!< TIMER control register 1 */ 52 #define TIMER_SMCFG(timerx) REG32((timerx) + 0x00000008U) /*!< TIMER slave mode configuration register */ 53 #define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0000000CU) /*!< TIMER DMA and interrupt enable register */ 54 #define TIMER_INTF(timerx) REG32((timerx) + 0x00000010U) /*!< TIMER interrupt flag register */ 55 #define TIMER_SWEVG(timerx) REG32((timerx) + 0x00000014U) /*!< TIMER software event generation register */ 56 #define TIMER_CHCTL0(timerx) REG32((timerx) + 0x00000018U) /*!< TIMER channel control register 0 */ 57 #define TIMER_CHCTL1(timerx) REG32((timerx) + 0x0000001CU) /*!< TIMER channel control register 1 */ 58 #define TIMER_CHCTL2(timerx) REG32((timerx) + 0x00000020U) /*!< TIMER channel control register 2 */ 59 #define TIMER_CNT(timerx) REG32((timerx) + 0x00000024U) /*!< TIMER counter register */ 60 #define TIMER_PSC(timerx) REG32((timerx) + 0x00000028U) /*!< TIMER prescaler register */ 61 #define TIMER_CAR(timerx) REG32((timerx) + 0x0000002CU) /*!< TIMER counter auto reload register */ 62 #define TIMER_CREP(timerx) REG32((timerx) + 0x00000030U) /*!< TIMER counter repetition register */ 63 #define TIMER_CH0CV(timerx) REG32((timerx) + 0x00000034U) /*!< TIMER channel 0 capture or compare value register */ 64 #define TIMER_CH1CV(timerx) REG32((timerx) + 0x00000038U) /*!< TIMER channel 1 capture or compare value register */ 65 #define TIMER_CH2CV(timerx) REG32((timerx) + 0x0000003CU) /*!< TIMER channel 2 capture or compare value register */ 66 #define TIMER_CH3CV(timerx) REG32((timerx) + 0x00000040U) /*!< TIMER channel 3 capture or compare value register */ 67 #define TIMER_CCHP(timerx) REG32((timerx) + 0x00000044U) /*!< TIMER channel complementary protection register */ 68 #define TIMER_MCHCTL0(timerx) REG32((timerx) + 0x00000048U) /*!< TIMER multi mode channel control register 0 */ 69 #define TIMER_MCHCTL1(timerx) REG32((timerx) + 0x0000004CU) /*!< TIMER multi mode channel control register 1 */ 70 #define TIMER_MCHCTL2(timerx) REG32((timerx) + 0x00000050U) /*!< TIMER multi mode channel control register 2 */ 71 #define TIMER_IRMP(timerx) REG32((timerx) + 0x00000050U) /*!< TIMER channel input remap register (only for TIMER1) */ 72 #define TIMER_MCH0CV(timerx) REG32((timerx) + 0x00000054U) /*!< TIMER multi mode channel 0 capture or compare value register */ 73 #define TIMER_MCH1CV(timerx) REG32((timerx) + 0x00000058U) /*!< TIMER multi mode channel 1 capture or compare value register */ 74 #define TIMER_MCH2CV(timerx) REG32((timerx) + 0x0000005CU) /*!< TIMER multi mode channel 2 capture or compare value register */ 75 #define TIMER_MCH3CV(timerx) REG32((timerx) + 0x00000060U) /*!< TIMER multi mode channel 3 capture or compare value register */ 76 #define TIMER_CH0COMV_ADD(timerx) REG32((timerx) + 0x00000064U) /*!< TIMER channel 0 additional compare value register */ 77 #define TIMER_CH1COMV_ADD(timerx) REG32((timerx) + 0x00000068U) /*!< TIMER channel 1 additional compare value register */ 78 #define TIMER_CH2COMV_ADD(timerx) REG32((timerx) + 0x0000006CU) /*!< TIMER channel 2 additional compare value register */ 79 #define TIMER_CH3COMV_ADD(timerx) REG32((timerx) + 0x00000070U) /*!< TIMER channel 3 additional compare value register */ 80 #define TIMER_CTL2(timerx) REG32((timerx) + 0x00000074U) /*!< TIMER control register 2 */ 81 #define TIMER_BRKCFG(timerx) REG32((timerx) + 0x00000078U) /*!< TIMER break configuration register */ 82 #define TIMER_FCCHP0(timerx) REG32((timerx) + 0x0000007CU) /*!< TIMER free complementary channel protection register 0 */ 83 #define TIMER_FCCHP1(timerx) REG32((timerx) + 0x00000080U) /*!< TIMER free complementary channel protection register 1 */ 84 #define TIMER_FCCHP2(timerx) REG32((timerx) + 0x00000084U) /*!< TIMER free complementary channel protection register 2 */ 85 #define TIMER_FCCHP3(timerx) REG32((timerx) + 0x00000088U) /*!< TIMER free complementary channel protection register 3 */ 86 #define TIMER_DMACFG(timerx) REG32((timerx) + 0x000000E0U) /*!< TIMER DMA configuration register */ 87 #define TIMER_DMATB(timerx) REG32((timerx) + 0x000000E4U) /*!< TIMER DMA transfer buffer register */ 88 #define TIMER_CFG(timerx) REG32((timerx) + 0x000000FCU) /*!< TIMER configuration register */ 89 90 /* bits definitions */ 91 /* TIMER_CTL0 */ 92 #define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ 93 #define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ 94 #define TIMER_CTL0_UPS BIT(2) /*!< update source */ 95 #define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ 96 #define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ 97 #define TIMER_CTL0_CAM BITS(5,6) /*!< counter aligned mode selection */ 98 #define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ 99 #define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ 100 101 /* TIMER_CTL1 */ 102 #define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ 103 #define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ 104 #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ 105 #define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ 106 #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ 107 #define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ 108 #define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ 109 #define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ 110 #define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ 111 #define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ 112 #define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ 113 #define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ 114 #define TIMER_CTL1_ISO3N BIT(15) /*!< idle state of channel 3 complementary output */ 115 116 /* TIMER_SMCFG */ 117 #define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ 118 #define TIMER_SMCFG_TRGS (BITS(4,6)| BIT(31)) /*!< trigger selection */ 119 #define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ 120 #define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ 121 #define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ 122 #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ 123 #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ 124 #define TIMER_SMCFG_TRGS_BIT3 BIT(31) /*!< Trigger selection bit 3 */ 125 126 /* TIMER_DMAINTEN */ 127 #define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ 128 #define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture or compare interrupt enable */ 129 #define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture or compare interrupt enable */ 130 #define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture or compare interrupt enable */ 131 #define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture or compare interrupt enable */ 132 #define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ 133 #define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ 134 #define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ 135 #define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ 136 #define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture or compare DMA request enable */ 137 #define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture or compare DMA request enable */ 138 #define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture or compare DMA request enable */ 139 #define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture or compare DMA request enable */ 140 #define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ 141 #define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ 142 #define TIMER_DMAINTEN_MCH0IE BIT(20) /*!< multi mode channel 0 capture or compare interrupt enable */ 143 #define TIMER_DMAINTEN_MCH1IE BIT(21) /*!< multi mode channel 1 capture or compare interrupt enable */ 144 #define TIMER_DMAINTEN_MCH2IE BIT(22) /*!< multi mode channel 2 capture or compare interrupt enable */ 145 #define TIMER_DMAINTEN_MCH3IE BIT(23) /*!< multi mode channel 3 capture or compare interrupt enable */ 146 #define TIMER_DMAINTEN_MCH0DEN BIT(24) /*!< multi mode channel 0 capture or compare DMA request enable */ 147 #define TIMER_DMAINTEN_MCH1DEN BIT(25) /*!< multi mode channel 1 capture or compare DMA request enable */ 148 #define TIMER_DMAINTEN_MCH2DEN BIT(26) /*!< multi mode channel 2 capture or compare DMA request enable */ 149 #define TIMER_DMAINTEN_MCH3DEN BIT(27) /*!< multi mode channel 3 capture or compare DMA request enable */ 150 #define TIMER_DMAINTEN_CH0COMADDIE BIT(28) /*!< channel 0 additional compare interrupt enable */ 151 #define TIMER_DMAINTEN_CH1COMADDIE BIT(29) /*!< channel 1 additional compare interrupt enable */ 152 #define TIMER_DMAINTEN_CH2COMADDIE BIT(30) /*!< channel 2 additional compare interrupt enable */ 153 #define TIMER_DMAINTEN_CH3COMADDIE BIT(31) /*!< channel 3 additional compare interrupt enable */ 154 155 /* TIMER_INTF */ 156 #define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ 157 #define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture or compare interrupt flag */ 158 #define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture or compare interrupt flag */ 159 #define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture or compare interrupt flag */ 160 #define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture or compare interrupt flag */ 161 #define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ 162 #define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ 163 #define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ 164 #define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ 165 #define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ 166 #define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ 167 #define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ 168 #define TIMER_INTF_MCH0IF BIT(20) /*!< multi mode channel 0 capture or compare interrupt flag */ 169 #define TIMER_INTF_MCH1IF BIT(21) /*!< multi mode channel 1 capture or compare interrupt flag */ 170 #define TIMER_INTF_MCH2IF BIT(22) /*!< multi mode channel 2 capture or compare interrupt flag */ 171 #define TIMER_INTF_MCH3IF BIT(23) /*!< multi mode channel 3 capture or compare interrupt flag */ 172 #define TIMER_INTF_MCH0OF BIT(24) /*!< multi mode channel 0 over capture flag */ 173 #define TIMER_INTF_MCH1OF BIT(25) /*!< multi mode channel 1 over capture flag */ 174 #define TIMER_INTF_MCH2OF BIT(26) /*!< multi mode channel 2 over capture flag */ 175 #define TIMER_INTF_MCH3OF BIT(27) /*!< multi mode channel 3 over capture flag */ 176 #define TIMER_INTF_CH0COMADDIF BIT(28) /*!< channel 0 additional compare interrupt flag */ 177 #define TIMER_INTF_CH1COMADDIF BIT(29) /*!< channel 1 additional compare interrupt flag */ 178 #define TIMER_INTF_CH2COMADDIF BIT(30) /*!< channel 2 additional compare interrupt flag */ 179 #define TIMER_INTF_CH3COMADDIF BIT(31) /*!< channel 3 additional compare interrupt flag */ 180 181 /* TIMER_SWEVG */ 182 #define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ 183 #define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ 184 #define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ 185 #define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ 186 #define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ 187 #define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ 188 #define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ 189 #define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ 190 #define TIMER_SWEVG_MCH0G BIT(20) /*!< multi mode channel 0 capture or compare event generation */ 191 #define TIMER_SWEVG_MCH1G BIT(21) /*!< multi mode channel 1 capture or compare event generation */ 192 #define TIMER_SWEVG_MCH2G BIT(22) /*!< multi mode channel 2 capture or compare event generation */ 193 #define TIMER_SWEVG_MCH3G BIT(23) /*!< multi mode channel 3 capture or compare event generation */ 194 #define TIMER_SWEVG_CH0COMADDG BIT(28) /*!< channel 0 additional compare event generation */ 195 #define TIMER_SWEVG_CH1COMADDG BIT(29) /*!< channel 1 additional compare event generation */ 196 #define TIMER_SWEVG_CH2COMADDG BIT(30) /*!< channel 2 additional compare event generation */ 197 #define TIMER_SWEVG_CH3COMADDG BIT(31) /*!< channel 3 additional compare event generation */ 198 199 /* TIMER_CHCTL0 */ 200 /* output compare mode */ 201 #define TIMER_CHCTL0_CH0MS (TIMER_CHCTL0_CH0MS_BIT2 | BITS(0,1)) /*!< channel 0 mode selection */ 202 #define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ 203 #define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ 204 #define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ 205 #define TIMER_CHCTL0_CH1MS (TIMER_CHCTL0_CH1MS_BIT2 | BITS(8,9)) /*!< channel 1 mode selection */ 206 #define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ 207 #define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ 208 #define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ 209 #define TIMER_CHCTL0_CH0COMADDSEN BIT(28) /*!< channel 0 additional compare output shadow enable */ 210 #define TIMER_CHCTL0_CH1COMADDSEN BIT(29) /*!< channel 1 additional compare output shadow enable */ 211 #define TIMER_CHCTL0_CH0MS_BIT2 BIT(30) /*!< channel 0 I/O mode selection */ 212 #define TIMER_CHCTL0_CH1MS_BIT2 BIT(31) /*!< channel 1 I/O mode selection */ 213 /* input capture mode */ 214 #define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ 215 #define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ 216 #define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ 217 #define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ 218 219 /* TIMER_CHCTL1 */ 220 /* output compare mode */ 221 #define TIMER_CHCTL1_CH2MS (TIMER_CHCTL1_CH2MS_BIT2 | BITS(0,1)) /*!< channel 2 mode selection */ 222 #define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ 223 #define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ 224 #define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ 225 #define TIMER_CHCTL1_CH3MS (TIMER_CHCTL1_CH3MS_BIT2 | BITS(8,9)) /*!< channel 3 mode selection */ 226 #define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ 227 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ 228 #define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ 229 #define TIMER_CHCTL1_CH2COMADDSEN BIT(28) /*!< channel 2 additional compare output shadow enable */ 230 #define TIMER_CHCTL1_CH3COMADDSEN BIT(29) /*!< channel 3 additional compare output shadow enable */ 231 #define TIMER_CHCTL1_CH2MS_BIT2 BIT(30) /*!< channel 2 I/O mode selection */ 232 #define TIMER_CHCTL1_CH3MS_BIT2 BIT(31) /*!< channel 3 I/O mode selection */ 233 /* input capture mode */ 234 #define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ 235 #define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ 236 #define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ 237 #define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ 238 239 /* TIMER_CHCTL2 */ 240 #define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture or compare function enable */ 241 #define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture or compare function polarity */ 242 #define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ 243 #define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ 244 #define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture or compare function enable */ 245 #define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture or compare function polarity */ 246 #define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ 247 #define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ 248 #define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture or compare function enable */ 249 #define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture or compare function polarity */ 250 #define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ 251 #define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ 252 #define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture or compare function enable */ 253 #define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture or compare function polarity */ 254 #define TIMER_CHCTL2_CH3NEN BIT(14) /*!< channel 3 complementary output enable */ 255 #define TIMER_CHCTL2_CH3NP BIT(15) /*!< channel 3 complementary output polarity */ 256 257 #define TIMER_CHCTL2_MCH0EN BIT(2) /*!< multi mode channel 0 capture or compare function enable */ 258 #define TIMER_CHCTL2_MCH0P BIT(3) /*!< multi mode channel 0 complementary output polarity */ 259 #define TIMER_CHCTL2_MCH1EN BIT(6) /*!< multi mode channel 1 capture or compare function enable */ 260 #define TIMER_CHCTL2_MCH1P BIT(7) /*!< multi mode channel 1 complementary output polarity */ 261 #define TIMER_CHCTL2_MCH2EN BIT(10) /*!< multi mode channel 2 capture or compare function enable */ 262 #define TIMER_CHCTL2_MCH2P BIT(11) /*!< multi mode channel 2 complementary output polarity */ 263 #define TIMER_CHCTL2_MCH3EN BIT(14) /*!< multi mode channel 3 capture or compare function enable */ 264 #define TIMER_CHCTL2_MCH3P BIT(15) /*!< multi mode channel 3 complementary output polarity */ 265 266 /* TIMER_CNT */ 267 #define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ 268 269 /* TIMER_PSC */ 270 #define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ 271 272 /* TIMER_CAR */ 273 #define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ 274 275 /* TIMER_CREP */ 276 #define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ 277 278 /* TIMER_CH0CV */ 279 #define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture or compare value of channel 0 */ 280 281 /* TIMER_CH1CV */ 282 #define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture or compare value of channel 1 */ 283 284 /* TIMER_CH2CV */ 285 #define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture or compare value of channel 2 */ 286 287 /* TIMER_CH3CV */ 288 #define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture or compare value of channel 3 */ 289 290 /* TIMER_CCHP */ 291 #define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ 292 #define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ 293 #define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ 294 #define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ 295 #define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ 296 #define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ 297 #define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ 298 #define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ 299 300 /* TIMER_MCHCTL0 */ 301 /* output compare mode */ 302 #define TIMER_MCHCTL0_MCH0MS (BITS(0,1) | BIT(30)) /*!< multi mode channel 0 I/O mode selection */ 303 #define TIMER_MCHCTL0_MCH0COMSEN BIT(3) /*!< multi mode channel 0 output compare shadow enable */ 304 #define TIMER_MCHCTL0_MCH0COMCTL BITS(4,6) /*!< multi mode channel 0 compare output control */ 305 #define TIMER_MCHCTL0_MCH0COMCEN BIT(7) /*!< multi mode channel 0 output compare clear enable */ 306 #define TIMER_MCHCTL0_MCH1MS (BITS(8,9) | BIT(31)) /*!< multi mode channel 1 I/O mode selection */ 307 #define TIMER_MCHCTL0_MCH1COMSEN BIT(11) /*!< multi mode channel 1 output compare shadow enable */ 308 #define TIMER_MCHCTL0_MCH1COMCTL BITS(12,14) /*!< multi mode channel 1 compare output control */ 309 #define TIMER_MCHCTL0_MCH1COMCEN BIT(15) /*!< multi mode channel 1 output compare clear enable */ 310 /* input capture mode */ 311 #define TIMER_MCHCTL0_MCH0CAPPSC BITS(2,3) /*!< multi mode channel 0 input capture prescaler */ 312 #define TIMER_MCHCTL0_MCH0CAPFLT BITS(4,7) /*!< multi mode channel 0 input capture filter control */ 313 #define TIMER_MCHCTL0_MCH1CAPPSC BITS(10,11) /*!< multi mode channel 1 input capture prescaler */ 314 #define TIMER_MCHCTL0_MCH1CAPFLT BITS(12,15) /*!< multi mode channel 1 input capture filter control */ 315 316 /* TIMER_MCHCTL1 */ 317 /* output compare mode */ 318 #define TIMER_MCHCTL1_MCH2MS (BITS(0,1) | BIT(30)) /*!< multi mode channel 2 I/O mode selection */ 319 #define TIMER_MCHCTL1_MCH2COMSEN BIT(3) /*!< multi mode channel 2 output compare shadow enable */ 320 #define TIMER_MCHCTL1_MCH2COMCTL BITS(4,6) /*!< multi mode channel 2 compare output control */ 321 #define TIMER_MCHCTL1_MCH2COMCEN BIT(7) /*!< multi mode channel 2 output compare clear enable */ 322 #define TIMER_MCHCTL1_MCH3MS (BITS(8,9) | BIT(31)) /*!< multi mode channel 3 I/O mode selection */ 323 #define TIMER_MCHCTL1_MCH3COMSEN BIT(11) /*!< multi mode channel 3 output compare shadow enable */ 324 #define TIMER_MCHCTL1_MCH3COMCTL BITS(12,14) /*!< multi mode channel 3 compare output control */ 325 #define TIMER_MCHCTL1_MCH3COMCEN BIT(15) /*!< multi mode channel 3 output compare clear enable */ 326 /* input capture mode */ 327 #define TIMER_MCHCTL1_MCH2CAPPSC BITS(2,3) /*!< multi mode channel 2 input capture prescaler */ 328 #define TIMER_MCHCTL1_MCH2CAPFLT BITS(4,7) /*!< multi mode channel 2 input capture filter control */ 329 #define TIMER_MCHCTL1_MCH3CAPPSC BITS(10,11) /*!< multi mode channel 3 input capture prescaler */ 330 #define TIMER_MCHCTL1_MCH3CAPFLT BITS(12,15) /*!< multi mode channel 3 input capture filter control */ 331 332 /* TIMER_MCHCTL2 */ 333 #define TIMER_MCHCTL2_MCH0FP BITS(0,1) /*!< multi mode channel 0 capture or compare function polarity */ 334 #define TIMER_MCHCTL2_MCH1FP BITS(2,3) /*!< multi mode channel 1 capture or compare function polarity */ 335 #define TIMER_MCHCTL2_MCH2FP BITS(4,5) /*!< multi mode channel 2 capture or compare function polarity */ 336 #define TIMER_MCHCTL2_MCH3FP BITS(6,7) /*!< multi mode channel 3 capture or compare function polarity */ 337 338 /* TIMER_IRMP */ 339 #define TIMER1_IRMP_CI0_RMP BITS(0,1) /*!< TIMER1 channel 0 input remap */ 340 341 /* TIMER_MCH0CV */ 342 #define TIMER_MCH0CV_MCH0VAL BITS(0,15) /*!< 16 bit capture or compare value of multi mode channel 0 */ 343 344 /* TIMER_MCH1CV */ 345 #define TIMER_MCH1CV_MCH1VAL BITS(0,15) /*!< 16 bit capture or compare value of multi mode channel 1 */ 346 347 /* TIMER_MCH2CV */ 348 #define TIMER_MCH2CV_MCH2VAL BITS(0,15) /*!< 16 bit capture or compare value of multi mode channel 2 */ 349 350 /* TIMER_MCH3CV */ 351 #define TIMER_MCH3CV_MCH3VAL BITS(0,15) /*!< 16 bit capture or compare value of multi mode channel 3 */ 352 353 /* TIMER_CH0COMV_ADD */ 354 #define TIMER_CH0COMV_ADD_CH0COMVAL BITS(0,15) /*!< additional compare value of channel 0 */ 355 356 /* TIMER_CH1COMV_ADD */ 357 #define TIMER_CH1COMV_ADD_CH0COMVAL BITS(0,15) /*!< additional compare value of channel 1 */ 358 359 /* TIMER_CH2COMV_ADD */ 360 #define TIMER_CH2COMV_ADD_CH0COMVAL BITS(0,15) /*!< additional compare value of channel 2 */ 361 362 /* TIMER_CH3COMV_ADD */ 363 #define TIMER_CH3COMV_ADD_CH0COMVAL BITS(0,15) /*!< additional compare value of channel 3 */ 364 365 /* TIMER_CTL2 */ 366 #define TIMER_CTL2_DTIENCH0 BIT(0) /*!< dead time inserted enable for channel 0 and channel 0N */ 367 #define TIMER_CTL2_DTIENCH1 BIT(1) /*!< dead time inserted enable for channel 1 and channel 1N */ 368 #define TIMER_CTL2_DTIENCH2 BIT(2) /*!< dead time inserted enable for channel 2 and channel 2N */ 369 #define TIMER_CTL2_DTIENCH3 BIT(3) /*!< dead time inserted enable for channel 3 and channel 3N */ 370 #define TIMER_CTL2_BRKENCH0 BIT(4) /*!< break control enable for channel 0 and multi mode channel 0 */ 371 #define TIMER_CTL2_BRKENCH1 BIT(5) /*!< break control enable for channel 1 and multi mode channel 1 */ 372 #define TIMER_CTL2_BRKENCH2 BIT(6) /*!< break control enable for channel 2 and multi mode channel 2 */ 373 #define TIMER_CTL2_BRKENCH3 BIT(7) /*!< break control enable for channel 3 and multi mode channel 3 */ 374 #define TIMER_CTL2_CH0OMPSEL BITS(8,9) /*!< channel 0 output march pulse select */ 375 #define TIMER_CTL2_CH1OMPSEL BITS(10,11) /*!< channel 1 output march pulse select */ 376 #define TIMER_CTL2_CH2OMPSEL BITS(12,13) /*!< channel 2 output march pulse select */ 377 #define TIMER_CTL2_CH3OMPSEL BITS(14,15) /*!< channel 3 output march pulse select */ 378 #define TIMER_CTL2_MCH0MSEL BITS(20,21) /*!< multi mode channel 0 mode select */ 379 #define TIMER_CTL2_MCH1MSEL BITS(22,23) /*!< multi mode channel 1 mode select */ 380 #define TIMER_CTL2_MCH2MSEL BITS(24,25) /*!< multi mode channel 2 mode select */ 381 #define TIMER_CTL2_MCH3MSEL BITS(26,27) /*!< multi mode channel 3 mode select */ 382 #define TIMER_CTL2_CH0CPWMEN BIT(28) /*!< channel 0 composite PWM mode enable */ 383 #define TIMER_CTL2_CH1CPWMEN BIT(29) /*!< channel 1 composite PWM mode enable */ 384 #define TIMER_CTL2_CH2CPWMEN BIT(30) /*!< channel 2 composite PWM mode enable */ 385 #define TIMER_CTL2_CH3CPWMEN BIT(31) /*!< channel 3 composite PWM mode enable */ 386 387 /* TIMER_BRKCFG */ 388 #define TIMER_BRKCFG_BRK0F BITS(0,3) /*!< BRKIN0 input signal filter */ 389 #define TIMER_BRKCFG_BRK1F BITS(4,7) /*!< BRKIN1 input signal filter */ 390 #define TIMER_BRKCFG_BRK2F BITS(8,11) /*!< BRKIN2 input signal filter */ 391 #define TIMER_BRKCFG_BRK3F BITS(12,15) /*!< BRKIN3 input signal filter */ 392 #define TIMER_BRKCFG_BRK0EN BIT(24) /*!< BRKIN0 input signal enable */ 393 #define TIMER_BRKCFG_BRK0P BIT(25) /*!< BRKIN0 input signal polarity */ 394 #define TIMER_BRKCFG_BRK1EN BIT(26) /*!< BRKIN1 input signal enable */ 395 #define TIMER_BRKCFG_BRK1P BIT(27) /*!< BRKIN1 input signal polarity */ 396 #define TIMER_BRKCFG_BRK2EN BIT(28) /*!< BRKIN2 input signal enable */ 397 #define TIMER_BRKCFG_BRK2P BIT(29) /*!< BRKIN2 input signal polarity */ 398 #define TIMER_BRKCFG_BRK3EN BIT(30) /*!< BRKIN3 input signal enable */ 399 #define TIMER_BRKCFG_BRK3P BIT(31) /*!< BRKIN3 input signal polarity */ 400 401 /* TIMER_FCCHP0 */ 402 #define TIMER_FCCHP0_DTCFG BITS(0,7) /*!< dead time configure */ 403 #define TIMER_FCCHP0_IOS BIT(10) /*!< idle mode off-state configure */ 404 #define TIMER_FCCHP0_ROS BIT(11) /*!< run mode off-state configure */ 405 #define TIMER_FCCHP0_FCCHP0EN BIT(31) /*!< free complementary channel protection register 0 enable */ 406 407 /* TIMER_FCCHP1 */ 408 #define TIMER_FCCHP1_DTCFG BITS(0,7) /*!< dead time configure */ 409 #define TIMER_FCCHP1_IOS BIT(10) /*!< idle mode off-state configure */ 410 #define TIMER_FCCHP1_ROS BIT(11) /*!< run mode off-state configure */ 411 #define TIMER_FCCHP1_FCCHP1EN BIT(31) /*!< free complementary channel protection register 1 enable */ 412 413 /* TIMER_FCCHP2 */ 414 #define TIMER_FCCHP2_DTCFG BITS(0,7) /*!< dead time configure */ 415 #define TIMER_FCCHP2_IOS BIT(10) /*!< idle mode off-state configure */ 416 #define TIMER_FCCHP2_ROS BIT(11) /*!< run mode off-state configure */ 417 #define TIMER_FCCHP2_FCCHP2EN BIT(31) /*!< free complementary channel protection register 2 enable */ 418 419 /* TIMER_FCCHP3 */ 420 #define TIMER_FCCHP3_DTCFG BITS(0,7) /*!< dead time configure */ 421 #define TIMER_FCCHP3_IOS BIT(10) /*!< idle mode off-state configure */ 422 #define TIMER_FCCHP3_ROS BIT(11) /*!< run mode off-state configure */ 423 #define TIMER_FCCHP3_FCCHP3EN BIT(31) /*!< free complementary channel protection register 3 enable */ 424 425 /* TIMER_DMACFG */ 426 #define TIMER_DMACFG_DMATA BITS(0,5) /*!< DMA transfer access start address */ 427 #define TIMER_DMACFG_DMATC BITS(8,13) /*!< DMA transfer count */ 428 429 /* TIMER_DMATB */ 430 #define TIMER_DMATB_DMATB BITS(0,31) /*!< DMA transfer buffer address */ 431 432 /* TIMER_CFG */ 433 #define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ 434 #define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ 435 436 /* constants definitions */ 437 /* TIMER init parameter struct definitions */ 438 typedef struct { 439 uint16_t prescaler; /*!< prescaler value */ 440 uint16_t alignedmode; /*!< aligned mode */ 441 uint16_t counterdirection; /*!< counter direction */ 442 uint32_t period; /*!< period value */ 443 uint16_t clockdivision; /*!< clock division value */ 444 uint8_t repetitioncounter; /*!< the counter repetition value */ 445 } timer_parameter_struct; 446 447 /* break parameter struct definitions */ 448 typedef struct { 449 uint16_t runoffstate; /*!< run mode off-state */ 450 uint16_t ideloffstate; /*!< idle mode off-state */ 451 uint16_t deadtime; /*!< dead time */ 452 uint16_t breakpolarity; /*!< break polarity */ 453 uint16_t outputautostate; /*!< output automatic enable */ 454 uint16_t protectmode; /*!< complementary register protect control */ 455 uint16_t breakstate; /*!< break enable */ 456 } timer_break_parameter_struct; 457 458 /* channel output parameter struct definitions */ 459 typedef struct { 460 uint16_t outputstate; /*!< channel output state */ 461 uint16_t outputnstate; /*!< channel complementary output state */ 462 uint16_t ocpolarity; /*!< channel output polarity */ 463 uint16_t ocnpolarity; /*!< channel complementary output polarity */ 464 uint16_t ocidlestate; /*!< idle state of channel output */ 465 uint16_t ocnidlestate; /*!< idle state of channel complementary output */ 466 } timer_oc_parameter_struct; 467 468 /* multi mode channel output parameter struct definitions */ 469 typedef struct { 470 uint16_t outputmode; /*!< multi mode channel output mode selection */ 471 uint16_t outputstate; /*!< multi mode channel output state */ 472 uint16_t ocpolarity; /*!< multi mode channel output polarity */ 473 } timer_omc_parameter_struct; 474 475 /* channel input parameter struct definitions */ 476 typedef struct { 477 uint16_t icpolarity; /*!< channel input polarity */ 478 uint16_t icselection; /*!< channel input mode selection */ 479 uint16_t icprescaler; /*!< channel input capture prescaler */ 480 uint16_t icfilter; /*!< channel input capture filter control */ 481 } timer_ic_parameter_struct; 482 483 /* break external input parameter struct definitions */ 484 typedef struct { 485 uint32_t filter; /*!< break external input filter */ 486 uint32_t enable; /*!< break external input enable */ 487 uint32_t polarity; /*!< break external input polarity */ 488 } timer_break_ext_input_struct; 489 490 /* channel free complementary parameter struct definitions */ 491 typedef struct { 492 uint32_t freecomstate; /*!< free complementary channel protection enable */ 493 uint32_t runoffstate; /*!< run mode off-state */ 494 uint32_t ideloffstate; /*!< idle mode off-state */ 495 uint32_t deadtime; /*!< dead time */ 496 } timer_free_complementary_parameter_struct; 497 498 /* TIMER interrupt enable or disable */ 499 #define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ 500 #define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 capture or compare interrupt */ 501 #define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 capture or compare interrupt */ 502 #define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 capture or compare interrupt */ 503 #define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 capture or compare interrupt */ 504 #define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ 505 #define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ 506 #define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ 507 #define TIMER_INT_MCH0 TIMER_DMAINTEN_MCH0IE /*!< multi mode channel 0 capture or compare interrupt */ 508 #define TIMER_INT_MCH1 TIMER_DMAINTEN_MCH1IE /*!< multi mode channel 1 capture or compare interrupt */ 509 #define TIMER_INT_MCH2 TIMER_DMAINTEN_MCH2IE /*!< multi mode channel 2 capture or compare interrupt */ 510 #define TIMER_INT_MCH3 TIMER_DMAINTEN_MCH3IE /*!< multi mode channel 3 capture or compare interrupt */ 511 #define TIMER_INT_CH0COMADD TIMER_DMAINTEN_CH0COMADDIE /*!< channel 0 additional compare interrupt */ 512 #define TIMER_INT_CH1COMADD TIMER_DMAINTEN_CH1COMADDIE /*!< channel 1 additional compare interrupt */ 513 #define TIMER_INT_CH2COMADD TIMER_DMAINTEN_CH2COMADDIE /*!< channel 2 additional compare interrupt */ 514 #define TIMER_INT_CH3COMADD TIMER_DMAINTEN_CH3COMADDIE /*!< channel 3 additional compare interrupt */ 515 516 /* TIMER interrupt flag */ 517 #define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt flag */ 518 #define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt flag */ 519 #define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt flag */ 520 #define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt flag */ 521 #define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt flag */ 522 #define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ 523 #define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt flag */ 524 #define TIMER_INT_FLAG_BRK TIMER_INT_BRK /*!< break interrupt flag */ 525 #define TIMER_INT_FLAG_MCH0 TIMER_INT_MCH0 /*!< multi mode channel 0 capture or compare interrupt flag */ 526 #define TIMER_INT_FLAG_MCH1 TIMER_INT_MCH1 /*!< multi mode channel 1 capture or compare interrupt flag */ 527 #define TIMER_INT_FLAG_MCH2 TIMER_INT_MCH2 /*!< multi mode channel 2 capture or compare interrupt flag */ 528 #define TIMER_INT_FLAG_MCH3 TIMER_INT_MCH3 /*!< multi mode channel 3 capture or compare interrupt flag */ 529 #define TIMER_INT_FLAG_CH0COMADD TIMER_INT_CH0COMADD /*!< channel 0 additional compare interrupt flag */ 530 #define TIMER_INT_FLAG_CH1COMADD TIMER_INT_CH1COMADD /*!< channel 1 additional compare interrupt flag */ 531 #define TIMER_INT_FLAG_CH2COMADD TIMER_INT_CH2COMADD /*!< channel 2 additional compare interrupt flag */ 532 #define TIMER_INT_FLAG_CH3COMADD TIMER_INT_CH3COMADD /*!< channel 3 additional compare interrupt flag */ 533 534 /* TIMER flag */ 535 #define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ 536 #define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 capture or compare flag */ 537 #define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 capture or compare flag */ 538 #define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 capture or compare flag */ 539 #define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 capture or compare flag */ 540 #define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ 541 #define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ 542 #define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ 543 #define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ 544 #define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ 545 #define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ 546 #define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ 547 #define TIMER_FLAG_MCH0 TIMER_INTF_MCH0IF /*!< multi mode channel 0 capture or compare flag */ 548 #define TIMER_FLAG_MCH1 TIMER_INTF_MCH1IF /*!< multi mode channel 1 capture or compare flag */ 549 #define TIMER_FLAG_MCH2 TIMER_INTF_MCH2IF /*!< multi mode channel 2 capture or compare flag */ 550 #define TIMER_FLAG_MCH3 TIMER_INTF_MCH3IF /*!< multi mode channel 3 capture or compare flag */ 551 #define TIMER_FLAG_MCH0O TIMER_INTF_MCH0OF /*!< multi mode channel 0 overcapture flag */ 552 #define TIMER_FLAG_MCH1O TIMER_INTF_MCH1OF /*!< multi mode channel 1 overcapture flag */ 553 #define TIMER_FLAG_MCH2O TIMER_INTF_MCH2OF /*!< multi mode channel 2 overcapture flag */ 554 #define TIMER_FLAG_MCH3O TIMER_INTF_MCH3OF /*!< multi mode channel 3 overcapture flag */ 555 #define TIMER_FLAG_CH0COMADD TIMER_INTF_CH0COMADDIF /*!< channel 0 additional compare interrupt flag */ 556 #define TIMER_FLAG_CH1COMADD TIMER_INTF_CH1COMADDIF /*!< channel 1 additional compare interrupt flag */ 557 #define TIMER_FLAG_CH2COMADD TIMER_INTF_CH2COMADDIF /*!< channel 2 additional compare interrupt flag */ 558 #define TIMER_FLAG_CH3COMADD TIMER_INTF_CH3COMADDIF /*!< channel 3 additional compare interrupt flag */ 559 560 /* TIMER DMA source */ 561 #define TIMER_DMA_UPD TIMER_DMAINTEN_UPDEN /*!< update DMA request */ 562 #define TIMER_DMA_CH0D TIMER_DMAINTEN_CH0DEN /*!< channel 0 capture or compare DMA request */ 563 #define TIMER_DMA_CH1D TIMER_DMAINTEN_CH1DEN /*!< channel 1 capture or compare DMA request */ 564 #define TIMER_DMA_CH2D TIMER_DMAINTEN_CH2DEN /*!< channel 2 capture or compare DMA request */ 565 #define TIMER_DMA_CH3D TIMER_DMAINTEN_CH3DEN /*!< channel 3 capture or compare DMA request */ 566 #define TIMER_DMA_CMTD TIMER_DMAINTEN_CMTDEN /*!< commutation DMA request */ 567 #define TIMER_DMA_TRGD TIMER_DMAINTEN_TRGDEN /*!< trigger DMA request */ 568 #define TIMER_DMA_MCH0D TIMER_DMAINTEN_MCH0DEN /*!< multi mode channel 0 capture or compare DMA request */ 569 #define TIMER_DMA_MCH1D TIMER_DMAINTEN_MCH1DEN /*!< multi mode channel 1 capture or compare DMA request */ 570 #define TIMER_DMA_MCH2D TIMER_DMAINTEN_MCH2DEN /*!< multi mode channel 2 capture or compare DMA request */ 571 #define TIMER_DMA_MCH3D TIMER_DMAINTEN_MCH3DEN /*!< multi mode channel 3 capture or compare DMA request */ 572 573 /* channel DMA request source selection */ 574 #define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ 575 #define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ 576 577 /* DMA access base address */ 578 #define DMACFG_DMATA(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) 579 #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ 580 #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ 581 #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ 582 #define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ 583 #define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ 584 #define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ 585 #define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ 586 #define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ 587 #define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ 588 #define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ 589 #define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ 590 #define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ 591 #define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ 592 #define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ 593 #define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ 594 #define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ 595 #define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ 596 #define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ 597 #define TIMER_DMACFG_DMATA_MCHCTL0 DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_MCHCTL0 */ 598 #define TIMER_DMACFG_DMATA_MCHCTL1 DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_MCHCTL1 */ 599 #define TIMER_DMACFG_DMATA_MCHCTL2 DMACFG_DMATA(20) /*!< DMA transfer address is TIMER_MCHCTL2 */ 600 #define TIMER_DMACFG_DMATA_MCH0CV DMACFG_DMATA(21) /*!< DMA transfer address is TIMER_MCH0CV */ 601 #define TIMER_DMACFG_DMATA_MCH1CV DMACFG_DMATA(22) /*!< DMA transfer address is TIMER_MCH1CV */ 602 #define TIMER_DMACFG_DMATA_MCH2CV DMACFG_DMATA(23) /*!< DMA transfer address is TIMER_MCH2CV */ 603 #define TIMER_DMACFG_DMATA_MCH3CV DMACFG_DMATA(24) /*!< DMA transfer address is TIMER_MCH3CV */ 604 #define TIMER_DMACFG_DMATA_CH0COMV_ADD DMACFG_DMATA(25) /*!< DMA transfer address is TIMER_CH0COMV_ADD */ 605 #define TIMER_DMACFG_DMATA_CH1COMV_ADD DMACFG_DMATA(26) /*!< DMA transfer address is TIMER_CH1COMV_ADD */ 606 #define TIMER_DMACFG_DMATA_CH2COMV_ADD DMACFG_DMATA(27) /*!< DMA transfer address is TIMER_CH2COMV_ADD */ 607 #define TIMER_DMACFG_DMATA_CH3COMV_ADD DMACFG_DMATA(28) /*!< DMA transfer address is TIMER_CH3COMV_ADD */ 608 #define TIMER_DMACFG_DMATA_CTL2 DMACFG_DMATA(29) /*!< DMA transfer address is TIMER_CTL2 */ 609 #define TIMER_DMACFG_DMATA_BRKCFG DMACFG_DMATA(30) /*!< DMA transfer address is TIMER_BRKCFG */ 610 #define TIMER_DMACFG_DMATA_FCCHP0 DMACFG_DMATA(31) /*!< DMA transfer address is TIMER_FCCHP0 */ 611 #define TIMER_DMACFG_DMATA_FCCHP1 DMACFG_DMATA(32) /*!< DMA transfer address is TIMER_FCCHP1 */ 612 #define TIMER_DMACFG_DMATA_FCCHP2 DMACFG_DMATA(33) /*!< DMA transfer address is TIMER_FCCHP2 */ 613 #define TIMER_DMACFG_DMATA_FCCHP3 DMACFG_DMATA(34) /*!< DMA transfer address is TIMER_FCCHP3 */ 614 615 /* DMA access burst length */ 616 #define DMACFG_DMATC(regval) (BITS(8,13) & ((uint32_t)(regval) << 8U)) 617 #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ 618 #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ 619 #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ 620 #define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ 621 #define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ 622 #define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ 623 #define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ 624 #define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ 625 #define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ 626 #define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ 627 #define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ 628 #define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ 629 #define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ 630 #define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ 631 #define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ 632 #define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ 633 #define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ 634 #define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ 635 #define TIMER_DMACFG_DMATC_19TRANSFER DMACFG_DMATC(18) /*!< DMA transfer 19 times */ 636 #define TIMER_DMACFG_DMATC_20TRANSFER DMACFG_DMATC(19) /*!< DMA transfer 20 times */ 637 #define TIMER_DMACFG_DMATC_21TRANSFER DMACFG_DMATC(20) /*!< DMA transfer 21 times */ 638 #define TIMER_DMACFG_DMATC_22TRANSFER DMACFG_DMATC(21) /*!< DMA transfer 22 times */ 639 #define TIMER_DMACFG_DMATC_23TRANSFER DMACFG_DMATC(22) /*!< DMA transfer 23 times */ 640 #define TIMER_DMACFG_DMATC_24TRANSFER DMACFG_DMATC(23) /*!< DMA transfer 24 times */ 641 #define TIMER_DMACFG_DMATC_25TRANSFER DMACFG_DMATC(24) /*!< DMA transfer 25 times */ 642 #define TIMER_DMACFG_DMATC_26TRANSFER DMACFG_DMATC(25) /*!< DMA transfer 26 times */ 643 #define TIMER_DMACFG_DMATC_27TRANSFER DMACFG_DMATC(26) /*!< DMA transfer 27 times */ 644 #define TIMER_DMACFG_DMATC_28TRANSFER DMACFG_DMATC(27) /*!< DMA transfer 28 times */ 645 #define TIMER_DMACFG_DMATC_29TRANSFER DMACFG_DMATC(28) /*!< DMA transfer 29 times */ 646 #define TIMER_DMACFG_DMATC_30TRANSFER DMACFG_DMATC(29) /*!< DMA transfer 30 times */ 647 #define TIMER_DMACFG_DMATC_31TRANSFER DMACFG_DMATC(30) /*!< DMA transfer 31 times */ 648 #define TIMER_DMACFG_DMATC_32TRANSFER DMACFG_DMATC(31) /*!< DMA transfer 32 times */ 649 #define TIMER_DMACFG_DMATC_33TRANSFER DMACFG_DMATC(32) /*!< DMA transfer 33 times */ 650 #define TIMER_DMACFG_DMATC_34TRANSFER DMACFG_DMATC(33) /*!< DMA transfer 34 times */ 651 #define TIMER_DMACFG_DMATC_35TRANSFER DMACFG_DMATC(34) /*!< DMA transfer 35 times */ 652 653 /* TIMER software event generation source */ 654 #define TIMER_EVENT_SRC_UPG TIMER_SWEVG_UPG /*!< update event generation */ 655 #define TIMER_EVENT_SRC_CH0G TIMER_SWEVG_CH0G /*!< channel 0 capture or compare event generation */ 656 #define TIMER_EVENT_SRC_CH1G TIMER_SWEVG_CH1G /*!< channel 1 capture or compare event generation */ 657 #define TIMER_EVENT_SRC_CH2G TIMER_SWEVG_CH2G /*!< channel 2 capture or compare event generation */ 658 #define TIMER_EVENT_SRC_CH3G TIMER_SWEVG_CH3G /*!< channel 3 capture or compare event generation */ 659 #define TIMER_EVENT_SRC_CMTG TIMER_SWEVG_CMTG /*!< channel commutation event generation */ 660 #define TIMER_EVENT_SRC_TRGG TIMER_SWEVG_TRGG /*!< trigger event generation */ 661 #define TIMER_EVENT_SRC_BRKG TIMER_SWEVG_BRKG /*!< break event generation */ 662 #define TIMER_EVENT_SRC_MCH0G TIMER_SWEVG_MCH0G /*!< multi mode channel 0 capture or compare event generation */ 663 #define TIMER_EVENT_SRC_MCH1G TIMER_SWEVG_MCH1G /*!< multi mode channel 1 capture or compare event generation */ 664 #define TIMER_EVENT_SRC_MCH2G TIMER_SWEVG_MCH2G /*!< multi mode channel 2 capture or compare event generation */ 665 #define TIMER_EVENT_SRC_MCH3G TIMER_SWEVG_MCH3G /*!< multi mode channel 3 capture or compare event generation */ 666 #define TIMER_EVENT_SRC_CH0COMADDG TIMER_SWEVG_CH0COMADDG /*!< channel 0 additional compare event generation */ 667 #define TIMER_EVENT_SRC_CH1COMADDG TIMER_SWEVG_CH1COMADDG /*!< channel 1 additional compare event generation */ 668 #define TIMER_EVENT_SRC_CH2COMADDG TIMER_SWEVG_CH2COMADDG /*!< channel 2 additional compare event generation */ 669 #define TIMER_EVENT_SRC_CH3COMADDG TIMER_SWEVG_CH3COMADDG /*!< channel 3 additional compare event generation */ 670 671 /* center-aligned mode selection */ 672 #define CTL0_CAM(regval) ((uint16_t)(BITS(5,6) & ((uint32_t)(regval) << 5U))) 673 #define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ 674 #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ 675 #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ 676 #define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ 677 678 /* TIMER prescaler reload mode */ 679 #define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ 680 #define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ 681 682 /* count direction */ 683 #define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ 684 #define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ 685 686 /* specify division ratio between TIMER clock and dead-time and sampling clock */ 687 #define CTL0_CKDIV(regval) ((uint16_t)(BITS(8,9) & ((uint32_t)(regval) << 8U))) 688 #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1, fDTS = fTIMER_CK */ 689 #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2, fDTS = fTIMER_CK/2 */ 690 #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS = fTIMER_CK/4 */ 691 692 /* single pulse mode */ 693 #define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ 694 #define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ 695 696 /* update source */ 697 #define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ 698 #define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ 699 700 /* run mode off-state configure */ 701 #define TIMER_ROS_STATE_ENABLE ((uint32_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/MCHx) are enabled, with relationship to CHxEN/CHxNEN bits */ 702 #define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is set, the channel output signals(CHx_O/MCHx) are disabled */ 703 704 /* idle mode off-state configure */ 705 #define TIMER_IOS_STATE_ENABLE ((uint32_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, the channel output signals(CHx_O/MCHx) are enabled, with relationship to CHxEN/CHxNEN bits */ 706 #define TIMER_IOS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/MCHx) are disabled */ 707 708 /* break input polarity */ 709 #define TIMER_BREAK_POLARITY_LOW ((uint32_t)0x00000000U) /*!< break input polarity is low */ 710 #define TIMER_BREAK_POLARITY_HIGH ((uint32_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ 711 712 /* output automatic enable */ 713 #define TIMER_OUTAUTO_ENABLE ((uint32_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ 714 #define TIMER_OUTAUTO_DISABLE ((uint32_t)0x00000000U) /*!< output automatic disable */ 715 716 /* complementary register protect control */ 717 #define CCHP_PROT(regval) ((uint16_t)(BITS(8,9) & ((uint32_t)(regval) << 8U))) 718 #define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ 719 #define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ 720 #define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ 721 #define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ 722 723 /* break input enable */ 724 #define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ 725 #define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ 726 727 /* free complementary channel protection configure */ 728 #define TIMER_FCCHP_STATE_ENABLE ((uint32_t)TIMER_FCCHP0_FCCHP0EN) /*!< free complementary channel protection enable */ 729 #define TIMER_FCCHP_STATE_DISABLE ((uint32_t)0x00000000U) /*!< free complementary channel protection disable */ 730 731 /* TIMER external break input source */ 732 #define TIMER_BREAKINPUT_BRK0 ((uint16_t)0x0000U) /*!< TIMER break external input 0 */ 733 #define TIMER_BREAKINPUT_BRK1 ((uint16_t)0x0001U) /*!< TIMER break external input 1 */ 734 #define TIMER_BREAKINPUT_BRK2 ((uint16_t)0x0002U) /*!< TIMER break external input 2 */ 735 #define TIMER_BREAKINPUT_BRK3 ((uint16_t)0x0003U) /*!< TIMER break external input 3 */ 736 737 /* TIMER Break external input polarity*/ 738 #define TIMER_BRKIN_POLARITY_LOW ((uint16_t)0x0000U) /*!< TIMER break external input polarity is active low */ 739 #define TIMER_BRKIN_POLARITY_HIGH ((uint16_t)0x0001U) /*!< TIMER break external input polarity is active high */ 740 741 /* TIMER channel n(n=0,1,2,3) */ 742 #define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0 */ 743 #define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1 */ 744 #define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2 */ 745 #define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3 */ 746 #define TIMER_CH_0N ((uint16_t)0x0010U) /*!< TIMER complementary output channel 0 */ 747 #define TIMER_CH_1N ((uint16_t)0x0011U) /*!< TIMER complementary output channel 1 */ 748 #define TIMER_CH_2N ((uint16_t)0x0012U) /*!< TIMER complementary output channel 2 */ 749 #define TIMER_CH_3N ((uint16_t)0x0013U) /*!< TIMER complementary output channel 3 */ 750 #define TIMER_MCH_0 ((uint16_t)0x0010U) /*!< TIMER multi mode channel 0 */ 751 #define TIMER_MCH_1 ((uint16_t)0x0011U) /*!< TIMER multi mode channel 1 */ 752 #define TIMER_MCH_2 ((uint16_t)0x0012U) /*!< TIMER multi mode channel 2 */ 753 #define TIMER_MCH_3 ((uint16_t)0x0013U) /*!< TIMER multi mode channel 3 */ 754 755 /* channel enable state */ 756 #define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ 757 #define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ 758 759 /* channel complementary output enable state */ 760 #define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ 761 #define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ 762 763 /* multi mode channel enable state */ 764 #define TIMER_MCCX_ENABLE ((uint16_t)0x0004U) /*!< multi mode channel enable */ 765 #define TIMER_MCCX_DISABLE ((uint16_t)0x0000U) /*!< multi mode channel disable */ 766 767 /* channel output polarity */ 768 #define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ 769 #define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ 770 771 /* channel complementary output polarity */ 772 #define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ 773 #define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ 774 775 /* multi mode channel output polarity */ 776 #define TIMER_OMC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< multi mode channel output polarity is high */ 777 #define TIMER_OMC_POLARITY_LOW ((uint16_t)0x0001U) /*!< multi mode channel output polarity is low */ 778 779 /* idle state of channel output */ 780 #define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100U) /*!< idle state of channel output is high */ 781 #define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel output is low */ 782 783 /* idle state of channel complementary output */ 784 #define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ 785 #define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ 786 787 /* idle state of multi mode channel output */ 788 #define TIMER_OMC_IDLE_STATE_HIGH ((uint16_t)0x0100U) /*!< idle state of multi mode channel output is high */ 789 #define TIMER_OMC_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of multi mode channel output is low */ 790 791 /* channel output compare mode */ 792 #define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ 793 #define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ 794 #define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ 795 #define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ 796 #define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ 797 #define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ 798 #define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM mode 0 */ 799 #define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM mode 1 */ 800 801 /* channel output compare shadow enable */ 802 #define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output compare shadow enable */ 803 #define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output compare shadow disable */ 804 805 /* channel output compare clear enable */ 806 #define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ 807 #define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ 808 809 /* channel control shadow register update control */ 810 #define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ 811 #define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ 812 813 /* channel input capture polarity */ 814 #define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ 815 #define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge*/ 816 #define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ 817 818 /* TIMER input capture selection */ 819 #define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel n is configured as input and icy is mapped on CIy / CINy */ 820 #define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel n is configured as input and icy is mapped on opposite input */ 821 #define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel n is configured as input and icy is mapped on ITS */ 822 #define TIMER_IC_SELECTION_PAIR ((uint16_t)0x0004U) /*!< channel n is configured as input and icy is mapped on the other channel of same pair */ 823 824 /* channel input capture prescaler */ 825 #define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ 826 #define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ 827 #define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ 828 #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ 829 830 /* trigger selection */ 831 #define SMCFG_TRGSEL(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4U)) | (BIT(31) & ((uint32_t)(regval) << 28U))) 832 #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ 833 #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ 834 #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ 835 #define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ 836 #define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 edge detector */ 837 #define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered channel 0 input */ 838 #define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered channel 1 input */ 839 #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ 840 #define TIMER_SMCFG_TRGSEL_CI2FE2 SMCFG_TRGSEL(8) /*!< filtered channel 2 input */ 841 #define TIMER_SMCFG_TRGSEL_CI3FE3 SMCFG_TRGSEL(9) /*!< filtered channel 3 input */ 842 #define TIMER_SMCFG_TRGSEL_MCI0FEM0 SMCFG_TRGSEL(10) /*!< filtered multi mode channel 0 input */ 843 #define TIMER_SMCFG_TRGSEL_MCI1FEM1 SMCFG_TRGSEL(11) /*!< filtered multi mode channel 1 input */ 844 #define TIMER_SMCFG_TRGSEL_MCI2FEM2 SMCFG_TRGSEL(12) /*!< filtered multi mode channel 2 input */ 845 #define TIMER_SMCFG_TRGSEL_MCI3FEM3 SMCFG_TRGSEL(13) /*!< filtered multi mode channel 3 input */ 846 847 /* master mode control */ 848 #define CTL1_MMC(regval) (BITS(4,6) & ((uint32_t)(regval) << 4U)) 849 #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ 850 #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal as trigger output */ 851 #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ 852 #define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ 853 #define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ 854 #define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ 855 #define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ 856 #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ 857 858 /* slave mode control */ 859 #define SMCFG_SMC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) 860 #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ 861 #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ 862 #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ 863 #define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ 864 #define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ 865 #define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ 866 #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ 867 #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ 868 869 /* master slave mode selection */ 870 #define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ 871 #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ 872 873 /* external trigger prescaler */ 874 #define SMCFG_ETPSC(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U)) 875 #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ 876 #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ 877 #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ 878 #define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ 879 880 /* external trigger polarity */ 881 #define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ 882 #define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ 883 884 /* channel 0 trigger input selection */ 885 #define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ 886 #define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ 887 888 /* TIMER1 channel 0 input remap */ 889 #define TIMER1_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) 890 #define TIMER1_CI0_RMP_GPIO TIMER1_IRMP(0) /*!< TIMER1 channel 0 input remap to GPIO pin */ 891 #define TIMER1_CI0_RMP_LXTAL TIMER1_IRMP(1) /*!< TIMER1 channel 0 input remap to LXTAL */ 892 #define TIMER1_CI0_RMP_HXTAL TIMER1_IRMP(2) /*!< TIMER1 channel 0 input remap to HXTAL/128 */ 893 #define TIMER1_CI0_RMP_CKOUT0SEL TIMER1_IRMP(3) /*!< TIMER1 channel 0 input remap to CKOUT0SEL */ 894 895 /* TIMER write CHxVAL register selection */ 896 #define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_CHVSEL) /*!< write CHxVAL register selection enable */ 897 #define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ 898 899 /* TIMER output value selection enable */ 900 #define TIMER_OUTSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< output value selection enable */ 901 #define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ 902 903 /* channel additional output compare shadow enable */ 904 #define TIMER_ADD_SHADOW_ENABLE ((uint16_t)0x0001U) /*!< channel additional output shadow state enable */ 905 #define TIMER_ADD_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel additional output shadow state disable */ 906 907 /* channel output compare shadow enable */ 908 #define TIMER_OMC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< multi mode channel output shadow state enable */ 909 #define TIMER_OMC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< multi mode channel output shadow state disable */ 910 911 /* channel output compare clear enable */ 912 #define TIMER_OMC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< multi mode channel output clear function enable */ 913 #define TIMER_OMC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< multi mode channel output clear function disable */ 914 915 /* TIMER output value selection */ 916 #define TIMER_PULSE_OUTPUT_NORMAL ((uint16_t)0x0000U) /*!< channel output normal */ 917 #define TIMER_PULSE_OUTPUT_CNT_UP ((uint16_t)0x0001U) /*!< pulse output only when counting up */ 918 #define TIMER_PULSE_OUTPUT_CNT_DOWN ((uint16_t)0x0002U) /*!< pulse output only when counting down */ 919 #define TIMER_PULSE_OUTPUT_CNT_BOTH ((uint16_t)0x0003U) /*!< pulse output when counting up or down */ 920 #define TIMER_PULSE_OUTPUT_MASK ((uint16_t)0x0003U) /*!< pulse output mode mask */ 921 922 /* multi mode channel input capture polarity */ 923 #define TIMER_IMC_POLARITY_RISING ((uint16_t)0x0000U) /*!< multi mode channel input capture rising edge */ 924 #define TIMER_IMC_POLARITY_FALLING ((uint16_t)0x0001U) /*!< multi mode channel input capture falling edge */ 925 #define TIMER_IMC_POLARITY_BOTH_EDGE ((uint16_t)0x0003U) /*!< multi mode channel input capture both edge */ 926 927 /* TIMER multi mode channel mode selection */ 928 #define TIMER_MCH_MODE_INDEPENDENTLY ((uint16_t)0x0000U) /*!< multi mode channel work in independently mode */ 929 #define TIMER_MCH_MODE_MIRRORED ((uint16_t)0x0001U) /*!< multi mode channel work in mirrored output mode */ 930 #define TIMER_MCH_MODE_COMPLEMENTARY ((uint16_t)0x0003U) /*!< multi mode channel work in complementary output mode */ 931 #define TIMER_MCH_MODE_MASK ((uint16_t)0x0003U) /*!< multi mode channel mode mask */ 932 933 /* function declarations */ 934 /* TIMER timebase */ 935 /* deinit a TIMER */ 936 void timer_deinit(uint32_t timer_periph); 937 /* initialize TIMER init parameter struct */ 938 void timer_struct_para_init(timer_parameter_struct *initpara); 939 /* initialize TIMER counter */ 940 void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct *initpara); 941 /* enable a TIMER */ 942 void timer_enable(uint32_t timer_periph); 943 /* disable a TIMER */ 944 void timer_disable(uint32_t timer_periph); 945 /* enable the auto reload shadow function */ 946 void timer_auto_reload_shadow_enable(uint32_t timer_periph); 947 /* disable the auto reload shadow function */ 948 void timer_auto_reload_shadow_disable(uint32_t timer_periph); 949 /* enable the update event */ 950 void timer_update_event_enable(uint32_t timer_periph); 951 /* disable the update event */ 952 void timer_update_event_disable(uint32_t timer_periph); 953 /* set TIMER counter alignment mode */ 954 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); 955 /* set TIMER counter up direction */ 956 void timer_counter_up_direction(uint32_t timer_periph); 957 /* set TIMER counter down direction */ 958 void timer_counter_down_direction(uint32_t timer_periph); 959 960 /* configure TIMER prescaler */ 961 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); 962 /* configure TIMER repetition register value */ 963 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); 964 /* configure TIMER autoreload register value */ 965 void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload); 966 /* configure TIMER counter register value */ 967 void timer_counter_value_config(uint32_t timer_periph, uint16_t counter); 968 /* read TIMER counter value */ 969 uint32_t timer_counter_read(uint32_t timer_periph); 970 /* read TIMER prescaler value */ 971 uint16_t timer_prescaler_read(uint32_t timer_periph); 972 /* configure TIMER single pulse mode */ 973 void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); 974 /* configure TIMER update source */ 975 void timer_update_source_config(uint32_t timer_periph, uint32_t update); 976 /* configure channel commutation control shadow register */ 977 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); 978 /* configure TIMER channel control shadow register update control */ 979 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); 980 981 /* TIMER DMA and event */ 982 /* enable the TIMER DMA */ 983 void timer_dma_enable(uint32_t timer_periph, uint32_t dma); 984 /* disable the TIMER DMA */ 985 void timer_dma_disable(uint32_t timer_periph, uint32_t dma); 986 /* channel DMA request source selection */ 987 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); 988 /* configure the TIMER DMA transfer */ 989 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); 990 /* software generate events */ 991 void timer_event_software_generate(uint32_t timer_periph, uint32_t event); 992 993 /* TIMER channel complementary protection */ 994 /* initialize TIMER break parameter struct */ 995 void timer_break_struct_para_init(timer_break_parameter_struct *breakpara); 996 /* configure TIMER break function */ 997 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara); 998 /* enable TIMER break function */ 999 void timer_break_enable(uint32_t timer_periph); 1000 /* disable TIMER break function */ 1001 void timer_break_disable(uint32_t timer_periph); 1002 /* enable TIMER output automatic function */ 1003 void timer_automatic_output_enable(uint32_t timer_periph); 1004 /* disable TIMER output automatic function */ 1005 void timer_automatic_output_disable(uint32_t timer_periph); 1006 /* configure TIMER primary output function */ 1007 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); 1008 1009 /* TIMER channel output */ 1010 /* initialize TIMER channel output parameter struct */ 1011 void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara); 1012 /* configure TIMER channel output function */ 1013 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara); 1014 /* configure TIMER channel output compare mode */ 1015 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); 1016 /* configure TIMER channel output pulse value */ 1017 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); 1018 /* configure TIMER channel output shadow function */ 1019 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); 1020 /* configure TIMER channel output clear function */ 1021 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); 1022 /* configure TIMER channel output polarity */ 1023 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); 1024 /* configure TIMER channel complementary output polarity */ 1025 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); 1026 /* configure TIMER channel enable state */ 1027 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); 1028 /* configure TIMER channel complementary output enable state */ 1029 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); 1030 1031 /* TIMER channel input */ 1032 /* initialize TIMER channel input parameter struct */ 1033 void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara); 1034 /* configure TIMER input capture parameter */ 1035 void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara); 1036 /* configure TIMER channel input capture prescaler value */ 1037 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); 1038 /* read TIMER channel capture compare register value */ 1039 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); 1040 /* configure TIMER input pwm capture function */ 1041 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm); 1042 /* configure TIMER hall sensor mode */ 1043 void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); 1044 1045 /* TIMER multi mode channel */ 1046 /* initialize TIMER multi mode channel output parameter struct */ 1047 void timer_multi_mode_channel_output_parameter_struct_init(timer_omc_parameter_struct *omcpara); 1048 /* configure TIMER multi mode channel output function */ 1049 void timer_multi_mode_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_omc_parameter_struct *omcpara); 1050 /* multi mode channel mode select */ 1051 void timer_multi_mode_channel_mode_config(uint32_t timer_periph, uint32_t channel, uint32_t multi_mode_sel); 1052 1053 /* TIMER master and slave mode */ 1054 /* select TIMER input trigger source */ 1055 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); 1056 /* select TIMER master mode output trigger source */ 1057 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); 1058 /* select TIMER slave mode */ 1059 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); 1060 /* configure TIMER master slave mode */ 1061 void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); 1062 /* configure TIMER external trigger input */ 1063 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); 1064 /* configure TIMER quadrature decoder mode */ 1065 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); 1066 /* configure TIMER internal clock mode */ 1067 void timer_internal_clock_config(uint32_t timer_periph); 1068 /* configure TIMER the internal trigger as external clock input */ 1069 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); 1070 /* configure TIMER the external trigger as external clock input */ 1071 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); 1072 /* configure TIMER the external clock mode 0 */ 1073 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); 1074 /* configure TIMER the external clock mode 1 */ 1075 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); 1076 /* disable TIMER the external clock mode 1 */ 1077 void timer_external_clock_mode1_disable(uint32_t timer_periph); 1078 1079 /* TIMER configure */ 1080 /* configure TIMER channel input remap function */ 1081 void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap); 1082 /* configure TIMER write CHxVAL register selection */ 1083 void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); 1084 /* configure TIMER output value selection */ 1085 void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); 1086 /* configure TIMER output match pulse selection */ 1087 void timer_output_match_pulse_select(uint32_t timer_periph, uint32_t channel, uint16_t pulsesel); 1088 1089 /* TIMER composite PWM mode */ 1090 /* configure the TIMER composite PWM mode */ 1091 void timer_channel_composite_pwm_mode_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue); 1092 /* configure the TIMER composite PWM mode output pulse value */ 1093 void timer_channel_composite_pwm_mode_output_pulse_value_config(uint32_t timer_periph, uint32_t channel, uint32_t pulse, uint32_t add_pulse); 1094 /* configure TIMER channel additional compare value */ 1095 void timer_channel_additional_compare_value_config(uint32_t timer_periph, uint16_t channel, uint32_t value); 1096 /* configure TIMER channel additional output shadow function */ 1097 void timer_channel_additional_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t aocshadow); 1098 1099 /* TIMER break external inputs */ 1100 /* initialize TIMER break external input parameter struct */ 1101 void timer_break_external_input_struct_para_init(timer_break_ext_input_struct *breakinpara); 1102 /* configure TIMER break external input polarity */ 1103 void timer_break_external_input_config(uint32_t timer_periph, uint32_t break_input, timer_break_ext_input_struct *breakinpara); 1104 /* break external input enable */ 1105 void timer_break_external_input_enable(uint32_t timer_periph, uint32_t break_input); 1106 /* break external input disable */ 1107 void timer_break_external_input_disable(uint32_t timer_periph, uint32_t break_input); 1108 /* configure TIMER break external input polarity */ 1109 void timer_break_external_input_polarity_config(uint32_t timer_periph, uint32_t break_input, uint32_t polarity); 1110 1111 /* TIMER channel free complementary protection */ 1112 /* configure the TIMER channel break function */ 1113 void timer_channel_break_control_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue); 1114 /* configure the TIMER channel dead time function */ 1115 void timer_channel_dead_time_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue); 1116 /* initialize TIMER channel free complementary parameter struct with a default value */ 1117 void timer_free_complementary_struct_para_init(timer_free_complementary_parameter_struct *freecompara); 1118 /* configure channel free complementary protection */ 1119 void timer_channel_free_complementary_config(uint32_t timer_periph, uint16_t channel, timer_free_complementary_parameter_struct *fcpara); 1120 1121 /* TIMER interrupt and flag */ 1122 /* get TIMER flags */ 1123 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); 1124 /* clear TIMER flags */ 1125 void timer_flag_clear(uint32_t timer_periph, uint32_t flag); 1126 /* enable the TIMER interrupt */ 1127 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); 1128 /* disable the TIMER interrupt */ 1129 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); 1130 /* get TIMER interrupt flags */ 1131 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t int_flag); 1132 /* clear TIMER interrupt flags */ 1133 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t int_flag); 1134 1135 #endif /* GD32A50X_TIMER_H */ 1136
