1 /*! 2 \file gd32a50x_pmu.h 3 \brief definitions for the PMU 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_PMU_H 36 #define GD32A50X_PMU_H 37 38 #include "gd32a50x.h" 39 40 /* PMU definitions */ 41 #define PMU PMU_BASE /*!< PMU base address */ 42 43 /* registers definitions */ 44 #define PMU_CTL REG32((PMU) + 0x00000000U) /*!< PMU control register */ 45 #define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */ 46 47 /* bits definitions */ 48 /* PMU_CTL */ 49 #define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ 50 #define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ 51 #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ 52 #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ 53 #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ 54 #define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ 55 #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ 56 #define PMU_CTL_OVDEN BIT(14) /*!< over voltage detector enable */ 57 #define PMU_CTL_OVDT BIT(15) /*!< over voltage detector threshold */ 58 #define PMU_CTL_LDEN BIT(18) /*!< low-driver mode enable in deep-sleep mode */ 59 #define PMU_CTL_SRAMSW1 BIT(20) /*!< SRAM1(16KB~32KB) power switch in deep-sleep mode */ 60 #define PMU_CTL_SRAMSW2 BIT(21) /*!< SRAM2(32KB~48KB) power switch in deep-sleep mode */ 61 62 /* PMU_CS */ 63 #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ 64 #define PMU_CS_STBF BIT(1) /*!< standby flag */ 65 #define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ 66 #define PMU_CS_OVDF BIT(3) /*!< over voltage detector status flag */ 67 #define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin 0 enable */ 68 #define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin 1 enable */ 69 70 /* constants definitions */ 71 /* PMU ldo definitions */ 72 #define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ 73 #define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ 74 75 /* PMU low voltage detector threshold definitions */ 76 #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) 77 #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.9V */ 78 #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 3.1V */ 79 #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 3.3V */ 80 #define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 3.5V */ 81 #define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 4.0V */ 82 #define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 4.2V */ 83 #define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 4.4V */ 84 #define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 4.6V */ 85 86 /* PMU over voltage detector threshold definitions */ 87 #define CTL_OVDT(regval) (BIT(15)&((uint32_t)(regval)<<15)) 88 #define PMU_OVDT_0 CTL_OVDT(0) /*!< voltage threshold is 5.0V */ 89 #define PMU_OVDT_1 CTL_OVDT(1) /*!< voltage threshold is 5.5V */ 90 91 /* PMU flag definitions */ 92 #define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ 93 #define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ 94 #define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ 95 #define PMU_FLAG_OVD PMU_CS_OVDF /*!< ovd flag status */ 96 97 /* PMU WKUP pin definitions */ 98 #define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */ 99 #define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */ 100 101 /* low-driver mode in deep-sleep mode */ 102 #define PMU_LOWDRIVER_DISABLE ((uint32_t)0x00000000U) /*!< low-driver mode disable in deep-sleep mode */ 103 #define PMU_LOWDRIVER_ENABLE PMU_CTL_LDEN /*!< low-driver mode enable in deep-sleep mode */ 104 105 /* PMU flag reset definitions */ 106 #define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ 107 #define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ 108 109 /* PMU command constants definitions */ 110 #define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ 111 #define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ 112 113 /* function declarations */ 114 /* reset PMU registers */ 115 void pmu_deinit(void); 116 117 /* select low voltage detector threshold */ 118 void pmu_lvd_select(uint32_t lvdt_n); 119 /* disable PMU lvd */ 120 void pmu_lvd_disable(void); 121 /* select over voltage detector threshold */ 122 void pmu_ovd_select(uint32_t ovdt_n); 123 /* disable PMU ovd */ 124 void pmu_ovd_disable(void); 125 126 /* enable low-driver mode in deep-sleep mode */ 127 void pmu_lowdriver_mode_enable(void); 128 /* disable low-driver mode in deep-sleep mode */ 129 void pmu_lowdriver_mode_disable(void); 130 /* SRAM1 power off in deep-sleep mode */ 131 void pmu_sram1_poweroff_mode_enable(void); 132 /* SRAM1 power on in deep-sleep mode */ 133 void pmu_sram1_poweroff_mode_disable(void); 134 /* SRAM2 power off in deep-sleep mode */ 135 void pmu_sram2_poweroff_mode_enable(void); 136 /* SRAM2 power on in deep-sleep mode */ 137 void pmu_sram2_poweroff_mode_disable(void); 138 139 /* set PMU mode */ 140 /* PMU work in sleep mode */ 141 void pmu_to_sleepmode(uint8_t sleepmodecmd); 142 /* PMU work in deepsleep mode */ 143 void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd); 144 /* PMU work in standby mode */ 145 void pmu_to_standbymode(void); 146 147 /* wakeup pin related functions */ 148 /* enable PMU wakeup pin */ 149 void pmu_wakeup_pin_enable(uint32_t wakeup_pin); 150 /* disable PMU wakeup pin */ 151 void pmu_wakeup_pin_disable(uint32_t wakeup_pin); 152 153 /* backup related functions */ 154 /* enable write access to the registers in backup domain */ 155 void pmu_backup_write_enable(void); 156 /* disable write access to the registers in backup domain */ 157 void pmu_backup_write_disable(void); 158 159 /* flag functions */ 160 /* get flag state */ 161 FlagStatus pmu_flag_get(uint32_t flag); 162 /* clear flag bit */ 163 void pmu_flag_clear(uint32_t flag); 164 165 #endif /* GD32A50X_PMU_H */ 166
