1 /*! 2 \file gd32a50x_dma.h 3 \brief definitions for the DMA 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_DMA_H 36 #define GD32A50X_DMA_H 37 38 #include "gd32a50x.h" 39 40 /* DMAx(x=0,1) definitions */ 41 #define DMA0 DMA_BASE /*!< DMA0 base address */ 42 #define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */ 43 /* DMAMUX definitions */ 44 #define DMAMUX DMAMUX_BASE /*!< DMA base address */ 45 46 /* DMAx(x=0,1) registers definitions */ 47 #define DMA_INTF(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register */ 48 #define DMA_INTC(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag clear register */ 49 #define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000008U) /*!< DMA channel 0 control register */ 50 #define DMA_CH0CNT(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA channel 0 counter register */ 51 #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 peripheral base address register */ 52 #define DMA_CH0MADDR(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 memory base address register */ 53 #define DMA_CH1CTL(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 1 control register */ 54 #define DMA_CH1CNT(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 1 counter register */ 55 #define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 1 peripheral base address register */ 56 #define DMA_CH1MADDR(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 memory base address register */ 57 #define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 2 control register */ 58 #define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 2 counter register */ 59 #define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 2 peripheral base address register */ 60 #define DMA_CH2MADDR(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 2 memory base address register */ 61 #define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 3 control register */ 62 #define DMA_CH3CNT(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 3 counter register */ 63 #define DMA_CH3PADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 3 peripheral base address register */ 64 #define DMA_CH3MADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 3 memory base address register */ 65 #define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 4 control register */ 66 #define DMA_CH4CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 4 counter register */ 67 #define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 4 peripheral base address register */ 68 #define DMA_CH4MADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 4 memory base address register */ 69 70 /* DMAx(x=0) registers definitions */ 71 #define DMA_CH5CTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 5 control register */ 72 #define DMA_CH5CNT(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 5 counter register */ 73 #define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 5 peripheral base address register */ 74 #define DMA_CH5MADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 5 memory base address register */ 75 #define DMA_CH6CTL(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 6 control register */ 76 #define DMA_CH6CNT(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 6 counter register */ 77 #define DMA_CH6PADDR(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 6 peripheral base address register */ 78 #define DMA_CH6MADDR(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 6 memory base address register */ 79 80 #define DMAMUX_RM_CH0CFG REG32(DMAMUX + 0x00000000U) /*!< DMAMUX request multiplexer channel 0 configuration register */ 81 #define DMAMUX_RM_CH1CFG REG32(DMAMUX + 0x00000004U) /*!< DMAMUX request multiplexer channel 1 configuration register */ 82 #define DMAMUX_RM_CH2CFG REG32(DMAMUX + 0x00000008U) /*!< DMAMUX request multiplexer channel 2 configuration register */ 83 #define DMAMUX_RM_CH3CFG REG32(DMAMUX + 0x0000000CU) /*!< DMAMUX request multiplexer channel 3 configuration register */ 84 #define DMAMUX_RM_CH4CFG REG32(DMAMUX + 0x00000010U) /*!< DMAMUX request multiplexer channel 4 configuration register */ 85 #define DMAMUX_RM_CH5CFG REG32(DMAMUX + 0x00000014U) /*!< DMAMUX request multiplexer channel 5 configuration register */ 86 #define DMAMUX_RM_CH6CFG REG32(DMAMUX + 0x00000018U) /*!< DMAMUX request multiplexer channel 6 configuration register */ 87 #define DMAMUX_RM_CH7CFG REG32(DMAMUX + 0x0000001CU) /*!< DMAMUX request multiplexer channel 7 configuration register */ 88 #define DMAMUX_RM_CH8CFG REG32(DMAMUX + 0x00000020U) /*!< DMAMUX request multiplexer channel 8 configuration register */ 89 #define DMAMUX_RM_CH9CFG REG32(DMAMUX + 0x00000024U) /*!< DMAMUX request multiplexer channel 9 configuration register */ 90 #define DMAMUX_RM_CH10CFG REG32(DMAMUX + 0x00000028U) /*!< DMAMUX request multiplexer channel 10 configuration register */ 91 #define DMAMUX_RM_CH11CFG REG32(DMAMUX + 0x0000002CU) /*!< DMAMUX request multiplexer channel 11 configuration register */ 92 93 #define DMAMUX_RM_INTF REG32(DMAMUX + 0x00000080U) /*!< DMAMUX request multiplexer channel interrupt flag register */ 94 #define DMAMUX_RM_INTC REG32(DMAMUX + 0x00000084U) /*!< DMAMUX request multiplexer channel interrupt flag clear register */ 95 #define DMAMUX_RG_CH0CFG REG32(DMAMUX + 0x00000100U) /*!< DMAMUX generator channel 0 configuration register */ 96 #define DMAMUX_RG_CH1CFG REG32(DMAMUX + 0x00000104U) /*!< DMAMUX generator channel 1 configuration register */ 97 #define DMAMUX_RG_CH2CFG REG32(DMAMUX + 0x00000108U) /*!< DMAMUX generator channel 2 configuration register */ 98 #define DMAMUX_RG_CH3CFG REG32(DMAMUX + 0x0000010CU) /*!< DMAMUX generator channel 3 configuration register */ 99 #define DMAMUX_RG_INTF REG32(DMAMUX + 0x00000140U) /*!< DMAMUX generator channel interrupt flag register */ 100 #define DMAMUX_RG_INTC REG32(DMAMUX + 0x00000144U) /*!< DMAMUX rgenerator channel interrupt flag clear register */ 101 102 /* bits definitions */ 103 /* DMA_INTF */ 104 #define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ 105 #define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ 106 #define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ 107 #define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ 108 109 /* DMA_INTC */ 110 #define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ 111 #define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ 112 #define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ 113 #define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ 114 115 /* DMA_CHxCTL,x=0..6 */ 116 #define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ 117 #define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */ 118 #define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */ 119 #define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */ 120 #define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */ 121 #define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */ 122 #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ 123 #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ 124 #define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */ 125 #define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */ 126 #define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */ 127 #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ 128 129 /* DMA_CHxCNT,x=0..6 */ 130 #define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ 131 132 /* DMA_CHxPADDR,x=0..6 */ 133 #define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ 134 135 /* DMA_CHxMADDR,x=0..6 */ 136 #define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ 137 138 /* DMAMUX_RM_CHxCFG,x=0..6 */ 139 #define DMAMUX_RM_CHXCFG_MUXID BITS(0,6) /*!< multiplexer input identification */ 140 #define DMAMUX_RM_CHXCFG_SOIE BIT(8) /*!< synchronization overrun interrupt enable */ 141 #define DMAMUX_RM_CHXCFG_EVGEN BIT(9) /*!< event generation enable */ 142 #define DMAMUX_RM_CHXCFG_SYNCEN BIT(16) /*!< synchronization enable */ 143 #define DMAMUX_RM_CHXCFG_SYNCP BITS(17,18) /*!< synchronization input polarity */ 144 #define DMAMUX_RM_CHXCFG_NBR BITS(19,23) /*!< number of DMA requests to forward */ 145 #define DMAMUX_RM_CHXCFG_SYNCID BITS(24,28) /*!< synchronization input identification */ 146 147 /* DMAMUX_RM_INTF */ 148 #define DMAMUX_RM_INTF_SOIF0 BIT(0) /*!< synchronization overrun event flag of request multiplexer channel 0 */ 149 #define DMAMUX_RM_INTF_SOIF1 BIT(1) /*!< synchronization overrun event flag of request multiplexer channel 1 */ 150 #define DMAMUX_RM_INTF_SOIF2 BIT(2) /*!< synchronization overrun event flag of request multiplexer channel 2 */ 151 #define DMAMUX_RM_INTF_SOIF3 BIT(3) /*!< synchronization overrun event flag of request multiplexer channel 3 */ 152 #define DMAMUX_RM_INTF_SOIF4 BIT(4) /*!< synchronization overrun event flag of request multiplexer channel 4 */ 153 #define DMAMUX_RM_INTF_SOIF5 BIT(5) /*!< synchronization overrun event flag of request multiplexer channel 5 */ 154 #define DMAMUX_RM_INTF_SOIF6 BIT(6) /*!< synchronization overrun event flag of request multiplexer channel 6 */ 155 #define DMAMUX_RM_INTF_SOIF7 BIT(7) /*!< synchronization overrun event flag of request multiplexer channel 7 */ 156 #define DMAMUX_RM_INTF_SOIF8 BIT(8) /*!< synchronization overrun event flag of request multiplexer channel 8 */ 157 #define DMAMUX_RM_INTF_SOIF9 BIT(9) /*!< synchronization overrun event flag of request multiplexer channel 9 */ 158 #define DMAMUX_RM_INTF_SOIF10 BIT(10) /*!< synchronization overrun event flag of request multiplexer channel 10 */ 159 #define DMAMUX_RM_INTF_SOIF11 BIT(11) /*!< synchronization overrun event flag of request multiplexer channel 11 */ 160 161 /* DMAMUX_RM_INTC */ 162 #define DMAMUX_RM_INTF_SOIFC0 BIT(0) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 0 */ 163 #define DMAMUX_RM_INTF_SOIFC1 BIT(1) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 1 */ 164 #define DMAMUX_RM_INTF_SOIFC2 BIT(2) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 2 */ 165 #define DMAMUX_RM_INTF_SOIFC3 BIT(3) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 3 */ 166 #define DMAMUX_RM_INTF_SOIFC4 BIT(4) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 4 */ 167 #define DMAMUX_RM_INTF_SOIFC5 BIT(5) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 5 */ 168 #define DMAMUX_RM_INTF_SOIFC6 BIT(6) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 6 */ 169 #define DMAMUX_RM_INTF_SOIFC7 BIT(7) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 7 */ 170 #define DMAMUX_RM_INTF_SOIFC8 BIT(8) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 8 */ 171 #define DMAMUX_RM_INTF_SOIFC9 BIT(9) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 9 */ 172 #define DMAMUX_RM_INTF_SOIFC10 BIT(10) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 10 */ 173 #define DMAMUX_RM_INTF_SOIFC11 BIT(11) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 11 */ 174 175 /* DMAMUX_RG_CHxCFG,x=0..3 */ 176 #define DMAMUX_RG_CHXCFG_TID BITS(0,4) /*!< trigger input identification */ 177 #define DMAMUX_RG_CHXCFG_TOIE BIT(8) /*!< trigger overrun interrupt enable */ 178 #define DMAMUX_RG_CHXCFG_RGEN BIT(16) /*!< DMA request generator channel x enable */ 179 #define DMAMUX_RG_CHXCFG_RGTP BITS(17,18) /*!< DMA request generator trigger polarity */ 180 #define DMAMUX_RG_CHXCFG_NBRG BITS(19,23) /*!< number of DMA requests to be generated */ 181 182 /* DMAMUX_RG_INTF */ 183 #define DMAMUX_RG_INTF_TOIF0 BIT(0) /*!< trigger overrun event flag of request generator channel 0 */ 184 #define DMAMUX_RG_INTF_TOIF1 BIT(1) /*!< trigger overrun event flag of request generator channel 1 */ 185 #define DMAMUX_RG_INTF_TOIF2 BIT(2) /*!< trigger overrun event flag of request generator channel 2 */ 186 #define DMAMUX_RG_INTF_TOIF3 BIT(3) /*!< trigger overrun event flag of request generator channel 3 */ 187 188 /* DMAMUX_RG_INTC */ 189 #define DMAMUX_RG_INTF_TOIFC0 BIT(0) /*!< clear bit for trigger overrun event flag of request generator channel 0 */ 190 #define DMAMUX_RG_INTF_TOIFC1 BIT(1) /*!< clear bit for trigger overrun event flag of request generator channel 1 */ 191 #define DMAMUX_RG_INTF_TOIFC2 BIT(2) /*!< clear bit for trigger overrun event flag of request generator channel 2 */ 192 #define DMAMUX_RG_INTF_TOIFC3 BIT(3) /*!< clear bit for trigger overrun event flag of request generator channel 3 */ 193 194 /* constants definitions */ 195 /* define the DMAMUX bit position and its register index offset */ 196 #define DMAMUX_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6U) | (uint32_t)(bitpos)) 197 #define DMAMUX_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22U) | (uint32_t)((bitpos2) << 16U) \ 198 | (((uint32_t)(regidx) << 6U) | (uint32_t)(bitpos))) 199 200 #define DMAMUX_REG_VAL(offset) (REG32(DMAMUX + (((uint32_t)(offset) & 0x0000FFFFU) >> 6U))) 201 #define DMAMUX_REG_VAL2(offset) (REG32(DMAMUX + ((uint32_t)(offset) >> 22U))) 202 #define DMAMUX_REG_VAL3(offset) (REG32(DMAMUX + (((uint32_t)(offset) & 0x0000FFFFU) >> 6U) + 0x4U)) 203 204 #define DMAMUX_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 205 #define DMAMUX_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16U) 206 207 /* register offset */ 208 #define DMAMUX_RM_CH0CFG_REG_OFFSET 0x00000000U /*!< DMAMUX_RM_CH0CFG register offset */ 209 #define DMAMUX_RM_CH1CFG_REG_OFFSET 0x00000004U /*!< DMAMUX_RM_CH1CFG register offset */ 210 #define DMAMUX_RM_CH2CFG_REG_OFFSET 0x00000008U /*!< DMAMUX_RM_CH2CFG register offset */ 211 #define DMAMUX_RM_CH3CFG_REG_OFFSET 0x0000000CU /*!< DMAMUX_RM_CH3CFG register offset */ 212 #define DMAMUX_RM_CH4CFG_REG_OFFSET 0x00000010U /*!< DMAMUX_RM_CH4CFG register offset */ 213 #define DMAMUX_RM_CH5CFG_REG_OFFSET 0x00000014U /*!< DMAMUX_RM_CH5CFG register offset */ 214 #define DMAMUX_RM_CH6CFG_REG_OFFSET 0x00000018U /*!< DMAMUX_RM_CH6CFG register offset */ 215 #define DMAMUX_RM_CH7CFG_REG_OFFSET 0x0000001CU /*!< DMAMUX_RM_CH7CFG register offset */ 216 #define DMAMUX_RM_CH8CFG_REG_OFFSET 0x00000020U /*!< DMAMUX_RM_CH8CFG register offset */ 217 #define DMAMUX_RM_CH9CFG_REG_OFFSET 0x00000024U /*!< DMAMUX_RM_CH9CFG register offset */ 218 #define DMAMUX_RM_CH10CFG_REG_OFFSET 0x00000028U /*!< DMAMUX_RM_CH10CFG register offset */ 219 #define DMAMUX_RM_CH11CFG_REG_OFFSET 0x0000002CU /*!< DMAMUX_RM_CH11CFG register offset */ 220 221 #define DMAMUX_RG_CH0CFG_REG_OFFSET 0x00000100U /*!< DMAMUX_RG_CH0CFG register offset */ 222 #define DMAMUX_RG_CH1CFG_REG_OFFSET 0x00000104U /*!< DMAMUX_RG_CH1CFG register offset */ 223 #define DMAMUX_RG_CH2CFG_REG_OFFSET 0x00000108U /*!< DMAMUX_RG_CH2CFG register offset */ 224 #define DMAMUX_RG_CH3CFG_REG_OFFSET 0x0000010CU /*!< DMAMUX_RG_CH3CFG register offset */ 225 226 #define DMAMUX_RM_INTF_REG_OFFSET 0x00000080U /*!< DMAMUX_RM_INTF register offset */ 227 #define DMAMUX_RM_INTC_REG_OFFSET 0x00000084U /*!< DMAMUX_RM_INTC register offset */ 228 #define DMAMUX_RG_INTF_REG_OFFSET 0x00000140U /*!< DMAMUX_RG_INTF register offset */ 229 #define DMAMUX_RG_INTC_REG_OFFSET 0x00000144U /*!< DMAMUX_RG_INTC register offset */ 230 231 /* DMA channel select */ 232 typedef enum 233 { 234 DMA_CH0 = 0U, /*!< DMA Channel 0 */ 235 DMA_CH1, /*!< DMA Channel 1 */ 236 DMA_CH2, /*!< DMA Channel 2 */ 237 DMA_CH3, /*!< DMA Channel 3 */ 238 DMA_CH4, /*!< DMA Channel 4 */ 239 DMA_CH5, /*!< DMA Channel 5 */ 240 DMA_CH6, /*!< DMA Channel 6 */ 241 } dma_channel_enum; 242 243 /* DMAMUX request line multiplexer channel */ 244 typedef enum 245 { 246 DMAMUX_MULTIPLEXER_CH0 = 0, /*!< DMAMUX request multiplexer Channel0 */ 247 DMAMUX_MULTIPLEXER_CH1, /*!< DMAMUX request multiplexer Channel1 */ 248 DMAMUX_MULTIPLEXER_CH2, /*!< DMAMUX request multiplexer Channel2 */ 249 DMAMUX_MULTIPLEXER_CH3, /*!< DMAMUX request multiplexer Channel3 */ 250 DMAMUX_MULTIPLEXER_CH4, /*!< DMAMUX request multiplexer Channel4 */ 251 DMAMUX_MULTIPLEXER_CH5, /*!< DMAMUX request multiplexer Channel5 */ 252 DMAMUX_MULTIPLEXER_CH6, /*!< DMAMUX request multiplexer Channel6 */ 253 DMAMUX_MULTIPLEXER_CH7, /*!< DMAMUX request multiplexer Channel7 */ 254 DMAMUX_MULTIPLEXER_CH8, /*!< DMAMUX request multiplexer Channel8 */ 255 DMAMUX_MULTIPLEXER_CH9, /*!< DMAMUX request multiplexer Channel9 */ 256 DMAMUX_MULTIPLEXER_CH10, /*!< DMAMUX request multiplexer Channel10 */ 257 DMAMUX_MULTIPLEXER_CH11, /*!< DMAMUX request multiplexer Channel11 */ 258 } dmamux_multiplexer_channel_enum; 259 260 /* DMAMUX request generator channel */ 261 typedef enum { 262 DMAMUX_GENCH0 = 0U, /*!< DMAMUX request generator Channel0 */ 263 DMAMUX_GENCH1, /*!< DMAMUX request generator Channel1 */ 264 DMAMUX_GENCH2, /*!< DMAMUX request generator Channel2 */ 265 DMAMUX_GENCH3, /*!< DMAMUX request generator Channel3 */ 266 } dmamux_generator_channel_enum; 267 268 /* DMAMUX interrupt enable or disable */ 269 typedef enum { 270 /* interrupts in CHxCFG register */ 271 DMAMUX_INT_MUXCH0_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 0 synchronization overrun interrupt */ 272 DMAMUX_INT_MUXCH1_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 1 synchronization overrun interrupt */ 273 DMAMUX_INT_MUXCH2_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 2 synchronization overrun interrupt */ 274 DMAMUX_INT_MUXCH3_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 3 synchronization overrun interrupt */ 275 DMAMUX_INT_MUXCH4_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH4CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 4 synchronization overrun interrupt */ 276 DMAMUX_INT_MUXCH5_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH5CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 5 synchronization overrun interrupt */ 277 DMAMUX_INT_MUXCH6_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH6CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ 278 DMAMUX_INT_MUXCH7_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH7CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ 279 DMAMUX_INT_MUXCH8_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH8CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ 280 DMAMUX_INT_MUXCH9_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH9CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ 281 DMAMUX_INT_MUXCH10_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH10CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ 282 DMAMUX_INT_MUXCH11_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH11CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ 283 DMAMUX_INT_GENCH0_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 0 trigger overrun interrupt */ 284 DMAMUX_INT_GENCH1_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 1 trigger overrun interrupt */ 285 DMAMUX_INT_GENCH2_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 2 trigger overrun interrupt */ 286 DMAMUX_INT_GENCH3_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 3 trigger overrun interrupt */ 287 } dmamux_interrupt_enum; 288 289 290 /* DMAMUX flags */ 291 typedef enum { 292 /* flags in INTF register */ 293 DMAMUX_FLAG_MUXCH0_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 0U), /*!< DMAMUX request multiplexer channel 0 synchronization overrun flag */ 294 DMAMUX_FLAG_MUXCH1_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 1U), /*!< DMAMUX request multiplexer channel 1 synchronization overrun flag */ 295 DMAMUX_FLAG_MUXCH2_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 2U), /*!< DMAMUX request multiplexer channel 2 synchronization overrun flag */ 296 DMAMUX_FLAG_MUXCH3_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 3U), /*!< DMAMUX request multiplexer channel 3 synchronization overrun flag */ 297 DMAMUX_FLAG_MUXCH4_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 4U), /*!< DMAMUX request multiplexer channel 4 synchronization overrun flag */ 298 DMAMUX_FLAG_MUXCH5_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 5U), /*!< DMAMUX request multiplexer channel 5 synchronization overrun flag */ 299 DMAMUX_FLAG_MUXCH6_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 6U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun flag */ 300 DMAMUX_FLAG_MUXCH7_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 7U), /*!< DMAMUX request multiplexer channel 7 synchronization overrun flag */ 301 DMAMUX_FLAG_MUXCH8_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 8 synchronization overrun flag */ 302 DMAMUX_FLAG_MUXCH9_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 9U), /*!< DMAMUX request multiplexer channel 9 synchronization overrun flag */ 303 DMAMUX_FLAG_MUXCH10_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 10U), /*!< DMAMUX request multiplexer channel 10 synchronization overrun flag */ 304 DMAMUX_FLAG_MUXCH11_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 11U), /*!< DMAMUX request multiplexer channel 11 synchronization overrun flag */ 305 DMAMUX_FLAG_GENCH0_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 0U), /*!< DMAMUX request generator channel 0 trigger overrun flag */ 306 DMAMUX_FLAG_GENCH1_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 1U), /*!< DMAMUX request generator channel 1 trigger overrun flag */ 307 DMAMUX_FLAG_GENCH2_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 2U), /*!< DMAMUX request generator channel 2 trigger overrun flag */ 308 DMAMUX_FLAG_GENCH3_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 3U), /*!< DMAMUX request generator channel 3 trigger overrun flag */ 309 } dmamux_flag_enum; 310 311 /* DMAMUX interrupt flags */ 312 typedef enum { 313 /* interrupt flags in INTF register */ 314 DMAMUX_INT_FLAG_MUXCH0_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 0U, DMAMUX_RM_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 0 synchronization overrun interrupt flag */ 315 DMAMUX_INT_FLAG_MUXCH1_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 1U, DMAMUX_RM_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 1 synchronization overrun interrupt flag */ 316 DMAMUX_INT_FLAG_MUXCH2_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 2U, DMAMUX_RM_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 2 synchronization overrun interrupt flag */ 317 DMAMUX_INT_FLAG_MUXCH3_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 3U, DMAMUX_RM_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 3 synchronization overrun interrupt flag */ 318 DMAMUX_INT_FLAG_MUXCH4_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 4U, DMAMUX_RM_CH4CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 4 synchronization overrun interrupt flag */ 319 DMAMUX_INT_FLAG_MUXCH5_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 5U, DMAMUX_RM_CH5CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 5 synchronization overrun interrupt flag */ 320 DMAMUX_INT_FLAG_MUXCH6_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 6U, DMAMUX_RM_CH6CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt flag */ 321 DMAMUX_INT_FLAG_MUXCH7_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 7U, DMAMUX_RM_CH7CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 7 synchronization overrun interrupt flag */ 322 DMAMUX_INT_FLAG_MUXCH8_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 8U, DMAMUX_RM_CH8CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 8 synchronization overrun interrupt flag */ 323 DMAMUX_INT_FLAG_MUXCH9_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 9U, DMAMUX_RM_CH9CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 9 synchronization overrun interrupt flag */ 324 DMAMUX_INT_FLAG_MUXCH10_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 10U, DMAMUX_RM_CH10CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 10 synchronization overrun interrupt flag */ 325 DMAMUX_INT_FLAG_MUXCH11_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 11U, DMAMUX_RM_CH11CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 11 synchronization overrun interrupt flag */ 326 DMAMUX_INT_FLAG_GENCH0_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 0U, DMAMUX_RG_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 0 trigger overrun interrupt flag */ 327 DMAMUX_INT_FLAG_GENCH1_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 1U, DMAMUX_RG_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 1 trigger overrun interrupt flag */ 328 DMAMUX_INT_FLAG_GENCH2_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 2U, DMAMUX_RG_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 2 trigger overrun interrupt flag */ 329 DMAMUX_INT_FLAG_GENCH3_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 3U, DMAMUX_RG_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 3 trigger overrun interrupt flag */ 330 } dmamux_interrupt_flag_enum; 331 332 /* DMA initialization structure */ 333 typedef struct 334 { 335 uint32_t periph_addr; /*!< peripheral base address */ 336 uint32_t periph_width; /*!< transfer data size of peripheral */ 337 uint32_t memory_addr; /*!< memory base address */ 338 uint32_t memory_width; /*!< transfer data size of memory */ 339 uint32_t number; /*!< channel transfer number */ 340 uint32_t priority; /*!< channel priority level */ 341 uint8_t periph_inc; /*!< peripheral increasing mode */ 342 uint8_t memory_inc; /*!< memory increasing mode */ 343 uint8_t direction; /*!< channel data transfer direction */ 344 uint32_t request; /*!< channel input identification */ 345 } dma_parameter_struct; 346 347 /* DMAMUX request multiplexer synchronization configuration structure */ 348 typedef struct 349 { 350 uint32_t sync_id; /*!< synchronization input identification */ 351 uint32_t sync_polarity; /*!< synchronization input polarity */ 352 uint32_t request_number; /*!< number of DMA requests to forward */ 353 } dmamux_sync_parameter_struct; 354 355 /* DMAMUX request generator trigger configuration structure */ 356 typedef struct 357 { 358 uint32_t trigger_id; /*!< trigger input identification */ 359 uint32_t trigger_polarity; /*!< DMA request generator trigger polarity */ 360 uint32_t request_number; /*!< number of DMA requests to be generated */ 361 } dmamux_gen_parameter_struct; 362 363 /* DMA reset value */ 364 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ 365 #define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ 366 #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ 367 #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ 368 #define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ 369 DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< the reset value of DMA channel DMA_INTF register */ 370 371 #define DMA_FLAG_ADD(flag, shift) ((uint32_t)flag << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */ 372 373 /* DMA channel shift bit */ 374 #define DMA_CHCTL(dma, channel) REG32(((dma) + 0x00000008U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ 375 #define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0000000CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ 376 #define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x00000010U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ 377 #define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x00000014U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ 378 379 /* DMAMUX_RM_CHxCFG base address */ 380 #define DMAMUX_RM_CHXCFG_BASE (DMAMUX) /*!< the base address of DMAMUX channel CHxCFG register */ 381 382 /* DMAMUX request multiplexer channel shift bit */ 383 #define DMAMUX_RM_CHXCFG(channel) REG32(DMAMUX_RM_CHXCFG_BASE + 0x4U * (uint32_t)(channel)) /*!< the address of DMAMUX channel CHxCFG register */ 384 385 /* DMAMUX_RG_CHxCFG base address */ 386 #define DMAMUX_RG_CHXCFG_BASE (DMAMUX + 0x00000100U) /*!< the base address of DMAMUX channel request generator CHxCFG register */ 387 388 /* DMAMUX request generator channel shift bit */ 389 #define DMAMUX_RG_CHXCFG(channel) REG32(DMAMUX_RG_CHXCFG_BASE + 0x4U * (uint32_t)(channel)) /*!< the address of DMAMUX channel request generator CHxCFG register */ 390 391 /* DMA interrupt flag bits */ 392 #define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ 393 #define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ 394 #define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ 395 #define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ 396 397 /* DMA flag bits */ 398 #define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ 399 #define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ 400 #define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ 401 #define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ 402 403 /* DMA interrupt enable bits */ 404 #define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ 405 #define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ 406 #define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ 407 408 /* DMA transfer direction */ 409 #define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */ 410 #define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */ 411 412 /* DMA peripheral increasing mode */ 413 #define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00U) /*!< next address of peripheral is fixed address mode */ 414 #define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x01U) /*!< next address of peripheral is increasing address mode */ 415 416 /* DMA memory increasing mode */ 417 #define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00U) /*!< next address of memory is fixed address mode */ 418 #define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x01U) /*!< next address of memory is increasing address mode */ 419 420 /* DMA transfer data size of peripheral */ 421 #define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8U)) /*!< transfer data size of peripheral */ 422 #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ 423 #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ 424 #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ 425 426 /* DMA transfer data size of memory */ 427 #define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10U)) /*!< transfer data size of memory */ 428 #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ 429 #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ 430 #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ 431 432 /* DMA channel priority level */ 433 #define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12U)) /*!< DMA channel priority level */ 434 #define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ 435 #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ 436 #define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ 437 #define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ 438 439 /* DMA transfer counter */ 440 #define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ 441 442 /* DMAMUX request multiplexer channel input identification */ 443 #define RM_CHXCFG_MUXID(regval) (BITS(0,5) & ((regval) << 0U)) /*!< multiplexer input identification */ 444 #define DMA_REQUEST_M2M RM_CHXCFG_MUXID(0U) /*!< memory to memory transfer */ 445 #define DMA_REQUEST_GENERATOR0 RM_CHXCFG_MUXID(1U) /*!< DMAMUX request generator 0 */ 446 #define DMA_REQUEST_GENERATOR1 RM_CHXCFG_MUXID(2U) /*!< DMAMUX request generator 1 */ 447 #define DMA_REQUEST_GENERATOR2 RM_CHXCFG_MUXID(3U) /*!< DMAMUX request generator 2 */ 448 #define DMA_REQUEST_GENERATOR3 RM_CHXCFG_MUXID(4U) /*!< DMAMUX request generator 3 */ 449 #define DMA_REQUEST_ADC RM_CHXCFG_MUXID(5U) /*!< DMAMUX ADC request */ 450 #define DMA_REQUEST_DAC_CH0 RM_CHXCFG_MUXID(6U) /*!< DMAMUX DAC CH0 request */ 451 #define DMA_REQUEST_I2C1_RX RM_CHXCFG_MUXID(8U) /*!< DMAMUX I2C1 RX request */ 452 #define DMA_REQUEST_I2C1_TX RM_CHXCFG_MUXID(9U) /*!< DMAMUX I2C1 TX request */ 453 #define DMA_REQUEST_I2C0_RX RM_CHXCFG_MUXID(10U) /*!< DMAMUX I2C0 RX request */ 454 #define DMA_REQUEST_I2C0_TX RM_CHXCFG_MUXID(11U) /*!< DMAMUX I2C0 TX request */ 455 #define DMA_REQUESR_SSTAT0 RM_CHXCFG_MUXID(12U) /*!< DMAMUX SSTAT0 request */ 456 #define DMA_REQUESR_SSTAT1 RM_CHXCFG_MUXID(13U) /*!< DMAMUX SSTAT1 request */ 457 #define DMA_REQUESR_SSTAT2 RM_CHXCFG_MUXID(14U) /*!< DMAMUX SSTAT2 request */ 458 #define DMA_REQUESR_SSTAT3 RM_CHXCFG_MUXID(15U) /*!< DMAMUX SSTAT3 request */ 459 #define DMA_REQUEST_SPI0_RX RM_CHXCFG_MUXID(16U) /*!< DMAMUX SPI0 RX request */ 460 #define DMA_REQUEST_SPI0_TX RM_CHXCFG_MUXID(17U) /*!< DMAMUX SPI0 TX request */ 461 #define DMA_REQUEST_SPI1_RX RM_CHXCFG_MUXID(18U) /*!< DMAMUX SPI1 RX request */ 462 #define DMA_REQUEST_SPI1_TX RM_CHXCFG_MUXID(19U) /*!< DMAMUX SPI1 TX request */ 463 #define DMA_REQUEST_TIMER0_CH0 RM_CHXCFG_MUXID(20U) /*!< DMAMUX TIMER0 CH0 request */ 464 #define DMA_REQUEST_TIMER0_CH1 RM_CHXCFG_MUXID(21U) /*!< DMAMUX TIMER0 CH1 request */ 465 #define DMA_REQUEST_TIMER0_CH2 RM_CHXCFG_MUXID(22U) /*!< DMAMUX TIMER0 CH2 request */ 466 #define DMA_REQUEST_TIMER0_CH3 RM_CHXCFG_MUXID(23U) /*!< DMAMUX TIMER0 CH3 request */ 467 #define DMA_REQUEST_TIMER0_TI RM_CHXCFG_MUXID(24U) /*!< DMAMUX TIMER0 TI request */ 468 #define DMA_REQUEST_TIMER0_UP RM_CHXCFG_MUXID(25U) /*!< DMAMUX TIMER0 UP request */ 469 #define DMA_REQUEST_TIMER0_CO RM_CHXCFG_MUXID(26U) /*!< DMAMUX TIMER0 CO request */ 470 #define DMA_REQUEST_TIMER0_MCH0 RM_CHXCFG_MUXID(27U) /*!< DMAMUX TIMER0 MCH0 request */ 471 #define DMA_REQUEST_TIMER0_MCH1 RM_CHXCFG_MUXID(28U) /*!< DMAMUX TIMER0 MCH1 request */ 472 #define DMA_REQUEST_TIMER0_MCH2 RM_CHXCFG_MUXID(29U) /*!< DMAMUX TIMER0 MCH2 request */ 473 #define DMA_REQUEST_TIMER0_MCH3 RM_CHXCFG_MUXID(30U) /*!< DMAMUX TIMER0 MCH3 request */ 474 #define DMA_REQUEST_TIMER1_CH0 RM_CHXCFG_MUXID(31U) /*!< DMAMUX TIMER1 CH0 request */ 475 #define DMA_REQUEST_TIMER1_CH1 RM_CHXCFG_MUXID(32U) /*!< DMAMUX TIMER1 CH1 request */ 476 #define DMA_REQUEST_TIMER1_CH2 RM_CHXCFG_MUXID(33U) /*!< DMAMUX TIMER1 CH2 request */ 477 #define DMA_REQUEST_TIMER1_CH3 RM_CHXCFG_MUXID(34U) /*!< DMAMUX TIMER1 CH3 request */ 478 #define DMA_REQUEST_TIMER1_TI RM_CHXCFG_MUXID(35U) /*!< DMAMUX TIMER1 TI request */ 479 #define DMA_REQUEST_TIMER1_UP RM_CHXCFG_MUXID(36U) /*!< DMAMUX TIMER1 UP request */ 480 #define DMA_REQUEST_TIMER7_CH0 RM_CHXCFG_MUXID(37U) /*!< DMAMUX TIMER7 CH0 request */ 481 #define DMA_REQUEST_TIMER7_CH1 RM_CHXCFG_MUXID(38U) /*!< DMAMUX TIMER7 CH1 request */ 482 #define DMA_REQUEST_TIMER7_CH2 RM_CHXCFG_MUXID(39U) /*!< DMAMUX TIMER7 CH2 request */ 483 #define DMA_REQUEST_TIMER7_CH3 RM_CHXCFG_MUXID(40U) /*!< DMAMUX TIMER7 CH3 request */ 484 #define DMA_REQUEST_TIMER7_TI RM_CHXCFG_MUXID(41U) /*!< DMAMUX TIMER7 TI request */ 485 #define DMA_REQUEST_TIMER7_UP RM_CHXCFG_MUXID(42U) /*!< DMAMUX TIMER7 UP request */ 486 #define DMA_REQUEST_TIMER7_CO RM_CHXCFG_MUXID(43U) /*!< DMAMUX TIMER7 CO request */ 487 #define DMA_REQUEST_TIMER7_MCH0 RM_CHXCFG_MUXID(44U) /*!< DMAMUX TIMER7 MCH0 request */ 488 #define DMA_REQUEST_TIMER7_MCH1 RM_CHXCFG_MUXID(45U) /*!< DMAMUX TIMER7 MCH1 request */ 489 #define DMA_REQUEST_TIMER7_MCH2 RM_CHXCFG_MUXID(46U) /*!< DMAMUX TIMER7 MCH2 request */ 490 #define DMA_REQUEST_TIMER7_MCH3 RM_CHXCFG_MUXID(47U) /*!< DMAMUX TIMER7 MCH3 request */ 491 #define DMA_REQUEST_CAN1 RM_CHXCFG_MUXID(48U) /*!< DMAMUX CAN1 request */ 492 #define DMA_REQUEST_CAN0 RM_CHXCFG_MUXID(49U) /*!< DMAMUX CAN0 request */ 493 #define DMA_REQUEST_USART0_RX RM_CHXCFG_MUXID(50U) /*!< DMAMUX USART0 RX request */ 494 #define DMA_REQUEST_USART0_TX RM_CHXCFG_MUXID(51U) /*!< DMAMUX USART0 TX request */ 495 #define DMA_REQUEST_USART1_RX RM_CHXCFG_MUXID(52U) /*!< DMAMUX USART1 RX request */ 496 #define DMA_REQUEST_USART1_TX RM_CHXCFG_MUXID(53U) /*!< DMAMUX USART1 TX request */ 497 #define DMA_REQUEST_USART2_RX RM_CHXCFG_MUXID(54U) /*!< DMAMUX USART2 RX request */ 498 #define DMA_REQUEST_USART2_TX RM_CHXCFG_MUXID(55U) /*!< DMAMUX USART2 TX request */ 499 #define DMA_REQUEST_TIMER5_UP RM_CHXCFG_MUXID(56U) /*!< DMAMUX TIMER5 UP request */ 500 #define DMA_REQUEST_TIMER6_UP RM_CHXCFG_MUXID(57U) /*!< DMAMUX TIMER6 UP request */ 501 #define DMA_REQUEST_TIMER19_CH0 RM_CHXCFG_MUXID(58U) /*!< DMAMUX TIMER19 CH0 request */ 502 #define DMA_REQUEST_TIMER19_CH1 RM_CHXCFG_MUXID(59U) /*!< DMAMUX TIMER19 CH1 request */ 503 #define DMA_REQUEST_TIMER19_CH2 RM_CHXCFG_MUXID(60U) /*!< DMAMUX TIMER19 CH2 request */ 504 #define DMA_REQUEST_TIMER19_CH3 RM_CHXCFG_MUXID(61U) /*!< DMAMUX TIMER19 CH3 request */ 505 #define DMA_REQUEST_TIMER19_TI RM_CHXCFG_MUXID(62U) /*!< DMAMUX TIMER19 TI request */ 506 #define DMA_REQUEST_TIMER19_UP RM_CHXCFG_MUXID(63U) /*!< DMAMUX TIMER19 UP request */ 507 #define DMA_REQUEST_TIMER19_CO RM_CHXCFG_MUXID(64U) /*!< DMAMUX TIMER19 CO request */ 508 #define DMA_REQUEST_TIMER19_MCH0 RM_CHXCFG_MUXID(65U) /*!< DMAMUX TIMER19 MCH0 request */ 509 #define DMA_REQUEST_TIMER19_MCH1 RM_CHXCFG_MUXID(66U) /*!< DMAMUX TIMER19 MCH1 request */ 510 #define DMA_REQUEST_TIMER19_MCH2 RM_CHXCFG_MUXID(67U) /*!< DMAMUX TIMER19 MCH2 request */ 511 #define DMA_REQUEST_TIMER19_MCH3 RM_CHXCFG_MUXID(68U) /*!< DMAMUX TIMER19 MCH3 request */ 512 #define DMA_REQUEST_TIMER20_CH0 RM_CHXCFG_MUXID(69U) /*!< DMAMUX TIMER20 CH0 request */ 513 #define DMA_REQUEST_TIMER20_CH1 RM_CHXCFG_MUXID(70U) /*!< DMAMUX TIMER20 CH1 request */ 514 #define DMA_REQUEST_TIMER20_CH2 RM_CHXCFG_MUXID(71U) /*!< DMAMUX TIMER20 CH2 request */ 515 #define DMA_REQUEST_TIMER20_CH3 RM_CHXCFG_MUXID(72U) /*!< DMAMUX TIMER20 CH3 request */ 516 #define DMA_REQUEST_TIMER20_TI RM_CHXCFG_MUXID(73U) /*!< DMAMUX TIMER20 TI request */ 517 #define DMA_REQUEST_TIMER20_UP RM_CHXCFG_MUXID(74U) /*!< DMAMUX TIMER20 UP request */ 518 #define DMA_REQUEST_TIMER20_CO RM_CHXCFG_MUXID(75U) /*!< DMAMUX TIMER20 CO request */ 519 #define DMA_REQUEST_TIMER20_MCH0 RM_CHXCFG_MUXID(76U) /*!< DMAMUX TIMER20 MCH0 request */ 520 #define DMA_REQUEST_TIMER20_MCH1 RM_CHXCFG_MUXID(77U) /*!< DMAMUX TIMER20 MCH1 request */ 521 #define DMA_REQUEST_TIMER20_MCH2 RM_CHXCFG_MUXID(78U) /*!< DMAMUX TIMER20 MCH2 request */ 522 #define DMA_REQUEST_TIMER20_MCH3 RM_CHXCFG_MUXID(79U) /*!< DMAMUX TIMER20 MCH3 request */ 523 524 /* DMAMUX request generator trigger input identification */ 525 #define RG_CHXCFG_TID(regval) (BITS(0,4) & ((regval) << 0U)) /*!< trigger input identification */ 526 #define DMAMUX_TRIGGER_EXTI0 RG_CHXCFG_TID(0U) /*!< trigger input is EXTI0 */ 527 #define DMAMUX_TRIGGER_EXTI1 RG_CHXCFG_TID(1U) /*!< trigger input is EXTI1 */ 528 #define DMAMUX_TRIGGER_EXTI2 RG_CHXCFG_TID(2U) /*!< trigger input is EXTI2 */ 529 #define DMAMUX_TRIGGER_EXTI3 RG_CHXCFG_TID(3U) /*!< trigger input is EXTI3 */ 530 #define DMAMUX_TRIGGER_EXTI4 RG_CHXCFG_TID(4U) /*!< trigger input is EXTI4 */ 531 #define DMAMUX_TRIGGER_EXTI5 RG_CHXCFG_TID(5U) /*!< trigger input is EXTI5 */ 532 #define DMAMUX_TRIGGER_EXTI6 RG_CHXCFG_TID(6U) /*!< trigger input is EXTI6 */ 533 #define DMAMUX_TRIGGER_EXTI7 RG_CHXCFG_TID(7U) /*!< trigger input is EXTI7 */ 534 #define DMAMUX_TRIGGER_EXTI8 RG_CHXCFG_TID(8U) /*!< trigger input is EXTI8 */ 535 #define DMAMUX_TRIGGER_EXTI9 RG_CHXCFG_TID(9U) /*!< trigger input is EXTI9 */ 536 #define DMAMUX_TRIGGER_EXTI10 RG_CHXCFG_TID(10U) /*!< trigger input is EXTI10 */ 537 #define DMAMUX_TRIGGER_EXTI11 RG_CHXCFG_TID(11U) /*!< trigger input is EXTI11 */ 538 #define DMAMUX_TRIGGER_EXTI12 RG_CHXCFG_TID(12U) /*!< trigger input is EXTI12 */ 539 #define DMAMUX_TRIGGER_EXTI13 RG_CHXCFG_TID(13U) /*!< trigger input is EXTI13 */ 540 #define DMAMUX_TRIGGER_EXTI14 RG_CHXCFG_TID(14U) /*!< trigger input is EXTI14 */ 541 #define DMAMUX_TRIGGER_EXTI15 RG_CHXCFG_TID(15U) /*!< trigger input is EXTI15 */ 542 #define DMAMUX_TRIGGER_EVTX_OUT0 RG_CHXCFG_TID(16U) /*!< trigger input is Evtx_out0 */ 543 #define DMAMUX_TRIGGER_EVTX_OUT1 RG_CHXCFG_TID(17U) /*!< trigger input is Evtx_out1 */ 544 #define DMAMUX_TRIGGER_EVTX_OUT2 RG_CHXCFG_TID(18U) /*!< trigger input is Evtx_out2 */ 545 #define DMAMUX_TRIGGER_EVTX_OUT3 RG_CHXCFG_TID(19U) /*!< trigger input is Evtx_out3 */ 546 #define DMAMUX_TRIGGER_TIMER20_CH0_O RG_CHXCFG_TID(22U) /*!< trigger input is TIMER20_CH0_O */ 547 548 /* DMAMUX request generator trigger polarity */ 549 #define RM_CHXCFG_RGTP(regval) (BITS(17,18) & ((regval) << 17U)) /*!< DMA request generator trigger polarity */ 550 #define DMAMUX_GEN_NO_EVENT RM_CHXCFG_RGTP(0U) /*!< no event detection */ 551 #define DMAMUX_GEN_RISING RM_CHXCFG_RGTP(1U) /*!< rising edge */ 552 #define DMAMUX_GEN_FALLING RM_CHXCFG_RGTP(2U) /*!< falling edge */ 553 #define DMAMUX_GEN_RISING_FALLING RM_CHXCFG_RGTP(3U) /*!< rising and falling edges */ 554 555 /* number of DMA requests to be generated */ 556 #define RG_CHXCFG_NBRG(regval) (BITS(19,23) & ((regval) << 19U)) /*!< number of DMA requests to be generated */ 557 558 /* DMAMUX request multiplexer channel synchronization input identification */ 559 #define RM_CHXCFG_SYNCID(regval) (BITS(24,28) & ((regval) << 24U)) /*!< synchronization input identification */ 560 #define DMAMUX_SYNC_EXTI0 RM_CHXCFG_SYNCID(0U) /*!< synchronization input is EXTI0 */ 561 #define DMAMUX_SYNC_EXTI1 RM_CHXCFG_SYNCID(1U) /*!< synchronization input is EXTI1 */ 562 #define DMAMUX_SYNC_EXTI2 RM_CHXCFG_SYNCID(2U) /*!< synchronization input is EXTI2 */ 563 #define DMAMUX_SYNC_EXTI3 RM_CHXCFG_SYNCID(3U) /*!< synchronization input is EXTI3 */ 564 #define DMAMUX_SYNC_EXTI4 RM_CHXCFG_SYNCID(4U) /*!< synchronization input is EXTI4 */ 565 #define DMAMUX_SYNC_EXTI5 RM_CHXCFG_SYNCID(5U) /*!< synchronization input is EXTI5 */ 566 #define DMAMUX_SYNC_EXTI6 RM_CHXCFG_SYNCID(6U) /*!< synchronization input is EXTI6 */ 567 #define DMAMUX_SYNC_EXTI7 RM_CHXCFG_SYNCID(7U) /*!< synchronization input is EXTI7 */ 568 #define DMAMUX_SYNC_EXTI8 RM_CHXCFG_SYNCID(8U) /*!< synchronization input is EXTI8 */ 569 #define DMAMUX_SYNC_EXTI9 RM_CHXCFG_SYNCID(9U) /*!< synchronization input is EXTI9 */ 570 #define DMAMUX_SYNC_EXTI10 RM_CHXCFG_SYNCID(10U) /*!< synchronization input is EXTI10 */ 571 #define DMAMUX_SYNC_EXTI11 RM_CHXCFG_SYNCID(11U) /*!< synchronization input is EXTI11 */ 572 #define DMAMUX_SYNC_EXTI12 RM_CHXCFG_SYNCID(12U) /*!< synchronization input is EXTI12 */ 573 #define DMAMUX_SYNC_EXTI13 RM_CHXCFG_SYNCID(13U) /*!< synchronization input is EXTI13 */ 574 #define DMAMUX_SYNC_EXTI14 RM_CHXCFG_SYNCID(14U) /*!< synchronization input is EXTI14 */ 575 #define DMAMUX_SYNC_EXTI15 RM_CHXCFG_SYNCID(15U) /*!< synchronization input is EXTI15 */ 576 #define DMAMUX_SYNC_EVTX_OUT0 RM_CHXCFG_SYNCID(16U) /*!< synchronization input is Evtx_out0 */ 577 #define DMAMUX_SYNC_EVTX_OUT1 RM_CHXCFG_SYNCID(17U) /*!< synchronization input is Evtx_out1 */ 578 #define DMAMUX_SYNC_EVTX_OUT2 RM_CHXCFG_SYNCID(18U) /*!< synchronization input is Evtx_out2 */ 579 #define DMAMUX_SYNC_EVTX_OUT3 RM_CHXCFG_SYNCID(19U) /*!< synchronization input is Evtx_out3 */ 580 #define DMAMUX_SYNC_TIMER20_CH0_O RM_CHXCFG_SYNCID(22U) /*!< synchronization input is TIMER20_CH0_O */ 581 582 /* DMAMUX request multiplexer synchronization input polarity */ 583 #define RM_CHXCFG_SYNCP(regval) (BITS(17,18) & ((regval) << 17U)) /*!< synchronization input polarity */ 584 #define DMAMUX_SYNC_NO_EVENT RM_CHXCFG_SYNCP(0U) /*!< no event detection */ 585 #define DMAMUX_SYNC_RISING RM_CHXCFG_SYNCP(1U) /*!< rising edge */ 586 #define DMAMUX_SYNC_FALLING RM_CHXCFG_SYNCP(2U) /*!< falling edge */ 587 #define DMAMUX_SYNC_RISING_FALLING RM_CHXCFG_SYNCP(3U) /*!< rising and falling edges */ 588 589 /* number of DMA requests to forward */ 590 #define RM_CHXCFG_NBR(regval) (BITS(19,23) & ((regval) << 19)) /*!< number of DMA requests to forward */ 591 592 /* function declarations */ 593 /* DMA functions */ 594 /* DMA initialization functions */ 595 /* deinitialize DMA channel registers */ 596 void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); 597 /* initialize the parameters of DMA structure with the default values */ 598 void dma_struct_para_init(dma_parameter_struct* init_struct); 599 /* initialize DMA channel */ 600 void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct); 601 /* enable DMA circulation mode */ 602 void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); 603 /* disable DMA circulation mode */ 604 void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); 605 /* enable memory to memory mode */ 606 void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); 607 /* disable memory to memory mode */ 608 void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); 609 /* enable DMA channel */ 610 void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); 611 /* disable DMA channel */ 612 void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); 613 614 /* DMA configuration functions */ 615 /* set DMA peripheral base address */ 616 void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); 617 /* configure DMA memory base address */ 618 void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); 619 /* configure the number of remaining data to be transferred by the DMA */ 620 void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); 621 /* get the number of remaining data to be transferred by the DMA */ 622 uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); 623 /* configure priority level of DMA channel */ 624 void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); 625 /* configure transfer data size of memory */ 626 void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); 627 /* configure transfer data size of peripheral */ 628 void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); 629 /* enable next address increasement algorithm of memory */ 630 void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); 631 /* disable next address increasement algorithm of memory */ 632 void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); 633 /* enable next address increasement algorithm of peripheral */ 634 void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); 635 /* disable next address increasement algorithm of peripheral */ 636 void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); 637 /* configure the direction of data transfer on the channel */ 638 void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); 639 640 /* DMA interrupt and flag functions */ 641 /* check DMA flag is set or not */ 642 FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); 643 /* clear a DMA channel flag */ 644 void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); 645 /* enable DMA interrupt */ 646 void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); 647 /* disable DMA interrupt */ 648 void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); 649 /* check DMA flag and interrupt enable bit is set or not */ 650 FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag); 651 /* clear a DMA channel interrupt flag */ 652 void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag); 653 654 /* DMAMUX functions */ 655 /* DMAMUX request multiplexer functions */ 656 /* initialize the parameters of DMAMUX synchronization mode structure with the default values */ 657 void dmamux_sync_struct_para_init(dmamux_sync_parameter_struct *init_struct); 658 /* initialize DMAMUX request multiplexer channel synchronization mode */ 659 void dmamux_synchronization_init(dmamux_multiplexer_channel_enum channelx, dmamux_sync_parameter_struct *init_struct); 660 /* enable synchronization mode */ 661 void dmamux_synchronization_enable(dmamux_multiplexer_channel_enum channelx); 662 /* disable synchronization mode */ 663 void dmamux_synchronization_disable(dmamux_multiplexer_channel_enum channelx); 664 /* enable event generation */ 665 void dmamux_event_generation_enable(dmamux_multiplexer_channel_enum channelx); 666 /* disable event generation */ 667 void dmamux_event_generation_disable(dmamux_multiplexer_channel_enum channelx); 668 669 /* DMAMUX request generator functions */ 670 /* initialize the parameters of DMAMUX request generator structure with the default values */ 671 void dmamux_gen_struct_para_init(dmamux_gen_parameter_struct *init_struct); 672 /* initialize DMAMUX request generator channel */ 673 void dmamux_request_generator_init(dmamux_generator_channel_enum channelx, dmamux_gen_parameter_struct *init_struct); 674 /* enable DMAMUX request generator channel */ 675 void dmamux_request_generator_channel_enable(dmamux_generator_channel_enum channelx); 676 /* disable DMAMUX request generator channel */ 677 void dmamux_request_generator_channel_disable(dmamux_generator_channel_enum channelx); 678 679 /* DMAMUX configuration functions */ 680 /* configure synchronization input polarity */ 681 void dmamux_synchronization_polarity_config(dmamux_multiplexer_channel_enum channelx, uint32_t polarity); 682 /* configure number of DMA requests to forward */ 683 void dmamux_request_forward_number_config(dmamux_multiplexer_channel_enum channelx, uint32_t number); 684 /* configure synchronization input identification */ 685 void dmamux_sync_id_config(dmamux_multiplexer_channel_enum channelx, uint32_t id); 686 /* configure multiplexer input identification */ 687 void dmamux_request_id_config(dmamux_multiplexer_channel_enum channelx, uint32_t id); 688 /* configure trigger input polarity */ 689 void dmamux_trigger_polarity_config(dmamux_generator_channel_enum channelx, uint32_t polarity); 690 /* configure number of DMA requests to be generated */ 691 void dmamux_request_generate_number_config(dmamux_generator_channel_enum channelx, uint32_t number); 692 /* configure trigger input identification */ 693 void dmamux_trigger_id_config(dmamux_generator_channel_enum channelx, uint32_t id); 694 695 /* DMAMUX interrupt and flag functions */ 696 /* get DMAMUX flag */ 697 FlagStatus dmamux_flag_get(dmamux_flag_enum flag); 698 /* clear DMAMUX flag */ 699 void dmamux_flag_clear(dmamux_flag_enum flag); 700 /* enable DMAMUX interrupt */ 701 void dmamux_interrupt_enable(dmamux_interrupt_enum interrupt); 702 /* disable DMAMUX interrupt */ 703 void dmamux_interrupt_disable(dmamux_interrupt_enum interrupt); 704 /* get DMAMUX interrupt flag */ 705 FlagStatus dmamux_interrupt_flag_get(dmamux_interrupt_flag_enum int_flag); 706 /* clear DMAMUX interrupt flag */ 707 void dmamux_interrupt_flag_clear(dmamux_interrupt_flag_enum int_flag); 708 709 #endif /* GD32A50X_DMA_H */ 710
