1 /*! 2 \file gd32a50x_can.h 3 \brief definitions for the CAN 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_CAN_H 36 #define GD32A50X_CAN_H 37 38 #include "gd32a50x.h" 39 40 /* CAN definitions */ 41 #define CAN0 CAN_BASE /*!< CAN0 base address */ 42 #define CAN1 (CAN_BASE + 0x00001000U) /*!< CAN1 base address */ 43 #define CAN_RAM(canx) ((uint32_t)((canx) + 0x00000080U)) /*!< can ram base address */ 44 #define CAN_PN_RAM(canx) ((uint32_t)(canx) + 0x00000B40U) /*!< Pretended Networking ram base address */ 45 46 /* registers definitions */ 47 #define CAN_CTL0(canx) REG32((canx) + 0x00000000U) /*!< CAN control register 0 */ 48 #define CAN_CTL1(canx) REG32((canx) + 0x00000004U) /*!< CAN control register 1 */ 49 #define CAN_TIMER(canx) REG32((canx) + 0x00000008U) /*!< CAN timer register */ 50 #define CAN_RMPUBF(canx) REG32((canx) + 0x00000010U) /*!< CAN receive mailbox public filter register */ 51 #define CAN_ERR0(canx) REG32((canx) + 0x0000001CU) /*!< CAN error register 0 */ 52 #define CAN_ERR1(canx) REG32((canx) + 0x00000020U) /*!< CAN error register 1 */ 53 #define CAN_INTEN(canx) REG32((canx) + 0x00000028U) /*!< CAN interrupt enable register */ 54 #define CAN_STAT(canx) REG32((canx) + 0x00000030U) /*!< CAN status register */ 55 #define CAN_CTL2(canx) REG32((canx) + 0x00000034U) /*!< CAN control register 2 */ 56 #define CAN_CRCC(canx) REG32((canx) + 0x00000044U) /*!< CAN crc for classical frame register */ 57 #define CAN_RFIFOPUBF(canx) REG32((canx) + 0x00000048U) /*!< CAN receive fifo public filter register */ 58 #define CAN_RFIFOIFMN(canx) REG32((canx) + 0x0000004CU) /*!< CAN receive fifo identifier filter matching number register */ 59 #define CAN_BT(canx) REG32((canx) + 0x00000050U) /*!< CAN bit timing register */ 60 #define CAN_RFIFOMPF0(canx) REG32((canx) + 0x00000880U) /*!< CAN receive fifo / mailbox private filter 0 register */ 61 #define CAN_RFIFOMPF1(canx) REG32((canx) + 0x00000884U) /*!< CAN receive fifo / mailbox private filter 1 register */ 62 #define CAN_RFIFOMPF2(canx) REG32((canx) + 0x00000888U) /*!< CAN receive fifo / mailbox private filter 2 register */ 63 #define CAN_RFIFOMPF3(canx) REG32((canx) + 0x0000088CU) /*!< CAN receive fifo / mailbox private filter 3 register */ 64 #define CAN_RFIFOMPF4(canx) REG32((canx) + 0x00000890U) /*!< CAN receive fifo / mailbox private filter 4 register */ 65 #define CAN_RFIFOMPF5(canx) REG32((canx) + 0x00000894U) /*!< CAN receive fifo / mailbox private filter 5 register */ 66 #define CAN_RFIFOMPF6(canx) REG32((canx) + 0x00000898U) /*!< CAN receive fifo / mailbox private filter 6 register */ 67 #define CAN_RFIFOMPF7(canx) REG32((canx) + 0x0000089CU) /*!< CAN receive fifo / mailbox private filter 7 register */ 68 #define CAN_RFIFOMPF8(canx) REG32((canx) + 0x000008A0U) /*!< CAN receive fifo / mailbox private filter 8 register */ 69 #define CAN_RFIFOMPF9(canx) REG32((canx) + 0x000008A4U) /*!< CAN receive fifo / mailbox private filter 9 register */ 70 #define CAN_RFIFOMPF10(canx) REG32((canx) + 0x000008A8U) /*!< CAN receive fifo / mailbox private filter 10 register */ 71 #define CAN_RFIFOMPF11(canx) REG32((canx) + 0x000008ACU) /*!< CAN receive fifo / mailbox private filter 11 register */ 72 #define CAN_RFIFOMPF12(canx) REG32((canx) + 0x000008B0U) /*!< CAN receive fifo / mailbox private filter 12 register */ 73 #define CAN_RFIFOMPF13(canx) REG32((canx) + 0x000008B4U) /*!< CAN receive fifo / mailbox private filter 13 register */ 74 #define CAN_RFIFOMPF14(canx) REG32((canx) + 0x000008B8U) /*!< CAN receive fifo / mailbox private filter 14 register */ 75 #define CAN_RFIFOMPF15(canx) REG32((canx) + 0x000008BCU) /*!< CAN receive fifo / mailbox private filter 15 register */ 76 #define CAN_RFIFOMPF16(canx) REG32((canx) + 0x000008C0U) /*!< CAN receive fifo / mailbox private filter 16 register */ 77 #define CAN_RFIFOMPF17(canx) REG32((canx) + 0x000008C4U) /*!< CAN receive fifo / mailbox private filter 17 register */ 78 #define CAN_RFIFOMPF18(canx) REG32((canx) + 0x000008C8U) /*!< CAN receive fifo / mailbox private filter 18 register */ 79 #define CAN_RFIFOMPF19(canx) REG32((canx) + 0x000008CCU) /*!< CAN receive fifo / mailbox private filter 19 register */ 80 #define CAN_RFIFOMPF20(canx) REG32((canx) + 0x000008D0U) /*!< CAN receive fifo / mailbox private filter 20 register */ 81 #define CAN_RFIFOMPF21(canx) REG32((canx) + 0x000008D4U) /*!< CAN receive fifo / mailbox private filter 21 register */ 82 #define CAN_RFIFOMPF22(canx) REG32((canx) + 0x000008D8U) /*!< CAN receive fifo / mailbox private filter 22 register */ 83 #define CAN_RFIFOMPF23(canx) REG32((canx) + 0x000008DCU) /*!< CAN receive fifo / mailbox private filter 23 register */ 84 #define CAN_RFIFOMPF24(canx) REG32((canx) + 0x000008E0U) /*!< CAN receive fifo / mailbox private filter 24 register */ 85 #define CAN_RFIFOMPF25(canx) REG32((canx) + 0x000008E4U) /*!< CAN receive fifo / mailbox private filter 25 register */ 86 #define CAN_RFIFOMPF26(canx) REG32((canx) + 0x000008E8U) /*!< CAN receive fifo / mailbox private filter 26 register */ 87 #define CAN_RFIFOMPF27(canx) REG32((canx) + 0x000008ECU) /*!< CAN receive fifo / mailbox private filter 27 register */ 88 #define CAN_RFIFOMPF28(canx) REG32((canx) + 0x000008F0U) /*!< CAN receive fifo / mailbox private filter 28 register */ 89 #define CAN_RFIFOMPF29(canx) REG32((canx) + 0x000008F4U) /*!< CAN receive fifo / mailbox private filter 29 register */ 90 #define CAN_RFIFOMPF30(canx) REG32((canx) + 0x000008F8U) /*!< CAN receive fifo / mailbox private filter 30 register */ 91 #define CAN_RFIFOMPF31(canx) REG32((canx) + 0x000008FCU) /*!< CAN receive fifo / mailbox private filter 31 register */ 92 #define CAN_PN_CTL0(canx) REG32((canx) + 0x00000B00U) /*!< Pretended Networking mode control register 0 */ 93 #define CAN_PN_TO(canx) REG32((canx) + 0x00000B04U) /*!< Pretended Networking mode timeout register */ 94 #define CAN_PN_STAT(canx) REG32((canx) + 0x00000B08U) /*!< Pretended Networking mode status register */ 95 #define CAN_PN_EID0(canx) REG32((canx) + 0x00000B0CU) /*!< Pretended Networking mode expected identifier 0 register */ 96 #define CAN_PN_EDLC(canx) REG32((canx) + 0x00000B10U) /*!< Pretended Networking mode expected dlc register */ 97 #define CAN_PN_EDL0(canx) REG32((canx) + 0x00000B14U) /*!< Pretended Networking mode expected data low 0 register */ 98 #define CAN_PN_EDL1(canx) REG32((canx) + 0x00000B18U) /*!< Pretended Networking mode expected data low 1 register */ 99 #define CAN_PN_IFEID1(canx) REG32((canx) + 0x00000B1CU) /*!< Pretended Networking mode identifier filter / expected identifier 1 register */ 100 #define CAN_PN_DF0EDH0(canx) REG32((canx) + 0x00000B20U) /*!< Pretended Networking mode data 0 filter / expected data high 0 register */ 101 #define CAN_PN_DF1EDH1(canx) REG32((canx) + 0x00000B24U) /*!< Pretended Networking mode data 1 filter / expected data high 1 register */ 102 #define CAN_PN_RWM0CS(canx) REG32((canx) + 0x00000B40U) /*!< Pretended Networking mode received wakeup mailbox 0 control status information register */ 103 #define CAN_PN_RWM0I(canx) REG32((canx) + 0x00000B44U) /*!< Pretended Networking mode received wakeup mailbox 0 identifier register */ 104 #define CAN_PN_RWM0D0(canx) REG32((canx) + 0x00000B48U) /*!< Pretended Networking mode received wakeup mailbox 0 data 0 register */ 105 #define CAN_PN_RWM0D1(canx) REG32((canx) + 0x00000B4CU) /*!< Pretended Networking mode received wakeup mailbox 0 data 1 register */ 106 #define CAN_PN_RWM1CS(canx) REG32((canx) + 0x00000B50U) /*!< Pretended Networking mode received wakeup mailbox 1 control status information register */ 107 #define CAN_PN_RWM1I(canx) REG32((canx) + 0x00000B54U) /*!< Pretended Networking mode received wakeup mailbox 1 identifier register */ 108 #define CAN_PN_RWM1D0(canx) REG32((canx) + 0x00000B58U) /*!< Pretended Networking mode received wakeup mailbox 1 data 0 register */ 109 #define CAN_PN_RWM1D1(canx) REG32((canx) + 0x00000B5CU) /*!< Pretended Networking mode received wakeup mailbox 1 data 1 register */ 110 #define CAN_PN_RWM2CS(canx) REG32((canx) + 0x00000B60U) /*!< Pretended Networking mode received wakeup mailbox 2 control status information register */ 111 #define CAN_PN_RWM2I(canx) REG32((canx) + 0x00000B64U) /*!< Pretended Networking mode received wakeup mailbox 2 identifier register */ 112 #define CAN_PN_RWM2D0(canx) REG32((canx) + 0x00000B68U) /*!< Pretended Networking mode received wakeup mailbox 2 data 0 register */ 113 #define CAN_PN_RWM2D1(canx) REG32((canx) + 0x00000B6CU) /*!< Pretended Networking mode received wakeup mailbox 2 data 1 register */ 114 #define CAN_PN_RWM3CS(canx) REG32((canx) + 0x00000B70U) /*!< Pretended Networking mode received wakeup mailbox 3 control status information register */ 115 #define CAN_PN_RWM3I(canx) REG32((canx) + 0x00000B74U) /*!< Pretended Networking mode received wakeup mailbox 3 identifier register */ 116 #define CAN_PN_RWM3D0(canx) REG32((canx) + 0x00000B78U) /*!< Pretended Networking mode received wakeup mailbox 3 data 0 register */ 117 #define CAN_PN_RWM3D1(canx) REG32((canx) + 0x00000B7CU) /*!< Pretended Networking mode received wakeup mailbox 3 data 1 register */ 118 #define CAN_FDCTL(canx) REG32((canx) + 0x00000C00U) /*!< CAN FD control register */ 119 #define CAN_FDBT(canx) REG32((canx) + 0x00000C04U) /*!< CAN bit timing register */ 120 #define CAN_CRCCFD(canx) REG32((canx) + 0x00000C08U) /*!< CAN CRC for classical and FD frame register */ 121 122 /* bits definitions */ 123 /* CAN_CTL0 */ 124 #define CAN_CTL0_MSZ BITS(0, 4) /*!< memory size */ 125 #define CAN_CTL0_FS BITS(8, 9) /*!< format selection */ 126 #define CAN_CTL0_FDEN BIT(11) /*!< CAN FD operation enable */ 127 #define CAN_CTL0_MST BIT(12) /*!< mailbox stop transmission */ 128 #define CAN_CTL0_LAPRIOEN BIT(13) /*!< enable local arbitration priority */ 129 #define CAN_CTL0_PNMOD BIT(14) /*!< Pretended Networking mode selection */ 130 #define CAN_CTL0_DMAEN BIT(15) /*!< enable DMA */ 131 #define CAN_CTL0_RPFQEN BIT(16) /*!< enable rx private filters enable & rx mailbox queue */ 132 #define CAN_CTL0_SRDIS BIT(17) /*!< enable self reception */ 133 #define CAN_CTL0_PNS BIT(18) /*!< Pretended Networking state */ 134 #define CAN_CTL0_PNEN BIT(19) /*!< enable Pretended Networking mode */ 135 #define CAN_CTL0_LPS BIT(20) /*!< low power state */ 136 #define CAN_CTL0_WERREN BIT(21) /*!< enable error warning */ 137 #define CAN_CTL0_INAS BIT(24) /*!< inactive mode state */ 138 #define CAN_CTL0_SWRST BIT(25) /*!< software reset */ 139 #define CAN_CTL0_NRDY BIT(27) /*!< not ready */ 140 #define CAN_CTL0_HALT BIT(28) /*!< halt CAN */ 141 #define CAN_CTL0_RFEN BIT(29) /*!< rx fifo enable */ 142 #define CAN_CTL0_INAMOD BIT(30) /*!< enable inactive mode */ 143 #define CAN_CTL0_CANDIS BIT(31) /*!< disable CAN */ 144 145 /* CAN_CTL1 */ 146 #define CAN_CTL1_MMOD BIT(3) /*!< monitor mode */ 147 #define CAN_CTL1_MTO BIT(4) /*!< mailbox transmission order */ 148 #define CAN_CTL1_TSYNC BIT(5) /*!< enable time synchronization */ 149 #define CAN_CTL1_ABORDIS BIT(6) /*!< not enable automatic bus off recovery */ 150 #define CAN_CTL1_BSPMOD BIT(7) /*!< bit sampling mode */ 151 #define CAN_CTL1_RWERRIE BIT(10) /*!< enable rx error warning interrupt */ 152 #define CAN_CTL1_TWERRIE BIT(11) /*!< enable tx error warning interrupt */ 153 #define CAN_CTL1_LSCMOD BIT(12) /*!< loopback and silent communication mode */ 154 #define CAN_CTL1_ERRSIE BIT(14) /*!< enable error summary interrupt */ 155 #define CAN_CTL1_BOIE BIT(15) /*!< enable bus off interrupt */ 156 157 /* CAN_TIMER */ 158 #define CAN_TIMER_CNT BITS(0,15) /*!< counter value */ 159 160 /* CAN_RMPUBF */ 161 #define CAN_RMPUBF_MFD0 BIT(0) /*!< mailbox filter data bit 0 */ 162 #define CAN_RMPUBF_MFD1 BIT(1) /*!< mailbox filter data bit 1 */ 163 #define CAN_RMPUBF_MFD2 BIT(2) /*!< mailbox filter data bit 2 */ 164 #define CAN_RMPUBF_MFD3 BIT(3) /*!< mailbox filter data bit 3 */ 165 #define CAN_RMPUBF_MFD4 BIT(4) /*!< mailbox filter data bit 4 */ 166 #define CAN_RMPUBF_MFD5 BIT(5) /*!< mailbox filter data bit 5 */ 167 #define CAN_RMPUBF_MFD6 BIT(6) /*!< mailbox filter data bit 6 */ 168 #define CAN_RMPUBF_MFD7 BIT(7) /*!< mailbox filter data bit 7 */ 169 #define CAN_RMPUBF_MFD8 BIT(8) /*!< mailbox filter data bit 8 */ 170 #define CAN_RMPUBF_MFD9 BIT(9) /*!< mailbox filter data bit 9 */ 171 #define CAN_RMPUBF_MFD10 BIT(10) /*!< mailbox filter data bit 10 */ 172 #define CAN_RMPUBF_MFD11 BIT(11) /*!< mailbox filter data bit 11 */ 173 #define CAN_RMPUBF_MFD12 BIT(12) /*!< mailbox filter data bit 12 */ 174 #define CAN_RMPUBF_MFD13 BIT(13) /*!< mailbox filter data bit 13 */ 175 #define CAN_RMPUBF_MFD14 BIT(14) /*!< mailbox filter data bit 14 */ 176 #define CAN_RMPUBF_MFD15 BIT(15) /*!< mailbox filter data bit 15 */ 177 #define CAN_RMPUBF_MFD16 BIT(16) /*!< mailbox filter data bit 16 */ 178 #define CAN_RMPUBF_MFD17 BIT(17) /*!< mailbox filter data bit 17 */ 179 #define CAN_RMPUBF_MFD18 BIT(18) /*!< mailbox filter data bit 18 */ 180 #define CAN_RMPUBF_MFD19 BIT(19) /*!< mailbox filter data bit 19 */ 181 #define CAN_RMPUBF_MFD20 BIT(20) /*!< mailbox filter data bit 20 */ 182 #define CAN_RMPUBF_MFD21 BIT(21) /*!< mailbox filter data bit 21 */ 183 #define CAN_RMPUBF_MFD22 BIT(22) /*!< mailbox filter data bit 22 */ 184 #define CAN_RMPUBF_MFD23 BIT(23) /*!< mailbox filter data bit 23 */ 185 #define CAN_RMPUBF_MFD24 BIT(24) /*!< mailbox filter data bit 24 */ 186 #define CAN_RMPUBF_MFD25 BIT(25) /*!< mailbox filter data bit 25 */ 187 #define CAN_RMPUBF_MFD26 BIT(26) /*!< mailbox filter data bit 26 */ 188 #define CAN_RMPUBF_MFD27 BIT(27) /*!< mailbox filter data bit 27 */ 189 #define CAN_RMPUBF_MFD28 BIT(28) /*!< mailbox filter data bit 28 */ 190 #define CAN_RMPUBF_MFD29 BIT(29) /*!< mailbox filter data bit 29 */ 191 #define CAN_RMPUBF_MFD30 BIT(30) /*!< mailbox filter data bit 30 */ 192 #define CAN_RMPUBF_MFD31 BIT(31) /*!< mailbox filter data bit 31 */ 193 194 /* CAN_ERR0 */ 195 #define CAN_ERR0_TECNT BITS(0, 7) /*!< transmit error count defined by the CAN standard */ 196 #define CAN_ERR0_RECNT BITS(8, 15) /*!< receive error count defined by the CAN standard */ 197 #define CAN_ERR0_TEFCNT BITS(16, 23) /*!< transmit error count for the data phase of FD frames with BRS bit set */ 198 #define CAN_ERR0_REFCNT BITS(24, 31) /*!< receive error count for the data phase of FD frames with BRS bit set */ 199 200 /* CAN_ERR1 */ 201 #define CAN_ERR1_ERRSF BIT(1) /*!< error summary flag */ 202 #define CAN_ERR1_BOF BIT(2) /*!< bus off flag */ 203 #define CAN_ERR1_RS BIT(3) /*!< receiving state */ 204 #define CAN_ERR1_ERRSI BITS(4, 5) /*!< error state indicator */ 205 #define CAN_ERR1_TS BIT(6) /*!< transmitting state */ 206 #define CAN_ERR1_IDLEF BIT(7) /*!< idle flag */ 207 #define CAN_ERR1_RWERRF BIT(8) /*!< rx error warning flag */ 208 #define CAN_ERR1_TWERRF BIT(9) /*!< tx error warning flag */ 209 #define CAN_ERR1_STFERR BIT(10) /*!< stuff error */ 210 #define CAN_ERR1_FMERR BIT(11) /*!< form error */ 211 #define CAN_ERR1_CRCERR BIT(12) /*!< CRC error */ 212 #define CAN_ERR1_ACKERR BIT(13) /*!< ACK error */ 213 #define CAN_ERR1_BDERR BIT(14) /*!< bit dominant error for all format frames */ 214 #define CAN_ERR1_BRERR BIT(15) /*!< bit recessive error for all format frames */ 215 #define CAN_ERR1_RWERRIF BIT(16) /*!< rx error warning interrupt flag */ 216 #define CAN_ERR1_TWERRIF BIT(17) /*!< tx error warning interrupt flag */ 217 #define CAN_ERR1_SYN BIT(18) /*!< synchronization flag */ 218 #define CAN_ERR1_BORF BIT(19) /*!< bus off recovery flag */ 219 #define CAN_ERR1_ERRFSF BIT(20) /*!< error summary flag for data phase of FD frames with BRS bit set */ 220 #define CAN_ERR1_ERROVR BIT(21) /*!< error overrun */ 221 #define CAN_ERR1_STFFERR BIT(26) /*!< stuff error in data phase of FD frames with BRS bit set */ 222 #define CAN_ERR1_FMFERR BIT(27) /*!< form error in data phase of FD frames with BRS bit set */ 223 #define CAN_ERR1_CRCFERR BIT(28) /*!< CRC error in data phase of FD frames with BRS bit set */ 224 #define CAN_ERR1_BDFERR BIT(30) /*!< bit dominant error in data phase of FD frames with BRS bit set */ 225 #define CAN_ERR1_BRFERR BIT(31) /*!< bit recessive error in data phase of FD frames with BRS bit set */ 226 227 /* CAN_INTEN */ 228 #define CAN_INTEN_MIE0 BIT(0) /*!< enable message 0 transmission and reception interrupt */ 229 #define CAN_INTEN_MIE1 BIT(1) /*!< enable message 1 transmission and reception interrupt */ 230 #define CAN_INTEN_MIE2 BIT(2) /*!< enable message 2 transmission and reception interrupt */ 231 #define CAN_INTEN_MIE3 BIT(3) /*!< enable message 3 transmission and reception interrupt */ 232 #define CAN_INTEN_MIE4 BIT(4) /*!< enable message 4 transmission and reception interrupt */ 233 #define CAN_INTEN_MIE5 BIT(5) /*!< enable message 5 transmission and reception interrupt */ 234 #define CAN_INTEN_MIE6 BIT(6) /*!< enable message 6 transmission and reception interrupt */ 235 #define CAN_INTEN_MIE7 BIT(7) /*!< enable message 7 transmission and reception interrupt */ 236 #define CAN_INTEN_MIE8 BIT(8) /*!< enable message 8 transmission and reception interrupt */ 237 #define CAN_INTEN_MIE9 BIT(9) /*!< enable message 9 transmission and reception interrupt */ 238 #define CAN_INTEN_MIE10 BIT(10) /*!< enable message 10 transmission and reception interrupt */ 239 #define CAN_INTEN_MIE11 BIT(11) /*!< enable message 11 transmission and reception interrupt */ 240 #define CAN_INTEN_MIE12 BIT(12) /*!< enable message 12 transmission and reception interrupt */ 241 #define CAN_INTEN_MIE13 BIT(13) /*!< enable message 13 transmission and reception interrupt */ 242 #define CAN_INTEN_MIE14 BIT(14) /*!< enable message 14 transmission and reception interrupt */ 243 #define CAN_INTEN_MIE15 BIT(15) /*!< enable message 15 transmission and reception interrupt */ 244 #define CAN_INTEN_MIE16 BIT(16) /*!< enable message 16 transmission and reception interrupt */ 245 #define CAN_INTEN_MIE17 BIT(17) /*!< enable message 17 transmission and reception interrupt */ 246 #define CAN_INTEN_MIE18 BIT(18) /*!< enable message 18 transmission and reception interrupt */ 247 #define CAN_INTEN_MIE19 BIT(19) /*!< enable message 19 transmission and reception interrupt */ 248 #define CAN_INTEN_MIE20 BIT(20) /*!< enable message 20 transmission and reception interrupt */ 249 #define CAN_INTEN_MIE21 BIT(21) /*!< enable message 21 transmission and reception interrupt */ 250 #define CAN_INTEN_MIE22 BIT(22) /*!< enable message 22 transmission and reception interrupt */ 251 #define CAN_INTEN_MIE23 BIT(23) /*!< enable message 23 transmission and reception interrupt */ 252 #define CAN_INTEN_MIE24 BIT(24) /*!< enable message 24 transmission and reception interrupt */ 253 #define CAN_INTEN_MIE25 BIT(25) /*!< enable message 25 transmission and reception interrupt */ 254 #define CAN_INTEN_MIE26 BIT(26) /*!< enable message 26 transmission and reception interrupt */ 255 #define CAN_INTEN_MIE27 BIT(27) /*!< enable message 27 transmission and reception interrupt */ 256 #define CAN_INTEN_MIE28 BIT(28) /*!< enable message 28 transmission and reception interrupt */ 257 #define CAN_INTEN_MIE29 BIT(29) /*!< enable message 29 transmission and reception interrupt */ 258 #define CAN_INTEN_MIE30 BIT(30) /*!< enable message 30 transmission and reception interrupt */ 259 #define CAN_INTEN_MIE31 BIT(31) /*!< enable message 31 transmission and reception interrupt */ 260 261 /* CAN_STAT */ 262 #define CAN_STAT_MS0_RFC BIT(0) /*!< mailbox 0 state / clear rx fifo bit */ 263 #define CAN_STAT_MS1_RES BIT(1) /*!< mailbox 1 state */ 264 #define CAN_STAT_MS2_RES BIT(2) /*!< mailbox 2 state */ 265 #define CAN_STAT_MS3_RES BIT(3) /*!< mailbox 3 state */ 266 #define CAN_STAT_MS4_RES BIT(4) /*!< mailbox 4 state */ 267 #define CAN_STAT_MS5_RFNE BIT(5) /*!< mailbox 5 state / rx fifo not empty */ 268 #define CAN_STAT_MS6_RFW BIT(6) /*!< mailbox 6 state / rx fifo warning */ 269 #define CAN_STAT_MS7_RFO BIT(7) /*!< mailbox 7 state / rx fifo overflow */ 270 #define CAN_STAT_MS8 BIT(8) /*!< mailbox 8 state */ 271 #define CAN_STAT_MS9 BIT(9) /*!< mailbox 9 state */ 272 #define CAN_STAT_MS10 BIT(10) /*!< mailbox 10 state */ 273 #define CAN_STAT_MS11 BIT(11) /*!< mailbox 11 state */ 274 #define CAN_STAT_MS12 BIT(12) /*!< mailbox 12 state */ 275 #define CAN_STAT_MS13 BIT(13) /*!< mailbox 13 state */ 276 #define CAN_STAT_MS14 BIT(14) /*!< mailbox 14 state */ 277 #define CAN_STAT_MS15 BIT(15) /*!< mailbox 15 state */ 278 #define CAN_STAT_MS16 BIT(16) /*!< mailbox 16 state */ 279 #define CAN_STAT_MS17 BIT(17) /*!< mailbox 17 state */ 280 #define CAN_STAT_MS18 BIT(18) /*!< mailbox 18 state */ 281 #define CAN_STAT_MS19 BIT(19) /*!< mailbox 19 state */ 282 #define CAN_STAT_MS20 BIT(20) /*!< mailbox 20 state */ 283 #define CAN_STAT_MS21 BIT(21) /*!< mailbox 21 state */ 284 #define CAN_STAT_MS22 BIT(22) /*!< mailbox 22 state */ 285 #define CAN_STAT_MS23 BIT(23) /*!< mailbox 23 state */ 286 #define CAN_STAT_MS24 BIT(24) /*!< mailbox 24 state */ 287 #define CAN_STAT_MS25 BIT(25) /*!< mailbox 25 state */ 288 #define CAN_STAT_MS26 BIT(26) /*!< mailbox 26 state */ 289 #define CAN_STAT_MS27 BIT(27) /*!< mailbox 27 state */ 290 #define CAN_STAT_MS28 BIT(28) /*!< mailbox 28 state */ 291 #define CAN_STAT_MS29 BIT(29) /*!< mailbox 29 state */ 292 #define CAN_STAT_MS30 BIT(30) /*!< mailbox 30 state */ 293 #define CAN_STAT_MS31 BIT(31) /*!< mailbox 31 state */ 294 295 /* CAN_CTL2 */ 296 #define CAN_CTL2_EFDIS BIT(11) /*!< disable edge filtering */ 297 #define CAN_CTL2_ISO BIT(12) /*!< ISO CAN FD */ 298 #define CAN_CTL2_PREEN BIT(14) /*!< protocol exception detection enable by CAN standard */ 299 #define CAN_CTL2_ITSRC BIT(15) /*!< internal counter source */ 300 #define CAN_CTL2_IDERTR_RMF BIT(16) /*!< IDE and RTR field filter type for rx mailbox reception */ 301 #define CAN_CTL2_RRFRMS BIT(17) /*!< remote request frame is stored */ 302 #define CAN_CTL2_RFO BIT(18) /*!< receive filter order */ 303 #define CAN_CTL2_ASD BITS(19, 23) /*!< arbitration start delay */ 304 #define CAN_CTL2_RFFN BITS(24, 27) /*!< rx fifo filter number */ 305 #define CAN_CTL2_BORIE BIT(30) /*!< enable bus off recovery interrupt */ 306 #define CAN_CTL2_ERRFSIE BIT(31) /*!< error summary interrupt enable bit for data phase of FD frames with BRS bit set */ 307 308 /* CAN_CRCC */ 309 #define CAN_CRCC_CRCTC BITS(0, 14) /*!< transmitted CRC value for classical frames */ 310 #define CAN_CRCC_ANTM BITS(16, 20) /*!< associated number of mailbox for transmitting the CRCTC[14:0] value */ 311 312 /* CAN_RFIFOPUBF */ 313 #define CAN_RFIFOPUBF_FFD0 BIT(0) /*!< rx fifo filter data bit 0 */ 314 #define CAN_RFIFOPUBF_FFD1 BIT(1) /*!< rx fifo filter data bit 1 */ 315 #define CAN_RFIFOPUBF_FFD2 BIT(2) /*!< rx fifo filter data bit 2 */ 316 #define CAN_RFIFOPUBF_FFD3 BIT(3) /*!< rx fifo filter data bit 3 */ 317 #define CAN_RFIFOPUBF_FFD4 BIT(4) /*!< rx fifo filter data bit 4 */ 318 #define CAN_RFIFOPUBF_FFD5 BIT(5) /*!< rx fifo filter data bit 5 */ 319 #define CAN_RFIFOPUBF_FFD6 BIT(6) /*!< rx fifo filter data bit 6 */ 320 #define CAN_RFIFOPUBF_FFD7 BIT(7) /*!< rx fifo filter data bit 7 */ 321 #define CAN_RFIFOPUBF_FFD8 BIT(8) /*!< rx fifo filter data bit 8 */ 322 #define CAN_RFIFOPUBF_FFD9 BIT(9) /*!< rx fifo filter data bit 9 */ 323 #define CAN_RFIFOPUBF_FFD10 BIT(10) /*!< rx fifo filter data bit 10 */ 324 #define CAN_RFIFOPUBF_FFD11 BIT(11) /*!< rx fifo filter data bit 11 */ 325 #define CAN_RFIFOPUBF_FFD12 BIT(12) /*!< rx fifo filter data bit 12 */ 326 #define CAN_RFIFOPUBF_FFD13 BIT(13) /*!< rx fifo filter data bit 13 */ 327 #define CAN_RFIFOPUBF_FFD14 BIT(14) /*!< rx fifo filter data bit 14 */ 328 #define CAN_RFIFOPUBF_FFD15 BIT(15) /*!< rx fifo filter data bit 15 */ 329 #define CAN_RFIFOPUBF_FFD16 BIT(16) /*!< rx fifo filter data bit 16 */ 330 #define CAN_RFIFOPUBF_FFD17 BIT(17) /*!< rx fifo filter data bit 17 */ 331 #define CAN_RFIFOPUBF_FFD18 BIT(18) /*!< rx fifo filter data bit 18 */ 332 #define CAN_RFIFOPUBF_FFD19 BIT(19) /*!< rx fifo filter data bit 19 */ 333 #define CAN_RFIFOPUBF_FFD20 BIT(20) /*!< rx fifo filter data bit 20 */ 334 #define CAN_RFIFOPUBF_FFD21 BIT(21) /*!< rx fifo filter data bit 21 */ 335 #define CAN_RFIFOPUBF_FFD22 BIT(22) /*!< rx fifo filter data bit 22 */ 336 #define CAN_RFIFOPUBF_FFD23 BIT(23) /*!< rx fifo filter data bit 23 */ 337 #define CAN_RFIFOPUBF_FFD24 BIT(24) /*!< rx fifo filter data bit 24 */ 338 #define CAN_RFIFOPUBF_FFD25 BIT(25) /*!< rx fifo filter data bit 25 */ 339 #define CAN_RFIFOPUBF_FFD26 BIT(26) /*!< rx fifo filter data bit 26 */ 340 #define CAN_RFIFOPUBF_FFD27 BIT(27) /*!< rx fifo filter data bit 27 */ 341 #define CAN_RFIFOPUBF_FFD28 BIT(28) /*!< rx fifo filter data bit 28 */ 342 #define CAN_RFIFOPUBF_FFD29 BIT(29) /*!< rx fifo filter data bit 29 */ 343 #define CAN_RFIFOPUBF_FFD30 BIT(30) /*!< rx fifo filter data bit 30 */ 344 #define CAN_RFIFOPUBF_FFD31 BIT(31) /*!< rx fifo filter data bit 31 */ 345 346 /* CAN_RFIFOIFMN */ 347 #define CAN_RFIFOIFMN_IDFMN BITS(0, 8) /*!< identifier filter matching number */ 348 349 /* CAN_BT */ 350 #define CAN_BT_PBS2 BITS(0, 4) /*!< phase buffer segment 2 */ 351 #define CAN_BT_PBS1 BITS(5, 9) /*!< phase buffer segment 1 */ 352 #define CAN_BT_PTS BITS(10, 15) /*!< propagation time segment */ 353 #define CAN_BT_SJW BITS(16, 20) /*!< resynchronization jump width */ 354 #define CAN_BT_BAUDPSC BITS(21, 30) /*!< baud rate prescaler */ 355 356 /* CAN_RFIFOMPFx, x = 0..31 */ 357 #define CAN_RFIFOMPF_FMFD0 BIT(0) /*!< fifo / mailbox filter data bit 0 */ 358 #define CAN_RFIFOMPF_FMFD1 BIT(1) /*!< fifo / mailbox filter data bit 1 */ 359 #define CAN_RFIFOMPF_FMFD2 BIT(2) /*!< fifo / mailbox filter data bit 2 */ 360 #define CAN_RFIFOMPF_FMFD3 BIT(3) /*!< fifo / mailbox filter data bit 3 */ 361 #define CAN_RFIFOMPF_FMFD4 BIT(4) /*!< fifo / mailbox filter data bit 4 */ 362 #define CAN_RFIFOMPF_FMFD5 BIT(5) /*!< fifo / mailbox filter data bit 5 */ 363 #define CAN_RFIFOMPF_FMFD6 BIT(6) /*!< fifo / mailbox filter data bit 6 */ 364 #define CAN_RFIFOMPF_FMFD7 BIT(7) /*!< fifo / mailbox filter data bit 7 */ 365 #define CAN_RFIFOMPF_FMFD8 BIT(8) /*!< fifo / mailbox filter data bit 8 */ 366 #define CAN_RFIFOMPF_FMFD9 BIT(9) /*!< fifo / mailbox filter data bit 9 */ 367 #define CAN_RFIFOMPF_FMFD10 BIT(10) /*!< fifo / mailbox filter data bit 10 */ 368 #define CAN_RFIFOMPF_FMFD11 BIT(11) /*!< fifo / mailbox filter data bit 11 */ 369 #define CAN_RFIFOMPF_FMFD12 BIT(12) /*!< fifo / mailbox filter data bit 12 */ 370 #define CAN_RFIFOMPF_FMFD13 BIT(13) /*!< fifo / mailbox filter data bit 13 */ 371 #define CAN_RFIFOMPF_FMFD14 BIT(14) /*!< fifo / mailbox filter data bit 14 */ 372 #define CAN_RFIFOMPF_FMFD15 BIT(15) /*!< fifo / mailbox filter data bit 15 */ 373 #define CAN_RFIFOMPF_FMFD16 BIT(16) /*!< fifo / mailbox filter data bit 16 */ 374 #define CAN_RFIFOMPF_FMFD17 BIT(17) /*!< fifo / mailbox filter data bit 17 */ 375 #define CAN_RFIFOMPF_FMFD18 BIT(18) /*!< fifo / mailbox filter data bit 18 */ 376 #define CAN_RFIFOMPF_FMFD19 BIT(19) /*!< fifo / mailbox filter data bit 19 */ 377 #define CAN_RFIFOMPF_FMFD20 BIT(20) /*!< fifo / mailbox filter data bit 20 */ 378 #define CAN_RFIFOMPF_FMFD21 BIT(21) /*!< fifo / mailbox filter data bit 21 */ 379 #define CAN_RFIFOMPF_FMFD22 BIT(22) /*!< fifo / mailbox filter data bit 22 */ 380 #define CAN_RFIFOMPF_FMFD23 BIT(23) /*!< fifo / mailbox filter data bit 23 */ 381 #define CAN_RFIFOMPF_FMFD24 BIT(24) /*!< fifo / mailbox filter data bit 24 */ 382 #define CAN_RFIFOMPF_FMFD25 BIT(25) /*!< fifo / mailbox filter data bit 25 */ 383 #define CAN_RFIFOMPF_FMFD26 BIT(26) /*!< fifo / mailbox filter data bit 26 */ 384 #define CAN_RFIFOMPF_FMFD27 BIT(27) /*!< fifo / mailbox filter data bit 27 */ 385 #define CAN_RFIFOMPF_FMFD28 BIT(28) /*!< fifo / mailbox filter data bit 28 */ 386 #define CAN_RFIFOMPF_FMFD29 BIT(29) /*!< fifo / mailbox filter data bit 29 */ 387 #define CAN_RFIFOMPF_FMFD30 BIT(30) /*!< fifo / mailbox filter data bit 30 */ 388 #define CAN_RFIFOMPF_FMFD31 BIT(31) /*!< fifo / mailbox filter data bit 31 */ 389 390 /* CAN_PN_CTL0 */ 391 #define CAN_PN_CTL0_FFT BITS(0, 1) /*!< frame filtering type in Pretended Networking mode */ 392 #define CAN_PN_CTL0_IDFT BITS(2, 3) /*!< ID field filtering type in Pretended Networking mode */ 393 #define CAN_PN_CTL0_DATAFT BITS(4, 5) /*!< data field filtering type in Pretended Networking mode */ 394 #define CAN_PN_CTL0_NMM BITS(8, 15) /*!< number of messages matching times */ 395 #define CAN_PN_CTL0_WMIE BIT(16) /*!< enable wakeup match interrupt */ 396 #define CAN_PN_CTL0_WTOIE BIT(17) /*!< enable wakeup timeout interrupt */ 397 398 /* CAN_PN_TO */ 399 #define CAN_PN_TO_WTO BITS(0, 15) /*!< wakeup timeout */ 400 401 /* CAN_PN_STAT */ 402 #define CAN_PN_STAT_MMCNTS BIT(7) /*!< matching message counter state */ 403 #define CAN_PN_STAT_MMCNT BITS(8, 15) /*!< matching message counter in Pretended Networking mode */ 404 #define CAN_PN_STAT_WMS BIT(16) /*!< wakeup match flag status */ 405 #define CAN_PN_STAT_WTOS BIT(17) /*!< wakeup timeout flag status */ 406 407 /* CAN_PN_EID0 */ 408 #define CAN_PN_EID0_EID_ELT BITS(0, 28) /*!< expected ID field / expected ID low threshold in Pretended Networking mode */ 409 #define CAN_PN_EID0_ERTR BIT(29) /*!< expected RTR in Pretended Networking mode */ 410 #define CAN_PN_EID0_EIDE BIT(30) /*!< expected IDE in Pretended Networking mode */ 411 412 /* CAN_PN_EDLC */ 413 #define CAN_PN_EDLC_DLCEHT BITS(0, 3) /*!< DLC expected high threshold in Pretended Networking mode */ 414 #define CAN_PN_EDLC_DLCELT BITS(16, 19) /*!< DLC expected low threshold in Pretended Networking mode */ 415 416 /* CAN_PN_EDL0 */ 417 #define CAN_PN_EDL0_DB3ELT BITS(0, 7) /*!< data byte 3 expected low threshold in Pretended Networking mode */ 418 #define CAN_PN_EDL0_DB2ELT BITS(8, 15) /*!< data byte 2 expected low threshold in Pretended Networking mode */ 419 #define CAN_PN_EDL0_DB1ELT BITS(16, 23) /*!< data byte 1 expected low threshold in Pretended Networking mode */ 420 #define CAN_PN_EDL0_DB0ELT BITS(24, 31) /*!< data byte 0 expected low threshold in Pretended Networking mode */ 421 422 /* CAN_PN_EDL1 */ 423 #define CAN_PN_EDL1_DB7ELT BITS(0, 7) /*!< data byte 7 expected low threshold in Pretended Networking mode */ 424 #define CAN_PN_EDL1_DB6ELT BITS(8, 15) /*!< data byte 6 expected low threshold in Pretended Networking mode */ 425 #define CAN_PN_EDL1_DB5ELT BITS(16, 23) /*!< data byte 5 expected low threshold in Pretended Networking mode */ 426 #define CAN_PN_EDL1_DB4ELT BITS(24, 31) /*!< data byte 4 expected low threshold in Pretended Networking mode */ 427 428 /* CAN_PN_IFEID1 */ 429 #define CAN_PN_IFEID1_IDFD_EHT BITS(0, 28) /*!< IDE filter data in Pretended Networking mode */ 430 #define CAN_PN_IFEID1_RTRFD BIT(29) /*!< RTR filter data in Pretended Networking mode */ 431 #define CAN_PN_IFEID1_IDEFD BIT(30) /*!< ID filter data / ID expected high threshold in Pretended Networking mode */ 432 433 /* CAN_PN_DF0EDH0 */ 434 #define CAN_PN_DF0EDH0_DB3FD_EHT BITS(0, 7) /*!< data byte 3 filter data / data byte 3 expected high threshold in Pretended Networking mode */ 435 #define CAN_PN_DF0EDH0_DB2FD_EHT BITS(8, 15) /*!< data byte 2 filter data / data byte 2 expected high threshold in Pretended Networking mode */ 436 #define CAN_PN_DF0EDH0_DB1FD_EHT BITS(16, 23) /*!< data byte 1 filter data / data byte 1 expected high threshold in Pretended Networking mode */ 437 #define CAN_PN_DF0EDH0_DB0FD_EHT BITS(24, 31) /*!< data byte 0 filter data / data byte 0 expected high threshold in Pretended Networking mode */ 438 439 /* CAN_PN_DF1EDH1 */ 440 #define CAN_PN_DF1EDH1_DB7FD_EHT BITS(0, 7) /*!< data byte 7 filter data / data byte 7 expected high threshold in Pretended Networking mode */ 441 #define CAN_PN_DF1EDH1_DB6FD_EHT BITS(8, 15) /*!< data byte 6 filter data / data byte 6 expected high threshold in Pretended Networking mode */ 442 #define CAN_PN_DF1EDH1_DB5FD_EHT BITS(16, 23) /*!< data byte 5 filter data / data byte 5 expected high threshold in Pretended Networking mode */ 443 #define CAN_PN_DF1EDH1_DB4FD_EHT BITS(24, 31) /*!< data byte 4 filter data / data byte 4 expected high threshold in Pretended Networking mode */ 444 445 /* CAN_PN_RWMxCS, x = 0..3 */ 446 #define CAN_PN_RWMXCS_RDLC BITS(16, 19) /*!< received DLC bits */ 447 #define CAN_PN_RWMXCS_RRTR BIT(20) /*!< received RTR bit */ 448 #define CAN_PN_RWMXCS_RIDE BIT(21) /*!< received IDE bit */ 449 #define CAN_PN_RWMXCS_RSRR BIT(22) /*!< received SRR bit */ 450 451 /* CAN_PN_RWMxI, x = 0..3 */ 452 #define CAN_PN_RWMXI_RID BITS(0, 28) /*!< received ID bits */ 453 454 /* CAN_PN_RWMxD0, x = 0..3 */ 455 #define CAN_PN_RWMXD0_RDB3 BITS(0, 7) /*!< received data byte 3 */ 456 #define CAN_PN_RWMXD0_RDB2 BITS(8, 15) /*!< received data byte 2 */ 457 #define CAN_PN_RWMXD0_RDB1 BITS(16, 23) /*!< received data byte 1 */ 458 #define CAN_PN_RWMXD0_RDB0 BITS(24, 31) /*!< received data byte 0 */ 459 460 /* CAN_PN_RWMxD1, x = 0..3 */ 461 #define CAN_PN_RWMXD1_RDB7 BITS(0, 7) /*!< received data byte 7 */ 462 #define CAN_PN_RWMXD1_RDB6 BITS(8, 15) /*!< received data byte 6 */ 463 #define CAN_PN_RWMXD1_RDB5 BITS(16, 23) /*!< received data byte 5 */ 464 #define CAN_PN_RWMXD1_RDB4 BITS(24, 31) /*!< received data byte 4 */ 465 466 /* CAN_FDCTL */ 467 #define CAN_FDCTL_TDCV BITS(0, 5) /*!< transmitter delay compensation value */ 468 #define CAN_FDCTL_TDCO BITS(8, 12) /*!< transmitter delay compensation offset */ 469 #define CAN_FDCTL_TDCS BIT(14) /*!< transmitter delay compensation status */ 470 #define CAN_FDCTL_TDCEN BIT(15) /*!< transmitter delay compensation enable */ 471 #define CAN_FDCTL_MDSZ BITS(16, 17) /*!< mailbox data size */ 472 #define CAN_FDCTL_BRSEN BIT(31) /*!< bit rate of data switch enable */ 473 474 /* CAN_FDBT */ 475 #define CAN_FDBT_DPBS2 BITS(0, 2) /*!< phase buffer segment 2 for data bit time */ 476 #define CAN_FDBT_DPBS1 BITS(5, 7) /*!< phase buffer segment 1 for data bit time */ 477 #define CAN_FDBT_DPTS BITS(10, 14) /*!< propagation time segment for data bit time */ 478 #define CAN_FDBT_DSJW BITS(16, 18) /*!< resynchronization jump width for data bit time */ 479 #define CAN_FDBT_DBAUDPSC BITS(20, 29) /*!< baud rate prescaler for data bit time */ 480 481 /* CAN_CRCCFD */ 482 #define CAN_CRCCFD_CRCTCI BITS(0, 20) /*!< transmitted CRC value for classical and ISO / non-ISO frames */ 483 #define CAN_CRCCFD_ANTM BITS(24, 28) /*!< associated number of mailbox for transmitting the CRCTCI[20:0] value */ 484 485 /* CAN_MDES0 */ 486 #define CAN_MDES0_TIMESTAMP BITS(0, 15) /*!< free-running counter timestamp */ 487 #define CAN_MDES0_DLC BITS(16, 19) /*!< data length code in bytes */ 488 #define CAN_MDES0_RTR BIT(20) /*!< remote transmission request */ 489 #define CAN_MDES0_IDE BIT(21) /*!< ID extended bit */ 490 #define CAN_MDES0_SRR BIT(22) /*!< substitute remote request */ 491 #define CAN_MDES0_CODE BITS(24, 27) /*!< mailbox code */ 492 #define CAN_MDES0_ESI BIT(29) /*!< error state indicator */ 493 #define CAN_MDES0_BRS BIT(30) /*!< bit rate switch */ 494 #define CAN_MDES0_FDF BIT(31) /*!< FD format indicator */ 495 496 /* CAN_MDES1 */ 497 #define CAN_MDES1_ID_EXD BITS(0, 17) /*!< identifier for extended frame */ 498 #define CAN_MDES1_ID_STD BITS(18, 28) /*!< identifier for standard frame */ 499 #define CAN_MDES1_PRIO BITS(29, 31) /*!< local priority */ 500 501 /* CAN_FDES0 */ 502 #define CAN_FDES0_TIMESTAMP BITS(0, 15) /*!< free-running counter timestamp */ 503 #define CAN_FDES0_DLC BITS(16, 19) /*!< data length code in bytes */ 504 #define CAN_FDES0_RTR BIT(20) /*!< remote transmission request */ 505 #define CAN_FDES0_IDE BIT(21) /*!< ID extended bit */ 506 #define CAN_FDES0_SRR BIT(22) /*!< substitute remote request */ 507 #define CAN_FDES0_IDFMN BITS(23, 31) /*!< identifier filter matching number */ 508 509 /* CAN_FDES1 */ 510 #define CAN_FDES1_ID_EXT BITS(0, 17) /*!< identifier for extended frame */ 511 #define CAN_FDES1_ID_STD BITS(18, 28) /*!< identifier for standard frame */ 512 513 /* CAN_FDESX_A */ 514 #define CAN_FDESX_ID_EXD_A BITS(0, 28) /*!< extended ID in format A */ 515 #define CAN_FDESX_ID_STD_A BITS(18, 28) /*!< standard ID in format A */ 516 #define CAN_FDESX_IDE_A BIT(30) /*!< ID extended frame for format A */ 517 #define CAN_FDESX_RTR_A BIT(31) /*!< remote frame for format A */ 518 519 /* CAN_FDESX_B */ 520 #define CAN_FDESX_ID_EXD_B_1 BITS(0, 13) /*!< extended ID 1 in format B */ 521 #define CAN_FDESX_ID_STD_B_1 BITS(3, 13) /*!< standard ID 1 in format B */ 522 #define CAN_FDESX_IDE_B1 BIT(14) /*!< ID extended frame 1 for format B */ 523 #define CAN_FDESX_RTR_B1 BIT(15) /*!< remote frame 1 for format B */ 524 #define CAN_FDESX_ID_EXD_B_0 BITS(16, 29) /*!< extended ID 0 in format B */ 525 #define CAN_FDESX_ID_STD_B_0 BITS(19, 29) /*!< standard ID 0 in format B */ 526 #define CAN_FDESX_IDE_B0 BIT(30) /*!< ID extended frame 0 for format B */ 527 #define CAN_FDESX_RTR_B0 BIT(31) /*!< remote frame 0 for format B */ 528 529 /* CAN_FDESX_C */ 530 #define CAN_FDESX_ID_C_3 BITS(0, 7) /*!< ID for frame 3 for format C */ 531 #define CAN_FDESX_ID_C_2 BITS(8, 15) /*!< ID for frame 2 for format C */ 532 #define CAN_FDESX_ID_C_1 BITS(16, 23) /*!< ID for frame 1 for format C */ 533 #define CAN_FDESX_ID_C_0 BITS(24, 31) /*!< ID for frame 0 for format C */ 534 535 /* consts definitions */ 536 /* define the CAN bit position and its register index offset */ 537 #define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6U) | (uint32_t)(bitpos)) 538 #define CAN_REG_VAL(canx, offset) (REG32((uint32_t)(canx) + ((uint32_t)(offset) >> 6U))) 539 #define CAN_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) 540 #define CAN_RFIFOMPF(canx, num) REG32((canx) + 0x00000880U + (num) * 0x00000004U) /*!< CAN receive fifo / mailbox private filter x register */ 541 542 /* register offset */ 543 #define CTL0_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */ 544 #define CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ 545 #define ERR1_REG_OFFSET ((uint32_t)0x00000020U) /*!< ERR1 register offset */ 546 #define INTEN_REG_OFFSET ((uint32_t)0x00000028U) /*!< INTEN register offset */ 547 #define STAT_REG_OFFSET ((uint32_t)0x00000030U) /*!< STAT register offset */ 548 #define CTL2_REG_OFFSET ((uint32_t)0x00000034U) /*!< CTL2 register offset */ 549 #define PN_CTL0_REG_OFFSET ((uint32_t)0x00000B00U) /*!< PN_CTL0 register offset */ 550 #define PN_STAT_REG_OFFSET ((uint32_t)0x00000B08U) /*!< PN_STAT register offset */ 551 #define FDCTL_REG_OFFSET ((uint32_t)0x00000C00U) /*!< FDCTL register offset */ 552 553 /* CAN interrupt enable or disable */ 554 typedef enum { 555 /* interrupt in CLT1 register */ 556 CAN_INT_RX_WARNING = CAN_REGIDX_BIT(CTL1_REG_OFFSET, 10U), /*!< receive warning interrupt */ 557 CAN_INT_TX_WARNING = CAN_REGIDX_BIT(CTL1_REG_OFFSET, 11U), /*!< transmit warning interrupt */ 558 CAN_INT_ERR_SUMMARY = CAN_REGIDX_BIT(CTL1_REG_OFFSET, 14U), /*!< error interrupt */ 559 CAN_INT_BUSOFF = CAN_REGIDX_BIT(CTL1_REG_OFFSET, 15U), /*!< bus off interrupt */ 560 /* interrupt in CLT2 register */ 561 CAN_INT_BUSOFF_RECOVERY = CAN_REGIDX_BIT(CTL2_REG_OFFSET, 30U), /*!< bus off recovery interrupt */ 562 CAN_INT_ERR_SUMMARY_FD = CAN_REGIDX_BIT(CTL2_REG_OFFSET, 31U), /*!< fd error interrupt */ 563 /* interrupt in INTEN register */ 564 CAN_INT_MB0 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 0U), /*!< mailbox 0 interrupt */ 565 CAN_INT_MB1 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 1U), /*!< mailbox 1 interrupt */ 566 CAN_INT_MB2 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 2U), /*!< mailbox 2 interrupt */ 567 CAN_INT_MB3 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 3U), /*!< mailbox 3 interrupt */ 568 CAN_INT_MB4 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 4U), /*!< mailbox 4 interrupt */ 569 CAN_INT_MB5 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 5U), /*!< mailbox 5 interrupt */ 570 CAN_INT_MB6 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 6U), /*!< mailbox 6 interrupt */ 571 CAN_INT_MB7 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 7U), /*!< mailbox 7 interrupt */ 572 CAN_INT_MB8 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 8U), /*!< mailbox 8 interrupt */ 573 CAN_INT_MB9 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 9U), /*!< mailbox 9 interrupt */ 574 CAN_INT_MB10 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 10U), /*!< mailbox 10 interrupt */ 575 CAN_INT_MB11 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 11U), /*!< mailbox 11 interrupt */ 576 CAN_INT_MB12 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 12U), /*!< mailbox 12 interrupt */ 577 CAN_INT_MB13 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 13U), /*!< mailbox 13 interrupt */ 578 CAN_INT_MB14 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 14U), /*!< mailbox 14 interrupt */ 579 CAN_INT_MB15 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 15U), /*!< mailbox 15 interrupt */ 580 CAN_INT_MB16 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 16U), /*!< mailbox 16 interrupt */ 581 CAN_INT_MB17 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 17U), /*!< mailbox 17 interrupt */ 582 CAN_INT_MB18 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 18U), /*!< mailbox 18 interrupt */ 583 CAN_INT_MB19 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 19U), /*!< mailbox 19 interrupt */ 584 CAN_INT_MB20 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 20U), /*!< mailbox 20 interrupt */ 585 CAN_INT_MB21 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 21U), /*!< mailbox 21 interrupt */ 586 CAN_INT_MB22 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 22U), /*!< mailbox 22 interrupt */ 587 CAN_INT_MB23 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 23U), /*!< mailbox 23 interrupt */ 588 CAN_INT_MB24 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 24U), /*!< mailbox 24 interrupt */ 589 CAN_INT_MB25 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 25U), /*!< mailbox 25 interrupt */ 590 CAN_INT_MB26 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 26U), /*!< mailbox 26 interrupt */ 591 CAN_INT_MB27 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 27U), /*!< mailbox 27 interrupt */ 592 CAN_INT_MB28 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 28U), /*!< mailbox 28 interrupt */ 593 CAN_INT_MB29 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 29U), /*!< mailbox 29 interrupt */ 594 CAN_INT_MB30 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 30U), /*!< mailbox 30 interrupt */ 595 CAN_INT_MB31 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 31U), /*!< mailbox 31 interrupt */ 596 CAN_INT_FIFO_AVAILABLE = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 5U), /*!< fifo availabe interrupt */ 597 CAN_INT_FIFO_WARNING = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 6U), /*!< fifo warning interrupt */ 598 CAN_INT_FIFO_OVERFLOW = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 7U), /*!< fifo overflow interrupt */ 599 /* interrupt in PN_CTL0 registeister */ 600 CAN_INT_WAKEUP_MATCH = CAN_REGIDX_BIT(PN_CTL0_REG_OFFSET, 16U), /*!< Pretended Networking match interrupt */ 601 CAN_INT_WAKEUP_TIMEOUT = CAN_REGIDX_BIT(PN_CTL0_REG_OFFSET, 17U) /*!< Pretended Networking timeout wakeup interrupt */ 602 } can_interrupt_enum; 603 604 /* CAN flags */ 605 typedef enum { 606 /* flags in CTL0 register */ 607 CAN_FLAG_CAN_PN = CAN_REGIDX_BIT(CTL0_REG_OFFSET, 18U), /*!< Pretended Networking state flag */ 608 CAN_FLAG_SOFT_RST = CAN_REGIDX_BIT(CTL0_REG_OFFSET, 25U), /*!< software reset flag */ 609 /* flags in ERR1 register */ 610 CAN_FLAG_ERR_SUMMARY = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 1U), /*!< error summary flag */ 611 CAN_FLAG_BUSOFF = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 2U), /*!< bus off flag */ 612 CAN_FLAG_RECEIVING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 3U), /*!< receiving state flag */ 613 CAN_FLAG_TRANSMITTING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 6U), /*!< transmitting state flag */ 614 CAN_FLAG_IDLE = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 7U), /*!< IDLE state flag */ 615 CAN_FLAG_RX_WARNING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 8U), /*!< receive warning flag */ 616 CAN_FLAG_TX_WARNING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 9U), /*!< transmit warning flag */ 617 CAN_FLAG_STUFF_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 10U), /*!< stuff error flag */ 618 CAN_FLAG_FORM_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 11U), /*!< form error flag */ 619 CAN_FLAG_CRC_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 12U), /*!< CRC error flag */ 620 CAN_FLAG_ACK_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 13U), /*!< ACK error flag */ 621 CAN_FLAG_BIT_DOMINANT_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 14U), /*!< bit dominant error flag */ 622 CAN_FLAG_BIT_RECESSIVE_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 15U), /*!< bit recessive error flag */ 623 CAN_FLAG_SYNC_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 18U), /*!< synchronization flag */ 624 CAN_FLAG_BUSOFF_RECOVERY = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 19U), /*!< bus off recovery flag */ 625 CAN_FLAG_ERR_SUMMARY_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 20U), /*!< FD error summary flag */ 626 CAN_FLAG_ERR_OVERRUN = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 21U), /*!< error overrun flag */ 627 CAN_FLAG_STUFF_ERR_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 26U), /*!< stuff error in FD data phase flag */ 628 CAN_FLAG_FORM_ERR_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 27U), /*!< form error in FD data phase flag */ 629 CAN_FLAG_CRC_ERR_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 28U), /*!< CRC error in FD data phase flag */ 630 CAN_FLAG_BIT_DOMINANT_ERR_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 30U), /*!< bit dominant error in FD data phase flag */ 631 CAN_FLAG_BIT_RECESSIVE_ERR_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 31U), /*!< bit recessive error in FD data phase flag */ 632 /* flags in STAT register */ 633 CAN_FLAG_MB0 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< mailbox 0 flag */ 634 CAN_FLAG_MB1 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< mailbox 1 flag */ 635 CAN_FLAG_MB2 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< mailbox 2 flag */ 636 CAN_FLAG_MB3 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< mailbox 3 flag */ 637 CAN_FLAG_MB4 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< mailbox 4 flag */ 638 CAN_FLAG_MB5 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 5U), /*!< mailbox 5 flag */ 639 CAN_FLAG_MB6 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 6U), /*!< mailbox 6 flag */ 640 CAN_FLAG_MB7 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 7U), /*!< mailbox 7 flag */ 641 CAN_FLAG_MB8 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< mailbox 8 flag */ 642 CAN_FLAG_MB9 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< mailbox 9 flag */ 643 CAN_FLAG_MB10 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< mailbox 10 flag */ 644 CAN_FLAG_MB11 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< mailbox 11 flag */ 645 CAN_FLAG_MB12 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 12U), /*!< mailbox 12 flag */ 646 CAN_FLAG_MB13 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 13U), /*!< mailbox 13 flag */ 647 CAN_FLAG_MB14 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 14U), /*!< mailbox 14 flag */ 648 CAN_FLAG_MB15 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 15U), /*!< mailbox 15 flag */ 649 CAN_FLAG_MB16 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 16U), /*!< mailbox 16 flag */ 650 CAN_FLAG_MB17 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 17U), /*!< mailbox 17 flag */ 651 CAN_FLAG_MB18 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 18U), /*!< mailbox 18 flag */ 652 CAN_FLAG_MB19 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 19U), /*!< mailbox 19 flag */ 653 CAN_FLAG_MB20 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 20U), /*!< mailbox 20 flag */ 654 CAN_FLAG_MB21 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 21U), /*!< mailbox 21 flag */ 655 CAN_FLAG_MB22 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 22U), /*!< mailbox 22 flag */ 656 CAN_FLAG_MB23 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 23U), /*!< mailbox 23 flag */ 657 CAN_FLAG_MB24 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 24U), /*!< mailbox 24 flag */ 658 CAN_FLAG_MB25 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 25U), /*!< mailbox 25 flag */ 659 CAN_FLAG_MB26 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 26U), /*!< mailbox 26 flag */ 660 CAN_FLAG_MB27 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 27U), /*!< mailbox 27 flag */ 661 CAN_FLAG_MB28 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 28U), /*!< mailbox 28 flag */ 662 CAN_FLAG_MB29 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 29U), /*!< mailbox 29 flag */ 663 CAN_FLAG_MB30 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 30U), /*!< mailbox 30 flag */ 664 CAN_FLAG_MB31 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 31U), /*!< mailbox 31 flag */ 665 CAN_FLAG_FIFO_AVAILABLE = CAN_REGIDX_BIT(STAT_REG_OFFSET, 5U), /*!< fifo availabe flag */ 666 CAN_FLAG_FIFO_WARNING = CAN_REGIDX_BIT(STAT_REG_OFFSET, 6U), /*!< fifo warning flag */ 667 CAN_FLAG_FIFO_OVERFLOW = CAN_REGIDX_BIT(STAT_REG_OFFSET, 7U), /*!< fifo overflow flag */ 668 /* flags in PN_STAT register */ 669 CAN_FLAG_WAKEUP_MATCH = CAN_REGIDX_BIT(PN_STAT_REG_OFFSET, 16U), /*!< Pretended Networking match flag */ 670 CAN_FLAG_WAKEUP_TIMEOUT = CAN_REGIDX_BIT(PN_STAT_REG_OFFSET, 17U), /*!< Pretended Networking timeout wakeup flag */ 671 /* flags in FDCTL register */ 672 CAN_FLAG_TDC_OUT_OF_RANGE = CAN_REGIDX_BIT(FDCTL_REG_OFFSET, 14U), /*!< transmitter delay is out of compensation range flag */ 673 } can_flag_enum; 674 675 /* CAN interrupt flags */ 676 typedef enum { 677 /* interrupt flags in ERR1 register */ 678 CAN_INT_FLAG_ERR_SUMMARY = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 1U), /*!< error summary interrupt flag */ 679 CAN_INT_FLAG_BUSOFF = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 2U), /*!< bus off interrupt flag */ 680 CAN_INT_FLAG_RX_WARNING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 16U), /*!< receive warning interrupt flag */ 681 CAN_INT_FLAG_TX_WARNING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 17U), /*!< transmit warning interrupt flag */ 682 CAN_INT_FLAG_BUSOFF_RECOVERY = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 19U), /*!< bus off recovery interrupt flag */ 683 CAN_INT_FLAG_ERR_SUMMARY_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 20U), /*!< fd error summary interrupt flag */ 684 /* interrupt flags in STAT register */ 685 CAN_INT_FLAG_MB0 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< mailbox 0 interrupt flag */ 686 CAN_INT_FLAG_MB1 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< mailbox 1 interrupt flag */ 687 CAN_INT_FLAG_MB2 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< mailbox 2 interrupt flag */ 688 CAN_INT_FLAG_MB3 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< mailbox 3 interrupt flag */ 689 CAN_INT_FLAG_MB4 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< mailbox 4 interrupt flag */ 690 CAN_INT_FLAG_MB5 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 5U), /*!< mailbox 5 interrupt flag */ 691 CAN_INT_FLAG_MB6 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 6U), /*!< mailbox 6 interrupt flag */ 692 CAN_INT_FLAG_MB7 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 7U), /*!< mailbox 7 interrupt flag */ 693 CAN_INT_FLAG_MB8 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< mailbox 8 interrupt flag */ 694 CAN_INT_FLAG_MB9 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< mailbox 9 interrupt flag */ 695 CAN_INT_FLAG_MB10 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< mailbox 10 interrupt flag */ 696 CAN_INT_FLAG_MB11 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< mailbox 11 interrupt flag */ 697 CAN_INT_FLAG_MB12 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 12U), /*!< mailbox 12 interrupt flag */ 698 CAN_INT_FLAG_MB13 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 13U), /*!< mailbox 13 interrupt flag */ 699 CAN_INT_FLAG_MB14 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 14U), /*!< mailbox 14 interrupt flag */ 700 CAN_INT_FLAG_MB15 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 15U), /*!< mailbox 15 interrupt flag */ 701 CAN_INT_FLAG_MB16 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 16U), /*!< mailbox 16 interrupt flag */ 702 CAN_INT_FLAG_MB17 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 17U), /*!< mailbox 17 interrupt flag */ 703 CAN_INT_FLAG_MB18 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 18U), /*!< mailbox 18 interrupt flag */ 704 CAN_INT_FLAG_MB19 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 19U), /*!< mailbox 19 interrupt flag */ 705 CAN_INT_FLAG_MB20 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 20U), /*!< mailbox 20 interrupt flag */ 706 CAN_INT_FLAG_MB21 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 21U), /*!< mailbox 21 interrupt flag */ 707 CAN_INT_FLAG_MB22 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 22U), /*!< mailbox 22 interrupt flag */ 708 CAN_INT_FLAG_MB23 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 23U), /*!< mailbox 23 interrupt flag */ 709 CAN_INT_FLAG_MB24 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 24U), /*!< mailbox 24 interrupt flag */ 710 CAN_INT_FLAG_MB25 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 25U), /*!< mailbox 25 interrupt flag */ 711 CAN_INT_FLAG_MB26 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 26U), /*!< mailbox 26 interrupt flag */ 712 CAN_INT_FLAG_MB27 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 27U), /*!< mailbox 27 interrupt flag */ 713 CAN_INT_FLAG_MB28 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 28U), /*!< mailbox 28 interrupt flag */ 714 CAN_INT_FLAG_MB29 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 29U), /*!< mailbox 29 interrupt flag */ 715 CAN_INT_FLAG_MB30 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 30U), /*!< mailbox 30 interrupt flag */ 716 CAN_INT_FLAG_MB31 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 31U), /*!< mailbox 31 interrupt flag */ 717 CAN_INT_FLAG_FIFO_AVAILABLE = CAN_REGIDX_BIT(STAT_REG_OFFSET, 5U), /*!< fifo availabe interrupt flag */ 718 CAN_INT_FLAG_FIFO_WARNING = CAN_REGIDX_BIT(STAT_REG_OFFSET, 6U), /*!< fifo warning interrupt flag */ 719 CAN_INT_FLAG_FIFO_OVERFLOW = CAN_REGIDX_BIT(STAT_REG_OFFSET, 7U), /*!< fifo overflow interrupt flag */ 720 /* interrupt flags in PN_STAT register */ 721 CAN_INT_FLAG_WAKEUP_MATCH = CAN_REGIDX_BIT(PN_STAT_REG_OFFSET, 16U), /*!< Pretended Networking match interrupt flag */ 722 CAN_INT_FLAG_WAKEUP_TIMEOUT = CAN_REGIDX_BIT(PN_STAT_REG_OFFSET, 17U) /*!< Pretended Networking timeout wakeup interrupt flag */ 723 } can_interrupt_flag_enum; 724 725 /* operation modes */ 726 typedef enum { 727 GD32_CAN_NORMAL_MODE = 0U, /*!< normal mode */ 728 GD32_CAN_MONITOR_MODE = 1U, /*!< monitor mode */ 729 GD32_CAN_LOOPBACK_SILENT_MODE = 2U, /*!< loopback mode */ 730 GD32_CAN_INACTIVE_MODE = 3U, /*!< inactive mode */ 731 GD32_CAN_DISABLE_MODE = 4U, /*!< disable mode */ 732 GD32_CAN_PN_MODE = 5U /*!< Pretended Networking mode */ 733 } can_operation_modes_enum; 734 735 /* initiliaze parameter type */ 736 typedef enum { 737 CAN_INIT_STRUCT = 0U, /*!< CAN initiliaze parameters struct */ 738 CAN_FD_INIT_STRUCT = 1U, /*!< CAN FD parameters struct */ 739 CAN_FIFO_INIT_STRUCT = 2U, /*!< CAN fifo parameters struct */ 740 CAN_PN_MODE_INIT_STRUCT = 3U, /*!< Pretended Networking mode parameter strcut */ 741 CAN_PN_MODE_FILTER_STRUCT = 4U, /*!< Pretended Networking mode filter parameter strcut */ 742 CAN_MDSC_STRUCT = 5U, /*!< mailbox descriptor strcut */ 743 CAN_FDES_STRUCT = 6U, /*!< Rx fifo descriptor strcut */ 744 CAN_FIFO_ID_FILTER_STRUCT = 7U, /*!< Rx fifo id filter strcut */ 745 CAN_CRC_STRUCT = 8U, /*!< CRC strcut */ 746 CAN_ERRCNT_STRUCT = 9U, /*!< error counter strcut */ 747 } can_struct_type_enum; 748 749 /* error state indicator */ 750 typedef enum { 751 CAN_ERROR_STATE_ACTIVE = 0U, /*!< CAN in error active */ 752 CAN_ERROR_STATE_PASSIVE = 1U, /*!< CAN in error passive */ 753 CAN_ERROR_STATE_BUS_OFF = 2U /*!< CAN in bus off */ 754 } can_error_state_enum; 755 756 /* error counter structure */ 757 typedef struct { 758 uint8_t fd_data_phase_rx_errcnt; /*!< receive error counter for data phase of FD frames with BRS bit set */ 759 uint8_t fd_data_phase_tx_errcnt; /*!< transmit error count for the data phase of FD frames with BRS bit set */ 760 uint8_t rx_errcnt; /*!< receive error count defined by the CAN standard */ 761 uint8_t tx_errcnt; /*!< transmit error count defined by the CAN standard */ 762 } can_error_counter_struct; 763 764 /* CAN initiliaze parameters structure */ 765 typedef struct { 766 uint32_t internal_counter_source; /*!< internal counter source */ 767 uint32_t mb_tx_order; /*!< mailbox transmit order */ 768 uint32_t mb_rx_ide_rtr_type; /*!< IDE and RTR field fitler type */ 769 uint32_t mb_remote_frame; /*!< remote request frame is stored */ 770 uint8_t self_reception; /*!< enable or disable self reception */ 771 uint8_t mb_tx_abort_enable; /*!< enable or disable transmit abort */ 772 uint8_t local_priority_enable; /*!< enable or disable local priority */ 773 uint8_t rx_private_filter_queue_enable; /*!< private filter and queue enable */ 774 uint32_t edge_filter_enable; /*!< edge filter enable*/ 775 uint32_t protocol_exception_enable; /*!< protocol exception enable */ 776 uint32_t rx_filter_order; /*!< receive filter order */ 777 uint32_t memory_size; /*!< memory size */ 778 uint32_t mb_public_filter; /*!< mailbox public filter */ 779 uint32_t prescaler; /*!< baudrate prescaler */ 780 uint8_t resync_jump_width; /*!< resynchronization jump width */ 781 uint8_t prop_time_segment; /*!< propagation time segment */ 782 uint8_t time_segment_1; /*!< time segment 1 */ 783 uint8_t time_segment_2; /*!< time segment 2 */ 784 } can_parameter_struct; 785 786 /* mailbox descriptor struct */ 787 typedef struct { 788 uint32_t timestamp : 16; /*!< free-running counter timestamp */ 789 uint32_t dlc : 4; /*!< data length code in bytes */ 790 uint32_t rtr : 1; /*!< remote transmission request */ 791 uint32_t ide : 1; /*!< ID extended bit */ 792 uint32_t srr : 1; /*!< substitute remote request */ 793 uint32_t reserve1 : 1; /*!< reserve bit 1 */ 794 uint32_t code : 4; /*!< mailbox code */ 795 uint32_t reserve2 : 1; /*!< reserve bit 2 */ 796 uint32_t esi : 1; /*!< error state indicator */ 797 uint32_t brs : 1; /*!< bit rate switch */ 798 uint32_t fdf : 1; /*!< FD format indicator */ 799 uint32_t id : 29; /*!< identifier for frame */ 800 uint32_t prio : 3; /*!< local priority */ 801 uint32_t *data; /*!< data */ 802 uint32_t data_bytes; /*!< data bytes */ 803 uint8_t padding; /*!< FD mode padding data */ 804 } can_mailbox_descriptor_struct; 805 806 /* fifo descriptor struct */ 807 typedef struct { 808 uint32_t timestamp : 16; /*!< free-running counter timestamp */ 809 uint32_t dlc : 4; /*!< data length code in bytes */ 810 uint32_t rtr : 1; /*!< remote transmission request */ 811 uint32_t ide : 1; /*!< ID extended bit */ 812 uint32_t srr : 1; /*!< substitute remote request */ 813 uint32_t idhit : 9; /*!< identifier filter matching number */ 814 uint32_t id; /*!< identifier for frame */ 815 uint32_t data[2]; /*!< fifo data */ 816 } can_rx_fifo_struct; 817 818 /* FD initiliaze parameter struct */ 819 typedef struct { 820 uint32_t iso_can_fd_enable; /*!< ISO CAN FD protocol enable */ 821 uint32_t bitrate_switch_enable; /*!< data bit rate switch */ 822 uint32_t mailbox_data_size; /*!< mailbox data size */ 823 uint32_t tdc_enable; /*!< trnasmitter delay compensation enable */ 824 uint32_t tdc_offset; /*!< trnasmitter delay compensation offset */ 825 uint32_t prescaler; /*!< baudrate prescaler */ 826 uint8_t resync_jump_width; /*!< resynchronization jump width */ 827 uint8_t prop_time_segment; /*!< propagation time segment */ 828 uint8_t time_segment_1; /*!< time segment 1 */ 829 uint8_t time_segment_2; /*!< time segment 2 */ 830 } can_fd_parameter_struct; 831 832 /* FIFO ID filter table struct */ 833 typedef struct { 834 uint32_t remote_frame; /*!< expected remote frame*/ 835 uint32_t extended_frame; /*!< expected extended frame */ 836 uint32_t id; /*!< expected id */ 837 } can_rx_fifo_id_filter_struct; 838 839 /* FIFO initiliaze parameter struct */ 840 typedef struct { 841 uint8_t dma_enable; /*!< DMA enable */ 842 uint32_t filter_format_and_number; /*!< FIFO ID filter format and number */ 843 uint32_t fifo_public_filter; /*!< FIFO ID public filter */ 844 } can_fifo_parameter_struct; 845 846 /* Pretended Networking mode filter parameter struct */ 847 typedef struct { 848 uint32_t remote_frame; /*!< remote frame */ 849 uint32_t extended_frame; /*!< extended frame */ 850 uint32_t id; /*!< id */ 851 uint32_t dlc_high_threshold; /*!< DLC expected high threshold */ 852 uint32_t dlc_low_threshold; /*!< DLC expected low threshold */ 853 uint32_t payload[2]; /*!< data */ 854 } can_pn_mode_filter_struct; 855 856 /* Pretended Networking mode initiliaze parameter struct */ 857 typedef struct { 858 uint32_t timeout_int; /*!< enable or disable timeout interrupt */ 859 uint32_t match_int; /*!< enable or disable match interrupt */ 860 uint32_t num_matches; /*!< set number of message matching times */ 861 uint32_t match_timeout; /*!< set wakeup timeout value */ 862 uint32_t frame_filter; /*!< set frame filtering type */ 863 uint32_t id_filter; /*!< set id filtering type */ 864 uint32_t data_filter; /*!< set data filtering type */ 865 } can_pn_mode_config_struct; 866 867 /* CRC parameter struct */ 868 typedef struct { 869 uint32_t classical_frm_mb_number; /*!< associated number of mailbox for transmitting the CRCTC[14:0] value */ 870 uint32_t classical_frm_transmitted_crc; /*!< transmitted CRC value for classical frames */ 871 uint32_t classical_fd_frm_mb_number; /*!< associated number of mailbox for transmitting the CRCTCI[20:0] value */ 872 uint32_t classical_fd_frm_transmitted_crc; /*!< transmitted CRC value for classical and ISO / non-ISO FD frames */ 873 } can_crc_struct; 874 875 /* CAN_CTL0 register */ 876 #define CTL0_MSZ(regval) (CAN_CTL0_MSZ & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_CTL0_MSZ bit field */ 877 #define CAN_MEMSIZE_1_UNIT CTL0_MSZ(0U) /*!< 1 unit for message transmission and reception */ 878 #define CAN_MEMSIZE_2_UNIT CTL0_MSZ(1U) /*!< 2 units for message transmission and reception */ 879 #define CAN_MEMSIZE_3_UNIT CTL0_MSZ(2U) /*!< 3 units for message transmission and reception */ 880 #define CAN_MEMSIZE_4_UNIT CTL0_MSZ(3U) /*!< 4 units for message transmission and reception */ 881 #define CAN_MEMSIZE_5_UNIT CTL0_MSZ(4U) /*!< 5 units for message transmission and reception */ 882 #define CAN_MEMSIZE_6_UNIT CTL0_MSZ(5U) /*!< 6 units for message transmission and reception */ 883 #define CAN_MEMSIZE_7_UNIT CTL0_MSZ(6U) /*!< 7 units for message transmission and reception */ 884 #define CAN_MEMSIZE_8_UNIT CTL0_MSZ(7U) /*!< 8 units for message transmission and reception */ 885 #define CAN_MEMSIZE_9_UNIT CTL0_MSZ(8U) /*!< 9 units for message transmission and reception */ 886 #define CAN_MEMSIZE_10_UNIT CTL0_MSZ(9U) /*!< 10 units for message transmission and reception */ 887 #define CAN_MEMSIZE_11_UNIT CTL0_MSZ(10U) /*!< 11 units for message transmission and reception */ 888 #define CAN_MEMSIZE_12_UNIT CTL0_MSZ(11U) /*!< 12 units for message transmission and reception */ 889 #define CAN_MEMSIZE_13_UNIT CTL0_MSZ(12U) /*!< 13 units for message transmission and reception */ 890 #define CAN_MEMSIZE_14_UNIT CTL0_MSZ(13U) /*!< 14 units for message transmission and reception */ 891 #define CAN_MEMSIZE_15_UNIT CTL0_MSZ(14U) /*!< 15 units for message transmission and reception */ 892 #define CAN_MEMSIZE_16_UNIT CTL0_MSZ(15U) /*!< 16 units for message transmission and reception */ 893 #define CAN_MEMSIZE_17_UNIT CTL0_MSZ(16U) /*!< 17 units for message transmission and reception */ 894 #define CAN_MEMSIZE_18_UNIT CTL0_MSZ(17U) /*!< 18 units for message transmission and reception */ 895 #define CAN_MEMSIZE_19_UNIT CTL0_MSZ(18U) /*!< 19 units for message transmission and reception */ 896 #define CAN_MEMSIZE_20_UNIT CTL0_MSZ(19U) /*!< 20 units for message transmission and reception */ 897 #define CAN_MEMSIZE_21_UNIT CTL0_MSZ(20U) /*!< 21 units for message transmission and reception */ 898 #define CAN_MEMSIZE_22_UNIT CTL0_MSZ(21U) /*!< 22 units for message transmission and reception */ 899 #define CAN_MEMSIZE_23_UNIT CTL0_MSZ(22U) /*!< 23 units for message transmission and reception */ 900 #define CAN_MEMSIZE_24_UNIT CTL0_MSZ(23U) /*!< 24 units for message transmission and reception */ 901 #define CAN_MEMSIZE_25_UNIT CTL0_MSZ(24U) /*!< 25 units for message transmission and reception */ 902 #define CAN_MEMSIZE_26_UNIT CTL0_MSZ(25U) /*!< 26 units for message transmission and reception */ 903 #define CAN_MEMSIZE_27_UNIT CTL0_MSZ(26U) /*!< 27 units for message transmission and reception */ 904 #define CAN_MEMSIZE_28_UNIT CTL0_MSZ(27U) /*!< 28 units for message transmission and reception */ 905 #define CAN_MEMSIZE_29_UNIT CTL0_MSZ(28U) /*!< 29 units for message transmission and reception */ 906 #define CAN_MEMSIZE_30_UNIT CTL0_MSZ(29U) /*!< 30 units for message transmission and reception */ 907 #define CAN_MEMSIZE_31_UNIT CTL0_MSZ(30U) /*!< 31 units for message transmission and reception */ 908 #define CAN_MEMSIZE_32_UNIT CTL0_MSZ(31U) /*!< 32 units for message transmission and reception */ 909 910 #define CTL0_FS(regval) (CAN_CTL0_FS & ((uint32_t)(regval) << 8U)) /*!< write value to CAN_CTL0_FS bit field */ 911 #define CAN_FIFO_FILTER_FORMAT_A CTL0_FS(0U) /*!< FIFO filter format A */ 912 #define CAN_FIFO_FILTER_FORMAT_B CTL0_FS(1U) /*!< FIFO filter format B */ 913 #define CAN_FIFO_FILTER_FORMAT_C CTL0_FS(2U) /*!< FIFO filter format C */ 914 #define CAN_FIFO_FILTER_FORMAT_D CTL0_FS(3U) /*!< FIFO filter format D */ 915 916 #define GET_CTL0_FS(regval) GET_BITS((regval),8,9) /*!< get CAN_CTL0_FS bit field */ 917 918 /* CAN_CTL1 register */ 919 #define CAN_TX_HIGH_PRIORITY_MB_FIRST ((uint32_t)0x00000000U) /*!< highest priority mailbox first */ 920 #define CAN_TX_LOW_NUM_MB_FIRST CAN_CTL1_MTO /*!< low number mailbox first */ 921 922 #define CAN_BSP_MODE_ONE_SAMPLE ((uint32_t)0x00000000U) /*!< one sample for the received bit */ 923 #define CAN_BSP_MODE_THREE_SAMPLES CAN_CTL1_BSPMOD /*!< three sample for received bit */ 924 925 /* CAN_ERR0 register */ 926 #define GET_ERR0_REFCNT(regval) GET_BITS((regval),24,31) /*!< get receive error counter for data phase of FD frames with BRS bit set */ 927 #define GET_ERR0_TEFCNT(regval) GET_BITS((regval),16,23) /*!< get transmit error counter for data phase of FD frames with BRS bit set */ 928 #define GET_ERR0_RECNT(regval) GET_BITS((regval),8,15) /*!< get receive error counter defined by the CAN standard */ 929 #define GET_ERR0_TECNT(regval) GET_BITS((regval),0,7) /*!< get transmit error counter defined by the CAN standard */ 930 #define ERR0_REFCNT(regval) (BITS(24,31) & ((uint32_t)(regval) << 24U)) /*!< set receive error counter for data phase of FD frames with BRS bit set */ 931 #define ERR0_TEFCNT(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U)) /*!< set transmit error counter for data phase of FD frames with BRS bit set */ 932 #define ERR0_RECNT(regval) (BITS(8,15) & ((uint32_t)(regval) << 8U)) /*!< set receive error counter defined by the CAN standard */ 933 #define ERR0_TECNT(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< set transmit error counter defined by the CAN standard */ 934 935 /* CAN_ERR1 register */ 936 #define GET_ERR1_ERRSI(regval) GET_BITS((regval),4,5) /*!< read CAN_ERR1_ERRSI bit field */ 937 938 /* CAN_STAT register */ 939 #define STAT_MS(regval) BIT(regval) /*!< write value to CAN_STAT_MS bit field */ 940 941 /* CAN_CTL2 register */ 942 #define CAN_TIMER_SOURCE_BIT_CLOCK ((uint32_t)0x00000000U) /*!< internal counter source is CAN bit clock */ 943 #define CAN_TIMER_SOURCE_EXTERNAL_TIME_TICK CAN_CTL2_ITSRC /*!< internal counter source is external time tick */ 944 945 #define CAN_IDE_RTR_COMPARED ((uint32_t)0x00000000U) /*!< always compare IDE bit, never compare RTR bit */ 946 #define CAN_IDE_RTR_FILTERED CAN_CTL2_IDERTR_RMF /*!< filtering IDE and RTR fields */ 947 948 #define CAN_GEN_REMOTE_RESPONSE_FRAME ((uint32_t)0x00000000U) /* remote response frame is generated when a mailbox with CODE RANSWER is found with the same ID */ 949 #define CAN_STORE_REMOTE_REQUEST_FRAME CAN_CTL2_RRFRMS /* remote request frame is stored as a data frame without automatic remote response frame transmitted */ 950 951 #define CAN_RX_FILTER_ORDER_FIFO_FIRST ((uint32_t)0x00000000U) /*!< receive search FIFO first */ 952 #define CAN_RX_FILTER_ORDER_MAILBOX_FIRST CAN_CTL2_RFO /*!< receive search mailbox first */ 953 954 #define CTL2_ASD(regval) (BITS(19,23) & ((uint32_t)(regval) << 19U)) /*!< write value to CAN_CTL2_ASD bit field */ 955 956 #define CTL2_RFFN(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) /*!< write value to CAN_CTL2_RFFN bit field */ 957 #define GET_CTL2_RFFN(regval) GET_BITS((regval),24,27) /*!< get CAN_CTL2_RFFN bit field */ 958 #define CAN_RXFIFO_FILTER_A_NUM_8 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(0U)) /*!< FIFO ID filter format A and 8 filters */ 959 #define CAN_RXFIFO_FILTER_A_NUM_16 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(1U)) /*!< FIFO ID filter format A and 16 filters */ 960 #define CAN_RXFIFO_FILTER_A_NUM_24 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(2U)) /*!< FIFO ID filter format A and 24 filters */ 961 #define CAN_RXFIFO_FILTER_A_NUM_32 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(3U)) /*!< FIFO ID filter format A and 32 filters */ 962 #define CAN_RXFIFO_FILTER_A_NUM_40 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(4U)) /*!< FIFO ID filter format A and 40 filters */ 963 #define CAN_RXFIFO_FILTER_A_NUM_48 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(5U)) /*!< FIFO ID filter format A and 48 filters */ 964 #define CAN_RXFIFO_FILTER_A_NUM_56 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(6U)) /*!< FIFO ID filter format A and 56 filters */ 965 #define CAN_RXFIFO_FILTER_A_NUM_64 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(7U)) /*!< FIFO ID filter format A and 64 filters */ 966 #define CAN_RXFIFO_FILTER_A_NUM_72 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(8U)) /*!< FIFO ID filter format A and 72 filters */ 967 #define CAN_RXFIFO_FILTER_A_NUM_80 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(9U)) /*!< FIFO ID filter format A and 80 filters */ 968 #define CAN_RXFIFO_FILTER_A_NUM_88 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(10U)) /*!< FIFO ID filter format A and 88 filters */ 969 #define CAN_RXFIFO_FILTER_A_NUM_96 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(11U)) /*!< FIFO ID filter format A and 96 filters */ 970 #define CAN_RXFIFO_FILTER_A_NUM_104 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(12U)) /*!< FIFO ID filter format A and 104 filters */ 971 #define CAN_RXFIFO_FILTER_B_NUM_16 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(0U)) /*!< FIFO ID filter format B and 16 filters */ 972 #define CAN_RXFIFO_FILTER_B_NUM_32 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(1U)) /*!< FIFO ID filter format B and 32 filters */ 973 #define CAN_RXFIFO_FILTER_B_NUM_48 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(2U)) /*!< FIFO ID filter format B and 48 filters */ 974 #define CAN_RXFIFO_FILTER_B_NUM_64 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(3U)) /*!< FIFO ID filter format B and 64 filters */ 975 #define CAN_RXFIFO_FILTER_B_NUM_80 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(4U)) /*!< FIFO ID filter format B and 80 filters */ 976 #define CAN_RXFIFO_FILTER_B_NUM_96 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(5U)) /*!< FIFO ID filter format B and 96 filters */ 977 #define CAN_RXFIFO_FILTER_B_NUM_112 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(6U)) /*!< FIFO ID filter format B and 112 filters */ 978 #define CAN_RXFIFO_FILTER_B_NUM_128 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(7U)) /*!< FIFO ID filter format B and 128 filters */ 979 #define CAN_RXFIFO_FILTER_B_NUM_144 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(8U)) /*!< FIFO ID filter format B and 144 filters */ 980 #define CAN_RXFIFO_FILTER_B_NUM_160 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(9U)) /*!< FIFO ID filter format B and 160 filters */ 981 #define CAN_RXFIFO_FILTER_B_NUM_176 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(10U)) /*!< FIFO ID filter format B and 176 filters */ 982 #define CAN_RXFIFO_FILTER_B_NUM_192 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(11U)) /*!< FIFO ID filter format B and 192 filters */ 983 #define CAN_RXFIFO_FILTER_B_NUM_208 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(12U)) /*!< FIFO ID filter format B and 208 filters */ 984 #define CAN_RXFIFO_FILTER_C_NUM_32 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(0U)) /*!< FIFO ID filter format C and 32 filters */ 985 #define CAN_RXFIFO_FILTER_C_NUM_64 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(1U)) /*!< FIFO ID filter format C and 64 filters */ 986 #define CAN_RXFIFO_FILTER_C_NUM_96 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(2U)) /*!< FIFO ID filter format C and 96 filters */ 987 #define CAN_RXFIFO_FILTER_C_NUM_128 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(3U)) /*!< FIFO ID filter format C and 128 filters */ 988 #define CAN_RXFIFO_FILTER_C_NUM_160 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(4U)) /*!< FIFO ID filter format C and 160 filters */ 989 #define CAN_RXFIFO_FILTER_C_NUM_192 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(5U)) /*!< FIFO ID filter format C and 192 filters */ 990 #define CAN_RXFIFO_FILTER_C_NUM_224 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(6U)) /*!< FIFO ID filter format C and 224 filters */ 991 #define CAN_RXFIFO_FILTER_C_NUM_256 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(7U)) /*!< FIFO ID filter format C and 256 filters */ 992 #define CAN_RXFIFO_FILTER_C_NUM_288 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(8U)) /*!< FIFO ID filter format C and 288 filters */ 993 #define CAN_RXFIFO_FILTER_C_NUM_320 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(9U)) /*!< FIFO ID filter format C and 320 filters */ 994 #define CAN_RXFIFO_FILTER_C_NUM_352 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(10U)) /*!< FIFO ID filter format C and 352 filters */ 995 #define CAN_RXFIFO_FILTER_C_NUM_384 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(11U)) /*!< FIFO ID filter format C and 384 filters */ 996 #define CAN_RXFIFO_FILTER_C_NUM_416 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(12U)) /*!< FIFO ID filter format C and 416 filters */ 997 #define CAN_RXFIFO_FILTER_D CAN_FIFO_FILTER_FORMAT_D /*!< FIFO ID filter format D */ 998 999 /* CAN_CRCC register */ 1000 #define GET_CRCC_ANTM(regval) GET_BITS((regval),16,20) /*!< get associated number of mailbox for transmitting the CRCTC[14:0] value */ 1001 #define GET_CRCC_CRCTC(regval) GET_BITS((regval),0,14) /*!< get transmitted CRC value for classical frames */ 1002 1003 /* CAN_RFIFOIFMN register */ 1004 #define GET_RFIFOIFMN_IDFMN(regval) GET_BITS((regval),0,8) /*!< get identifier filter matching number */ 1005 1006 /* CAN_BT register */ 1007 #define BT_PBS2(regval) (BITS(0,4) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_BT_PBS2 bit field */ 1008 #define BT_PBS1(regval) (BITS(5,9) & ((uint32_t)(regval) << 5U)) /*!< write value to CAN_BT_PBS1 bit field */ 1009 #define BT_PTS(regval) (BITS(10,15) & ((uint32_t)(regval) << 10U)) /*!< write value to CAN_BT_PTS bit field */ 1010 #define BT_SJW(regval) (BITS(16,20) & ((uint32_t)(regval) << 16U)) /*!< write value to CAN_BT_SJW bit field */ 1011 #define BT_BAUDPSC(regval) (BITS(21,30) & ((uint32_t)(regval) << 21U)) /*!< write value to CAN_BT_BAUDPSC bit field */ 1012 1013 /* CAN_FDCTL register */ 1014 #define GET_FDCTL_MDSZ(regval) GET_BITS((regval),16,17) /*!< get mailbox data size */ 1015 1016 /* CAN_PN_CTL0 register */ 1017 #define PN_CTL0_FFT(regval) (BITS(0,1) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_PN_CTL0_FFT bit field */ 1018 #define CAN_PN_FRAME_FILTERING_ID PN_CTL0_FFT(0U) /*!< all fields except DATA field, DLC field are filtered */ 1019 #define CAN_PN_FRAME_FILTERING_ID_DATA PN_CTL0_FFT(1U) /*!< all fields are filtered */ 1020 #define CAN_PN_FRAME_FILTERING_ID_NMM PN_CTL0_FFT(2U) /*!< all fields except DATA field, DLC field are filtered with NMM[7:0] matching times */ 1021 #define CAN_PN_FRAME_FILTERING_ID_DATA_NMM PN_CTL0_FFT(3U) /*!< all fields are filtered with NMM[7:0] matching times */ 1022 1023 #define PN_CTL0_IDFT(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U)) /*!< write value to CAN_PN_CTL0_IDFT bit field */ 1024 #define CAN_PN_ID_FILTERING_EXACT PN_CTL0_IDFT(0U) /*!< DATA field equal to the expected data field */ 1025 #define CAN_PN_ID_FILTERING_GREATER PN_CTL0_IDFT(1U) /*!< DATA field greater than or equal to the expected data */ 1026 #define CAN_PN_ID_FILTERING_SMALLER PN_CTL0_IDFT(2U) /*!< DATA field greater than or equal to the expected data */ 1027 #define CAN_PN_ID_FILTERING_RANGE PN_CTL0_IDFT(3U) /*!< DATA field is between expected data high threshold and low threshold */ 1028 1029 #define PN_CTL0_DATAFT(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U)) /*!< write value to CAN_PN_CTL0_DATAFT bit field */ 1030 #define CAN_PN_DATA_FILTERING_EXACT PN_CTL0_DATAFT(0U) /*!< ID field equal to the expected identifie */ 1031 #define CAN_PN_DATA_FILTERING_GREATER PN_CTL0_DATAFT(1U) /*!< ID field greater than or equal to the expected identifier */ 1032 #define CAN_PN_DATA_FILTERING_SMALLER PN_CTL0_DATAFT(2U) /*!< ID field smaller than or equal to the expected identifier */ 1033 #define CAN_PN_DATA_FILTERING_RANGE PN_CTL0_DATAFT(3U) /*!< ID field is between expected idetifier high threshold and low threshold */ 1034 1035 #define PN_CTL0_NMM(regval) (BITS(8,15) & ((uint32_t)(regval) << 8U)) /*!< write value to CAN_PN_CTL0_NMM bit field */ 1036 1037 #define PN_CTL0_WMIE(regval) (BIT(16) & ((uint32_t)(regval) << 16U)) /*!< write value to CAN_PN_CTL0_WMIE bit */ 1038 1039 #define PN_CTL0_WTOIE(regval) (BIT(17) & ((uint32_t)(regval) << 17U)) /*!< write value to CAN_PN_CTL0_WTOIE bit */ 1040 1041 /* CAN_PN_TO register */ 1042 #define PN_TO_WTO(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_PN_TO_WTO bit field */ 1043 1044 /* CAN_PN_STAT register */ 1045 #define GET_PN_STAT_MMCNT(regval) GET_BITS((regval),8,15) /*!< get matching message counter in Pretended Networking mode */ 1046 1047 /* CAN_PN_EID0 register */ 1048 #define PN_EID0_EIDF_ELT_STD(regval) (BITS(18,28) & ((uint32_t)(regval) << 18U)) /*!< write value to CAN_PN_EID0_EIDF_ELT bit field for standard frames */ 1049 #define PN_EID0_EIDF_ELT_EXD(regval) (BITS(0,28) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_PN_EID0_EIDF_ELT bit field for extended frames */ 1050 1051 /* CAN_PN_EDLC register */ 1052 #define PN_EDLC_DLCEHT(regval) (BITS(0,3) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_PN_EDLC_DLCEHT bit field */ 1053 #define PN_EDLC_DLCELT(regval) (BITS(16,19) & ((uint32_t)(regval) << 16U)) /*!< write value to CAN_PN_EDLC_DLCELT bit field */ 1054 1055 /* CAN_PN_IFEID1 register */ 1056 #define PN_IFEID1_IDEFD_STD(regval) (BITS(18,28) & ((uint32_t)(regval) << 18U)) /*!< write value to CAN_PN_IFEID1_IDEFD bit field for standard frames */ 1057 #define PN_IFEID1_IDEFD_EXD(regval) (BITS(0,28) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_PN_IFEID1_IDEFD bit field for extended frames */ 1058 1059 /* CAN_FDCTL register */ 1060 #define GET_FDCTL_TDCV(regval) GET_BITS((regval),0,5) /*!< get transmitter delay compensation value */ 1061 1062 #define FDCTL_TDCO(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to CAN_FDCTL_TDCO bit field */ 1063 1064 #define FDCTL_MDSZ(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U)) /*!< write value to CAN_FDCTL_MDSZ bit field */ 1065 #define CAN_MAILBOX_DATA_SIZE_8_BYTES FDCTL_MDSZ(0U) /*!< mailbox data size is 8 bytes */ 1066 #define CAN_MAILBOX_DATA_SIZE_16_BYTES FDCTL_MDSZ(1U) /*!< mailbox data size is 16 bytes */ 1067 #define CAN_MAILBOX_DATA_SIZE_32_BYTES FDCTL_MDSZ(2U) /*!< mailbox data size is 32 bytes */ 1068 #define CAN_MAILBOX_DATA_SIZE_64_BYTES FDCTL_MDSZ(3U) /*!< mailbox data size is 64 bytes */ 1069 1070 /* CAN_FDBT register */ 1071 #define FDBT_DPBS2(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_FDBT_DPBS2 bit field */ 1072 #define FDBT_DPBS1(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U)) /*!< write value to CAN_FDBT_DPBS1 bit field */ 1073 #define FDBT_DPTS(regval) (BITS(10,14) & ((uint32_t)(regval) << 10U)) /*!< write value to CAN_FDBT_DPTS bit field */ 1074 #define FDBT_DSJW(regval) (BITS(16,18) & ((uint32_t)(regval) << 16U)) /*!< write value to CAN_FDBT_DSJW bit field */ 1075 #define FDBT_DBAUDPSC(regval) (BITS(20,29) & ((uint32_t)(regval) << 20U)) /*!< write value to CAN_FDBT_DBAUDPSC bit field */ 1076 1077 /* CAN_CRCCFD register */ 1078 #define GET_CRCCFD_CRCTCI(regval) GET_BITS((regval),0,20) /*!< get transmitted CRC value for classical and ISO / non-ISO FD frames */ 1079 #define GET_CRCCFD_ANTM(regval) GET_BITS((regval),24,28) /*!< get associated number of mailbox for transmitting the CRCTCI[20:0] value */ 1080 1081 /* MDES0 descriptor */ 1082 #define MDES0_DLC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16U)) /*!< write value to MDES0 descriptor DLC bit field */ 1083 1084 #define MDES0_CODE(regval) (((uint32_t)(regval) << 24U) & CAN_MDES0_CODE) 1085 #define CAN_MB_RX_STATUS_INACTIVE (0U) /*!< mailbox receive status inactive */ 1086 #define CAN_MB_RX_STATUS_FULL (2U) /*!< mailbox receive status full */ 1087 #define CAN_MB_RX_STATUS_EMPTY (4U) /*!< mailbox receive status empty */ 1088 #define CAN_MB_RX_STATUS_OVERRUN (6U) /*!< mailbox receive status overrun */ 1089 #define CAN_MB_RX_STATUS_RANSWER (10U) /*!< mailbox receive status answer */ 1090 #define CAN_MB_RX_STATUS_BUSY (1U) /*!< mailbox receive status busy */ 1091 #define CAN_MB_TX_STATUS_INACTIVE (8U) /*!< mailbox transmit status inactive */ 1092 #define CAN_MB_TX_STATUS_ABORT (9U) /*!< mailbox transmit status abort */ 1093 #define CAN_MB_TX_STATUS_DATA (12U) /*!< mailbox transmit status data */ 1094 1095 #define GET_MDES0_CODE(regval) GET_BITS((regval),24,27) /*!< get MDES0 descriptor CODE bit field */ 1096 1097 /* MDES1 descriptor */ 1098 #define GET_MDES1_ID_EXD(regval) GET_BITS((regval),0,28) /*!< get MDES1 descriptor ID_STD and ID_EXD bit field */ 1099 #define MDES1_ID_EXD(regval) (BITS(0,28) & ((uint32_t)(regval) << 0U)) /*!< write value to MDES1 descriptor ID_STD and ID_EXD bit field */ 1100 1101 #define GET_MDES1_ID_STD(regval) GET_BITS((regval),18,28) /*!< get MDES1 descriptor ID_STD bit field */ 1102 #define MDES1_ID_STD(regval) (BITS(18,28) & ((uint32_t)(regval) << 18U)) /*!< write value to MDES1 descriptor ID_STD bit field */ 1103 1104 #define MDES1_PRIO(regval) (BITS(29,31) & ((uint32_t)(regval) << 29U)) /*!< write value to MDES1 descriptor PRIO bit field */ 1105 1106 /* FDES1 descriptor */ 1107 #define GET_FDES1_ID_EXD(regval) GET_BITS((regval),0,28) /*!< get FDES1 descriptor ID_STD and ID_EXD bit field */ 1108 #define FDES1_ID_EXD(regval) (BITS(0,28) & ((uint32_t)(regval) << 0U)) /*!< write value to FDES1 descriptor ID_STD and ID_EXD bit field */ 1109 1110 #define GET_FDES1_ID_STD(regval) GET_BITS((regval),18,28) /*!< get FDES1 descriptor ID_STD bit field */ 1111 #define FDES1_ID_STD(regval) (BITS(18,28) & ((uint32_t)(regval) << 18U)) /*!< write value to FDES1 descriptor ID_STD bit field */ 1112 1113 /* FDESx descriptor */ 1114 #define CAN_DATA_FRAME_ACCEPTED ((uint32_t)0x00000000U) /*!< remote frames are rejected and data frames can be stored */ 1115 #define CAN_REMOTE_FRAME_ACCEPTED ((uint32_t)0x00000001U) /*!< remote frames can be stored and data frames are rejected */ 1116 1117 #define CAN_STANDARD_FRAME_ACCEPTED ((uint32_t)0x00000000U) /*!< extended frames are rejected and standard frames can be stored */ 1118 #define CAN_EXTENDED_FRAME_ACCEPTED ((uint32_t)0x00000001U) /*!< extended frames can be stored and standard frames are rejected */ 1119 1120 #define FIFO_FILTER_ID_EXD_A(val) (((uint32_t)(val) << 0U) & CAN_FDESX_ID_EXD_A) /*!< valid extended ID filter field in format A */ 1121 #define FIFO_FILTER_ID_STD_A(val) (((uint32_t)(val) << 18U) & CAN_FDESX_ID_STD_A)/*!< valid standard ID filter field in format A */ 1122 #define FIFO_FILTER_ID_EXD_B0(val) (GET_BITS((val),15,28) << 16U) /*!< valid extended ID filter field in format B */ 1123 #define FIFO_FILTER_ID_EXD_B1(val) (GET_BITS((val),15,28) << 0U) /*!< valid extended ID filter field in format B */ 1124 #define FIFO_FILTER_ID_STD_B0(val) (GET_BITS((val),0,10) << 19U) /*!< valid standard ID filter field in format B */ 1125 #define FIFO_FILTER_ID_STD_B1(val) (GET_BITS((val),0,10) << 3U) /*!< valid standard ID filter field in format B */ 1126 #define FIFO_FILTER_ID_EXD_C0(val) (GET_BITS((val),21,28) << 24U) /*!< valid extended ID filter field in format C */ 1127 #define FIFO_FILTER_ID_EXD_C1(val) (GET_BITS((val),21,28) << 16U) /*!< valid extended ID filter field in format C */ 1128 #define FIFO_FILTER_ID_EXD_C2(val) (GET_BITS((val),21,28) << 8U) /*!< valid extended ID filter field in format C */ 1129 #define FIFO_FILTER_ID_EXD_C3(val) (GET_BITS((val),21,28) << 0U) /*!< valid extended ID filter field in format C */ 1130 #define FIFO_FILTER_ID_STD_C0(val) (GET_BITS((val),3,10) << 24U) /*!< valid standard ID filter field in format C */ 1131 #define FIFO_FILTER_ID_STD_C1(val) (GET_BITS((val),3,10) << 16U) /*!< valid standard ID filter field in format C */ 1132 #define FIFO_FILTER_ID_STD_C2(val) (GET_BITS((val),3,10) << 8U) /*!< valid standard ID filter field in format C */ 1133 #define FIFO_FILTER_ID_STD_C3(val) (GET_BITS((val),3,10) << 0U) /*!< valid standard ID filter field in format C */ 1134 1135 /* timeout definitions */ 1136 #define CAN_DELAY ((uint32_t)0x01FFFFFFU) /*!< state timeout */ 1137 #define CAN_MAX_MAILBOX_NUM 32U /*!< the supported maximum mailbox number */ 1138 #define CAN_MAX_RAM_SIZE (CAN_MAX_MAILBOX_NUM * 4U) /*!< the maximum RAM size used for CAN mailbox */ 1139 1140 1141 /* function declarations */ 1142 /* CAN module initialize */ 1143 /* deinitialize CAN */ 1144 void can_deinit(uint32_t can_periph); 1145 /* reset CAN interanl state machines and CAN registers */ 1146 ErrStatus can_software_reset(uint32_t can_periph); 1147 /* CAN module initialization */ 1148 ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); 1149 /* initialize CAN parameter structure with a default value */ 1150 void can_struct_para_init(can_struct_type_enum type, void *p_struct); 1151 /* configure receive fifo/mailbox private filter */ 1152 void can_private_filter_config(uint32_t can_periph, uint32_t index, uint32_t filter_data); 1153 1154 /* CAN operation modes */ 1155 /* enter the corresponding mode */ 1156 ErrStatus can_operation_mode_enter(uint32_t can_periph, can_operation_modes_enum mode); 1157 /* get operation mode */ 1158 can_operation_modes_enum can_operation_mode_get(uint32_t can_periph); 1159 /* exit inactive mode */ 1160 ErrStatus can_inactive_mode_exit(uint32_t can_periph); 1161 /* exit Pretended Networking mode */ 1162 ErrStatus can_pn_mode_exit(uint32_t can_periph); 1163 1164 /* CAN FD mode configuration */ 1165 /* can FD initialize */ 1166 void can_fd_config(uint32_t can_periph, can_fd_parameter_struct *can_fd_para_init); 1167 /* enable bit rate switching */ 1168 void can_bitrate_switch_enable(uint32_t can_periph); 1169 /* disable bit rate switching */ 1170 void can_bitrate_switch_disable(uint32_t can_periph); 1171 /* get transmitter delay compensation value */ 1172 uint32_t can_tdc_get(uint32_t can_periph); 1173 /* enable transmitter delay compensation */ 1174 void can_tdc_enable(uint32_t can_periph); 1175 /* disable transmitter delay compensation */ 1176 void can_tdc_disable(uint32_t can_periph); 1177 1178 /* CAN FIFO configuration */ 1179 /* configure rx FIFO */ 1180 void can_rx_fifo_config(uint32_t can_periph, can_fifo_parameter_struct *can_fifo_para_init); 1181 /* configure rx FIFO filter table */ 1182 void can_rx_fifo_filter_table_config(uint32_t can_periph, can_rx_fifo_id_filter_struct id_filter_table[]); 1183 /* read rx FIFO data */ 1184 void can_rx_fifo_read(uint32_t can_periph, can_rx_fifo_struct *rx_fifo); 1185 /* get rx FIFO filter matching number */ 1186 uint32_t can_rx_fifo_filter_matching_number_get(uint32_t can_periph); 1187 /* clear rx FIFO */ 1188 void can_rx_fifo_clear(uint32_t can_periph); 1189 1190 /* CAN mailbox operation */ 1191 /* get mailbox RAM address */ 1192 uint32_t *can_ram_address_get(uint32_t can_periph, uint32_t index); 1193 /* config mailbox */ 1194 void can_mailbox_config(uint32_t can_periph, uint32_t index, can_mailbox_descriptor_struct *mdpara); 1195 /* abort mailbox transmit */ 1196 void can_mailbox_transmit_abort(uint32_t can_periph, uint32_t index); 1197 /* inactive transmit mailbox */ 1198 void can_mailbox_transmit_inactive(uint32_t can_periph, uint32_t index); 1199 /* read receive mailbox data */ 1200 ErrStatus can_mailbox_receive_data_read(uint32_t can_periph, uint32_t index, can_mailbox_descriptor_struct *mdpara); 1201 /* lock the receive mailbox */ 1202 void can_mailbox_receive_lock(uint32_t can_periph, uint32_t index); 1203 /* unlock the receive mailbox */ 1204 void can_mailbox_receive_unlock(uint32_t can_periph); 1205 /* inactive the receive mailbox */ 1206 void can_mailbox_receive_inactive(uint32_t can_periph, uint32_t index); 1207 /* get mailbox code value */ 1208 uint32_t can_mailbox_code_get(uint32_t can_periph, uint32_t index); 1209 1210 /* errors & CRC */ 1211 /* configure error counter */ 1212 void can_error_counter_config(uint32_t can_periph, can_error_counter_struct *errcnt_struct); 1213 /* get error count */ 1214 void can_error_counter_get(uint32_t can_periph, can_error_counter_struct *errcnt_struct); 1215 /* get error state indicator */ 1216 can_error_state_enum can_error_state_get(uint32_t can_periph); 1217 /* get mailbox CRC value */ 1218 void can_crc_get(uint32_t can_periph, can_crc_struct *crc_struct); 1219 1220 /* Pretended Networking mode configuration */ 1221 /* configure Pretended Networking mode parameter */ 1222 void can_pn_mode_config(uint32_t can_periph, can_pn_mode_config_struct *pnmod_config); 1223 /* configure pn mode filter */ 1224 void can_pn_mode_filter_config(uint32_t can_periph, can_pn_mode_filter_struct *expect, can_pn_mode_filter_struct *filter); 1225 /* get matching message counter of Pretended Networking mode */ 1226 int32_t can_pn_mode_num_of_match_get(uint32_t can_periph); 1227 /* get matching message */ 1228 void can_pn_mode_data_read(uint32_t can_periph, uint32_t index, can_mailbox_descriptor_struct *mdpara); 1229 1230 /* others */ 1231 /* enable self reception */ 1232 void can_self_reception_enable(uint32_t can_periph); 1233 /* disable self reception */ 1234 void can_self_reception_disable(uint32_t can_periph); 1235 /* enable transmit abort */ 1236 void can_transmit_abort_enable(uint32_t can_periph); 1237 /* disable transmit abort */ 1238 void can_transmit_abort_disable(uint32_t can_periph); 1239 /* enable auto bus off recovery mode */ 1240 void can_auto_busoff_recovery_enable(uint32_t can_periph); 1241 /* disable auto bus off recovery mode */ 1242 void can_auto_busoff_recovery_disable(uint32_t can_periph); 1243 /* enable time sync mode */ 1244 void can_time_sync_enable(uint32_t can_periph); 1245 /* disable time sync mode */ 1246 void can_time_sync_disable(uint32_t can_periph); 1247 /* enable edge filter mode */ 1248 void can_edge_filter_mode_enable(uint32_t can_periph); 1249 /* disable edge filter mode */ 1250 void can_edge_filter_mode_disable(uint32_t can_periph); 1251 /* enable protocol exception detection mode */ 1252 void can_ped_mode_enable(uint32_t can_periph); 1253 /* disable protocol exception detection mode */ 1254 void can_ped_mode_disable(uint32_t can_periph); 1255 /* configure arbitation delay bits */ 1256 void can_arbitation_delay_bits_config(uint32_t can_periph, uint32_t delay_bits); 1257 /* configure bit sampling mode */ 1258 void can_bsp_mode_config(uint32_t can_periph, uint32_t sampling_mode); 1259 1260 /* CAN interrupt and flag */ 1261 /* get CAN flag */ 1262 FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); 1263 /* clear CAN flag */ 1264 void can_flag_clear(uint32_t can_periph, can_flag_enum flag); 1265 /* enable CAN interrupt */ 1266 void can_interrupt_enable(uint32_t can_periph, can_interrupt_enum interrupt); 1267 /* disable CAN interrupt */ 1268 void can_interrupt_disable(uint32_t can_periph, can_interrupt_enum interrupt); 1269 /* get CAN interrupt flag */ 1270 FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum int_flag); 1271 /* clear CAN interrupt flag */ 1272 void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum int_flag); 1273 1274 #endif /* GD32A50X_CAN_H */ 1275
