1 /*! 2 \file gd32e50x_sqpi.h 3 \brief definitions for the SQPI 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2021, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32E50X_SQPI_H 38 #define GD32E50X_SQPI_H 39 40 #include "gd32e50x.h" 41 42 /* SQPI definitions */ 43 #define SQPI SQPI_BASE 44 /* SQPI registers definitions */ 45 #define SQPI_INIT REG32((SQPI) + 0x00000000U) /*!< SQPI initial register*/ 46 #define SQPI_RCMD REG32((SQPI) + 0x00000004U) /*!< SQPI read command register */ 47 #define SQPI_WCMD REG32((SQPI) + 0x00000008U) /*!< SQPI write command register */ 48 #define SQPI_IDL REG32((SQPI) + 0x0000000CU) /*!< SQPI ID low register */ 49 #define SQPI_IDH REG32((SQPI) + 0x00000010U) /*!< SQPI ID high register */ 50 51 52 /* bits definitions */ 53 /* SQPI_INIT */ 54 #define SQPI_INIT_CMDBIT BITS(16,17) /*!< bit number of SQPI controller command phase */ 55 #define SQPI_INIT_CLKDIV BITS(18,23) /*!< clock divider for SQPI output clock */ 56 #define SQPI_INIT_ADDRBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase*/ 57 #define SQPI_INIT_IDLEN BITS(29,30) /*!< external memory ID length */ 58 #define SQPI_INIT_PL BIT(31) /*!< SQPI read data sample polarity */ 59 60 /* SQPI_RCMD */ 61 #define SQPI_RCMD_RCMD BITS(0,15) /*!< SQPI read command for AHB read transfer */ 62 #define SQPI_RCMD_RWAITCYCLE BITS(16,19) /*!< read command waitcycle number */ 63 #define SQPI_RCMD_RMODE BITS(20,22) /*!< read command mode */ 64 #define SQPI_RCMD_RID BIT(31) /*!< send read ID command */ 65 66 /* SQPI_WCMD */ 67 #define SQPI_WCMD_WCMD BITS(0,15) /*!< SQPI write command for AHB write transfer */ 68 #define SQPI_WCMD_WWAITCYCLE BITS(16,19) /*!< write command waitcycle number */ 69 #define SQPI_WCMD_WMODE BITS(20,22) /*!< write command mode */ 70 #define SQPI_WCMD_SCMD BIT(31) /*!< send special command */ 71 72 /* SQPI_IDL */ 73 #define SQPI_IDL_IDL BITS(0,31) /*!< ID low register */ 74 75 /* SQPI_IDH */ 76 #define SQPI_IDH_IDH BITS(0,31) /*!< ID high register */ 77 78 79 /* constants definitions */ 80 /* SQPI parameter struct definitions */ 81 typedef struct 82 { 83 uint32_t polarity; /*!< SQPI sample polarity*/ 84 uint32_t id_length; /*!< external memory ID length */ 85 uint32_t addr_bit; /*!< bit number of SPI PSRAM address phase */ 86 uint32_t clk_div; /*!< clock divider for SQPI output clock */ 87 uint32_t cmd_bit; /*!< bit number of SQPI controller command phase */ 88 }sqpi_parameter_struct; 89 /* SQPI sample shift */ 90 #define SQPI_SAMPLE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< SQPI read data at rising edge */ 91 #define SQPI_SAMPLE_POLARITY_FALLING (SQPI_INIT_PL) /*!< SQPI read data at falling edge */ 92 93 /* SQPI ID length */ 94 #define INIT_IDLEN(regval) (BITS(29,30) & ((uint32_t)(regval) << 29)) 95 #define SQPI_ID_LENGTH_64_BITS INIT_IDLEN(0) /*!< 64 bits ID */ 96 #define SQPI_ID_LENGTH_32_BITS INIT_IDLEN(1) /*!< 32 bits ID */ 97 #define SQPI_ID_LENGTH_16_BITS INIT_IDLEN(2) /*!< 16 bits ID */ 98 #define SQPI_ID_LENGTH_8_BITS INIT_IDLEN(3) /*!< 8 bits ID */ 99 100 /* SQPI command bits */ 101 #define INIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) 102 #define SQPI_CMDBIT_4_BITS INIT_CMDBIT(0) /*!< 4 bits command */ 103 #define SQPI_CMDBIT_8_BITS INIT_CMDBIT(1) /*!< 8 bits command */ 104 #define SQPI_CMDBIT_16_BITS INIT_CMDBIT(2) /*!< 16 bits command */ 105 106 /* SQPI mode */ 107 #define SQPI_MODE(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) 108 #define SQPI_MODE_SSQ SQPI_MODE(0) /*!< SQPI SSQ mode */ 109 #define SQPI_MODE_SSS SQPI_MODE(1) /*!< SQPI SSS mode */ 110 #define SQPI_MODE_SQQ SQPI_MODE(2) /*!< SQPI SQQ mode */ 111 #define SQPI_MODE_QQQ SQPI_MODE(3) /*!< SQPI QQQ mode */ 112 #define SQPI_MODE_SSD SQPI_MODE(4) /*!< SQPI SSD mode */ 113 #define SQPI_MODE_SDD SQPI_MODE(5) /*!< SQPI SDD mode */ 114 115 /* function declarations */ 116 /* SQPI deinitialization and initialization functions */ 117 /* reset SQPI */ 118 void sqpi_deinit(void); 119 /* initialize the parameters of SQPI struct with the default values */ 120 void sqpi_struct_para_init(sqpi_parameter_struct* sqpi_struct); 121 /* initialize SQPI parameter */ 122 void sqpi_init(sqpi_parameter_struct *sqpi_struct); 123 124 /* send SQPI read ID command */ 125 void sqpi_read_id_command(void); 126 /* send SQPI special command */ 127 void sqpi_special_command(void); 128 /* configure SQPI read command */ 129 void sqpi_read_command_config(uint32_t rmode, uint32_t rwaitcycle, uint32_t rcmd); 130 /* configure SQPI write command */ 131 void sqpi_write_command_config(uint32_t wmode, uint32_t wwaitcycle, uint32_t wcmd); 132 /* SQPI receive low ID */ 133 uint32_t sqpi_low_id_receive(void); 134 /* SQPI receive high ID*/ 135 uint32_t sqpi_high_id_receive(void); 136 137 #endif /* GD32E50X_SQPI_H */ 138
