1 /*! 2 \file gd32e50x_shrtimer.h 3 \brief definitions for the SHRTIMER 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2021, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32E50X_SHRTIMER_H 38 #define GD32E50X_SHRTIMER_H 39 40 #include "gd32e50x.h" 41 42 /* SHRTIMERy(y=0) definitions */ 43 #define SHRTIMER0 (SHRTIMER_BASE + 0x00000000U) 44 45 /* registers definitions */ 46 /* Master_TIMER registers definitions */ 47 #define SHRTIMER_MTCTL0(shrtimery) REG32((shrtimery) + 0x00000000U) /*!< SHRTIMER Master_TIMER control register 0 */ 48 #define SHRTIMER_MTINTF(shrtimery) REG32((shrtimery) + 0x00000004U) /*!< SHRTIMER Master_TIMER interrupt flag register */ 49 #define SHRTIMER_MTINTC(shrtimery) REG32((shrtimery) + 0x00000008U) /*!< SHRTIMER Master_TIMER interrupt flag clear register */ 50 #define SHRTIMER_MTDMAINTEN(shrtimery) REG32((shrtimery) + 0x0000000CU) /*!< SHRTIMER Master_TIMER DMA and interrupt enable register */ 51 #define SHRTIMER_MTCNT(shrtimery) REG32((shrtimery) + 0x00000010U) /*!< SHRTIMER Master_TIMER counter register */ 52 #define SHRTIMER_MTCAR(shrtimery) REG32((shrtimery) + 0x00000014U) /*!< SHRTIMER Master_TIMER counter auto reload register */ 53 #define SHRTIMER_MTCREP(shrtimery) REG32((shrtimery) + 0x00000018U) /*!< SHRTIMER Master_TIMER counter repetition register */ 54 #define SHRTIMER_MTCMP0V(shrtimery) REG32((shrtimery) + 0x0000001CU) /*!< SHRTIMER Master_TIMER compare 0 value register */ 55 #define SHRTIMER_MTCMP1V(shrtimery) REG32((shrtimery) + 0x00000024U) /*!< SHRTIMER Master_TIMER compare 1 value register */ 56 #define SHRTIMER_MTCMP2V(shrtimery) REG32((shrtimery) + 0x00000028U) /*!< SHRTIMER Master_TIMER compare 2 value register */ 57 #define SHRTIMER_MTCMP3V(shrtimery) REG32((shrtimery) + 0x0000002CU) /*!< SHRTIMER Master_TIMER compare 3 value register */ 58 #define SHRTIMER_MTACTL(shrtimery) REG32((shrtimery) + 0x0000007CU) /*!< SHRTIMER Master_TIMER additional control register */ 59 60 /* Slave_TIMERx(x=0..4) registers definitions */ 61 #define SHRTIMER_STXCTL0(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000000U) /*!< SHRTIMER Slave_TIMERx control register 0 */ 62 #define SHRTIMER_STXINTF(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000004U) /*!< SHRTIMER Slave_TIMERx interrupt flag register */ 63 #define SHRTIMER_STXINTC(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000008U) /*!< SHRTIMER Slave_TIMERx interrupt flag clear register */ 64 #define SHRTIMER_STXDMAINTEN(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x0000000CU) /*!< SHRTIMER Slave_TIMERx DMA and interrupt enable register */ 65 #define SHRTIMER_STXCNT(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000010U) /*!< SHRTIMER Slave_TIMERx counter register */ 66 #define SHRTIMER_STXCAR(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000014U) /*!< SHRTIMER Slave_TIMERx counter auto reload register */ 67 #define SHRTIMER_STXCREP(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000018U) /*!< SHRTIMER Slave_TIMERx counter repetition register */ 68 #define SHRTIMER_STXCMP0V(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x0000001CU) /*!< SHRTIMER Slave_TIMERx compare 0 value register */ 69 #define SHRTIMER_STXCMP0CP(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000020U) /*!< SHRTIMER Slave_TIMERx compare 0 composite register */ 70 #define SHRTIMER_STXCMP1V(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000024U) /*!< SHRTIMER Slave_TIMERx compare 1 value register */ 71 #define SHRTIMER_STXCMP2V(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000028U) /*!< SHRTIMER Slave_TIMERx compare 2 value register */ 72 #define SHRTIMER_STXCMP3V(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x0000002CU) /*!< SHRTIMER Slave_TIMERx compare 3 value register */ 73 #define SHRTIMER_STXCAP0V(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000030U) /*!< SHRTIMER Slave_TIMERx capture 0 value register */ 74 #define SHRTIMER_STXCAP1V(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000034U) /*!< SHRTIMER Slave_TIMERx capture 1 value register */ 75 #define SHRTIMER_STXDTCTL(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000038U) /*!< SHRTIMER Slave_TIMERx dead-time control register */ 76 #define SHRTIMER_STXCH0SET(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x0000003CU) /*!< SHRTIMER Slave_TIMERx channel 0 set request register */ 77 #define SHRTIMER_STXCH0RST(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000040U) /*!< SHRTIMER Slave_TIMERx channel 0 reset request register */ 78 #define SHRTIMER_STXCH1SET(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000044U) /*!< SHRTIMER Slave_TIMERx channel 1 set request register */ 79 #define SHRTIMER_STXCH1RST(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000048U) /*!< SHRTIMER Slave_TIMERx channel 1 reset request register */ 80 #define SHRTIMER_STXEXEVFCFG0(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x0000004CU) /*!< SHRTIMER Slave_TIMERx external event filter configuration register 0 */ 81 #define SHRTIMER_STXEXEVFCFG1(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000050U) /*!< SHRTIMER Slave_TIMERx external event filter configuration register 1 */ 82 #define SHRTIMER_STXCNTRST(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000054U) /*!< SHRTIMER Slave_TIMERx counter reset register */ 83 #define SHRTIMER_STXCSCTL(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000058U) /*!< SHRTIMER Slave_TIMERx carrier-signal control register */ 84 #define SHRTIMER_STXCAP0TRG(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x0000005CU) /*!< SHRTIMER Slave_TIMERx capture 0 trigger register */ 85 #define SHRTIMER_STXCAP1TRG(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000060U) /*!< SHRTIMER Slave_TIMERx capture 1 trigger register */ 86 #define SHRTIMER_STXCHOCTL(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000064U) /*!< SHRTIMER Slave_TIMERx channel output control register */ 87 #define SHRTIMER_STXFLTCTL(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x00000068U) /*!< SHRTIMER Slave_TIMERx fault control register */ 88 #define SHRTIMER_STXACTL(shrtimery, slavex) REG32((shrtimery) + (((slavex) + 0x0001U) * 0x0080U) + 0x0000007CU) /*!< SHRTIMER Slave_TIMERx additional control register */ 89 90 /* common registers definitions */ 91 #define SHRTIMER_CTL0(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000000U) /*!< SHRTIMER control register 0 */ 92 #define SHRTIMER_CTL1(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000004U) /*!< SHRTIMER control register 1 */ 93 #define SHRTIMER_INTF(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000008U) /*!< SHRTIMER interrupt flag register */ 94 #define SHRTIMER_INTC(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x0000000CU) /*!< SHRTIMER interrupt flag clear register */ 95 #define SHRTIMER_INTEN(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000010U) /*!< SHRTIMER interrupt enable register */ 96 #define SHRTIMER_CHOUTEN(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000014U) /*!< SHRTIMER channel output enable register */ 97 #define SHRTIMER_CHOUTDIS(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000018U) /*!< SHRTIMER channel output disable register */ 98 #define SHRTIMER_CHOUTDISF(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x0000001CU) /*!< SHRTIMER channel output disable flag register */ 99 #define SHRTIMER_BMCTL(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000020U) /*!< SHRTIMER bunch mode control register */ 100 #define SHRTIMER_BMSTRG(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000024U) /*!< SHRTIMER bunch mode start trigger register */ 101 #define SHRTIMER_BMCMPV(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000028U) /*!< SHRTIMER bunch mode compare value register */ 102 #define SHRTIMER_BMCAR(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x0000002CU) /*!< SHRTIMER bunch mode counter auto reload register */ 103 #define SHRTIMER_EXEVCFG0(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000030U) /*!< SHRTIMER external event configuration register 0 */ 104 #define SHRTIMER_EXEVCFG1(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000034U) /*!< SHRTIMER external event configuration register 1 */ 105 #define SHRTIMER_EXEVDFCTL(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000038U) /*!< SHRTIMER external event digital filter control register */ 106 #define SHRTIMER_ADCTRIGS0(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x0000003CU) /*!< SHRTIMER trigger source 0 to ADC register */ 107 #define SHRTIMER_ADCTRIGS1(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000040U) /*!< SHRTIMER trigger source 1 to ADC register */ 108 #define SHRTIMER_ADCTRIGS2(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000044U) /*!< SHRTIMER trigger source 2 to ADC register */ 109 #define SHRTIMER_ADCTRIGS3(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000048U) /*!< SHRTIMER trigger source 3 to ADC register */ 110 #define SHRTIMER_DLLCCTL(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x0000004CU) /*!< SHRTIMER DLL calibration control register */ 111 #define SHRTIMER_FLTINCFG0(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000050U) /*!< SHRTIMER fault input configuration register 0 */ 112 #define SHRTIMER_FLTINCFG1(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000054U) /*!< SHRTIMER fault input configuration register 1 */ 113 #define SHRTIMER_DMAUPMTR(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000058U) /*!< SHRTIMER DMA update Master_TIMER register */ 114 #define SHRTIMER_DMAUPST0R(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x0000005CU) /*!< SHRTIMER DMA update Slave_TIMER0 register */ 115 #define SHRTIMER_DMAUPST1R(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000060U) /*!< SHRTIMER DMA update Slave_TIMER1 register */ 116 #define SHRTIMER_DMAUPST2R(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000064U) /*!< SHRTIMER DMA update Slave_TIMER2 register */ 117 #define SHRTIMER_DMAUPST3R(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000068U) /*!< SHRTIMER DMA update Slave_TIMER3 register */ 118 #define SHRTIMER_DMAUPST4R(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x0000006CU) /*!< SHRTIMER DMA update Slave_TIMER4 register */ 119 #define SHRTIMER_DMATB(shrtimery) REG32(((shrtimery) + 0x00000380U) + 0x00000070U) /*!< SHRTIMER DMA transfer buffer register */ 120 121 /* bits definitions */ 122 /* Master_TIMER registers */ 123 /* SHRTIMER_MTCTL0 */ 124 #define SHRTIMER_MTCTL0_CNTCKDIV2_0 BITS(0,2) /*!< counter clock division */ 125 #define SHRTIMER_MTCTL0_CTNM BIT(3) /*!< continuous mode */ 126 #define SHRTIMER_MTCTL0_CNTRSTM BIT(4) /*!< counter reset mode */ 127 #define SHRTIMER_MTCTL0_HALFM BIT(5) /*!< half mode */ 128 #define SHRTIMER_MTCTL0_SYNISRC BITS(8,9) /*!< synchronization input source */ 129 #define SHRTIMER_MTCTL0_SYNIRST BIT(10) /*!< synchronization input reset counter */ 130 #define SHRTIMER_MTCTL0_SYNISTRT BIT(11) /*!< synchronization input start counter */ 131 #define SHRTIMER_MTCTL0_SYNOPLS BITS(12,13) /*!< synchronization output pulse */ 132 #define SHRTIMER_MTCTL0_SYNOSRC BITS(14,15) /*!< synchronization output source */ 133 #define SHRTIMER_MTCTL0_MTCEN BIT(16) /*!< the counter of Master_TIMER enable */ 134 #define SHRTIMER_MTCTL0_ST0CEN BIT(17) /*!< the counter of Slave_TIMER0 enable */ 135 #define SHRTIMER_MTCTL0_ST1CEN BIT(18) /*!< the counter of Slave_TIMER1 enable */ 136 #define SHRTIMER_MTCTL0_ST2CEN BIT(19) /*!< the counter of Slave_TIMER2 enable */ 137 #define SHRTIMER_MTCTL0_ST3CEN BIT(20) /*!< the counter of Slave_TIMER3 enable */ 138 #define SHRTIMER_MTCTL0_ST4CEN BIT(21) /*!< the counter of Slave_TIMER4 enable */ 139 #define SHRTIMER_MTCTL0_DACTRGS BITS(25,26) /*!< trigger source to DAC */ 140 #define SHRTIMER_MTCTL0_SHWEN BIT(27) /*!< shadow registers enable */ 141 #define SHRTIMER_MTCTL0_UPREP BIT(29) /*!< update event generated by repetition event */ 142 #define SHRTIMER_MTCTL0_UPSEL BITS(30,31) /*!< update event selection */ 143 144 /* SHRTIMER_MTINTF */ 145 #define SHRTIMER_MTINTF_CMP0IF BIT(0) /*!< compare 0 interrupt flag */ 146 #define SHRTIMER_MTINTF_CMP1IF BIT(1) /*!< compare 1 interrupt flag */ 147 #define SHRTIMER_MTINTF_CMP2IF BIT(2) /*!< compare 2 interrupt flag */ 148 #define SHRTIMER_MTINTF_CMP3IF BIT(3) /*!< compare 3 interrupt flag */ 149 #define SHRTIMER_MTINTF_REPIF BIT(4) /*!< repetition interrupt flag */ 150 #define SHRTIMER_MTINTF_SYNIIF BIT(5) /*!< synchronization input interrupt flag */ 151 #define SHRTIMER_MTINTF_UPIF BIT(6) /*!< update interrupt flag */ 152 153 /* SHRTIMER_MTINTC */ 154 #define SHRTIMER_MTINTC_CMP0IFC BIT(0) /*!< clear compare 0 interrupt flag */ 155 #define SHRTIMER_MTINTC_CMP1IFC BIT(1) /*!< clear compare 1 interrupt flag */ 156 #define SHRTIMER_MTINTC_CMP2IFC BIT(2) /*!< clear compare 2 interrupt flag */ 157 #define SHRTIMER_MTINTC_CMP3IFC BIT(3) /*!< clear compare 3 interrupt flag */ 158 #define SHRTIMER_MTINTC_REPIFC BIT(4) /*!< clear repetition interrupt flag */ 159 #define SHRTIMER_MTINTC_SYNIIFC BIT(5) /*!< clear synchronization input interrupt flag */ 160 #define SHRTIMER_MTINTC_UPIFC BIT(6) /*!< clear update interrupt flag */ 161 162 /* SHRTIMER_MTDMAINTEN */ 163 #define SHRTIMER_MTDMAINTEN_CMP0IE BIT(0) /*!< compare 0 interrupt enable */ 164 #define SHRTIMER_MTDMAINTEN_CMP1IE BIT(1) /*!< compare 1 interrupt enable */ 165 #define SHRTIMER_MTDMAINTEN_CMP2IE BIT(2) /*!< compare 2 interrupt enable */ 166 #define SHRTIMER_MTDMAINTEN_CMP3IE BIT(3) /*!< compare 3 interrupt enable */ 167 #define SHRTIMER_MTDMAINTEN_REPIE BIT(4) /*!< repetition interrupt enable */ 168 #define SHRTIMER_MTDMAINTEN_SYNIIE BIT(5) /*!< synchronization input interrupt enable */ 169 #define SHRTIMER_MTDMAINTEN_UPIE BIT(6) /*!< update interrupt enable */ 170 #define SHRTIMER_MTDMAINTEN_CMP0DEN BIT(16) /*!< compare 0 DMA request enable */ 171 #define SHRTIMER_MTDMAINTEN_CMP1DEN BIT(17) /*!< compare 1 DMA request enable */ 172 #define SHRTIMER_MTDMAINTEN_CMP2DEN BIT(18) /*!< compare 2 DMA request enable */ 173 #define SHRTIMER_MTDMAINTEN_CMP3DEN BIT(19) /*!< compare 3 DMA request enable */ 174 #define SHRTIMER_MTDMAINTEN_REPDEN BIT(20) /*!< repetition DMA request enable */ 175 #define SHRTIMER_MTDMAINTEN_SYNIDEN BIT(21) /*!< synchronization input DMA request enable */ 176 #define SHRTIMER_MTDMAINTEN_UPDEN BIT(22) /*!< update DMA request enable */ 177 178 /* SHRTIMER_MTCNT */ 179 #define SHRTIMER_MTCNT_CNT BITS(0,15) /*!< the current counter value */ 180 181 /* SHRTIMER_MTCAR */ 182 #define SHRTIMER_MTCAR_CARL BITS(0,15) /*!< counter auto reload value */ 183 184 /* SHRTIMER_MTCREP */ 185 #define SHRTIMER_MTCREP_CREP BITS(0,7) /*!< counter repetition value */ 186 187 /* SHRTIMER_MTCMP0V */ 188 #define SHRTIMER_MTCMP0V_CMP0VAL BITS(0,15) /*!< compare 0 value */ 189 190 /* SHRTIMER_MTCMP1V */ 191 #define SHRTIMER_MTCMP1V_CMP1VAL BITS(0,15) /*!< compare 1 value */ 192 193 /* SHRTIMER_MTCMP2V */ 194 #define SHRTIMER_MTCMP2V_CMP0VAL BITS(0,15) /*!< compare 2 value */ 195 196 /* SHRTIMER_MTCMP3V */ 197 #define SHRTIMER_MTCMP3V_CMP0VAL BITS(0,15) /*!< compare 3 value */ 198 199 /* SHRTIMER_MTACTL */ 200 #define SHRTIMER_MTACTL_CNTCKDIV3 BIT(3) /*!< counter clock division */ 201 202 /* Slave_TIMERx registers(x=0..4) */ 203 /* SHRTIMER_STxCTL0 */ 204 #define SHRTIMER_STXCTL0_CNTCKDIV2_0 BITS(0,2) /*!< counter clock division */ 205 #define SHRTIMER_STXCTL0_CTNM BIT(3) /*!< continuous mode */ 206 #define SHRTIMER_STXCTL0_CNTRSTM BIT(4) /*!< counter reset mode */ 207 #define SHRTIMER_STXCTL0_HALFM BIT(5) /*!< half mode */ 208 #define SHRTIMER_STXCTL0_BLNMEN BIT(6) /*!< balanced mode enable */ 209 #define SHRTIMER_STXCTL0_SYNIRST BIT(10) /*!< synchronization input reset counter */ 210 #define SHRTIMER_STXCTL0_SYNISTRT BIT(11) /*!< synchronization input start counter */ 211 #define SHRTIMER_STXCTL0_DELCMP1M BITS(12,13) /*!< compare 1 delayed mode */ 212 #define SHRTIMER_STXCTL0_DELCMP3M BITS(14,15) /*!< compare 3 delayed mode */ 213 #define SHRTIMER_STXCTL0_UPREP BIT(17) /*!< update event generated by repetition event */ 214 #define SHRTIMER_STXCTL0_UPRST BIT(18) /*!< update event generated by reset event */ 215 #define SHRTIMER_STXCTL0_UPBST0 BIT(19) /*!< update by Slave_TIMER0 update event */ 216 #define SHRTIMER_STXCTL0_UPBST1 BIT(20) /*!< update by Slave_TIMER1 update event */ 217 #define SHRTIMER_STXCTL0_UPBST2 BIT(21) /*!< update by Slave_TIMER2 update event */ 218 #define SHRTIMER_STXCTL0_UPBST3 BIT(22) /*!< update by Slave_TIMER3 update event */ 219 #define SHRTIMER_STXCTL0_UPBST4 BIT(23) /*!< update by Slave_TIMER4 update event */ 220 #define SHRTIMER_STXCTL0_UPBMT BIT(24) /*!< update by Master_TIMER update event */ 221 #define SHRTIMER_STXCTL0_DACTRGS BITS(25,26) /*!< trigger source to DAC */ 222 #define SHRTIMER_STXCTL0_SHWEN BIT(27) /*!< shadow registers enable */ 223 #define SHRTIMER_STXCTL0_UPSEL BITS(28,31) /*!< update event selection */ 224 225 /* SHRTIMER_STxINTF */ 226 #define SHRTIMER_STXINTF_CMP0IF BIT(0) /*!< compare 0 interrupt flag */ 227 #define SHRTIMER_STXINTF_CMP1IF BIT(1) /*!< compare 1 interrupt flag */ 228 #define SHRTIMER_STXINTF_CMP2IF BIT(2) /*!< compare 2 interrupt flag */ 229 #define SHRTIMER_STXINTF_CMP3IF BIT(3) /*!< compare 3 interrupt flag */ 230 #define SHRTIMER_STXINTF_REPIF BIT(4) /*!< repetition interrupt flag */ 231 #define SHRTIMER_STXINTF_UPIF BIT(6) /*!< update interrupt flag */ 232 #define SHRTIMER_STXINTF_CAP0IF BIT(7) /*!< capture 0 interrupt flag */ 233 #define SHRTIMER_STXINTF_CAP1IF BIT(8) /*!< capture 1 interrupt flag */ 234 #define SHRTIMER_STXINTF_CH0OAIF BIT(9) /*!< channel 0 output active interrupt flag */ 235 #define SHRTIMER_STXINTF_CH0ONAIF BIT(10) /*!< channel 0 output inactive interrupt flag */ 236 #define SHRTIMER_STXINTF_CH1OAIF BIT(11) /*!< channel 1 output active interrupt flag */ 237 #define SHRTIMER_STXINTF_CH1ONAIF BIT(12) /*!< channel 1 output inactive interrupt flag */ 238 #define SHRTIMER_STXINTF_RSTIF BIT(13) /*!< counter reset interrupt flag */ 239 #define SHRTIMER_STXINTF_DLYIIF BIT(14) /*!< delayed IDLE mode entry interrupt flag */ 240 #define SHRTIMER_STXINTF_CBLNF BIT(16) /*!< current balanced flag */ 241 #define SHRTIMER_STXINTF_BLNIF BIT(17) /*!< balanced IDLE flag */ 242 #define SHRTIMER_STXINTF_CH0F BIT(20) /*!< channel 0 output flag */ 243 #define SHRTIMER_STXINTF_CH1F BIT(21) /*!< channel 1 output flag */ 244 245 /* SHRTIMER_STxINTC */ 246 #define SHRTIMER_STXINTC_CMP0IFC BIT(0) /*!< clear compare 0 interrupt flag */ 247 #define SHRTIMER_STXINTC_CMP1IFC BIT(1) /*!< clear compare 1 interrupt flag */ 248 #define SHRTIMER_STXINTC_CMP2IFC BIT(2) /*!< clear compare 2 interrupt flag */ 249 #define SHRTIMER_STXINTC_CMP3IFC BIT(3) /*!< clear compare 3 interrupt flag */ 250 #define SHRTIMER_STXINTC_REPIFC BIT(4) /*!< clear repetition interrupt flag */ 251 #define SHRTIMER_STXINTC_UPIFC BIT(6) /*!< clear update interrupt flag */ 252 #define SHRTIMER_STXINTC_CAP0IFC BIT(7) /*!< clear capture 0 interrupt flag */ 253 #define SHRTIMER_STXINTC_CAP1IFC BIT(8) /*!< clear capture 1 interrupt flag */ 254 #define SHRTIMER_STXINTC_CH0OAIFC BIT(9) /*!< clear channel 0 output active interrupt flag */ 255 #define SHRTIMER_STXINTC_CH0ONAIFC BIT(10) /*!< clear channel 0 output inactive interrupt flag */ 256 #define SHRTIMER_STXINTC_CH1OAIFC BIT(11) /*!< clear channel 1 output active interrupt flag */ 257 #define SHRTIMER_STXINTC_CH1ONAIFC BIT(12) /*!< clear channel 1 output inactive interrupt flag */ 258 #define SHRTIMER_STXINTC_RSTIFC BIT(13) /*!< clear counter reset interrupt flag */ 259 #define SHRTIMER_STXINTC_DLYIIFC BIT(14) /*!< clear delayed IDLE mode entry interrupt flag */ 260 261 /* SHRTIMER_STxDMAINTEN */ 262 #define SHRTIMER_STXDMAINTEN_CMP0IE BIT(0) /*!< compare 0 interrupt enable */ 263 #define SHRTIMER_STXDMAINTEN_CMP1IE BIT(1) /*!< compare 1 interrupt enable */ 264 #define SHRTIMER_STXDMAINTEN_CMP2IE BIT(2) /*!< compare 2 interrupt enable */ 265 #define SHRTIMER_STXDMAINTEN_CMP3IE BIT(3) /*!< compare 3 interrupt enable */ 266 #define SHRTIMER_STXDMAINTEN_REPIE BIT(4) /*!< repetition interrupt enable */ 267 #define SHRTIMER_STXDMAINTEN_UPIE BIT(6) /*!< update interrupt enable */ 268 #define SHRTIMER_STXDMAINTEN_CAP0IE BIT(7) /*!< capture 0 interrupt enable */ 269 #define SHRTIMER_STXDMAINTEN_CAP1IE BIT(8) /*!< capture 1 interrupt enable */ 270 #define SHRTIMER_STXDMAINTEN_CH0OAIE BIT(9) /*!< channel 0 output active interrupt enable */ 271 #define SHRTIMER_STXDMAINTEN_CH0ONAIE BIT(10) /*!< channel 0 output inactive interrupt enable */ 272 #define SHRTIMER_STXDMAINTEN_CH1OAIE BIT(11) /*!< channel 1 output active interrupt enable */ 273 #define SHRTIMER_STXDMAINTEN_CH1ONAIE BIT(12) /*!< channel 1 output inactive interrupt enable */ 274 #define SHRTIMER_STXDMAINTEN_RSTIE BIT(13) /*!< counter reset interrupt enable */ 275 #define SHRTIMER_STXDMAINTEN_DLYIIE BIT(14) /*!< delayed IDLE mode entry interrupt enable */ 276 #define SHRTIMER_STXDMAINTEN_CMP0DEN BIT(16) /*!< compare 0 DMA request enable */ 277 #define SHRTIMER_STXDMAINTEN_CMP1DEN BIT(17) /*!< compare 1 DMA request enable */ 278 #define SHRTIMER_STXDMAINTEN_CMP2DEN BIT(18) /*!< compare 2 DMA request enable */ 279 #define SHRTIMER_STXDMAINTEN_CMP3DEN BIT(19) /*!< compare 3 DMA request enable */ 280 #define SHRTIMER_STXDMAINTEN_REPDEN BIT(20) /*!< repetition DMA request enable */ 281 #define SHRTIMER_STXDMAINTEN_UPDEN BIT(22) /*!< update DMA request enable */ 282 #define SHRTIMER_STXDMAINTEN_CAP0DEN BIT(23) /*!< capture 0 DMA request enable */ 283 #define SHRTIMER_STXDMAINTEN_CAP1DEN BIT(24) /*!< capture 1 DMA request enable */ 284 #define SHRTIMER_STXDMAINTEN_CH0OADEN BIT(25) /*!< channel 0 output active DMA request enable */ 285 #define SHRTIMER_STXDMAINTEN_CH0ONADEN BIT(26) /*!< channel 0 output inactive DMA request enable */ 286 #define SHRTIMER_STXDMAINTEN_CH1OADEN BIT(27) /*!< channel 1 output active DMA request enable */ 287 #define SHRTIMER_STXDMAINTEN_CH1ONADEN BIT(28) /*!< channel 1 output inactive DMA request enable */ 288 #define SHRTIMER_STXDMAINTEN_RSTDEN BIT(29) /*!< counter reset DMA request enable */ 289 #define SHRTIMER_STXDMAINTEN_DLYIDEN BIT(30) /*!< delayed IDLE mode entry DMA request enable */ 290 291 /* SHRTIMER_STxCNT */ 292 #define SHRTIMER_STXCNT_CNT BITS(0,15) /*!< the current counter value */ 293 294 /* SHRTIMER_STxCAR */ 295 #define SHRTIMER_STXCAR_CARL BITS(0,15) /*!< counter auto reload value */ 296 297 /* SHRTIMER_STxCREP */ 298 #define SHRTIMER_STXCREP_CREP BITS(0,7) /*!< counter repetition value */ 299 300 /* SHRTIMER_STxCMP0V */ 301 #define SHRTIMER_STXCMP0V_CMP0VAL BITS(0,15) /*!< compare 0 value */ 302 303 /* SHRTIMER_STxCMP0CP */ 304 #define SHRTIMER_STXCMP0CP_CMP0VAL BITS(0,15) /*!< compare 0 value */ 305 #define SHRTIMER_STXCMP0CP_CREP BITS(16,23) /*!< counter repetition value */ 306 307 /* SHRTIMER_STxCMP1V */ 308 #define SHRTIMER_STXCMP1V_CMP1VAL BITS(0,15) /*!< compare 1 value */ 309 310 /* SHRTIMER_STxCMP2V */ 311 #define SHRTIMER_STXCMP2V_CMP2VAL BITS(0,15) /*!< compare 2 value */ 312 313 /* SHRTIMER_STxCMP3V */ 314 #define SHRTIMER_STXCMP3V_CMP3VAL BITS(0,15) /*!< compare 3 value */ 315 316 /* SHRTIMER_STxCAP0V */ 317 #define SHRTIMER_STXCAP0V_CAP0VAL BITS(0,15) /*!< capture 0 value */ 318 319 /* SHRTIMER_STxCAP1V */ 320 #define SHRTIMER_STXCAP1V_CAP1VAL BITS(0,15) /*!< capture 1 value */ 321 322 /* SHRTIMER_STxDTCTL */ 323 #define SHRTIMER_STXDTCTL_DTRCFG8_0 BITS(0,8) /*!< rising edge dead-time value */ 324 #define SHRTIMER_STXDTCTL_DTRS BIT(9) /*!< the sign of rising edge dead-time value */ 325 #define SHRTIMER_STXDTCTL_DTGCKDIV BITS(10,13) /*!< dead time generator clock division */ 326 #define SHRTIMER_STXDTCTL_DTRSPROT BIT(14) /*!< dead-time rising edge protection for sign */ 327 #define SHRTIMER_STXDTCTL_DTRSVPROT BIT(15) /*!< dead-time rising edge protection for value and sign */ 328 #define SHRTIMER_STXDTCTL_DTFCFG8_0 BITS(16,24) /*!< falling edge dead-time value */ 329 #define SHRTIMER_STXDTCTL_DTFS BIT(25) /*!< the sign of falling edge dead-time value */ 330 #define SHRTIMER_STXDTCTL_DTFSPROT BIT(30) /*!< dead-time falling edge protection for sign */ 331 #define SHRTIMER_STXDTCTL_DTFSVPROT BIT(31) /*!< dead-time falling edge protection for value and sign */ 332 333 /* SHRTIMER_STxCH0SET */ 334 #define SHRTIMER_STXCH0SET_CH0SSEV BIT(0) /*!< software event generates channel 0 ��set request�� */ 335 #define SHRTIMER_STXCH0SET_CH0SRST BIT(1) /*!< Slave_TIMERx reset event generates channel 0 ��set request�� */ 336 #define SHRTIMER_STXCH0SET_CH0SPER BIT(2) /*!< Slave_TIMERx period event generates channel 0 ��set request�� */ 337 #define SHRTIMER_STXCH0SET_CH0SCMP0 BIT(3) /*!< Slave_TIMERx compare 0 event generates channel 0 ��set request�� */ 338 #define SHRTIMER_STXCH0SET_CH0SCMP1 BIT(4) /*!< Slave_TIMERx compare 1 event generates channel 0 ��set request�� */ 339 #define SHRTIMER_STXCH0SET_CH0SCMP2 BIT(5) /*!< Slave_TIMERx compare 2 event generates channel 0 ��set request�� */ 340 #define SHRTIMER_STXCH0SET_CH0SCMP3 BIT(6) /*!< Slave_TIMERx compare 3 event generates channel 0 ��set request�� */ 341 #define SHRTIMER_STXCH0SET_CH0SMTPER BIT(7) /*!< Master_TIMER period event generates channel 0 ��set request�� */ 342 #define SHRTIMER_STXCH0SET_CH0SMTCMP0 BIT(8) /*!< Master_TIMER compare 0 event generates channel 0 ��set request�� */ 343 #define SHRTIMER_STXCH0SET_CH0SMTCMP1 BIT(9) /*!< Master_TIMER compare 1 event generates channel 0 ��set request�� */ 344 #define SHRTIMER_STXCH0SET_CH0SMTCMP2 BIT(10) /*!< Master_TIMER compare 2 event generates channel 0 ��set request�� */ 345 #define SHRTIMER_STXCH0SET_CH0SMTCMP3 BIT(11) /*!< Master_TIMER compare 3 event generates channel 0 ��set request�� */ 346 #define SHRTIMER_STXCH0SET_CH0SSTEV0 BIT(12) /*!< Slave_TIMERx interconnection event 0 generates channel 0 ��set request�� */ 347 #define SHRTIMER_STXCH0SET_CH0SSTEV1 BIT(13) /*!< Slave_TIMERx interconnection event 1 generates channel 0 ��set request�� */ 348 #define SHRTIMER_STXCH0SET_CH0SSTEV2 BIT(14) /*!< Slave_TIMERx interconnection event 2 generates channel 0 ��set request�� */ 349 #define SHRTIMER_STXCH0SET_CH0SSTEV3 BIT(15) /*!< Slave_TIMERx interconnection event 3 generates channel 0 ��set request�� */ 350 #define SHRTIMER_STXCH0SET_CH0SSTEV4 BIT(16) /*!< Slave_TIMERx interconnection event 4 generates channel 0 ��set request�� */ 351 #define SHRTIMER_STXCH0SET_CH0SSTEV5 BIT(17) /*!< Slave_TIMERx interconnection event 5 generates channel 0 ��set request�� */ 352 #define SHRTIMER_STXCH0SET_CH0SSTEV6 BIT(18) /*!< Slave_TIMERx interconnection event 6 generates channel 0 ��set request�� */ 353 #define SHRTIMER_STXCH0SET_CH0SSTEV7 BIT(19) /*!< Slave_TIMERx interconnection event 7 generates channel 0 ��set request�� */ 354 #define SHRTIMER_STXCH0SET_CH0SSTEV8 BIT(20) /*!< Slave_TIMERx interconnection event 8 generates channel 0 ��set request�� */ 355 #define SHRTIMER_STXCH0SET_CH0SEXEV0 BIT(21) /*!< external event 0 generates channel 0 ��set request�� */ 356 #define SHRTIMER_STXCH0SET_CH0SEXEV1 BIT(22) /*!< external event 1 generates channel 0 ��set request�� */ 357 #define SHRTIMER_STXCH0SET_CH0SEXEV2 BIT(23) /*!< external event 2 generates channel 0 ��set request�� */ 358 #define SHRTIMER_STXCH0SET_CH0SEXEV3 BIT(24) /*!< external event 3 generates channel 0 ��set request�� */ 359 #define SHRTIMER_STXCH0SET_CH0SEXEV4 BIT(25) /*!< external event 4 generates channel 0 ��set request�� */ 360 #define SHRTIMER_STXCH0SET_CH0SEXEV5 BIT(26) /*!< external event 5 generates channel 0 ��set request�� */ 361 #define SHRTIMER_STXCH0SET_CH0SEXEV6 BIT(27) /*!< external event 6 generates channel 0 ��set request�� */ 362 #define SHRTIMER_STXCH0SET_CH0SEXEV7 BIT(28) /*!< external event 7 generates channel 0 ��set request�� */ 363 #define SHRTIMER_STXCH0SET_CH0SEXEV8 BIT(29) /*!< external event 8 generates channel 0 ��set request�� */ 364 #define SHRTIMER_STXCH0SET_CH0SEXEV9 BIT(30) /*!< external event 9 generates channel 0 ��set request�� */ 365 #define SHRTIMER_STXCH0SET_CH0SUP BIT(31) /*!< update event generates channel 0 ��set request�� */ 366 367 /* SHRTIMER_STxCH0RST */ 368 #define SHRTIMER_STXCH0RST_CH0RSSEV BIT(0) /*!< software event generates channel 0 ��reset request�� */ 369 #define SHRTIMER_STXCH0RST_CH0RSRST BIT(1) /*!< Slave_TIMERx reset event generates channel 0 ��reset request�� */ 370 #define SHRTIMER_STXCH0RST_CH0RSPER BIT(2) /*!< Slave_TIMERx period event generates channel 0 ��reset request�� */ 371 #define SHRTIMER_STXCH0RST_CH0RSCMP0 BIT(3) /*!< Slave_TIMERx compare 0 event generates channel 0 ��reset request�� */ 372 #define SHRTIMER_STXCH0RST_CH0RSCMP1 BIT(4) /*!< Slave_TIMERx compare 1 event generates channel 0 ��reset request�� */ 373 #define SHRTIMER_STXCH0RST_CH0RSCMP2 BIT(5) /*!< Slave_TIMERx compare 2 event generates channel 0 ��reset request�� */ 374 #define SHRTIMER_STXCH0RST_CH0RSCMP3 BIT(6) /*!< Slave_TIMERx compare 3 event generates channel 0 ��reset request�� */ 375 #define SHRTIMER_STXCH0RST_CH0RSMTPER BIT(7) /*!< Master_TIMER period event generates channel 0 ��reset request�� */ 376 #define SHRTIMER_STXCH0RST_CH0RSMTCMP0 BIT(8) /*!< Master_TIMER compare 0 event generates channel 0 ��reset request�� */ 377 #define SHRTIMER_STXCH0RST_CH0RSMTCMP1 BIT(9) /*!< Master_TIMER compare 1 event generates channel 0 ��reset request�� */ 378 #define SHRTIMER_STXCH0RST_CH0RSMTCMP2 BIT(10) /*!< Master_TIMER compare 2 event generates channel 0 ��reset request�� */ 379 #define SHRTIMER_STXCH0RST_CH0RSMTCMP3 BIT(11) /*!< Master_TIMER compare 3 event generates channel 0 ��reset request�� */ 380 #define SHRTIMER_STXCH0RST_CH0RSSTEV0 BIT(12) /*!< Slave_TIMERx interconnection event 0 generates channel 0 ��reset request�� */ 381 #define SHRTIMER_STXCH0RST_CH0RSSTEV1 BIT(13) /*!< Slave_TIMERx interconnection event 1 generates channel 0 ��reset request�� */ 382 #define SHRTIMER_STXCH0RST_CH0RSSTEV2 BIT(14) /*!< Slave_TIMERx interconnection event 2 generates channel 0 ��reset request�� */ 383 #define SHRTIMER_STXCH0RST_CH0RSSTEV3 BIT(15) /*!< Slave_TIMERx interconnection event 3 generates channel 0 ��reset request�� */ 384 #define SHRTIMER_STXCH0RST_CH0RSSTEV4 BIT(16) /*!< Slave_TIMERx interconnection event 4 generates channel 0 ��reset request�� */ 385 #define SHRTIMER_STXCH0RST_CH0RSSTEV5 BIT(17) /*!< Slave_TIMERx interconnection event 5 generates channel 0 ��reset request�� */ 386 #define SHRTIMER_STXCH0RST_CH0RSSTEV6 BIT(18) /*!< Slave_TIMERx interconnection event 6 generates channel 0 ��reset request�� */ 387 #define SHRTIMER_STXCH0RST_CH0RSSTEV7 BIT(19) /*!< Slave_TIMERx interconnection event 7 generates channel 0 ��reset request�� */ 388 #define SHRTIMER_STXCH0RST_CH0RSSTEV8 BIT(20) /*!< Slave_TIMERx interconnection event 8 generates channel 0 ��reset request�� */ 389 #define SHRTIMER_STXCH0RST_CH0RSEXEV0 BIT(21) /*!< external event 0 generates channel 0 ��reset request�� */ 390 #define SHRTIMER_STXCH0RST_CH0RSEXEV1 BIT(22) /*!< external event 1 generates channel 0 ��reset request�� */ 391 #define SHRTIMER_STXCH0RST_CH0RSEXEV2 BIT(23) /*!< external event 2 generates channel 0 ��reset request�� */ 392 #define SHRTIMER_STXCH0RST_CH0RSEXEV3 BIT(24) /*!< external event 3 generates channel 0 ��reset request�� */ 393 #define SHRTIMER_STXCH0RST_CH0RSEXEV4 BIT(25) /*!< external event 4 generates channel 0 ��reset request�� */ 394 #define SHRTIMER_STXCH0RST_CH0RSEXEV5 BIT(26) /*!< external event 5 generates channel 0 ��reset request�� */ 395 #define SHRTIMER_STXCH0RST_CH0RSEXEV6 BIT(27) /*!< external event 6 generates channel 0 ��reset request�� */ 396 #define SHRTIMER_STXCH0RST_CH0RSEXEV7 BIT(28) /*!< external event 7 generates channel 0 ��reset request�� */ 397 #define SHRTIMER_STXCH0RST_CH0RSEXEV8 BIT(29) /*!< external event 8 generates channel 0 ��reset request�� */ 398 #define SHRTIMER_STXCH0RST_CH0RSEXEV9 BIT(30) /*!< external event 9 generates channel 0 ��reset request�� */ 399 #define SHRTIMER_STXCH0RST_CH0RSUP BIT(31) /*!< update event generates channel 0 ��reset request�� */ 400 401 /* SHRTIMER_STxCH1SET */ 402 #define SHRTIMER_STXCH1SET_CH1SSEV BIT(0) /*!< software event generates channel 1 ��set request�� */ 403 #define SHRTIMER_STXCH1SET_CH1SRST BIT(1) /*!< Slave_TIMERx reset event generates channel 1 ��set request�� */ 404 #define SHRTIMER_STXCH1SET_CH1SPER BIT(2) /*!< Slave_TIMERx period event generates channel 1 ��set request�� */ 405 #define SHRTIMER_STXCH1SET_CH1SCMP0 BIT(3) /*!< Slave_TIMERx compare 0 event generates channel 1 ��set request�� */ 406 #define SHRTIMER_STXCH1SET_CH1SCMP1 BIT(4) /*!< Slave_TIMERx compare 1 event generates channel 1 ��set request�� */ 407 #define SHRTIMER_STXCH1SET_CH1SCMP2 BIT(5) /*!< Slave_TIMERx compare 2 event generates channel 1 ��set request�� */ 408 #define SHRTIMER_STXCH1SET_CH1SCMP3 BIT(6) /*!< Slave_TIMERx compare 3 event generates channel 1 ��set request�� */ 409 #define SHRTIMER_STXCH1SET_CH1SMTPER BIT(7) /*!< Master_TIMER period event generates channel 1 ��set request�� */ 410 #define SHRTIMER_STXCH1SET_CH1SMTCMP0 BIT(8) /*!< Master_TIMER compare 0 event generates channel 1 ��set request�� */ 411 #define SHRTIMER_STXCH1SET_CH1SMTCMP1 BIT(9) /*!< Master_TIMER compare 1 event generates channel 1 ��set request�� */ 412 #define SHRTIMER_STXCH1SET_CH1SMTCMP2 BIT(10) /*!< Master_TIMER compare 2 event generates channel 1 ��set request�� */ 413 #define SHRTIMER_STXCH1SET_CH1SMTCMP3 BIT(11) /*!< Master_TIMER compare 3 event generates channel 1 ��set request�� */ 414 #define SHRTIMER_STXCH1SET_CH1SSTEV0 BIT(12) /*!< Slave_TIMERx interconnection event 0 generates channel 1 ��set request�� */ 415 #define SHRTIMER_STXCH1SET_CH1SSTEV1 BIT(13) /*!< Slave_TIMERx interconnection event 1 generates channel 1 ��set request�� */ 416 #define SHRTIMER_STXCH1SET_CH1SSTEV2 BIT(14) /*!< Slave_TIMERx interconnection event 2 generates channel 1 ��set request�� */ 417 #define SHRTIMER_STXCH1SET_CH1SSTEV3 BIT(15) /*!< Slave_TIMERx interconnection event 3 generates channel 1 ��set request�� */ 418 #define SHRTIMER_STXCH1SET_CH1SSTEV4 BIT(16) /*!< Slave_TIMERx interconnection event 4 generates channel 1 ��set request�� */ 419 #define SHRTIMER_STXCH1SET_CH1SSTEV5 BIT(17) /*!< Slave_TIMERx interconnection event 5 generates channel 1 ��set request�� */ 420 #define SHRTIMER_STXCH1SET_CH1SSTEV6 BIT(18) /*!< Slave_TIMERx interconnection event 6 generates channel 1 ��set request�� */ 421 #define SHRTIMER_STXCH1SET_CH1SSTEV7 BIT(19) /*!< Slave_TIMERx interconnection event 7 generates channel 1 ��set request�� */ 422 #define SHRTIMER_STXCH1SET_CH1SSTEV8 BIT(20) /*!< Slave_TIMERx interconnection event 8 generates channel 1 ��set request�� */ 423 #define SHRTIMER_STXCH1SET_CH1SEXEV0 BIT(21) /*!< external event 0 generates channel 1 ��set request�� */ 424 #define SHRTIMER_STXCH1SET_CH1SEXEV1 BIT(22) /*!< external event 1 generates channel 1 ��set request�� */ 425 #define SHRTIMER_STXCH1SET_CH1SEXEV2 BIT(23) /*!< external event 2 generates channel 1 ��set request�� */ 426 #define SHRTIMER_STXCH1SET_CH1SEXEV3 BIT(24) /*!< external event 3 generates channel 1 ��set request�� */ 427 #define SHRTIMER_STXCH1SET_CH1SEXEV4 BIT(25) /*!< external event 4 generates channel 1 ��set request�� */ 428 #define SHRTIMER_STXCH1SET_CH1SEXEV5 BIT(26) /*!< external event 5 generates channel 1 ��set request�� */ 429 #define SHRTIMER_STXCH1SET_CH1SEXEV6 BIT(27) /*!< external event 6 generates channel 1 ��set request�� */ 430 #define SHRTIMER_STXCH1SET_CH1SEXEV7 BIT(28) /*!< external event 7 generates channel 1 ��set request�� */ 431 #define SHRTIMER_STXCH1SET_CH1SEXEV8 BIT(29) /*!< external event 8 generates channel 1 ��set request�� */ 432 #define SHRTIMER_STXCH1SET_CH1SEXEV9 BIT(30) /*!< external event 9 generates channel 1 ��set request�� */ 433 #define SHRTIMER_STXCH1SET_CH1SUP BIT(31) /*!< update event generates channel 1 ��set request�� */ 434 435 /* SHRTIMER_STxCH1RST */ 436 #define SHRTIMER_STXCH1RST_CH1RSSEV BIT(0) /*!< software event generates channel 1 ��reset request�� */ 437 #define SHRTIMER_STXCH1RST_CH1RSRST BIT(1) /*!< Slave_TIMERx reset event generates channel 1 ��reset request�� */ 438 #define SHRTIMER_STXCH1RST_CH1RSPER BIT(2) /*!< Slave_TIMERx period event generates channel 1 ��reset request�� */ 439 #define SHRTIMER_STXCH1RST_CH1RSCMP0 BIT(3) /*!< Slave_TIMERx compare 0 event generates channel 1 ��reset request�� */ 440 #define SHRTIMER_STXCH1RST_CH1RSCMP1 BIT(4) /*!< Slave_TIMERx compare 1 event generates channel 1 ��reset request�� */ 441 #define SHRTIMER_STXCH1RST_CH1RSCMP2 BIT(5) /*!< Slave_TIMERx compare 2 event generates channel 1 ��reset request�� */ 442 #define SHRTIMER_STXCH1RST_CH1RSCMP3 BIT(6) /*!< Slave_TIMERx compare 3 event generates channel 1 ��reset request�� */ 443 #define SHRTIMER_STXCH1RST_CH1RSMTPER BIT(7) /*!< Master_TIMER period event generates channel 1 ��reset request�� */ 444 #define SHRTIMER_STXCH1RST_CH1RSMTCMP0 BIT(8) /*!< Master_TIMER compare 0 event generates channel 1 ��reset request�� */ 445 #define SHRTIMER_STXCH1RST_CH1RSMTCMP1 BIT(9) /*!< Master_TIMER compare 1 event generates channel 1 ��reset request�� */ 446 #define SHRTIMER_STXCH1RST_CH1RSMTCMP2 BIT(10) /*!< Master_TIMER compare 2 event generates channel 1 ��reset request�� */ 447 #define SHRTIMER_STXCH1RST_CH1RSMTCMP3 BIT(11) /*!< Master_TIMER compare 3 event generates channel 1 ��reset request�� */ 448 #define SHRTIMER_STXCH1RST_CH1RSSTEV0 BIT(12) /*!< Slave_TIMERx interconnection event 0 generates channel 1 ��reset request�� */ 449 #define SHRTIMER_STXCH1RST_CH1RSSTEV1 BIT(13) /*!< Slave_TIMERx interconnection event 1 generates channel 1 ��reset request�� */ 450 #define SHRTIMER_STXCH1RST_CH1RSSTEV2 BIT(14) /*!< Slave_TIMERx interconnection event 2 generates channel 1 ��reset request�� */ 451 #define SHRTIMER_STXCH1RST_CH1RSSTEV3 BIT(15) /*!< Slave_TIMERx interconnection event 3 generates channel 1 ��reset request�� */ 452 #define SHRTIMER_STXCH1RST_CH1RSSTEV4 BIT(16) /*!< Slave_TIMERx interconnection event 4 generates channel 1 ��reset request�� */ 453 #define SHRTIMER_STXCH1RST_CH1RSSTEV5 BIT(17) /*!< Slave_TIMERx interconnection event 5 generates channel 1 ��reset request�� */ 454 #define SHRTIMER_STXCH1RST_CH1RSSTEV6 BIT(18) /*!< Slave_TIMERx interconnection event 6 generates channel 1 ��reset request�� */ 455 #define SHRTIMER_STXCH1RST_CH1RSSTEV7 BIT(19) /*!< Slave_TIMERx interconnection event 7 generates channel 1 ��reset request�� */ 456 #define SHRTIMER_STXCH1RST_CH1RSSTEV8 BIT(20) /*!< Slave_TIMERx interconnection event 8 generates channel 1 ��reset request�� */ 457 #define SHRTIMER_STXCH1RST_CH1RSEXEV0 BIT(21) /*!< external event 0 generates channel 1 ��reset request�� */ 458 #define SHRTIMER_STXCH1RST_CH1RSEXEV1 BIT(22) /*!< external event 1 generates channel 1 ��reset request�� */ 459 #define SHRTIMER_STXCH1RST_CH1RSEXEV2 BIT(23) /*!< external event 2 generates channel 1 ��reset request�� */ 460 #define SHRTIMER_STXCH1RST_CH1RSEXEV3 BIT(24) /*!< external event 3 generates channel 1 ��reset request�� */ 461 #define SHRTIMER_STXCH1RST_CH1RSEXEV4 BIT(25) /*!< external event 4 generates channel 1 ��reset request�� */ 462 #define SHRTIMER_STXCH1RST_CH1RSEXEV5 BIT(26) /*!< external event 5 generates channel 1 ��reset request�� */ 463 #define SHRTIMER_STXCH1RST_CH1RSEXEV6 BIT(27) /*!< external event 6 generates channel 1 ��reset request�� */ 464 #define SHRTIMER_STXCH1RST_CH1RSEXEV7 BIT(28) /*!< external event 7 generates channel 1 ��reset request�� */ 465 #define SHRTIMER_STXCH1RST_CH1RSEXEV8 BIT(29) /*!< external event 8 generates channel 1 ��reset request�� */ 466 #define SHRTIMER_STXCH1RST_CH1RSEXEV9 BIT(30) /*!< external event 9 generates channel 1 ��reset request�� */ 467 #define SHRTIMER_STXCH1RST_CH1RSUP BIT(31) /*!< update event generates channel 1 ��reset request�� */ 468 469 /* SHRTIMER_STxEXEVFCFG0 */ 470 #define SHRTIMER_STXEXEVFCFG0_EXEV0MEEN BIT(0) /*!< external event 0 memory */ 471 #define SHRTIMER_STXEXEVFCFG0_EXEV0FM BITS(1,4) /*!< external event 0 filter mode */ 472 #define SHRTIMER_STXEXEVFCFG0_EXEV1MEEN BIT(6) /*!< external event 1 memory */ 473 #define SHRTIMER_STXEXEVFCFG0_EXEV1FM BITS(7,10) /*!< external event 1 filter mode */ 474 #define SHRTIMER_STXEXEVFCFG0_EXEV2MEEN BIT(12) /*!< external event 2 memory */ 475 #define SHRTIMER_STXEXEVFCFG0_EXEV2FM BITS(13,16) /*!< external event 2 filter mode */ 476 #define SHRTIMER_STXEXEVFCFG0_EXEV3MEEN BIT(18) /*!< external event 3 memory */ 477 #define SHRTIMER_STXEXEVFCFG0_EXEV3FM BITS(19,22) /*!< external event 3 filter mode */ 478 #define SHRTIMER_STXEXEVFCFG0_EXEV4MEEN BIT(24) /*!< external event 4 memory */ 479 #define SHRTIMER_STXEXEVFCFG0_EXEV4FM BITS(25,28) /*!< external event 4 filter mode */ 480 481 /* SHRTIMER_STxEXEVFCFG1 */ 482 #define SHRTIMER_STXEXEVFCFG1_EXEV5MEEN BIT(0) /*!< external event 5 memory */ 483 #define SHRTIMER_STXEXEVFCFG1_EXEV5FM BITS(1,4) /*!< external event 5 filter mode */ 484 #define SHRTIMER_STXEXEVFCFG1_EXEV6MEEN BIT(6) /*!< external event 6 memory */ 485 #define SHRTIMER_STXEXEVFCFG1_EXEV6FM BITS(7,10) /*!< external event 6 filter mode */ 486 #define SHRTIMER_STXEXEVFCFG1_EXEV7MEEN BIT(12) /*!< external event 7 memory */ 487 #define SHRTIMER_STXEXEVFCFG1_EXEV7FM BITS(13,16) /*!< external event 7 filter mode */ 488 #define SHRTIMER_STXEXEVFCFG1_EXEV8MEEN BIT(18) /*!< external event 8 memory */ 489 #define SHRTIMER_STXEXEVFCFG1_EXEV8FM BITS(19,22) /*!< external event 8 filter mode */ 490 #define SHRTIMER_STXEXEVFCFG1_EXEV9MEEN BIT(24) /*!< external event 9 memory */ 491 #define SHRTIMER_STXEXEVFCFG1_EXEV9FM BITS(25,28) /*!< external event 9 filter mode */ 492 493 /* SHRTIMER_STxCNTRST */ 494 #define SHRTIMER_STXCNTRST_UPRST BIT(1) /*!< Slave_TIMER0 update event resets counter */ 495 #define SHRTIMER_STXCNTRST_CMP1RST BIT(2) /*!< Slave_TIMER0 compare 1 event resets counter */ 496 #define SHRTIMER_STXCNTRST_CMP3RST BIT(3) /*!< Slave_TIMER0 compare 3 event resets counter */ 497 #define SHRTIMER_STXCNTRST_MTPERRST BIT(4) /*!< Master_TIMER period event resets counter */ 498 #define SHRTIMER_STXCNTRST_MTCMP0RST BIT(5) /*!< Master_TIMER compare 0 event resets counter */ 499 #define SHRTIMER_STXCNTRST_MTCMP1RST BIT(6) /*!< Master_TIMER compare 1 event resets counter */ 500 #define SHRTIMER_STXCNTRST_MTCMP2RST BIT(7) /*!< Master_TIMER compare 2 event resets counter */ 501 #define SHRTIMER_STXCNTRST_MTCMP3RST BIT(8) /*!< Master_TIMER compare 3 event resets counter */ 502 #define SHRTIMER_STXCNTRST_EXEV0RST BIT(9) /*!< external event 0 resets counter */ 503 #define SHRTIMER_STXCNTRST_EXEV1RST BIT(10) /*!< external event 1 resets counter */ 504 #define SHRTIMER_STXCNTRST_EXEV2RST BIT(11) /*!< external event 2 resets counter */ 505 #define SHRTIMER_STXCNTRST_EXEV3RST BIT(12) /*!< external event 3 resets counter */ 506 #define SHRTIMER_STXCNTRST_EXEV4RST BIT(13) /*!< external event 4 resets counter */ 507 #define SHRTIMER_STXCNTRST_EXEV5RST BIT(14) /*!< external event 5 resets counter */ 508 #define SHRTIMER_STXCNTRST_EXEV6RST BIT(15) /*!< external event 6 resets counter */ 509 #define SHRTIMER_STXCNTRST_EXEV7RST BIT(16) /*!< external event 7 resets counter */ 510 #define SHRTIMER_STXCNTRST_EXEV8RST BIT(17) /*!< external event 8 resets counter */ 511 #define SHRTIMER_STXCNTRST_EXEV9RST BIT(18) /*!< external event 9 resets counter */ 512 /* For Slave_TIMER0 */ 513 #define SHRTIMER_ST0CNTRST_ST1CMP0RST BIT(19) /*!< Slave_TIMER1 compare 0 event resets counter */ 514 #define SHRTIMER_ST0CNTRST_ST1CMP1RST BIT(20) /*!< Slave_TIMER1 compare 1 event resets counter */ 515 #define SHRTIMER_ST0CNTRST_ST1CMP3RST BIT(21) /*!< Slave_TIMER1 compare 3 event resets counter */ 516 #define SHRTIMER_ST0CNTRST_ST2CMP0RST BIT(22) /*!< Slave_TIMER2 compare 0 event resets counter */ 517 #define SHRTIMER_ST0CNTRST_ST2CMP1RST BIT(23) /*!< Slave_TIMER2 compare 1 event resets counter */ 518 #define SHRTIMER_ST0CNTRST_ST2CMP3RST BIT(24) /*!< Slave_TIMER2 compare 3 event resets counter */ 519 #define SHRTIMER_ST0CNTRST_ST3CMP0RST BIT(25) /*!< Slave_TIMER3 compare 0 event resets counter */ 520 #define SHRTIMER_ST0CNTRST_ST3CMP1RST BIT(26) /*!< Slave_TIMER3 compare 1 event resets counter */ 521 #define SHRTIMER_ST0CNTRST_ST3CMP3RST BIT(27) /*!< Slave_TIMER3 compare 3 event resets counter */ 522 #define SHRTIMER_ST0CNTRST_ST4CMP0RST BIT(28) /*!< Slave_TIMER4 compare 0 event resets counter */ 523 #define SHRTIMER_ST0CNTRST_ST4CMP1RST BIT(29) /*!< Slave_TIMER4 compare 1 event resets counter */ 524 #define SHRTIMER_ST0CNTRST_ST4CMP3RST BIT(30) /*!< Slave_TIMER4 compare 3 event resets counter */ 525 /* For Slave_TIMER1 */ 526 #define SHRTIMER_ST1CNTRST_ST0CMP0RST BIT(19) /*!< Slave_TIMER0 compare 0 event resets counter */ 527 #define SHRTIMER_ST1CNTRST_ST0CMP1RST BIT(20) /*!< Slave_TIMER0 compare 1 event resets counter */ 528 #define SHRTIMER_ST1CNTRST_ST0CMP3RST BIT(21) /*!< Slave_TIMER0 compare 3 event resets counter */ 529 #define SHRTIMER_ST1CNTRST_ST2CMP0RST BIT(22) /*!< Slave_TIMER2 compare 0 event resets counter */ 530 #define SHRTIMER_ST1CNTRST_ST2CMP1RST BIT(23) /*!< Slave_TIMER2 compare 1 event resets counter */ 531 #define SHRTIMER_ST1CNTRST_ST2CMP3RST BIT(24) /*!< Slave_TIMER2 compare 3 event resets counter */ 532 #define SHRTIMER_ST1CNTRST_ST3CMP0RST BIT(25) /*!< Slave_TIMER3 compare 0 event resets counter */ 533 #define SHRTIMER_ST1CNTRST_ST3CMP1RST BIT(26) /*!< Slave_TIMER3 compare 1 event resets counter */ 534 #define SHRTIMER_ST1CNTRST_ST3CMP3RST BIT(27) /*!< Slave_TIMER3 compare 3 event resets counter */ 535 #define SHRTIMER_ST1CNTRST_ST4CMP0RST BIT(28) /*!< Slave_TIMER4 compare 0 event resets counter */ 536 #define SHRTIMER_ST1CNTRST_ST4CMP1RST BIT(29) /*!< Slave_TIMER4 compare 1 event resets counter */ 537 #define SHRTIMER_ST1CNTRST_ST4CMP3RST BIT(30) /*!< Slave_TIMER4 compare 3 event resets counter */ 538 /* For Slave_TIMER2 */ 539 #define SHRTIMER_ST2CNTRST_ST0CMP0RST BIT(19) /*!< Slave_TIMER0 compare 0 event resets counter */ 540 #define SHRTIMER_ST2CNTRST_ST0CMP1RST BIT(20) /*!< Slave_TIMER0 compare 1 event resets counter */ 541 #define SHRTIMER_ST2CNTRST_ST0CMP3RST BIT(21) /*!< Slave_TIMER0 compare 3 event resets counter */ 542 #define SHRTIMER_ST2CNTRST_ST1CMP0RST BIT(22) /*!< Slave_TIMER1 compare 0 event resets counter */ 543 #define SHRTIMER_ST2CNTRST_ST1CMP1RST BIT(23) /*!< Slave_TIMER1 compare 1 event resets counter */ 544 #define SHRTIMER_ST2CNTRST_ST1CMP3RST BIT(24) /*!< Slave_TIMER1 compare 3 event resets counter */ 545 #define SHRTIMER_ST2CNTRST_ST3CMP0RST BIT(25) /*!< Slave_TIMER3 compare 0 event resets counter */ 546 #define SHRTIMER_ST2CNTRST_ST3CMP1RST BIT(26) /*!< Slave_TIMER3 compare 1 event resets counter */ 547 #define SHRTIMER_ST2CNTRST_ST3CMP3RST BIT(27) /*!< Slave_TIMER3 compare 3 event resets counter */ 548 #define SHRTIMER_ST2CNTRST_ST4CMP0RST BIT(28) /*!< Slave_TIMER4 compare 0 event resets counter */ 549 #define SHRTIMER_ST2CNTRST_ST4CMP1RST BIT(29) /*!< Slave_TIMER4 compare 1 event resets counter */ 550 #define SHRTIMER_ST2CNTRST_ST4CMP3RST BIT(30) /*!< Slave_TIMER4 compare 3 event resets counter */ 551 /* For Slave_TIMER3 */ 552 #define SHRTIMER_ST3CNTRST_ST0CMP0RST BIT(19) /*!< Slave_TIMER0 compare 0 event resets counter */ 553 #define SHRTIMER_ST3CNTRST_ST0CMP1RST BIT(20) /*!< Slave_TIMER0 compare 1 event resets counter */ 554 #define SHRTIMER_ST3CNTRST_ST0CMP3RST BIT(21) /*!< Slave_TIMER0 compare 3 event resets counter */ 555 #define SHRTIMER_ST3CNTRST_ST1CMP0RST BIT(22) /*!< Slave_TIMER1 compare 0 event resets counter */ 556 #define SHRTIMER_ST3CNTRST_ST1CMP1RST BIT(23) /*!< Slave_TIMER1 compare 1 event resets counter */ 557 #define SHRTIMER_ST3CNTRST_ST1CMP3RST BIT(24) /*!< Slave_TIMER1 compare 3 event resets counter */ 558 #define SHRTIMER_ST3CNTRST_ST2CMP0RST BIT(25) /*!< Slave_TIMER2 compare 0 event resets counter */ 559 #define SHRTIMER_ST3CNTRST_ST2CMP1RST BIT(26) /*!< Slave_TIMER2 compare 1 event resets counter */ 560 #define SHRTIMER_ST3CNTRST_ST2CMP3RST BIT(27) /*!< Slave_TIMER2 compare 3 event resets counter */ 561 #define SHRTIMER_ST3CNTRST_ST4CMP0RST BIT(28) /*!< Slave_TIMER4 compare 0 event resets counter */ 562 #define SHRTIMER_ST3CNTRST_ST4CMP1RST BIT(29) /*!< Slave_TIMER4 compare 1 event resets counter */ 563 #define SHRTIMER_ST3CNTRST_ST4CMP3RST BIT(30) /*!< Slave_TIMER4 compare 3 event resets counter */ 564 /* For Slave_TIMER4 */ 565 #define SHRTIMER_ST4CNTRST_ST0CMP0RST BIT(19) /*!< Slave_TIMER0 compare 0 event resets counter */ 566 #define SHRTIMER_ST4CNTRST_ST0CMP1RST BIT(20) /*!< Slave_TIMER0 compare 1 event resets counter */ 567 #define SHRTIMER_ST4CNTRST_ST0CMP3RST BIT(21) /*!< Slave_TIMER0 compare 3 event resets counter */ 568 #define SHRTIMER_ST4CNTRST_ST1CMP0RST BIT(22) /*!< Slave_TIMER1 compare 0 event resets counter */ 569 #define SHRTIMER_ST4CNTRST_ST1CMP1RST BIT(23) /*!< Slave_TIMER1 compare 1 event resets counter */ 570 #define SHRTIMER_ST4CNTRST_ST1CMP3RST BIT(24) /*!< Slave_TIMER1 compare 3 event resets counter */ 571 #define SHRTIMER_ST4CNTRST_ST2CMP0RST BIT(25) /*!< Slave_TIMER2 compare 0 event resets counter */ 572 #define SHRTIMER_ST4CNTRST_ST2CMP1RST BIT(26) /*!< Slave_TIMER2 compare 1 event resets counter */ 573 #define SHRTIMER_ST4CNTRST_ST2CMP3RST BIT(27) /*!< Slave_TIMER2 compare 3 event resets counter */ 574 #define SHRTIMER_ST4CNTRST_ST3CMP0RST BIT(28) /*!< Slave_TIMER3 compare 0 event resets counter */ 575 #define SHRTIMER_ST4CNTRST_ST3CMP1RST BIT(29) /*!< Slave_TIMER3 compare 1 event resets counter */ 576 #define SHRTIMER_ST4CNTRST_ST3CMP3RST BIT(30) /*!< Slave_TIMER3 compare 3 event resets counter */ 577 578 /* SHRTIMER_STxCSCTL */ 579 #define SHRTIMER_STXCSCTL_CSPRD BITS(0,3) /*!< carrier signal period */ 580 #define SHRTIMER_STXCSCTL_CSDTY BITS(4,6) /*!< carrier signal duty cycle */ 581 #define SHRTIMER_STXCSCTL_CSFSTPW BITS(7,10) /*!< first carrier-signal pulse width */ 582 583 /* SHRTIMER_STxCAP0TRG */ 584 #define SHRTIMER_STXCAP0TRG_CP0BSW BIT(0) /*!< capture 0 triggered by software */ 585 #define SHRTIMER_STXCAP0TRG_CP0BUP BIT(1) /*!< capture 0 triggered by update event */ 586 #define SHRTIMER_STXCAP0TRG_CP0BEXEV0 BIT(2) /*!< capture 0 triggered by external event 0 */ 587 #define SHRTIMER_STXCAP0TRG_CP0BEXEV1 BIT(3) /*!< capture 0 triggered by external event 1 */ 588 #define SHRTIMER_STXCAP0TRG_CP0BEXEV2 BIT(4) /*!< capture 0 triggered by external event 2 */ 589 #define SHRTIMER_STXCAP0TRG_CP0BEXEV3 BIT(5) /*!< capture 0 triggered by external event 3 */ 590 #define SHRTIMER_STXCAP0TRG_CP0BEXEV4 BIT(6) /*!< capture 0 triggered by external event 4 */ 591 #define SHRTIMER_STXCAP0TRG_CP0BEXEV5 BIT(7) /*!< capture 0 triggered by external event 5 */ 592 #define SHRTIMER_STXCAP0TRG_CP0BEXEV6 BIT(8) /*!< capture 0 triggered by external event 6 */ 593 #define SHRTIMER_STXCAP0TRG_CP0BEXEV7 BIT(9) /*!< capture 0 triggered by external event 7 */ 594 #define SHRTIMER_STXCAP0TRG_CP0BEXEV8 BIT(10) /*!< capture 0 triggered by external event 8 */ 595 #define SHRTIMER_STXCAP0TRG_CP0BEXEV9 BIT(11) /*!< capture 0 triggered by external event 9 */ 596 #define SHRTIMER_STXCAP0TRG_CP0BST0A BIT(12) /*!< capture 0 triggered by ST0CH0_O output inactive to active transition */ 597 #define SHRTIMER_STXCAP0TRG_CP0BST0NA BIT(13) /*!< capture 0 triggered by ST0CH0_O output active to inactive transition */ 598 #define SHRTIMER_STXCAP0TRG_CP0BST0CMP0 BIT(14) /*!< capture 0 triggered by compare 0 event of Slave_TIMER0 */ 599 #define SHRTIMER_STXCAP0TRG_CP0BST0CMP1 BIT(15) /*!< capture 0 triggered by compare 1 event of Slave_TIMER0 */ 600 #define SHRTIMER_STXCAP0TRG_CP0BST1A BIT(16) /*!< capture 0 triggered by ST1CH0_O output inactive to active transition */ 601 #define SHRTIMER_STXCAP0TRG_CP0BST1NA BIT(17) /*!< capture 0 triggered by ST1CH0_O output active to inactive transition */ 602 #define SHRTIMER_STXCAP0TRG_CP0BST1CMP0 BIT(18) /*!< capture 0 triggered by compare 0 event of Slave_TIMER1 */ 603 #define SHRTIMER_STXCAP0TRG_CP0BST1CMP1 BIT(19) /*!< capture 0 triggered by compare 1 event of Slave_TIMER1 */ 604 #define SHRTIMER_STXCAP0TRG_CP0BST2A BIT(20) /*!< capture 0 triggered by ST2CH0_O output inactive to active transition */ 605 #define SHRTIMER_STXCAP0TRG_CP0BST2NA BIT(21) /*!< capture 0 triggered by ST2CH0_O output active to inactive transition */ 606 #define SHRTIMER_STXCAP0TRG_CP0BST2CMP0 BIT(22) /*!< capture 0 triggered by compare 0 event of Slave_TIMER2 */ 607 #define SHRTIMER_STXCAP0TRG_CP0BST2CMP1 BIT(23) /*!< capture 0 triggered by compare 1 event of Slave_TIMER2 */ 608 #define SHRTIMER_STXCAP0TRG_CP0BST3A BIT(24) /*!< capture 0 triggered by ST3CH0_O output inactive to active transition */ 609 #define SHRTIMER_STXCAP0TRG_CP0BST3NA BIT(25) /*!< capture 0 triggered by ST3CH0_O output active to inactive transition */ 610 #define SHRTIMER_STXCAP0TRG_CP0BST3CMP0 BIT(26) /*!< capture 0 triggered by compare 0 event of Slave_TIMER3 */ 611 #define SHRTIMER_STXCAP0TRG_CP0BST3CMP1 BIT(27) /*!< capture 0 triggered by compare 1 event of Slave_TIMER3 */ 612 #define SHRTIMER_STXCAP0TRG_CP0BST4A BIT(28) /*!< capture 0 triggered by ST4CH0_O output inactive to active transition */ 613 #define SHRTIMER_STXCAP0TRG_CP0BST4NA BIT(29) /*!< capture 0 triggered by ST4CH0_O output active to inactive transition. */ 614 #define SHRTIMER_STXCAP0TRG_CP0BST4CMP0 BIT(30) /*!< capture 0 triggered by compare 0 event of Slave_TIMER4 */ 615 #define SHRTIMER_STXCAP0TRG_CP0BST4CMP1 BIT(31) /*!< capture 0 triggered by compare 1 event of Slave_TIMER4 */ 616 617 /* SHRTIMER_STxCAP1TRG */ 618 #define SHRTIMER_STXCAP1TRG_CP1BSW BIT(0) /*!< capture 1 triggered by software */ 619 #define SHRTIMER_STXCAP1TRG_CP1BUP BIT(1) /*!< capture 1 triggered by update event */ 620 #define SHRTIMER_STXCAP1TRG_CP1BEXEV0 BIT(2) /*!< capture 1 triggered by external event 0 */ 621 #define SHRTIMER_STXCAP1TRG_CP1BEXEV1 BIT(3) /*!< capture 1 triggered by external event 1 */ 622 #define SHRTIMER_STXCAP1TRG_CP1BEXEV2 BIT(4) /*!< capture 1 triggered by external event 2 */ 623 #define SHRTIMER_STXCAP1TRG_CP1BEXEV3 BIT(5) /*!< capture 1 triggered by external event 3 */ 624 #define SHRTIMER_STXCAP1TRG_CP1BEXEV4 BIT(6) /*!< capture 1 triggered by external event 4 */ 625 #define SHRTIMER_STXCAP1TRG_CP1BEXEV5 BIT(7) /*!< capture 1 triggered by external event 5 */ 626 #define SHRTIMER_STXCAP1TRG_CP1BEXEV6 BIT(8) /*!< capture 1 triggered by external event 6 */ 627 #define SHRTIMER_STXCAP1TRG_CP1BEXEV7 BIT(9) /*!< capture 1 triggered by external event 7 */ 628 #define SHRTIMER_STXCAP1TRG_CP1BEXEV8 BIT(10) /*!< capture 1 triggered by external event 8 */ 629 #define SHRTIMER_STXCAP1TRG_CP1BEXEV9 BIT(11) /*!< capture 1 triggered by external event 9 */ 630 #define SHRTIMER_STXCAP1TRG_CP1BST0A BIT(12) /*!< capture 1 triggered by ST0CH0_O output inactive to active transition */ 631 #define SHRTIMER_STXCAP1TRG_CP1BST0NA BIT(13) /*!< capture 1 triggered by ST0CH0_O output active to inactive transition */ 632 #define SHRTIMER_STXCAP1TRG_CP1BST0CMP0 BIT(14) /*!< capture 1 triggered by compare 0 event of Slave_TIMER0 */ 633 #define SHRTIMER_STXCAP1TRG_CP1BST0CMP1 BIT(15) /*!< capture 1 triggered by compare 1 event of Slave_TIMER0 */ 634 #define SHRTIMER_STXCAP1TRG_CP1BST1A BIT(16) /*!< capture 1 triggered by ST1CH0_O output inactive to active transition */ 635 #define SHRTIMER_STXCAP1TRG_CP1BST1NA BIT(17) /*!< capture 1 triggered by ST1CH0_O output active to inactive transition */ 636 #define SHRTIMER_STXCAP1TRG_CP1BST1CMP0 BIT(18) /*!< capture 1 triggered by compare 0 event of Slave_TIMER1 */ 637 #define SHRTIMER_STXCAP1TRG_CP1BST1CMP1 BIT(19) /*!< capture 1 triggered by compare 1 event of Slave_TIMER1 */ 638 #define SHRTIMER_STXCAP1TRG_CP1BST2A BIT(20) /*!< capture 1 triggered by ST2CH0_O output inactive to active transition */ 639 #define SHRTIMER_STXCAP1TRG_CP1BST2NA BIT(21) /*!< capture 1 triggered by ST2CH0_O output active to inactive transition */ 640 #define SHRTIMER_STXCAP1TRG_CP1BST2CMP0 BIT(22) /*!< capture 1 triggered by compare 0 event of Slave_TIMER2 */ 641 #define SHRTIMER_STXCAP1TRG_CP1BST2CMP1 BIT(23) /*!< capture 1 triggered by compare 1 event of Slave_TIMER2 */ 642 #define SHRTIMER_STXCAP1TRG_CP1BST3A BIT(24) /*!< capture 1 triggered by ST3CH0_O output inactive to active transition */ 643 #define SHRTIMER_STXCAP1TRG_CP1BST3NA BIT(25) /*!< capture 1 triggered by ST3CH0_O output active to inactive transition */ 644 #define SHRTIMER_STXCAP1TRG_CP1BST3CMP0 BIT(26) /*!< capture 1 triggered by compare 0 event of Slave_TIMER3 */ 645 #define SHRTIMER_STXCAP1TRG_CP1BST3CMP1 BIT(27) /*!< capture 1 triggered by compare 1 event of Slave_TIMER3 */ 646 #define SHRTIMER_STXCAP1TRG_CP1BST4A BIT(28) /*!< capture 1 triggered by ST4CH0_O output inactive to active transition */ 647 #define SHRTIMER_STXCAP1TRG_CP1BST4NA BIT(29) /*!< capture 1 triggered by ST4CH0_O output active to inactive transition. */ 648 #define SHRTIMER_STXCAP1TRG_CP1BST4CMP0 BIT(30) /*!< capture 1 triggered by compare 0 event of Slave_TIMER4 */ 649 #define SHRTIMER_STXCAP1TRG_CP1BST4CMP1 BIT(31) /*!< capture 1 triggered by compare 1 event of Slave_TIMER4 */ 650 651 /* SHRTIMER_STxCHOCTL */ 652 #define SHRTIMER_STXCHOCTL_CH0P BIT(1) /*!< channel 0 output polarity */ 653 #define SHRTIMER_STXCHOCTL_BMCH0IEN BIT(2) /*!< channel 0 IDLE state enable in bunch mode */ 654 #define SHRTIMER_STXCHOCTL_ISO0 BIT(3) /*!< channel 0 output idle state */ 655 #define SHRTIMER_STXCHOCTL_CH0FLTOS BITS(4,5) /*!< channel 0 fault output state */ 656 #define SHRTIMER_STXCHOCTL_CH0CSEN BIT(6) /*!< channel 0 carrier-signal mode enable */ 657 #define SHRTIMER_STXCHOCTL_BMCH0DTI BIT(7) /*!< channel 0 dead-time insert in bunch mode */ 658 #define SHRTIMER_STXCHOCTL_DTEN BIT(8) /*!< dead time enable */ 659 #define SHRTIMER_STXCHOCTL_DLYISMEN BIT(9) /*!< delayed IDLE state mode enable */ 660 #define SHRTIMER_STXCHOCTL_DLYISCH BITS(10,12) /*!< delayed IDLE source and channel */ 661 #define SHRTIMER_STXCHOCTL_CH1P BIT(17) /*!< channel 1 output polarity */ 662 #define SHRTIMER_STXCHOCTL_BMCH1IEN BIT(18) /*!< channel 1 IDLE state enable in bunch mode */ 663 #define SHRTIMER_STXCHOCTL_ISO1 BIT(19) /*!< channel 1 output idle state */ 664 #define SHRTIMER_STXCHOCTL_CH1FLTOS BITS(20,21) /*!< channel 1 fault output state */ 665 #define SHRTIMER_STXCHOCTL_CH1CSEN BIT(22) /*!< channel 1 carrier-signal mode enable */ 666 #define SHRTIMER_STXCHOCTL_BMCH1DTI BIT(23) /*!< channel 1 dead-time insert in bunch mode */ 667 668 /* SHRTIMER_STxFLTCTL */ 669 #define SHRTIMER_STXFLTCTL_FLT0EN BIT(0) /*!< fault 0 enable */ 670 #define SHRTIMER_STXFLTCTL_FLT1EN BIT(1) /*!< fault 1 enable */ 671 #define SHRTIMER_STXFLTCTL_FLT2EN BIT(2) /*!< fault 2 enable */ 672 #define SHRTIMER_STXFLTCTL_FLT3EN BIT(3) /*!< fault 3 enable */ 673 #define SHRTIMER_STXFLTCTL_FLT4EN BIT(4) /*!< fault 4 enable */ 674 #define SHRTIMER_STXFLTCTL_FLTENPROT BIT(31) /*!< protect fault enable */ 675 676 /* SHRTIMER_STxACTL */ 677 #define SHRTIMER_STXACTL_CNTCKDIV3 BIT(3) /*!< counter clock division */ 678 #define SHRTIMER_STXACTL_DTRCFG15_9 BITS(9,15) /*!< rising edge dead-time value configure */ 679 #define SHRTIMER_STXACTL_DTFCFG15_9 BITS(25,31) /*!< falling edge dead-time value configure */ 680 681 /* Common registers */ 682 /* SHRTIMER_CTL0 */ 683 #define SHRTIMER_CTL0_MTUPDIS BIT(0) /*!< Master_TIMER update disable */ 684 #define SHRTIMER_CTL0_ST0UPDIS BIT(1) /*!< Slave_TIMER0 update disable */ 685 #define SHRTIMER_CTL0_ST1UPDIS BIT(2) /*!< Slave_TIMER1 update disable */ 686 #define SHRTIMER_CTL0_ST2UPDIS BIT(3) /*!< Slave_TIMER2 update disable */ 687 #define SHRTIMER_CTL0_ST3UPDIS BIT(4) /*!< Slave_TIMER3 update disable */ 688 #define SHRTIMER_CTL0_ST4UPDIS BIT(5) /*!< Slave_TIMER4 update disable */ 689 #define SHRTIMER_CTL0_ADTG0USRC BITS(16,18) /*!< SHRTIMER_ADCTRIG0 update source */ 690 #define SHRTIMER_CTL0_ADTG1USRC BITS(19,21) /*!< SHRTIMER_ADCTRIG1 update source */ 691 #define SHRTIMER_CTL0_ADTG2USRC BITS(22,24) /*!< SHRTIMER_ADCTRIG2 update source */ 692 #define SHRTIMER_CTL0_ADTG3USRC BITS(25,27) /*!< SHRTIMER_ADCTRIG3 update source */ 693 694 /* SHRTIMER_CTL1 */ 695 #define SHRTIMER_CTL1_MTSUP BIT(0) /*!< Master_TIMER software update */ 696 #define SHRTIMER_CTL1_ST0SUP BIT(1) /*!< Slave_TIMER0 software update */ 697 #define SHRTIMER_CTL1_ST1SUP BIT(2) /*!< Slave_TIMER1 software update */ 698 #define SHRTIMER_CTL1_ST2SUP BIT(3) /*!< Slave_TIMER2 software update */ 699 #define SHRTIMER_CTL1_ST3SUP BIT(4) /*!< Slave_TIMER3 software update */ 700 #define SHRTIMER_CTL1_ST4SUP BIT(5) /*!< Slave_TIMER4 software update */ 701 #define SHRTIMER_CTL1_MTSRST BIT(8) /*!< Master_TIMER software reset */ 702 #define SHRTIMER_CTL1_ST0SRST BIT(9) /*!< Slave_TIMER0 software reset */ 703 #define SHRTIMER_CTL1_ST1SRST BIT(10) /*!< Slave_TIMER1 software reset */ 704 #define SHRTIMER_CTL1_ST2SRST BIT(11) /*!< Slave_TIMER2 software reset */ 705 #define SHRTIMER_CTL1_ST3SRST BIT(12) /*!< Slave_TIMER3 software reset */ 706 #define SHRTIMER_CTL1_ST4SRST BIT(13) /*!< Slave_TIMER4 software reset */ 707 708 /* SHRTIMER_INTF */ 709 #define SHRTIMER_INTF_FLT0IF BIT(0) /*!< fault 0 interrupt flag */ 710 #define SHRTIMER_INTF_FLT1IF BIT(1) /*!< fault 1 interrupt flag */ 711 #define SHRTIMER_INTF_FLT2IF BIT(2) /*!< fault 2 interrupt flag */ 712 #define SHRTIMER_INTF_FLT3IF BIT(3) /*!< fault 3 interrupt flag */ 713 #define SHRTIMER_INTF_FLT4IF BIT(4) /*!< fault 4 interrupt flag */ 714 #define SHRTIMER_INTF_SYSFLTIF BIT(5) /*!< system fault interrupt flag */ 715 #define SHRTIMER_INTF_DLLCALIF BIT(16) /*!< DLL calibration completed interrupt flag */ 716 #define SHRTIMER_INTF_BMPERIF BIT(17) /*!< bunch mode period interrupt flag */ 717 718 /* SHRTIMER_INTC */ 719 #define SHRTIMER_INTC_FLT0IFC BIT(0) /*!< clear fault 0 interrupt flag */ 720 #define SHRTIMER_INTC_FLT1IFC BIT(1) /*!< clear fault 1 interrupt flag */ 721 #define SHRTIMER_INTC_FLT2IFC BIT(2) /*!< clear fault 2 interrupt flag */ 722 #define SHRTIMER_INTC_FLT3IFC BIT(3) /*!< clear fault 3 interrupt flag */ 723 #define SHRTIMER_INTC_FLT4IFC BIT(4) /*!< clear fault 4 interrupt flag */ 724 #define SHRTIMER_INTC_SYSFLTIFC BIT(5) /*!< clear system fault interrupt flag */ 725 #define SHRTIMER_INTC_DLLCALIFC BIT(16) /*!< clear DLL calibration completed interrupt flag */ 726 #define SHRTIMER_INTC_BMPERIFC BIT(17) /*!< clear bunch mode period interrupt flag */ 727 728 /* SHRTIMER_INTEN */ 729 #define SHRTIMER_INTEN_FLT0IE BIT(0) /*!< fault 0 interrupt enable */ 730 #define SHRTIMER_INTEN_FLT1IE BIT(1) /*!< fault 1 interrupt enable */ 731 #define SHRTIMER_INTEN_FLT2IE BIT(2) /*!< fault 2 interrupt enable */ 732 #define SHRTIMER_INTEN_FLT3IE BIT(3) /*!< fault 3 interrupt enable */ 733 #define SHRTIMER_INTEN_FLT4IE BIT(4) /*!< fault 4 interrupt enable */ 734 #define SHRTIMER_INTEN_SYSFLTIE BIT(5) /*!< system fault interrupt enable */ 735 #define SHRTIMER_INTEN_DLLCALIE BIT(16) /*!< DLL calibration completed interrupt enable */ 736 #define SHRTIMER_INTEN_BMPERIE BIT(17) /*!< bunch mode period interrupt enable */ 737 738 /* SHRTIMER_CHOUTEN */ 739 #define SHRTIMER_CHOUTEN_ST0CH0EN BIT(0) /*!< Slave_TIMER0 channel 0 output (ST0CH0_O) enable */ 740 #define SHRTIMER_CHOUTEN_ST0CH1EN BIT(1) /*!< Slave_TIMER0 channel 1 output (ST0CH1_O) enable */ 741 #define SHRTIMER_CHOUTEN_ST1CH0EN BIT(2) /*!< Slave_TIMER1 channel 0 output (ST1CH0_O) enable */ 742 #define SHRTIMER_CHOUTEN_ST1CH1EN BIT(3) /*!< Slave_TIMER1 channel 1 output (ST1CH1_O) enable */ 743 #define SHRTIMER_CHOUTEN_ST2CH0EN BIT(4) /*!< Slave_TIMER2 channel 0 output (ST2CH0_O) enable */ 744 #define SHRTIMER_CHOUTEN_ST2CH1EN BIT(5) /*!< Slave_TIMER2 channel 1 output (ST2CH1_O) enable */ 745 #define SHRTIMER_CHOUTEN_ST3CH0EN BIT(6) /*!< Slave_TIMER3 channel 0 output (ST3CH0_O) enable */ 746 #define SHRTIMER_CHOUTEN_ST3CH1EN BIT(7) /*!< Slave_TIMER3 channel 1 output (ST3CH1_O) enable */ 747 #define SHRTIMER_CHOUTEN_ST4CH0EN BIT(8) /*!< Slave_TIMER4 channel 0 output (ST4CH0_O) enable */ 748 #define SHRTIMER_CHOUTEN_ST4CH1EN BIT(9) /*!< Slave_TIMER4 channel 1 output (ST4CH1_O) enable */ 749 750 /* SHRTIMER_CHOUTDIS */ 751 #define SHRTIMER_CHOUTDIS_ST0CH0DIS BIT(0) /*!< Slave_TIMER0 channel 0 output (ST0CH0_O) disable */ 752 #define SHRTIMER_CHOUTDIS_ST0CH1DIS BIT(1) /*!< Slave_TIMER0 channel 1 output (ST0CH1_O) disable */ 753 #define SHRTIMER_CHOUTDIS_ST1CH0DIS BIT(2) /*!< Slave_TIMER1 channel 0 output (ST1CH0_O) disable */ 754 #define SHRTIMER_CHOUTDIS_ST1CH1DIS BIT(3) /*!< Slave_TIMER1 channel 1 output (ST1CH1_O) disable */ 755 #define SHRTIMER_CHOUTDIS_ST2CH0DIS BIT(4) /*!< Slave_TIMER2 channel 0 output (ST2CH0_O) disable */ 756 #define SHRTIMER_CHOUTDIS_ST2CH1DIS BIT(5) /*!< Slave_TIMER2 channel 1 output (ST2CH1_O) disable */ 757 #define SHRTIMER_CHOUTDIS_ST3CH0DIS BIT(6) /*!< Slave_TIMER3 channel 0 output (ST3CH0_O) disable */ 758 #define SHRTIMER_CHOUTDIS_ST3CH1DIS BIT(7) /*!< Slave_TIMER3 channel 1 output (ST3CH1_O) disable */ 759 #define SHRTIMER_CHOUTDIS_ST4CH0DIS BIT(8) /*!< Slave_TIMER4 channel 0 output (ST4CH0_O) disable */ 760 #define SHRTIMER_CHOUTDIS_ST4CH1DIS BIT(9) /*!< Slave_TIMER4 channel 1 output (ST4CH1_O) disable */ 761 762 /* SHRTIMER_CHOUTDISF */ 763 #define SHRTIMER_CHOUTDISF_ST0CH0DISF BIT(0) /*!< Slave_TIMER0 channel 0 output (ST0CH0_O) disable flag */ 764 #define SHRTIMER_CHOUTDISF_ST0CH1DISF BIT(1) /*!< Slave_TIMER0 channel 1 output (ST0CH1_O) disable flag */ 765 #define SHRTIMER_CHOUTDISF_ST1CH0DISF BIT(2) /*!< Slave_TIMER1 channel 0 output (ST1CH0_O) disable flag */ 766 #define SHRTIMER_CHOUTDISF_ST1CH1DISF BIT(3) /*!< Slave_TIMER1 channel 1 output (ST1CH1_O) disable flag */ 767 #define SHRTIMER_CHOUTDISF_ST2CH0DISF BIT(4) /*!< Slave_TIMER2 channel 0 output (ST2CH0_O) disable flag */ 768 #define SHRTIMER_CHOUTDISF_ST2CH1DISF BIT(5) /*!< Slave_TIMER2 channel 1 output (ST2CH1_O) disable flag */ 769 #define SHRTIMER_CHOUTDISF_ST3CH0DISF BIT(6) /*!< Slave_TIMER3 channel 0 output (ST3CH0_O) disable flag */ 770 #define SHRTIMER_CHOUTDISF_ST3CH1DISF BIT(7) /*!< Slave_TIMER3 channel 1 output (ST3CH1_O) disable flag */ 771 #define SHRTIMER_CHOUTDISF_ST4CH0DISF BIT(8) /*!< Slave_TIMER4 channel 0 output (ST4CH0_O) disable flag */ 772 #define SHRTIMER_CHOUTDISF_ST4CH1DISF BIT(9) /*!< Slave_TIMER4 channel 1 output (ST4CH1_O) disable flag */ 773 774 /* SHRTIMER_BMCTL */ 775 #define SHRTIMER_BMCTL_BMEN BIT(0) /*!< bunch mode enable */ 776 #define SHRTIMER_BMCTL_BMCTN BIT(1) /*!< continuous mode in bunch mode */ 777 #define SHRTIMER_BMCTL_BMCLKS BITS(2,5) /*!< bunch mode clock source */ 778 #define SHRTIMER_BMCTL_BMPSC BITS(6,9) /*!< bunch mode clock division */ 779 #define SHRTIMER_BMCTL_BMSE BIT(10) /*!< bunch mode shadow enable */ 780 #define SHRTIMER_BMCTL_BMMT BIT(16) /*!< Master_TIMER bunch mode */ 781 #define SHRTIMER_BMCTL_BMST0 BIT(17) /*!< Slave_TIMER0 bunch mode */ 782 #define SHRTIMER_BMCTL_BMST1 BIT(18) /*!< Slave_TIMER1 bunch mode */ 783 #define SHRTIMER_BMCTL_BMST2 BIT(19) /*!< Slave_TIMER2 bunch mode */ 784 #define SHRTIMER_BMCTL_BMST3 BIT(20) /*!< Slave_TIMER3 bunch mode */ 785 #define SHRTIMER_BMCTL_BMST4 BIT(21) /*!< Slave_TIMER4 bunch mode */ 786 #define SHRTIMER_BMCTL_BMOPTF BIT(31) /*!< bunch mode operating flag */ 787 788 /* SHRTIMER_BMSTRG */ 789 #define SHRTIMER_BMSTRG_SWTRG BIT(0) /*!< software triggers bunch mode operation */ 790 #define SHRTIMER_BMSTRG_MTRST BIT(1) /*!< Master_TIMER reset event triggers bunch mode operation */ 791 #define SHRTIMER_BMSTRG_MTREP BIT(2) /*!< Master_TIMER repetition event triggers bunch mode operation */ 792 #define SHRTIMER_BMSTRG_MTCMP0 BIT(3) /*!< Master_TIMER compare 0 event triggers bunch mode operation */ 793 #define SHRTIMER_BMSTRG_MTCMP1 BIT(4) /*!< Master_TIMER compare 1 event triggers bunch mode operation */ 794 #define SHRTIMER_BMSTRG_MTCMP2 BIT(5) /*!< Master_TIMER compare 2 event triggers bunch mode operation */ 795 #define SHRTIMER_BMSTRG_MTCMP3 BIT(6) /*!< Master_TIMER compare 3 event triggers bunch mode operation */ 796 #define SHRTIMER_BMSTRG_ST0RST BIT(7) /*!< Slave_TIMER0 reset event triggers bunch mode operation */ 797 #define SHRTIMER_BMSTRG_ST0REP BIT(8) /*!< Slave_TIMER0 repetition event triggers bunch mode operation */ 798 #define SHRTIMER_BMSTRG_ST0CMP0 BIT(9) /*!< Slave_TIMER0 compare 0 event triggers bunch mode operation */ 799 #define SHRTIMER_BMSTRG_ST0CMP1 BIT(10) /*!< Slave_TIMER0 compare 1 event triggers bunch mode operation */ 800 #define SHRTIMER_BMSTRG_ST1RST BIT(11) /*!< Slave_TIMER1 reset event triggers bunch mode operation */ 801 #define SHRTIMER_BMSTRG_ST1REP BIT(12) /*!< Slave_TIMER1 repetition event triggers bunch mode operation */ 802 #define SHRTIMER_BMSTRG_ST1CMP0 BIT(13) /*!< Slave_TIMER1 compare 0 event triggers bunch mode operation */ 803 #define SHRTIMER_BMSTRG_ST1CMP1 BIT(14) /*!< Slave_TIMER1 compare 1 event triggers bunch mode operation */ 804 #define SHRTIMER_BMSTRG_ST2RST BIT(15) /*!< Slave_TIMER2 reset event triggers bunch mode operation */ 805 #define SHRTIMER_BMSTRG_ST2REP BIT(16) /*!< Slave_TIMER2 repetition event triggers bunch mode operation */ 806 #define SHRTIMER_BMSTRG_ST2CMP0 BIT(17) /*!< Slave_TIMER2 compare 0 event triggers bunch mode operation */ 807 #define SHRTIMER_BMSTRG_ST2CMP1 BIT(18) /*!< Slave_TIMER2 compare 1 event triggers bunch mode operation */ 808 #define SHRTIMER_BMSTRG_ST3RST BIT(19) /*!< Slave_TIMER3 reset event triggers bunch mode operation */ 809 #define SHRTIMER_BMSTRG_ST3REP BIT(20) /*!< Slave_TIMER3 repetition event triggers bunch mode operation */ 810 #define SHRTIMER_BMSTRG_ST3CMP0 BIT(21) /*!< Slave_TIMER3 compare 0 event triggers bunch mode operation */ 811 #define SHRTIMER_BMSTRG_ST3CMP1 BIT(22) /*!< Slave_TIMER3 compare 1 event triggers bunch mode operation */ 812 #define SHRTIMER_BMSTRG_ST4RST BIT(23) /*!< Slave_TIMER4 reset event triggers bunch mode operation */ 813 #define SHRTIMER_BMSTRG_ST4REP BIT(24) /*!< Slave_TIMER4 repetition event triggers bunch mode operation */ 814 #define SHRTIMER_BMSTRG_ST4CMP0 BIT(25) /*!< Slave_TIMER4 compare 0 event triggers bunch mode operation */ 815 #define SHRTIMER_BMSTRG_ST4CMP1 BIT(26) /*!< Slave_TIMER4 compare 1 event triggers bunch mode operation */ 816 #define SHRTIMER_BMSTRG_ST0EXEV6 BIT(27) /*!< Slave_TIMER0 period event following external event 6 triggers bunch mode operation */ 817 #define SHRTIMER_BMSTRG_ST3EXEV7 BIT(28) /*!< Slave_TIMER3 period event following external event 7 triggers bunch mode operation */ 818 #define SHRTIMER_BMSTRG_EXEV6 BIT(29) /*!< external event 6 triggers bunch mode operation */ 819 #define SHRTIMER_BMSTRG_EXEV7 BIT(30) /*!< external event 7 triggers bunch mode operation */ 820 #define SHRTIMER_BMSTRG_CISGN BIT(31) /*!< chip internal signal triggers bunch mode operation */ 821 822 /* SHRTIMER_BMCMPV */ 823 #define SHRTIMER_BMCMPV_BMCMPVAL BITS(0,15) /*!< bunch mode compare value */ 824 825 /* SHRTIMER_BMCAR */ 826 #define SHRTIMER_BMCAR_BMCARL BITS(0,15) /*!< bunch mode counter auto reload value */ 827 828 /* SHRTIMER_EXEVCFG0 */ 829 #define SHRTIMER_EXEVCFG0_EXEV0SRC BITS(0,1) /*!< external event 0 source */ 830 #define SHRTIMER_EXEVCFG0_EXEV0P BIT(2) /*!< external event 0 polarity */ 831 #define SHRTIMER_EXEVCFG0_EXEV0EG BITS(3,4) /*!< external event 0 edge sensitivity */ 832 #define SHRTIMER_EXEVCFG0_EXEV1SRC BITS(6,7) /*!< external event 1 source */ 833 #define SHRTIMER_EXEVCFG0_EXEV1P BIT(8) /*!< external event 1 polarity */ 834 #define SHRTIMER_EXEVCFG0_EXEV1EG BITS(9,10) /*!< external event 1 edge sensitivity */ 835 #define SHRTIMER_EXEVCFG0_EXEV2SRC BITS(12,13) /*!< external event 2 source */ 836 #define SHRTIMER_EXEVCFG0_EXEV2P BIT(14) /*!< external event 2 polarity */ 837 #define SHRTIMER_EXEVCFG0_EXEV2EG BITS(15,16) /*!< external event 2 edge sensitivity */ 838 #define SHRTIMER_EXEVCFG0_EXEV3SRC BITS(18,19) /*!< external event 3 source */ 839 #define SHRTIMER_EXEVCFG0_EXEV3P BIT(20) /*!< external event 3 polarity */ 840 #define SHRTIMER_EXEVCFG0_EXEV3EG BITS(21,22) /*!< external event 3 edge sensitivity */ 841 #define SHRTIMER_EXEVCFG0_EXEV4SRC BITS(24,25) /*!< external event 4 source */ 842 #define SHRTIMER_EXEVCFG0_EXEV4P BIT(26) /*!< external event 4 polarity */ 843 #define SHRTIMER_EXEVCFG0_EXEV4EG BITS(27,28) /*!< external event 4 edge sensitivity */ 844 845 /* SHRTIMER_EXEVCFG1 */ 846 #define SHRTIMER_EXEVCFG1_EXEV5SRC BITS(0,1) /*!< external event 5 source */ 847 #define SHRTIMER_EXEVCFG1_EXEV5P BIT(2) /*!< external event 5 polarity */ 848 #define SHRTIMER_EXEVCFG1_EXEV5EG BITS(3,4) /*!< external event 5 edge sensitivity */ 849 #define SHRTIMER_EXEVCFG1_EXEV6SRC BITS(6,7) /*!< external event 6 source */ 850 #define SHRTIMER_EXEVCFG1_EXEV6P BIT(8) /*!< external event 6 polarity */ 851 #define SHRTIMER_EXEVCFG1_EXEV6EG BITS(9,10) /*!< external event 6 edge sensitivity */ 852 #define SHRTIMER_EXEVCFG1_EXEV7SRC BITS(12,13) /*!< external event 7 source */ 853 #define SHRTIMER_EXEVCFG1_EXEV7P BIT(14) /*!< external event 7 polarity */ 854 #define SHRTIMER_EXEVCFG1_EXEV7EG BITS(15,16) /*!< external event 7 edge sensitivity */ 855 #define SHRTIMER_EXEVCFG1_EXEV8SRC BITS(18,19) /*!< external event 8 source */ 856 #define SHRTIMER_EXEVCFG1_EXEV8P BIT(20) /*!< external event 8 polarity */ 857 #define SHRTIMER_EXEVCFG1_EXEV8EG BITS(21,22) /*!< external event 8 edge sensitivity */ 858 #define SHRTIMER_EXEVCFG1_EXEV9SRC BITS(24,25) /*!< external event 9 source */ 859 #define SHRTIMER_EXEVCFG1_EXEV9P BIT(26) /*!< external event 9 polarity */ 860 #define SHRTIMER_EXEVCFG1_EXEV9EG BITS(27,28) /*!< external event 9 edge sensitivity */ 861 862 /* SHRTIMER_EXEVDFCTL */ 863 #define SHRTIMER_EXEVDFCTL_EXEV5FC BITS(0,3) /*!< external event 5 filter control */ 864 #define SHRTIMER_EXEVDFCTL_EXEV6FC BITS(6,9) /*!< external event 6 filter control */ 865 #define SHRTIMER_EXEVDFCTL_EXEV7FC BITS(12,15) /*!< external event 7 filter control */ 866 #define SHRTIMER_EXEVDFCTL_EXEV8FC BITS(18,21) /*!< external event 8 filter control */ 867 #define SHRTIMER_EXEVDFCTL_EXEV9FC BITS(24,27) /*!< external event 9 filter control */ 868 #define SHRTIMER_EXEVDFCTL_EXEVFDIV BITS(30,31) /*!< external event digital filter clock division */ 869 870 /* SHRTIMER_ADCTRIGS0 */ 871 #define SHRTIMER_ADCTRIGS0_TRG0MTC0 BIT(0) /*!< SHRTIMER_ADCTRIG0 on Master_TIMER compare 0 event */ 872 #define SHRTIMER_ADCTRIGS0_TRG0MTC1 BIT(1) /*!< SHRTIMER_ADCTRIG0 on Master_TIMER compare 1 event */ 873 #define SHRTIMER_ADCTRIGS0_TRG0MTC2 BIT(2) /*!< SHRTIMER_ADCTRIG0 on Master_TIMER compare 2 event */ 874 #define SHRTIMER_ADCTRIGS0_TRG0MTC3 BIT(3) /*!< SHRTIMER_ADCTRIG0 on Master_TIMER compare 3 event */ 875 #define SHRTIMER_ADCTRIGS0_TRG0MTPER BIT(4) /*!< SHRTIMER_ADCTRIG0 on Master_TIMER period event */ 876 #define SHRTIMER_ADCTRIGS0_TRG0EXEV0 BIT(5) /*!< SHRTIMER_ADCTRIG0 on external event 0 */ 877 #define SHRTIMER_ADCTRIGS0_TRG0EXEV1 BIT(6) /*!< SHRTIMER_ADCTRIG0 on external event 1 */ 878 #define SHRTIMER_ADCTRIGS0_TRG0EXEV2 BIT(7) /*!< SHRTIMER_ADCTRIG0 on external event 2 */ 879 #define SHRTIMER_ADCTRIGS0_TRG0EXEV3 BIT(8) /*!< SHRTIMER_ADCTRIG0 on external event 3 */ 880 #define SHRTIMER_ADCTRIGS0_TRG0EXEV4 BIT(9) /*!< SHRTIMER_ADCTRIG0 on external event 4 */ 881 #define SHRTIMER_ADCTRIGS0_TRG0ST0C1 BIT(10) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 1 event */ 882 #define SHRTIMER_ADCTRIGS0_TRG0ST0C2 BIT(11) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 2 event */ 883 #define SHRTIMER_ADCTRIGS0_TRG0ST0C3 BIT(12) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 3 event */ 884 #define SHRTIMER_ADCTRIGS0_TRG0ST0PER BIT(13) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER0 period event */ 885 #define SHRTIMER_ADCTRIGS0_TRG0ST0RST BIT(14) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER0 reset and counter roll-over event */ 886 #define SHRTIMER_ADCTRIGS0_TRG0ST1C1 BIT(15) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 1 event */ 887 #define SHRTIMER_ADCTRIGS0_TRG0ST1C2 BIT(16) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 2 event */ 888 #define SHRTIMER_ADCTRIGS0_TRG0ST1C3 BIT(17) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 3 event */ 889 #define SHRTIMER_ADCTRIGS0_TRG0ST1PER BIT(18) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER1 period event */ 890 #define SHRTIMER_ADCTRIGS0_TRG0ST1RST BIT(19) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER1 reset and counter roll-over event */ 891 #define SHRTIMER_ADCTRIGS0_TRG0ST2C1 BIT(20) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 1 event */ 892 #define SHRTIMER_ADCTRIGS0_TRG0ST2C2 BIT(21) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 2 event */ 893 #define SHRTIMER_ADCTRIGS0_TRG0ST2C3 BIT(22) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 3 event */ 894 #define SHRTIMER_ADCTRIGS0_TRG0ST2PER BIT(23) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER2 period event */ 895 #define SHRTIMER_ADCTRIGS0_TRG0ST3C1 BIT(24) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 1 event */ 896 #define SHRTIMER_ADCTRIGS0_TRG0ST3C2 BIT(25) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 2 event */ 897 #define SHRTIMER_ADCTRIGS0_TRG0ST3C3 BIT(26) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 3 event */ 898 #define SHRTIMER_ADCTRIGS0_TRG0ST3PER BIT(27) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER3 period event */ 899 #define SHRTIMER_ADCTRIGS0_TRG0ST4C1 BIT(28) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 1 event */ 900 #define SHRTIMER_ADCTRIGS0_TRG0ST4C2 BIT(29) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 2 event */ 901 #define SHRTIMER_ADCTRIGS0_TRG0ST4C3 BIT(30) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 3 event */ 902 #define SHRTIMER_ADCTRIGS0_TRG0ST4PER BIT(31) /*!< SHRTIMER_ADCTRIG0 on Slave_TIMER4 period event */ 903 904 /* SHRTIMER_ADCTRIGS1 */ 905 #define SHRTIMER_ADCTRIGS1_TRG1MTC0 BIT(0) /*!< SHRTIMER_ADCTRIG1 on Master_TIMER compare 0 event */ 906 #define SHRTIMER_ADCTRIGS1_TRG1MTC1 BIT(1) /*!< SHRTIMER_ADCTRIG1 on Master_TIMER compare 1 event */ 907 #define SHRTIMER_ADCTRIGS1_TRG1MTC2 BIT(2) /*!< SHRTIMER_ADCTRIG1 on Master_TIMER compare 2 event */ 908 #define SHRTIMER_ADCTRIGS1_TRG1MTC3 BIT(3) /*!< SHRTIMER_ADCTRIG1 on Master_TIMER compare 3 event */ 909 #define SHRTIMER_ADCTRIGS1_TRG1MTPER BIT(4) /*!< SHRTIMER_ADCTRIG1 on Master_TIMER period event */ 910 #define SHRTIMER_ADCTRIGS1_TRG1EXEV5 BIT(5) /*!< SHRTIMER_ADCTRIG1 on external event 5 */ 911 #define SHRTIMER_ADCTRIGS1_TRG1EXEV6 BIT(6) /*!< SHRTIMER_ADCTRIG1 on external event 6 */ 912 #define SHRTIMER_ADCTRIGS1_TRG1EXEV7 BIT(7) /*!< SHRTIMER_ADCTRIG1 on external event 7 */ 913 #define SHRTIMER_ADCTRIGS1_TRG1EXEV8 BIT(8) /*!< SHRTIMER_ADCTRIG1 on external event 8 */ 914 #define SHRTIMER_ADCTRIGS1_TRG1EXEV9 BIT(9) /*!< SHRTIMER_ADCTRIG1 on external event 9 */ 915 #define SHRTIMER_ADCTRIGS1_TRG1ST0C1 BIT(10) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 1 event */ 916 #define SHRTIMER_ADCTRIGS1_TRG1ST0C2 BIT(11) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 2 event */ 917 #define SHRTIMER_ADCTRIGS1_TRG1ST0C3 BIT(12) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 3 event */ 918 #define SHRTIMER_ADCTRIGS1_TRG1ST0PER BIT(13) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER0 period event */ 919 #define SHRTIMER_ADCTRIGS1_TRG1ST1C1 BIT(14) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 1 event */ 920 #define SHRTIMER_ADCTRIGS1_TRG1ST1C2 BIT(15) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 2 event */ 921 #define SHRTIMER_ADCTRIGS1_TRG1ST1C3 BIT(16) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 3 event */ 922 #define SHRTIMER_ADCTRIGS1_TRG1ST1PER BIT(17) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER1 period event */ 923 #define SHRTIMER_ADCTRIGS1_TRG1ST2C1 BIT(18) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 1 event */ 924 #define SHRTIMER_ADCTRIGS1_TRG1ST2C2 BIT(19) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 2 event */ 925 #define SHRTIMER_ADCTRIGS1_TRG1ST2C3 BIT(20) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 3 event */ 926 #define SHRTIMER_ADCTRIGS1_TRG1ST2PER BIT(21) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER2 period event */ 927 #define SHRTIMER_ADCTRIGS1_TRG1ST2RST BIT(22) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER2 reset and counter roll-over event */ 928 #define SHRTIMER_ADCTRIGS1_TRG1ST3C1 BIT(23) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 1 event */ 929 #define SHRTIMER_ADCTRIGS1_TRG1ST3C2 BIT(24) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 2 event */ 930 #define SHRTIMER_ADCTRIGS1_TRG1ST3C3 BIT(25) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 3 event */ 931 #define SHRTIMER_ADCTRIGS1_TRG1ST3PER BIT(26) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER3 period event */ 932 #define SHRTIMER_ADCTRIGS1_TRG1ST3RST BIT(27) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER3 reset and counter roll-over event */ 933 #define SHRTIMER_ADCTRIGS1_TRG1ST4C1 BIT(28) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 1 event */ 934 #define SHRTIMER_ADCTRIGS1_TRG1ST4C2 BIT(29) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 2 event */ 935 #define SHRTIMER_ADCTRIGS1_TRG1ST4C3 BIT(30) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 3 event */ 936 #define SHRTIMER_ADCTRIGS1_TRG1ST4RST BIT(31) /*!< SHRTIMER_ADCTRIG1 on Slave_TIMER4 reset and counter roll-over event */ 937 938 /* SHRTIMER_ADCTRIGS2 */ 939 #define SHRTIMER_ADCTRIGS2_TRG2MTC0 BIT(0) /*!< SHRTIMER_ADCTRIG2 on Master_TIMER compare 0 event */ 940 #define SHRTIMER_ADCTRIGS2_TRG2MTC1 BIT(1) /*!< SHRTIMER_ADCTRIG2 on Master_TIMER compare 1 event */ 941 #define SHRTIMER_ADCTRIGS2_TRG2MTC2 BIT(2) /*!< SHRTIMER_ADCTRIG2 on Master_TIMER compare 2 event */ 942 #define SHRTIMER_ADCTRIGS2_TRG2MTC3 BIT(3) /*!< SHRTIMER_ADCTRIG2 on Master_TIMER compare 3 event */ 943 #define SHRTIMER_ADCTRIGS2_TRG2MTPER BIT(4) /*!< SHRTIMER_ADCTRIG2 on Master_TIMER period event */ 944 #define SHRTIMER_ADCTRIGS2_TRG2EXEV0 BIT(5) /*!< SHRTIMER_ADCTRIG2 on external event 0 */ 945 #define SHRTIMER_ADCTRIGS2_TRG2EXEV1 BIT(6) /*!< SHRTIMER_ADCTRIG2 on external event 1 */ 946 #define SHRTIMER_ADCTRIGS2_TRG2EXEV2 BIT(7) /*!< SHRTIMER_ADCTRIG2 on external event 2 */ 947 #define SHRTIMER_ADCTRIGS2_TRG2EXEV3 BIT(8) /*!< SHRTIMER_ADCTRIG2 on external event 3 */ 948 #define SHRTIMER_ADCTRIGS2_TRG2EXEV4 BIT(9) /*!< SHRTIMER_ADCTRIG2 on external event 4 */ 949 #define SHRTIMER_ADCTRIGS2_TRG2ST0C1 BIT(10) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 1 event */ 950 #define SHRTIMER_ADCTRIGS2_TRG2ST0C2 BIT(11) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 2 event */ 951 #define SHRTIMER_ADCTRIGS2_TRG2ST0C3 BIT(12) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 3 event */ 952 #define SHRTIMER_ADCTRIGS2_TRG2ST0PER BIT(13) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER0 period event */ 953 #define SHRTIMER_ADCTRIGS2_TRG2ST0RST BIT(14) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER0 reset and counter roll-over event */ 954 #define SHRTIMER_ADCTRIGS2_TRG2ST1C1 BIT(15) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 1 event */ 955 #define SHRTIMER_ADCTRIGS2_TRG2ST1C2 BIT(16) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 2 event */ 956 #define SHRTIMER_ADCTRIGS2_TRG2ST1C3 BIT(17) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 3 event */ 957 #define SHRTIMER_ADCTRIGS2_TRG2ST1PER BIT(18) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER1 period event */ 958 #define SHRTIMER_ADCTRIGS2_TRG2ST1RST BIT(19) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER1 reset and counter roll-over event */ 959 #define SHRTIMER_ADCTRIGS2_TRG2ST2C1 BIT(20) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 1 event */ 960 #define SHRTIMER_ADCTRIGS2_TRG2ST2C2 BIT(21) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 2 event */ 961 #define SHRTIMER_ADCTRIGS2_TRG2ST2C3 BIT(22) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 3 event */ 962 #define SHRTIMER_ADCTRIGS2_TRG2ST2PER BIT(23) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER2 period event */ 963 #define SHRTIMER_ADCTRIGS2_TRG2ST3C1 BIT(24) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 1 event */ 964 #define SHRTIMER_ADCTRIGS2_TRG2ST3C2 BIT(25) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 2 event */ 965 #define SHRTIMER_ADCTRIGS2_TRG2ST3C3 BIT(26) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 3 event */ 966 #define SHRTIMER_ADCTRIGS2_TRG2ST3PER BIT(27) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER3 period event */ 967 #define SHRTIMER_ADCTRIGS2_TRG2ST4C1 BIT(28) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 1 event */ 968 #define SHRTIMER_ADCTRIGS2_TRG2ST4C2 BIT(29) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 2 event */ 969 #define SHRTIMER_ADCTRIGS2_TRG2ST4C3 BIT(30) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 3 event */ 970 #define SHRTIMER_ADCTRIGS2_TRG2ST4PER BIT(31) /*!< SHRTIMER_ADCTRIG2 on Slave_TIMER4 period event */ 971 972 /* SHRTIMER_ADCTRIGS3 */ 973 #define SHRTIMER_ADCTRIGS3_TRG3MTC0 BIT(0) /*!< SHRTIMER_ADCTRIG3 on Master_TIMER compare 0 event */ 974 #define SHRTIMER_ADCTRIGS3_TRG3MTC1 BIT(1) /*!< SHRTIMER_ADCTRIG3 on Master_TIMER compare 1 event */ 975 #define SHRTIMER_ADCTRIGS3_TRG3MTC2 BIT(2) /*!< SHRTIMER_ADCTRIG3 on Master_TIMER compare 2 event */ 976 #define SHRTIMER_ADCTRIGS3_TRG3MTC3 BIT(3) /*!< SHRTIMER_ADCTRIG3 on Master_TIMER compare 3 event */ 977 #define SHRTIMER_ADCTRIGS3_TRG3MTPER BIT(4) /*!< SHRTIMER_ADCTRIG3 on Master_TIMER period event */ 978 #define SHRTIMER_ADCTRIGS3_TRG3EXEV5 BIT(5) /*!< SHRTIMER_ADCTRIG3 on external event 5 */ 979 #define SHRTIMER_ADCTRIGS3_TRG3EXEV6 BIT(6) /*!< SHRTIMER_ADCTRIG3 on external event 6 */ 980 #define SHRTIMER_ADCTRIGS3_TRG3EXEV7 BIT(7) /*!< SHRTIMER_ADCTRIG3 on external event 7 */ 981 #define SHRTIMER_ADCTRIGS3_TRG3EXEV8 BIT(8) /*!< SHRTIMER_ADCTRIG3 on external event 8 */ 982 #define SHRTIMER_ADCTRIGS3_TRG3EXEV9 BIT(9) /*!< SHRTIMER_ADCTRIG3 on external event 9 */ 983 #define SHRTIMER_ADCTRIGS3_TRG3ST0C1 BIT(10) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 1 event */ 984 #define SHRTIMER_ADCTRIGS3_TRG3ST0C2 BIT(11) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 2 event */ 985 #define SHRTIMER_ADCTRIGS3_TRG3ST0C3 BIT(12) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 3 event */ 986 #define SHRTIMER_ADCTRIGS3_TRG3ST0PER BIT(13) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER0 period event */ 987 #define SHRTIMER_ADCTRIGS3_TRG3ST1C1 BIT(14) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 1 event */ 988 #define SHRTIMER_ADCTRIGS3_TRG3ST1C2 BIT(15) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 2 event */ 989 #define SHRTIMER_ADCTRIGS3_TRG3ST1C3 BIT(16) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 3 event */ 990 #define SHRTIMER_ADCTRIGS3_TRG3ST1PER BIT(17) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER1 period event */ 991 #define SHRTIMER_ADCTRIGS3_TRG3ST2C1 BIT(18) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 1 event */ 992 #define SHRTIMER_ADCTRIGS3_TRG3ST2C2 BIT(19) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 2 event */ 993 #define SHRTIMER_ADCTRIGS3_TRG3ST2C3 BIT(20) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 3 event */ 994 #define SHRTIMER_ADCTRIGS3_TRG3ST2PER BIT(21) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER2 period event */ 995 #define SHRTIMER_ADCTRIGS3_TRG3ST2RST BIT(22) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER2 reset and counter roll-over event */ 996 #define SHRTIMER_ADCTRIGS3_TRG3ST3C1 BIT(23) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 1 event */ 997 #define SHRTIMER_ADCTRIGS3_TRG3ST3C2 BIT(24) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 2 event */ 998 #define SHRTIMER_ADCTRIGS3_TRG3ST3C3 BIT(25) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 3 event */ 999 #define SHRTIMER_ADCTRIGS3_TRG3ST3PER BIT(26) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER3 period event */ 1000 #define SHRTIMER_ADCTRIGS3_TRG3ST3RST BIT(27) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER3 reset and counter roll-over event */ 1001 #define SHRTIMER_ADCTRIGS3_TRG3ST4C1 BIT(28) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 1 event */ 1002 #define SHRTIMER_ADCTRIGS3_TRG3ST4C2 BIT(29) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 2 event */ 1003 #define SHRTIMER_ADCTRIGS3_TRG3ST4C3 BIT(30) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 3 event */ 1004 #define SHRTIMER_ADCTRIGS3_TRG3ST4RST BIT(31) /*!< SHRTIMER_ADCTRIG3 on Slave_TIMER4 reset and counter roll-over event */ 1005 1006 /* SHRTIMER_DLLCCTL */ 1007 #define SHRTIMER_DLLCCTL_CLBSTRT BIT(0) /*!< DLL calibration start once */ 1008 #define SHRTIMER_DLLCCTL_CLBPEREN BIT(1) /*!< DLL periodic calibration enable */ 1009 #define SHRTIMER_DLLCCTL_CLBPER BITS(2,3) /*!< DLL calibration period */ 1010 1011 /* SHRTIMER_FLTINCFG0 */ 1012 #define SHRTIMER_FLTINCFG0_FLT0INEN BIT(0) /*!< fault 0 input enable */ 1013 #define SHRTIMER_FLTINCFG0_FLT0INP BIT(1) /*!< fault 0 input polarity */ 1014 #define SHRTIMER_FLTINCFG0_FLT0INSRC BIT(2) /*!< fault 0 input source */ 1015 #define SHRTIMER_FLTINCFG0_FLT0INFC BITS(3,6) /*!< fault 0 input filter control */ 1016 #define SHRTIMER_FLTINCFG0_FLT0INPROT BIT(7) /*!< protect fault 0 input configuration */ 1017 #define SHRTIMER_FLTINCFG0_FLT1INEN BIT(8) /*!< fault 1 input enable */ 1018 #define SHRTIMER_FLTINCFG0_FLT1INP BIT(9) /*!< fault 1 input polarity */ 1019 #define SHRTIMER_FLTINCFG0_FLT1INSRC BIT(10) /*!< fault 1 input source */ 1020 #define SHRTIMER_FLTINCFG0_FLT1INFC BITS(11,14) /*!< fault 1 input filter control */ 1021 #define SHRTIMER_FLTINCFG0_FLT1INPROT BIT(15) /*!< protect fault 1 input configuration */ 1022 #define SHRTIMER_FLTINCFG0_FLT2INEN BIT(16) /*!< fault 2 input enable */ 1023 #define SHRTIMER_FLTINCFG0_FLT2INP BIT(17) /*!< fault 2 input polarity */ 1024 #define SHRTIMER_FLTINCFG0_FLT2INSRC BIT(18) /*!< fault 2 input source */ 1025 #define SHRTIMER_FLTINCFG0_FLT2INFC BITS(19,22) /*!< fault 2 input filter control */ 1026 #define SHRTIMER_FLTINCFG0_FLT2INPROT BIT(23) /*!< protect fault 2 input configuration */ 1027 #define SHRTIMER_FLTINCFG0_FLT3INEN BIT(24) /*!< fault 3 input enable */ 1028 #define SHRTIMER_FLTINCFG0_FLT3INP BIT(25) /*!< fault 3 input polarity */ 1029 #define SHRTIMER_FLTINCFG0_FLT3INSRC BIT(26) /*!< fault 3 input source */ 1030 #define SHRTIMER_FLTINCFG0_FLT3INFC BITS(27,30) /*!< fault 3 input filter control */ 1031 #define SHRTIMER_FLTINCFG0_FLT3INPROT BIT(31) /*!< protect fault 3 input configuration */ 1032 1033 /* SHRTIMER_FLTINCFG1 */ 1034 #define SHRTIMER_FLTINCFG1_FLT4INEN BIT(0) /*!< fault 4 input enable */ 1035 #define SHRTIMER_FLTINCFG1_FLT4INP BIT(1) /*!< fault 4 input polarity */ 1036 #define SHRTIMER_FLTINCFG1_FLT4INSRC BIT(2) /*!< fault 4 input source */ 1037 #define SHRTIMER_FLTINCFG1_FLT4INFC BITS(3,6) /*!< fault 4 input filter control */ 1038 #define SHRTIMER_FLTINCFG1_FLT4INPROT BIT(7) /*!< protect fault 4 input configuration */ 1039 #define SHRTIMER_FLTINCFG1_FLTFDIV BITS(24,25) /*!< fault input digital filter clock division */ 1040 1041 /* SHRTIMER_DMAUPMTR */ 1042 #define SHRTIMER_DMAUPMTR_MTCTL0 BIT(0) /*!< SHRTIMER_MTCTL0 update by DMA mode */ 1043 #define SHRTIMER_DMAUPMTR_MTINTC BIT(1) /*!< SHRTIMER_MTINTC update by DMA mode */ 1044 #define SHRTIMER_DMAUPMTR_MTDMAINTEN BIT(2) /*!< SHRTIMER_MTDMAINTEN update by DMA mode */ 1045 #define SHRTIMER_DMAUPMTR_MTCNT BIT(3) /*!< SHRTIMER_MTCNT update by DMA mode */ 1046 #define SHRTIMER_DMAUPMTR_MTCAR BIT(4) /*!< SHRTIMER_MTCAR update by DMA mode */ 1047 #define SHRTIMER_DMAUPMTR_MTCREP BIT(5) /*!< SHRTIMER_MTCREP update by DMA mode */ 1048 #define SHRTIMER_DMAUPMTR_MTCMP0V BIT(6) /*!< SHRTIMER_MTCMP0V update by DMA mode */ 1049 #define SHRTIMER_DMAUPMTR_MTCMP1V BIT(7) /*!< SHRTIMER_MTCMP1V update by DMA mode */ 1050 #define SHRTIMER_DMAUPMTR_MTCMP2V BIT(8) /*!< SHRTIMER_MTCMP2V update by DMA mode */ 1051 #define SHRTIMER_DMAUPMTR_MTCMP3V BIT(9) /*!< SHRTIMER_MTCMP3V update by DMA mode */ 1052 #define SHRTIMER_DMAUPMTR_MTACTL BIT(31) /*!< SHRTIMER_MTACTL update by DMA mode */ 1053 1054 /* SHRTIMER_DMAUPSTxR */ 1055 #define SHRTIMER_DMAUPSTXR_STXCTL0 BIT(0) /*!< SHRTIMER_STxCTL0 update by DMA mode */ 1056 #define SHRTIMER_DMAUPSTXR_STXINTC BIT(1) /*!< SHRTIMER_STxINTC update by DMA mode */ 1057 #define SHRTIMER_DMAUPSTXR_STXDMAINTEN BIT(2) /*!< SHRTIMER_STxDMAINTEN update by DMA mode */ 1058 #define SHRTIMER_DMAUPSTXR_STXCNT BIT(3) /*!< SHRTIMER_STxCNT update by DMA mode */ 1059 #define SHRTIMER_DMAUPSTXR_STXCAR BIT(4) /*!< SHRTIMER_STxCAR update by DMA mode */ 1060 #define SHRTIMER_DMAUPSTXR_STXCREP BIT(5) /*!< SHRTIMER_STxCREP update by DMA mode */ 1061 #define SHRTIMER_DMAUPSTXR_STXCMP0V BIT(6) /*!< SHRTIMER_STxCMP0V update by DMA mode */ 1062 #define SHRTIMER_DMAUPSTXR_STXCMP1V BIT(7) /*!< SHRTIMER_STxCMP1V update by DMA mode */ 1063 #define SHRTIMER_DMAUPSTXR_STXCMP2V BIT(8) /*!< SHRTIMER_STxCMP2V update by DMA mode */ 1064 #define SHRTIMER_DMAUPSTXR_STXCMP3V BIT(9) /*!< SHRTIMER_STxCMP3V update by DMA mode */ 1065 #define SHRTIMER_DMAUPSTXR_STXDTCTL BIT(10) /*!< SHRTIMER_STxDTCTL update by DMA mode */ 1066 #define SHRTIMER_DMAUPSTXR_STXCH0SET BIT(11) /*!< SHRTIMER_STxCH0SET update by DMA mode */ 1067 #define SHRTIMER_DMAUPSTXR_STXCH0RST BIT(12) /*!< SHRTIMER_STxCH0RST update by DMA mode */ 1068 #define SHRTIMER_DMAUPSTXR_STXCH1SET BIT(13) /*!< SHRTIMER_STxCH1SET update by DMA mode */ 1069 #define SHRTIMER_DMAUPSTXR_STXCH1RST BIT(14) /*!< SHRTIMER_STxCH1RST update by DMA mode */ 1070 #define SHRTIMER_DMAUPSTXR_STXEXEVFCFG0 BIT(15) /*!< SHRTIMER_STxEXEVFCFG0 update by DMA mode */ 1071 #define SHRTIMER_DMAUPSTXR_STXEXEVFCFG1 BIT(16) /*!< SHRTIMER_STxEXEVFCFG1 update by DMA mode */ 1072 #define SHRTIMER_DMAUPSTXR_STXCNTRST BIT(17) /*!< SHRTIMER_STxCNTRST update by DMA mode */ 1073 #define SHRTIMER_DMAUPSTXR_STXCSCTL BIT(18) /*!< SHRTIMER_STxCSCTL update by DMA mode */ 1074 #define SHRTIMER_DMAUPSTXR_STXCHOCTL BIT(19) /*!< SHRTIMER_STxCHOCTL update by DMA mode */ 1075 #define SHRTIMER_DMAUPSTXR_STXFLTCTL BIT(20) /*!< SHRTIMER_STxFLTCTL update by DMA mode */ 1076 #define SHRTIMER_DMAUPSTXR_STXACTL BIT(31) /*!< SHRTIMER_STxACTL update by DMA mode */ 1077 1078 /* SHRTIMER_DMATB */ 1079 #define SHRTIMER_DMATB_DMATB BITS(0,31) /*!< DMA transfer buffer */ 1080 1081 /* constants definitions */ 1082 /* SHRTIMER time base parameters struct definitions */ 1083 typedef struct 1084 { 1085 uint32_t period; /*!< period value, min value: 3*tSHRTIMER_CK clock, max value: 0xFFFF �C (1*tSHRTIMER_CK) */ 1086 uint32_t repetitioncounter; /*!< the counter repetition value, 0x00~0xFF */ 1087 uint32_t prescaler; /*!< prescaler value, refer to: counter clock division */ 1088 uint32_t counter_mode; /*!< counter operating mode, refer to: counter operating mode */ 1089 }shrtimer_baseinit_parameter_struct; 1090 1091 /* waveform mode initialization parameters struct definitions */ 1092 typedef struct { 1093 uint32_t half_mode; /*!< specifies whether or not half mode is enabled, refer to: half mode enabling status */ 1094 uint32_t start_sync; /*!< specifies whether or not timer is started by a rising edge on the synchronization input, refer to: synchronous input start timer */ 1095 uint32_t reset_sync; /*!< specifies whether or not timer is reset by a rising edge on the synchronization input, refer to: synchronous input reset timer */ 1096 uint32_t dac_trigger; /*!< indicates whether or not the a DAC synchronization event is generated, refer to: trigger source to DAC */ 1097 uint32_t shadow; /*!< specifies whether or not the shadow registers are enabled, refer to: shadow registers enabling status */ 1098 uint32_t update_selection; /*!< the update occurs with respect to DMA mode or STxUPINy (Slave_TIMERx only), refer to: update event selection */ 1099 uint32_t cnt_bunch; /*!< the timer behaves during a bunch mode operation, refer to: timer behaves during a bunch mode operation */ 1100 uint32_t repetition_update; /*!< specifies whether or not registers update is triggered by the repetition event, refer to: update event generated by repetition event */ 1101 }shrtimer_timerinit_parameter_struct; 1102 1103 /* Slave_TIMER general behavior configuration struct definitions */ 1104 typedef struct { 1105 uint32_t balanced_mode; /*!< specifies whether or not the balanced mode is enabled, refer to: set balanced mode */ 1106 uint32_t fault_enable; /*!< specifies whether or not the fault channels are enabled for the Slave_TIMER, refer to: faut channel enabled for a Slave_TIMER*/ 1107 uint32_t fault_protect ; /*!< specifies whether the write protection function is enable or not, refer to: protect fault enable */ 1108 uint32_t deadtime_enable; /*!< specifies whether or not dead time insertion is enabled for the timer, refer to: dead time enable */ 1109 uint32_t delayed_idle; /*!< the delayed IDLE mode, refer to: set delayed IDLE state mode */ 1110 uint32_t update_source; /*!< the source triggering the Slave_TIMER registers update, refer to: update is done synchronously with any other Slave_TIMER or Master_TIMER update */ 1111 uint32_t cnt_reset; /*!< the source triggering the Slave_TIMER counter reset, refer to: Slave_TIMER counter reset */ 1112 uint32_t reset_update; /*!< specifies whether or not registers update is triggered when the timer counter is reset, refer to: update event generated by reset event */ 1113 }shrtimer_timercfg_parameter_struct; 1114 1115 /* compare unit configuration struct definitions */ 1116 typedef struct { 1117 uint32_t compare_value; /*!< compare value, min value: 3*tSHRTIMER_CK clock, max value: 0xFFFF �C (1*tSHRTIMER_CK) */ 1118 uint32_t delayed_mode; /*!< defining whether the compare register is behaving in regular mode or in delayed mode, refer to: compare 3 or 1 delayed mode */ 1119 uint32_t timeout_value; /*!< compare value for compare 0 or 2 when compare 3 or 1 is delayed mode with time out is selected , timeout_value + compare_value must be less than 0xFFFF */ 1120 }shrtimer_comparecfg_parameter_struct; 1121 1122 /* external event filtering for Slave_TIMER configuration struct definitions */ 1123 typedef struct { 1124 uint32_t filter_mode; /*!< the external event filter mode for Slave_TIMER, refer to: external event filter mode */ 1125 uint32_t memorized; /*!< specifies whether or not the signal is memorized, refer to: external event memorized enable */ 1126 }shrtimer_exevfilter_parameter_struct; 1127 1128 /* dead time configuration struct definitions */ 1129 typedef struct { 1130 uint32_t prescaler; /*!< dead time generator clock division, refer to: dead time prescaler */ 1131 uint32_t rising_value; /*!< rising edge dead-time value, 0x0000~0xFFFF */ 1132 uint32_t rising_sign; /*!< the sign of rising edge dead-time value, refer to: dead time rising sign */ 1133 uint32_t rising_protect; /*!< dead time rising edge protection for value and sign, refer to: dead time rising edge protection for value and sign */ 1134 uint32_t risingsign_protect; /*!< dead time rising edge protection for sign, refer to: dead time rising edge protection only for sign */ 1135 uint32_t falling_value; /*!< falling edge dead-time value, 0x0000~0xFFFF */ 1136 uint32_t falling_sign; /*!< the sign of falling edge dead-time value, refer to: dead time falling sign */ 1137 uint32_t falling_protect; /*!< dead time falling edge protection for value and sign, refer to: dead time falling edge protection for value and sign */ 1138 uint32_t fallingsign_protect; /*!< dead time falling edge protection for sign, refer to: dead time falling edge protection only for sign */ 1139 }shrtimer_deadtimecfg_parameter_struct; 1140 1141 /* carrier signal configuration struct definitions */ 1142 typedef struct { 1143 uint32_t period; /*!< carrier signal period: tCSPRD, 0x0~0xF. tCSPRD = (period + 1) * 16 * tSHRTIMER_CK */ 1144 uint32_t duty_cycle; /*!< carrier signal duty cycle, 0x0~0x7, duty cycle = duty_cycle/8 */ 1145 uint32_t first_pulse; /*!< first carrier-signal pulse width: tCSFSTPW, 0x0~0xF. tCSFSTPW = (first_pulse+1) * 16 * tSHRTIMER_CK */ 1146 }shrtimer_carriersignalcfg_parameter_struct; 1147 1148 /* synchronization configuration struct definitions */ 1149 typedef struct { 1150 uint32_t input_source; /*!< the external synchronization input source, refer to: the synchronization input source */ 1151 uint32_t output_source; /*!< the source and event to be sent on the external synchronization outputs, refer to: the synchronization output source */ 1152 uint32_t output_polarity; /*!< the polarity and length of the pulse to be sent on the external synchronization outputs, refer to: the pulse on the synchronization output pad SHRTIMER_SCOUT */ 1153 }shrtimer_synccfg_parameter_struct; 1154 1155 /* bunch mode configuration struct definitions */ 1156 typedef struct { 1157 uint32_t mode; /*!< the bunch mode operating mode, refer to: continuous mode in bunch mode */ 1158 uint32_t clock_source; /*!< specifies the burst mode clock source, refer to: bunch mode clock source*/ 1159 uint32_t prescaler; /*!< the bunch mode prescaler, refer to: bunch mode clock division */ 1160 uint32_t shadow; /*!< specifies whether or not preload is enabled for SHRTIMER_BMCMPV and SHRTIMER_BMCAR registers, refer to: bunch mode shadow enable */ 1161 uint32_t trigger; /*!< the event triggering the bunch operation, refer to: the event triggers bunch mode operation */ 1162 uint32_t idle_duration; /*!< the duration of the IDLE, 0x0000~0xFFFF */ 1163 uint32_t period; /*!< the bunch mode period which is the sum of the IDLE and RUN duration, 0x0001~0xFFFF */ 1164 }shrtimer_bunchmode_parameter_struct; 1165 1166 /* external event configuration struct definitions */ 1167 typedef struct { 1168 uint32_t source; /*!< the source of the external event,refer to: external event source */ 1169 uint32_t polarity; /*!< the active level of external event 0 when EXEVyEG[1:0] = 2��b00, refer to: external event polarity */ 1170 uint32_t edge ; /*!< the sensitivity of the external event, external event edge sensitivity */ 1171 uint32_t digital_filter; /*!< external event filter control, 0x0~0xF */ 1172 }shrtimer_exeventcfg_parameter_struct; 1173 1174 /* fault input configuration struct definitions */ 1175 typedef struct { 1176 uint32_t source; /*!< the source of the fault input, refer to: fault input source */ 1177 uint32_t polarity; /*!< the polarity of the fault input, refer to: fault input polarity */ 1178 uint32_t filter; /*!< fault input filter control, 0x0~0xF */ 1179 uint32_t control; /*!< fault input enable or disable, refer to: enable or disable fault */ 1180 uint32_t protect ; /*!< protect fault input configuration, refer to: protect fault input configuration */ 1181 }shrtimer_faultcfg_parameter_struct; 1182 1183 /* ADC trigger configuration struct definitions */ 1184 typedef struct { 1185 uint32_t update_source; /*!< the source triggering the update of the SHRTIMER_ADCTRIGSy register, refer to: SHRTIMER_ADCTRIG update source */ 1186 uint32_t trigger; /*!< the event triggering the ADC conversion, refer to: ADC trigger event */ 1187 }shrtimer_adctrigcfg_parameter_struct; 1188 1189 /* channel output configuration struct definitions */ 1190 typedef struct { 1191 uint32_t polarity; /*!< configure channel output polarity, refer to: channel output polarity */ 1192 uint32_t set_request; /*!< configure the event generates channel ��set request��, refer to channel set request */ 1193 uint32_t reset_request; /*!< configure the event generates channel ��reset request��, refer to: channel reset request */ 1194 uint32_t idle_bunch; /*!< specifies whether channel output can be IDLE state in bunch mode, refer to: channel IDLE state enable in bunch mode */ 1195 uint32_t idle_state; /*!< specifies channel output idle state, refer to channel output idle state */ 1196 uint32_t fault_state; /*!< specifies the output level when in FAULT state, refer to: channel output in fault state */ 1197 uint32_t carrier_mode; /*!< specifies whether or not the carrier-signal mode is enabled, refer to: channel carrier-signal mode enable */ 1198 uint32_t deadtime_bunch; /*!< specifies whether or not deadtime is inserted before output entering the IDLE state in bunch mode, refer to: channel dead-time insert in bunch mode */ 1199 }shrtimer_channel_outputcfg_parameter_struct; 1200 1201 /* SHRTIMER timer to configure */ 1202 #define SHRTIMER_SLAVE_TIMER0 ((uint32_t)0x00000000U) /*!< index associated to Slave_TIMER0 */ 1203 #define SHRTIMER_SLAVE_TIMER1 ((uint32_t)0x00000001U) /*!< index associated to Slave_TIMER1 */ 1204 #define SHRTIMER_SLAVE_TIMER2 ((uint32_t)0x00000002U) /*!< index associated to Slave_TIMER2 */ 1205 #define SHRTIMER_SLAVE_TIMER3 ((uint32_t)0x00000003U) /*!< index associated to Slave_TIMER3 */ 1206 #define SHRTIMER_SLAVE_TIMER4 ((uint32_t)0x00000004U) /*!< index associated to Slave_TIMER4 */ 1207 #define SHRTIMER_MASTER_TIMER ((uint32_t)0x00000005U) /*!< index associated to Master_TIMER */ 1208 #define SHRTIMER_COMMONINDEX ((uint32_t)0x00000006U) /*!< index associated to common registers */ 1209 1210 /* compare unit to configure */ 1211 #define SHRTIMER_COMPARE0 ((uint32_t)0x00000000U) /*!< compare unit 0 */ 1212 #define SHRTIMER_COMPARE1 ((uint32_t)0x00000001U) /*!< compare unit 1 */ 1213 #define SHRTIMER_COMPARE2 ((uint32_t)0x00000002U) /*!< compare unit 2 */ 1214 #define SHRTIMER_COMPARE3 ((uint32_t)0x00000003U) /*!< compare unit 3 */ 1215 #define SHRTIMER_COMPARE0_COMPOSITE ((uint32_t)0x00000005U) /*!< compare 0 composite unit */ 1216 1217 /* capture unit to configure */ 1218 #define SHRTIMER_CAPTURE_0 ((uint32_t)0x00000000U) /*!< capture unit 0 */ 1219 #define SHRTIMER_CAPTURE_1 ((uint32_t)0x00000001U) /*!< capture unit 1 */ 1220 1221 /* external event to configure */ 1222 #define SHRTIMER_EXEVENT_NONE ((uint32_t)0x00000000U) /*!< undefined event channel */ 1223 #define SHRTIMER_EXEVENT_0 ((uint32_t)0x00000001U) /*!< extern event 0 */ 1224 #define SHRTIMER_EXEVENT_1 ((uint32_t)0x00000002U) /*!< extern event 1 */ 1225 #define SHRTIMER_EXEVENT_2 ((uint32_t)0x00000004U) /*!< extern event 2 */ 1226 #define SHRTIMER_EXEVENT_3 ((uint32_t)0x00000008U) /*!< extern event 3 */ 1227 #define SHRTIMER_EXEVENT_4 ((uint32_t)0x00000010U) /*!< extern event 4 */ 1228 #define SHRTIMER_EXEVENT_5 ((uint32_t)0x00000020U) /*!< extern event 5 */ 1229 #define SHRTIMER_EXEVENT_6 ((uint32_t)0x00000040U) /*!< extern event 6 */ 1230 #define SHRTIMER_EXEVENT_7 ((uint32_t)0x00000080U) /*!< extern event 7 */ 1231 #define SHRTIMER_EXEVENT_8 ((uint32_t)0x00000100U) /*!< extern event 8 */ 1232 #define SHRTIMER_EXEVENT_9 ((uint32_t)0x00000200U) /*!< extern event 9 */ 1233 1234 /* fault to configure */ 1235 #define SHRTIMER_FAULT_0 ((uint32_t)0x00000000U) /*!< fault 0 */ 1236 #define SHRTIMER_FAULT_1 ((uint32_t)0x00000001U) /*!< fault 1 */ 1237 #define SHRTIMER_FAULT_2 ((uint32_t)0x00000002U) /*!< fault 2 */ 1238 #define SHRTIMER_FAULT_3 ((uint32_t)0x00000004U) /*!< fault 3 */ 1239 #define SHRTIMER_FAULT_4 ((uint32_t)0x00000008U) /*!< fault 4 */ 1240 1241 /* SHRTIMER_ADCTRIG to configure */ 1242 #define SHRTIMER_ADCTRIG_0 ((uint32_t)0x00000000U) /*!< SHRTIMER_ADCTRIG0 */ 1243 #define SHRTIMER_ADCTRIG_1 ((uint32_t)0x00000001U) /*!< SHRTIMER_ADCTRIG1 */ 1244 #define SHRTIMER_ADCTRIG_2 ((uint32_t)0x00000002U) /*!< SHRTIMER_ADCTRIG2 */ 1245 #define SHRTIMER_ADCTRIG_3 ((uint32_t)0x00000003U) /*!< SHRTIMER_ADCTRIG3 */ 1246 1247 /* channel to configure */ 1248 #define SHRTIMER_ST0_CH0 ((uint32_t)0x00000001U) /*!< Slave_TIMER0 channel 0 */ 1249 #define SHRTIMER_ST0_CH1 ((uint32_t)0x00000002U) /*!< Slave_TIMER0 channel 1 */ 1250 #define SHRTIMER_ST1_CH0 ((uint32_t)0x00000004U) /*!< Slave_TIMER1 channel 0 */ 1251 #define SHRTIMER_ST1_CH1 ((uint32_t)0x00000008U) /*!< Slave_TIMER1 channel 1 */ 1252 #define SHRTIMER_ST2_CH0 ((uint32_t)0x00000010U) /*!< Slave_TIMER2 channel 0 */ 1253 #define SHRTIMER_ST2_CH1 ((uint32_t)0x00000020U) /*!< Slave_TIMER2 channel 1 */ 1254 #define SHRTIMER_ST3_CH0 ((uint32_t)0x00000040U) /*!< Slave_TIMER3 channel 0 */ 1255 #define SHRTIMER_ST3_CH1 ((uint32_t)0x00000080U) /*!< Slave_TIMER3 channel 1 */ 1256 #define SHRTIMER_ST4_CH0 ((uint32_t)0x00000100U) /*!< Slave_TIMER4 channel 0 */ 1257 #define SHRTIMER_ST4_CH1 ((uint32_t)0x00000200U) /*!< Slave_TIMER4 channel 1 */ 1258 1259 /* the counter to enable/disable */ 1260 #define SHRTIMER_MT_COUNTER (SHRTIMER_MTCTL0_MTCEN) /*!< the counter of Master_TIMER */ 1261 #define SHRTIMER_ST0_COUNTER (SHRTIMER_MTCTL0_ST0CEN) /*!< the counter of Slave_TIMER0 */ 1262 #define SHRTIMER_ST1_COUNTER (SHRTIMER_MTCTL0_ST1CEN) /*!< the counter of Slave_TIMER1 */ 1263 #define SHRTIMER_ST2_COUNTER (SHRTIMER_MTCTL0_ST2CEN) /*!< the counter of Slave_TIMER2 */ 1264 #define SHRTIMER_ST3_COUNTER (SHRTIMER_MTCTL0_ST3CEN) /*!< the counter of Slave_TIMER3 */ 1265 #define SHRTIMER_ST4_COUNTER (SHRTIMER_MTCTL0_ST4CEN) /*!< the counter of Slave_TIMER4 */ 1266 1267 /* counter clock division */ 1268 #define SHRTIMER_PRESCALER_MUL64 ((uint32_t)0x00000008U) /* fSHRTIMER_PSSCK = fHPTIM_HPCK = 64 *fSHRTIMER_CK */ 1269 #define SHRTIMER_PRESCALER_MUL32 ((uint32_t)0x00000000U) /* fSHRTIMER_PSSCK = fHPTIM_HPCK/2 = 32 *fSHRTIMER_CK */ 1270 #define SHRTIMER_PRESCALER_MUL16 ((uint32_t)0x00000001U) /* fSHRTIMER_PSSCK = fHPTIM_HPCK/4 = 16 *fSHRTIMER_CK */ 1271 #define SHRTIMER_PRESCALER_MUL8 ((uint32_t)0x00000002U) /* fSHRTIMER_PSSCK = fHPTIM_HPCK/8 = 8 *fSHRTIMER_CK */ 1272 #define SHRTIMER_PRESCALER_MUL4 ((uint32_t)0x00000003U) /* fSHRTIMER_PSSCK = fHPTIM_HPCK/16 = 4 *fSHRTIMER_CK */ 1273 #define SHRTIMER_PRESCALER_MUL2 ((uint32_t)0x00000004U) /* fSHRTIMER_PSSCK = fHPTIM_HPCK/32 = 2*fSHRTIMER_CK */ 1274 #define SHRTIMER_PRESCALER_DIV1 ((uint32_t)0x00000005U) /* fSHRTIMER_PSSCK = fHPTIM_HPCK/64 = fSHRTIMER_CK */ 1275 #define SHRTIMER_PRESCALER_DIV2 ((uint32_t)0x00000006U) /* fSHRTIMER_PSSCK = fHPTIM_HPCK/128 = fSHRTIMER_CK/2 */ 1276 #define SHRTIMER_PRESCALER_DIV4 ((uint32_t)0x00000007U) /* fSHRTIMER_PSSCK = fHPTIM_HPCK/256 = fSHRTIMER_CK/4 */ 1277 1278 /* counter operating mode */ 1279 #define SHRTIMER_COUNTER_MODE_CONTINOUS ((uint32_t)0x00000008U) /*!< the timer operates in continuous (free-running) mode */ 1280 #define SHRTIMER_COUNTER_MODE_SINGLEPULSE ((uint32_t)0x00000000U) /*!< single pulse mode: the counter can be reset only if it stops (period elapsed) */ 1281 #define SHRTIMER_COUNTER_MODE_SINGLEPULSE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< single pulse mode: the counter can be reset at any time (running or stopped) */ 1282 1283 /* half mode enabling status */ 1284 #define SHRTIMER_HALFMODE_DISABLED ((uint32_t)0x00000000U) /*!< half mode disable */ 1285 #define SHRTIMER_HALFMODE_ENABLED ((uint32_t)0x00000020U) /*!< half mode enable */ 1286 1287 /* synchronous input start timer */ 1288 #define SHRTIMER_SYNISTART_DISABLED ((uint32_t)0x00000000U) /*!< the synchronous input signal cannot start the counter */ 1289 #define SHRTIMER_SYNISTART_ENABLED ((uint32_t)0x00000800U) /*!< the synchronous input signal can start the counter */ 1290 1291 /* synchronous input reset timer */ 1292 #define SHRTIMER_SYNCRESET_DISABLED ((uint32_t)0x00000000U) /*!< the synchronous input signal cannot reset the counter */ 1293 #define SHRTIMER_SYNCRESET_ENABLED ((uint32_t)0x00000400U) /*!< the synchronous input signal can reset the counter */ 1294 1295 /* trigger source to DAC */ 1296 #define SHRTIMER_DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< no DAC trigger event generated */ 1297 #define SHRTIMER_DAC_TRIGGER_DACTRIG0 ((uint32_t)0x02000000U) /*!< DAC trigger event generated on SHRTIMER_DACTRIG0 */ 1298 #define SHRTIMER_DAC_TRIGGER_DACTRIG1 ((uint32_t)0x04000000U) /*!< DAC trigger event generated on SHRTIMER_DACTRIG1 */ 1299 #define SHRTIMER_DAC_TRIGGER_DACTRIG2 ((uint32_t)0x06000000U) /*!< DAC trigger event generated on SHRTIMER_DACTRIG2 */ 1300 1301 /* shadow registers enabling status */ 1302 #define SHRTIMER_SHADOW_DISABLED ((uint32_t)0x00000000U) /*!< the shadow registers are disabled: the write access is directly done into the active registers */ 1303 #define SHRTIMER_SHADOW_ENABLED ((uint32_t)0x08000000U) /*!< the shadow registers are enabled: the write access is done into the shadow registers */ 1304 1305 /* update event selection */ 1306 #define SHRTIMER_MT_ST_UPDATE_SELECTION_INDEPENDENT ((uint32_t)0x00000000U) /*!< update event generated independently from DMA mode */ 1307 #define SHRTIMER_MT_ST_UPDATE_SELECTION_DMAMODE ((uint32_t)0x10000000U) /*!< update event generated when the DMA transfer completed in DMA mode */ 1308 #define SHRTIMER_MT_ST_UPDATE_SELECTION_DMAMODE_UPDATE ((uint32_t)0x20000000U) /*!< update event generated on the update event following the DMA transfer completed in DMA mode */ 1309 #define SHRTIMER_ST_UPDATE_SELECTION_STXUPIN2 ((uint32_t)0x50000000U) /*!< update event generated on the rising edge of STxUPIN2 */ 1310 #define SHRTIMER_ST_UPDATE_SELECTION_STXUPIN2_UPDATE ((uint32_t)0x80000000U) /*!< update event generated on the update event following the rising edge of STxUPIN2 */ 1311 1312 /* timer behaves during a bunch mode operation */ 1313 #define SHRTIMER_TIMERBUNCHNMODE_MAINTAINCLOCK ((uint32_t)0x00000000U) /*!< counter clock(SHRTIMER_PSCCK) is maintained and the counter operates normally */ 1314 #define SHRTIMER_TIMERBUNCHMODE_RESETCOUNTER ((uint32_t)0x00010000U) /*!< counter clock(SHRTIMER_PSCCK) is stopped and the counter is reset */ 1315 1316 /* update event generated by repetition event */ 1317 #define SHRTIMER_UPDATEONREPETITION_DISABLED ((uint32_t)0x00000000U) /*!< update event generated by repetition event disable */ 1318 #define SHRTIMER_UPDATEONREPETITION_ENABLED ((uint32_t)0x20000000U) /*!< update event generated by repetition event enable */ 1319 1320 /* set balanced mode */ 1321 #define SHRTIMER_STXBALANCEDMODE_DISABLED ((uint32_t)0x00000000U) /*!< balanced mode disabled */ 1322 #define SHRTIMER_STXBALANCEDMODE_ENABLED ((uint32_t)0x00000040U) /*!< balanced mode enabled */ 1323 1324 /* faut channel enabled for a Slave_TIMER */ 1325 #define SHRTIMER_STXFAULTENABLE_NONE ((uint32_t)0x00000000U) /*!< no fault enabled */ 1326 #define SHRTIMER_STXFAULTENABLE_FAULT0 (SHRTIMER_STXFLTCTL_FLT0EN) /*!< fault 0 enabled */ 1327 #define SHRTIMER_STXFAULTENABLE_FAULT1 (SHRTIMER_STXFLTCTL_FLT1EN) /*!< fault 1 enabled */ 1328 #define SHRTIMER_STXFAULTENABLE_FAULT2 (SHRTIMER_STXFLTCTL_FLT2EN) /*!< fault 2 enabled */ 1329 #define SHRTIMER_STXFAULTENABLE_FAULT3 (SHRTIMER_STXFLTCTL_FLT3EN) /*!< fault 3 enabled */ 1330 #define SHRTIMER_STXFAULTENABLE_FAULT4 (SHRTIMER_STXFLTCTL_FLT4EN) /*!< fault 4 enabled */ 1331 1332 /* protect fault enable */ 1333 #define SHRTIMER_STXFAULT_PROTECT_READWRITE ((uint32_t)0x00000000U) /*!< protect disable. FLTyEN (y=0..4) is writable */ 1334 #define SHRTIMER_STXFAULT_PROTECT_READONLY (SHRTIMER_STXFLTCTL_FLTENPROT) /*!< protect enable. FLTyEN (y=0..4) is read-only */ 1335 1336 /* dead time enable */ 1337 #define SHRTIMER_STXDEADTIME_DISABLED ((uint32_t)0x00000000U) /*!< channel 0 and channel 1 outputs are independent. */ 1338 #define SHRTIMER_STXDEADTIME_ENABLED (SHRTIMER_STXCHOCTL_DTEN) /*!< channel 0 and channel 1 outputs are complementary and dead-time is inserted between channel 0 and channel 1 outputs */ 1339 1340 /* set delayed IDLE state mode */ 1341 #define SHRTIMER_STXDELAYED_IDLE_DISABLED ((uint32_t)0x00000000U) /*!< no action */ 1342 #define SHRTIMER_STXDELAYED_IDLE_CH0_EEV57 (SHRTIMER_STXCHOCTL_DLYISMEN) /*!< channel 0 output delayed IDLE on external event 5 or 7 */ 1343 #define SHRTIMER_STXDELAYED_IDLE_CH1_EEV57 (((uint32_t)0x00000400U) | SHRTIMER_STXCHOCTL_DLYISMEN) /*!< channel 1 output delayed IDLE on external event 5 or 7 */ 1344 #define SHRTIMER_STXDELAYED_IDLE_BOTH_EEV57 (((uint32_t)0x00000800U) | SHRTIMER_STXCHOCTL_DLYISMEN) /*!< channel 0 and channel 1 output delayed IDLE on external event 5 or 7 */ 1345 #define SHRTIMER_STXDELAYED_IDLE_BALANCED_EEV57 (((uint32_t)0x00000C00U) | SHRTIMER_STXCHOCTL_DLYISMEN) /*!< balanced IDLE on external event 5 or 7 */ 1346 #define SHRTIMER_STXDELAYED_IDLE_CH0_DEEV68 (((uint32_t)0x00001000U) | SHRTIMER_STXCHOCTL_DLYISMEN) /*!< channel 0 output delayed IDLE on external event 6 or 8 */ 1347 #define SHRTIMER_STXDELAYED_IDLE_CH1_DEEV68 (((uint32_t)0x00001400U) | SHRTIMER_STXCHOCTL_DLYISMEN) /*!< channel 1 output delayed IDLE on external event 6 or 8 */ 1348 #define SHRTIMER_STXDELAYED_IDLE_BOTH_EEV68 (((uint32_t)0x00001800U) | SHRTIMER_STXCHOCTL_DLYISMEN) /*!< channel 0 and channel 1 output delayed IDLE on external event 6 or 8 */ 1349 #define SHRTIMER_STXDELAYED_IDLE_BALANCED_EEV68 (((uint32_t)0x00001C00U) | SHRTIMER_STXCHOCTL_DLYISMEN) /*!< balanced IDLE on external event 6 or 8 */ 1350 1351 /* update is done synchronously with any other Slave_TIMER or Master_TIMER update */ 1352 #define SHRTIMER_STXUPDATETRIGGER_NONE ((uint32_t)0x00000000U) /*!< register update is disabled */ 1353 #define SHRTIMER_STXUPDATETRIGGER_MASTER (SHRTIMER_STXCTL0_UPBMT) /*!< update by Master_TIMER update event */ 1354 #define SHRTIMER_STXUPDATETRIGGER_ST0 (SHRTIMER_STXCTL0_UPBST0) /*!< update by Slave_TIMER0 update event */ 1355 #define SHRTIMER_STXUPDATETRIGGER_ST1 (SHRTIMER_STXCTL0_UPBST1) /*!< update by Slave_TIMER1 update event */ 1356 #define SHRTIMER_STXUPDATETRIGGER_ST2 (SHRTIMER_STXCTL0_UPBST2) /*!< update by Slave_TIMER2 update event */ 1357 #define SHRTIMER_STXUPDATETRIGGER_ST3 (SHRTIMER_STXCTL0_UPBST3) /*!< update by Slave_TIMER3 update event */ 1358 #define SHRTIMER_STXUPDATETRIGGER_ST4 (SHRTIMER_STXCTL0_UPBST4) /*!< update by Slave_TIMER4 update event */ 1359 1360 /* Slave_TIMER counter reset */ 1361 #define SHRTIMER_STXCNT_RESET_NONE ((uint32_t)0x00000000U) /*!< no counter reset trigger */ 1362 #define SHRTIMER_STXCNT_RESET_UPDATE (SHRTIMER_STXCNTRST_UPRST) /*!< the Slave_TIMER counter is reset upon update event */ 1363 #define SHRTIMER_STXCNT_RESET_CMP1 (SHRTIMER_STXCNTRST_CMP1RST) /*!< the Slave_TIMER counter is reset upon Slave_TIMER compare 1 event */ 1364 #define SHRTIMER_STXCNT_RESET_CMP3 (SHRTIMER_STXCNTRST_CMP3RST) /*!< the Slave_TIMER counter is reset upon Slave_TIMER compare 3 event */ 1365 #define SHRTIMER_STXCNT_RESET_MASTER_PER (SHRTIMER_STXCNTRST_MTPERRST) /*!< the Slave_TIMER counter is reset upon Master_TIMER period event */ 1366 #define SHRTIMER_STXCNT_RESET_MASTER_CMP0 (SHRTIMER_STXCNTRST_MTCMP0RST) /*!< the Slave_TIMER counter is reset upon Master_TIMER compare 0 event */ 1367 #define SHRTIMER_STXCNT_RESET_MASTER_CMP1 (SHRTIMER_STXCNTRST_MTCMP1RST) /*!< the Slave_TIMER counter is reset upon Master_TIMER compare 1 event */ 1368 #define SHRTIMER_STXCNT_RESET_MASTER_CMP2 (SHRTIMER_STXCNTRST_MTCMP2RST) /*!< the Slave_TIMER counter is reset upon Master_TIMER compare 2 event */ 1369 #define SHRTIMER_STXCNT_RESET_MASTER_CMP3 (SHRTIMER_STXCNTRST_MTCMP3RST) /*!< the Slave_TIMER counter is reset upon Master_TIMER compare 3 event */ 1370 #define SHRTIMER_STXCNT_RESET_EEV_0 (SHRTIMER_STXCNTRST_EXEV0RST) /*!< the Slave_TIMER counter is reset upon external event 0 */ 1371 #define SHRTIMER_STXCNT_RESET_EEV_1 (SHRTIMER_STXCNTRST_EXEV1RST) /*!< the Slave_TIMER counter is reset upon external event 1 */ 1372 #define SHRTIMER_STXCNT_RESET_EEV_2 (SHRTIMER_STXCNTRST_EXEV2RST) /*!< the Slave_TIMER counter is reset upon external event 2 */ 1373 #define SHRTIMER_STXCNT_RESET_EEV_3 (SHRTIMER_STXCNTRST_EXEV3RST) /*!< the Slave_TIMER counter is reset upon external event 3 */ 1374 #define SHRTIMER_STXCNT_RESET_EEV_4 (SHRTIMER_STXCNTRST_EXEV4RST) /*!< the Slave_TIMER counter is reset upon external event 4 */ 1375 #define SHRTIMER_STXCNT_RESET_EEV_5 (SHRTIMER_STXCNTRST_EXEV5RST) /*!< the Slave_TIMER counter is reset upon external event 5 */ 1376 #define SHRTIMER_STXCNT_RESET_EEV_6 (SHRTIMER_STXCNTRST_EXEV6RST) /*!< the Slave_TIMER counter is reset upon external event 6 */ 1377 #define SHRTIMER_STXCNT_RESET_EEV_7 (SHRTIMER_STXCNTRST_EXEV7RST) /*!< the Slave_TIMER counter is reset upon external event 7 */ 1378 #define SHRTIMER_STXCNT_RESET_EEV_8 (SHRTIMER_STXCNTRST_EXEV8RST) /*!< the Slave_TIMER counter is reset upon external event 8 */ 1379 #define SHRTIMER_STXCNT_RESET_EEV_9 (SHRTIMER_STXCNTRST_EXEV9RST) /*!< the Slave_TIMER counter is reset upon external event 9 */ 1380 #define SHRTIMER_STXCNT_RESET_OTHER0_CMP0 BIT(19) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 0 event */ 1381 #define SHRTIMER_STXCNT_RESET_OTHER0_CMP1 BIT(20) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 1 event */ 1382 #define SHRTIMER_STXCNT_RESET_OTHER0_CMP3 BIT(21) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 3 event */ 1383 #define SHRTIMER_STXCNT_RESET_OTHER1_CMP0 BIT(22) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 0 event */ 1384 #define SHRTIMER_STXCNT_RESET_OTHER1_CMP1 BIT(23) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 1 event */ 1385 #define SHRTIMER_STXCNT_RESET_OTHER1_CMP3 BIT(24) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 3 event */ 1386 #define SHRTIMER_STXCNT_RESET_OTHER2_CMP0 BIT(25) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 0 event */ 1387 #define SHRTIMER_STXCNT_RESET_OTHER2_CMP1 BIT(26) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 1 event */ 1388 #define SHRTIMER_STXCNT_RESET_OTHER2_CMP3 BIT(27) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 3 event */ 1389 #define SHRTIMER_STXCNT_RESET_OTHER3_CMP0 BIT(28) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 0 event */ 1390 #define SHRTIMER_STXCNT_RESET_OTHER3_CMP1 BIT(29) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 1 event */ 1391 #define SHRTIMER_STXCNT_RESET_OTHER3_CMP3 BIT(30) /*!< the Slave_TIMER counter is reset upon other Slave_TIMER compare 3 event */ 1392 1393 /* update event generated by reset event */ 1394 #define SHRTIMER_STXUPDATEONRESET_DISABLED ((uint32_t)0x00000000U) /*!< update event generated by reset event or roll-over event disable */ 1395 #define SHRTIMER_STXUPDATEONRESET_ENABLED (SHRTIMER_STXCTL0_UPRST) /*!< update event generated by reset event or roll-over event enable */ 1396 1397 /* compare 3 or 1 delayed mode */ 1398 #define SHRTIMER_DELAYEDMODE_DISABLE ((uint32_t)0x00000000U) /*!< delayed mode disable */ 1399 #define SHRTIMER_DELAYEDMODE_NOTIMEOUT ((uint32_t)0x00001000U) /*!< compare event generated only if a capture has occurred */ 1400 #define SHRTIMER_DELAYEDMODE_TIMEOUTCMP0 ((uint32_t)0x00002000U) /*!< compare event generated if a capture has occurred or after a compare 0 match (timeout if capture event is missing) */ 1401 #define SHRTIMER_DELAYEDMODE_TIMEOUTCMP2 ((uint32_t)0x00003000U) /*!< compare event generated if a capture has occurred or after a compare 2 match (timeout if capture event is missing) */ 1402 1403 /* capture trigger source */ 1404 #define SHRTIMER_CAPTURETRIGGER_NONE ((uint32_t)0x00000000U) /*!< capture trigger is disabled */ 1405 #define SHRTIMER_CAPTURETRIGGER_UPDATE (SHRTIMER_STXCAP0TRG_CP0BUP) /*!< capture triggered by update event */ 1406 #define SHRTIMER_CAPTURETRIGGER_EXEV_0 (SHRTIMER_STXCAP0TRG_CP0BEXEV0) /*!< capture triggered by external event 0 */ 1407 #define SHRTIMER_CAPTURETRIGGER_EXEV_1 (SHRTIMER_STXCAP0TRG_CP0BEXEV1) /*!< capture triggered by external event 1 */ 1408 #define SHRTIMER_CAPTURETRIGGER_EXEV_2 (SHRTIMER_STXCAP0TRG_CP0BEXEV2) /*!< capture triggered by external event 2 */ 1409 #define SHRTIMER_CAPTURETRIGGER_EXEV_3 (SHRTIMER_STXCAP0TRG_CP0BEXEV3) /*!< capture triggered by external event 3 */ 1410 #define SHRTIMER_CAPTURETRIGGER_EXEV_4 (SHRTIMER_STXCAP0TRG_CP0BEXEV4) /*!< capture triggered by external event 4 */ 1411 #define SHRTIMER_CAPTURETRIGGER_EXEV_5 (SHRTIMER_STXCAP0TRG_CP0BEXEV5) /*!< capture triggered by external event 5 */ 1412 #define SHRTIMER_CAPTURETRIGGER_EXEV_6 (SHRTIMER_STXCAP0TRG_CP0BEXEV6) /*!< capture triggered by external event 6 */ 1413 #define SHRTIMER_CAPTURETRIGGER_EXEV_7 (SHRTIMER_STXCAP0TRG_CP0BEXEV7) /*!< capture triggered by external event 7 */ 1414 #define SHRTIMER_CAPTURETRIGGER_EXEV_8 (SHRTIMER_STXCAP0TRG_CP0BEXEV8) /*!< capture triggered by external event 8 */ 1415 #define SHRTIMER_CAPTURETRIGGER_EXEV_9 (SHRTIMER_STXCAP0TRG_CP0BEXEV9) /*!< capture triggered by external event 9 */ 1416 #define SHRTIMER_CAPTURETRIGGER_ST0_ACTIVE (SHRTIMER_STXCAP0TRG_CP0BST0A) /*!< capture triggered by ST0CH0_O output inactive to active transition */ 1417 #define SHRTIMER_CAPTURETRIGGER_ST0_INACTIVE (SHRTIMER_STXCAP0TRG_CP0BST0NA) /*!< capture triggered by ST0CH0_O output active to inactive transition */ 1418 #define SHRTIMER_CAPTURETRIGGER_ST0_CMP0 (SHRTIMER_STXCAP0TRG_CP0BST0CMP0) /*!< capture triggered by compare 0 event of Slave_TIMER0 */ 1419 #define SHRTIMER_CAPTURETRIGGER_ST0_CMP1 (SHRTIMER_STXCAP0TRG_CP0BST0CMP1) /*!< capture triggered by compare 0 event of Slave_TIMER0 */ 1420 #define SHRTIMER_CAPTURETRIGGER_ST1_ACTIVE (SHRTIMER_STXCAP0TRG_CP0BST1A) /*!< capture triggered by ST1CH0_O output inactive to active transition */ 1421 #define SHRTIMER_CAPTURETRIGGER_ST1_INACTIVE (SHRTIMER_STXCAP0TRG_CP0BST1NA) /*!< capture triggered by ST1CH0_O output active to inactive transition */ 1422 #define SHRTIMER_CAPTURETRIGGER_ST1_CMP0 (SHRTIMER_STXCAP0TRG_CP0BST1CMP0) /*!< capture triggered by compare 0 event of Slave_TIMER1 */ 1423 #define SHRTIMER_CAPTURETRIGGER_ST1_CMP1 (SHRTIMER_STXCAP0TRG_CP0BST1CMP1) /*!< capture triggered by compare 0 event of Slave_TIMER1 */ 1424 #define SHRTIMER_CAPTURETRIGGER_ST2_ACTIVE (SHRTIMER_STXCAP0TRG_CP0BST2A) /*!< capture triggered by ST2CH0_O output inactive to active transition */ 1425 #define SHRTIMER_CAPTURETRIGGER_ST2_INACTIVE (SHRTIMER_STXCAP0TRG_CP0BST2NA) /*!< capture triggered by ST2CH0_O output active to inactive transition */ 1426 #define SHRTIMER_CAPTURETRIGGER_ST2_CMP0 (SHRTIMER_STXCAP0TRG_CP0BST2CMP0) /*!< capture triggered by compare 0 event of Slave_TIMER2 */ 1427 #define SHRTIMER_CAPTURETRIGGER_ST2_CMP1 (SHRTIMER_STXCAP0TRG_CP0BST2CMP1) /*!< capture triggered by compare 0 event of Slave_TIMER2 */ 1428 #define SHRTIMER_CAPTURETRIGGER_ST3_ACTIVE (SHRTIMER_STXCAP0TRG_CP0BST3A) /*!< capture triggered by ST3CH0_O output inactive to active transition */ 1429 #define SHRTIMER_CAPTURETRIGGER_ST3_INACTIVE (SHRTIMER_STXCAP0TRG_CP0BST3NA) /*!< capture triggered by ST3CH0_O output active to inactive transition */ 1430 #define SHRTIMER_CAPTURETRIGGER_ST3_CMP0 (SHRTIMER_STXCAP0TRG_CP0BST3CMP0) /*!< capture triggered by compare 0 event of Slave_TIMER3 */ 1431 #define SHRTIMER_CAPTURETRIGGER_ST3_CMP1 (SHRTIMER_STXCAP0TRG_CP0BST3CMP1) /*!< capture triggered by compare 0 event of Slave_TIMER3 */ 1432 #define SHRTIMER_CAPTURETRIGGER_ST4_ACTIVE (SHRTIMER_STXCAP0TRG_CP0BST4A) /*!< capture triggered by ST4CH0_O output inactive to active transition */ 1433 #define SHRTIMER_CAPTURETRIGGER_ST4_INACTIVE (SHRTIMER_STXCAP0TRG_CP0BST4NA) /*!< capture triggered by ST4CH0_O output active to inactive transition */ 1434 #define SHRTIMER_CAPTURETRIGGER_ST4_CMP0 (SHRTIMER_STXCAP0TRG_CP0BST4CMP0) /*!< capture triggered by compare 0 event of Slave_TIMER4 */ 1435 #define SHRTIMER_CAPTURETRIGGER_ST4_CMP1 (SHRTIMER_STXCAP0TRG_CP0BST4CMP1) /*!< capture triggered by compare 0 event of Slave_TIMER4 */ 1436 1437 /* external event filter mode */ 1438 #define SHRTIMER_EXEVFILTER_DISABLE ((uint32_t)0x00000000U) /* filter mode disable */ 1439 #define SHRTIMER_EXEVFILTER_BLANKINGCMP0 ((uint32_t)0x00000002U) /*!< blanking mode. the blank is from counter reset/roll-over to SHRTIMER_STxCMP0V */ 1440 #define SHRTIMER_EXEVFILTER_BLANKINGCMP1 ((uint32_t)0x00000004U) /*!< blanking mode. the blank is from counter reset/roll-over to SHRTIMER_STxCMP1V */ 1441 #define SHRTIMER_EXEVFILTER_BLANKINGCMP2 ((uint32_t)0x00000006U) /*!< blanking mode. the blank is from counter reset/roll-over to SHRTIMER_STxCMP2V */ 1442 #define SHRTIMER_EXEVFILTER_BLANKINGCMP3 ((uint32_t)0x00000008U) /*!< blanking mode. the blank is from counter reset/roll-over to SHRTIMER_STxCMP3V */ 1443 #define SHRTIMER_EXEVFILTER_BLANKINGSRC0 ((uint32_t)0x0000000AU) /*!< blanking mode. the blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC0 */ 1444 #define SHRTIMER_EXEVFILTER_BLANKINGSRC1 ((uint32_t)0x0000000CU) /*!< blanking mode. the blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC1 */ 1445 #define SHRTIMER_EXEVFILTER_BLANKINGSRC2 ((uint32_t)0x0000000EU) /*!< blanking mode. the blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC2 */ 1446 #define SHRTIMER_EXEVFILTER_BLANKINGSRC3 ((uint32_t)0x00000010U) /*!< blanking mode. the blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC3 */ 1447 #define SHRTIMER_EXEVFILTER_BLANKINGSRC4 ((uint32_t)0x00000012U) /*!< blanking mode. the blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC4 */ 1448 #define SHRTIMER_EXEVFILTER_BLANKINGSRC5 ((uint32_t)0x00000014U) /*!< blanking mode. the blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC5 */ 1449 #define SHRTIMER_EXEVFILTER_BLANKINGSRC6 ((uint32_t)0x00000016U) /*!< blanking mode. the blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC6 */ 1450 #define SHRTIMER_EXEVFILTER_BLANKINGSRC7 ((uint32_t)0x00000018U) /*!< blanking mode. the blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC7 */ 1451 #define SHRTIMER_EXEVFILTER_WINDOWINGCMP1 ((uint32_t)0x0000001AU) /*!< windowing mode. the windowing is from counter reset/roll-over to SHRTIMER_STxCMP1V */ 1452 #define SHRTIMER_EXEVFILTER_WINDOWINGCMP2 ((uint32_t)0x0000001CU) /*!< windowing mode. the windowing is from counter reset/roll-over to SHRTIMER_STxCMP2V */ 1453 #define SHRTIMER_EXEVFILTER_WINDOWINGSRC ((uint32_t)0x0000001EU) /*!< windowing mode. the windowing is from other Slave_TIMERy(not Slave_TIMERx):STWDSRC */ 1454 1455 /* external event memorized enable */ 1456 #define SHRTIMER_EXEVMEMORIZED_DISABLE ((uint32_t)0x00000000U) /*!< external event memory disable */ 1457 #define SHRTIMER_EXEVMEMORIZED_ENABLE (SHRTIMER_STXEXEVFCFG0_EXEV0MEEN) /*!< external event memory enable. the memorized event is generated as soon as the blanking period or windowing period is completed */ 1458 1459 /* dead time prescaler */ 1460 #define SHRTIMER_DEADTIME_PRESCALER_MUL64 ((uint32_t)0x0000000AU) /*!< fSHRTIMER_DTGCK = 64* fSHRTIMER_CK */ 1461 #define SHRTIMER_DEADTIME_PRESCALER_MUL32 ((uint32_t)0x00000009U) /*!< fSHRTIMER_DTGCK = 32* fSHRTIMER_CK */ 1462 #define SHRTIMER_DEADTIME_PRESCALER_MUL16 ((uint32_t)0x00000008U) /*!< fSHRTIMER_DTGCK = 16* fSHRTIMER_CK */ 1463 #define SHRTIMER_DEADTIME_PRESCALER_MUL8 ((uint32_t)0x00000000U) /*!< fSHRTIMER_DTGCK = 8*fSHRTIMER_CK */ 1464 #define SHRTIMER_DEADTIME_PRESCALER_MUL4 ((uint32_t)0x00000001U) /*!< fSHRTIMER_DTGCK = (8*fSHRTIMER_CK)/2 = 4*fSHRTIMER_CK */ 1465 #define SHRTIMER_DEADTIME_PRESCALER_MUL2 ((uint32_t)0x00000002U) /*!< fSHRTIMER_DTGCK = (8*fSHRTIMER_CK)/4 = 2*fSHRTIMER_CK */ 1466 #define SHRTIMER_DEADTIME_PRESCALER_DIV1 ((uint32_t)0x00000003U) /*!< fSHRTIMER_DTGCK = (8*fSHRTIMER_CK)/8 = fSHRTIMER_CK*/ 1467 #define SHRTIMER_DEADTIME_PRESCALER_DIV2 ((uint32_t)0x00000004U) /*!< fSHRTIMER_DTGCK = (8*fSHRTIMER_CK)/16 = fSHRTIMER_CK / 2 */ 1468 #define SHRTIMER_DEADTIME_PRESCALER_DIV4 ((uint32_t)0x00000005U) /*!< fSHRTIMER_DTGCK = (8*fSHRTIMER_CK)/32 = fSHRTIMER_CK / 4 */ 1469 #define SHRTIMER_DEADTIME_PRESCALER_DIV8 ((uint32_t)0x00000006U) /*!< fSHRTIMER_DTGCK = (8*fSHRTIMER_CK)/64 = fSHRTIMER_CK / 8 */ 1470 #define SHRTIMER_DEADTIME_PRESCALER_DIV16 ((uint32_t)0x00000007U) /*!< fSHRTIMER_DTGCK = (8*fSHRTIMER_CK)/128 = fSHRTIMER_CK / 16 */ 1471 1472 /* dead time rising sign */ 1473 #define SHRTIMER_DEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000U) /*!< the sign of rising edge dead-time value is positive */ 1474 #define SHRTIMER_DEADTIME_RISINGSIGN_NEGATIVE (SHRTIMER_STXDTCTL_DTRS) /*!< the sign of rising edge dead-time value is negative */ 1475 1476 /* dead time rising edge protection for value and sign */ 1477 #define SHRTIMER_DEADTIME_RISING_PROTECT_DISABLE ((uint32_t)0x00000000U) /*!< protect disable. DTRS and DTRCFG[15:0] register are writable */ 1478 #define SHRTIMER_DEADTIME_RISING_PROTECT_ENABLE (SHRTIMER_STXDTCTL_DTRSVPROT) /*!< protect enable. DTRS and DTRCFG[15:0] are read-only */ 1479 1480 /* dead time rising edge protection only for sign */ 1481 #define SHRTIMER_DEADTIME_RISINGSIGN_PROTECT_DISABLE ((uint32_t)0x00000000U) /*!< protect disable. DTRS bit is writable */ 1482 #define SHRTIMER_DEADTIME_RISINGSIGN_PROTECT_ENABLE (SHRTIMER_STXDTCTL_DTRSPROT) /*!< protect enable. DTRS bit is read-only */ 1483 1484 /* dead time falling sign */ 1485 #define SHRTIMER_DEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000U) /*!< the sign of falling edge dead-time value is positive */ 1486 #define SHRTIMER_DEADTIME_FALLINGSIGN_NEGATIVE (SHRTIMER_STXDTCTL_DTFS) /*!< the sign of falling edge dead-time value is negative */ 1487 1488 /* dead time falling edge protection for value and sign */ 1489 #define SHRTIMER_DEADTIME_FALLING_PROTECT_DISABLE ((uint32_t)0x00000000U) /*!< protect disable. DTFS and DTFCFG[15:0] register are writable */ 1490 #define SHRTIMER_DEADTIME_FALLING_PROTECT_ENABLE (SHRTIMER_STXDTCTL_DTFSVPROT) /*!< protect enable. DTFS and DTFCFG[15:0] are read-only */ 1491 1492 /* dead time falling edge protection only for sign */ 1493 #define SHRTIMER_DEADTIME_FALLINGSIGN_PROTECT_DISABLE ((uint32_t)0x00000000U) /*!< protect disable. DTFS bit is writable */ 1494 #define SHRTIMER_DEADTIME_FALLINGSIGN_PROTECT_ENABLE (SHRTIMER_STXDTCTL_DTFSPROT) /*!< protect enable. DTFS bit is read-only */ 1495 1496 /* the registers that can be written by DMA mode */ 1497 #define SHRTIMER_DMAMODE_NONE ((uint32_t)0x00000000U) /*!< no register is updated by DMA mode */ 1498 #define SHRTIMER_DMAMODE_CTL0 (SHRTIMER_DMAUPSTXR_STXCTL0) /*!< MTCTL0 or STxCTL0 register is updated by DMA mode */ 1499 #define SHRTIMER_DMAMODE_INTC (SHRTIMER_DMAUPSTXR_STXINTC) /*!< MT or STx register is updated by DMA mode */ 1500 #define SHRTIMER_DMAMODE_DMAINTEN (SHRTIMER_DMAUPSTXR_STXDMAINTEN) /*!< MTINTC or STxINTC register is updated by DMA mode */ 1501 #define SHRTIMER_DMAMODE_CNT (SHRTIMER_DMAUPSTXR_STXCNT) /*!< MTCNT or STxCNT register is updated by DMA mode */ 1502 #define SHRTIMER_DMAMODE_CAR (SHRTIMER_DMAUPSTXR_STXCAR) /*!< MTCAR or STxCAR register is updated by DMA mode */ 1503 #define SHRTIMER_DMAMODE_CREP (SHRTIMER_DMAUPSTXR_STXCREP) /*!< MTCREP or STxCREP register is updated by DMA mode */ 1504 #define SHRTIMER_DMAMODE_CMP0V (SHRTIMER_DMAUPSTXR_STXCMP0V) /*!< MTCMP0V or STxCMP0V register is updated by DMA mode */ 1505 #define SHRTIMER_DMAMODE_CMP1V (SHRTIMER_DMAUPSTXR_STXCMP1V) /*!< MTCMP1V or STxCMP1V register is updated by DMA mode */ 1506 #define SHRTIMER_DMAMODE_CMP2V (SHRTIMER_DMAUPSTXR_STXCMP2V) /*!< MTCMP2V or STxCMP2V register is updated by DMA mode */ 1507 #define SHRTIMER_DMAMODE_CMP3V (SHRTIMER_DMAUPSTXR_STXCMP3V) /*!< MTCMP3V or STxCMP3V register is updated by DMA mode */ 1508 #define SHRTIMER_DMAMODE_DTCTL (SHRTIMER_DMAUPSTXR_STXDTCTL) /*!< STxDTCTL register is updated by DMA mode */ 1509 #define SHRTIMER_DMAMODE_CH0SET (SHRTIMER_DMAUPSTXR_STXCH0SET) /*!< STxCH0SET register is updated by DMA mode */ 1510 #define SHRTIMER_DMAMODE_CH0RST (SHRTIMER_DMAUPSTXR_STXCH0RST) /*!< STxCH0RST register is updated by DMA mode */ 1511 #define SHRTIMER_DMAMODE_CH1SET (SHRTIMER_DMAUPSTXR_STXCH1SET) /*!< STxCH1SET register is updated by DMA mode */ 1512 #define SHRTIMER_DMAMODE_CH1RST (SHRTIMER_DMAUPSTXR_STXCH1RST) /*!< STxCH1RST register is updated by DMA mode */ 1513 #define SHRTIMER_DMAMODE_EXEVFCFG0 (SHRTIMER_DMAUPSTXR_STXEXEVFCFG0) /*!< STxEXEVFCFG0 register is updated by DMA mode */ 1514 #define SHRTIMER_DMAMODE_EXEVFCFG1 (SHRTIMER_DMAUPSTXR_STXEXEVFCFG1) /*!< STxEXEVFCFG1 register is updated by DMA mode */ 1515 #define SHRTIMER_DMAMODE_CNTRST (SHRTIMER_DMAUPSTXR_STXCNTRST) /*!< STxCNTRST register is updated by DMA mode */ 1516 #define SHRTIMER_DMAMODE_CSCTL (SHRTIMER_DMAUPSTXR_STXCSCTL) /*!< STxCSCTL register is updated by DMA mode */ 1517 #define SHRTIMER_DMAMODE_CHOCTL (SHRTIMER_DMAUPSTXR_STXCHOCTL) /*!< STxCHOCTL register is updated by DMA mode */ 1518 #define SHRTIMER_DMAMODE_FLTCTL (SHRTIMER_DMAUPSTXR_STXFLTCTL) /*!< STxFLTCTL register is updated by DMA mode */ 1519 #define SHRTIMER_DMAMODE_ACTL (SHRTIMER_DMAUPSTXR_STXACTL) /*!< STxACTL register is updated by DMA mode */ 1520 1521 /* the synchronization input source */ 1522 #define SHRTIMER_SYNCINPUTSOURCE_DISABLE ((uint32_t)0x00000000U) /*!< synchronization input disable */ 1523 #define SHRTIMER_SYNCINPUTSOURCE_INTERNAL ((uint32_t)0x00000200U) /*!< internal signal: TIMER0_TRGO in the advanced timer TIMER0 */ 1524 #define SHRTIMER_SYNCINPUTSOURCE_EXTERNAL ((uint32_t)0x00000300U) /*!< external signal: a positive pulse on the SHRTIMER_SCIN pin triggers the Master_TIMER */ 1525 1526 /* the synchronization output source */ 1527 #define SHRTIMER_SYNCOUTPUTSOURCE_MTSTART ((uint32_t)0x00000000U) /*!< Master_TIMER start event to be sent to the synchronization output pad SHRTIMER_SCOUT */ 1528 #define SHRTIMER_SYNCOUTPUTSOURCE_MTCMP0 ((uint32_t)0x00004000U) /*!< Master_TIMER compare 0 event to be sent to the synchronization output pad SHRTIMER_SCOUT*/ 1529 #define SHRTIMER_SYNCOUTPUTSOURCE_ST0START ((uint32_t)0x00008000U) /*!< Slave_TIMER0 reset and start event to be sent to the synchronization output pad SHRTIMER_SCOUT */ 1530 #define SHRTIMER_SYNCOUTPUTSOURCE_ST0CMP0 ((uint32_t)0x0000C000U) /*!< Slave_TIMER0 compare 0 event to be sent to the synchronization output pad SHRTIMER_SCOUT */ 1531 1532 /* the pulse on the synchronization output pad SHRTIMER_SCOUT */ 1533 #define SHRTIMER_SYNCOUTPUTPOLARITY_DISABLE ((uint32_t)0x00000000U) /*!< pulse generated disable. No pulse on SHRTIMER_SCOUT */ 1534 #define SHRTIMER_SYNCOUTPUTPOLARITY_POSITIVE ((uint32_t)0x00002000U) /*!< positive pulse generated on the SHRTIMER_SCOUT. the length of it is 16 tSHRTIMER_CK cycles */ 1535 #define SHRTIMER_SYNCOUTPUTPOLARITY_NEGATIVE ((uint32_t)0x00003000U) /*!< negative pulse generated on the SHRTIMER_SCOUT. the length of it is 16 tSHRTIMER_CK cycles */ 1536 1537 /* continuous mode in bunch mode */ 1538 #define SHRTIMER_BUNCHMODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode. the BM-counter stops by hardware when it reaches the SHRTIMER_BMCAR value */ 1539 #define SHRTIMER_BUNCHMODE_CONTINOUS (SHRTIMER_BMCTL_BMCTN) /*!< continuous mode. the BM-counter rolls over to zero and counts continuously when it reaches the SHRTIMER_BMCAR value */ 1540 1541 /* bunch mode clock source */ 1542 #define SHRTIMER_BUNCHMODE_CLOCKSOURCE_MASTER ((uint32_t)0x00000000U) /*!< the clock source for the bunch mode counter: Master_TIMER counter reset/roll-over event */ 1543 #define SHRTIMER_BUNCHMODE_CLOCKSOURCE_ST0 ((uint32_t)0x00000004U) /*!< the clock source for the bunch mode counter: Slave_TIMER0 counter reset/roll-over event */ 1544 #define SHRTIMER_BUNCHMODE_CLOCKSOURCE_ST1 ((uint32_t)0x00000008U) /*!< the clock source for the bunch mode counter: Slave_TIMER1 counter reset/roll-over event */ 1545 #define SHRTIMER_BUNCHMODE_CLOCKSOURCE_ST2 ((uint32_t)0x0000000CU) /*!< the clock source for the bunch mode counter: Slave_TIMER2 counter reset/roll-over event */ 1546 #define SHRTIMER_BUNCHMODE_CLOCKSOURCE_ST3 ((uint32_t)0x00000010U) /*!< the clock source for the bunch mode counter: Slave_TIMER3 counter reset/roll-over event */ 1547 #define SHRTIMER_BUNCHMODE_CLOCKSOURCE_ST4 ((uint32_t)0x00000014U) /*!< the clock source for the bunch mode counter: Slave_TIMER4 counter reset/roll-over event */ 1548 #define SHRTIMER_BUNCHMODE_CLOCKSOURCE_TIMER6_TRGO ((uint32_t)0x00000020U) /*!< the clock source for the bunch mode counter: chip internal signal BMCLK2 */ 1549 #define SHRTIMER_BUNCHMODE_CLOCKSOURCE_SHRTIMERCK ((uint32_t)0x00000028U) /*!< the clock source for the bunch mode counter: prescaled fSHRTIMER_CK clock */ 1550 1551 /* bunch mode clock division */ 1552 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK */ 1553 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV2 ((uint32_t)0x00000040U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/2 */ 1554 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV4 ((uint32_t)0x00000080U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/4 */ 1555 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV8 ((uint32_t)0x000000C0U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/8 */ 1556 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV16 ((uint32_t)0x00000100U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/16 */ 1557 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV32 ((uint32_t)0x00000140U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/32 */ 1558 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV64 ((uint32_t)0x00000180U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/64 */ 1559 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV128 ((uint32_t)0x000001C0U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/128 */ 1560 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV256 ((uint32_t)0x00000200U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/256 */ 1561 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV512 ((uint32_t)0x00000240U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/512 */ 1562 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV1024 ((uint32_t)0x00000280U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/1024 */ 1563 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV2048 ((uint32_t)0x000002C0U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/2048*/ 1564 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV4096 ((uint32_t)0x00000300U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/4096 */ 1565 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV8192 ((uint32_t)0x00000340U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/8192 */ 1566 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV16384 ((uint32_t)0x00000380U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/16384 */ 1567 #define SHRTIMER_BUNCHMODE_PRESCALER_DIV32768 ((uint32_t)0x000003C0U) /*!< fSHRTIMER_BMCNTCK = fSHRTIMER_CK/32768 */ 1568 1569 /* bunch mode shadow enable */ 1570 #define SHRTIMER_BUNCHMODEPRELOAD_DISABLED ((uint32_t)0x00000000U) /*!< the shadow registers for SHRTIMER_BMCMPV and SHRTIMER_BMCAR registers are disabled */ 1571 #define SHRTIMER_BUNCHMODEPRELOAD_ENABLED (SHRTIMER_BMCTL_BMSE) /*!< the shadow registers for SHRTIMER_BMCMPV and SHRTIMER_BMCAR registers are enabled */ 1572 1573 /* the event triggers bunch mode operation */ 1574 #define SHRTIMER_BUNCHMODE_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< clear all triggers */ 1575 #define SHRTIMER_BUNCHMODE_TRIGGER_MTRESET (SHRTIMER_BMSTRG_MTRST) /*!< Master_TIMER reset event triggers bunch mode operation */ 1576 #define SHRTIMER_BUNCHMODE_TRIGGER_MTREPETITION (SHRTIMER_BMSTRG_MTREP) /*!< Master_TIMER repetition event triggers bunch mode operation */ 1577 #define SHRTIMER_BUNCHMODE_TRIGGER_MTCMP0 (SHRTIMER_BMSTRG_MTCMP0) /*!< Master_TIMER compare 0 event triggers bunch mode operation */ 1578 #define SHRTIMER_BUNCHMODE_TRIGGER_MTCMP1 (SHRTIMER_BMSTRG_MTCMP1) /*!< Master_TIMER compare 1 event triggers bunch mode operation */ 1579 #define SHRTIMER_BUNCHMODE_TRIGGER_MTCMP2 (SHRTIMER_BMSTRG_MTCMP2) /*!< Master_TIMER compare 2 event triggers bunch mode operation */ 1580 #define SHRTIMER_BUNCHMODE_TRIGGER_MTCMP3 (SHRTIMER_BMSTRG_MTCMP3) /*!< Master_TIMER compare 3 event triggers bunch mode operation */ 1581 #define SHRTIMER_BUNCHMODE_TRIGGER_ST0RESET (SHRTIMER_BMSTRG_ST0RST) /*!< Slave_TIMER0 reset event triggers bunch mode operation */ 1582 #define SHRTIMER_BUNCHMODE_TRIGGER_ST0REPETITION (SHRTIMER_BMSTRG_ST0REP) /*!< Slave_TIMER0 repetition event triggers bunch mode operation */ 1583 #define SHRTIMER_BUNCHMODE_TRIGGER_ST0CMP0 (SHRTIMER_BMSTRG_ST0CMP0) /*!< Slave_TIMER0 compare 0 event triggers bunch mode operation */ 1584 #define SHRTIMER_BUNCHMODE_TRIGGER_ST0CMP1 (SHRTIMER_BMSTRG_ST0CMP1) /*!< Slave_TIMER0 compare 1 event triggers bunch mode operation */ 1585 #define SHRTIMER_BUNCHMODE_TRIGGER_ST1RESET (SHRTIMER_BMSTRG_ST1RST) /*!< Slave_TIMER1 reset event triggers bunch mode operation */ 1586 #define SHRTIMER_BUNCHMODE_TRIGGER_ST1REPETITION (SHRTIMER_BMSTRG_ST1REP) /*!< Slave_TIMER1 repetition event triggers bunch mode operation */ 1587 #define SHRTIMER_BUNCHMODE_TRIGGER_ST1CMP0 (SHRTIMER_BMSTRG_ST1CMP0) /*!< Slave_TIMER1 compare 0 event triggers bunch mode operation */ 1588 #define SHRTIMER_BUNCHMODE_TRIGGER_ST1CMP1 (SHRTIMER_BMSTRG_ST1CMP1) /*!< Slave_TIMER1 compare 1 event triggers bunch mode operation */ 1589 #define SHRTIMER_BUNCHMODE_TRIGGER_ST2RESET (SHRTIMER_BMSTRG_ST2RST) /*!< Slave_TIMER2 reset event triggers bunch mode operation */ 1590 #define SHRTIMER_BUNCHMODE_TRIGGER_ST2REPETITION (SHRTIMER_BMSTRG_ST2REP) /*!< Slave_TIMER2 repetition event triggers bunch mode operation */ 1591 #define SHRTIMER_BUNCHMODE_TRIGGER_ST2CMP0 (SHRTIMER_BMSTRG_ST2CMP0) /*!< Slave_TIMER2 compare 0 event triggers bunch mode operation */ 1592 #define SHRTIMER_BUNCHMODE_TRIGGER_ST2CMP1 (SHRTIMER_BMSTRG_ST2CMP1) /*!< Slave_TIMER2 compare 1 event triggers bunch mode operation */ 1593 #define SHRTIMER_BUNCHMODE_TRIGGER_ST3RESET (SHRTIMER_BMSTRG_ST3RST) /*!< Slave_TIMER3 reset event triggers bunch mode operation */ 1594 #define SHRTIMER_BUNCHMODE_TRIGGER_ST3REPETITION (SHRTIMER_BMSTRG_ST3REP) /*!< Slave_TIMER3 repetition event triggers bunch mode operation */ 1595 #define SHRTIMER_BUNCHMODE_TRIGGER_ST3CMP0 (SHRTIMER_BMSTRG_ST3CMP0) /*!< Slave_TIMER3 compare 0 event triggers bunch mode operation */ 1596 #define SHRTIMER_BUNCHMODE_TRIGGER_ST3CMP1 (SHRTIMER_BMSTRG_ST3CMP1) /*!< Slave_TIMER3 compare 1 event triggers bunch mode operation */ 1597 #define SHRTIMER_BUNCHMODE_TRIGGER_ST4RESET (SHRTIMER_BMSTRG_ST4RST) /*!< Slave_TIMER4 reset event triggers bunch mode operation */ 1598 #define SHRTIMER_BUNCHMODE_TRIGGER_ST4REPETITION (SHRTIMER_BMSTRG_ST4REP) /*!< Slave_TIMER4 repetition event triggers bunch mode operation */ 1599 #define SHRTIMER_BUNCHMODE_TRIGGER_ST4CMP0 (SHRTIMER_BMSTRG_ST4CMP0) /*!< Slave_TIMER4 compare 0 event triggers bunch mode operation */ 1600 #define SHRTIMER_BUNCHMODE_TRIGGER_ST4CMP1 (SHRTIMER_BMSTRG_ST4CMP1) /*!< Slave_TIMER4 compare 1 event triggers bunch mode operation */ 1601 #define SHRTIMER_BUNCHMODE_TRIGGER_ST0EVENT6 (SHRTIMER_BMSTRG_ST0EXEV6) /*!< Slave_TIMER0 period event following external event 6 triggers bunch mode operation */ 1602 #define SHRTIMER_BUNCHMODE_TRIGGER_ST3EVENT7 (SHRTIMER_BMSTRG_ST3EXEV7) /*!< Slave_TIMER3 period event following external event 7 triggers bunch mode operation */ 1603 #define SHRTIMER_BUNCHMODE_TRIGGER_EVENT6 (SHRTIMER_BMSTRG_EXEV6) /*!< external event 6 triggers bunch mode operation */ 1604 #define SHRTIMER_BUNCHMODE_TRIGGER_EVENT7 (SHRTIMER_BMSTRG_EXEV7) /*!< external event 7 triggers bunch mode operation */ 1605 #define SHRTIMER_BUNCHMODE_TRIGGER_CHIP (SHRTIMER_BMSTRG_CISGN) /*!< chip internal signal triggers bunch mode operation */ 1606 1607 /* external event source */ 1608 #define SHRTIMER_EXEV_SRC0 ((uint32_t)0x00000000U) /*!< external event y source is EXEVySRC 0 */ 1609 #define SHRTIMER_EXEV_SRC1 ((uint32_t)0x00000001U) /*!< external event y source is EXEVySRC 1 */ 1610 #define SHRTIMER_EXEV_SRC2 ((uint32_t)0x00000002U) /*!< external event y source is EXEVySRC 2 */ 1611 #define SHRTIMER_EXEV_SRC3 ((uint32_t)0x00000003U) /*!< external event y source is EXEVySRC 3 */ 1612 1613 /* external event polarity */ 1614 #define SHRTIMER_EXEV_POLARITY_HIGH ((uint32_t)0x00000000U) /*!< external event y active at high level */ 1615 #define SHRTIMER_EXEV_POLARITY_LOW (SHRTIMER_EXEVCFG0_EXEV0P) /*!< external event y active at low level */ 1616 1617 /* external event edge sensitivity */ 1618 #define SHRTIMER_EXEV_EDGE_LEVEL ((uint32_t)0x00000000U) /*!< level active. active level is defined by EXEVyP bit */ 1619 #define SHRTIMER_EXEV_EDGE_RISING ((uint32_t)0x00000008U) /*!< rising edge active */ 1620 #define SHRTIMER_EXEV_EDGE_FALLING ((uint32_t)0x00000010U) /*!< falling edge active */ 1621 #define SHRTIMER_EXEV_EDGE_BOTH ((uint32_t)0x00000018U) /*!< both edges active */ 1622 1623 /* external event digital filter clock division */ 1624 #define SHRTIMER_EXEV_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< fSHRTIMER_EXEVFCK = fSHRTIMER_CK */ 1625 #define SHRTIMER_EXEV_PRESCALER_DIV2 ((uint32_t)0x40000000U) /*!< fSHRTIMER_EXEVFCK = fSHRTIMER_CK / 2 */ 1626 #define SHRTIMER_EXEV_PRESCALER_DIV4 ((uint32_t)0x80000000U) /*!< fSHRTIMER_EXEVFCK = fSHRTIMER_CK / 4 */ 1627 #define SHRTIMER_EXEV_PRESCALER_DIV8 ((uint32_t)0xC0000000U) /*!< fSHRTIMER_EXEVFCK = fSHRTIMER_CK / 8 */ 1628 1629 /* fault input source */ 1630 #define SHRTIMER_FAULT_SOURCE_PIN ((uint32_t)0x00000000U) /*!< the source of fault input is chip external pin */ 1631 #define SHRTIMER_FAULT_SOURCE_INTERNAL (SHRTIMER_FLTINCFG0_FLT0INSRC) /*!< the source of fault input is chip internal signal(for example comparator) */ 1632 1633 /* fault input polarity */ 1634 #define SHRTIMER_FAULT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< fault 0 input active at low level */ 1635 #define SHRTIMER_FAULT_POLARITY_HIGH (SHRTIMER_FLTINCFG0_FLT0INP) /*!< fault 0 input active at high level */ 1636 1637 /* enable or disable fault */ 1638 #define SHRTIMER_FAULT_CHANNEL_DISABLE ((uint32_t)0x00000000U) /*!< fault channel disable */ 1639 #define SHRTIMER_FAULT_CHANNEL_ENABLE (SHRTIMER_FLTINCFG0_FLT0INEN) /*!< fault channel enable */ 1640 1641 /* protect fault input configuration */ 1642 #define SHRTIMER_FAULT_PROTECT_DISABLE ((uint32_t)0x00000000U) /*!< protect disable. FLT0INEN, FLT0INP, FLT0INSRC and FLT0INFC[3:0] is writable */ 1643 #define SHRTIMER_FAULT_PROTECT_ENABLE (SHRTIMER_FLTINCFG0_FLT0INPROT) /*!< protect enable. FLT0INEN, FLT0INP, FLT0INSRC and FLT0INFC[3:0] is read-only */ 1644 1645 /* fault input digital filter clock division */ 1646 #define SHRTIMER_FAULT_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< fSHRTIMER_FLTFCK = fSHRTIMER_CK */ 1647 #define SHRTIMER_FAULT_PRESCALER_DIV2 ((uint32_t)0x01000000U) /*!< fSHRTIMER_FLTFCK = fSHRTIMER_CK/2 */ 1648 #define SHRTIMER_FAULT_PRESCALER_DIV4 ((uint32_t)0x02000000U) /*!< fSHRTIMER_FLTFCK = fSHRTIMER_CK/4 */ 1649 #define SHRTIMER_FAULT_PRESCALER_DIV8 ((uint32_t)0x03000000U) /*!< fSHRTIMER_FLTFCK = fSHRTIMER_CK/8 */ 1650 1651 /* SHRTIMER_ADCTRIG update source */ 1652 #define SHRTIMER_ADCTRGI_UPDATE_MT ((uint32_t)0x00000000U) /*!< Master_TIMER update event */ 1653 #define SHRTIMER_ADCTRGI_UPDATE_ST0 ((uint32_t)0x00010000U) /*!< Slaver_TIMER0 update event */ 1654 #define SHRTIMER_ADCTRGI_UPDATE_ST1 ((uint32_t)0x00020000U) /*!< Slaver_TIMER1 update event */ 1655 #define SHRTIMER_ADCTRGI_UPDATE_ST2 ((uint32_t)0x00030000U) /*!< Slaver_TIMER2 update event */ 1656 #define SHRTIMER_ADCTRGI_UPDATE_ST3 ((uint32_t)0x00040000U) /*!< Slaver_TIMER3 update event */ 1657 #define SHRTIMER_ADCTRGI_UPDATE_ST4 ((uint32_t)0x00050000U) /*!< Slaver_TIMER4 update event */ 1658 1659 /* ADC trigger event */ 1660 #define SHRTIMER_ADCTRGI02_EVENT_NONE ((uint32_t)0x00000000U) /*!< no ADC trigger event */ 1661 #define SHRTIMER_ADCTRGI02_EVENT_MTCMP0 (SHRTIMER_ADCTRIGS0_TRG0MTC0) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Master_TIMER compare 0 */ 1662 #define SHRTIMER_ADCTRGI02_EVENT_MTCMP1 (SHRTIMER_ADCTRIGS0_TRG0MTC1) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Master_TIMER compare 1 */ 1663 #define SHRTIMER_ADCTRGI02_EVENT_MTCMP2 (SHRTIMER_ADCTRIGS0_TRG0MTC2) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Master_TIMER compare 2 */ 1664 #define SHRTIMER_ADCTRGI02_EVENT_MTCMP3 (SHRTIMER_ADCTRIGS0_TRG0MTC3) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Master_TIMER compare 3 */ 1665 #define SHRTIMER_ADCTRGI02_EVENT_MTPER (SHRTIMER_ADCTRIGS0_TRG0MTPER) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Master_TIMER period */ 1666 #define SHRTIMER_ADCTRGI02_EVENT_EXEV0 (SHRTIMER_ADCTRIGS0_TRG0EXEV0) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on external event 0 */ 1667 #define SHRTIMER_ADCTRGI02_EVENT_EXEV1 (SHRTIMER_ADCTRIGS0_TRG0EXEV1) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on external event 1 */ 1668 #define SHRTIMER_ADCTRGI02_EVENT_EXEV2 (SHRTIMER_ADCTRIGS0_TRG0EXEV2) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on external event 2 */ 1669 #define SHRTIMER_ADCTRGI02_EVENT_EXEV3 (SHRTIMER_ADCTRIGS0_TRG0EXEV3) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on external event 3 */ 1670 #define SHRTIMER_ADCTRGI02_EVENT_EXEV4 (SHRTIMER_ADCTRIGS0_TRG0EXEV4) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on external event 4 */ 1671 #define SHRTIMER_ADCTRGI02_EVENT_ST0CMP1 (SHRTIMER_ADCTRIGS0_TRG0ST0C1) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 1 */ 1672 #define SHRTIMER_ADCTRGI02_EVENT_ST0CMP2 (SHRTIMER_ADCTRIGS0_TRG0ST0C2) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 2 */ 1673 #define SHRTIMER_ADCTRGI02_EVENT_ST0CMP3 (SHRTIMER_ADCTRIGS0_TRG0ST0C3) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 3 */ 1674 #define SHRTIMER_ADCTRGI02_EVENT_ST0PER (SHRTIMER_ADCTRIGS0_TRG0ST0PER) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER0 period */ 1675 #define SHRTIMER_ADCTRGI02_EVENT_ST0RST (SHRTIMER_ADCTRIGS0_TRG0ST0RST) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER0 reset */ 1676 #define SHRTIMER_ADCTRGI02_EVENT_ST1CMP1 (SHRTIMER_ADCTRIGS0_TRG0ST1C1) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 1 */ 1677 #define SHRTIMER_ADCTRGI02_EVENT_ST1CMP2 (SHRTIMER_ADCTRIGS0_TRG0ST1C2) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 2 */ 1678 #define SHRTIMER_ADCTRGI02_EVENT_ST1CMP3 (SHRTIMER_ADCTRIGS0_TRG0ST1C3) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 3 */ 1679 #define SHRTIMER_ADCTRGI02_EVENT_ST1PER (SHRTIMER_ADCTRIGS0_TRG0ST1PER) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER1 period */ 1680 #define SHRTIMER_ADCTRGI02_EVENT_ST1RST (SHRTIMER_ADCTRIGS0_TRG0ST1RST) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER1 reset */ 1681 #define SHRTIMER_ADCTRGI02_EVENT_ST2CMP1 (SHRTIMER_ADCTRIGS0_TRG0ST2C1) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 1 */ 1682 #define SHRTIMER_ADCTRGI02_EVENT_ST2CMP2 (SHRTIMER_ADCTRIGS0_TRG0ST2C2) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 2 */ 1683 #define SHRTIMER_ADCTRGI02_EVENT_ST2CMP3 (SHRTIMER_ADCTRIGS0_TRG0ST2C3) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 3 */ 1684 #define SHRTIMER_ADCTRGI02_EVENT_ST2PER (SHRTIMER_ADCTRIGS0_TRG0ST2PER) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER2 period */ 1685 #define SHRTIMER_ADCTRGI02_EVENT_ST3CMP1 (SHRTIMER_ADCTRIGS0_TRG0ST3C1) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 1 */ 1686 #define SHRTIMER_ADCTRGI02_EVENT_ST3CMP2 (SHRTIMER_ADCTRIGS0_TRG0ST3C2) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 2 */ 1687 #define SHRTIMER_ADCTRGI02_EVENT_ST3CMP3 (SHRTIMER_ADCTRIGS0_TRG0ST3C3) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 3 */ 1688 #define SHRTIMER_ADCTRGI02_EVENT_ST3PER (SHRTIMER_ADCTRIGS0_TRG0ST3PER) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER3 period */ 1689 #define SHRTIMER_ADCTRGI02_EVENT_ST4CMP1 (SHRTIMER_ADCTRIGS0_TRG0ST4C1) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 1 */ 1690 #define SHRTIMER_ADCTRGI02_EVENT_ST4CMP2 (SHRTIMER_ADCTRIGS0_TRG0ST4C2) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 2 */ 1691 #define SHRTIMER_ADCTRGI02_EVENT_ST4CMP3 (SHRTIMER_ADCTRIGS0_TRG0ST4C3) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 3 */ 1692 #define SHRTIMER_ADCTRGI02_EVENT_ST4PER (SHRTIMER_ADCTRIGS0_TRG0ST4PER) /*!< SHRTIMER_ADCTRIG0 or SHRTIMER_ADCTRIG2 on Slave_TIMER4 period */ 1693 1694 #define SHRTIMER_ADCTRGI13_EVENT_NONE ((uint32_t)0x00000000U) /*!< no ADC trigger event */ 1695 #define SHRTIMER_ADCTRGI13_EVENT_MTCMP0 (SHRTIMER_ADCTRIGS1_TRG1MTC0) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Master_TIMER compare 0 */ 1696 #define SHRTIMER_ADCTRGI13_EVENT_MTCMP1 (SHRTIMER_ADCTRIGS1_TRG1MTC1) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Master_TIMER compare 1 */ 1697 #define SHRTIMER_ADCTRGI13_EVENT_MTCMP2 (SHRTIMER_ADCTRIGS1_TRG1MTC2) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Master_TIMER compare 2 */ 1698 #define SHRTIMER_ADCTRGI13_EVENT_MTCMP3 (SHRTIMER_ADCTRIGS1_TRG1MTC3) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Master_TIMER compare 3 */ 1699 #define SHRTIMER_ADCTRGI13_EVENT_MTPER (SHRTIMER_ADCTRIGS1_TRG1MTPER) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Master_TIMER period */ 1700 #define SHRTIMER_ADCTRGI13_EVENT_EXEV5 (SHRTIMER_ADCTRIGS1_TRG1EXEV5) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on external event 5 */ 1701 #define SHRTIMER_ADCTRGI13_EVENT_EXEV6 (SHRTIMER_ADCTRIGS1_TRG1EXEV6) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on external event 6 */ 1702 #define SHRTIMER_ADCTRGI13_EVENT_EXEV7 (SHRTIMER_ADCTRIGS1_TRG1EXEV7) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on external event 7 */ 1703 #define SHRTIMER_ADCTRGI13_EVENT_EXEV8 (SHRTIMER_ADCTRIGS1_TRG1EXEV8) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on external event 8 */ 1704 #define SHRTIMER_ADCTRGI13_EVENT_EXEV9 (SHRTIMER_ADCTRIGS1_TRG1EXEV9) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on external event 9 */ 1705 #define SHRTIMER_ADCTRGI13_EVENT_ST0CMP1 (SHRTIMER_ADCTRIGS1_TRG1ST0C1) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 1 */ 1706 #define SHRTIMER_ADCTRGI13_EVENT_ST0CMP2 (SHRTIMER_ADCTRIGS1_TRG1ST0C2) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 2 */ 1707 #define SHRTIMER_ADCTRGI13_EVENT_ST0CMP3 (SHRTIMER_ADCTRIGS1_TRG1ST0C3) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 3 */ 1708 #define SHRTIMER_ADCTRGI13_EVENT_ST0PER (SHRTIMER_ADCTRIGS1_TRG1ST0PER) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER0 period */ 1709 #define SHRTIMER_ADCTRGI13_EVENT_ST1CMP1 (SHRTIMER_ADCTRIGS1_TRG1ST1C1) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 1 */ 1710 #define SHRTIMER_ADCTRGI13_EVENT_ST1CMP2 (SHRTIMER_ADCTRIGS1_TRG1ST1C2) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 2 */ 1711 #define SHRTIMER_ADCTRGI13_EVENT_ST1CMP3 (SHRTIMER_ADCTRIGS1_TRG1ST1C3) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 3 */ 1712 #define SHRTIMER_ADCTRGI13_EVENT_ST1PER (SHRTIMER_ADCTRIGS1_TRG1ST1PER) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER1 period */ 1713 #define SHRTIMER_ADCTRGI13_EVENT_ST2CMP1 (SHRTIMER_ADCTRIGS1_TRG1ST2C1) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 1 */ 1714 #define SHRTIMER_ADCTRGI13_EVENT_ST2CMP2 (SHRTIMER_ADCTRIGS1_TRG1ST2C2) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 2 */ 1715 #define SHRTIMER_ADCTRGI13_EVENT_ST2CMP3 (SHRTIMER_ADCTRIGS1_TRG1ST2C3) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 3 */ 1716 #define SHRTIMER_ADCTRGI13_EVENT_ST2PER (SHRTIMER_ADCTRIGS1_TRG1ST2PER) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER2 period */ 1717 #define SHRTIMER_ADCTRGI13_EVENT_ST2RST (SHRTIMER_ADCTRIGS1_TRG1ST2RST) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER2 reset */ 1718 #define SHRTIMER_ADCTRGI13_EVENT_ST3CMP1 (SHRTIMER_ADCTRIGS1_TRG1ST3C1) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 1 */ 1719 #define SHRTIMER_ADCTRGI13_EVENT_ST3CMP2 (SHRTIMER_ADCTRIGS1_TRG1ST3C2) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 2 */ 1720 #define SHRTIMER_ADCTRGI13_EVENT_ST3CMP3 (SHRTIMER_ADCTRIGS1_TRG1ST3C3) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 3 */ 1721 #define SHRTIMER_ADCTRGI13_EVENT_ST3PER (SHRTIMER_ADCTRIGS1_TRG1ST3PER) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER3 period */ 1722 #define SHRTIMER_ADCTRGI13_EVENT_ST3RST (SHRTIMER_ADCTRIGS1_TRG1ST3RST) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER3 reset */ 1723 #define SHRTIMER_ADCTRGI13_EVENT_ST4CMP1 (SHRTIMER_ADCTRIGS1_TRG1ST4C1) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 1 */ 1724 #define SHRTIMER_ADCTRGI13_EVENT_ST4CMP2 (SHRTIMER_ADCTRIGS1_TRG1ST4C2) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 2 */ 1725 #define SHRTIMER_ADCTRGI13_EVENT_ST4CMP3 (SHRTIMER_ADCTRIGS1_TRG1ST4C3) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 3 */ 1726 #define SHRTIMER_ADCTRGI13_EVENT_ST4RST (SHRTIMER_ADCTRIGS1_TRG1ST4RST) /*!< SHRTIMER_ADCTRIG1 or SHRTIMER_ADCTRIG3 on Slave_TIMER4 reset */ 1727 1728 /* DLL calibration control */ 1729 #define SHRTIMER_CALIBRATION_ONCE ((uint32_t)0x88888888U) /*!< DLL calibration start once */ 1730 #define SHRTIMER_CALIBRATION_1048576_PERIOD ((uint32_t)0x00000000U) /*!< 1048576 * tSHRTIMER_CK */ 1731 #define SHRTIMER_CALIBRATION_131072_PERIOD ((uint32_t)0x00000004U) /*!< 131072 * tSHRTIMER_CK */ 1732 #define SHRTIMER_CALIBRATION_16384_PERIOD ((uint32_t)0x00000008U) /*!< 16384 * tSHRTIMER_CK */ 1733 #define SHRTIMER_CALIBRATIO_2048_PERIOD ((uint32_t)0x0000000CU) /*!< 2048 * tSHRTIMER_CK */ 1734 1735 /* Master_TIMER and Slave_TIMER interrupt enable or disable */ 1736 #define SHRTIMER_MT_ST_INT_CMP0 SHRTIMER_STXDMAINTEN_CMP0IE /*!< compare 0 interrupt */ 1737 #define SHRTIMER_MT_ST_INT_CMP1 SHRTIMER_STXDMAINTEN_CMP1IE /*!< compare 1 interrupt */ 1738 #define SHRTIMER_MT_ST_INT_CMP2 SHRTIMER_STXDMAINTEN_CMP2IE /*!< compare 2 interrupt */ 1739 #define SHRTIMER_MT_ST_INT_CMP3 SHRTIMER_STXDMAINTEN_CMP3IE /*!< compare 3 interrupt */ 1740 #define SHRTIMER_MT_ST_INT_REP SHRTIMER_STXDMAINTEN_REPIE /*!< repetition interrupt */ 1741 #define SHRTIMER_MT_INT_SYNI SHRTIMER_MTDMAINTEN_SYNIIE /*!< synchronization input interrupt */ 1742 #define SHRTIMER_MT_ST_INT_UPD SHRTIMER_STXDMAINTEN_UPIE /*!< update interrupt */ 1743 #define SHRTIMER_ST_INT_CAP0 SHRTIMER_STXDMAINTEN_CAP0IE /*!< capture 0 interrupt */ 1744 #define SHRTIMER_ST_INT_CAP1 SHRTIMER_STXDMAINTEN_CAP1IE /*!< capture 1 interrupt */ 1745 #define SHRTIMER_ST_INT_CH0OA SHRTIMER_STXDMAINTEN_CH0OAIE /*!< channel 0 output active interrupt */ 1746 #define SHRTIMER_ST_INT_CH0ONA SHRTIMER_STXDMAINTEN_CH0ONAIE /*!< channel 0 output inactive interrupt */ 1747 #define SHRTIMER_ST_INT_CH1OA SHRTIMER_STXDMAINTEN_CH1OAIE /*!< channel 1 output active interrupt */ 1748 #define SHRTIMER_ST_INT_CH1ONA SHRTIMER_STXDMAINTEN_CH1ONAIE /*!< channel 1 output inactive interrupt */ 1749 #define SHRTIMER_ST_INT_CNTRST SHRTIMER_STXDMAINTEN_RSTIE /*!< counter reset interrupt */ 1750 #define SHRTIMER_ST_INT_DLYIDLE SHRTIMER_STXDMAINTEN_DLYIIE /*!< delayed IDLE mode entry interrupt */ 1751 1752 /* SHRTIMER common interrupt */ 1753 #define SHRTIMER_INT_SYSFLT SHRTIMER_INTEN_SYSFLTIE /*!< system fault interrupt */ 1754 #define SHRTIMER_INT_DLLCAL SHRTIMER_INTEN_DLLCALIE /*!< DLL calibration completed interrupt */ 1755 #define SHRTIMER_INT_BMPER SHRTIMER_INTEN_BMPERIE /*!< bunch mode period interrupt */ 1756 1757 /* Master_TIMER and Slave_TIMER interrupt flag */ 1758 #define SHRTIMER_MT_ST_INT_FLAG_CMP0 SHRTIMER_STXINTF_CMP0IF /*!< compare 0 interrupt flag */ 1759 #define SHRTIMER_MT_ST_INT_FLAG_CMP1 SHRTIMER_STXINTF_CMP1IF /*!< compare 1 interrupt flag */ 1760 #define SHRTIMER_MT_ST_INT_FLAG_CMP2 SHRTIMER_STXINTF_CMP2IF /*!< compare 2 interrupt flag */ 1761 #define SHRTIMER_MT_ST_INT_FLAG_CMP3 SHRTIMER_STXINTF_CMP3IF /*!< compare 3 interrupt flag */ 1762 #define SHRTIMER_MT_ST_INT_FLAG_REP SHRTIMER_STXINTF_REPIF /*!< repetition interrupt flag */ 1763 #define SHRTIMER_MT_INT_FLAG_SYNI SHRTIMER_MTINTF_SYNIIF /*!< synchronization input interrupt flag */ 1764 #define SHRTIMER_MT_ST_INT_FLAG_UPD SHRTIMER_STXINTF_UPIF /*!< update interrupt flag */ 1765 #define SHRTIMER_ST_INT_FLAG_CAP0 SHRTIMER_STXINTF_CAP0IF /*!< capture 0 interrupt flag */ 1766 #define SHRTIMER_ST_INT_FLAG_CAP1 SHRTIMER_STXINTF_CAP1IF /*!< capture 1 interrupt flag */ 1767 #define SHRTIMER_ST_INT_FLAG_CH0OA SHRTIMER_STXINTF_CH0OAIF /*!< channel 0 output active interrupt flag */ 1768 #define SHRTIMER_ST_INT_FLAG_CH0ONA SHRTIMER_STXINTF_CH0ONAIF /*!< channel 0 output inactive interrupt flag */ 1769 #define SHRTIMER_ST_INT_FLAG_CH1OA SHRTIMER_STXINTF_CH1OAIF /*!< channel 1 output active interrupt flag */ 1770 #define SHRTIMER_ST_INT_FLAG_CH1ONA SHRTIMER_STXINTF_CH1ONAIF /*!< channel 1 output inactive interrupt flag */ 1771 #define SHRTIMER_ST_INT_FLAG_CNTRST SHRTIMER_STXINTF_RSTIF /*!< counter reset interrupt flag */ 1772 #define SHRTIMER_ST_INT_FLAG_DLYIDLE SHRTIMER_STXINTF_DLYIIF /*!< delayed IDLE mode entry interrupt flag */ 1773 1774 /* SHRTIMER common interrupt flag */ 1775 #define SHRTIMER_INT_FLAG_FLT0 SHRTIMER_INTF_FLT0IF /*!< fault 0 interrupt flag */ 1776 #define SHRTIMER_INT_FLAG_FLT1 SHRTIMER_INTF_FLT1IF /*!< fault 1 interrupt flag */ 1777 #define SHRTIMER_INT_FLAG_FLT2 SHRTIMER_INTF_FLT2IF /*!< fault 2 interrupt flag */ 1778 #define SHRTIMER_INT_FLAG_FLT3 SHRTIMER_INTF_FLT3IF /*!< fault 3 interrupt flag */ 1779 #define SHRTIMER_INT_FLAG_FLT4 SHRTIMER_INTF_FLT4IF /*!< fault 4 interrupt flag */ 1780 #define SHRTIMER_INT_FLAG_SYSFLT SHRTIMER_INTF_SYSFLTIF /*!< system fault interrupt flag */ 1781 #define SHRTIMER_INT_FLAG_DLLCAL SHRTIMER_INTF_DLLCALIF /*!< DLL calibration completed interrupt flag */ 1782 #define SHRTIMER_INT_FLAG_BMPER SHRTIMER_INTF_BMPERIF /*!< bunch mode period interrupt flag */ 1783 1784 /* Master_TIMER and Slave_TIMER flag */ 1785 #define SHRTIMER_MT_ST_FLAG_CMP0 SHRTIMER_STXINTF_CMP0IF /*!< compare 0 flag */ 1786 #define SHRTIMER_MT_ST_FLAG_CMP1 SHRTIMER_STXINTF_CMP1IF /*!< compare 1 flag */ 1787 #define SHRTIMER_MT_ST_FLAG_CMP2 SHRTIMER_STXINTF_CMP2IF /*!< compare 2 flag */ 1788 #define SHRTIMER_MT_ST_FLAG_CMP3 SHRTIMER_STXINTF_CMP3IF /*!< compare 3 flag */ 1789 #define SHRTIMER_MT_ST_FLAG_REP SHRTIMER_STXINTF_REPIF /*!< repetition flag */ 1790 #define SHRTIMER_MT_FLAG_SYNI SHRTIMER_MTINTF_SYNIIF /*!< synchronization input flag */ 1791 #define SHRTIMER_MT_ST_FLAG_UPD SHRTIMER_STXINTF_UPIF /*!< update flag */ 1792 #define SHRTIMER_ST_FLAG_CAP0 SHRTIMER_STXINTF_CAP0IF /*!< capture 0 flag */ 1793 #define SHRTIMER_ST_FLAG_CAP1 SHRTIMER_STXINTF_CAP1IF /*!< capture 1 flag */ 1794 #define SHRTIMER_ST_FLAG_CH0OA SHRTIMER_STXINTF_CH0OAIF /*!< channel 0 output active flag */ 1795 #define SHRTIMER_ST_FLAG_CH0ONA SHRTIMER_STXINTF_CH0ONAIF /*!< channel 0 output inactive flag */ 1796 #define SHRTIMER_ST_FLAG_CH1OA SHRTIMER_STXINTF_CH1OAIF /*!< channel 1 output active flag */ 1797 #define SHRTIMER_ST_FLAG_CH1ONA SHRTIMER_STXINTF_CH1ONAIF /*!< channel 1 output inactive flag */ 1798 #define SHRTIMER_ST_FLAG_CNTRST SHRTIMER_STXINTF_RSTIF /*!< counter reset flag */ 1799 #define SHRTIMER_ST_FLAG_DLYIDLE SHRTIMER_STXINTF_DLYIIF /*!< delayed IDLE mode entry flag */ 1800 #define SHRTIMER_ST_FLAG_CBLN SHRTIMER_STXINTF_CBLNF /*!< current balanced flag */ 1801 #define SHRTIMER_ST_FLAG_BLNIDLE SHRTIMER_STXINTF_BLNIF /*!< balanced IDLE flag */ 1802 #define SHRTIMER_ST_FLAG_CH0OUT SHRTIMER_STXINTF_CH0F /*!< channel 0 output flag */ 1803 #define SHRTIMER_ST_FLAG_CH1OUT SHRTIMER_STXINTF_CH1F /*!< channel 1 output flag */ 1804 1805 /* SHRTIMER common flag */ 1806 #define SHRTIMER_FLAG_FLT0 SHRTIMER_INTF_FLT0IF /*!< fault 0 flag */ 1807 #define SHRTIMER_FLAG_FLT1 SHRTIMER_INTF_FLT1IF /*!< fault 1 flag */ 1808 #define SHRTIMER_FLAG_FLT2 SHRTIMER_INTF_FLT2IF /*!< fault 2 flag */ 1809 #define SHRTIMER_FLAG_FLT3 SHRTIMER_INTF_FLT3IF /*!< fault 3 flag */ 1810 #define SHRTIMER_FLAG_FLT4 SHRTIMER_INTF_FLT4IF /*!< fault 4 flag */ 1811 #define SHRTIMER_FLAG_SYSFLT SHRTIMER_INTF_SYSFLTIF /*!< system fault flag */ 1812 #define SHRTIMER_FLAG_DLLCAL SHRTIMER_INTF_DLLCALIF /*!< DLL calibration completed flag */ 1813 #define SHRTIMER_FLAG_BMPER SHRTIMER_INTF_BMPERIF /*!< bunch mode period flag */ 1814 1815 /* Master_TIMER and Slave_TIMER DMA request */ 1816 #define SHRTIMER_MT_ST_DMA_CMP0 SHRTIMER_STXDMAINTEN_CMP0DEN /*!< compare 0 DMA request */ 1817 #define SHRTIMER_MT_ST_DMA_CMP1 SHRTIMER_STXDMAINTEN_CMP1DEN /*!< compare 1 DMA request */ 1818 #define SHRTIMER_MT_ST_DMA_CMP2 SHRTIMER_STXDMAINTEN_CMP2DEN /*!< compare 2 DMA request */ 1819 #define SHRTIMER_MT_ST_DMA_CMP3 SHRTIMER_STXDMAINTEN_CMP3DEN /*!< compare 3 DMA request */ 1820 #define SHRTIMER_MT_ST_DMA_REP SHRTIMER_STXDMAINTEN_REPDEN /*!< repetition DMA request */ 1821 #define SHRTIMER_MT_DMA_SYNID SHRTIMER_MTDMAINTEN_SYNIDEN /*!< synchronization input DMA request */ 1822 #define SHRTIMER_MT_ST_DMA_UPD SHRTIMER_STXDMAINTEN_UPDEN /*!< update DMA request */ 1823 #define SHRTIMER_ST_DMA_CAP0 SHRTIMER_STXDMAINTEN_CAP0DEN /*!< capture 0 DMA request */ 1824 #define SHRTIMER_ST_DMA_CAP1 SHRTIMER_STXDMAINTEN_CAP1DEN /*!< capture 1 DMA request */ 1825 #define SHRTIMER_ST_DMA_CH0OA SHRTIMER_STXDMAINTEN_CH0OADEN /*!< channel 0 output active DMA request */ 1826 #define SHRTIMER_ST_DMA_CH0ONA SHRTIMER_STXDMAINTEN_CH0ONADEN /*!< channel 0 output inactive DMA request */ 1827 #define SHRTIMER_ST_DMA_CH1OA SHRTIMER_STXDMAINTEN_CH1OADEN /*!< channel 1 output active DMA request */ 1828 #define SHRTIMER_ST_DMA_CH1ONA SHRTIMER_STXDMAINTEN_CH1ONADEN /*!< channel 1 output inactive DMA request */ 1829 #define SHRTIMER_ST_DMA_CNTRST SHRTIMER_STXDMAINTEN_RSTDEN /*!< counter reset DMA request */ 1830 #define SHRTIMER_ST_DMA_DLYIDLE SHRTIMER_STXDMAINTEN_DLYIDEN /*!< delay IDLE DMA request */ 1831 1832 /* Master_TIMER or Slave_TIMER update by software */ 1833 #define SHRTIMER_UPDATE_SW_MT (SHRTIMER_CTL1_MTSUP) /*!< Master_TIMER software update */ 1834 #define SHRTIMER_UPDATE_SW_ST0 (SHRTIMER_CTL1_ST0SUP) /*!< Slave_TIMER0 software update */ 1835 #define SHRTIMER_UPDATE_SW_ST1 (SHRTIMER_CTL1_ST1SUP) /*!< Slave_TIMER1 software update */ 1836 #define SHRTIMER_UPDATE_SW_ST2 (SHRTIMER_CTL1_ST2SUP) /*!< Slave_TIMER2 software update */ 1837 #define SHRTIMER_UPDATE_SW_ST3 (SHRTIMER_CTL1_ST3SUP) /*!< Slave_TIMER3 software update */ 1838 #define SHRTIMER_UPDATE_SW_ST4 (SHRTIMER_CTL1_ST4SUP) /*!< Slave_TIMER4 software update */ 1839 1840 /* Master_TIMER or Slave_TIMER counter reset by software */ 1841 #define SHRTIMER_COUNTER_RESET_SW_MT (SHRTIMER_CTL1_MTSRST) /*!< Master_TIMER software reset */ 1842 #define SHRTIMER_COUNTER_RESET_SW_ST0 (SHRTIMER_CTL1_ST0SRST) /*!< Slave_TIMER0 software reset */ 1843 #define SHRTIMER_COUNTER_RESET_SW_ST1 (SHRTIMER_CTL1_ST1SRST) /*!< Slave_TIMER1 software reset */ 1844 #define SHRTIMER_COUNTER_RESET_SW_ST2 (SHRTIMER_CTL1_ST2SRST) /*!< Slave_TIMER2 software reset */ 1845 #define SHRTIMER_COUNTER_RESET_SW_ST3 (SHRTIMER_CTL1_ST3SRST) /*!< Slave_TIMER3 software reset */ 1846 #define SHRTIMER_COUNTER_RESET_SW_ST4 (SHRTIMER_CTL1_ST4SRST) /*!< Slave_TIMER4 software reset */ 1847 1848 /* channel output polarity */ 1849 #define SHRTIMER_CHANNEL_POLARITY_HIGH ((uint32_t)0x00000000U) /*!< channel active high */ 1850 #define SHRTIMER_CHANNEL_POLARITY_LOW (SHRTIMER_STXCHOCTL_CH0P) /*!< channel active low */ 1851 1852 /* channel set request */ 1853 #define SHRTIMER_CHANNEL_SET_NONE ((uint32_t)0x00000000U) /*!< clear all channel ��set request�� */ 1854 #define SHRTIMER_CHANNEL_SET_RSTSYNI (SHRTIMER_STXCH0SET_CH0SRST) /*!< Slave_TIMERx reset event from synchronous input and software can generate channel ��set request�� */ 1855 #define SHRTIMER_CHANNEL_SET_PER (SHRTIMER_STXCH0SET_CH0SPER) /*!< Slave_TIMERx period event can generate ��set request�� */ 1856 #define SHRTIMER_CHANNEL_SET_CMP0 (SHRTIMER_STXCH0SET_CH0SCMP0) /*!< Slave_TIMERx compare 0 event can generate ��set request�� */ 1857 #define SHRTIMER_CHANNEL_SET_CMP1 (SHRTIMER_STXCH0SET_CH0SCMP1) /*!< Slave_TIMERx compare 1 event can generate ��set request�� */ 1858 #define SHRTIMER_CHANNEL_SET_CMP2 (SHRTIMER_STXCH0SET_CH0SCMP2) /*!< Slave_TIMERx compare 2 event can generate ��set request�� */ 1859 #define SHRTIMER_CHANNEL_SET_CMP3 (SHRTIMER_STXCH0SET_CH0SCMP3) /*!< Slave_TIMERx compare 3 event can generate ��set request�� */ 1860 #define SHRTIMER_CHANNEL_SET_MTPER (SHRTIMER_STXCH0SET_CH0SMTPER) /*!< Master_TIMER period event generates channel ��set request�� */ 1861 #define SHRTIMER_CHANNEL_SET_MTCMP0 (SHRTIMER_STXCH0SET_CH0SMTCMP0) /*!< Master_TIMER compare 0 event generates channel ��set request�� */ 1862 #define SHRTIMER_CHANNEL_SET_MTCMP1 (SHRTIMER_STXCH0SET_CH0SMTCMP1) /*!< Master_TIMER compare 1 event generates channel ��set request�� */ 1863 #define SHRTIMER_CHANNEL_SET_MTCMP2 (SHRTIMER_STXCH0SET_CH0SMTCMP2) /*!< Master_TIMER compare 2 event generates channel ��set request�� */ 1864 #define SHRTIMER_CHANNEL_SET_MTCMP3 (SHRTIMER_STXCH0SET_CH0SMTCMP3) /*!< Master_TIMER compare 3 event generates channel ��set request�� */ 1865 #define SHRTIMER_CHANNEL_SET_STEV0 (SHRTIMER_STXCH0SET_CH0SSTEV0) /*!< Slave_TIMERx interconnection event 0 generates channel ��set request�� */ 1866 #define SHRTIMER_CHANNEL_SET_STEV1 (SHRTIMER_STXCH0SET_CH0SSTEV1) /*!< Slave_TIMERx interconnection event 1 generates channel ��set request�� */ 1867 #define SHRTIMER_CHANNEL_SET_STEV2 (SHRTIMER_STXCH0SET_CH0SSTEV2) /*!< Slave_TIMERx interconnection event 2 generates channel ��set request�� */ 1868 #define SHRTIMER_CHANNEL_SET_STEV3 (SHRTIMER_STXCH0SET_CH0SSTEV3) /*!< Slave_TIMERx interconnection event 3 generates channel ��set request�� */ 1869 #define SHRTIMER_CHANNEL_SET_STEV4 (SHRTIMER_STXCH0SET_CH0SSTEV4) /*!< Slave_TIMERx interconnection event 4 generates channel ��set request�� */ 1870 #define SHRTIMER_CHANNEL_SET_STEV5 (SHRTIMER_STXCH0SET_CH0SSTEV5) /*!< Slave_TIMERx interconnection event 5 generates channel ��set request�� */ 1871 #define SHRTIMER_CHANNEL_SET_STEV6 (SHRTIMER_STXCH0SET_CH0SSTEV6) /*!< Slave_TIMERx interconnection event 6 generates channel ��set request�� */ 1872 #define SHRTIMER_CHANNEL_SET_STEV7 (SHRTIMER_STXCH0SET_CH0SSTEV7) /*!< Slave_TIMERx interconnection event 7 generates channel ��set request�� */ 1873 #define SHRTIMER_CHANNEL_SET_STEV8 (SHRTIMER_STXCH0SET_CH0SSTEV8) /*!< Slave_TIMERx interconnection event 8 generates channel ��set request�� */ 1874 #define SHRTIMER_CHANNEL_SET_EXEV0 (SHRTIMER_STXCH0SET_CH0SEXEV0) /*!< external event 0 generates channel ��set request�� */ 1875 #define SHRTIMER_CHANNEL_SET_EXEV1 (SHRTIMER_STXCH0SET_CH0SEXEV1) /*!< external event 1 generates channel ��set request�� */ 1876 #define SHRTIMER_CHANNEL_SET_EXEV2 (SHRTIMER_STXCH0SET_CH0SEXEV2) /*!< external event 2 generates channel ��set request�� */ 1877 #define SHRTIMER_CHANNEL_SET_EXEV3 (SHRTIMER_STXCH0SET_CH0SEXEV3) /*!< external event 3 generates channel ��set request�� */ 1878 #define SHRTIMER_CHANNEL_SET_EXEV4 (SHRTIMER_STXCH0SET_CH0SEXEV4) /*!< external event 4 generates channel ��set request�� */ 1879 #define SHRTIMER_CHANNEL_SET_EXEV5 (SHRTIMER_STXCH0SET_CH0SEXEV5) /*!< external event 5 generates channel ��set request�� */ 1880 #define SHRTIMER_CHANNEL_SET_EXEV6 (SHRTIMER_STXCH0SET_CH0SEXEV6) /*!< external event 6 generates channel ��set request�� */ 1881 #define SHRTIMER_CHANNEL_SET_EXEV7 (SHRTIMER_STXCH0SET_CH0SEXEV7) /*!< external event 7 generates channel ��set request�� */ 1882 #define SHRTIMER_CHANNEL_SET_EXEV8 (SHRTIMER_STXCH0SET_CH0SEXEV8) /*!< external event 8 generates channel ��set request�� */ 1883 #define SHRTIMER_CHANNEL_SET_EXEV9 (SHRTIMER_STXCH0SET_CH0SEXEV9) /*!< external event 9 generates channel ��set request�� */ 1884 #define SHRTIMER_CHANNEL_SET_UPDATE (SHRTIMER_STXCH0SET_CH0SUP) /*!< update event generates channel ��set request�� */ 1885 1886 /* channel reset request */ 1887 #define SHRTIMER_CHANNEL_RESET_NONE ((uint32_t)0x00000000U) /*!< clear all channel ��reset request�� */ 1888 #define SHRTIMER_CHANNEL_RESET_RSTSYNI (SHRTIMER_STXCH0RST_CH0RSRST) /*!< Slave_TIMERx reset event from synchronous input and software can generate channel ��reset request�� */ 1889 #define SHRTIMER_CHANNEL_RESET_PER (SHRTIMER_STXCH0RST_CH0RSPER) /*!< Slave_TIMERx period event can generate ��reset request�� */ 1890 #define SHRTIMER_CHANNEL_RESET_CMP0 (SHRTIMER_STXCH0RST_CH0RSCMP0) /*!< Slave_TIMERx compare 0 event can generate ��reset request�� */ 1891 #define SHRTIMER_CHANNEL_RESET_CMP1 (SHRTIMER_STXCH0RST_CH0RSCMP1) /*!< Slave_TIMERx compare 1 event can generate ��reset request�� */ 1892 #define SHRTIMER_CHANNEL_RESET_CMP2 (SHRTIMER_STXCH0RST_CH0RSCMP2) /*!< Slave_TIMERx compare 2 event can generate ��reset request�� */ 1893 #define SHRTIMER_CHANNEL_RESET_CMP3 (SHRTIMER_STXCH0RST_CH0RSCMP3) /*!< Slave_TIMERx compare 3 event can generate ��reset request�� */ 1894 #define SHRTIMER_CHANNEL_RESET_MTPER (SHRTIMER_STXCH0RST_CH0RSMTPER) /*!< Master_TIMER period event generates channel ��reset request�� */ 1895 #define SHRTIMER_CHANNEL_RESET_MTCMP0 (SHRTIMER_STXCH0RST_CH0RSMTCMP0) /*!< Master_TIMER compare 0 event generates channel ��reset request�� */ 1896 #define SHRTIMER_CHANNEL_RESET_MTCMP1 (SHRTIMER_STXCH0RST_CH0RSMTCMP1) /*!< Master_TIMER compare 1 event generates channel ��reset request�� */ 1897 #define SHRTIMER_CHANNEL_RESET_MTCMP2 (SHRTIMER_STXCH0RST_CH0RSMTCMP2) /*!< Master_TIMER compare 2 event generates channel ��reset request�� */ 1898 #define SHRTIMER_CHANNEL_RESET_MTCMP3 (SHRTIMER_STXCH0RST_CH0RSMTCMP3) /*!< Master_TIMER compare 3 event generates channel ��reset request�� */ 1899 #define SHRTIMER_CHANNEL_RESET_STEV0 (SHRTIMER_STXCH0RST_CH0RSSTEV0) /*!< Slave_TIMERx interconnection event 0 generates channel ��reset request�� */ 1900 #define SHRTIMER_CHANNEL_RESET_STEV1 (SHRTIMER_STXCH0RST_CH0RSSTEV1) /*!< Slave_TIMERx interconnection event 1 generates channel ��reset request�� */ 1901 #define SHRTIMER_CHANNEL_RESET_STEV2 (SHRTIMER_STXCH0RST_CH0RSSTEV2) /*!< Slave_TIMERx interconnection event 2 generates channel ��reset request�� */ 1902 #define SHRTIMER_CHANNEL_RESET_STEV3 (SHRTIMER_STXCH0RST_CH0RSSTEV3) /*!< Slave_TIMERx interconnection event 3 generates channel ��reset request�� */ 1903 #define SHRTIMER_CHANNEL_RESET_STEV4 (SHRTIMER_STXCH0RST_CH0RSSTEV4) /*!< Slave_TIMERx interconnection event 4 generates channel ��reset request�� */ 1904 #define SHRTIMER_CHANNEL_RESET_STEV5 (SHRTIMER_STXCH0RST_CH0RSSTEV5) /*!< Slave_TIMERx interconnection event 5 generates channel ��reset request�� */ 1905 #define SHRTIMER_CHANNEL_RESET_STEV6 (SHRTIMER_STXCH0RST_CH0RSSTEV6) /*!< Slave_TIMERx interconnection event 6 generates channel ��reset request�� */ 1906 #define SHRTIMER_CHANNEL_RESET_STEV7 (SHRTIMER_STXCH0RST_CH0RSSTEV7) /*!< Slave_TIMERx interconnection event 7 generates channel ��reset request�� */ 1907 #define SHRTIMER_CHANNEL_RESET_STEV8 (SHRTIMER_STXCH0RST_CH0RSSTEV8) /*!< Slave_TIMERx interconnection event 8 generates channel ��reset request�� */ 1908 #define SHRTIMER_CHANNEL_RESET_EXEV0 (SHRTIMER_STXCH0RST_CH0RSEXEV0) /*!< external event 0 generates channel ��reset request�� */ 1909 #define SHRTIMER_CHANNEL_RESET_EXEV1 (SHRTIMER_STXCH0RST_CH0RSEXEV1) /*!< external event 1 generates channel ��reset request�� */ 1910 #define SHRTIMER_CHANNEL_RESET_EXEV2 (SHRTIMER_STXCH0RST_CH0RSEXEV2) /*!< external event 2 generates channel ��reset request�� */ 1911 #define SHRTIMER_CHANNEL_RESET_EXEV3 (SHRTIMER_STXCH0RST_CH0RSEXEV3) /*!< external event 3 generates channel ��reset request�� */ 1912 #define SHRTIMER_CHANNEL_RESET_EXEV4 (SHRTIMER_STXCH0RST_CH0RSEXEV4) /*!< external event 4 generates channel ��reset request�� */ 1913 #define SHRTIMER_CHANNEL_RESET_EXEV5 (SHRTIMER_STXCH0RST_CH0RSEXEV5) /*!< external event 5 generates channel ��reset request�� */ 1914 #define SHRTIMER_CHANNEL_RESET_EXEV6 (SHRTIMER_STXCH0RST_CH0RSEXEV6) /*!< external event 6 generates channel ��reset request�� */ 1915 #define SHRTIMER_CHANNEL_RESET_EXEV7 (SHRTIMER_STXCH0RST_CH0RSEXEV7) /*!< external event 7 generates channel ��reset request�� */ 1916 #define SHRTIMER_CHANNEL_RESET_EXEV8 (SHRTIMER_STXCH0RST_CH0RSEXEV8) /*!< external event 8 generates channel ��reset request�� */ 1917 #define SHRTIMER_CHANNEL_RESET_EXEV9 (SHRTIMER_STXCH0RST_CH0RSEXEV9) /*!< external event 9 generates channel ��reset request�� */ 1918 #define SHRTIMER_CHANNEL_RESET_UPDATE (SHRTIMER_STXCH0RST_CH0RSUP) /*!< update event generates channel ��reset request�� */ 1919 1920 /* channel IDLE state enable in bunch mode */ 1921 #define SHRTIMER_CHANNEL_BUNCH_IDLE_DISABLE ((uint32_t)0x00000000U) /*!< channel output is not affected by the bunch mode */ 1922 #define SHRTIMER_CHANNEL_BUNCH_IDLE_ENABLE (SHRTIMER_STXCHOCTL_BMCH0IEN) /*!< channel output can be IDLE state in bunch mode */ 1923 1924 /* channel output idle state */ 1925 #define SHRTIMER_CHANNEL_IDLESTATE_INACTIVE ((uint32_t)0x00000000U) /*!< channel idle state output is inactive */ 1926 #define SHRTIMER_CHANNEL_IDLESTATE_ACTIVE (SHRTIMER_STXCHOCTL_ISO0) /*!< channel idle state output is active */ 1927 1928 /* channel output in fault state */ 1929 #define SHRTIMER_CHANNEL_FAULTSTATE_NONE ((uint32_t)0x00000000U) /*!< no effect. the output is normally in Run mode when a fault event happened */ 1930 #define SHRTIMER_CHANNEL_FAULTSTATE_ACTIVE ((uint32_t)0x00000010U) /*!< output is active level when in FAULT state */ 1931 #define SHRTIMER_CHANNEL_FAULTSTATE_INACTIVE ((uint32_t)0x00000020U) /*!< output is inactive level when in FAULT state */ 1932 #define SHRTIMER_CHANNEL_FAULTSTATE_HIGHZ ((uint32_t)0x00000030U) /*!< output is Hi-Z when in FAULT state */ 1933 1934 /* channel carrier-signal mode enable */ 1935 #define SHRTIMER_CHANNEL_CARRIER_DISABLED ((uint32_t)0x00000000U) /*!< the output is not affected by the fault input */ 1936 #define SHRTIMER_CHANNEL_CARRIER_ENABLED (SHRTIMER_STXCHOCTL_CH0CSEN) /*!< output at active level when in FAULT state */ 1937 1938 /* channel dead-time insert in bunch mode */ 1939 #define SHRTIMER_CHANNEL_BUNCH_ENTRY_REGULAR ((uint32_t)0x00000000U) /*!< the output enter IDLE immediately */ 1940 #define SHRTIMER_CHANNEL_BUNCH_ENTRY_DEADTIME ((uint32_t)0x00000080U) /*!< dead-time is inserted before entering the IDLE state */ 1941 1942 /* software event generates channel ��set request�� or ��reset request�� */ 1943 #define SHRTIMER_CHANNEL_SOFTWARE_SET ((uint32_t)0x00000001U) /*!< software event cannot generate request */ 1944 #define SHRTIMER_CHANNEL_SOFTWARE_RESET ((uint32_t)0x00000002U) /*!< software event can generate request */ 1945 1946 /* channel output level */ 1947 #define SHRTIMER_CHANNEL_OUTPUT_ACTIVE ((uint32_t)0x00000001U) /*!< channel outputs active level */ 1948 #define SHRTIMER_CHANNEL_OUTPUT_INACTIVE ((uint32_t)0x00000002U) /*!< channel outputs inactive leve */ 1949 1950 /* channel run state */ 1951 #define SHRTIMER_CHANNEL_STATE_IDLE ((uint32_t)0x00000001U) /*!< Run state: the channel output can take the active or inactive level as programmed in the crossbar unit */ 1952 #define SHRTIMER_CHANNEL_STATE_RUN ((uint32_t)0x00000002U) /*!< Idle state: after an SHRTIMER reset, when the outputs are disabled by software or during a bunch mode operation */ 1953 #define SHRTIMER_CHANNEL_STATE_FAULT ((uint32_t)0x00000003U) /*!< Fault state: when a fault happen */ 1954 1955 /* bunch mode operating flag */ 1956 #define SHRTIMER_BUNCHMODE_OPERATION_OFF ((uint32_t)0x00000000U) /*!< normal operation. bunch mode is not operation */ 1957 #define SHRTIMER_BUNCHMODE_OPERATION_ON ((uint32_t)0x80000000U) /*!< bunch mode operation on-going. */ 1958 1959 /* function declarations */ 1960 /* SHRTIMER timebase configure functions */ 1961 /* deinit a SHRTIMER */ 1962 void shrtimer_deinit(uint32_t shrtimer_periph); 1963 /* configure and start DLL calibration */ 1964 void shrtimer_dll_calibration_start(uint32_t shrtimer_periph, uint32_t calform); 1965 /* initialize SHRTIMER SHRTIMER time base parameters struct with a default value */ 1966 void shrtimer_baseinit_struct_para_init(shrtimer_baseinit_parameter_struct* baseinit); 1967 /* initialize Master_TIMER and Slave_TIMER timerbase */ 1968 void shrtimer_timers_base_init(uint32_t shrtimer_periph, uint32_t timer_id, shrtimer_baseinit_parameter_struct* baseinit); 1969 /* enable a counter */ 1970 void shrtimer_timers_counter_enable(uint32_t shrtimer_periph, uint32_t cntid); 1971 /* disable a counter */ 1972 void shrtimer_timers_counter_disable(uint32_t shrtimer_periph, uint32_t cntid); 1973 /* enable the Master_TIMER or Slave_TIMER update event */ 1974 void shrtimer_timers_update_event_enable(uint32_t shrtimer_periph, uint32_t timer_id); 1975 /* disable the Master_TIMER or Slave_TIMER update event */ 1976 void shrtimer_timers_update_event_disable(uint32_t shrtimer_periph, uint32_t timer_id); 1977 /* trigger the Master_TIMER and Slave_TIMER registers update by software */ 1978 void shrtimer_software_update(uint32_t shrtimer_periph, uint32_t timersrc); 1979 /* reset the Master_TIMER and Slave_TIMER counter by software */ 1980 void shrtimer_software_counter_reset(uint32_t shrtimer_periph, uint32_t timerrst); 1981 1982 /* SHRTIMER waveform configure functions */ 1983 /* initialize waveform mode initialization parameters struct with a default value */ 1984 void shrtimer_timerinit_struct_para_init(shrtimer_timerinit_parameter_struct* timerinit); 1985 /* initialize a timer to work in waveform mode */ 1986 void shrtimer_timers_waveform_init(uint32_t shrtimer_periph, uint32_t timer_id, shrtimer_timerinit_parameter_struct* timerinitpara); 1987 /* initialize Slave_TIMER general behavior configuration struct with a default value */ 1988 void shrtimer_timercfg_struct_para_init(shrtimer_timercfg_parameter_struct* timercgf); 1989 /* configure the general behavior of a Slave_TIMER which work in waveform mode */ 1990 void shrtimer_slavetimer_waveform_config(uint32_t shrtimer_periph, uint32_t timer_id, shrtimer_timercfg_parameter_struct * timercfg); 1991 /* initialize compare unit configuration struct with a default value */ 1992 void shrtimer_comparecfg_struct_para_init(shrtimer_comparecfg_parameter_struct* comparecfg); 1993 /* configure the compare unit of a Slave_TIMER which work in waveform mode */ 1994 void shrtimer_slavetimer_waveform_compare_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t comparex, shrtimer_comparecfg_parameter_struct* cmpcfg); 1995 /* initialize channel output configuration struct with a default value */ 1996 void shrtimer_channel_outputcfg_struct_para_init(shrtimer_channel_outputcfg_parameter_struct * channelcfg); 1997 /* configure the channel output of a Slave_TIMER work in waveform mode */ 1998 void shrtimer_slavetimer_waveform_channel_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t channel, shrtimer_channel_outputcfg_parameter_struct * channelcfg); 1999 /* software generates channel "set request" or "reset request" */ 2000 void shrtimer_slavetimer_waveform_channel_software_request(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t channel, uint32_t request); 2001 /* get Slave_TIMER channel output level */ 2002 uint32_t shrtimer_slavetimer_waveform_channel_output_level_get(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t channel); 2003 /* get Slave_TIMER channel run state */ 2004 uint32_t shrtimer_slavetimer_waveform_channel_state_get(uint32_t shrtimer_periph, uint32_t channel); 2005 /* initialize dead time configuration struct with a default value */ 2006 void shrtimer_deadtimercfg_struct_para_init(shrtimer_deadtimecfg_parameter_struct * dtcfg); 2007 /* configure the dead time for Slave_TIMER */ 2008 void shrtimer_slavetimer_deadtime_config(uint32_t shrtimer_periph, uint32_t timer_id, shrtimer_deadtimecfg_parameter_struct* dtcfg); 2009 /* initialize carrier signal configuration struct with a default value */ 2010 void shrtimer_carriersignalcfg_struct_para_init(shrtimer_carriersignalcfg_parameter_struct* carriercfg); 2011 /* configure the carrier signal mode for Slave_TIMER */ 2012 void shrtimer_slavetimer_carriersignal_config(uint32_t shrtimer_periph, uint32_t timer_id, shrtimer_carriersignalcfg_parameter_struct* carriercfg); 2013 /* enable a output channel */ 2014 void shrtimer_output_channel_enable(uint32_t shrtimer_periph, uint32_t chid); 2015 /* disable a output channel */ 2016 void shrtimer_output_channel_disable(uint32_t shrtimer_periph, uint32_t chid); 2017 2018 /* Master_TIMER and Slave_TIMER numerical related functions */ 2019 /* configure the compare value in Master_TIMER */ 2020 void shrtimer_mastertimer_compare_value_config(uint32_t shrtimer_periph, uint32_t comparex, uint32_t cmpvalue); 2021 /* get the compare value in Master_TIMER */ 2022 uint32_t shrtimer_mastertimer_compare_value_get(uint32_t shrtimer_periph, uint32_t comparex); 2023 /* configure the compare value in Slave_TIMER */ 2024 void shrtimer_slavetimer_compare_value_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t comparex, uint32_t cmpvalue); 2025 /* get the compare value in Slave_TIMER */ 2026 uint32_t shrtimer_slavetimer_compare_value_get(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t comparex); 2027 /* configure the counter value in Master_TIMER and Slave_TIMER */ 2028 void shrtimer_timers_counter_value_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t cntvalue); 2029 /* get the counter value in Master_TIMER and Slave_TIMER */ 2030 uint32_t shrtimer_timers_counter_value_get(uint32_t shrtimer_periph, uint32_t timer_id); 2031 /* configure the counter auto reload value in Master_TIMER and Slave_TIMER */ 2032 void shrtimer_timers_autoreload_value_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t carlvalue); 2033 /* get the counter auto reload value in Master_TIMER and Slave_TIMER */ 2034 uint32_t shrtimer_timers_autoreload_value_get(uint32_t shrtimer_periph, uint32_t timer_id); 2035 /* configure the counter repetition value in Master_TIMER and Slave_TIMER */ 2036 void shrtimer_timers_repetition_value_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t replvalue); 2037 /* get the counter repetition value in Master_TIMER and Slave_TIMER */ 2038 uint32_t shrtimer_timers_repetition_value_get(uint32_t shrtimer_periph, uint32_t timer_id); 2039 2040 /* external event and synchronization configure functions */ 2041 /* initialize external event filtering for Slave_TIMER configuration struct with a default value */ 2042 void shrtimer_exevfilter_struct_para_init(shrtimer_exevfilter_parameter_struct * exevfilter); 2043 /* configure the external event filtering for Slave_TIMER (blanking, windowing) */ 2044 void shrtimer_slavetimer_exevent_filtering_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t event_id, shrtimer_exevfilter_parameter_struct* exevfilter); 2045 /* initialize external event configuration struct with a default value */ 2046 void shrtimer_exeventcfg_struct_para_init(shrtimer_exeventcfg_parameter_struct * exevcfg); 2047 /* configure the an external event */ 2048 void shrtimer_exevent_config(uint32_t shrtimer_periph, uint32_t event_id, shrtimer_exeventcfg_parameter_struct* exevcfg); 2049 /* configure external event digital filter clock division */ 2050 void shrtimer_exevent_prescaler(uint32_t shrtimer_periph, uint32_t prescaler); 2051 /* initialize synchronization configuration struct with a default value */ 2052 void shrtimer_synccfg_struct_para_init(shrtimer_synccfg_parameter_struct* synccfg); 2053 /* configure the synchronization input/output of the SHRTIMER */ 2054 void shrtimer_synchronization_config(uint32_t shrtimer_periph, shrtimer_synccfg_parameter_struct* synccfg); 2055 2056 /* fault configure functions */ 2057 /* configure the synchronization input/output of the SHRTIMER */ 2058 void shrtimer_faultcfg_struct_para_init(shrtimer_faultcfg_parameter_struct * faultcfg); 2059 /* configure the fault input */ 2060 void shrtimer_fault_config(uint32_t shrtimer_periph, uint32_t fault_id, shrtimer_faultcfg_parameter_struct* faultcfg); 2061 /* configure the fault input digital filter clock division */ 2062 void shrtimer_fault_prescaler_config(uint32_t shrtimer_periph, uint32_t prescaler); 2063 /* fault input enable */ 2064 void shrtimer_fault_input_enable(uint32_t shrtimer_periph, uint32_t fault_id); 2065 /* fault input disable */ 2066 void shrtimer_fault_input_disable(uint32_t shrtimer_periph, uint32_t fault_id); 2067 2068 /* DMA configure functions */ 2069 /* enable the Master_TIMER and Slave_TIMER DMA request */ 2070 void shrtimer_timers_dma_enable(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t dmareq); 2071 /* disable the Master_TIMER and Slave_TIMER DMA request */ 2072 void shrtimer_timers_dma_disable(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t dmareq); 2073 /* configure the DMA mode for Master_TIMER or Slave_TIMER */ 2074 void shrtimer_dmamode_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t regupdate); 2075 2076 /* bunch mode configure functions */ 2077 /* initialize bunch mode configuration struct with a default value */ 2078 void shrtimer_bunchmode_struct_para_init(shrtimer_bunchmode_parameter_struct* bmcfg); 2079 /* configure bunch mode for the SHRTIMER */ 2080 void shrtimer_bunchmode_config(uint32_t shrtimer_periph, shrtimer_bunchmode_parameter_struct* bmcfg); 2081 /* enable the bunch mode */ 2082 void shrtimer_bunchmode_enable(uint32_t shrtimer_periph); 2083 /* disable the bunch mode */ 2084 void shrtimer_bunchmode_disable(uint32_t shrtimer_periph); 2085 /* get bunch mode operating flag */ 2086 uint32_t shrtimer_bunchmode_flag_get(uint32_t shrtimer_periph); 2087 /* bunch mode started by software */ 2088 void shrtimer_bunchmode_software_start(uint32_t shrtimer_periph); 2089 2090 /* configure the capture functions in Slave_TIMER */ 2091 /* configure the capture source in Slave_TIMER */ 2092 void shrtimer_slavetimer_capture_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t capturex, uint32_t trgsource); 2093 /* capture triggered by software in Slave_TIMER */ 2094 void shrtimer_slavetimer_capture_software(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t capturex); 2095 /* read the capture value */ 2096 uint32_t shrtimer_slavetimer_capture_value_read(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t capturex); 2097 2098 /* ADC trigger configure functions */ 2099 /* initialize ADC trigger configuration struct with a default value */ 2100 void shrtimer_adctrigcfg_struct_para_init(shrtimer_adctrigcfg_parameter_struct* triggercfg); 2101 /* configure the trigger source to ADC and the update source */ 2102 void shrtimer_adc_trigger_config(uint32_t shrtimer_periph, uint32_t trigger_id, shrtimer_adctrigcfg_parameter_struct* triggercfg); 2103 2104 /* TIMER interrupt and flag functions */ 2105 /* get the Master_TIMER and Slave_TIMER flag */ 2106 FlagStatus shrtimer_timers_flag_get(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t flag); 2107 /* clear the Master_TIMER and Slave_TIMER flag */ 2108 void shrtimer_timers_flag_clear(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t flag); 2109 /* get the common flag */ 2110 FlagStatus shrtimer_common_flag_get(uint32_t shrtimer_periph, uint32_t flag); 2111 /* clear the common flag */ 2112 void shrtimer_common_flag_clear(uint32_t shrtimer_periph, uint32_t flag); 2113 /* enable the Master_TIMER and Slave_TIMER interrupt */ 2114 void shrtimer_timers_interrupt_enable(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t interrupt); 2115 /* disable the Master_TIMER and Slave_TIMER interrupt */ 2116 void shrtimer_timers_interrupt_disable(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t interrupt); 2117 /* clear the Master_TIMER and Slave_TIMER interrupt flag */ 2118 FlagStatus shrtimer_timers_interrupt_flag_get(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t interrupt); 2119 /* clear the Master_TIMER and Slave_TIMER interrupt flag */ 2120 void shrtimer_timers_interrupt_flag_clear(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t interrupt); 2121 /* enable the common interrupt */ 2122 void shrtimer_common_interrupt_enable(uint32_t shrtimer_periph, uint32_t interrupt); 2123 /* disable common interrupt */ 2124 void shrtimer_common_interrupt_disable(uint32_t shrtimer_periph, uint32_t interrupt); 2125 /* clear the common interrupt flag */ 2126 FlagStatus shrtimer_common_interrupt_flag_get(uint32_t shrtimer_periph, uint32_t interrupt); 2127 /* clear the common interrupt flag */ 2128 void shrtimer_common_interrupt_flag_clear(uint32_t shrtimer_periph, uint32_t interrupt); 2129 2130 #endif /* GD32E50X_SHRTIMER_H */ 2131
