1 /*
2  * Copyright (c) 2020-2021 Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Licensed under the Apache License, Version 2.0 (the License); you may
7  * not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  * www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  */
18 
19 #ifndef ETHOSU65_INTERFACE_H
20 #define ETHOSU65_INTERFACE_H
21 
22 #ifdef __KERNEL__
23 #include <linux/types.h>
24 #else
25 #include <stdint.h>
26 #endif
27 
28 #if !defined(__cplusplus) || __cplusplus < 201402L
29 #define CONSTEXPR
30 #else
31 #define CONSTEXPR constexpr
32 #endif
33 
34 #ifndef __cplusplus
35 #define STRUCT struct
36 #else
37 #define STRUCT
38 #endif
39 
40 #if defined(__cplusplus) && defined(NPU_DISASSEMBLE)
41 #include <iomanip>
42 #include <sstream>
43 #include <vector>
44 #endif
45 
46 #if defined(__cplusplus) && !defined(NPU_NAMESPACE)
47 #define NPU_NAMESPACE npu
48 #endif
49 
50 #ifdef __cplusplus
51 #include <cstring>
52 #include <limits>
53 #endif
54 
55 #ifdef __cplusplus
56 namespace NPU_NAMESPACE
57 {
58 #endif
59 #define NNX_ARCH_VERSION_MAJOR 1
60 #define NNX_ARCH_VERSION_MINOR 0
61 #define NNX_ARCH_VERSION_PATCH 6
62 
63 // Register offsets
64 //
65 // Register subpage BASE
66 //
67 #define NPU_REG_ID 0x0000
68 #define NPU_REG_STATUS 0x0004
69 #define NPU_REG_CMD 0x0008
70 #define NPU_REG_RESET 0x000C
71 #define NPU_REG_QBASE 0x0010
72 #define NPU_REG_QBASE_HI 0x0014
73 #define NPU_REG_QREAD 0x0018
74 #define NPU_REG_QCONFIG 0x001C
75 #define NPU_REG_QSIZE 0x0020
76 #define NPU_REG_PROT 0x0024
77 #define NPU_REG_CONFIG 0x0028
78 #define NPU_REG_LOCK 0x002C
79 #define NPU_REG_REGIONCFG 0x003C
80 #define NPU_REG_AXI_LIMIT0 0x0040
81 #define NPU_REG_AXI_LIMIT1 0x0044
82 #define NPU_REG_AXI_LIMIT2 0x0048
83 #define NPU_REG_AXI_LIMIT3 0x004C
84 #define BASE_REGISTERS_SIZE 0x0080
85 
86 //
87 // Register subpage BASE_POINTERS
88 //
89 #define NPU_REG_BASEP_BASE 0x0080
90 #define NPU_REG_BASEP_ARRLEN 0x0008
91 #define BASE_POINTERS_REGISTERS_SIZE 0x0100
92 
93 //
94 // Register subpage DEBUG
95 //
96 #define NPU_REG_WD_STATUS 0x0100
97 #define NPU_REG_MAC_STATUS 0x0104
98 #define NPU_REG_AO_STATUS 0x0108
99 #define NPU_REG_DMA_STATUS0 0x0110
100 #define NPU_REG_DMA_STATUS1 0x0114
101 #define NPU_REG_CLKFORCE 0x0140
102 #define NPU_REG_DEBUG_ADDRESS 0x0144
103 #define NPU_REG_DEBUG_MISC 0x0148
104 #define NPU_REG_DEBUGCORE 0x014C
105 #define NPU_REG_DEBUG_BLOCK 0x0150
106 #define DEBUG_REGISTERS_SIZE 0x0180
107 
108 //
109 // Register subpage PMU
110 //
111 #define NPU_REG_PMCR 0x0180
112 #define NPU_REG_PMCNTENSET 0x0184
113 #define NPU_REG_PMCNTENCLR 0x0188
114 #define NPU_REG_PMOVSSET 0x018C
115 #define NPU_REG_PMOVSCLR 0x0190
116 #define NPU_REG_PMINTSET 0x0194
117 #define NPU_REG_PMINTCLR 0x0198
118 #define NPU_REG_PMCCNTR 0x01A0
119 #define NPU_REG_PMCCNTR_HI 0x01A4
120 #define NPU_REG_PMCCNTR_CFG 0x01A8
121 #define NPU_REG_PMCAXI_CHAN 0x01AC
122 #define PMU_REGISTERS_SIZE 0x0200
123 
124 //
125 // Register subpage TSU_DEBUG
126 //
127 #define NPU_REG_KERNEL_X 0x0200
128 #define NPU_REG_KERNEL_Y 0x0204
129 #define NPU_REG_KERNEL_W_M1 0x0208
130 #define NPU_REG_KERNEL_H_M1 0x020C
131 #define NPU_REG_OFM_CBLK_WIDTH_M1 0x0210
132 #define NPU_REG_OFM_CBLK_HEIGHT_M1 0x0214
133 #define NPU_REG_OFM_CBLK_DEPTH_M1 0x0218
134 #define NPU_REG_IFM_CBLK_DEPTH_M1 0x021C
135 #define NPU_REG_OFM_X 0x0220
136 #define NPU_REG_OFM_Y 0x0224
137 #define NPU_REG_OFM_Z 0x0228
138 #define NPU_REG_IFM_Z 0x022C
139 #define NPU_REG_PAD_TOP 0x0230
140 #define NPU_REG_PAD_LEFT 0x0234
141 #define NPU_REG_IFM_CBLK_WIDTH 0x0238
142 #define NPU_REG_IFM_CBLK_HEIGHT 0x023C
143 #define NPU_REG_DMA_IFM_SRC 0x0240
144 #define NPU_REG_DMA_IFM_SRC_HI 0x0244
145 #define NPU_REG_DMA_IFM_DST 0x0248
146 #define NPU_REG_DMA_OFM_SRC 0x024C
147 #define NPU_REG_DMA_OFM_DST 0x0250
148 #define NPU_REG_DMA_OFM_DST_HI 0x0254
149 #define NPU_REG_DMA_WEIGHT_SRC 0x0258
150 #define NPU_REG_DMA_WEIGHT_SRC_HI 0x025C
151 #define NPU_REG_DMA_CMD_SRC 0x0260
152 #define NPU_REG_DMA_CMD_SRC_HI 0x0264
153 #define NPU_REG_DMA_CMD_SIZE 0x0268
154 #define NPU_REG_DMA_M2M_SRC 0x026C
155 #define NPU_REG_DMA_M2M_SRC_HI 0x0270
156 #define NPU_REG_DMA_M2M_DST 0x0274
157 #define NPU_REG_DMA_M2M_DST_HI 0x0278
158 #define NPU_REG_CURRENT_QREAD 0x027C
159 #define NPU_REG_DMA_SCALE_SRC 0x0280
160 #define NPU_REG_DMA_SCALE_SRC_HI 0x0284
161 #define NPU_REG_CURRENT_BLOCK 0x02B4
162 #define NPU_REG_CURRENT_OP 0x02B8
163 #define NPU_REG_CURRENT_CMD 0x02BC
164 #define TSU_DEBUG_REGISTERS_SIZE 0x02C0
165 
166 //
167 // Register subpage PMU_COUNTERS
168 //
169 #define NPU_REG_PMEVCNTR_BASE 0x0300
170 #define NPU_REG_PMEVCNTR_ARRLEN 0x0004
171 #define NPU_REG_PMEVTYPER_BASE 0x0380
172 #define NPU_REG_PMEVTYPER_ARRLEN 0x0004
173 #define PMU_COUNTERS_REGISTERS_SIZE 0x0400
174 
175 //
176 // Register subpage SHARED_BUFFER
177 //
178 #define NPU_REG_SHARED_BUFFER_BASE 0x0400
179 #define NPU_REG_SHARED_BUFFER_ARRLEN 0x0100
180 #define SHARED_BUFFER_REGISTERS_SIZE 0x0800
181 
182 //
183 // Register subpage TSU_IFM
184 //
185 #define NPU_REG_IFM_PAD_TOP 0x0800
186 #define NPU_REG_IFM_PAD_LEFT 0x0804
187 #define NPU_REG_IFM_PAD_RIGHT 0x0808
188 #define NPU_REG_IFM_PAD_BOTTOM 0x080C
189 #define NPU_REG_IFM_DEPTH_M1 0x0810
190 #define NPU_REG_IFM_PRECISION 0x0814
191 #define NPU_REG_IFM_UPSCALE 0x081C
192 #define NPU_REG_IFM_ZERO_POINT 0x0824
193 #define NPU_REG_IFM_WIDTH0_M1 0x0828
194 #define NPU_REG_IFM_HEIGHT0_M1 0x082C
195 #define NPU_REG_IFM_HEIGHT1_M1 0x0830
196 #define NPU_REG_IFM_IB_END 0x0834
197 #define NPU_REG_IFM_REGION 0x083C
198 #define TSU_IFM_REGISTERS_SIZE 0x0840
199 
200 //
201 // Register subpage TSU_OFM
202 //
203 #define NPU_REG_OFM_WIDTH_M1 0x0844
204 #define NPU_REG_OFM_HEIGHT_M1 0x0848
205 #define NPU_REG_OFM_DEPTH_M1 0x084C
206 #define NPU_REG_OFM_PRECISION 0x0850
207 #define NPU_REG_OFM_BLK_WIDTH_M1 0x0854
208 #define NPU_REG_OFM_BLK_HEIGHT_M1 0x0858
209 #define NPU_REG_OFM_BLK_DEPTH_M1 0x085C
210 #define NPU_REG_OFM_ZERO_POINT 0x0860
211 #define NPU_REG_OFM_WIDTH0_M1 0x0868
212 #define NPU_REG_OFM_HEIGHT0_M1 0x086C
213 #define NPU_REG_OFM_HEIGHT1_M1 0x0870
214 #define NPU_REG_OFM_REGION 0x087C
215 #define TSU_OFM_REGISTERS_SIZE 0x0880
216 
217 //
218 // Register subpage TSU_KERNEL
219 //
220 #define NPU_REG_KERNEL_WIDTH_M1 0x0880
221 #define NPU_REG_KERNEL_HEIGHT_M1 0x0884
222 #define NPU_REG_KERNEL_STRIDE 0x0888
223 #define NPU_REG_PARALLEL_MODE 0x088C
224 #define NPU_REG_ACC_FORMAT 0x0890
225 #define NPU_REG_ACTIVATION 0x0894
226 #define NPU_REG_ACTIVATION_MIN 0x0898
227 #define NPU_REG_ACTIVATION_MAX 0x089C
228 #define NPU_REG_WEIGHT_REGION 0x08A0
229 #define NPU_REG_SCALE_REGION 0x08A4
230 #define NPU_REG_AB_START 0x08B4
231 #define NPU_REG_BLOCKDEP 0x08BC
232 #define TSU_KERNEL_REGISTERS_SIZE 0x08C0
233 
234 //
235 // Register subpage TSU_DMA
236 //
237 #define NPU_REG_DMA0_SRC_REGION 0x08C0
238 #define NPU_REG_DMA0_DST_REGION 0x08C4
239 #define NPU_REG_DMA0_SIZE0 0x08C8
240 #define NPU_REG_DMA0_SIZE1 0x08CC
241 #define TSU_DMA_REGISTERS_SIZE 0x0900
242 
243 //
244 // Register subpage TSU_IFM2
245 //
246 #define NPU_REG_IFM2_BROADCAST 0x0900
247 #define NPU_REG_IFM2_SCALAR 0x0904
248 #define NPU_REG_IFM2_PRECISION 0x0914
249 #define NPU_REG_IFM2_ZERO_POINT 0x0924
250 #define NPU_REG_IFM2_WIDTH0_M1 0x0928
251 #define NPU_REG_IFM2_HEIGHT0_M1 0x092C
252 #define NPU_REG_IFM2_HEIGHT1_M1 0x0930
253 #define NPU_REG_IFM2_IB_START 0x0934
254 #define NPU_REG_IFM2_REGION 0x093C
255 #define TSU_IFM2_REGISTERS_SIZE 0x0940
256 
257 //
258 // Register subpage TSU_IFM_BASE
259 //
260 #define NPU_REG_IFM_BASE0 0x0A00
261 #define NPU_REG_IFM_BASE0_HI 0x0A04
262 #define NPU_REG_IFM_BASE1 0x0A08
263 #define NPU_REG_IFM_BASE1_HI 0x0A0C
264 #define NPU_REG_IFM_BASE2 0x0A10
265 #define NPU_REG_IFM_BASE2_HI 0x0A14
266 #define NPU_REG_IFM_BASE3 0x0A18
267 #define NPU_REG_IFM_BASE3_HI 0x0A1C
268 #define NPU_REG_IFM_STRIDE_X 0x0A20
269 #define NPU_REG_IFM_STRIDE_X_HI 0x0A24
270 #define NPU_REG_IFM_STRIDE_Y 0x0A28
271 #define NPU_REG_IFM_STRIDE_Y_HI 0x0A2C
272 #define NPU_REG_IFM_STRIDE_C 0x0A30
273 #define NPU_REG_IFM_STRIDE_C_HI 0x0A34
274 #define TSU_IFM_BASE_REGISTERS_SIZE 0x0A40
275 
276 //
277 // Register subpage TSU_OFM_BASE
278 //
279 #define NPU_REG_OFM_BASE0 0x0A40
280 #define NPU_REG_OFM_BASE0_HI 0x0A44
281 #define NPU_REG_OFM_BASE1 0x0A48
282 #define NPU_REG_OFM_BASE1_HI 0x0A4C
283 #define NPU_REG_OFM_BASE2 0x0A50
284 #define NPU_REG_OFM_BASE2_HI 0x0A54
285 #define NPU_REG_OFM_BASE3 0x0A58
286 #define NPU_REG_OFM_BASE3_HI 0x0A5C
287 #define NPU_REG_OFM_STRIDE_X 0x0A60
288 #define NPU_REG_OFM_STRIDE_X_HI 0x0A64
289 #define NPU_REG_OFM_STRIDE_Y 0x0A68
290 #define NPU_REG_OFM_STRIDE_Y_HI 0x0A6C
291 #define NPU_REG_OFM_STRIDE_C 0x0A70
292 #define NPU_REG_OFM_STRIDE_C_HI 0x0A74
293 #define TSU_OFM_BASE_REGISTERS_SIZE 0x0A80
294 
295 //
296 // Register subpage TSU_WS_BASE
297 //
298 #define NPU_REG_WEIGHT_BASE 0x0A80
299 #define NPU_REG_WEIGHT_BASE_HI 0x0A84
300 #define NPU_REG_WEIGHT_LENGTH 0x0A88
301 #define NPU_REG_WEIGHT_LENGTH_HI 0x0A8C
302 #define NPU_REG_SCALE_BASE 0x0A90
303 #define NPU_REG_SCALE_BASE_HI 0x0A94
304 #define NPU_REG_SCALE_LENGTH 0x0A98
305 #define NPU_REG_SCALE_LENGTH_HI 0x0A9C
306 #define NPU_REG_OFM_SCALE 0x0AA0
307 #define NPU_REG_OFM_SCALE_SHIFT 0x0AA4
308 #define NPU_REG_OPA_SCALE 0x0AA8
309 #define NPU_REG_OPA_SCALE_SHIFT 0x0AAC
310 #define NPU_REG_OPB_SCALE 0x0AB0
311 #define TSU_WS_BASE_REGISTERS_SIZE 0x0AC0
312 
313 //
314 // Register subpage TSU_DMA_BASE
315 //
316 #define NPU_REG_DMA0_SRC 0x0AC0
317 #define NPU_REG_DMA0_SRC_HI 0x0AC4
318 #define NPU_REG_DMA0_DST 0x0AC8
319 #define NPU_REG_DMA0_DST_HI 0x0ACC
320 #define NPU_REG_DMA0_LEN 0x0AD0
321 #define NPU_REG_DMA0_LEN_HI 0x0AD4
322 #define NPU_REG_DMA0_SKIP0 0x0AD8
323 #define NPU_REG_DMA0_SKIP0_HI 0x0ADC
324 #define NPU_REG_DMA0_SKIP1 0x0AE0
325 #define NPU_REG_DMA0_SKIP1_HI 0x0AE4
326 #define TSU_DMA_BASE_REGISTERS_SIZE 0x0B00
327 
328 //
329 // Register subpage TSU_IFM2_BASE
330 //
331 #define NPU_REG_IFM2_BASE0 0x0B00
332 #define NPU_REG_IFM2_BASE0_HI 0x0B04
333 #define NPU_REG_IFM2_BASE1 0x0B08
334 #define NPU_REG_IFM2_BASE1_HI 0x0B0C
335 #define NPU_REG_IFM2_BASE2 0x0B10
336 #define NPU_REG_IFM2_BASE2_HI 0x0B14
337 #define NPU_REG_IFM2_BASE3 0x0B18
338 #define NPU_REG_IFM2_BASE3_HI 0x0B1C
339 #define NPU_REG_IFM2_STRIDE_X 0x0B20
340 #define NPU_REG_IFM2_STRIDE_X_HI 0x0B24
341 #define NPU_REG_IFM2_STRIDE_Y 0x0B28
342 #define NPU_REG_IFM2_STRIDE_Y_HI 0x0B2C
343 #define NPU_REG_IFM2_STRIDE_C 0x0B30
344 #define NPU_REG_IFM2_STRIDE_C_HI 0x0B34
345 #define TSU_IFM2_BASE_REGISTERS_SIZE 0x0B40
346 
347 //
348 // Register subpage TSU_WS1_BASE
349 //
350 #define NPU_REG_WEIGHT1_BASE 0x0B40
351 #define NPU_REG_WEIGHT1_BASE_HI 0x0B44
352 #define NPU_REG_WEIGHT1_LENGTH 0x0B48
353 #define NPU_REG_WEIGHT1_LENGTH_HI 0x0B4C
354 #define NPU_REG_SCALE1_BASE 0x0B50
355 #define NPU_REG_SCALE1_BASE_HI 0x0B54
356 #define NPU_REG_SCALE1_LENGTH 0x0B58
357 #define NPU_REG_SCALE1_LENGTH_HI 0x0B5C
358 #define TSU_WS1_BASE_REGISTERS_SIZE 0x0B80
359 
360 //
361 // Register subpage TSU_USER_BASE
362 //
363 #define TSU_USER_BASE_REGISTERS_SIZE 0x0BC0
364 
365 //
366 // Register subpage TSU_DMA_EBASE
367 //
368 #define TSU_DMA_EBASE_REGISTERS_SIZE 0x0C00
369 
370 //
371 // Register subpage ID
372 //
373 #define NPU_REG_REVISION 0x0FC0
374 #define NPU_REG_PID4 0x0FD0
375 #define NPU_REG_PID5 0x0FD4
376 #define NPU_REG_PID6 0x0FD8
377 #define NPU_REG_PID7 0x0FDC
378 #define NPU_REG_PID0 0x0FE0
379 #define NPU_REG_PID1 0x0FE4
380 #define NPU_REG_PID2 0x0FE8
381 #define NPU_REG_PID3 0x0FEC
382 #define NPU_REG_CID0 0x0FF0
383 #define NPU_REG_CID1 0x0FF4
384 #define NPU_REG_CID2 0x0FF8
385 #define NPU_REG_CID3 0x0FFC
386 #define ID_REGISTERS_SIZE 0x1000
387 
388 #ifdef __cplusplus
389 // Enum types
390 enum class acc_format : uint8_t
391 {
392     I32 = 0,
393     I40 = 1,
394     F16 = 2,
395 };
396 
397 enum class activation_clip_range : uint8_t
398 {
399     OFM_PRECISION = 0,
400     FORCE_UINT8   = 2,
401     FORCE_INT8    = 3,
402     FORCE_INT16   = 5,
403 };
404 
405 enum class activation_format : uint8_t
406 {
407     NHWC    = 0,
408     NHCWB16 = 1,
409 };
410 
411 enum class activation_function : uint8_t
412 {
413     RELU    = 0,
414     TANH    = 3,
415     SIGMOID = 4,
416     TABLE_0 = 16,
417     TABLE_1 = 17,
418     TABLE_2 = 18,
419     TABLE_3 = 19,
420     TABLE_4 = 20,
421     TABLE_5 = 21,
422     TABLE_6 = 22,
423     TABLE_7 = 23,
424 };
425 
426 enum class activation_precision : uint8_t
427 {
428     B8  = 0,
429     B16 = 1,
430     B32 = 2,
431     B64 = 3,
432 };
433 
434 enum class activation_type : uint8_t
435 {
436     UNSIGNED = 0,
437     SIGNED   = 1,
438 };
439 
440 enum class axi_mem_encoding : uint8_t
441 {
442     DEVICE_NON_BUFFERABLE                 = 0,
443     DEVICE_BUFFERABLE                     = 1,
444     NORMAL_NON_CACHEABLE_NON_BUFFERABLE   = 2,
445     NORMAL_NON_CACHEABLE_BUFFERABLE       = 3,
446     WRITE_THROUGH_NO_ALLOCATE             = 4,
447     WRITE_THROUGH_READ_ALLOCATE           = 5,
448     WRITE_THROUGH_WRITE_ALLOCATE          = 6,
449     WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7,
450     WRITE_BACK_NO_ALLOCATE                = 8,
451     WRITE_BACK_READ_ALLOCATE              = 9,
452     WRITE_BACK_WRITE_ALLOCATE             = 10,
453     WRITE_BACK_READ_AND_WRITE_ALLOCATE    = 11,
454 };
455 
456 enum class broadcast_mode : uint8_t
457 {
458     DISABLE = 0,
459     ENABLE  = 1,
460 };
461 
462 enum class cmd0_opcode : uint16_t
463 {
464     NPU_OP_STOP               = 0,
465     NPU_OP_IRQ                = 1,
466     NPU_OP_CONV               = 2,
467     NPU_OP_DEPTHWISE          = 3,
468     NPU_OP_POOL               = 5,
469     NPU_OP_ELEMENTWISE        = 6,
470     NPU_OP_DMA_START          = 16,
471     NPU_OP_DMA_WAIT           = 17,
472     NPU_OP_KERNEL_WAIT        = 18,
473     NPU_OP_PMU_MASK           = 19,
474     NPU_SET_IFM_PAD_TOP       = 256,
475     NPU_SET_IFM_PAD_LEFT      = 257,
476     NPU_SET_IFM_PAD_RIGHT     = 258,
477     NPU_SET_IFM_PAD_BOTTOM    = 259,
478     NPU_SET_IFM_DEPTH_M1      = 260,
479     NPU_SET_IFM_PRECISION     = 261,
480     NPU_SET_IFM_UPSCALE       = 263,
481     NPU_SET_IFM_ZERO_POINT    = 265,
482     NPU_SET_IFM_WIDTH0_M1     = 266,
483     NPU_SET_IFM_HEIGHT0_M1    = 267,
484     NPU_SET_IFM_HEIGHT1_M1    = 268,
485     NPU_SET_IFM_IB_END        = 269,
486     NPU_SET_IFM_REGION        = 271,
487     NPU_SET_OFM_WIDTH_M1      = 273,
488     NPU_SET_OFM_HEIGHT_M1     = 274,
489     NPU_SET_OFM_DEPTH_M1      = 275,
490     NPU_SET_OFM_PRECISION     = 276,
491     NPU_SET_OFM_BLK_WIDTH_M1  = 277,
492     NPU_SET_OFM_BLK_HEIGHT_M1 = 278,
493     NPU_SET_OFM_BLK_DEPTH_M1  = 279,
494     NPU_SET_OFM_ZERO_POINT    = 280,
495     NPU_SET_OFM_WIDTH0_M1     = 282,
496     NPU_SET_OFM_HEIGHT0_M1    = 283,
497     NPU_SET_OFM_HEIGHT1_M1    = 284,
498     NPU_SET_OFM_REGION        = 287,
499     NPU_SET_KERNEL_WIDTH_M1   = 288,
500     NPU_SET_KERNEL_HEIGHT_M1  = 289,
501     NPU_SET_KERNEL_STRIDE     = 290,
502     NPU_SET_PARALLEL_MODE     = 291,
503     NPU_SET_ACC_FORMAT        = 292,
504     NPU_SET_ACTIVATION        = 293,
505     NPU_SET_ACTIVATION_MIN    = 294,
506     NPU_SET_ACTIVATION_MAX    = 295,
507     NPU_SET_WEIGHT_REGION     = 296,
508     NPU_SET_SCALE_REGION      = 297,
509     NPU_SET_AB_START          = 301,
510     NPU_SET_BLOCKDEP          = 303,
511     NPU_SET_DMA0_SRC_REGION   = 304,
512     NPU_SET_DMA0_DST_REGION   = 305,
513     NPU_SET_DMA0_SIZE0        = 306,
514     NPU_SET_DMA0_SIZE1        = 307,
515     NPU_SET_IFM2_BROADCAST    = 384,
516     NPU_SET_IFM2_SCALAR       = 385,
517     NPU_SET_IFM2_PRECISION    = 389,
518     NPU_SET_IFM2_ZERO_POINT   = 393,
519     NPU_SET_IFM2_WIDTH0_M1    = 394,
520     NPU_SET_IFM2_HEIGHT0_M1   = 395,
521     NPU_SET_IFM2_HEIGHT1_M1   = 396,
522     NPU_SET_IFM2_IB_START     = 397,
523     NPU_SET_IFM2_REGION       = 399,
524 };
525 
526 enum class cmd1_opcode : uint16_t
527 {
528     NPU_SET_IFM_BASE0      = 0,
529     NPU_SET_IFM_BASE1      = 1,
530     NPU_SET_IFM_BASE2      = 2,
531     NPU_SET_IFM_BASE3      = 3,
532     NPU_SET_IFM_STRIDE_X   = 4,
533     NPU_SET_IFM_STRIDE_Y   = 5,
534     NPU_SET_IFM_STRIDE_C   = 6,
535     NPU_SET_OFM_BASE0      = 16,
536     NPU_SET_OFM_BASE1      = 17,
537     NPU_SET_OFM_BASE2      = 18,
538     NPU_SET_OFM_BASE3      = 19,
539     NPU_SET_OFM_STRIDE_X   = 20,
540     NPU_SET_OFM_STRIDE_Y   = 21,
541     NPU_SET_OFM_STRIDE_C   = 22,
542     NPU_SET_WEIGHT_BASE    = 32,
543     NPU_SET_WEIGHT_LENGTH  = 33,
544     NPU_SET_SCALE_BASE     = 34,
545     NPU_SET_SCALE_LENGTH   = 35,
546     NPU_SET_OFM_SCALE      = 36,
547     NPU_SET_OPA_SCALE      = 37,
548     NPU_SET_OPB_SCALE      = 38,
549     NPU_SET_DMA0_SRC       = 48,
550     NPU_SET_DMA0_DST       = 49,
551     NPU_SET_DMA0_LEN       = 50,
552     NPU_SET_DMA0_SKIP0     = 51,
553     NPU_SET_DMA0_SKIP1     = 52,
554     NPU_SET_IFM2_BASE0     = 128,
555     NPU_SET_IFM2_BASE1     = 129,
556     NPU_SET_IFM2_BASE2     = 130,
557     NPU_SET_IFM2_BASE3     = 131,
558     NPU_SET_IFM2_STRIDE_X  = 132,
559     NPU_SET_IFM2_STRIDE_Y  = 133,
560     NPU_SET_IFM2_STRIDE_C  = 134,
561     NPU_SET_WEIGHT1_BASE   = 144,
562     NPU_SET_WEIGHT1_LENGTH = 145,
563     NPU_SET_SCALE1_BASE    = 146,
564     NPU_SET_SCALE1_LENGTH  = 147,
565 };
566 
567 enum class cmd_ctrl : uint8_t
568 {
569     CMD0_CTRL = 0,
570     CMD1_CTRL = 1,
571 };
572 
573 enum class custom_dma : uint8_t
574 {
575     NOT_IMPLEMENTED = 0,
576     IMPLEMENTED     = 1,
577 };
578 
579 enum class dma_fault_src : uint8_t
580 {
581     AXI_M0 = 0,
582     AXI_M1 = 1,
583 };
584 
585 enum class dma_region_mode : uint8_t
586 {
587     EXTERNAL = 0,
588     INTERNAL = 1,
589 };
590 
591 enum class dma_stride_mode : uint8_t
592 {
593     D1 = 0,
594     D2 = 1,
595     D3 = 2,
596 };
597 
598 enum class elementwise_mode : uint8_t
599 {
600     MUL   = 0,
601     ADD   = 1,
602     SUB   = 2,
603     MIN   = 3,
604     MAX   = 4,
605     LRELU = 5,
606     ABS   = 6,
607     CLZ   = 7,
608     SHR   = 8,
609     SHL   = 9,
610 };
611 
612 enum class functional_safety : uint8_t
613 {
614     NOT_IMPLEMENTED = 0,
615     IMPLEMENTED     = 1,
616 };
617 
618 enum class ifm2_operand_order : uint8_t
619 {
620     ORDER_B = 0,
621     ORDER_A = 1,
622 };
623 
624 enum class ifm_scale_mode : uint8_t
625 {
626     OPA_OPB_16 = 0,
627     OPA_32     = 1,
628     OPB_32     = 2,
629 };
630 
631 enum class ifm_upscale_mode : uint8_t
632 {
633     NONE    = 0,
634     NEAREST = 1,
635     ZEROS   = 2,
636 };
637 
638 enum class kernel_decomposition : uint8_t
639 {
640     D8X8 = 0,
641     D4X4 = 1,
642 };
643 
644 enum class kernel_dilation : uint8_t
645 {
646     NONE = 0,
647     X2   = 1,
648 };
649 
650 enum class max_beats : uint8_t
651 {
652     B64  = 0,
653     B128 = 1,
654     B256 = 2,
655 };
656 
657 enum class mem_attr : uint8_t
658 {
659     AXI0_OUTSTANDING_COUNTER0 = 0,
660     AXI0_OUTSTANDING_COUNTER1 = 1,
661     AXI1_OUTSTANDING_COUNTER2 = 2,
662     AXI1_OUTSTANDING_COUNTER3 = 3,
663 };
664 
665 enum class ofm_scale_mode : uint8_t
666 {
667     PER_CHANNEL = 0,
668     GLOBAL      = 1,
669 };
670 
671 enum class parallel_mode : uint8_t
672 {
673     SINGLE_CORE     = 0,
674     DUAL_CORE_DEPTH = 1,
675 };
676 
677 enum class pmu_axi_channel : uint8_t
678 {
679     RD_CMD        = 0,
680     RD_IFM        = 1,
681     RD_WEIGHTS    = 2,
682     RD_SCALE_BIAS = 3,
683     RD_MEM2MEM    = 4,
684     WR_OFM        = 8,
685     WR_MEM2MEM    = 9,
686 };
687 
688 enum class pmu_event : uint16_t
689 {
690     NO_EVENT                     = 0,
691     CYCLE                        = 17,
692     NPU_IDLE                     = 32,
693     CC_STALLED_ON_BLOCKDEP       = 33,
694     CC_STALLED_ON_SHRAM_RECONFIG = 34,
695     NPU_ACTIVE                   = 35,
696     MAC_ACTIVE                   = 48,
697     MAC_ACTIVE_8BIT              = 49,
698     MAC_ACTIVE_16BIT             = 50,
699     MAC_DPU_ACTIVE               = 51,
700     MAC_STALLED_BY_WD_ACC        = 52,
701     MAC_STALLED_BY_WD            = 53,
702     MAC_STALLED_BY_ACC           = 54,
703     MAC_STALLED_BY_IB            = 55,
704     MAC_ACTIVE_32BIT             = 56,
705     MAC_STALLED_BY_INT_W         = 57,
706     MAC_STALLED_BY_INT_ACC       = 58,
707     AO_ACTIVE                    = 64,
708     AO_ACTIVE_8BIT               = 65,
709     AO_ACTIVE_16BIT              = 66,
710     AO_STALLED_BY_OFMP_OB        = 67,
711     AO_STALLED_BY_OFMP           = 68,
712     AO_STALLED_BY_OB             = 69,
713     AO_STALLED_BY_ACC_IB         = 70,
714     AO_STALLED_BY_ACC            = 71,
715     AO_STALLED_BY_IB             = 72,
716     WD_ACTIVE                    = 80,
717     WD_STALLED                   = 81,
718     WD_STALLED_BY_WS             = 82,
719     WD_STALLED_BY_WD_BUF         = 83,
720     WD_PARSE_ACTIVE              = 84,
721     WD_PARSE_STALLED             = 85,
722     WD_PARSE_STALLED_IN          = 86,
723     WD_PARSE_STALLED_OUT         = 87,
724     WD_TRANS_WS                  = 88,
725     WD_TRANS_WB                  = 89,
726     WD_TRANS_DW0                 = 90,
727     WD_TRANS_DW1                 = 91,
728     AXI0_RD_TRANS_ACCEPTED       = 128,
729     AXI0_RD_TRANS_COMPLETED      = 129,
730     AXI0_RD_DATA_BEAT_RECEIVED   = 130,
731     AXI0_RD_TRAN_REQ_STALLED     = 131,
732     AXI0_WR_TRANS_ACCEPTED       = 132,
733     AXI0_WR_TRANS_COMPLETED_M    = 133,
734     AXI0_WR_TRANS_COMPLETED_S    = 134,
735     AXI0_WR_DATA_BEAT_WRITTEN    = 135,
736     AXI0_WR_TRAN_REQ_STALLED     = 136,
737     AXI0_WR_DATA_BEAT_STALLED    = 137,
738     AXI0_ENABLED_CYCLES          = 140,
739     AXI0_RD_STALL_LIMIT          = 142,
740     AXI0_WR_STALL_LIMIT          = 143,
741     AXI_LATENCY_ANY              = 160,
742     AXI_LATENCY_32               = 161,
743     AXI_LATENCY_64               = 162,
744     AXI_LATENCY_128              = 163,
745     AXI_LATENCY_256              = 164,
746     AXI_LATENCY_512              = 165,
747     AXI_LATENCY_1024             = 166,
748     ECC_DMA                      = 176,
749     ECC_SB0                      = 177,
750     AXI1_RD_TRANS_ACCEPTED       = 384,
751     AXI1_RD_TRANS_COMPLETED      = 385,
752     AXI1_RD_DATA_BEAT_RECEIVED   = 386,
753     AXI1_RD_TRAN_REQ_STALLED     = 387,
754     AXI1_WR_TRANS_ACCEPTED       = 388,
755     AXI1_WR_TRANS_COMPLETED_M    = 389,
756     AXI1_WR_TRANS_COMPLETED_S    = 390,
757     AXI1_WR_DATA_BEAT_WRITTEN    = 391,
758     AXI1_WR_TRAN_REQ_STALLED     = 392,
759     AXI1_WR_DATA_BEAT_STALLED    = 393,
760     AXI1_ENABLED_CYCLES          = 396,
761     AXI1_RD_STALL_LIMIT          = 398,
762     AXI1_WR_STALL_LIMIT          = 399,
763     ECC_SB1                      = 433,
764 };
765 
766 enum class pooling_mode : uint8_t
767 {
768     MAX        = 0,
769     AVERAGE    = 1,
770     REDUCE_SUM = 2,
771 };
772 
773 enum class privilege_level : uint8_t
774 {
775     USER       = 0,
776     PRIVILEGED = 1,
777 };
778 
779 enum class round_mode : uint8_t
780 {
781     DBL      = 0,
782     TRUNCATE = 1,
783     NATURAL  = 2,
784 };
785 
786 enum class security_level : uint8_t
787 {
788     SECURE     = 0,
789     NON_SECURE = 1,
790 };
791 
792 enum class state : uint8_t
793 {
794     STOPPED = 0,
795     RUNNING = 1,
796 };
797 
798 enum class wd_core_slice_state : uint8_t
799 {
800     HEADER  = 0,
801     PALETTE = 1,
802     WEIGHTS = 2,
803 };
804 
805 enum class wd_ctrl_state : uint8_t
806 {
807     IDLE     = 0,
808     DRAIN    = 1,
809     OFD_INIT = 2,
810     OFD_RUN  = 3,
811 };
812 
813 enum class weight_order : uint8_t
814 {
815     DEPTH_FIRST       = 0,
816     PART_KERNEL_FIRST = 1,
817 };
818 
819 #else
820 
821 enum acc_format
822 {
823     ACC_FORMAT_I32 = 0,
824     ACC_FORMAT_I40 = 1,
825     ACC_FORMAT_F16 = 2,
826 };
827 
828 enum activation_clip_range
829 {
830     ACTIVATION_CLIP_RANGE_OFM_PRECISION = 0,
831     ACTIVATION_CLIP_RANGE_FORCE_UINT8   = 2,
832     ACTIVATION_CLIP_RANGE_FORCE_INT8    = 3,
833     ACTIVATION_CLIP_RANGE_FORCE_INT16   = 5,
834 };
835 
836 enum activation_format
837 {
838     ACTIVATION_FORMAT_NHWC    = 0,
839     ACTIVATION_FORMAT_NHCWB16 = 1,
840 };
841 
842 enum activation_function
843 {
844     ACTIVATION_FUNCTION_RELU    = 0,
845     ACTIVATION_FUNCTION_TANH    = 3,
846     ACTIVATION_FUNCTION_SIGMOID = 4,
847     ACTIVATION_FUNCTION_TABLE_0 = 16,
848     ACTIVATION_FUNCTION_TABLE_1 = 17,
849     ACTIVATION_FUNCTION_TABLE_2 = 18,
850     ACTIVATION_FUNCTION_TABLE_3 = 19,
851     ACTIVATION_FUNCTION_TABLE_4 = 20,
852     ACTIVATION_FUNCTION_TABLE_5 = 21,
853     ACTIVATION_FUNCTION_TABLE_6 = 22,
854     ACTIVATION_FUNCTION_TABLE_7 = 23,
855 };
856 
857 enum activation_precision
858 {
859     ACTIVATION_PRECISION_B8  = 0,
860     ACTIVATION_PRECISION_B16 = 1,
861     ACTIVATION_PRECISION_B32 = 2,
862     ACTIVATION_PRECISION_B64 = 3,
863 };
864 
865 enum activation_type
866 {
867     ACTIVATION_TYPE_UNSIGNED = 0,
868     ACTIVATION_TYPE_SIGNED   = 1,
869 };
870 
871 enum axi_mem_encoding
872 {
873     AXI_MEM_ENCODING_DEVICE_NON_BUFFERABLE                 = 0,
874     AXI_MEM_ENCODING_DEVICE_BUFFERABLE                     = 1,
875     AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_NON_BUFFERABLE   = 2,
876     AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_BUFFERABLE       = 3,
877     AXI_MEM_ENCODING_WRITE_THROUGH_NO_ALLOCATE             = 4,
878     AXI_MEM_ENCODING_WRITE_THROUGH_READ_ALLOCATE           = 5,
879     AXI_MEM_ENCODING_WRITE_THROUGH_WRITE_ALLOCATE          = 6,
880     AXI_MEM_ENCODING_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7,
881     AXI_MEM_ENCODING_WRITE_BACK_NO_ALLOCATE                = 8,
882     AXI_MEM_ENCODING_WRITE_BACK_READ_ALLOCATE              = 9,
883     AXI_MEM_ENCODING_WRITE_BACK_WRITE_ALLOCATE             = 10,
884     AXI_MEM_ENCODING_WRITE_BACK_READ_AND_WRITE_ALLOCATE    = 11,
885 };
886 
887 enum broadcast_mode
888 {
889     BROADCAST_MODE_DISABLE = 0,
890     BROADCAST_MODE_ENABLE  = 1,
891 };
892 
893 enum cmd0_opcode
894 {
895     CMD0_OPCODE_NPU_OP_STOP               = 0,
896     CMD0_OPCODE_NPU_OP_IRQ                = 1,
897     CMD0_OPCODE_NPU_OP_CONV               = 2,
898     CMD0_OPCODE_NPU_OP_DEPTHWISE          = 3,
899     CMD0_OPCODE_NPU_OP_POOL               = 5,
900     CMD0_OPCODE_NPU_OP_ELEMENTWISE        = 6,
901     CMD0_OPCODE_NPU_OP_DMA_START          = 16,
902     CMD0_OPCODE_NPU_OP_DMA_WAIT           = 17,
903     CMD0_OPCODE_NPU_OP_KERNEL_WAIT        = 18,
904     CMD0_OPCODE_NPU_OP_PMU_MASK           = 19,
905     CMD0_OPCODE_NPU_SET_IFM_PAD_TOP       = 256,
906     CMD0_OPCODE_NPU_SET_IFM_PAD_LEFT      = 257,
907     CMD0_OPCODE_NPU_SET_IFM_PAD_RIGHT     = 258,
908     CMD0_OPCODE_NPU_SET_IFM_PAD_BOTTOM    = 259,
909     CMD0_OPCODE_NPU_SET_IFM_DEPTH_M1      = 260,
910     CMD0_OPCODE_NPU_SET_IFM_PRECISION     = 261,
911     CMD0_OPCODE_NPU_SET_IFM_UPSCALE       = 263,
912     CMD0_OPCODE_NPU_SET_IFM_ZERO_POINT    = 265,
913     CMD0_OPCODE_NPU_SET_IFM_WIDTH0_M1     = 266,
914     CMD0_OPCODE_NPU_SET_IFM_HEIGHT0_M1    = 267,
915     CMD0_OPCODE_NPU_SET_IFM_HEIGHT1_M1    = 268,
916     CMD0_OPCODE_NPU_SET_IFM_IB_END        = 269,
917     CMD0_OPCODE_NPU_SET_IFM_REGION        = 271,
918     CMD0_OPCODE_NPU_SET_OFM_WIDTH_M1      = 273,
919     CMD0_OPCODE_NPU_SET_OFM_HEIGHT_M1     = 274,
920     CMD0_OPCODE_NPU_SET_OFM_DEPTH_M1      = 275,
921     CMD0_OPCODE_NPU_SET_OFM_PRECISION     = 276,
922     CMD0_OPCODE_NPU_SET_OFM_BLK_WIDTH_M1  = 277,
923     CMD0_OPCODE_NPU_SET_OFM_BLK_HEIGHT_M1 = 278,
924     CMD0_OPCODE_NPU_SET_OFM_BLK_DEPTH_M1  = 279,
925     CMD0_OPCODE_NPU_SET_OFM_ZERO_POINT    = 280,
926     CMD0_OPCODE_NPU_SET_OFM_WIDTH0_M1     = 282,
927     CMD0_OPCODE_NPU_SET_OFM_HEIGHT0_M1    = 283,
928     CMD0_OPCODE_NPU_SET_OFM_HEIGHT1_M1    = 284,
929     CMD0_OPCODE_NPU_SET_OFM_REGION        = 287,
930     CMD0_OPCODE_NPU_SET_KERNEL_WIDTH_M1   = 288,
931     CMD0_OPCODE_NPU_SET_KERNEL_HEIGHT_M1  = 289,
932     CMD0_OPCODE_NPU_SET_KERNEL_STRIDE     = 290,
933     CMD0_OPCODE_NPU_SET_PARALLEL_MODE     = 291,
934     CMD0_OPCODE_NPU_SET_ACC_FORMAT        = 292,
935     CMD0_OPCODE_NPU_SET_ACTIVATION        = 293,
936     CMD0_OPCODE_NPU_SET_ACTIVATION_MIN    = 294,
937     CMD0_OPCODE_NPU_SET_ACTIVATION_MAX    = 295,
938     CMD0_OPCODE_NPU_SET_WEIGHT_REGION     = 296,
939     CMD0_OPCODE_NPU_SET_SCALE_REGION      = 297,
940     CMD0_OPCODE_NPU_SET_AB_START          = 301,
941     CMD0_OPCODE_NPU_SET_BLOCKDEP          = 303,
942     CMD0_OPCODE_NPU_SET_DMA0_SRC_REGION   = 304,
943     CMD0_OPCODE_NPU_SET_DMA0_DST_REGION   = 305,
944     CMD0_OPCODE_NPU_SET_DMA0_SIZE0        = 306,
945     CMD0_OPCODE_NPU_SET_DMA0_SIZE1        = 307,
946     CMD0_OPCODE_NPU_SET_IFM2_BROADCAST    = 384,
947     CMD0_OPCODE_NPU_SET_IFM2_SCALAR       = 385,
948     CMD0_OPCODE_NPU_SET_IFM2_PRECISION    = 389,
949     CMD0_OPCODE_NPU_SET_IFM2_ZERO_POINT   = 393,
950     CMD0_OPCODE_NPU_SET_IFM2_WIDTH0_M1    = 394,
951     CMD0_OPCODE_NPU_SET_IFM2_HEIGHT0_M1   = 395,
952     CMD0_OPCODE_NPU_SET_IFM2_HEIGHT1_M1   = 396,
953     CMD0_OPCODE_NPU_SET_IFM2_IB_START     = 397,
954     CMD0_OPCODE_NPU_SET_IFM2_REGION       = 399,
955 };
956 
957 enum cmd1_opcode
958 {
959     CMD1_OPCODE_NPU_SET_IFM_BASE0      = 0,
960     CMD1_OPCODE_NPU_SET_IFM_BASE1      = 1,
961     CMD1_OPCODE_NPU_SET_IFM_BASE2      = 2,
962     CMD1_OPCODE_NPU_SET_IFM_BASE3      = 3,
963     CMD1_OPCODE_NPU_SET_IFM_STRIDE_X   = 4,
964     CMD1_OPCODE_NPU_SET_IFM_STRIDE_Y   = 5,
965     CMD1_OPCODE_NPU_SET_IFM_STRIDE_C   = 6,
966     CMD1_OPCODE_NPU_SET_OFM_BASE0      = 16,
967     CMD1_OPCODE_NPU_SET_OFM_BASE1      = 17,
968     CMD1_OPCODE_NPU_SET_OFM_BASE2      = 18,
969     CMD1_OPCODE_NPU_SET_OFM_BASE3      = 19,
970     CMD1_OPCODE_NPU_SET_OFM_STRIDE_X   = 20,
971     CMD1_OPCODE_NPU_SET_OFM_STRIDE_Y   = 21,
972     CMD1_OPCODE_NPU_SET_OFM_STRIDE_C   = 22,
973     CMD1_OPCODE_NPU_SET_WEIGHT_BASE    = 32,
974     CMD1_OPCODE_NPU_SET_WEIGHT_LENGTH  = 33,
975     CMD1_OPCODE_NPU_SET_SCALE_BASE     = 34,
976     CMD1_OPCODE_NPU_SET_SCALE_LENGTH   = 35,
977     CMD1_OPCODE_NPU_SET_OFM_SCALE      = 36,
978     CMD1_OPCODE_NPU_SET_OPA_SCALE      = 37,
979     CMD1_OPCODE_NPU_SET_OPB_SCALE      = 38,
980     CMD1_OPCODE_NPU_SET_DMA0_SRC       = 48,
981     CMD1_OPCODE_NPU_SET_DMA0_DST       = 49,
982     CMD1_OPCODE_NPU_SET_DMA0_LEN       = 50,
983     CMD1_OPCODE_NPU_SET_DMA0_SKIP0     = 51,
984     CMD1_OPCODE_NPU_SET_DMA0_SKIP1     = 52,
985     CMD1_OPCODE_NPU_SET_IFM2_BASE0     = 128,
986     CMD1_OPCODE_NPU_SET_IFM2_BASE1     = 129,
987     CMD1_OPCODE_NPU_SET_IFM2_BASE2     = 130,
988     CMD1_OPCODE_NPU_SET_IFM2_BASE3     = 131,
989     CMD1_OPCODE_NPU_SET_IFM2_STRIDE_X  = 132,
990     CMD1_OPCODE_NPU_SET_IFM2_STRIDE_Y  = 133,
991     CMD1_OPCODE_NPU_SET_IFM2_STRIDE_C  = 134,
992     CMD1_OPCODE_NPU_SET_WEIGHT1_BASE   = 144,
993     CMD1_OPCODE_NPU_SET_WEIGHT1_LENGTH = 145,
994     CMD1_OPCODE_NPU_SET_SCALE1_BASE    = 146,
995     CMD1_OPCODE_NPU_SET_SCALE1_LENGTH  = 147,
996 };
997 
998 enum cmd_ctrl
999 {
1000     CMD_CTRL_CMD0_CTRL = 0,
1001     CMD_CTRL_CMD1_CTRL = 1,
1002 };
1003 
1004 enum custom_dma
1005 {
1006     CUSTOM_DMA_NOT_IMPLEMENTED = 0,
1007     CUSTOM_DMA_IMPLEMENTED     = 1,
1008 };
1009 
1010 enum dma_fault_src
1011 {
1012     DMA_FAULT_SRC_AXI_M0 = 0,
1013     DMA_FAULT_SRC_AXI_M1 = 1,
1014 };
1015 
1016 enum dma_region_mode
1017 {
1018     DMA_REGION_MODE_EXTERNAL = 0,
1019     DMA_REGION_MODE_INTERNAL = 1,
1020 };
1021 
1022 enum dma_stride_mode
1023 {
1024     DMA_STRIDE_MODE_D1 = 0,
1025     DMA_STRIDE_MODE_D2 = 1,
1026     DMA_STRIDE_MODE_D3 = 2,
1027 };
1028 
1029 enum elementwise_mode
1030 {
1031     ELEMENTWISE_MODE_MUL   = 0,
1032     ELEMENTWISE_MODE_ADD   = 1,
1033     ELEMENTWISE_MODE_SUB   = 2,
1034     ELEMENTWISE_MODE_MIN   = 3,
1035     ELEMENTWISE_MODE_MAX   = 4,
1036     ELEMENTWISE_MODE_LRELU = 5,
1037     ELEMENTWISE_MODE_ABS   = 6,
1038     ELEMENTWISE_MODE_CLZ   = 7,
1039     ELEMENTWISE_MODE_SHR   = 8,
1040     ELEMENTWISE_MODE_SHL   = 9,
1041 };
1042 
1043 enum functional_safety
1044 {
1045     FUNCTIONAL_SAFETY_NOT_IMPLEMENTED = 0,
1046     FUNCTIONAL_SAFETY_IMPLEMENTED     = 1,
1047 };
1048 
1049 enum ifm2_operand_order
1050 {
1051     IFM2_OPERAND_ORDER_ORDER_B = 0,
1052     IFM2_OPERAND_ORDER_ORDER_A = 1,
1053 };
1054 
1055 enum ifm_scale_mode
1056 {
1057     IFM_SCALE_MODE_OPA_OPB_16 = 0,
1058     IFM_SCALE_MODE_OPA_32     = 1,
1059     IFM_SCALE_MODE_OPB_32     = 2,
1060 };
1061 
1062 enum ifm_upscale_mode
1063 {
1064     IFM_UPSCALE_MODE_NONE    = 0,
1065     IFM_UPSCALE_MODE_NEAREST = 1,
1066     IFM_UPSCALE_MODE_ZEROS   = 2,
1067 };
1068 
1069 enum kernel_decomposition
1070 {
1071     KERNEL_DECOMPOSITION_D8X8 = 0,
1072     KERNEL_DECOMPOSITION_D4X4 = 1,
1073 };
1074 
1075 enum kernel_dilation
1076 {
1077     KERNEL_DILATION_NONE = 0,
1078     KERNEL_DILATION_X2   = 1,
1079 };
1080 
1081 enum max_beats
1082 {
1083     MAX_BEATS_B64  = 0,
1084     MAX_BEATS_B128 = 1,
1085     MAX_BEATS_B256 = 2,
1086 };
1087 
1088 enum mem_attr
1089 {
1090     MEM_ATTR_AXI0_OUTSTANDING_COUNTER0 = 0,
1091     MEM_ATTR_AXI0_OUTSTANDING_COUNTER1 = 1,
1092     MEM_ATTR_AXI1_OUTSTANDING_COUNTER2 = 2,
1093     MEM_ATTR_AXI1_OUTSTANDING_COUNTER3 = 3,
1094 };
1095 
1096 enum ofm_scale_mode
1097 {
1098     OFM_SCALE_MODE_PER_CHANNEL = 0,
1099     OFM_SCALE_MODE_GLOBAL      = 1,
1100 };
1101 
1102 enum parallel_mode
1103 {
1104     PARALLEL_MODE_SINGLE_CORE     = 0,
1105     PARALLEL_MODE_DUAL_CORE_DEPTH = 1,
1106 };
1107 
1108 enum pmu_axi_channel
1109 {
1110     PMU_AXI_CHANNEL_RD_CMD        = 0,
1111     PMU_AXI_CHANNEL_RD_IFM        = 1,
1112     PMU_AXI_CHANNEL_RD_WEIGHTS    = 2,
1113     PMU_AXI_CHANNEL_RD_SCALE_BIAS = 3,
1114     PMU_AXI_CHANNEL_RD_MEM2MEM    = 4,
1115     PMU_AXI_CHANNEL_WR_OFM        = 8,
1116     PMU_AXI_CHANNEL_WR_MEM2MEM    = 9,
1117 };
1118 
1119 enum pmu_event
1120 {
1121     PMU_EVENT_NO_EVENT                     = 0,
1122     PMU_EVENT_CYCLE                        = 17,
1123     PMU_EVENT_NPU_IDLE                     = 32,
1124     PMU_EVENT_CC_STALLED_ON_BLOCKDEP       = 33,
1125     PMU_EVENT_CC_STALLED_ON_SHRAM_RECONFIG = 34,
1126     PMU_EVENT_NPU_ACTIVE                   = 35,
1127     PMU_EVENT_MAC_ACTIVE                   = 48,
1128     PMU_EVENT_MAC_ACTIVE_8BIT              = 49,
1129     PMU_EVENT_MAC_ACTIVE_16BIT             = 50,
1130     PMU_EVENT_MAC_DPU_ACTIVE               = 51,
1131     PMU_EVENT_MAC_STALLED_BY_WD_ACC        = 52,
1132     PMU_EVENT_MAC_STALLED_BY_WD            = 53,
1133     PMU_EVENT_MAC_STALLED_BY_ACC           = 54,
1134     PMU_EVENT_MAC_STALLED_BY_IB            = 55,
1135     PMU_EVENT_MAC_ACTIVE_32BIT             = 56,
1136     PMU_EVENT_MAC_STALLED_BY_INT_W         = 57,
1137     PMU_EVENT_MAC_STALLED_BY_INT_ACC       = 58,
1138     PMU_EVENT_AO_ACTIVE                    = 64,
1139     PMU_EVENT_AO_ACTIVE_8BIT               = 65,
1140     PMU_EVENT_AO_ACTIVE_16BIT              = 66,
1141     PMU_EVENT_AO_STALLED_BY_OFMP_OB        = 67,
1142     PMU_EVENT_AO_STALLED_BY_OFMP           = 68,
1143     PMU_EVENT_AO_STALLED_BY_OB             = 69,
1144     PMU_EVENT_AO_STALLED_BY_ACC_IB         = 70,
1145     PMU_EVENT_AO_STALLED_BY_ACC            = 71,
1146     PMU_EVENT_AO_STALLED_BY_IB             = 72,
1147     PMU_EVENT_WD_ACTIVE                    = 80,
1148     PMU_EVENT_WD_STALLED                   = 81,
1149     PMU_EVENT_WD_STALLED_BY_WS             = 82,
1150     PMU_EVENT_WD_STALLED_BY_WD_BUF         = 83,
1151     PMU_EVENT_WD_PARSE_ACTIVE              = 84,
1152     PMU_EVENT_WD_PARSE_STALLED             = 85,
1153     PMU_EVENT_WD_PARSE_STALLED_IN          = 86,
1154     PMU_EVENT_WD_PARSE_STALLED_OUT         = 87,
1155     PMU_EVENT_WD_TRANS_WS                  = 88,
1156     PMU_EVENT_WD_TRANS_WB                  = 89,
1157     PMU_EVENT_WD_TRANS_DW0                 = 90,
1158     PMU_EVENT_WD_TRANS_DW1                 = 91,
1159     PMU_EVENT_AXI0_RD_TRANS_ACCEPTED       = 128,
1160     PMU_EVENT_AXI0_RD_TRANS_COMPLETED      = 129,
1161     PMU_EVENT_AXI0_RD_DATA_BEAT_RECEIVED   = 130,
1162     PMU_EVENT_AXI0_RD_TRAN_REQ_STALLED     = 131,
1163     PMU_EVENT_AXI0_WR_TRANS_ACCEPTED       = 132,
1164     PMU_EVENT_AXI0_WR_TRANS_COMPLETED_M    = 133,
1165     PMU_EVENT_AXI0_WR_TRANS_COMPLETED_S    = 134,
1166     PMU_EVENT_AXI0_WR_DATA_BEAT_WRITTEN    = 135,
1167     PMU_EVENT_AXI0_WR_TRAN_REQ_STALLED     = 136,
1168     PMU_EVENT_AXI0_WR_DATA_BEAT_STALLED    = 137,
1169     PMU_EVENT_AXI0_ENABLED_CYCLES          = 140,
1170     PMU_EVENT_AXI0_RD_STALL_LIMIT          = 142,
1171     PMU_EVENT_AXI0_WR_STALL_LIMIT          = 143,
1172     PMU_EVENT_AXI_LATENCY_ANY              = 160,
1173     PMU_EVENT_AXI_LATENCY_32               = 161,
1174     PMU_EVENT_AXI_LATENCY_64               = 162,
1175     PMU_EVENT_AXI_LATENCY_128              = 163,
1176     PMU_EVENT_AXI_LATENCY_256              = 164,
1177     PMU_EVENT_AXI_LATENCY_512              = 165,
1178     PMU_EVENT_AXI_LATENCY_1024             = 166,
1179     PMU_EVENT_ECC_DMA                      = 176,
1180     PMU_EVENT_ECC_SB0                      = 177,
1181     PMU_EVENT_AXI1_RD_TRANS_ACCEPTED       = 384,
1182     PMU_EVENT_AXI1_RD_TRANS_COMPLETED      = 385,
1183     PMU_EVENT_AXI1_RD_DATA_BEAT_RECEIVED   = 386,
1184     PMU_EVENT_AXI1_RD_TRAN_REQ_STALLED     = 387,
1185     PMU_EVENT_AXI1_WR_TRANS_ACCEPTED       = 388,
1186     PMU_EVENT_AXI1_WR_TRANS_COMPLETED_M    = 389,
1187     PMU_EVENT_AXI1_WR_TRANS_COMPLETED_S    = 390,
1188     PMU_EVENT_AXI1_WR_DATA_BEAT_WRITTEN    = 391,
1189     PMU_EVENT_AXI1_WR_TRAN_REQ_STALLED     = 392,
1190     PMU_EVENT_AXI1_WR_DATA_BEAT_STALLED    = 393,
1191     PMU_EVENT_AXI1_ENABLED_CYCLES          = 396,
1192     PMU_EVENT_AXI1_RD_STALL_LIMIT          = 398,
1193     PMU_EVENT_AXI1_WR_STALL_LIMIT          = 399,
1194     PMU_EVENT_ECC_SB1                      = 433,
1195 };
1196 
1197 enum pooling_mode
1198 {
1199     POOLING_MODE_MAX        = 0,
1200     POOLING_MODE_AVERAGE    = 1,
1201     POOLING_MODE_REDUCE_SUM = 2,
1202 };
1203 
1204 enum privilege_level
1205 {
1206     PRIVILEGE_LEVEL_USER       = 0,
1207     PRIVILEGE_LEVEL_PRIVILEGED = 1,
1208 };
1209 
1210 enum round_mode
1211 {
1212     ROUND_MODE_DBL      = 0,
1213     ROUND_MODE_TRUNCATE = 1,
1214     ROUND_MODE_NATURAL  = 2,
1215 };
1216 
1217 enum security_level
1218 {
1219     SECURITY_LEVEL_SECURE     = 0,
1220     SECURITY_LEVEL_NON_SECURE = 1,
1221 };
1222 
1223 enum state
1224 {
1225     STATE_STOPPED = 0,
1226     STATE_RUNNING = 1,
1227 };
1228 
1229 enum wd_core_slice_state
1230 {
1231     WD_CORE_SLICE_STATE_HEADER  = 0,
1232     WD_CORE_SLICE_STATE_PALETTE = 1,
1233     WD_CORE_SLICE_STATE_WEIGHTS = 2,
1234 };
1235 
1236 enum wd_ctrl_state
1237 {
1238     WD_CTRL_STATE_IDLE     = 0,
1239     WD_CTRL_STATE_DRAIN    = 1,
1240     WD_CTRL_STATE_OFD_INIT = 2,
1241     WD_CTRL_STATE_OFD_RUN  = 3,
1242 };
1243 
1244 enum weight_order
1245 {
1246     WEIGHT_ORDER_DEPTH_FIRST       = 0,
1247     WEIGHT_ORDER_PART_KERNEL_FIRST = 1,
1248 };
1249 
1250 #endif
1251 
1252 #ifdef NPU_DISASSEMBLE
1253 
1254 static const char *acc_format_str[] = {
1255     "ACC_FORMAT_I32",
1256     "ACC_FORMAT_I40",
1257     "ACC_FORMAT_F16",
1258 };
1259 
1260 static const char *activation_clip_range_str[] = {
1261     "ACTIVATION_CLIP_RANGE_OFM_PRECISION",
1262     "****",
1263     "ACTIVATION_CLIP_RANGE_FORCE_UINT8",
1264     "ACTIVATION_CLIP_RANGE_FORCE_INT8",
1265     "****",
1266     "ACTIVATION_CLIP_RANGE_FORCE_INT16",
1267 };
1268 
1269 static const char *activation_format_str[] = {
1270     "ACTIVATION_FORMAT_NHWC",
1271     "ACTIVATION_FORMAT_NHCWB16",
1272 };
1273 
1274 static const char *activation_function_str[] = {
1275     "ACTIVATION_FUNCTION_RELU",
1276     "****",
1277     "****",
1278     "ACTIVATION_FUNCTION_TANH",
1279     "ACTIVATION_FUNCTION_SIGMOID",
1280     "****",
1281     "****",
1282     "****",
1283     "****",
1284     "****",
1285     "****",
1286     "****",
1287     "****",
1288     "****",
1289     "****",
1290     "****",
1291     "ACTIVATION_FUNCTION_TABLE_0",
1292     "ACTIVATION_FUNCTION_TABLE_1",
1293     "ACTIVATION_FUNCTION_TABLE_2",
1294     "ACTIVATION_FUNCTION_TABLE_3",
1295     "ACTIVATION_FUNCTION_TABLE_4",
1296     "ACTIVATION_FUNCTION_TABLE_5",
1297     "ACTIVATION_FUNCTION_TABLE_6",
1298     "ACTIVATION_FUNCTION_TABLE_7",
1299 };
1300 
1301 static const char *activation_precision_str[] = {
1302     "ACTIVATION_PRECISION_B8",
1303     "ACTIVATION_PRECISION_B16",
1304     "ACTIVATION_PRECISION_B32",
1305     "ACTIVATION_PRECISION_B64",
1306 };
1307 
1308 static const char *activation_type_str[] = {
1309     "ACTIVATION_TYPE_UNSIGNED",
1310     "ACTIVATION_TYPE_SIGNED",
1311 };
1312 
1313 static const char *axi_mem_encoding_str[] = {
1314     "AXI_MEM_ENCODING_DEVICE_NON_BUFFERABLE",
1315     "AXI_MEM_ENCODING_DEVICE_BUFFERABLE",
1316     "AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_NON_BUFFERABLE",
1317     "AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_BUFFERABLE",
1318     "AXI_MEM_ENCODING_WRITE_THROUGH_NO_ALLOCATE",
1319     "AXI_MEM_ENCODING_WRITE_THROUGH_READ_ALLOCATE",
1320     "AXI_MEM_ENCODING_WRITE_THROUGH_WRITE_ALLOCATE",
1321     "AXI_MEM_ENCODING_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE",
1322     "AXI_MEM_ENCODING_WRITE_BACK_NO_ALLOCATE",
1323     "AXI_MEM_ENCODING_WRITE_BACK_READ_ALLOCATE",
1324     "AXI_MEM_ENCODING_WRITE_BACK_WRITE_ALLOCATE",
1325     "AXI_MEM_ENCODING_WRITE_BACK_READ_AND_WRITE_ALLOCATE",
1326 };
1327 
1328 static const char *broadcast_mode_str[] = {
1329     "BROADCAST_MODE_DISABLE",
1330     "BROADCAST_MODE_ENABLE",
1331 };
1332 
1333 static const char *cmd0_opcode_str[] = {
1334     "CMD0_OPCODE_NPU_OP_STOP",
1335     "CMD0_OPCODE_NPU_OP_IRQ",
1336     "CMD0_OPCODE_NPU_OP_CONV",
1337     "CMD0_OPCODE_NPU_OP_DEPTHWISE",
1338     "****",
1339     "CMD0_OPCODE_NPU_OP_POOL",
1340     "CMD0_OPCODE_NPU_OP_ELEMENTWISE",
1341     "****",
1342     "****",
1343     "****",
1344     "****",
1345     "****",
1346     "****",
1347     "****",
1348     "****",
1349     "****",
1350     "CMD0_OPCODE_NPU_OP_DMA_START",
1351     "CMD0_OPCODE_NPU_OP_DMA_WAIT",
1352     "CMD0_OPCODE_NPU_OP_KERNEL_WAIT",
1353     "CMD0_OPCODE_NPU_OP_PMU_MASK",
1354     "****",
1355     "****",
1356     "****",
1357     "****",
1358     "****",
1359     "****",
1360     "****",
1361     "****",
1362     "****",
1363     "****",
1364     "****",
1365     "****",
1366     "****",
1367     "****",
1368     "****",
1369     "****",
1370     "****",
1371     "****",
1372     "****",
1373     "****",
1374     "****",
1375     "****",
1376     "****",
1377     "****",
1378     "****",
1379     "****",
1380     "****",
1381     "****",
1382     "****",
1383     "****",
1384     "****",
1385     "****",
1386     "****",
1387     "****",
1388     "****",
1389     "****",
1390     "****",
1391     "****",
1392     "****",
1393     "****",
1394     "****",
1395     "****",
1396     "****",
1397     "****",
1398     "****",
1399     "****",
1400     "****",
1401     "****",
1402     "****",
1403     "****",
1404     "****",
1405     "****",
1406     "****",
1407     "****",
1408     "****",
1409     "****",
1410     "****",
1411     "****",
1412     "****",
1413     "****",
1414     "****",
1415     "****",
1416     "****",
1417     "****",
1418     "****",
1419     "****",
1420     "****",
1421     "****",
1422     "****",
1423     "****",
1424     "****",
1425     "****",
1426     "****",
1427     "****",
1428     "****",
1429     "****",
1430     "****",
1431     "****",
1432     "****",
1433     "****",
1434     "****",
1435     "****",
1436     "****",
1437     "****",
1438     "****",
1439     "****",
1440     "****",
1441     "****",
1442     "****",
1443     "****",
1444     "****",
1445     "****",
1446     "****",
1447     "****",
1448     "****",
1449     "****",
1450     "****",
1451     "****",
1452     "****",
1453     "****",
1454     "****",
1455     "****",
1456     "****",
1457     "****",
1458     "****",
1459     "****",
1460     "****",
1461     "****",
1462     "****",
1463     "****",
1464     "****",
1465     "****",
1466     "****",
1467     "****",
1468     "****",
1469     "****",
1470     "****",
1471     "****",
1472     "****",
1473     "****",
1474     "****",
1475     "****",
1476     "****",
1477     "****",
1478     "****",
1479     "****",
1480     "****",
1481     "****",
1482     "****",
1483     "****",
1484     "****",
1485     "****",
1486     "****",
1487     "****",
1488     "****",
1489     "****",
1490     "****",
1491     "****",
1492     "****",
1493     "****",
1494     "****",
1495     "****",
1496     "****",
1497     "****",
1498     "****",
1499     "****",
1500     "****",
1501     "****",
1502     "****",
1503     "****",
1504     "****",
1505     "****",
1506     "****",
1507     "****",
1508     "****",
1509     "****",
1510     "****",
1511     "****",
1512     "****",
1513     "****",
1514     "****",
1515     "****",
1516     "****",
1517     "****",
1518     "****",
1519     "****",
1520     "****",
1521     "****",
1522     "****",
1523     "****",
1524     "****",
1525     "****",
1526     "****",
1527     "****",
1528     "****",
1529     "****",
1530     "****",
1531     "****",
1532     "****",
1533     "****",
1534     "****",
1535     "****",
1536     "****",
1537     "****",
1538     "****",
1539     "****",
1540     "****",
1541     "****",
1542     "****",
1543     "****",
1544     "****",
1545     "****",
1546     "****",
1547     "****",
1548     "****",
1549     "****",
1550     "****",
1551     "****",
1552     "****",
1553     "****",
1554     "****",
1555     "****",
1556     "****",
1557     "****",
1558     "****",
1559     "****",
1560     "****",
1561     "****",
1562     "****",
1563     "****",
1564     "****",
1565     "****",
1566     "****",
1567     "****",
1568     "****",
1569     "****",
1570     "****",
1571     "****",
1572     "****",
1573     "****",
1574     "****",
1575     "****",
1576     "****",
1577     "****",
1578     "****",
1579     "****",
1580     "****",
1581     "****",
1582     "****",
1583     "****",
1584     "****",
1585     "****",
1586     "****",
1587     "****",
1588     "****",
1589     "****",
1590     "CMD0_OPCODE_NPU_SET_IFM_PAD_TOP",
1591     "CMD0_OPCODE_NPU_SET_IFM_PAD_LEFT",
1592     "CMD0_OPCODE_NPU_SET_IFM_PAD_RIGHT",
1593     "CMD0_OPCODE_NPU_SET_IFM_PAD_BOTTOM",
1594     "CMD0_OPCODE_NPU_SET_IFM_DEPTH_M1",
1595     "CMD0_OPCODE_NPU_SET_IFM_PRECISION",
1596     "****",
1597     "CMD0_OPCODE_NPU_SET_IFM_UPSCALE",
1598     "****",
1599     "CMD0_OPCODE_NPU_SET_IFM_ZERO_POINT",
1600     "CMD0_OPCODE_NPU_SET_IFM_WIDTH0_M1",
1601     "CMD0_OPCODE_NPU_SET_IFM_HEIGHT0_M1",
1602     "CMD0_OPCODE_NPU_SET_IFM_HEIGHT1_M1",
1603     "CMD0_OPCODE_NPU_SET_IFM_IB_END",
1604     "****",
1605     "CMD0_OPCODE_NPU_SET_IFM_REGION",
1606     "****",
1607     "CMD0_OPCODE_NPU_SET_OFM_WIDTH_M1",
1608     "CMD0_OPCODE_NPU_SET_OFM_HEIGHT_M1",
1609     "CMD0_OPCODE_NPU_SET_OFM_DEPTH_M1",
1610     "CMD0_OPCODE_NPU_SET_OFM_PRECISION",
1611     "CMD0_OPCODE_NPU_SET_OFM_BLK_WIDTH_M1",
1612     "CMD0_OPCODE_NPU_SET_OFM_BLK_HEIGHT_M1",
1613     "CMD0_OPCODE_NPU_SET_OFM_BLK_DEPTH_M1",
1614     "CMD0_OPCODE_NPU_SET_OFM_ZERO_POINT",
1615     "****",
1616     "CMD0_OPCODE_NPU_SET_OFM_WIDTH0_M1",
1617     "CMD0_OPCODE_NPU_SET_OFM_HEIGHT0_M1",
1618     "CMD0_OPCODE_NPU_SET_OFM_HEIGHT1_M1",
1619     "****",
1620     "****",
1621     "CMD0_OPCODE_NPU_SET_OFM_REGION",
1622     "CMD0_OPCODE_NPU_SET_KERNEL_WIDTH_M1",
1623     "CMD0_OPCODE_NPU_SET_KERNEL_HEIGHT_M1",
1624     "CMD0_OPCODE_NPU_SET_KERNEL_STRIDE",
1625     "CMD0_OPCODE_NPU_SET_PARALLEL_MODE",
1626     "CMD0_OPCODE_NPU_SET_ACC_FORMAT",
1627     "CMD0_OPCODE_NPU_SET_ACTIVATION",
1628     "CMD0_OPCODE_NPU_SET_ACTIVATION_MIN",
1629     "CMD0_OPCODE_NPU_SET_ACTIVATION_MAX",
1630     "CMD0_OPCODE_NPU_SET_WEIGHT_REGION",
1631     "CMD0_OPCODE_NPU_SET_SCALE_REGION",
1632     "****",
1633     "****",
1634     "****",
1635     "CMD0_OPCODE_NPU_SET_AB_START",
1636     "****",
1637     "CMD0_OPCODE_NPU_SET_BLOCKDEP",
1638     "CMD0_OPCODE_NPU_SET_DMA0_SRC_REGION",
1639     "CMD0_OPCODE_NPU_SET_DMA0_DST_REGION",
1640     "CMD0_OPCODE_NPU_SET_DMA0_SIZE0",
1641     "CMD0_OPCODE_NPU_SET_DMA0_SIZE1",
1642     "****",
1643     "****",
1644     "****",
1645     "****",
1646     "****",
1647     "****",
1648     "****",
1649     "****",
1650     "****",
1651     "****",
1652     "****",
1653     "****",
1654     "****",
1655     "****",
1656     "****",
1657     "****",
1658     "****",
1659     "****",
1660     "****",
1661     "****",
1662     "****",
1663     "****",
1664     "****",
1665     "****",
1666     "****",
1667     "****",
1668     "****",
1669     "****",
1670     "****",
1671     "****",
1672     "****",
1673     "****",
1674     "****",
1675     "****",
1676     "****",
1677     "****",
1678     "****",
1679     "****",
1680     "****",
1681     "****",
1682     "****",
1683     "****",
1684     "****",
1685     "****",
1686     "****",
1687     "****",
1688     "****",
1689     "****",
1690     "****",
1691     "****",
1692     "****",
1693     "****",
1694     "****",
1695     "****",
1696     "****",
1697     "****",
1698     "****",
1699     "****",
1700     "****",
1701     "****",
1702     "****",
1703     "****",
1704     "****",
1705     "****",
1706     "****",
1707     "****",
1708     "****",
1709     "****",
1710     "****",
1711     "****",
1712     "****",
1713     "****",
1714     "****",
1715     "****",
1716     "****",
1717     "****",
1718     "CMD0_OPCODE_NPU_SET_IFM2_BROADCAST",
1719     "CMD0_OPCODE_NPU_SET_IFM2_SCALAR",
1720     "****",
1721     "****",
1722     "****",
1723     "CMD0_OPCODE_NPU_SET_IFM2_PRECISION",
1724     "****",
1725     "****",
1726     "****",
1727     "CMD0_OPCODE_NPU_SET_IFM2_ZERO_POINT",
1728     "CMD0_OPCODE_NPU_SET_IFM2_WIDTH0_M1",
1729     "CMD0_OPCODE_NPU_SET_IFM2_HEIGHT0_M1",
1730     "CMD0_OPCODE_NPU_SET_IFM2_HEIGHT1_M1",
1731     "CMD0_OPCODE_NPU_SET_IFM2_IB_START",
1732     "****",
1733     "CMD0_OPCODE_NPU_SET_IFM2_REGION",
1734 };
1735 
1736 static const char *cmd1_opcode_str[] = {
1737     "CMD1_OPCODE_NPU_SET_IFM_BASE0",
1738     "CMD1_OPCODE_NPU_SET_IFM_BASE1",
1739     "CMD1_OPCODE_NPU_SET_IFM_BASE2",
1740     "CMD1_OPCODE_NPU_SET_IFM_BASE3",
1741     "CMD1_OPCODE_NPU_SET_IFM_STRIDE_X",
1742     "CMD1_OPCODE_NPU_SET_IFM_STRIDE_Y",
1743     "CMD1_OPCODE_NPU_SET_IFM_STRIDE_C",
1744     "****",
1745     "****",
1746     "****",
1747     "****",
1748     "****",
1749     "****",
1750     "****",
1751     "****",
1752     "****",
1753     "CMD1_OPCODE_NPU_SET_OFM_BASE0",
1754     "CMD1_OPCODE_NPU_SET_OFM_BASE1",
1755     "CMD1_OPCODE_NPU_SET_OFM_BASE2",
1756     "CMD1_OPCODE_NPU_SET_OFM_BASE3",
1757     "CMD1_OPCODE_NPU_SET_OFM_STRIDE_X",
1758     "CMD1_OPCODE_NPU_SET_OFM_STRIDE_Y",
1759     "CMD1_OPCODE_NPU_SET_OFM_STRIDE_C",
1760     "****",
1761     "****",
1762     "****",
1763     "****",
1764     "****",
1765     "****",
1766     "****",
1767     "****",
1768     "****",
1769     "CMD1_OPCODE_NPU_SET_WEIGHT_BASE",
1770     "CMD1_OPCODE_NPU_SET_WEIGHT_LENGTH",
1771     "CMD1_OPCODE_NPU_SET_SCALE_BASE",
1772     "CMD1_OPCODE_NPU_SET_SCALE_LENGTH",
1773     "CMD1_OPCODE_NPU_SET_OFM_SCALE",
1774     "CMD1_OPCODE_NPU_SET_OPA_SCALE",
1775     "CMD1_OPCODE_NPU_SET_OPB_SCALE",
1776     "****",
1777     "****",
1778     "****",
1779     "****",
1780     "****",
1781     "****",
1782     "****",
1783     "****",
1784     "****",
1785     "CMD1_OPCODE_NPU_SET_DMA0_SRC",
1786     "CMD1_OPCODE_NPU_SET_DMA0_DST",
1787     "CMD1_OPCODE_NPU_SET_DMA0_LEN",
1788     "CMD1_OPCODE_NPU_SET_DMA0_SKIP0",
1789     "CMD1_OPCODE_NPU_SET_DMA0_SKIP1",
1790     "****",
1791     "****",
1792     "****",
1793     "****",
1794     "****",
1795     "****",
1796     "****",
1797     "****",
1798     "****",
1799     "****",
1800     "****",
1801     "****",
1802     "****",
1803     "****",
1804     "****",
1805     "****",
1806     "****",
1807     "****",
1808     "****",
1809     "****",
1810     "****",
1811     "****",
1812     "****",
1813     "****",
1814     "****",
1815     "****",
1816     "****",
1817     "****",
1818     "****",
1819     "****",
1820     "****",
1821     "****",
1822     "****",
1823     "****",
1824     "****",
1825     "****",
1826     "****",
1827     "****",
1828     "****",
1829     "****",
1830     "****",
1831     "****",
1832     "****",
1833     "****",
1834     "****",
1835     "****",
1836     "****",
1837     "****",
1838     "****",
1839     "****",
1840     "****",
1841     "****",
1842     "****",
1843     "****",
1844     "****",
1845     "****",
1846     "****",
1847     "****",
1848     "****",
1849     "****",
1850     "****",
1851     "****",
1852     "****",
1853     "****",
1854     "****",
1855     "****",
1856     "****",
1857     "****",
1858     "****",
1859     "****",
1860     "****",
1861     "****",
1862     "****",
1863     "****",
1864     "****",
1865     "CMD1_OPCODE_NPU_SET_IFM2_BASE0",
1866     "CMD1_OPCODE_NPU_SET_IFM2_BASE1",
1867     "CMD1_OPCODE_NPU_SET_IFM2_BASE2",
1868     "CMD1_OPCODE_NPU_SET_IFM2_BASE3",
1869     "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_X",
1870     "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_Y",
1871     "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_C",
1872     "****",
1873     "****",
1874     "****",
1875     "****",
1876     "****",
1877     "****",
1878     "****",
1879     "****",
1880     "****",
1881     "CMD1_OPCODE_NPU_SET_WEIGHT1_BASE",
1882     "CMD1_OPCODE_NPU_SET_WEIGHT1_LENGTH",
1883     "CMD1_OPCODE_NPU_SET_SCALE1_BASE",
1884     "CMD1_OPCODE_NPU_SET_SCALE1_LENGTH",
1885 };
1886 
1887 static const char *cmd_ctrl_str[] = {
1888     "CMD_CTRL_CMD0_CTRL",
1889     "CMD_CTRL_CMD1_CTRL",
1890 };
1891 
1892 static const char *custom_dma_str[] = {
1893     "CUSTOM_DMA_NOT_IMPLEMENTED",
1894     "CUSTOM_DMA_IMPLEMENTED",
1895 };
1896 
1897 static const char *dma_fault_src_str[] = {
1898     "DMA_FAULT_SRC_AXI_M0",
1899     "DMA_FAULT_SRC_AXI_M1",
1900 };
1901 
1902 static const char *dma_region_mode_str[] = {
1903     "DMA_REGION_MODE_EXTERNAL",
1904     "DMA_REGION_MODE_INTERNAL",
1905 };
1906 
1907 static const char *dma_stride_mode_str[] = {
1908     "DMA_STRIDE_MODE_D1",
1909     "DMA_STRIDE_MODE_D2",
1910     "DMA_STRIDE_MODE_D3",
1911 };
1912 
1913 static const char *elementwise_mode_str[] = {
1914     "ELEMENTWISE_MODE_MUL",
1915     "ELEMENTWISE_MODE_ADD",
1916     "ELEMENTWISE_MODE_SUB",
1917     "ELEMENTWISE_MODE_MIN",
1918     "ELEMENTWISE_MODE_MAX",
1919     "ELEMENTWISE_MODE_LRELU",
1920     "ELEMENTWISE_MODE_ABS",
1921     "ELEMENTWISE_MODE_CLZ",
1922     "ELEMENTWISE_MODE_SHR",
1923     "ELEMENTWISE_MODE_SHL",
1924 };
1925 
1926 static const char *functional_safety_str[] = {
1927     "FUNCTIONAL_SAFETY_NOT_IMPLEMENTED",
1928     "FUNCTIONAL_SAFETY_IMPLEMENTED",
1929 };
1930 
1931 static const char *ifm2_operand_order_str[] = {
1932     "IFM2_OPERAND_ORDER_ORDER_B",
1933     "IFM2_OPERAND_ORDER_ORDER_A",
1934 };
1935 
1936 static const char *ifm_scale_mode_str[] = {
1937     "IFM_SCALE_MODE_OPA_OPB_16",
1938     "IFM_SCALE_MODE_OPA_32",
1939     "IFM_SCALE_MODE_OPB_32",
1940 };
1941 
1942 static const char *ifm_upscale_mode_str[] = {
1943     "IFM_UPSCALE_MODE_NONE",
1944     "IFM_UPSCALE_MODE_NEAREST",
1945     "IFM_UPSCALE_MODE_ZEROS",
1946 };
1947 
1948 static const char *kernel_decomposition_str[] = {
1949     "KERNEL_DECOMPOSITION_D8X8",
1950     "KERNEL_DECOMPOSITION_D4X4",
1951 };
1952 
1953 static const char *kernel_dilation_str[] = {
1954     "KERNEL_DILATION_NONE",
1955     "KERNEL_DILATION_X2",
1956 };
1957 
1958 static const char *max_beats_str[] = {
1959     "MAX_BEATS_B64",
1960     "MAX_BEATS_B128",
1961     "MAX_BEATS_B256",
1962 };
1963 
1964 static const char *mem_attr_str[] = {
1965     "MEM_ATTR_AXI0_OUTSTANDING_COUNTER0",
1966     "MEM_ATTR_AXI0_OUTSTANDING_COUNTER1",
1967     "MEM_ATTR_AXI1_OUTSTANDING_COUNTER2",
1968     "MEM_ATTR_AXI1_OUTSTANDING_COUNTER3",
1969 };
1970 
1971 static const char *ofm_scale_mode_str[] = {
1972     "OFM_SCALE_MODE_PER_CHANNEL",
1973     "OFM_SCALE_MODE_GLOBAL",
1974 };
1975 
1976 static const char *parallel_mode_str[] = {
1977     "PARALLEL_MODE_SINGLE_CORE",
1978     "PARALLEL_MODE_DUAL_CORE_DEPTH",
1979 };
1980 
1981 static const char *pmu_axi_channel_str[] = {
1982     "PMU_AXI_CHANNEL_RD_CMD",
1983     "PMU_AXI_CHANNEL_RD_IFM",
1984     "PMU_AXI_CHANNEL_RD_WEIGHTS",
1985     "PMU_AXI_CHANNEL_RD_SCALE_BIAS",
1986     "PMU_AXI_CHANNEL_RD_MEM2MEM",
1987     "****",
1988     "****",
1989     "****",
1990     "PMU_AXI_CHANNEL_WR_OFM",
1991     "PMU_AXI_CHANNEL_WR_MEM2MEM",
1992 };
1993 
1994 static const char *pmu_event_str[] = {
1995     "PMU_EVENT_NO_EVENT",
1996     "****",
1997     "****",
1998     "****",
1999     "****",
2000     "****",
2001     "****",
2002     "****",
2003     "****",
2004     "****",
2005     "****",
2006     "****",
2007     "****",
2008     "****",
2009     "****",
2010     "****",
2011     "****",
2012     "PMU_EVENT_CYCLE",
2013     "****",
2014     "****",
2015     "****",
2016     "****",
2017     "****",
2018     "****",
2019     "****",
2020     "****",
2021     "****",
2022     "****",
2023     "****",
2024     "****",
2025     "****",
2026     "****",
2027     "PMU_EVENT_NPU_IDLE",
2028     "PMU_EVENT_CC_STALLED_ON_BLOCKDEP",
2029     "PMU_EVENT_CC_STALLED_ON_SHRAM_RECONFIG",
2030     "PMU_EVENT_NPU_ACTIVE",
2031     "****",
2032     "****",
2033     "****",
2034     "****",
2035     "****",
2036     "****",
2037     "****",
2038     "****",
2039     "****",
2040     "****",
2041     "****",
2042     "****",
2043     "PMU_EVENT_MAC_ACTIVE",
2044     "PMU_EVENT_MAC_ACTIVE_8BIT",
2045     "PMU_EVENT_MAC_ACTIVE_16BIT",
2046     "PMU_EVENT_MAC_DPU_ACTIVE",
2047     "PMU_EVENT_MAC_STALLED_BY_WD_ACC",
2048     "PMU_EVENT_MAC_STALLED_BY_WD",
2049     "PMU_EVENT_MAC_STALLED_BY_ACC",
2050     "PMU_EVENT_MAC_STALLED_BY_IB",
2051     "PMU_EVENT_MAC_ACTIVE_32BIT",
2052     "PMU_EVENT_MAC_STALLED_BY_INT_W",
2053     "PMU_EVENT_MAC_STALLED_BY_INT_ACC",
2054     "****",
2055     "****",
2056     "****",
2057     "****",
2058     "****",
2059     "PMU_EVENT_AO_ACTIVE",
2060     "PMU_EVENT_AO_ACTIVE_8BIT",
2061     "PMU_EVENT_AO_ACTIVE_16BIT",
2062     "PMU_EVENT_AO_STALLED_BY_OFMP_OB",
2063     "PMU_EVENT_AO_STALLED_BY_OFMP",
2064     "PMU_EVENT_AO_STALLED_BY_OB",
2065     "PMU_EVENT_AO_STALLED_BY_ACC_IB",
2066     "PMU_EVENT_AO_STALLED_BY_ACC",
2067     "PMU_EVENT_AO_STALLED_BY_IB",
2068     "****",
2069     "****",
2070     "****",
2071     "****",
2072     "****",
2073     "****",
2074     "****",
2075     "PMU_EVENT_WD_ACTIVE",
2076     "PMU_EVENT_WD_STALLED",
2077     "PMU_EVENT_WD_STALLED_BY_WS",
2078     "PMU_EVENT_WD_STALLED_BY_WD_BUF",
2079     "PMU_EVENT_WD_PARSE_ACTIVE",
2080     "PMU_EVENT_WD_PARSE_STALLED",
2081     "PMU_EVENT_WD_PARSE_STALLED_IN",
2082     "PMU_EVENT_WD_PARSE_STALLED_OUT",
2083     "PMU_EVENT_WD_TRANS_WS",
2084     "PMU_EVENT_WD_TRANS_WB",
2085     "PMU_EVENT_WD_TRANS_DW0",
2086     "PMU_EVENT_WD_TRANS_DW1",
2087     "****",
2088     "****",
2089     "****",
2090     "****",
2091     "****",
2092     "****",
2093     "****",
2094     "****",
2095     "****",
2096     "****",
2097     "****",
2098     "****",
2099     "****",
2100     "****",
2101     "****",
2102     "****",
2103     "****",
2104     "****",
2105     "****",
2106     "****",
2107     "****",
2108     "****",
2109     "****",
2110     "****",
2111     "****",
2112     "****",
2113     "****",
2114     "****",
2115     "****",
2116     "****",
2117     "****",
2118     "****",
2119     "****",
2120     "****",
2121     "****",
2122     "****",
2123     "PMU_EVENT_AXI0_RD_TRANS_ACCEPTED",
2124     "PMU_EVENT_AXI0_RD_TRANS_COMPLETED",
2125     "PMU_EVENT_AXI0_RD_DATA_BEAT_RECEIVED",
2126     "PMU_EVENT_AXI0_RD_TRAN_REQ_STALLED",
2127     "PMU_EVENT_AXI0_WR_TRANS_ACCEPTED",
2128     "PMU_EVENT_AXI0_WR_TRANS_COMPLETED_M",
2129     "PMU_EVENT_AXI0_WR_TRANS_COMPLETED_S",
2130     "PMU_EVENT_AXI0_WR_DATA_BEAT_WRITTEN",
2131     "PMU_EVENT_AXI0_WR_TRAN_REQ_STALLED",
2132     "PMU_EVENT_AXI0_WR_DATA_BEAT_STALLED",
2133     "****",
2134     "****",
2135     "PMU_EVENT_AXI0_ENABLED_CYCLES",
2136     "****",
2137     "PMU_EVENT_AXI0_RD_STALL_LIMIT",
2138     "PMU_EVENT_AXI0_WR_STALL_LIMIT",
2139     "****",
2140     "****",
2141     "****",
2142     "****",
2143     "****",
2144     "****",
2145     "****",
2146     "****",
2147     "****",
2148     "****",
2149     "****",
2150     "****",
2151     "****",
2152     "****",
2153     "****",
2154     "****",
2155     "PMU_EVENT_AXI_LATENCY_ANY",
2156     "PMU_EVENT_AXI_LATENCY_32",
2157     "PMU_EVENT_AXI_LATENCY_64",
2158     "PMU_EVENT_AXI_LATENCY_128",
2159     "PMU_EVENT_AXI_LATENCY_256",
2160     "PMU_EVENT_AXI_LATENCY_512",
2161     "PMU_EVENT_AXI_LATENCY_1024",
2162     "****",
2163     "****",
2164     "****",
2165     "****",
2166     "****",
2167     "****",
2168     "****",
2169     "****",
2170     "****",
2171     "PMU_EVENT_ECC_DMA",
2172     "PMU_EVENT_ECC_SB0",
2173     "****",
2174     "****",
2175     "****",
2176     "****",
2177     "****",
2178     "****",
2179     "****",
2180     "****",
2181     "****",
2182     "****",
2183     "****",
2184     "****",
2185     "****",
2186     "****",
2187     "****",
2188     "****",
2189     "****",
2190     "****",
2191     "****",
2192     "****",
2193     "****",
2194     "****",
2195     "****",
2196     "****",
2197     "****",
2198     "****",
2199     "****",
2200     "****",
2201     "****",
2202     "****",
2203     "****",
2204     "****",
2205     "****",
2206     "****",
2207     "****",
2208     "****",
2209     "****",
2210     "****",
2211     "****",
2212     "****",
2213     "****",
2214     "****",
2215     "****",
2216     "****",
2217     "****",
2218     "****",
2219     "****",
2220     "****",
2221     "****",
2222     "****",
2223     "****",
2224     "****",
2225     "****",
2226     "****",
2227     "****",
2228     "****",
2229     "****",
2230     "****",
2231     "****",
2232     "****",
2233     "****",
2234     "****",
2235     "****",
2236     "****",
2237     "****",
2238     "****",
2239     "****",
2240     "****",
2241     "****",
2242     "****",
2243     "****",
2244     "****",
2245     "****",
2246     "****",
2247     "****",
2248     "****",
2249     "****",
2250     "****",
2251     "****",
2252     "****",
2253     "****",
2254     "****",
2255     "****",
2256     "****",
2257     "****",
2258     "****",
2259     "****",
2260     "****",
2261     "****",
2262     "****",
2263     "****",
2264     "****",
2265     "****",
2266     "****",
2267     "****",
2268     "****",
2269     "****",
2270     "****",
2271     "****",
2272     "****",
2273     "****",
2274     "****",
2275     "****",
2276     "****",
2277     "****",
2278     "****",
2279     "****",
2280     "****",
2281     "****",
2282     "****",
2283     "****",
2284     "****",
2285     "****",
2286     "****",
2287     "****",
2288     "****",
2289     "****",
2290     "****",
2291     "****",
2292     "****",
2293     "****",
2294     "****",
2295     "****",
2296     "****",
2297     "****",
2298     "****",
2299     "****",
2300     "****",
2301     "****",
2302     "****",
2303     "****",
2304     "****",
2305     "****",
2306     "****",
2307     "****",
2308     "****",
2309     "****",
2310     "****",
2311     "****",
2312     "****",
2313     "****",
2314     "****",
2315     "****",
2316     "****",
2317     "****",
2318     "****",
2319     "****",
2320     "****",
2321     "****",
2322     "****",
2323     "****",
2324     "****",
2325     "****",
2326     "****",
2327     "****",
2328     "****",
2329     "****",
2330     "****",
2331     "****",
2332     "****",
2333     "****",
2334     "****",
2335     "****",
2336     "****",
2337     "****",
2338     "****",
2339     "****",
2340     "****",
2341     "****",
2342     "****",
2343     "****",
2344     "****",
2345     "****",
2346     "****",
2347     "****",
2348     "****",
2349     "****",
2350     "****",
2351     "****",
2352     "****",
2353     "****",
2354     "****",
2355     "****",
2356     "****",
2357     "****",
2358     "****",
2359     "****",
2360     "****",
2361     "****",
2362     "****",
2363     "****",
2364     "****",
2365     "****",
2366     "****",
2367     "****",
2368     "****",
2369     "****",
2370     "****",
2371     "****",
2372     "****",
2373     "****",
2374     "****",
2375     "****",
2376     "****",
2377     "****",
2378     "****",
2379     "PMU_EVENT_AXI1_RD_TRANS_ACCEPTED",
2380     "PMU_EVENT_AXI1_RD_TRANS_COMPLETED",
2381     "PMU_EVENT_AXI1_RD_DATA_BEAT_RECEIVED",
2382     "PMU_EVENT_AXI1_RD_TRAN_REQ_STALLED",
2383     "PMU_EVENT_AXI1_WR_TRANS_ACCEPTED",
2384     "PMU_EVENT_AXI1_WR_TRANS_COMPLETED_M",
2385     "PMU_EVENT_AXI1_WR_TRANS_COMPLETED_S",
2386     "PMU_EVENT_AXI1_WR_DATA_BEAT_WRITTEN",
2387     "PMU_EVENT_AXI1_WR_TRAN_REQ_STALLED",
2388     "PMU_EVENT_AXI1_WR_DATA_BEAT_STALLED",
2389     "****",
2390     "****",
2391     "PMU_EVENT_AXI1_ENABLED_CYCLES",
2392     "****",
2393     "PMU_EVENT_AXI1_RD_STALL_LIMIT",
2394     "PMU_EVENT_AXI1_WR_STALL_LIMIT",
2395     "****",
2396     "****",
2397     "****",
2398     "****",
2399     "****",
2400     "****",
2401     "****",
2402     "****",
2403     "****",
2404     "****",
2405     "****",
2406     "****",
2407     "****",
2408     "****",
2409     "****",
2410     "****",
2411     "****",
2412     "****",
2413     "****",
2414     "****",
2415     "****",
2416     "****",
2417     "****",
2418     "****",
2419     "****",
2420     "****",
2421     "****",
2422     "****",
2423     "****",
2424     "****",
2425     "****",
2426     "****",
2427     "****",
2428     "PMU_EVENT_ECC_SB1",
2429 };
2430 
2431 static const char *pooling_mode_str[] = {
2432     "POOLING_MODE_MAX",
2433     "POOLING_MODE_AVERAGE",
2434     "POOLING_MODE_REDUCE_SUM",
2435 };
2436 
2437 static const char *privilege_level_str[] = {
2438     "PRIVILEGE_LEVEL_USER",
2439     "PRIVILEGE_LEVEL_PRIVILEGED",
2440 };
2441 
2442 static const char *round_mode_str[] = {
2443     "ROUND_MODE_DBL",
2444     "ROUND_MODE_TRUNCATE",
2445     "ROUND_MODE_NATURAL",
2446 };
2447 
2448 static const char *security_level_str[] = {
2449     "SECURITY_LEVEL_SECURE",
2450     "SECURITY_LEVEL_NON_SECURE",
2451 };
2452 
2453 static const char *state_str[] = {
2454     "STATE_STOPPED",
2455     "STATE_RUNNING",
2456 };
2457 
2458 static const char *wd_core_slice_state_str[] = {
2459     "WD_CORE_SLICE_STATE_HEADER",
2460     "WD_CORE_SLICE_STATE_PALETTE",
2461     "WD_CORE_SLICE_STATE_WEIGHTS",
2462 };
2463 
2464 static const char *wd_ctrl_state_str[] = {
2465     "WD_CTRL_STATE_IDLE",
2466     "WD_CTRL_STATE_DRAIN",
2467     "WD_CTRL_STATE_OFD_INIT",
2468     "WD_CTRL_STATE_OFD_RUN",
2469 };
2470 
2471 static const char *weight_order_str[] = {
2472     "WEIGHT_ORDER_DEPTH_FIRST",
2473     "WEIGHT_ORDER_PART_KERNEL_FIRST",
2474 };
2475 
2476 #endif
2477 
2478 // Register type structs
2479 // id_r - ID register
2480 struct id_r
2481 {
2482 #ifndef __cplusplus
2483     union
2484     {
2485         struct
2486         {
2487             uint32_t version_status : 4; // This is the version of the product
2488             uint32_t version_minor : 4;  // This is the n for the P part of an RnPn release number
2489             uint32_t version_major : 4;  // This is the n for the R part of an RnPn release number
2490             uint32_t product_major : 4;  // Product major ID number (unique per base product)
2491             uint32_t arch_patch_rev : 4; // This is the patch number of the architecture version a.b
2492             uint32_t
2493                 arch_minor_rev : 8; // This is the minor architecture version number, b in the architecture version a.b
2494             uint32_t
2495                 arch_major_rev : 4; // This is the major architecture version number, a in the architecture version a.b
2496         };
2497         uint32_t word;
2498     };
2499 #else
2500   private:
2501     uint32_t word0;
2502 
2503   public:
2504     CONSTEXPR id_r() : word0(268853249) {}
2505     CONSTEXPR id_r(uint32_t init) : word0(init) {}
2506     CONSTEXPR void operator=(uint32_t value)
2507     {
2508         word0 = value;
2509     }
2510     void operator=(uint32_t value) volatile
2511     {
2512         word0 = value;
2513     }
2514     CONSTEXPR operator uint32_t()
2515     {
2516         return word0;
2517     }
2518     operator uint32_t() volatile
2519     {
2520         return word0;
2521     }
2522     id_r copy() volatile
2523     {
2524         return *this;
2525     }
2526     CONSTEXPR uint32_t get_version_status() const
2527     {
2528         uint32_t value = ((1U << 4) - 1) & (word0 >> 0);
2529         return value;
2530     }
2531     uint32_t get_version_status() const volatile
2532     {
2533         uint32_t value = ((1U << 4) - 1) & (word0 >> 0);
2534         return value;
2535     }
2536     CONSTEXPR id_r &set_version_status(uint32_t value)
2537     {
2538         word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0);
2539         return *this;
2540     }
2541     volatile id_r &set_version_status(uint32_t value) volatile
2542     {
2543         word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0);
2544         return *this;
2545     }
2546     CONSTEXPR uint32_t get_version_minor() const
2547     {
2548         uint32_t value = ((1U << 4) - 1) & (word0 >> 4);
2549         return value;
2550     }
2551     uint32_t get_version_minor() const volatile
2552     {
2553         uint32_t value = ((1U << 4) - 1) & (word0 >> 4);
2554         return value;
2555     }
2556     CONSTEXPR id_r &set_version_minor(uint32_t value)
2557     {
2558         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4);
2559         return *this;
2560     }
2561     volatile id_r &set_version_minor(uint32_t value) volatile
2562     {
2563         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4);
2564         return *this;
2565     }
2566     CONSTEXPR uint32_t get_version_major() const
2567     {
2568         uint32_t value = ((1U << 4) - 1) & (word0 >> 8);
2569         return value;
2570     }
2571     uint32_t get_version_major() const volatile
2572     {
2573         uint32_t value = ((1U << 4) - 1) & (word0 >> 8);
2574         return value;
2575     }
2576     CONSTEXPR id_r &set_version_major(uint32_t value)
2577     {
2578         word0 = (((~((1U << 4) - 1)) << 8) & word0) | ((((1U << 4) - 1) & value) << 8);
2579         return *this;
2580     }
2581     volatile id_r &set_version_major(uint32_t value) volatile
2582     {
2583         word0 = (((~((1U << 4) - 1)) << 8) & word0) | ((((1U << 4) - 1) & value) << 8);
2584         return *this;
2585     }
2586     CONSTEXPR uint32_t get_product_major() const
2587     {
2588         uint32_t value = ((1U << 4) - 1) & (word0 >> 12);
2589         return value;
2590     }
2591     uint32_t get_product_major() const volatile
2592     {
2593         uint32_t value = ((1U << 4) - 1) & (word0 >> 12);
2594         return value;
2595     }
2596     CONSTEXPR id_r &set_product_major(uint32_t value)
2597     {
2598         word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12);
2599         return *this;
2600     }
2601     volatile id_r &set_product_major(uint32_t value) volatile
2602     {
2603         word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12);
2604         return *this;
2605     }
2606     CONSTEXPR uint32_t get_arch_patch_rev() const
2607     {
2608         uint32_t value = ((1U << 4) - 1) & (word0 >> 16);
2609         return value;
2610     }
2611     uint32_t get_arch_patch_rev() const volatile
2612     {
2613         uint32_t value = ((1U << 4) - 1) & (word0 >> 16);
2614         return value;
2615     }
2616     CONSTEXPR id_r &set_arch_patch_rev(uint32_t value)
2617     {
2618         word0 = (((~((1U << 4) - 1)) << 16) & word0) | ((((1U << 4) - 1) & value) << 16);
2619         return *this;
2620     }
2621     volatile id_r &set_arch_patch_rev(uint32_t value) volatile
2622     {
2623         word0 = (((~((1U << 4) - 1)) << 16) & word0) | ((((1U << 4) - 1) & value) << 16);
2624         return *this;
2625     }
2626     CONSTEXPR uint32_t get_arch_minor_rev() const
2627     {
2628         uint32_t value = ((1U << 8) - 1) & (word0 >> 20);
2629         return value;
2630     }
2631     uint32_t get_arch_minor_rev() const volatile
2632     {
2633         uint32_t value = ((1U << 8) - 1) & (word0 >> 20);
2634         return value;
2635     }
2636     CONSTEXPR id_r &set_arch_minor_rev(uint32_t value)
2637     {
2638         word0 = (((~((1U << 8) - 1)) << 20) & word0) | ((((1U << 8) - 1) & value) << 20);
2639         return *this;
2640     }
2641     volatile id_r &set_arch_minor_rev(uint32_t value) volatile
2642     {
2643         word0 = (((~((1U << 8) - 1)) << 20) & word0) | ((((1U << 8) - 1) & value) << 20);
2644         return *this;
2645     }
2646     CONSTEXPR uint32_t get_arch_major_rev() const
2647     {
2648         uint32_t value = ((1U << 4) - 1) & (word0 >> 28);
2649         return value;
2650     }
2651     uint32_t get_arch_major_rev() const volatile
2652     {
2653         uint32_t value = ((1U << 4) - 1) & (word0 >> 28);
2654         return value;
2655     }
2656     CONSTEXPR id_r &set_arch_major_rev(uint32_t value)
2657     {
2658         word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28);
2659         return *this;
2660     }
2661     volatile id_r &set_arch_major_rev(uint32_t value) volatile
2662     {
2663         word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28);
2664         return *this;
2665     }
2666 #endif
2667 };
2668 
2669 // status_r - Register describes the current operating status of the NPU
2670 struct status_r
2671 {
2672 #ifndef __cplusplus
2673     union
2674     {
2675         struct
2676         {
2677             uint32_t state : 1;      // NPU state, 0 = Stopped, 1 = Running
2678             uint32_t irq_raised : 1; // Raw IRQ status, 0 = IRQ not raised, 1 = IRQ raised. IRQ is cleared using command
2679                                      // register bit 1
2680             uint32_t
2681                 bus_status : 1; // 0=OK, 1=Bus abort detected and processing halted (NPU will reach IDLE state and not
2682                                 // to start process any more commands/AXI transactions). Can only be cleared by a reset
2683             uint32_t reset_status : 1; // Reset is ongoing and only this register can be read (other registers read as 0
2684                                        // and writes are ignored.) A value of 0 means NPU is not being reset and can be
2685                                        // accessed as normal
2686             uint32_t
2687                 cmd_parse_error : 1; // 0=No error 1=Command stream parsing error detected. Can only be cleared by reset
2688             uint32_t cmd_end_reached : 1; // 0=Not reached, 1=Reached. Cleared by writing QBASE or QSIZE when NPU is in
2689                                           // stopped state
2690             uint32_t pmu_irq_raised : 1;  // 0=No PMU IRQ, 1=PMU IRQ raised. Cleared by using command register bit 1
2691             uint32_t wd_fault : 1; // Weight decoder state: 0=no fault 1=weight decoder decompression fault. Can only be
2692                                    // cleared by reset
2693             uint32_t ecc_fault : 1; // ECC state for internal RAMs: 0=no fault 1=ECC fault signalled. Can only be
2694                                     // cleared by reset
2695             uint32_t reserved0 : 2;
2696             uint32_t faulting_interface : 1; // Faulting interface on bus abort
2697             uint32_t faulting_channel : 4;  // Faulting channel on a bus abort. Read: 0=Cmd 1=IFM 2=Weights 3=Scale+Bias
2698                                             // 4=Mem2Mem; Write: 8=OFM 9=Mem2Mem
2699             uint32_t irq_history_mask : 16; // IRQ History mask
2700         };
2701         uint32_t word;
2702     };
2703 #else
2704   private:
2705     uint32_t word0;
2706 
2707   public:
2708     CONSTEXPR status_r() : word0(8) {}
2709     CONSTEXPR status_r(uint32_t init) : word0(init) {}
2710     CONSTEXPR void operator=(uint32_t value)
2711     {
2712         word0 = value;
2713     }
2714     void operator=(uint32_t value) volatile
2715     {
2716         word0 = value;
2717     }
2718     CONSTEXPR operator uint32_t()
2719     {
2720         return word0;
2721     }
2722     operator uint32_t() volatile
2723     {
2724         return word0;
2725     }
2726     status_r copy() volatile
2727     {
2728         return *this;
2729     }
2730     CONSTEXPR NPU_NAMESPACE::state get_state() const
2731     {
2732         NPU_NAMESPACE::state value = static_cast<NPU_NAMESPACE::state>(((1U << 1) - 1) & (word0 >> 0));
2733         return value;
2734     }
2735     NPU_NAMESPACE::state get_state() const volatile
2736     {
2737         NPU_NAMESPACE::state value = static_cast<NPU_NAMESPACE::state>(((1U << 1) - 1) & (word0 >> 0));
2738         return value;
2739     }
2740     CONSTEXPR status_r &set_state(NPU_NAMESPACE::state value)
2741     {
2742         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
2743         return *this;
2744     }
2745     volatile status_r &set_state(NPU_NAMESPACE::state value) volatile
2746     {
2747         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
2748         return *this;
2749     }
2750     CONSTEXPR uint32_t get_irq_raised() const
2751     {
2752         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
2753         return value;
2754     }
2755     uint32_t get_irq_raised() const volatile
2756     {
2757         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
2758         return value;
2759     }
2760     CONSTEXPR status_r &set_irq_raised(uint32_t value)
2761     {
2762         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
2763         return *this;
2764     }
2765     volatile status_r &set_irq_raised(uint32_t value) volatile
2766     {
2767         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
2768         return *this;
2769     }
2770     CONSTEXPR uint32_t get_bus_status() const
2771     {
2772         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
2773         return value;
2774     }
2775     uint32_t get_bus_status() const volatile
2776     {
2777         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
2778         return value;
2779     }
2780     CONSTEXPR status_r &set_bus_status(uint32_t value)
2781     {
2782         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
2783         return *this;
2784     }
2785     volatile status_r &set_bus_status(uint32_t value) volatile
2786     {
2787         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
2788         return *this;
2789     }
2790     CONSTEXPR uint32_t get_reset_status() const
2791     {
2792         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
2793         return value;
2794     }
2795     uint32_t get_reset_status() const volatile
2796     {
2797         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
2798         return value;
2799     }
2800     CONSTEXPR status_r &set_reset_status(uint32_t value)
2801     {
2802         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
2803         return *this;
2804     }
2805     volatile status_r &set_reset_status(uint32_t value) volatile
2806     {
2807         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
2808         return *this;
2809     }
2810     CONSTEXPR uint32_t get_cmd_parse_error() const
2811     {
2812         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
2813         return value;
2814     }
2815     uint32_t get_cmd_parse_error() const volatile
2816     {
2817         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
2818         return value;
2819     }
2820     CONSTEXPR status_r &set_cmd_parse_error(uint32_t value)
2821     {
2822         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
2823         return *this;
2824     }
2825     volatile status_r &set_cmd_parse_error(uint32_t value) volatile
2826     {
2827         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
2828         return *this;
2829     }
2830     CONSTEXPR uint32_t get_cmd_end_reached() const
2831     {
2832         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
2833         return value;
2834     }
2835     uint32_t get_cmd_end_reached() const volatile
2836     {
2837         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
2838         return value;
2839     }
2840     CONSTEXPR status_r &set_cmd_end_reached(uint32_t value)
2841     {
2842         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
2843         return *this;
2844     }
2845     volatile status_r &set_cmd_end_reached(uint32_t value) volatile
2846     {
2847         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
2848         return *this;
2849     }
2850     CONSTEXPR uint32_t get_pmu_irq_raised() const
2851     {
2852         uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
2853         return value;
2854     }
2855     uint32_t get_pmu_irq_raised() const volatile
2856     {
2857         uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
2858         return value;
2859     }
2860     CONSTEXPR status_r &set_pmu_irq_raised(uint32_t value)
2861     {
2862         word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
2863         return *this;
2864     }
2865     volatile status_r &set_pmu_irq_raised(uint32_t value) volatile
2866     {
2867         word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
2868         return *this;
2869     }
2870     CONSTEXPR uint32_t get_wd_fault() const
2871     {
2872         uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
2873         return value;
2874     }
2875     uint32_t get_wd_fault() const volatile
2876     {
2877         uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
2878         return value;
2879     }
2880     CONSTEXPR status_r &set_wd_fault(uint32_t value)
2881     {
2882         word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
2883         return *this;
2884     }
2885     volatile status_r &set_wd_fault(uint32_t value) volatile
2886     {
2887         word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
2888         return *this;
2889     }
2890     CONSTEXPR uint32_t get_ecc_fault() const
2891     {
2892         uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
2893         return value;
2894     }
2895     uint32_t get_ecc_fault() const volatile
2896     {
2897         uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
2898         return value;
2899     }
2900     CONSTEXPR status_r &set_ecc_fault(uint32_t value)
2901     {
2902         word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
2903         return *this;
2904     }
2905     volatile status_r &set_ecc_fault(uint32_t value) volatile
2906     {
2907         word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
2908         return *this;
2909     }
2910     CONSTEXPR NPU_NAMESPACE::dma_fault_src get_faulting_interface() const
2911     {
2912         NPU_NAMESPACE::dma_fault_src value = static_cast<NPU_NAMESPACE::dma_fault_src>(((1U << 1) - 1) & (word0 >> 11));
2913         return value;
2914     }
2915     NPU_NAMESPACE::dma_fault_src get_faulting_interface() const volatile
2916     {
2917         NPU_NAMESPACE::dma_fault_src value = static_cast<NPU_NAMESPACE::dma_fault_src>(((1U << 1) - 1) & (word0 >> 11));
2918         return value;
2919     }
2920     CONSTEXPR status_r &set_faulting_interface(NPU_NAMESPACE::dma_fault_src value)
2921     {
2922         word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 11);
2923         return *this;
2924     }
2925     volatile status_r &set_faulting_interface(NPU_NAMESPACE::dma_fault_src value) volatile
2926     {
2927         word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 11);
2928         return *this;
2929     }
2930     CONSTEXPR uint32_t get_faulting_channel() const
2931     {
2932         uint32_t value = ((1U << 4) - 1) & (word0 >> 12);
2933         return value;
2934     }
2935     uint32_t get_faulting_channel() const volatile
2936     {
2937         uint32_t value = ((1U << 4) - 1) & (word0 >> 12);
2938         return value;
2939     }
2940     CONSTEXPR status_r &set_faulting_channel(uint32_t value)
2941     {
2942         word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12);
2943         return *this;
2944     }
2945     volatile status_r &set_faulting_channel(uint32_t value) volatile
2946     {
2947         word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12);
2948         return *this;
2949     }
2950     CONSTEXPR uint32_t get_irq_history_mask() const
2951     {
2952         uint32_t value = ((1U << 16) - 1) & (word0 >> 16);
2953         return value;
2954     }
2955     uint32_t get_irq_history_mask() const volatile
2956     {
2957         uint32_t value = ((1U << 16) - 1) & (word0 >> 16);
2958         return value;
2959     }
2960     CONSTEXPR status_r &set_irq_history_mask(uint32_t value)
2961     {
2962         word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16);
2963         return *this;
2964     }
2965     volatile status_r &set_irq_history_mask(uint32_t value) volatile
2966     {
2967         word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16);
2968         return *this;
2969     }
2970 #endif
2971 };
2972 
2973 // cmd_r - Command register, reads as last written command
2974 struct cmd_r
2975 {
2976 #ifndef __cplusplus
2977     union
2978     {
2979         struct
2980         {
2981             uint32_t transition_to_running_state : 1; // Write 1 to transition the NPU to running state. Writing 0 has
2982                                                       // no effect
2983             uint32_t clear_irq : 1; // Write 1 to clear the IRQ status in the STATUS register. Writing 0 has no effect
2984             uint32_t clock_q_enable : 1; // Write 1 to this bit to enable clock off using clock q-interface and enable
2985                                          // the requester clock gate
2986             uint32_t power_q_enable : 1; // Write 1 to this bit to enable power off using power q-interface
2987             uint32_t
2988                 stop_request : 1; // Write 1 to this bit to request STOP after completing any already-started commands
2989             uint32_t reserved0 : 11;
2990             uint32_t clear_irq_history : 16; // Clears the IRQ history mask
2991         };
2992         uint32_t word;
2993     };
2994 #else
2995   private:
2996     uint32_t word0;
2997 
2998   public:
2999     CONSTEXPR cmd_r() : word0(12) {}
3000     CONSTEXPR cmd_r(uint32_t init) : word0(init) {}
3001     CONSTEXPR void operator=(uint32_t value)
3002     {
3003         word0 = value;
3004     }
3005     void operator=(uint32_t value) volatile
3006     {
3007         word0 = value;
3008     }
3009     CONSTEXPR operator uint32_t()
3010     {
3011         return word0;
3012     }
3013     operator uint32_t() volatile
3014     {
3015         return word0;
3016     }
3017     cmd_r copy() volatile
3018     {
3019         return *this;
3020     }
3021     CONSTEXPR uint32_t get_transition_to_running_state() const
3022     {
3023         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
3024         return value;
3025     }
3026     uint32_t get_transition_to_running_state() const volatile
3027     {
3028         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
3029         return value;
3030     }
3031     CONSTEXPR cmd_r &set_transition_to_running_state(uint32_t value)
3032     {
3033         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
3034         return *this;
3035     }
3036     volatile cmd_r &set_transition_to_running_state(uint32_t value) volatile
3037     {
3038         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
3039         return *this;
3040     }
3041     CONSTEXPR uint32_t get_clear_irq() const
3042     {
3043         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
3044         return value;
3045     }
3046     uint32_t get_clear_irq() const volatile
3047     {
3048         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
3049         return value;
3050     }
3051     CONSTEXPR cmd_r &set_clear_irq(uint32_t value)
3052     {
3053         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
3054         return *this;
3055     }
3056     volatile cmd_r &set_clear_irq(uint32_t value) volatile
3057     {
3058         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
3059         return *this;
3060     }
3061     CONSTEXPR uint32_t get_clock_q_enable() const
3062     {
3063         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
3064         return value;
3065     }
3066     uint32_t get_clock_q_enable() const volatile
3067     {
3068         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
3069         return value;
3070     }
3071     CONSTEXPR cmd_r &set_clock_q_enable(uint32_t value)
3072     {
3073         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
3074         return *this;
3075     }
3076     volatile cmd_r &set_clock_q_enable(uint32_t value) volatile
3077     {
3078         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
3079         return *this;
3080     }
3081     CONSTEXPR uint32_t get_power_q_enable() const
3082     {
3083         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
3084         return value;
3085     }
3086     uint32_t get_power_q_enable() const volatile
3087     {
3088         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
3089         return value;
3090     }
3091     CONSTEXPR cmd_r &set_power_q_enable(uint32_t value)
3092     {
3093         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
3094         return *this;
3095     }
3096     volatile cmd_r &set_power_q_enable(uint32_t value) volatile
3097     {
3098         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
3099         return *this;
3100     }
3101     CONSTEXPR uint32_t get_stop_request() const
3102     {
3103         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
3104         return value;
3105     }
3106     uint32_t get_stop_request() const volatile
3107     {
3108         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
3109         return value;
3110     }
3111     CONSTEXPR cmd_r &set_stop_request(uint32_t value)
3112     {
3113         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
3114         return *this;
3115     }
3116     volatile cmd_r &set_stop_request(uint32_t value) volatile
3117     {
3118         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
3119         return *this;
3120     }
3121     CONSTEXPR uint32_t get_clear_irq_history() const
3122     {
3123         uint32_t value = ((1U << 16) - 1) & (word0 >> 16);
3124         return value;
3125     }
3126     uint32_t get_clear_irq_history() const volatile
3127     {
3128         uint32_t value = ((1U << 16) - 1) & (word0 >> 16);
3129         return value;
3130     }
3131     CONSTEXPR cmd_r &set_clear_irq_history(uint32_t value)
3132     {
3133         word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16);
3134         return *this;
3135     }
3136     volatile cmd_r &set_clear_irq_history(uint32_t value) volatile
3137     {
3138         word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16);
3139         return *this;
3140     }
3141 #endif
3142 };
3143 
3144 // reset_r - Request Reset and new security mode
3145 struct reset_r
3146 {
3147 #ifndef __cplusplus
3148     union
3149     {
3150         struct
3151         {
3152             uint32_t pending_CPL : 1; // Current privilege level 0=User 1=Privileged
3153             uint32_t pending_CSL : 1; // Current security level 0=Secure 1=Non secure
3154             uint32_t reserved0 : 30;
3155         };
3156         uint32_t word;
3157     };
3158 #else
3159   private:
3160     uint32_t word0;
3161 
3162   public:
3163     CONSTEXPR reset_r() : word0(0) {}
3164     CONSTEXPR reset_r(uint32_t init) : word0(init) {}
3165     CONSTEXPR void operator=(uint32_t value)
3166     {
3167         word0 = value;
3168     }
3169     void operator=(uint32_t value) volatile
3170     {
3171         word0 = value;
3172     }
3173     CONSTEXPR operator uint32_t()
3174     {
3175         return word0;
3176     }
3177     operator uint32_t() volatile
3178     {
3179         return word0;
3180     }
3181     reset_r copy() volatile
3182     {
3183         return *this;
3184     }
3185     CONSTEXPR NPU_NAMESPACE::privilege_level get_pending_CPL() const
3186     {
3187         NPU_NAMESPACE::privilege_level value =
3188             static_cast<NPU_NAMESPACE::privilege_level>(((1U << 1) - 1) & (word0 >> 0));
3189         return value;
3190     }
3191     NPU_NAMESPACE::privilege_level get_pending_CPL() const volatile
3192     {
3193         NPU_NAMESPACE::privilege_level value =
3194             static_cast<NPU_NAMESPACE::privilege_level>(((1U << 1) - 1) & (word0 >> 0));
3195         return value;
3196     }
3197     CONSTEXPR reset_r &set_pending_CPL(NPU_NAMESPACE::privilege_level value)
3198     {
3199         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
3200         return *this;
3201     }
3202     volatile reset_r &set_pending_CPL(NPU_NAMESPACE::privilege_level value) volatile
3203     {
3204         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
3205         return *this;
3206     }
3207     CONSTEXPR NPU_NAMESPACE::security_level get_pending_CSL() const
3208     {
3209         NPU_NAMESPACE::security_level value =
3210             static_cast<NPU_NAMESPACE::security_level>(((1U << 1) - 1) & (word0 >> 1));
3211         return value;
3212     }
3213     NPU_NAMESPACE::security_level get_pending_CSL() const volatile
3214     {
3215         NPU_NAMESPACE::security_level value =
3216             static_cast<NPU_NAMESPACE::security_level>(((1U << 1) - 1) & (word0 >> 1));
3217         return value;
3218     }
3219     CONSTEXPR reset_r &set_pending_CSL(NPU_NAMESPACE::security_level value)
3220     {
3221         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 1);
3222         return *this;
3223     }
3224     volatile reset_r &set_pending_CSL(NPU_NAMESPACE::security_level value) volatile
3225     {
3226         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 1);
3227         return *this;
3228     }
3229 #endif
3230 };
3231 
3232 // qbase_r - Base address of the command stream in bytes
3233 struct qbase_r
3234 {
3235 #ifndef __cplusplus
3236     union
3237     {
3238         struct
3239         {
3240             uint32_t offset_LO : 32; // Offset - LSB
3241             uint32_t offset_HI : 8;  // Offset - MSB
3242             uint32_t reserved0 : 24;
3243         };
3244         uint32_t word[2];
3245     };
3246 #else
3247   private:
3248     uint32_t word0;
3249     uint32_t word1;
3250 
3251   public:
3252     CONSTEXPR qbase_r() : word0(0), word1(0) {}
3253     CONSTEXPR qbase_r(uint64_t init) :
3254         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
3255         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
3256     {
3257     }
3258     CONSTEXPR void operator=(uint64_t value)
3259     {
3260         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
3261         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
3262     }
3263     void operator=(uint64_t value) volatile
3264     {
3265         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
3266         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
3267     }
3268     CONSTEXPR operator uint64_t()
3269     {
3270         return (static_cast<uint64_t>(word1) << 32) | word0;
3271     }
3272     operator uint64_t() volatile
3273     {
3274         return (static_cast<uint64_t>(word1) << 32) | word0;
3275     }
3276     qbase_r copy() volatile
3277     {
3278         return *this;
3279     }
3280 #endif
3281 };
3282 
3283 // qread_r - Read offset in the command stream in bytes. Multiple of 4 in the range 0 to 16 MB
3284 struct qread_r
3285 {
3286 #ifndef __cplusplus
3287     union
3288     {
3289         struct
3290         {
3291             uint32_t QREAD : 32; // The read offset of the current command under execution
3292         };
3293         uint32_t word;
3294     };
3295 #else
3296   private:
3297     uint32_t word0;
3298 
3299   public:
3300     CONSTEXPR qread_r() : word0(0) {}
3301     CONSTEXPR qread_r(uint32_t init) : word0(init) {}
3302     CONSTEXPR void operator=(uint32_t value)
3303     {
3304         word0 = value;
3305     }
3306     void operator=(uint32_t value) volatile
3307     {
3308         word0 = value;
3309     }
3310     CONSTEXPR operator uint32_t()
3311     {
3312         return word0;
3313     }
3314     operator uint32_t() volatile
3315     {
3316         return word0;
3317     }
3318     qread_r copy() volatile
3319     {
3320         return *this;
3321     }
3322     CONSTEXPR uint32_t get_QREAD() const
3323     {
3324         uint32_t value = word0;
3325         return value;
3326     }
3327     uint32_t get_QREAD() const volatile
3328     {
3329         uint32_t value = word0;
3330         return value;
3331     }
3332     CONSTEXPR qread_r &set_QREAD(uint32_t value)
3333     {
3334         word0 = value;
3335         return *this;
3336     }
3337     volatile qread_r &set_QREAD(uint32_t value) volatile
3338     {
3339         word0 = value;
3340         return *this;
3341     }
3342 #endif
3343 };
3344 
3345 // qconfig_r - AXI configuration for the command stream in the range 0-3. Same encoding as for REGIONCFG
3346 struct qconfig_r
3347 {
3348 #ifndef __cplusplus
3349     union
3350     {
3351         struct
3352         {
3353             uint32_t cmd_region0 : 2; // Command region configuration
3354             uint32_t reserved0 : 30;
3355         };
3356         uint32_t word;
3357     };
3358 #else
3359   private:
3360     uint32_t word0;
3361 
3362   public:
3363     CONSTEXPR qconfig_r() : word0(0) {}
3364     CONSTEXPR qconfig_r(uint32_t init) : word0(init) {}
3365     CONSTEXPR void operator=(uint32_t value)
3366     {
3367         word0 = value;
3368     }
3369     void operator=(uint32_t value) volatile
3370     {
3371         word0 = value;
3372     }
3373     CONSTEXPR operator uint32_t()
3374     {
3375         return word0;
3376     }
3377     operator uint32_t() volatile
3378     {
3379         return word0;
3380     }
3381     qconfig_r copy() volatile
3382     {
3383         return *this;
3384     }
3385     CONSTEXPR NPU_NAMESPACE::mem_attr get_cmd_region0() const
3386     {
3387         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 0));
3388         return value;
3389     }
3390     NPU_NAMESPACE::mem_attr get_cmd_region0() const volatile
3391     {
3392         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 0));
3393         return value;
3394     }
3395     CONSTEXPR qconfig_r &set_cmd_region0(NPU_NAMESPACE::mem_attr value)
3396     {
3397         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
3398         return *this;
3399     }
3400     volatile qconfig_r &set_cmd_region0(NPU_NAMESPACE::mem_attr value) volatile
3401     {
3402         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
3403         return *this;
3404     }
3405 #endif
3406 };
3407 
3408 // qsize_r - Size of the command stream in bytes. Multiple of 4 in the range 0 to 16 MB
3409 struct qsize_r
3410 {
3411 #ifndef __cplusplus
3412     union
3413     {
3414         struct
3415         {
3416             uint32_t QSIZE : 32; // Size of the next command stream to be executed by the NPU
3417         };
3418         uint32_t word;
3419     };
3420 #else
3421   private:
3422     uint32_t word0;
3423 
3424   public:
3425     CONSTEXPR qsize_r() : word0(0) {}
3426     CONSTEXPR qsize_r(uint32_t init) : word0(init) {}
3427     CONSTEXPR void operator=(uint32_t value)
3428     {
3429         word0 = value;
3430     }
3431     void operator=(uint32_t value) volatile
3432     {
3433         word0 = value;
3434     }
3435     CONSTEXPR operator uint32_t()
3436     {
3437         return word0;
3438     }
3439     operator uint32_t() volatile
3440     {
3441         return word0;
3442     }
3443     qsize_r copy() volatile
3444     {
3445         return *this;
3446     }
3447     CONSTEXPR uint32_t get_QSIZE() const
3448     {
3449         uint32_t value = word0;
3450         return value;
3451     }
3452     uint32_t get_QSIZE() const volatile
3453     {
3454         uint32_t value = word0;
3455         return value;
3456     }
3457     CONSTEXPR qsize_r &set_QSIZE(uint32_t value)
3458     {
3459         word0 = value;
3460         return *this;
3461     }
3462     volatile qsize_r &set_QSIZE(uint32_t value) volatile
3463     {
3464         word0 = value;
3465         return *this;
3466     }
3467 #endif
3468 };
3469 
3470 // prot_r - Protection level configured for the NPU when acting as an AXI requester
3471 struct prot_r
3472 {
3473 #ifndef __cplusplus
3474     union
3475     {
3476         struct
3477         {
3478             uint32_t active_CPL : 1; // Current privilege level 0=User 1=Privileged
3479             uint32_t active_CSL : 1; // Current security level 0=Secure 1=Non secure
3480             uint32_t reserved0 : 30;
3481         };
3482         uint32_t word;
3483     };
3484 #else
3485   private:
3486     uint32_t word0;
3487 
3488   public:
3489     CONSTEXPR prot_r() : word0(0) {}
3490     CONSTEXPR prot_r(uint32_t init) : word0(init) {}
3491     CONSTEXPR void operator=(uint32_t value)
3492     {
3493         word0 = value;
3494     }
3495     void operator=(uint32_t value) volatile
3496     {
3497         word0 = value;
3498     }
3499     CONSTEXPR operator uint32_t()
3500     {
3501         return word0;
3502     }
3503     operator uint32_t() volatile
3504     {
3505         return word0;
3506     }
3507     prot_r copy() volatile
3508     {
3509         return *this;
3510     }
3511     CONSTEXPR NPU_NAMESPACE::privilege_level get_active_CPL() const
3512     {
3513         NPU_NAMESPACE::privilege_level value =
3514             static_cast<NPU_NAMESPACE::privilege_level>(((1U << 1) - 1) & (word0 >> 0));
3515         return value;
3516     }
3517     NPU_NAMESPACE::privilege_level get_active_CPL() const volatile
3518     {
3519         NPU_NAMESPACE::privilege_level value =
3520             static_cast<NPU_NAMESPACE::privilege_level>(((1U << 1) - 1) & (word0 >> 0));
3521         return value;
3522     }
3523     CONSTEXPR prot_r &set_active_CPL(NPU_NAMESPACE::privilege_level value)
3524     {
3525         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
3526         return *this;
3527     }
3528     volatile prot_r &set_active_CPL(NPU_NAMESPACE::privilege_level value) volatile
3529     {
3530         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
3531         return *this;
3532     }
3533     CONSTEXPR NPU_NAMESPACE::security_level get_active_CSL() const
3534     {
3535         NPU_NAMESPACE::security_level value =
3536             static_cast<NPU_NAMESPACE::security_level>(((1U << 1) - 1) & (word0 >> 1));
3537         return value;
3538     }
3539     NPU_NAMESPACE::security_level get_active_CSL() const volatile
3540     {
3541         NPU_NAMESPACE::security_level value =
3542             static_cast<NPU_NAMESPACE::security_level>(((1U << 1) - 1) & (word0 >> 1));
3543         return value;
3544     }
3545     CONSTEXPR prot_r &set_active_CSL(NPU_NAMESPACE::security_level value)
3546     {
3547         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 1);
3548         return *this;
3549     }
3550     volatile prot_r &set_active_CSL(NPU_NAMESPACE::security_level value) volatile
3551     {
3552         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 1);
3553         return *this;
3554     }
3555 #endif
3556 };
3557 
3558 // config_r - RTL configuration
3559 struct config_r
3560 {
3561 #ifndef __cplusplus
3562     union
3563     {
3564         struct
3565         {
3566             uint32_t macs_per_cc : 4;        // The log2(macs/clock cycle)
3567             uint32_t cmd_stream_version : 4; // command stream version accepted by this NPU
3568             uint32_t shram_size : 8;         // Total size in KB of internal SHRAM
3569             uint32_t reserved0 : 10;
3570             uint32_t functional_safety : 1; // Functional safety configuration
3571             uint32_t custom_dma : 1;        // Custom DMA configuration
3572             uint32_t product : 4;           // Product configuration
3573         };
3574         uint32_t word;
3575     };
3576 #else
3577   private:
3578     uint32_t word0;
3579 
3580   public:
3581     CONSTEXPR config_r() : word0(268435456) {}
3582     CONSTEXPR config_r(uint32_t init) : word0(init) {}
3583     CONSTEXPR void operator=(uint32_t value)
3584     {
3585         word0 = value;
3586     }
3587     void operator=(uint32_t value) volatile
3588     {
3589         word0 = value;
3590     }
3591     CONSTEXPR operator uint32_t()
3592     {
3593         return word0;
3594     }
3595     operator uint32_t() volatile
3596     {
3597         return word0;
3598     }
3599     config_r copy() volatile
3600     {
3601         return *this;
3602     }
3603     CONSTEXPR uint32_t get_macs_per_cc() const
3604     {
3605         uint32_t value = ((1U << 4) - 1) & (word0 >> 0);
3606         return value;
3607     }
3608     uint32_t get_macs_per_cc() const volatile
3609     {
3610         uint32_t value = ((1U << 4) - 1) & (word0 >> 0);
3611         return value;
3612     }
3613     CONSTEXPR config_r &set_macs_per_cc(uint32_t value)
3614     {
3615         word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0);
3616         return *this;
3617     }
3618     volatile config_r &set_macs_per_cc(uint32_t value) volatile
3619     {
3620         word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0);
3621         return *this;
3622     }
3623     CONSTEXPR uint32_t get_cmd_stream_version() const
3624     {
3625         uint32_t value = ((1U << 4) - 1) & (word0 >> 4);
3626         return value;
3627     }
3628     uint32_t get_cmd_stream_version() const volatile
3629     {
3630         uint32_t value = ((1U << 4) - 1) & (word0 >> 4);
3631         return value;
3632     }
3633     CONSTEXPR config_r &set_cmd_stream_version(uint32_t value)
3634     {
3635         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4);
3636         return *this;
3637     }
3638     volatile config_r &set_cmd_stream_version(uint32_t value) volatile
3639     {
3640         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4);
3641         return *this;
3642     }
3643     CONSTEXPR uint32_t get_shram_size() const
3644     {
3645         uint32_t value = ((1U << 8) - 1) & (word0 >> 8);
3646         return value;
3647     }
3648     uint32_t get_shram_size() const volatile
3649     {
3650         uint32_t value = ((1U << 8) - 1) & (word0 >> 8);
3651         return value;
3652     }
3653     CONSTEXPR config_r &set_shram_size(uint32_t value)
3654     {
3655         word0 = (((~((1U << 8) - 1)) << 8) & word0) | ((((1U << 8) - 1) & value) << 8);
3656         return *this;
3657     }
3658     volatile config_r &set_shram_size(uint32_t value) volatile
3659     {
3660         word0 = (((~((1U << 8) - 1)) << 8) & word0) | ((((1U << 8) - 1) & value) << 8);
3661         return *this;
3662     }
3663     CONSTEXPR NPU_NAMESPACE::functional_safety get_functional_safety() const
3664     {
3665         NPU_NAMESPACE::functional_safety value =
3666             static_cast<NPU_NAMESPACE::functional_safety>(((1U << 1) - 1) & (word0 >> 26));
3667         return value;
3668     }
3669     NPU_NAMESPACE::functional_safety get_functional_safety() const volatile
3670     {
3671         NPU_NAMESPACE::functional_safety value =
3672             static_cast<NPU_NAMESPACE::functional_safety>(((1U << 1) - 1) & (word0 >> 26));
3673         return value;
3674     }
3675     CONSTEXPR config_r &set_functional_safety(NPU_NAMESPACE::functional_safety value)
3676     {
3677         word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 26);
3678         return *this;
3679     }
3680     volatile config_r &set_functional_safety(NPU_NAMESPACE::functional_safety value) volatile
3681     {
3682         word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 26);
3683         return *this;
3684     }
3685     CONSTEXPR NPU_NAMESPACE::custom_dma get_custom_dma() const
3686     {
3687         NPU_NAMESPACE::custom_dma value = static_cast<NPU_NAMESPACE::custom_dma>(((1U << 1) - 1) & (word0 >> 27));
3688         return value;
3689     }
3690     NPU_NAMESPACE::custom_dma get_custom_dma() const volatile
3691     {
3692         NPU_NAMESPACE::custom_dma value = static_cast<NPU_NAMESPACE::custom_dma>(((1U << 1) - 1) & (word0 >> 27));
3693         return value;
3694     }
3695     CONSTEXPR config_r &set_custom_dma(NPU_NAMESPACE::custom_dma value)
3696     {
3697         word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 27);
3698         return *this;
3699     }
3700     volatile config_r &set_custom_dma(NPU_NAMESPACE::custom_dma value) volatile
3701     {
3702         word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 27);
3703         return *this;
3704     }
3705     CONSTEXPR uint32_t get_product() const
3706     {
3707         uint32_t value = ((1U << 4) - 1) & (word0 >> 28);
3708         return value;
3709     }
3710     uint32_t get_product() const volatile
3711     {
3712         uint32_t value = ((1U << 4) - 1) & (word0 >> 28);
3713         return value;
3714     }
3715     CONSTEXPR config_r &set_product(uint32_t value)
3716     {
3717         word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28);
3718         return *this;
3719     }
3720     volatile config_r &set_product(uint32_t value) volatile
3721     {
3722         word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28);
3723         return *this;
3724     }
3725 #endif
3726 };
3727 
3728 // lock_r - Lock register. This register is designed for driver use and does not affect NPU functionality
3729 struct lock_r
3730 {
3731 #ifndef __cplusplus
3732     union
3733     {
3734         struct
3735         {
3736             uint32_t LOCK : 32; // 32 bit value for LOCK configuration
3737         };
3738         uint32_t word;
3739     };
3740 #else
3741   private:
3742     uint32_t word0;
3743 
3744   public:
3745     CONSTEXPR lock_r() : word0(0) {}
3746     CONSTEXPR lock_r(uint32_t init) : word0(init) {}
3747     CONSTEXPR void operator=(uint32_t value)
3748     {
3749         word0 = value;
3750     }
3751     void operator=(uint32_t value) volatile
3752     {
3753         word0 = value;
3754     }
3755     CONSTEXPR operator uint32_t()
3756     {
3757         return word0;
3758     }
3759     operator uint32_t() volatile
3760     {
3761         return word0;
3762     }
3763     lock_r copy() volatile
3764     {
3765         return *this;
3766     }
3767     CONSTEXPR uint32_t get_LOCK() const
3768     {
3769         uint32_t value = word0;
3770         return value;
3771     }
3772     uint32_t get_LOCK() const volatile
3773     {
3774         uint32_t value = word0;
3775         return value;
3776     }
3777     CONSTEXPR lock_r &set_LOCK(uint32_t value)
3778     {
3779         word0 = value;
3780         return *this;
3781     }
3782     volatile lock_r &set_LOCK(uint32_t value) volatile
3783     {
3784         word0 = value;
3785         return *this;
3786     }
3787 #endif
3788 };
3789 
3790 // regioncfg_r - Region memory type configuration. Bits[2*k+1:2*k] give the memory type for REGION[k]
3791 struct regioncfg_r
3792 {
3793 #ifndef __cplusplus
3794     union
3795     {
3796         struct
3797         {
3798             uint32_t region0 : 2; // Bits for Region0 Configuration
3799             uint32_t region1 : 2; // Bits for Region1 Configuration
3800             uint32_t region2 : 2; // Bits for Region2 Configuration
3801             uint32_t region3 : 2; // Bits for Region3 Configuration
3802             uint32_t region4 : 2; // Bits for Region4 Configuration
3803             uint32_t region5 : 2; // Bits for Region5 Configuration
3804             uint32_t region6 : 2; // Bits for Region6 Configuration
3805             uint32_t region7 : 2; // Bits for Region7 Configuration
3806             uint32_t reserved0 : 16;
3807         };
3808         uint32_t word;
3809     };
3810 #else
3811   private:
3812     uint32_t word0;
3813 
3814   public:
3815     CONSTEXPR regioncfg_r() : word0(0) {}
3816     CONSTEXPR regioncfg_r(uint32_t init) : word0(init) {}
3817     CONSTEXPR void operator=(uint32_t value)
3818     {
3819         word0 = value;
3820     }
3821     void operator=(uint32_t value) volatile
3822     {
3823         word0 = value;
3824     }
3825     CONSTEXPR operator uint32_t()
3826     {
3827         return word0;
3828     }
3829     operator uint32_t() volatile
3830     {
3831         return word0;
3832     }
3833     regioncfg_r copy() volatile
3834     {
3835         return *this;
3836     }
3837     CONSTEXPR NPU_NAMESPACE::mem_attr get_region0() const
3838     {
3839         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 0));
3840         return value;
3841     }
3842     NPU_NAMESPACE::mem_attr get_region0() const volatile
3843     {
3844         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 0));
3845         return value;
3846     }
3847     CONSTEXPR regioncfg_r &set_region0(NPU_NAMESPACE::mem_attr value)
3848     {
3849         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
3850         return *this;
3851     }
3852     volatile regioncfg_r &set_region0(NPU_NAMESPACE::mem_attr value) volatile
3853     {
3854         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
3855         return *this;
3856     }
3857     CONSTEXPR NPU_NAMESPACE::mem_attr get_region1() const
3858     {
3859         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 2));
3860         return value;
3861     }
3862     NPU_NAMESPACE::mem_attr get_region1() const volatile
3863     {
3864         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 2));
3865         return value;
3866     }
3867     CONSTEXPR regioncfg_r &set_region1(NPU_NAMESPACE::mem_attr value)
3868     {
3869         word0 = (((~((1U << 2) - 1)) << 2) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 2);
3870         return *this;
3871     }
3872     volatile regioncfg_r &set_region1(NPU_NAMESPACE::mem_attr value) volatile
3873     {
3874         word0 = (((~((1U << 2) - 1)) << 2) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 2);
3875         return *this;
3876     }
3877     CONSTEXPR NPU_NAMESPACE::mem_attr get_region2() const
3878     {
3879         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 4));
3880         return value;
3881     }
3882     NPU_NAMESPACE::mem_attr get_region2() const volatile
3883     {
3884         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 4));
3885         return value;
3886     }
3887     CONSTEXPR regioncfg_r &set_region2(NPU_NAMESPACE::mem_attr value)
3888     {
3889         word0 = (((~((1U << 2) - 1)) << 4) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 4);
3890         return *this;
3891     }
3892     volatile regioncfg_r &set_region2(NPU_NAMESPACE::mem_attr value) volatile
3893     {
3894         word0 = (((~((1U << 2) - 1)) << 4) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 4);
3895         return *this;
3896     }
3897     CONSTEXPR NPU_NAMESPACE::mem_attr get_region3() const
3898     {
3899         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 6));
3900         return value;
3901     }
3902     NPU_NAMESPACE::mem_attr get_region3() const volatile
3903     {
3904         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 6));
3905         return value;
3906     }
3907     CONSTEXPR regioncfg_r &set_region3(NPU_NAMESPACE::mem_attr value)
3908     {
3909         word0 = (((~((1U << 2) - 1)) << 6) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 6);
3910         return *this;
3911     }
3912     volatile regioncfg_r &set_region3(NPU_NAMESPACE::mem_attr value) volatile
3913     {
3914         word0 = (((~((1U << 2) - 1)) << 6) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 6);
3915         return *this;
3916     }
3917     CONSTEXPR NPU_NAMESPACE::mem_attr get_region4() const
3918     {
3919         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 8));
3920         return value;
3921     }
3922     NPU_NAMESPACE::mem_attr get_region4() const volatile
3923     {
3924         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 8));
3925         return value;
3926     }
3927     CONSTEXPR regioncfg_r &set_region4(NPU_NAMESPACE::mem_attr value)
3928     {
3929         word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 8);
3930         return *this;
3931     }
3932     volatile regioncfg_r &set_region4(NPU_NAMESPACE::mem_attr value) volatile
3933     {
3934         word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 8);
3935         return *this;
3936     }
3937     CONSTEXPR NPU_NAMESPACE::mem_attr get_region5() const
3938     {
3939         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 10));
3940         return value;
3941     }
3942     NPU_NAMESPACE::mem_attr get_region5() const volatile
3943     {
3944         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 10));
3945         return value;
3946     }
3947     CONSTEXPR regioncfg_r &set_region5(NPU_NAMESPACE::mem_attr value)
3948     {
3949         word0 = (((~((1U << 2) - 1)) << 10) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 10);
3950         return *this;
3951     }
3952     volatile regioncfg_r &set_region5(NPU_NAMESPACE::mem_attr value) volatile
3953     {
3954         word0 = (((~((1U << 2) - 1)) << 10) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 10);
3955         return *this;
3956     }
3957     CONSTEXPR NPU_NAMESPACE::mem_attr get_region6() const
3958     {
3959         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 12));
3960         return value;
3961     }
3962     NPU_NAMESPACE::mem_attr get_region6() const volatile
3963     {
3964         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 12));
3965         return value;
3966     }
3967     CONSTEXPR regioncfg_r &set_region6(NPU_NAMESPACE::mem_attr value)
3968     {
3969         word0 = (((~((1U << 2) - 1)) << 12) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 12);
3970         return *this;
3971     }
3972     volatile regioncfg_r &set_region6(NPU_NAMESPACE::mem_attr value) volatile
3973     {
3974         word0 = (((~((1U << 2) - 1)) << 12) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 12);
3975         return *this;
3976     }
3977     CONSTEXPR NPU_NAMESPACE::mem_attr get_region7() const
3978     {
3979         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 14));
3980         return value;
3981     }
3982     NPU_NAMESPACE::mem_attr get_region7() const volatile
3983     {
3984         NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 14));
3985         return value;
3986     }
3987     CONSTEXPR regioncfg_r &set_region7(NPU_NAMESPACE::mem_attr value)
3988     {
3989         word0 = (((~((1U << 2) - 1)) << 14) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 14);
3990         return *this;
3991     }
3992     volatile regioncfg_r &set_region7(NPU_NAMESPACE::mem_attr value) volatile
3993     {
3994         word0 = (((~((1U << 2) - 1)) << 14) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 14);
3995         return *this;
3996     }
3997 #endif
3998 };
3999 
4000 // axi_limit0_r - AXI limits for port 0 counter 0
4001 struct axi_limit0_r
4002 {
4003 #ifndef __cplusplus
4004     union
4005     {
4006         struct
4007         {
4008             uint32_t max_beats : 2; // Burst split alignment
4009             uint32_t reserved0 : 2;
4010             uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals
4011             uint32_t reserved1 : 8;
4012             uint32_t
4013                 max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63
4014             uint32_t reserved2 : 2;
4015             uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range
4016                                                    // 0 to 31
4017             uint32_t reserved3 : 3;
4018         };
4019         uint32_t word;
4020     };
4021 #else
4022   private:
4023     uint32_t word0;
4024 
4025   public:
4026     CONSTEXPR axi_limit0_r() : word0(0) {}
4027     CONSTEXPR axi_limit0_r(uint32_t init) : word0(init) {}
4028     CONSTEXPR void operator=(uint32_t value)
4029     {
4030         word0 = value;
4031     }
4032     void operator=(uint32_t value) volatile
4033     {
4034         word0 = value;
4035     }
4036     CONSTEXPR operator uint32_t()
4037     {
4038         return word0;
4039     }
4040     operator uint32_t() volatile
4041     {
4042         return word0;
4043     }
4044     axi_limit0_r copy() volatile
4045     {
4046         return *this;
4047     }
4048     CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const
4049     {
4050         NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4051         return value;
4052     }
4053     NPU_NAMESPACE::max_beats get_max_beats() const volatile
4054     {
4055         NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4056         return value;
4057     }
4058     CONSTEXPR axi_limit0_r &set_max_beats(NPU_NAMESPACE::max_beats value)
4059     {
4060         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4061         return *this;
4062     }
4063     volatile axi_limit0_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile
4064     {
4065         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4066         return *this;
4067     }
4068     CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const
4069     {
4070         NPU_NAMESPACE::axi_mem_encoding value =
4071             static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4072         return value;
4073     }
4074     NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile
4075     {
4076         NPU_NAMESPACE::axi_mem_encoding value =
4077             static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4078         return value;
4079     }
4080     CONSTEXPR axi_limit0_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value)
4081     {
4082         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4083         return *this;
4084     }
4085     volatile axi_limit0_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile
4086     {
4087         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4088         return *this;
4089     }
4090     CONSTEXPR uint32_t get_max_outstanding_read_m1() const
4091     {
4092         uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4093         return value;
4094     }
4095     uint32_t get_max_outstanding_read_m1() const volatile
4096     {
4097         uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4098         return value;
4099     }
4100     CONSTEXPR axi_limit0_r &set_max_outstanding_read_m1(uint32_t value)
4101     {
4102         word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4103         return *this;
4104     }
4105     volatile axi_limit0_r &set_max_outstanding_read_m1(uint32_t value) volatile
4106     {
4107         word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4108         return *this;
4109     }
4110     CONSTEXPR uint32_t get_max_outstanding_write_m1() const
4111     {
4112         uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4113         return value;
4114     }
4115     uint32_t get_max_outstanding_write_m1() const volatile
4116     {
4117         uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4118         return value;
4119     }
4120     CONSTEXPR axi_limit0_r &set_max_outstanding_write_m1(uint32_t value)
4121     {
4122         word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4123         return *this;
4124     }
4125     volatile axi_limit0_r &set_max_outstanding_write_m1(uint32_t value) volatile
4126     {
4127         word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4128         return *this;
4129     }
4130 #endif
4131 };
4132 
4133 // axi_limit1_r - AXI limits for port 0 counter 1
4134 struct axi_limit1_r
4135 {
4136 #ifndef __cplusplus
4137     union
4138     {
4139         struct
4140         {
4141             uint32_t max_beats : 2; // Burst split alignment
4142             uint32_t reserved0 : 2;
4143             uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals
4144             uint32_t reserved1 : 8;
4145             uint32_t
4146                 max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63
4147             uint32_t reserved2 : 2;
4148             uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range
4149                                                    // 0 to 31
4150             uint32_t reserved3 : 3;
4151         };
4152         uint32_t word;
4153     };
4154 #else
4155   private:
4156     uint32_t word0;
4157 
4158   public:
4159     CONSTEXPR axi_limit1_r() : word0(0) {}
4160     CONSTEXPR axi_limit1_r(uint32_t init) : word0(init) {}
4161     CONSTEXPR void operator=(uint32_t value)
4162     {
4163         word0 = value;
4164     }
4165     void operator=(uint32_t value) volatile
4166     {
4167         word0 = value;
4168     }
4169     CONSTEXPR operator uint32_t()
4170     {
4171         return word0;
4172     }
4173     operator uint32_t() volatile
4174     {
4175         return word0;
4176     }
4177     axi_limit1_r copy() volatile
4178     {
4179         return *this;
4180     }
4181     CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const
4182     {
4183         NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4184         return value;
4185     }
4186     NPU_NAMESPACE::max_beats get_max_beats() const volatile
4187     {
4188         NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4189         return value;
4190     }
4191     CONSTEXPR axi_limit1_r &set_max_beats(NPU_NAMESPACE::max_beats value)
4192     {
4193         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4194         return *this;
4195     }
4196     volatile axi_limit1_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile
4197     {
4198         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4199         return *this;
4200     }
4201     CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const
4202     {
4203         NPU_NAMESPACE::axi_mem_encoding value =
4204             static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4205         return value;
4206     }
4207     NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile
4208     {
4209         NPU_NAMESPACE::axi_mem_encoding value =
4210             static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4211         return value;
4212     }
4213     CONSTEXPR axi_limit1_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value)
4214     {
4215         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4216         return *this;
4217     }
4218     volatile axi_limit1_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile
4219     {
4220         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4221         return *this;
4222     }
4223     CONSTEXPR uint32_t get_max_outstanding_read_m1() const
4224     {
4225         uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4226         return value;
4227     }
4228     uint32_t get_max_outstanding_read_m1() const volatile
4229     {
4230         uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4231         return value;
4232     }
4233     CONSTEXPR axi_limit1_r &set_max_outstanding_read_m1(uint32_t value)
4234     {
4235         word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4236         return *this;
4237     }
4238     volatile axi_limit1_r &set_max_outstanding_read_m1(uint32_t value) volatile
4239     {
4240         word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4241         return *this;
4242     }
4243     CONSTEXPR uint32_t get_max_outstanding_write_m1() const
4244     {
4245         uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4246         return value;
4247     }
4248     uint32_t get_max_outstanding_write_m1() const volatile
4249     {
4250         uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4251         return value;
4252     }
4253     CONSTEXPR axi_limit1_r &set_max_outstanding_write_m1(uint32_t value)
4254     {
4255         word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4256         return *this;
4257     }
4258     volatile axi_limit1_r &set_max_outstanding_write_m1(uint32_t value) volatile
4259     {
4260         word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4261         return *this;
4262     }
4263 #endif
4264 };
4265 
4266 // axi_limit2_r - AXI limits for port 1 counter 2
4267 struct axi_limit2_r
4268 {
4269 #ifndef __cplusplus
4270     union
4271     {
4272         struct
4273         {
4274             uint32_t max_beats : 2; // Burst split alignment
4275             uint32_t reserved0 : 2;
4276             uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals
4277             uint32_t reserved1 : 8;
4278             uint32_t
4279                 max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63
4280             uint32_t reserved2 : 2;
4281             uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range
4282                                                    // 0 to 31
4283             uint32_t reserved3 : 3;
4284         };
4285         uint32_t word;
4286     };
4287 #else
4288   private:
4289     uint32_t word0;
4290 
4291   public:
4292     CONSTEXPR axi_limit2_r() : word0(0) {}
4293     CONSTEXPR axi_limit2_r(uint32_t init) : word0(init) {}
4294     CONSTEXPR void operator=(uint32_t value)
4295     {
4296         word0 = value;
4297     }
4298     void operator=(uint32_t value) volatile
4299     {
4300         word0 = value;
4301     }
4302     CONSTEXPR operator uint32_t()
4303     {
4304         return word0;
4305     }
4306     operator uint32_t() volatile
4307     {
4308         return word0;
4309     }
4310     axi_limit2_r copy() volatile
4311     {
4312         return *this;
4313     }
4314     CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const
4315     {
4316         NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4317         return value;
4318     }
4319     NPU_NAMESPACE::max_beats get_max_beats() const volatile
4320     {
4321         NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4322         return value;
4323     }
4324     CONSTEXPR axi_limit2_r &set_max_beats(NPU_NAMESPACE::max_beats value)
4325     {
4326         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4327         return *this;
4328     }
4329     volatile axi_limit2_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile
4330     {
4331         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4332         return *this;
4333     }
4334     CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const
4335     {
4336         NPU_NAMESPACE::axi_mem_encoding value =
4337             static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4338         return value;
4339     }
4340     NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile
4341     {
4342         NPU_NAMESPACE::axi_mem_encoding value =
4343             static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4344         return value;
4345     }
4346     CONSTEXPR axi_limit2_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value)
4347     {
4348         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4349         return *this;
4350     }
4351     volatile axi_limit2_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile
4352     {
4353         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4354         return *this;
4355     }
4356     CONSTEXPR uint32_t get_max_outstanding_read_m1() const
4357     {
4358         uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4359         return value;
4360     }
4361     uint32_t get_max_outstanding_read_m1() const volatile
4362     {
4363         uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4364         return value;
4365     }
4366     CONSTEXPR axi_limit2_r &set_max_outstanding_read_m1(uint32_t value)
4367     {
4368         word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4369         return *this;
4370     }
4371     volatile axi_limit2_r &set_max_outstanding_read_m1(uint32_t value) volatile
4372     {
4373         word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4374         return *this;
4375     }
4376     CONSTEXPR uint32_t get_max_outstanding_write_m1() const
4377     {
4378         uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4379         return value;
4380     }
4381     uint32_t get_max_outstanding_write_m1() const volatile
4382     {
4383         uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4384         return value;
4385     }
4386     CONSTEXPR axi_limit2_r &set_max_outstanding_write_m1(uint32_t value)
4387     {
4388         word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4389         return *this;
4390     }
4391     volatile axi_limit2_r &set_max_outstanding_write_m1(uint32_t value) volatile
4392     {
4393         word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4394         return *this;
4395     }
4396 #endif
4397 };
4398 
4399 // axi_limit3_r - AXI limits for port 1 counter 3
4400 struct axi_limit3_r
4401 {
4402 #ifndef __cplusplus
4403     union
4404     {
4405         struct
4406         {
4407             uint32_t max_beats : 2; // Burst split alignment
4408             uint32_t reserved0 : 2;
4409             uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals
4410             uint32_t reserved1 : 8;
4411             uint32_t
4412                 max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63
4413             uint32_t reserved2 : 2;
4414             uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range
4415                                                    // 0 to 31
4416             uint32_t reserved3 : 3;
4417         };
4418         uint32_t word;
4419     };
4420 #else
4421   private:
4422     uint32_t word0;
4423 
4424   public:
4425     CONSTEXPR axi_limit3_r() : word0(0) {}
4426     CONSTEXPR axi_limit3_r(uint32_t init) : word0(init) {}
4427     CONSTEXPR void operator=(uint32_t value)
4428     {
4429         word0 = value;
4430     }
4431     void operator=(uint32_t value) volatile
4432     {
4433         word0 = value;
4434     }
4435     CONSTEXPR operator uint32_t()
4436     {
4437         return word0;
4438     }
4439     operator uint32_t() volatile
4440     {
4441         return word0;
4442     }
4443     axi_limit3_r copy() volatile
4444     {
4445         return *this;
4446     }
4447     CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const
4448     {
4449         NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4450         return value;
4451     }
4452     NPU_NAMESPACE::max_beats get_max_beats() const volatile
4453     {
4454         NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4455         return value;
4456     }
4457     CONSTEXPR axi_limit3_r &set_max_beats(NPU_NAMESPACE::max_beats value)
4458     {
4459         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4460         return *this;
4461     }
4462     volatile axi_limit3_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile
4463     {
4464         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4465         return *this;
4466     }
4467     CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const
4468     {
4469         NPU_NAMESPACE::axi_mem_encoding value =
4470             static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4471         return value;
4472     }
4473     NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile
4474     {
4475         NPU_NAMESPACE::axi_mem_encoding value =
4476             static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4477         return value;
4478     }
4479     CONSTEXPR axi_limit3_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value)
4480     {
4481         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4482         return *this;
4483     }
4484     volatile axi_limit3_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile
4485     {
4486         word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4487         return *this;
4488     }
4489     CONSTEXPR uint32_t get_max_outstanding_read_m1() const
4490     {
4491         uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4492         return value;
4493     }
4494     uint32_t get_max_outstanding_read_m1() const volatile
4495     {
4496         uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4497         return value;
4498     }
4499     CONSTEXPR axi_limit3_r &set_max_outstanding_read_m1(uint32_t value)
4500     {
4501         word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4502         return *this;
4503     }
4504     volatile axi_limit3_r &set_max_outstanding_read_m1(uint32_t value) volatile
4505     {
4506         word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4507         return *this;
4508     }
4509     CONSTEXPR uint32_t get_max_outstanding_write_m1() const
4510     {
4511         uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4512         return value;
4513     }
4514     uint32_t get_max_outstanding_write_m1() const volatile
4515     {
4516         uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4517         return value;
4518     }
4519     CONSTEXPR axi_limit3_r &set_max_outstanding_write_m1(uint32_t value)
4520     {
4521         word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4522         return *this;
4523     }
4524     volatile axi_limit3_r &set_max_outstanding_write_m1(uint32_t value) volatile
4525     {
4526         word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4527         return *this;
4528     }
4529 #endif
4530 };
4531 
4532 // basep_r - The driver can use this address to relocate the command stream on region 0. If the region contains data
4533 // requiring A-byte alignment then the base must be a multiple of A
4534 struct basep_r
4535 {
4536 #ifndef __cplusplus
4537     union
4538     {
4539         struct
4540         {
4541             uint32_t offset_LO : 32; // Offset - LSB
4542             uint32_t offset_HI : 8;  // Offset - MSB
4543             uint32_t reserved0 : 24;
4544         };
4545         uint32_t word[2];
4546     };
4547 #else
4548   private:
4549     uint32_t word0;
4550     uint32_t word1;
4551 
4552   public:
4553     CONSTEXPR basep_r() : word0(0), word1(0) {}
4554     CONSTEXPR basep_r(uint64_t init) :
4555         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
4556         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
4557     {
4558     }
4559     CONSTEXPR void operator=(uint64_t value)
4560     {
4561         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
4562         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
4563     }
4564     void operator=(uint64_t value) volatile
4565     {
4566         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
4567         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
4568     }
4569     CONSTEXPR operator uint64_t()
4570     {
4571         return (static_cast<uint64_t>(word1) << 32) | word0;
4572     }
4573     operator uint64_t() volatile
4574     {
4575         return (static_cast<uint64_t>(word1) << 32) | word0;
4576     }
4577     basep_r copy() volatile
4578     {
4579         return *this;
4580     }
4581 #endif
4582 };
4583 
4584 // wd_status_r - WD_STATUS
4585 struct wd_status_r
4586 {
4587 #ifndef __cplusplus
4588     union
4589     {
4590         struct
4591         {
4592             uint32_t core_slice_state : 2; // WD core slice parser state
4593             uint32_t core_idle : 1;        // Core idle
4594             uint32_t ctrl_state : 2;       // WD control state
4595             uint32_t ctrl_idle : 1;        // All stripe jobs idle (all weights consumed)
4596             uint32_t write_buf_index0 : 3; // current write index for next data from core
4597             uint32_t write_buf_valid0 : 1; // write buf valid (full)
4598             uint32_t write_buf_idle0 : 1;  // write buf idle (empty)
4599             uint32_t write_buf_index1 : 3; // current write index for next data from core
4600             uint32_t write_buf_valid1 : 1; // write buf valid (full)
4601             uint32_t write_buf_idle1 : 1;  // write buf idle (empty)
4602             uint32_t events : 12;          // WD events mapped as appendix A
4603             uint32_t reserved0 : 4;
4604         };
4605         uint32_t word;
4606     };
4607 #else
4608   private:
4609     uint32_t word0;
4610 
4611   public:
4612     CONSTEXPR wd_status_r() : word0(0) {}
4613     CONSTEXPR wd_status_r(uint32_t init) : word0(init) {}
4614     CONSTEXPR void operator=(uint32_t value)
4615     {
4616         word0 = value;
4617     }
4618     void operator=(uint32_t value) volatile
4619     {
4620         word0 = value;
4621     }
4622     CONSTEXPR operator uint32_t()
4623     {
4624         return word0;
4625     }
4626     operator uint32_t() volatile
4627     {
4628         return word0;
4629     }
4630     wd_status_r copy() volatile
4631     {
4632         return *this;
4633     }
4634     CONSTEXPR NPU_NAMESPACE::wd_core_slice_state get_core_slice_state() const
4635     {
4636         NPU_NAMESPACE::wd_core_slice_state value =
4637             static_cast<NPU_NAMESPACE::wd_core_slice_state>(((1U << 2) - 1) & (word0 >> 0));
4638         return value;
4639     }
4640     NPU_NAMESPACE::wd_core_slice_state get_core_slice_state() const volatile
4641     {
4642         NPU_NAMESPACE::wd_core_slice_state value =
4643             static_cast<NPU_NAMESPACE::wd_core_slice_state>(((1U << 2) - 1) & (word0 >> 0));
4644         return value;
4645     }
4646     CONSTEXPR wd_status_r &set_core_slice_state(NPU_NAMESPACE::wd_core_slice_state value)
4647     {
4648         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4649         return *this;
4650     }
4651     volatile wd_status_r &set_core_slice_state(NPU_NAMESPACE::wd_core_slice_state value) volatile
4652     {
4653         word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4654         return *this;
4655     }
4656     CONSTEXPR uint32_t get_core_idle() const
4657     {
4658         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
4659         return value;
4660     }
4661     uint32_t get_core_idle() const volatile
4662     {
4663         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
4664         return value;
4665     }
4666     CONSTEXPR wd_status_r &set_core_idle(uint32_t value)
4667     {
4668         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
4669         return *this;
4670     }
4671     volatile wd_status_r &set_core_idle(uint32_t value) volatile
4672     {
4673         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
4674         return *this;
4675     }
4676     CONSTEXPR NPU_NAMESPACE::wd_ctrl_state get_ctrl_state() const
4677     {
4678         NPU_NAMESPACE::wd_ctrl_state value = static_cast<NPU_NAMESPACE::wd_ctrl_state>(((1U << 2) - 1) & (word0 >> 3));
4679         return value;
4680     }
4681     NPU_NAMESPACE::wd_ctrl_state get_ctrl_state() const volatile
4682     {
4683         NPU_NAMESPACE::wd_ctrl_state value = static_cast<NPU_NAMESPACE::wd_ctrl_state>(((1U << 2) - 1) & (word0 >> 3));
4684         return value;
4685     }
4686     CONSTEXPR wd_status_r &set_ctrl_state(NPU_NAMESPACE::wd_ctrl_state value)
4687     {
4688         word0 = (((~((1U << 2) - 1)) << 3) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 3);
4689         return *this;
4690     }
4691     volatile wd_status_r &set_ctrl_state(NPU_NAMESPACE::wd_ctrl_state value) volatile
4692     {
4693         word0 = (((~((1U << 2) - 1)) << 3) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 3);
4694         return *this;
4695     }
4696     CONSTEXPR uint32_t get_ctrl_idle() const
4697     {
4698         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
4699         return value;
4700     }
4701     uint32_t get_ctrl_idle() const volatile
4702     {
4703         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
4704         return value;
4705     }
4706     CONSTEXPR wd_status_r &set_ctrl_idle(uint32_t value)
4707     {
4708         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
4709         return *this;
4710     }
4711     volatile wd_status_r &set_ctrl_idle(uint32_t value) volatile
4712     {
4713         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
4714         return *this;
4715     }
4716     CONSTEXPR uint32_t get_write_buf_index0() const
4717     {
4718         uint32_t value = ((1U << 3) - 1) & (word0 >> 6);
4719         return value;
4720     }
4721     uint32_t get_write_buf_index0() const volatile
4722     {
4723         uint32_t value = ((1U << 3) - 1) & (word0 >> 6);
4724         return value;
4725     }
4726     CONSTEXPR wd_status_r &set_write_buf_index0(uint32_t value)
4727     {
4728         word0 = (((~((1U << 3) - 1)) << 6) & word0) | ((((1U << 3) - 1) & value) << 6);
4729         return *this;
4730     }
4731     volatile wd_status_r &set_write_buf_index0(uint32_t value) volatile
4732     {
4733         word0 = (((~((1U << 3) - 1)) << 6) & word0) | ((((1U << 3) - 1) & value) << 6);
4734         return *this;
4735     }
4736     CONSTEXPR uint32_t get_write_buf_valid0() const
4737     {
4738         uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
4739         return value;
4740     }
4741     uint32_t get_write_buf_valid0() const volatile
4742     {
4743         uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
4744         return value;
4745     }
4746     CONSTEXPR wd_status_r &set_write_buf_valid0(uint32_t value)
4747     {
4748         word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
4749         return *this;
4750     }
4751     volatile wd_status_r &set_write_buf_valid0(uint32_t value) volatile
4752     {
4753         word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
4754         return *this;
4755     }
4756     CONSTEXPR uint32_t get_write_buf_idle0() const
4757     {
4758         uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
4759         return value;
4760     }
4761     uint32_t get_write_buf_idle0() const volatile
4762     {
4763         uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
4764         return value;
4765     }
4766     CONSTEXPR wd_status_r &set_write_buf_idle0(uint32_t value)
4767     {
4768         word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
4769         return *this;
4770     }
4771     volatile wd_status_r &set_write_buf_idle0(uint32_t value) volatile
4772     {
4773         word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
4774         return *this;
4775     }
4776     CONSTEXPR uint32_t get_write_buf_index1() const
4777     {
4778         uint32_t value = ((1U << 3) - 1) & (word0 >> 11);
4779         return value;
4780     }
4781     uint32_t get_write_buf_index1() const volatile
4782     {
4783         uint32_t value = ((1U << 3) - 1) & (word0 >> 11);
4784         return value;
4785     }
4786     CONSTEXPR wd_status_r &set_write_buf_index1(uint32_t value)
4787     {
4788         word0 = (((~((1U << 3) - 1)) << 11) & word0) | ((((1U << 3) - 1) & value) << 11);
4789         return *this;
4790     }
4791     volatile wd_status_r &set_write_buf_index1(uint32_t value) volatile
4792     {
4793         word0 = (((~((1U << 3) - 1)) << 11) & word0) | ((((1U << 3) - 1) & value) << 11);
4794         return *this;
4795     }
4796     CONSTEXPR uint32_t get_write_buf_valid1() const
4797     {
4798         uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
4799         return value;
4800     }
4801     uint32_t get_write_buf_valid1() const volatile
4802     {
4803         uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
4804         return value;
4805     }
4806     CONSTEXPR wd_status_r &set_write_buf_valid1(uint32_t value)
4807     {
4808         word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
4809         return *this;
4810     }
4811     volatile wd_status_r &set_write_buf_valid1(uint32_t value) volatile
4812     {
4813         word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
4814         return *this;
4815     }
4816     CONSTEXPR uint32_t get_write_buf_idle1() const
4817     {
4818         uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
4819         return value;
4820     }
4821     uint32_t get_write_buf_idle1() const volatile
4822     {
4823         uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
4824         return value;
4825     }
4826     CONSTEXPR wd_status_r &set_write_buf_idle1(uint32_t value)
4827     {
4828         word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
4829         return *this;
4830     }
4831     volatile wd_status_r &set_write_buf_idle1(uint32_t value) volatile
4832     {
4833         word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
4834         return *this;
4835     }
4836     CONSTEXPR uint32_t get_events() const
4837     {
4838         uint32_t value = ((1U << 12) - 1) & (word0 >> 16);
4839         return value;
4840     }
4841     uint32_t get_events() const volatile
4842     {
4843         uint32_t value = ((1U << 12) - 1) & (word0 >> 16);
4844         return value;
4845     }
4846     CONSTEXPR wd_status_r &set_events(uint32_t value)
4847     {
4848         word0 = (((~((1U << 12) - 1)) << 16) & word0) | ((((1U << 12) - 1) & value) << 16);
4849         return *this;
4850     }
4851     volatile wd_status_r &set_events(uint32_t value) volatile
4852     {
4853         word0 = (((~((1U << 12) - 1)) << 16) & word0) | ((((1U << 12) - 1) & value) << 16);
4854         return *this;
4855     }
4856 #endif
4857 };
4858 
4859 // mac_status_r - MAC_STATUS
4860 struct mac_status_r
4861 {
4862 #ifndef __cplusplus
4863     union
4864     {
4865         struct
4866         {
4867             uint32_t block_cfg_valid : 1;     // MAC has a valid block configuration
4868             uint32_t trav_en : 1;             // MAC is doing block traversal
4869             uint32_t wait_for_ib : 1;         // MAC is waiting for an Input Buffer to become available
4870             uint32_t wait_for_acc_buf : 1;    // MAC is waiting for an Accumulator Buffer to become available
4871             uint32_t wait_for_weights : 1;    // MAC is waiting for a Weight Block to become available
4872             uint32_t stall_stripe : 1;        // MAC is stalling between two stripes
4873             uint32_t dw_sel : 1;              // Currently used weight interface in MAC AI
4874             uint32_t wait_for_dw0_ready : 1;  // MAC AI is waiting for MAC DPU to send dw0_ready to WD
4875             uint32_t wait_for_dw1_ready : 1;  // MAC AI is waiting for MAC DPU to send dw1_ready to WD
4876             uint32_t acc_buf_sel_ai : 1;      // Currently used AccBuf interface in MAC AI
4877             uint32_t wait_for_acc0_ready : 1; // MAC AI is waiting for acc0_ready from AO
4878             uint32_t wait_for_acc1_ready : 1; // MAC AI is waiting for acc1_ready from AO
4879             uint32_t acc_buf_sel_aa : 1;      // Currently used AccBuf interface in MAC ADDER_ARRAY
4880             uint32_t acc0_valid : 1;          // MAC outgoing value of acc0_valid
4881             uint32_t acc1_valid : 1;          // MAC outgoing value of acc1_valid
4882             uint32_t reserved0 : 1;
4883             uint32_t events : 11; // Mapped to MAC events described in Appendix A
4884             uint32_t reserved1 : 5;
4885         };
4886         uint32_t word;
4887     };
4888 #else
4889   private:
4890     uint32_t word0;
4891 
4892   public:
4893     CONSTEXPR mac_status_r() : word0(0) {}
4894     CONSTEXPR mac_status_r(uint32_t init) : word0(init) {}
4895     CONSTEXPR void operator=(uint32_t value)
4896     {
4897         word0 = value;
4898     }
4899     void operator=(uint32_t value) volatile
4900     {
4901         word0 = value;
4902     }
4903     CONSTEXPR operator uint32_t()
4904     {
4905         return word0;
4906     }
4907     operator uint32_t() volatile
4908     {
4909         return word0;
4910     }
4911     mac_status_r copy() volatile
4912     {
4913         return *this;
4914     }
4915     CONSTEXPR uint32_t get_block_cfg_valid() const
4916     {
4917         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
4918         return value;
4919     }
4920     uint32_t get_block_cfg_valid() const volatile
4921     {
4922         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
4923         return value;
4924     }
4925     CONSTEXPR mac_status_r &set_block_cfg_valid(uint32_t value)
4926     {
4927         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
4928         return *this;
4929     }
4930     volatile mac_status_r &set_block_cfg_valid(uint32_t value) volatile
4931     {
4932         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
4933         return *this;
4934     }
4935     CONSTEXPR uint32_t get_trav_en() const
4936     {
4937         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
4938         return value;
4939     }
4940     uint32_t get_trav_en() const volatile
4941     {
4942         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
4943         return value;
4944     }
4945     CONSTEXPR mac_status_r &set_trav_en(uint32_t value)
4946     {
4947         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
4948         return *this;
4949     }
4950     volatile mac_status_r &set_trav_en(uint32_t value) volatile
4951     {
4952         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
4953         return *this;
4954     }
4955     CONSTEXPR uint32_t get_wait_for_ib() const
4956     {
4957         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
4958         return value;
4959     }
4960     uint32_t get_wait_for_ib() const volatile
4961     {
4962         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
4963         return value;
4964     }
4965     CONSTEXPR mac_status_r &set_wait_for_ib(uint32_t value)
4966     {
4967         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
4968         return *this;
4969     }
4970     volatile mac_status_r &set_wait_for_ib(uint32_t value) volatile
4971     {
4972         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
4973         return *this;
4974     }
4975     CONSTEXPR uint32_t get_wait_for_acc_buf() const
4976     {
4977         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
4978         return value;
4979     }
4980     uint32_t get_wait_for_acc_buf() const volatile
4981     {
4982         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
4983         return value;
4984     }
4985     CONSTEXPR mac_status_r &set_wait_for_acc_buf(uint32_t value)
4986     {
4987         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
4988         return *this;
4989     }
4990     volatile mac_status_r &set_wait_for_acc_buf(uint32_t value) volatile
4991     {
4992         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
4993         return *this;
4994     }
4995     CONSTEXPR uint32_t get_wait_for_weights() const
4996     {
4997         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
4998         return value;
4999     }
5000     uint32_t get_wait_for_weights() const volatile
5001     {
5002         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
5003         return value;
5004     }
5005     CONSTEXPR mac_status_r &set_wait_for_weights(uint32_t value)
5006     {
5007         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5008         return *this;
5009     }
5010     volatile mac_status_r &set_wait_for_weights(uint32_t value) volatile
5011     {
5012         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5013         return *this;
5014     }
5015     CONSTEXPR uint32_t get_stall_stripe() const
5016     {
5017         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5018         return value;
5019     }
5020     uint32_t get_stall_stripe() const volatile
5021     {
5022         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5023         return value;
5024     }
5025     CONSTEXPR mac_status_r &set_stall_stripe(uint32_t value)
5026     {
5027         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5028         return *this;
5029     }
5030     volatile mac_status_r &set_stall_stripe(uint32_t value) volatile
5031     {
5032         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5033         return *this;
5034     }
5035     CONSTEXPR uint32_t get_dw_sel() const
5036     {
5037         uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5038         return value;
5039     }
5040     uint32_t get_dw_sel() const volatile
5041     {
5042         uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5043         return value;
5044     }
5045     CONSTEXPR mac_status_r &set_dw_sel(uint32_t value)
5046     {
5047         word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5048         return *this;
5049     }
5050     volatile mac_status_r &set_dw_sel(uint32_t value) volatile
5051     {
5052         word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5053         return *this;
5054     }
5055     CONSTEXPR uint32_t get_wait_for_dw0_ready() const
5056     {
5057         uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5058         return value;
5059     }
5060     uint32_t get_wait_for_dw0_ready() const volatile
5061     {
5062         uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5063         return value;
5064     }
5065     CONSTEXPR mac_status_r &set_wait_for_dw0_ready(uint32_t value)
5066     {
5067         word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5068         return *this;
5069     }
5070     volatile mac_status_r &set_wait_for_dw0_ready(uint32_t value) volatile
5071     {
5072         word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5073         return *this;
5074     }
5075     CONSTEXPR uint32_t get_wait_for_dw1_ready() const
5076     {
5077         uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
5078         return value;
5079     }
5080     uint32_t get_wait_for_dw1_ready() const volatile
5081     {
5082         uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
5083         return value;
5084     }
5085     CONSTEXPR mac_status_r &set_wait_for_dw1_ready(uint32_t value)
5086     {
5087         word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
5088         return *this;
5089     }
5090     volatile mac_status_r &set_wait_for_dw1_ready(uint32_t value) volatile
5091     {
5092         word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
5093         return *this;
5094     }
5095     CONSTEXPR uint32_t get_acc_buf_sel_ai() const
5096     {
5097         uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
5098         return value;
5099     }
5100     uint32_t get_acc_buf_sel_ai() const volatile
5101     {
5102         uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
5103         return value;
5104     }
5105     CONSTEXPR mac_status_r &set_acc_buf_sel_ai(uint32_t value)
5106     {
5107         word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
5108         return *this;
5109     }
5110     volatile mac_status_r &set_acc_buf_sel_ai(uint32_t value) volatile
5111     {
5112         word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
5113         return *this;
5114     }
5115     CONSTEXPR uint32_t get_wait_for_acc0_ready() const
5116     {
5117         uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
5118         return value;
5119     }
5120     uint32_t get_wait_for_acc0_ready() const volatile
5121     {
5122         uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
5123         return value;
5124     }
5125     CONSTEXPR mac_status_r &set_wait_for_acc0_ready(uint32_t value)
5126     {
5127         word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
5128         return *this;
5129     }
5130     volatile mac_status_r &set_wait_for_acc0_ready(uint32_t value) volatile
5131     {
5132         word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
5133         return *this;
5134     }
5135     CONSTEXPR uint32_t get_wait_for_acc1_ready() const
5136     {
5137         uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
5138         return value;
5139     }
5140     uint32_t get_wait_for_acc1_ready() const volatile
5141     {
5142         uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
5143         return value;
5144     }
5145     CONSTEXPR mac_status_r &set_wait_for_acc1_ready(uint32_t value)
5146     {
5147         word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
5148         return *this;
5149     }
5150     volatile mac_status_r &set_wait_for_acc1_ready(uint32_t value) volatile
5151     {
5152         word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
5153         return *this;
5154     }
5155     CONSTEXPR uint32_t get_acc_buf_sel_aa() const
5156     {
5157         uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
5158         return value;
5159     }
5160     uint32_t get_acc_buf_sel_aa() const volatile
5161     {
5162         uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
5163         return value;
5164     }
5165     CONSTEXPR mac_status_r &set_acc_buf_sel_aa(uint32_t value)
5166     {
5167         word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
5168         return *this;
5169     }
5170     volatile mac_status_r &set_acc_buf_sel_aa(uint32_t value) volatile
5171     {
5172         word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
5173         return *this;
5174     }
5175     CONSTEXPR uint32_t get_acc0_valid() const
5176     {
5177         uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
5178         return value;
5179     }
5180     uint32_t get_acc0_valid() const volatile
5181     {
5182         uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
5183         return value;
5184     }
5185     CONSTEXPR mac_status_r &set_acc0_valid(uint32_t value)
5186     {
5187         word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
5188         return *this;
5189     }
5190     volatile mac_status_r &set_acc0_valid(uint32_t value) volatile
5191     {
5192         word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
5193         return *this;
5194     }
5195     CONSTEXPR uint32_t get_acc1_valid() const
5196     {
5197         uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
5198         return value;
5199     }
5200     uint32_t get_acc1_valid() const volatile
5201     {
5202         uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
5203         return value;
5204     }
5205     CONSTEXPR mac_status_r &set_acc1_valid(uint32_t value)
5206     {
5207         word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
5208         return *this;
5209     }
5210     volatile mac_status_r &set_acc1_valid(uint32_t value) volatile
5211     {
5212         word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
5213         return *this;
5214     }
5215     CONSTEXPR uint32_t get_events() const
5216     {
5217         uint32_t value = ((1U << 11) - 1) & (word0 >> 16);
5218         return value;
5219     }
5220     uint32_t get_events() const volatile
5221     {
5222         uint32_t value = ((1U << 11) - 1) & (word0 >> 16);
5223         return value;
5224     }
5225     CONSTEXPR mac_status_r &set_events(uint32_t value)
5226     {
5227         word0 = (((~((1U << 11) - 1)) << 16) & word0) | ((((1U << 11) - 1) & value) << 16);
5228         return *this;
5229     }
5230     volatile mac_status_r &set_events(uint32_t value) volatile
5231     {
5232         word0 = (((~((1U << 11) - 1)) << 16) & word0) | ((((1U << 11) - 1) & value) << 16);
5233         return *this;
5234     }
5235 #endif
5236 };
5237 
5238 // ao_status_r - AO_STATUS
5239 struct ao_status_r
5240 {
5241 #ifndef __cplusplus
5242     union
5243     {
5244         struct
5245         {
5246             uint32_t cmd_sbw_valid : 1; // Block command to shared buffer write module is valid
5247             uint32_t cmd_act_valid : 1; // Block command to activation function module is valid
5248             uint32_t cmd_ctl_valid : 1; // Block command to control module is valid
5249             uint32_t cmd_scl_valid : 1; // Block command to scale module is valid
5250             uint32_t cmd_sbr_valid : 1; // Block command to shared buffer read module is valid
5251             uint32_t cmd_ofm_valid : 1; // Block command to ofm parameter module is valid
5252             uint32_t blk_cmd_ready : 1; // Ready to accept block command
5253             uint32_t blk_cmd_valid : 1; // Block command from CC is valid
5254             uint32_t reserved0 : 8;
5255             uint32_t events : 8; // Mapped to AO events described in Appendix A
5256             uint32_t reserved1 : 8;
5257         };
5258         uint32_t word;
5259     };
5260 #else
5261   private:
5262     uint32_t word0;
5263 
5264   public:
5265     CONSTEXPR ao_status_r() : word0(0) {}
5266     CONSTEXPR ao_status_r(uint32_t init) : word0(init) {}
5267     CONSTEXPR void operator=(uint32_t value)
5268     {
5269         word0 = value;
5270     }
5271     void operator=(uint32_t value) volatile
5272     {
5273         word0 = value;
5274     }
5275     CONSTEXPR operator uint32_t()
5276     {
5277         return word0;
5278     }
5279     operator uint32_t() volatile
5280     {
5281         return word0;
5282     }
5283     ao_status_r copy() volatile
5284     {
5285         return *this;
5286     }
5287     CONSTEXPR uint32_t get_cmd_sbw_valid() const
5288     {
5289         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
5290         return value;
5291     }
5292     uint32_t get_cmd_sbw_valid() const volatile
5293     {
5294         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
5295         return value;
5296     }
5297     CONSTEXPR ao_status_r &set_cmd_sbw_valid(uint32_t value)
5298     {
5299         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
5300         return *this;
5301     }
5302     volatile ao_status_r &set_cmd_sbw_valid(uint32_t value) volatile
5303     {
5304         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
5305         return *this;
5306     }
5307     CONSTEXPR uint32_t get_cmd_act_valid() const
5308     {
5309         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
5310         return value;
5311     }
5312     uint32_t get_cmd_act_valid() const volatile
5313     {
5314         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
5315         return value;
5316     }
5317     CONSTEXPR ao_status_r &set_cmd_act_valid(uint32_t value)
5318     {
5319         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
5320         return *this;
5321     }
5322     volatile ao_status_r &set_cmd_act_valid(uint32_t value) volatile
5323     {
5324         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
5325         return *this;
5326     }
5327     CONSTEXPR uint32_t get_cmd_ctl_valid() const
5328     {
5329         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
5330         return value;
5331     }
5332     uint32_t get_cmd_ctl_valid() const volatile
5333     {
5334         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
5335         return value;
5336     }
5337     CONSTEXPR ao_status_r &set_cmd_ctl_valid(uint32_t value)
5338     {
5339         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
5340         return *this;
5341     }
5342     volatile ao_status_r &set_cmd_ctl_valid(uint32_t value) volatile
5343     {
5344         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
5345         return *this;
5346     }
5347     CONSTEXPR uint32_t get_cmd_scl_valid() const
5348     {
5349         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
5350         return value;
5351     }
5352     uint32_t get_cmd_scl_valid() const volatile
5353     {
5354         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
5355         return value;
5356     }
5357     CONSTEXPR ao_status_r &set_cmd_scl_valid(uint32_t value)
5358     {
5359         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
5360         return *this;
5361     }
5362     volatile ao_status_r &set_cmd_scl_valid(uint32_t value) volatile
5363     {
5364         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
5365         return *this;
5366     }
5367     CONSTEXPR uint32_t get_cmd_sbr_valid() const
5368     {
5369         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
5370         return value;
5371     }
5372     uint32_t get_cmd_sbr_valid() const volatile
5373     {
5374         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
5375         return value;
5376     }
5377     CONSTEXPR ao_status_r &set_cmd_sbr_valid(uint32_t value)
5378     {
5379         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5380         return *this;
5381     }
5382     volatile ao_status_r &set_cmd_sbr_valid(uint32_t value) volatile
5383     {
5384         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5385         return *this;
5386     }
5387     CONSTEXPR uint32_t get_cmd_ofm_valid() const
5388     {
5389         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5390         return value;
5391     }
5392     uint32_t get_cmd_ofm_valid() const volatile
5393     {
5394         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5395         return value;
5396     }
5397     CONSTEXPR ao_status_r &set_cmd_ofm_valid(uint32_t value)
5398     {
5399         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5400         return *this;
5401     }
5402     volatile ao_status_r &set_cmd_ofm_valid(uint32_t value) volatile
5403     {
5404         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5405         return *this;
5406     }
5407     CONSTEXPR uint32_t get_blk_cmd_ready() const
5408     {
5409         uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5410         return value;
5411     }
5412     uint32_t get_blk_cmd_ready() const volatile
5413     {
5414         uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5415         return value;
5416     }
5417     CONSTEXPR ao_status_r &set_blk_cmd_ready(uint32_t value)
5418     {
5419         word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5420         return *this;
5421     }
5422     volatile ao_status_r &set_blk_cmd_ready(uint32_t value) volatile
5423     {
5424         word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5425         return *this;
5426     }
5427     CONSTEXPR uint32_t get_blk_cmd_valid() const
5428     {
5429         uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5430         return value;
5431     }
5432     uint32_t get_blk_cmd_valid() const volatile
5433     {
5434         uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5435         return value;
5436     }
5437     CONSTEXPR ao_status_r &set_blk_cmd_valid(uint32_t value)
5438     {
5439         word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5440         return *this;
5441     }
5442     volatile ao_status_r &set_blk_cmd_valid(uint32_t value) volatile
5443     {
5444         word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5445         return *this;
5446     }
5447     CONSTEXPR uint32_t get_events() const
5448     {
5449         uint32_t value = ((1U << 8) - 1) & (word0 >> 16);
5450         return value;
5451     }
5452     uint32_t get_events() const volatile
5453     {
5454         uint32_t value = ((1U << 8) - 1) & (word0 >> 16);
5455         return value;
5456     }
5457     CONSTEXPR ao_status_r &set_events(uint32_t value)
5458     {
5459         word0 = (((~((1U << 8) - 1)) << 16) & word0) | ((((1U << 8) - 1) & value) << 16);
5460         return *this;
5461     }
5462     volatile ao_status_r &set_events(uint32_t value) volatile
5463     {
5464         word0 = (((~((1U << 8) - 1)) << 16) & word0) | ((((1U << 8) - 1) & value) << 16);
5465         return *this;
5466     }
5467 #endif
5468 };
5469 
5470 // dma_status0_r - DMA_STATUS0
5471 struct dma_status0_r
5472 {
5473 #ifndef __cplusplus
5474     union
5475     {
5476         struct
5477         {
5478             uint32_t cmd_idle : 1; // When this bit is high means that the CMD block is not busy in generating addresses
5479                                    // for a CMD job
5480             uint32_t ifm_idle : 1; // When this bit is high means that there are no ongoing IFM jobs
5481             uint32_t wgt_idle_c0 : 1; // When this bit is high means that the WGT block is not busy in generating
5482                                       // addresses for a WGT job
5483             uint32_t bas_idle_c0 : 1; // When this bit is high means that the BAS block is not busy in generating
5484                                       // addresses for a BAS job
5485             uint32_t m2m_idle : 1;    // When this bit is high means that there are no ongoing M2M jobs
5486             uint32_t ofm_idle : 1;    // When this bit is high means that there are no ongoing OFM jobs
5487             uint32_t halt_req : 1;    // CPM has requested to HALT AXI bus before soft reset
5488             uint32_t halt_ack : 1;    // DMA is in condition to halt the AXI bus since there are no pending transactions
5489             uint32_t pause_req : 1;   // CC has requested to pause the AXI
5490             uint32_t pause_ack : 1; // DMA is in condition to pause the AXI bus since there are no pending transactions
5491             uint32_t ib0_ai_valid_c0 : 1;       // Data for AI to be read in IFM input buffer 0 - Core 0
5492             uint32_t ib0_ai_ready_c0 : 1;       // Data consumed from AI in IFM input buffer 0 - Core 0
5493             uint32_t ib1_ai_valid_c0 : 1;       // Data for AI to be read in IFM input buffer 1 - Core 0
5494             uint32_t ib1_ai_ready_c0 : 1;       // Data consumed from AI in IFM input buffer 1 - Core 0
5495             uint32_t ib0_ao_valid_c0 : 1;       // Data for AO to be read in IFM input buffer 0 - Core 0
5496             uint32_t ib0_ao_ready_c0 : 1;       // Data consumed from AO in IFM input buffer 0 - Core 0
5497             uint32_t ib1_ao_valid_c0 : 1;       // Data for AO to be read in IFM input buffer 0 - Core 0
5498             uint32_t ib1_ao_ready_c0 : 1;       // Data consumed from AO in IFM input buffer 1 - Core 0
5499             uint32_t ob0_valid_c0 : 1;          // Data for DMA ready to be consumed in OFM output buffer 0 -  Core 0
5500             uint32_t ob0_ready_c0 : 1;          // Data consumed from DMA in OFM output buffer 0 - Core 0
5501             uint32_t ob1_valid_c0 : 1;          // Data for DMA ready to be consumed in OFM output buffer 1 -  Core 0
5502             uint32_t ob1_ready_c0 : 1;          // Data consumed from DMA in OFM output buffer 1 - Core 0
5503             uint32_t cmd_valid : 1;             // New command word for CC to be consumed
5504             uint32_t cmd_ready : 1;             // command word consumed by CC
5505             uint32_t wd_bitstream_valid_c0 : 1; // New weight word for WD to be consumed - Core 0
5506             uint32_t wd_bitstream_ready_c0 : 1; // Weight word consumed by WD - Core 0
5507             uint32_t bs_bitstream_valid_c0 : 1; // New BaS word for AO to be consumed - Core 0
5508             uint32_t bs_bitstream_ready_c0 : 1; // BaS word consumed by AO - Core 0
5509             uint32_t axi0_ar_stalled : 1; // Read transfer request stalled on arready low AXI0 (due to memory system)
5510             uint32_t axi0_rd_limit_stall : 1; // Read stalled due to one AXI0 limit counter being reached
5511             uint32_t axi0_aw_stalled : 1; // Write transfer request stalled on awready low AXI0 (due to memory system)
5512             uint32_t axi0_w_stalled : 1;  // Write transfer stalled on awready low AXI0 (due to memory system)
5513         };
5514         uint32_t word;
5515     };
5516 #else
5517   private:
5518     uint32_t word0;
5519 
5520   public:
5521     CONSTEXPR dma_status0_r() : word0(0) {}
5522     CONSTEXPR dma_status0_r(uint32_t init) : word0(init) {}
5523     CONSTEXPR void operator=(uint32_t value)
5524     {
5525         word0 = value;
5526     }
5527     void operator=(uint32_t value) volatile
5528     {
5529         word0 = value;
5530     }
5531     CONSTEXPR operator uint32_t()
5532     {
5533         return word0;
5534     }
5535     operator uint32_t() volatile
5536     {
5537         return word0;
5538     }
5539     dma_status0_r copy() volatile
5540     {
5541         return *this;
5542     }
5543     CONSTEXPR uint32_t get_cmd_idle() const
5544     {
5545         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
5546         return value;
5547     }
5548     uint32_t get_cmd_idle() const volatile
5549     {
5550         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
5551         return value;
5552     }
5553     CONSTEXPR dma_status0_r &set_cmd_idle(uint32_t value)
5554     {
5555         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
5556         return *this;
5557     }
5558     volatile dma_status0_r &set_cmd_idle(uint32_t value) volatile
5559     {
5560         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
5561         return *this;
5562     }
5563     CONSTEXPR uint32_t get_ifm_idle() const
5564     {
5565         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
5566         return value;
5567     }
5568     uint32_t get_ifm_idle() const volatile
5569     {
5570         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
5571         return value;
5572     }
5573     CONSTEXPR dma_status0_r &set_ifm_idle(uint32_t value)
5574     {
5575         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
5576         return *this;
5577     }
5578     volatile dma_status0_r &set_ifm_idle(uint32_t value) volatile
5579     {
5580         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
5581         return *this;
5582     }
5583     CONSTEXPR uint32_t get_wgt_idle_c0() const
5584     {
5585         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
5586         return value;
5587     }
5588     uint32_t get_wgt_idle_c0() const volatile
5589     {
5590         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
5591         return value;
5592     }
5593     CONSTEXPR dma_status0_r &set_wgt_idle_c0(uint32_t value)
5594     {
5595         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
5596         return *this;
5597     }
5598     volatile dma_status0_r &set_wgt_idle_c0(uint32_t value) volatile
5599     {
5600         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
5601         return *this;
5602     }
5603     CONSTEXPR uint32_t get_bas_idle_c0() const
5604     {
5605         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
5606         return value;
5607     }
5608     uint32_t get_bas_idle_c0() const volatile
5609     {
5610         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
5611         return value;
5612     }
5613     CONSTEXPR dma_status0_r &set_bas_idle_c0(uint32_t value)
5614     {
5615         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
5616         return *this;
5617     }
5618     volatile dma_status0_r &set_bas_idle_c0(uint32_t value) volatile
5619     {
5620         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
5621         return *this;
5622     }
5623     CONSTEXPR uint32_t get_m2m_idle() const
5624     {
5625         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
5626         return value;
5627     }
5628     uint32_t get_m2m_idle() const volatile
5629     {
5630         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
5631         return value;
5632     }
5633     CONSTEXPR dma_status0_r &set_m2m_idle(uint32_t value)
5634     {
5635         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5636         return *this;
5637     }
5638     volatile dma_status0_r &set_m2m_idle(uint32_t value) volatile
5639     {
5640         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5641         return *this;
5642     }
5643     CONSTEXPR uint32_t get_ofm_idle() const
5644     {
5645         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5646         return value;
5647     }
5648     uint32_t get_ofm_idle() const volatile
5649     {
5650         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5651         return value;
5652     }
5653     CONSTEXPR dma_status0_r &set_ofm_idle(uint32_t value)
5654     {
5655         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5656         return *this;
5657     }
5658     volatile dma_status0_r &set_ofm_idle(uint32_t value) volatile
5659     {
5660         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5661         return *this;
5662     }
5663     CONSTEXPR uint32_t get_halt_req() const
5664     {
5665         uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5666         return value;
5667     }
5668     uint32_t get_halt_req() const volatile
5669     {
5670         uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5671         return value;
5672     }
5673     CONSTEXPR dma_status0_r &set_halt_req(uint32_t value)
5674     {
5675         word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5676         return *this;
5677     }
5678     volatile dma_status0_r &set_halt_req(uint32_t value) volatile
5679     {
5680         word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5681         return *this;
5682     }
5683     CONSTEXPR uint32_t get_halt_ack() const
5684     {
5685         uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5686         return value;
5687     }
5688     uint32_t get_halt_ack() const volatile
5689     {
5690         uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5691         return value;
5692     }
5693     CONSTEXPR dma_status0_r &set_halt_ack(uint32_t value)
5694     {
5695         word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5696         return *this;
5697     }
5698     volatile dma_status0_r &set_halt_ack(uint32_t value) volatile
5699     {
5700         word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5701         return *this;
5702     }
5703     CONSTEXPR uint32_t get_pause_req() const
5704     {
5705         uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
5706         return value;
5707     }
5708     uint32_t get_pause_req() const volatile
5709     {
5710         uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
5711         return value;
5712     }
5713     CONSTEXPR dma_status0_r &set_pause_req(uint32_t value)
5714     {
5715         word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
5716         return *this;
5717     }
5718     volatile dma_status0_r &set_pause_req(uint32_t value) volatile
5719     {
5720         word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
5721         return *this;
5722     }
5723     CONSTEXPR uint32_t get_pause_ack() const
5724     {
5725         uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
5726         return value;
5727     }
5728     uint32_t get_pause_ack() const volatile
5729     {
5730         uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
5731         return value;
5732     }
5733     CONSTEXPR dma_status0_r &set_pause_ack(uint32_t value)
5734     {
5735         word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
5736         return *this;
5737     }
5738     volatile dma_status0_r &set_pause_ack(uint32_t value) volatile
5739     {
5740         word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
5741         return *this;
5742     }
5743     CONSTEXPR uint32_t get_ib0_ai_valid_c0() const
5744     {
5745         uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
5746         return value;
5747     }
5748     uint32_t get_ib0_ai_valid_c0() const volatile
5749     {
5750         uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
5751         return value;
5752     }
5753     CONSTEXPR dma_status0_r &set_ib0_ai_valid_c0(uint32_t value)
5754     {
5755         word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
5756         return *this;
5757     }
5758     volatile dma_status0_r &set_ib0_ai_valid_c0(uint32_t value) volatile
5759     {
5760         word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
5761         return *this;
5762     }
5763     CONSTEXPR uint32_t get_ib0_ai_ready_c0() const
5764     {
5765         uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
5766         return value;
5767     }
5768     uint32_t get_ib0_ai_ready_c0() const volatile
5769     {
5770         uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
5771         return value;
5772     }
5773     CONSTEXPR dma_status0_r &set_ib0_ai_ready_c0(uint32_t value)
5774     {
5775         word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
5776         return *this;
5777     }
5778     volatile dma_status0_r &set_ib0_ai_ready_c0(uint32_t value) volatile
5779     {
5780         word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
5781         return *this;
5782     }
5783     CONSTEXPR uint32_t get_ib1_ai_valid_c0() const
5784     {
5785         uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
5786         return value;
5787     }
5788     uint32_t get_ib1_ai_valid_c0() const volatile
5789     {
5790         uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
5791         return value;
5792     }
5793     CONSTEXPR dma_status0_r &set_ib1_ai_valid_c0(uint32_t value)
5794     {
5795         word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
5796         return *this;
5797     }
5798     volatile dma_status0_r &set_ib1_ai_valid_c0(uint32_t value) volatile
5799     {
5800         word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
5801         return *this;
5802     }
5803     CONSTEXPR uint32_t get_ib1_ai_ready_c0() const
5804     {
5805         uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
5806         return value;
5807     }
5808     uint32_t get_ib1_ai_ready_c0() const volatile
5809     {
5810         uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
5811         return value;
5812     }
5813     CONSTEXPR dma_status0_r &set_ib1_ai_ready_c0(uint32_t value)
5814     {
5815         word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
5816         return *this;
5817     }
5818     volatile dma_status0_r &set_ib1_ai_ready_c0(uint32_t value) volatile
5819     {
5820         word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
5821         return *this;
5822     }
5823     CONSTEXPR uint32_t get_ib0_ao_valid_c0() const
5824     {
5825         uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
5826         return value;
5827     }
5828     uint32_t get_ib0_ao_valid_c0() const volatile
5829     {
5830         uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
5831         return value;
5832     }
5833     CONSTEXPR dma_status0_r &set_ib0_ao_valid_c0(uint32_t value)
5834     {
5835         word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
5836         return *this;
5837     }
5838     volatile dma_status0_r &set_ib0_ao_valid_c0(uint32_t value) volatile
5839     {
5840         word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
5841         return *this;
5842     }
5843     CONSTEXPR uint32_t get_ib0_ao_ready_c0() const
5844     {
5845         uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
5846         return value;
5847     }
5848     uint32_t get_ib0_ao_ready_c0() const volatile
5849     {
5850         uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
5851         return value;
5852     }
5853     CONSTEXPR dma_status0_r &set_ib0_ao_ready_c0(uint32_t value)
5854     {
5855         word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
5856         return *this;
5857     }
5858     volatile dma_status0_r &set_ib0_ao_ready_c0(uint32_t value) volatile
5859     {
5860         word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
5861         return *this;
5862     }
5863     CONSTEXPR uint32_t get_ib1_ao_valid_c0() const
5864     {
5865         uint32_t value = ((1U << 1) - 1) & (word0 >> 16);
5866         return value;
5867     }
5868     uint32_t get_ib1_ao_valid_c0() const volatile
5869     {
5870         uint32_t value = ((1U << 1) - 1) & (word0 >> 16);
5871         return value;
5872     }
5873     CONSTEXPR dma_status0_r &set_ib1_ao_valid_c0(uint32_t value)
5874     {
5875         word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16);
5876         return *this;
5877     }
5878     volatile dma_status0_r &set_ib1_ao_valid_c0(uint32_t value) volatile
5879     {
5880         word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16);
5881         return *this;
5882     }
5883     CONSTEXPR uint32_t get_ib1_ao_ready_c0() const
5884     {
5885         uint32_t value = ((1U << 1) - 1) & (word0 >> 17);
5886         return value;
5887     }
5888     uint32_t get_ib1_ao_ready_c0() const volatile
5889     {
5890         uint32_t value = ((1U << 1) - 1) & (word0 >> 17);
5891         return value;
5892     }
5893     CONSTEXPR dma_status0_r &set_ib1_ao_ready_c0(uint32_t value)
5894     {
5895         word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17);
5896         return *this;
5897     }
5898     volatile dma_status0_r &set_ib1_ao_ready_c0(uint32_t value) volatile
5899     {
5900         word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17);
5901         return *this;
5902     }
5903     CONSTEXPR uint32_t get_ob0_valid_c0() const
5904     {
5905         uint32_t value = ((1U << 1) - 1) & (word0 >> 18);
5906         return value;
5907     }
5908     uint32_t get_ob0_valid_c0() const volatile
5909     {
5910         uint32_t value = ((1U << 1) - 1) & (word0 >> 18);
5911         return value;
5912     }
5913     CONSTEXPR dma_status0_r &set_ob0_valid_c0(uint32_t value)
5914     {
5915         word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18);
5916         return *this;
5917     }
5918     volatile dma_status0_r &set_ob0_valid_c0(uint32_t value) volatile
5919     {
5920         word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18);
5921         return *this;
5922     }
5923     CONSTEXPR uint32_t get_ob0_ready_c0() const
5924     {
5925         uint32_t value = ((1U << 1) - 1) & (word0 >> 19);
5926         return value;
5927     }
5928     uint32_t get_ob0_ready_c0() const volatile
5929     {
5930         uint32_t value = ((1U << 1) - 1) & (word0 >> 19);
5931         return value;
5932     }
5933     CONSTEXPR dma_status0_r &set_ob0_ready_c0(uint32_t value)
5934     {
5935         word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19);
5936         return *this;
5937     }
5938     volatile dma_status0_r &set_ob0_ready_c0(uint32_t value) volatile
5939     {
5940         word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19);
5941         return *this;
5942     }
5943     CONSTEXPR uint32_t get_ob1_valid_c0() const
5944     {
5945         uint32_t value = ((1U << 1) - 1) & (word0 >> 20);
5946         return value;
5947     }
5948     uint32_t get_ob1_valid_c0() const volatile
5949     {
5950         uint32_t value = ((1U << 1) - 1) & (word0 >> 20);
5951         return value;
5952     }
5953     CONSTEXPR dma_status0_r &set_ob1_valid_c0(uint32_t value)
5954     {
5955         word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20);
5956         return *this;
5957     }
5958     volatile dma_status0_r &set_ob1_valid_c0(uint32_t value) volatile
5959     {
5960         word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20);
5961         return *this;
5962     }
5963     CONSTEXPR uint32_t get_ob1_ready_c0() const
5964     {
5965         uint32_t value = ((1U << 1) - 1) & (word0 >> 21);
5966         return value;
5967     }
5968     uint32_t get_ob1_ready_c0() const volatile
5969     {
5970         uint32_t value = ((1U << 1) - 1) & (word0 >> 21);
5971         return value;
5972     }
5973     CONSTEXPR dma_status0_r &set_ob1_ready_c0(uint32_t value)
5974     {
5975         word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21);
5976         return *this;
5977     }
5978     volatile dma_status0_r &set_ob1_ready_c0(uint32_t value) volatile
5979     {
5980         word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21);
5981         return *this;
5982     }
5983     CONSTEXPR uint32_t get_cmd_valid() const
5984     {
5985         uint32_t value = ((1U << 1) - 1) & (word0 >> 22);
5986         return value;
5987     }
5988     uint32_t get_cmd_valid() const volatile
5989     {
5990         uint32_t value = ((1U << 1) - 1) & (word0 >> 22);
5991         return value;
5992     }
5993     CONSTEXPR dma_status0_r &set_cmd_valid(uint32_t value)
5994     {
5995         word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22);
5996         return *this;
5997     }
5998     volatile dma_status0_r &set_cmd_valid(uint32_t value) volatile
5999     {
6000         word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22);
6001         return *this;
6002     }
6003     CONSTEXPR uint32_t get_cmd_ready() const
6004     {
6005         uint32_t value = ((1U << 1) - 1) & (word0 >> 23);
6006         return value;
6007     }
6008     uint32_t get_cmd_ready() const volatile
6009     {
6010         uint32_t value = ((1U << 1) - 1) & (word0 >> 23);
6011         return value;
6012     }
6013     CONSTEXPR dma_status0_r &set_cmd_ready(uint32_t value)
6014     {
6015         word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23);
6016         return *this;
6017     }
6018     volatile dma_status0_r &set_cmd_ready(uint32_t value) volatile
6019     {
6020         word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23);
6021         return *this;
6022     }
6023     CONSTEXPR uint32_t get_wd_bitstream_valid_c0() const
6024     {
6025         uint32_t value = ((1U << 1) - 1) & (word0 >> 24);
6026         return value;
6027     }
6028     uint32_t get_wd_bitstream_valid_c0() const volatile
6029     {
6030         uint32_t value = ((1U << 1) - 1) & (word0 >> 24);
6031         return value;
6032     }
6033     CONSTEXPR dma_status0_r &set_wd_bitstream_valid_c0(uint32_t value)
6034     {
6035         word0 = (((~((1U << 1) - 1)) << 24) & word0) | ((((1U << 1) - 1) & value) << 24);
6036         return *this;
6037     }
6038     volatile dma_status0_r &set_wd_bitstream_valid_c0(uint32_t value) volatile
6039     {
6040         word0 = (((~((1U << 1) - 1)) << 24) & word0) | ((((1U << 1) - 1) & value) << 24);
6041         return *this;
6042     }
6043     CONSTEXPR uint32_t get_wd_bitstream_ready_c0() const
6044     {
6045         uint32_t value = ((1U << 1) - 1) & (word0 >> 25);
6046         return value;
6047     }
6048     uint32_t get_wd_bitstream_ready_c0() const volatile
6049     {
6050         uint32_t value = ((1U << 1) - 1) & (word0 >> 25);
6051         return value;
6052     }
6053     CONSTEXPR dma_status0_r &set_wd_bitstream_ready_c0(uint32_t value)
6054     {
6055         word0 = (((~((1U << 1) - 1)) << 25) & word0) | ((((1U << 1) - 1) & value) << 25);
6056         return *this;
6057     }
6058     volatile dma_status0_r &set_wd_bitstream_ready_c0(uint32_t value) volatile
6059     {
6060         word0 = (((~((1U << 1) - 1)) << 25) & word0) | ((((1U << 1) - 1) & value) << 25);
6061         return *this;
6062     }
6063     CONSTEXPR uint32_t get_bs_bitstream_valid_c0() const
6064     {
6065         uint32_t value = ((1U << 1) - 1) & (word0 >> 26);
6066         return value;
6067     }
6068     uint32_t get_bs_bitstream_valid_c0() const volatile
6069     {
6070         uint32_t value = ((1U << 1) - 1) & (word0 >> 26);
6071         return value;
6072     }
6073     CONSTEXPR dma_status0_r &set_bs_bitstream_valid_c0(uint32_t value)
6074     {
6075         word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & value) << 26);
6076         return *this;
6077     }
6078     volatile dma_status0_r &set_bs_bitstream_valid_c0(uint32_t value) volatile
6079     {
6080         word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & value) << 26);
6081         return *this;
6082     }
6083     CONSTEXPR uint32_t get_bs_bitstream_ready_c0() const
6084     {
6085         uint32_t value = ((1U << 1) - 1) & (word0 >> 27);
6086         return value;
6087     }
6088     uint32_t get_bs_bitstream_ready_c0() const volatile
6089     {
6090         uint32_t value = ((1U << 1) - 1) & (word0 >> 27);
6091         return value;
6092     }
6093     CONSTEXPR dma_status0_r &set_bs_bitstream_ready_c0(uint32_t value)
6094     {
6095         word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & value) << 27);
6096         return *this;
6097     }
6098     volatile dma_status0_r &set_bs_bitstream_ready_c0(uint32_t value) volatile
6099     {
6100         word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & value) << 27);
6101         return *this;
6102     }
6103     CONSTEXPR uint32_t get_axi0_ar_stalled() const
6104     {
6105         uint32_t value = ((1U << 1) - 1) & (word0 >> 28);
6106         return value;
6107     }
6108     uint32_t get_axi0_ar_stalled() const volatile
6109     {
6110         uint32_t value = ((1U << 1) - 1) & (word0 >> 28);
6111         return value;
6112     }
6113     CONSTEXPR dma_status0_r &set_axi0_ar_stalled(uint32_t value)
6114     {
6115         word0 = (((~((1U << 1) - 1)) << 28) & word0) | ((((1U << 1) - 1) & value) << 28);
6116         return *this;
6117     }
6118     volatile dma_status0_r &set_axi0_ar_stalled(uint32_t value) volatile
6119     {
6120         word0 = (((~((1U << 1) - 1)) << 28) & word0) | ((((1U << 1) - 1) & value) << 28);
6121         return *this;
6122     }
6123     CONSTEXPR uint32_t get_axi0_rd_limit_stall() const
6124     {
6125         uint32_t value = ((1U << 1) - 1) & (word0 >> 29);
6126         return value;
6127     }
6128     uint32_t get_axi0_rd_limit_stall() const volatile
6129     {
6130         uint32_t value = ((1U << 1) - 1) & (word0 >> 29);
6131         return value;
6132     }
6133     CONSTEXPR dma_status0_r &set_axi0_rd_limit_stall(uint32_t value)
6134     {
6135         word0 = (((~((1U << 1) - 1)) << 29) & word0) | ((((1U << 1) - 1) & value) << 29);
6136         return *this;
6137     }
6138     volatile dma_status0_r &set_axi0_rd_limit_stall(uint32_t value) volatile
6139     {
6140         word0 = (((~((1U << 1) - 1)) << 29) & word0) | ((((1U << 1) - 1) & value) << 29);
6141         return *this;
6142     }
6143     CONSTEXPR uint32_t get_axi0_aw_stalled() const
6144     {
6145         uint32_t value = ((1U << 1) - 1) & (word0 >> 30);
6146         return value;
6147     }
6148     uint32_t get_axi0_aw_stalled() const volatile
6149     {
6150         uint32_t value = ((1U << 1) - 1) & (word0 >> 30);
6151         return value;
6152     }
6153     CONSTEXPR dma_status0_r &set_axi0_aw_stalled(uint32_t value)
6154     {
6155         word0 = (((~((1U << 1) - 1)) << 30) & word0) | ((((1U << 1) - 1) & value) << 30);
6156         return *this;
6157     }
6158     volatile dma_status0_r &set_axi0_aw_stalled(uint32_t value) volatile
6159     {
6160         word0 = (((~((1U << 1) - 1)) << 30) & word0) | ((((1U << 1) - 1) & value) << 30);
6161         return *this;
6162     }
6163     CONSTEXPR uint32_t get_axi0_w_stalled() const
6164     {
6165         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
6166         return value;
6167     }
6168     uint32_t get_axi0_w_stalled() const volatile
6169     {
6170         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
6171         return value;
6172     }
6173     CONSTEXPR dma_status0_r &set_axi0_w_stalled(uint32_t value)
6174     {
6175         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
6176         return *this;
6177     }
6178     volatile dma_status0_r &set_axi0_w_stalled(uint32_t value) volatile
6179     {
6180         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
6181         return *this;
6182     }
6183 #endif
6184 };
6185 
6186 // dma_status1_r - DMA_STATUS1
6187 struct dma_status1_r
6188 {
6189 #ifndef __cplusplus
6190     union
6191     {
6192         struct
6193         {
6194             uint32_t axi0_wr_limit_stall : 1; // Write stalled due to one AXI0 limit counter being reached
6195             uint32_t axi1_ar_stalled : 1; // Read transfer request stalled on arready low AXI1 (due to memory system)
6196             uint32_t axi1_rd_limit_stall : 1; // Read stalled due to one AXI1 limit counter being reached
6197             uint32_t axi1_wr_stalled : 1; // Write transfer request stalled on awready low AXI1 (due to memory system)
6198             uint32_t axi1_w_stalled : 1;  // Write transfer stalled on wready low AXI1 (due to memory system)
6199             uint32_t axi1_wr_limit_stall : 1; // Write stalled due to one AXI1 limit counter being reached
6200             uint32_t wgt_idle_c1 : 1;     // When this bit is high means that the WGT block is not busy in generating
6201                                           // addresses for a WGT job
6202             uint32_t bas_idle_c1 : 1;     // When this bit is high means that the BAS block is not busy in generating
6203                                           // addresses for a BAS job
6204             uint32_t ib0_ai_valid_c1 : 1; // Data for AI to be read in IFM input buffer 0 - Core 1
6205             uint32_t ib0_ai_ready_c1 : 1; // Data consumed from AI in IFM input buffer 0 - Core 1
6206             uint32_t ib1_ai_valid_c1 : 1; // Data for AI to be read in IFM input buffer 1 - Core 1
6207             uint32_t ib1_ai_ready_c1 : 1; // Data consumed from AI in IFM input buffer 1 - Core 1
6208             uint32_t ib0_ao_valid_c1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1
6209             uint32_t ib0_ao_ready_c1 : 1; // Data consumed from AO in IFM input buffer 0 - Core 1
6210             uint32_t ib1_ao_valid_c1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1
6211             uint32_t ib1_ao_ready_c1 : 1; // Data consumed from AO in IFM input buffer 1 - Core 1
6212             uint32_t ob0_valid_c1 : 1;    // Data for DMA ready to be consumed in OFM output buffer 0 - Core 1
6213             uint32_t ob0_ready_c1 : 1;    // Data consumed from DMA in OFM output buffer 0 - Core 1
6214             uint32_t ob1_valid_c1 : 1;    // Data for DMA ready to be consumed in OFM output buffer 1 - Core 1
6215             uint32_t ob1_ready_c1 : 1;    // Data consumed from DMA in OFM output buffer 1 - Core 1
6216             uint32_t wd_bitstream_valid_c1 : 1; // New weight word for WD to be consumed - Core 1
6217             uint32_t wd_bitstream_ready_c1 : 1; // Weight word consumed by WD - Core 1
6218             uint32_t bs_bitstream_valid_c1 : 1; // New BaS word for AO to be consumed - Core 1
6219             uint32_t bs_bitstream_ready_c1 : 1; // BaS word consumed by AO - Core 1
6220             uint32_t reserved0 : 8;
6221         };
6222         uint32_t word;
6223     };
6224 #else
6225   private:
6226     uint32_t word0;
6227 
6228   public:
6229     CONSTEXPR dma_status1_r() : word0(0) {}
6230     CONSTEXPR dma_status1_r(uint32_t init) : word0(init) {}
6231     CONSTEXPR void operator=(uint32_t value)
6232     {
6233         word0 = value;
6234     }
6235     void operator=(uint32_t value) volatile
6236     {
6237         word0 = value;
6238     }
6239     CONSTEXPR operator uint32_t()
6240     {
6241         return word0;
6242     }
6243     operator uint32_t() volatile
6244     {
6245         return word0;
6246     }
6247     dma_status1_r copy() volatile
6248     {
6249         return *this;
6250     }
6251     CONSTEXPR uint32_t get_axi0_wr_limit_stall() const
6252     {
6253         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
6254         return value;
6255     }
6256     uint32_t get_axi0_wr_limit_stall() const volatile
6257     {
6258         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
6259         return value;
6260     }
6261     CONSTEXPR dma_status1_r &set_axi0_wr_limit_stall(uint32_t value)
6262     {
6263         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
6264         return *this;
6265     }
6266     volatile dma_status1_r &set_axi0_wr_limit_stall(uint32_t value) volatile
6267     {
6268         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
6269         return *this;
6270     }
6271     CONSTEXPR uint32_t get_axi1_ar_stalled() const
6272     {
6273         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
6274         return value;
6275     }
6276     uint32_t get_axi1_ar_stalled() const volatile
6277     {
6278         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
6279         return value;
6280     }
6281     CONSTEXPR dma_status1_r &set_axi1_ar_stalled(uint32_t value)
6282     {
6283         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
6284         return *this;
6285     }
6286     volatile dma_status1_r &set_axi1_ar_stalled(uint32_t value) volatile
6287     {
6288         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
6289         return *this;
6290     }
6291     CONSTEXPR uint32_t get_axi1_rd_limit_stall() const
6292     {
6293         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
6294         return value;
6295     }
6296     uint32_t get_axi1_rd_limit_stall() const volatile
6297     {
6298         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
6299         return value;
6300     }
6301     CONSTEXPR dma_status1_r &set_axi1_rd_limit_stall(uint32_t value)
6302     {
6303         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
6304         return *this;
6305     }
6306     volatile dma_status1_r &set_axi1_rd_limit_stall(uint32_t value) volatile
6307     {
6308         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
6309         return *this;
6310     }
6311     CONSTEXPR uint32_t get_axi1_wr_stalled() const
6312     {
6313         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
6314         return value;
6315     }
6316     uint32_t get_axi1_wr_stalled() const volatile
6317     {
6318         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
6319         return value;
6320     }
6321     CONSTEXPR dma_status1_r &set_axi1_wr_stalled(uint32_t value)
6322     {
6323         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
6324         return *this;
6325     }
6326     volatile dma_status1_r &set_axi1_wr_stalled(uint32_t value) volatile
6327     {
6328         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
6329         return *this;
6330     }
6331     CONSTEXPR uint32_t get_axi1_w_stalled() const
6332     {
6333         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
6334         return value;
6335     }
6336     uint32_t get_axi1_w_stalled() const volatile
6337     {
6338         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
6339         return value;
6340     }
6341     CONSTEXPR dma_status1_r &set_axi1_w_stalled(uint32_t value)
6342     {
6343         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
6344         return *this;
6345     }
6346     volatile dma_status1_r &set_axi1_w_stalled(uint32_t value) volatile
6347     {
6348         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
6349         return *this;
6350     }
6351     CONSTEXPR uint32_t get_axi1_wr_limit_stall() const
6352     {
6353         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
6354         return value;
6355     }
6356     uint32_t get_axi1_wr_limit_stall() const volatile
6357     {
6358         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
6359         return value;
6360     }
6361     CONSTEXPR dma_status1_r &set_axi1_wr_limit_stall(uint32_t value)
6362     {
6363         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
6364         return *this;
6365     }
6366     volatile dma_status1_r &set_axi1_wr_limit_stall(uint32_t value) volatile
6367     {
6368         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
6369         return *this;
6370     }
6371     CONSTEXPR uint32_t get_wgt_idle_c1() const
6372     {
6373         uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
6374         return value;
6375     }
6376     uint32_t get_wgt_idle_c1() const volatile
6377     {
6378         uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
6379         return value;
6380     }
6381     CONSTEXPR dma_status1_r &set_wgt_idle_c1(uint32_t value)
6382     {
6383         word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
6384         return *this;
6385     }
6386     volatile dma_status1_r &set_wgt_idle_c1(uint32_t value) volatile
6387     {
6388         word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
6389         return *this;
6390     }
6391     CONSTEXPR uint32_t get_bas_idle_c1() const
6392     {
6393         uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
6394         return value;
6395     }
6396     uint32_t get_bas_idle_c1() const volatile
6397     {
6398         uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
6399         return value;
6400     }
6401     CONSTEXPR dma_status1_r &set_bas_idle_c1(uint32_t value)
6402     {
6403         word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
6404         return *this;
6405     }
6406     volatile dma_status1_r &set_bas_idle_c1(uint32_t value) volatile
6407     {
6408         word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
6409         return *this;
6410     }
6411     CONSTEXPR uint32_t get_ib0_ai_valid_c1() const
6412     {
6413         uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
6414         return value;
6415     }
6416     uint32_t get_ib0_ai_valid_c1() const volatile
6417     {
6418         uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
6419         return value;
6420     }
6421     CONSTEXPR dma_status1_r &set_ib0_ai_valid_c1(uint32_t value)
6422     {
6423         word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
6424         return *this;
6425     }
6426     volatile dma_status1_r &set_ib0_ai_valid_c1(uint32_t value) volatile
6427     {
6428         word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
6429         return *this;
6430     }
6431     CONSTEXPR uint32_t get_ib0_ai_ready_c1() const
6432     {
6433         uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
6434         return value;
6435     }
6436     uint32_t get_ib0_ai_ready_c1() const volatile
6437     {
6438         uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
6439         return value;
6440     }
6441     CONSTEXPR dma_status1_r &set_ib0_ai_ready_c1(uint32_t value)
6442     {
6443         word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
6444         return *this;
6445     }
6446     volatile dma_status1_r &set_ib0_ai_ready_c1(uint32_t value) volatile
6447     {
6448         word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
6449         return *this;
6450     }
6451     CONSTEXPR uint32_t get_ib1_ai_valid_c1() const
6452     {
6453         uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
6454         return value;
6455     }
6456     uint32_t get_ib1_ai_valid_c1() const volatile
6457     {
6458         uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
6459         return value;
6460     }
6461     CONSTEXPR dma_status1_r &set_ib1_ai_valid_c1(uint32_t value)
6462     {
6463         word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
6464         return *this;
6465     }
6466     volatile dma_status1_r &set_ib1_ai_valid_c1(uint32_t value) volatile
6467     {
6468         word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
6469         return *this;
6470     }
6471     CONSTEXPR uint32_t get_ib1_ai_ready_c1() const
6472     {
6473         uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
6474         return value;
6475     }
6476     uint32_t get_ib1_ai_ready_c1() const volatile
6477     {
6478         uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
6479         return value;
6480     }
6481     CONSTEXPR dma_status1_r &set_ib1_ai_ready_c1(uint32_t value)
6482     {
6483         word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
6484         return *this;
6485     }
6486     volatile dma_status1_r &set_ib1_ai_ready_c1(uint32_t value) volatile
6487     {
6488         word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
6489         return *this;
6490     }
6491     CONSTEXPR uint32_t get_ib0_ao_valid_c1() const
6492     {
6493         uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
6494         return value;
6495     }
6496     uint32_t get_ib0_ao_valid_c1() const volatile
6497     {
6498         uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
6499         return value;
6500     }
6501     CONSTEXPR dma_status1_r &set_ib0_ao_valid_c1(uint32_t value)
6502     {
6503         word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
6504         return *this;
6505     }
6506     volatile dma_status1_r &set_ib0_ao_valid_c1(uint32_t value) volatile
6507     {
6508         word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
6509         return *this;
6510     }
6511     CONSTEXPR uint32_t get_ib0_ao_ready_c1() const
6512     {
6513         uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
6514         return value;
6515     }
6516     uint32_t get_ib0_ao_ready_c1() const volatile
6517     {
6518         uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
6519         return value;
6520     }
6521     CONSTEXPR dma_status1_r &set_ib0_ao_ready_c1(uint32_t value)
6522     {
6523         word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
6524         return *this;
6525     }
6526     volatile dma_status1_r &set_ib0_ao_ready_c1(uint32_t value) volatile
6527     {
6528         word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
6529         return *this;
6530     }
6531     CONSTEXPR uint32_t get_ib1_ao_valid_c1() const
6532     {
6533         uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
6534         return value;
6535     }
6536     uint32_t get_ib1_ao_valid_c1() const volatile
6537     {
6538         uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
6539         return value;
6540     }
6541     CONSTEXPR dma_status1_r &set_ib1_ao_valid_c1(uint32_t value)
6542     {
6543         word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
6544         return *this;
6545     }
6546     volatile dma_status1_r &set_ib1_ao_valid_c1(uint32_t value) volatile
6547     {
6548         word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
6549         return *this;
6550     }
6551     CONSTEXPR uint32_t get_ib1_ao_ready_c1() const
6552     {
6553         uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
6554         return value;
6555     }
6556     uint32_t get_ib1_ao_ready_c1() const volatile
6557     {
6558         uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
6559         return value;
6560     }
6561     CONSTEXPR dma_status1_r &set_ib1_ao_ready_c1(uint32_t value)
6562     {
6563         word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
6564         return *this;
6565     }
6566     volatile dma_status1_r &set_ib1_ao_ready_c1(uint32_t value) volatile
6567     {
6568         word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
6569         return *this;
6570     }
6571     CONSTEXPR uint32_t get_ob0_valid_c1() const
6572     {
6573         uint32_t value = ((1U << 1) - 1) & (word0 >> 16);
6574         return value;
6575     }
6576     uint32_t get_ob0_valid_c1() const volatile
6577     {
6578         uint32_t value = ((1U << 1) - 1) & (word0 >> 16);
6579         return value;
6580     }
6581     CONSTEXPR dma_status1_r &set_ob0_valid_c1(uint32_t value)
6582     {
6583         word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16);
6584         return *this;
6585     }
6586     volatile dma_status1_r &set_ob0_valid_c1(uint32_t value) volatile
6587     {
6588         word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16);
6589         return *this;
6590     }
6591     CONSTEXPR uint32_t get_ob0_ready_c1() const
6592     {
6593         uint32_t value = ((1U << 1) - 1) & (word0 >> 17);
6594         return value;
6595     }
6596     uint32_t get_ob0_ready_c1() const volatile
6597     {
6598         uint32_t value = ((1U << 1) - 1) & (word0 >> 17);
6599         return value;
6600     }
6601     CONSTEXPR dma_status1_r &set_ob0_ready_c1(uint32_t value)
6602     {
6603         word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17);
6604         return *this;
6605     }
6606     volatile dma_status1_r &set_ob0_ready_c1(uint32_t value) volatile
6607     {
6608         word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17);
6609         return *this;
6610     }
6611     CONSTEXPR uint32_t get_ob1_valid_c1() const
6612     {
6613         uint32_t value = ((1U << 1) - 1) & (word0 >> 18);
6614         return value;
6615     }
6616     uint32_t get_ob1_valid_c1() const volatile
6617     {
6618         uint32_t value = ((1U << 1) - 1) & (word0 >> 18);
6619         return value;
6620     }
6621     CONSTEXPR dma_status1_r &set_ob1_valid_c1(uint32_t value)
6622     {
6623         word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18);
6624         return *this;
6625     }
6626     volatile dma_status1_r &set_ob1_valid_c1(uint32_t value) volatile
6627     {
6628         word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18);
6629         return *this;
6630     }
6631     CONSTEXPR uint32_t get_ob1_ready_c1() const
6632     {
6633         uint32_t value = ((1U << 1) - 1) & (word0 >> 19);
6634         return value;
6635     }
6636     uint32_t get_ob1_ready_c1() const volatile
6637     {
6638         uint32_t value = ((1U << 1) - 1) & (word0 >> 19);
6639         return value;
6640     }
6641     CONSTEXPR dma_status1_r &set_ob1_ready_c1(uint32_t value)
6642     {
6643         word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19);
6644         return *this;
6645     }
6646     volatile dma_status1_r &set_ob1_ready_c1(uint32_t value) volatile
6647     {
6648         word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19);
6649         return *this;
6650     }
6651     CONSTEXPR uint32_t get_wd_bitstream_valid_c1() const
6652     {
6653         uint32_t value = ((1U << 1) - 1) & (word0 >> 20);
6654         return value;
6655     }
6656     uint32_t get_wd_bitstream_valid_c1() const volatile
6657     {
6658         uint32_t value = ((1U << 1) - 1) & (word0 >> 20);
6659         return value;
6660     }
6661     CONSTEXPR dma_status1_r &set_wd_bitstream_valid_c1(uint32_t value)
6662     {
6663         word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20);
6664         return *this;
6665     }
6666     volatile dma_status1_r &set_wd_bitstream_valid_c1(uint32_t value) volatile
6667     {
6668         word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20);
6669         return *this;
6670     }
6671     CONSTEXPR uint32_t get_wd_bitstream_ready_c1() const
6672     {
6673         uint32_t value = ((1U << 1) - 1) & (word0 >> 21);
6674         return value;
6675     }
6676     uint32_t get_wd_bitstream_ready_c1() const volatile
6677     {
6678         uint32_t value = ((1U << 1) - 1) & (word0 >> 21);
6679         return value;
6680     }
6681     CONSTEXPR dma_status1_r &set_wd_bitstream_ready_c1(uint32_t value)
6682     {
6683         word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21);
6684         return *this;
6685     }
6686     volatile dma_status1_r &set_wd_bitstream_ready_c1(uint32_t value) volatile
6687     {
6688         word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21);
6689         return *this;
6690     }
6691     CONSTEXPR uint32_t get_bs_bitstream_valid_c1() const
6692     {
6693         uint32_t value = ((1U << 1) - 1) & (word0 >> 22);
6694         return value;
6695     }
6696     uint32_t get_bs_bitstream_valid_c1() const volatile
6697     {
6698         uint32_t value = ((1U << 1) - 1) & (word0 >> 22);
6699         return value;
6700     }
6701     CONSTEXPR dma_status1_r &set_bs_bitstream_valid_c1(uint32_t value)
6702     {
6703         word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22);
6704         return *this;
6705     }
6706     volatile dma_status1_r &set_bs_bitstream_valid_c1(uint32_t value) volatile
6707     {
6708         word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22);
6709         return *this;
6710     }
6711     CONSTEXPR uint32_t get_bs_bitstream_ready_c1() const
6712     {
6713         uint32_t value = ((1U << 1) - 1) & (word0 >> 23);
6714         return value;
6715     }
6716     uint32_t get_bs_bitstream_ready_c1() const volatile
6717     {
6718         uint32_t value = ((1U << 1) - 1) & (word0 >> 23);
6719         return value;
6720     }
6721     CONSTEXPR dma_status1_r &set_bs_bitstream_ready_c1(uint32_t value)
6722     {
6723         word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23);
6724         return *this;
6725     }
6726     volatile dma_status1_r &set_bs_bitstream_ready_c1(uint32_t value) volatile
6727     {
6728         word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23);
6729         return *this;
6730     }
6731 #endif
6732 };
6733 
6734 // clkforce_r - Force clocks on for clock gating
6735 struct clkforce_r
6736 {
6737 #ifndef __cplusplus
6738     union
6739     {
6740         struct
6741         {
6742             uint32_t top_level_clk : 1; // set to 1 to force on TOP level clock
6743             uint32_t cc_clk : 1;        // set to 1 to force on CC clock
6744             uint32_t dma_clk : 1;       // set to 1 to force on DMA clock
6745             uint32_t mac_clk : 1;       // set to 1 to force on MAC clock
6746             uint32_t ao_clk : 1;        // set to 1 to force on AO clock
6747             uint32_t wd_clk : 1;        // set to 1 to force on WD clock
6748             uint32_t reserved0 : 26;
6749         };
6750         uint32_t word;
6751     };
6752 #else
6753   private:
6754     uint32_t word0;
6755 
6756   public:
6757     CONSTEXPR clkforce_r() : word0(0) {}
6758     CONSTEXPR clkforce_r(uint32_t init) : word0(init) {}
6759     CONSTEXPR void operator=(uint32_t value)
6760     {
6761         word0 = value;
6762     }
6763     void operator=(uint32_t value) volatile
6764     {
6765         word0 = value;
6766     }
6767     CONSTEXPR operator uint32_t()
6768     {
6769         return word0;
6770     }
6771     operator uint32_t() volatile
6772     {
6773         return word0;
6774     }
6775     clkforce_r copy() volatile
6776     {
6777         return *this;
6778     }
6779     CONSTEXPR uint32_t get_top_level_clk() const
6780     {
6781         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
6782         return value;
6783     }
6784     uint32_t get_top_level_clk() const volatile
6785     {
6786         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
6787         return value;
6788     }
6789     CONSTEXPR clkforce_r &set_top_level_clk(uint32_t value)
6790     {
6791         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
6792         return *this;
6793     }
6794     volatile clkforce_r &set_top_level_clk(uint32_t value) volatile
6795     {
6796         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
6797         return *this;
6798     }
6799     CONSTEXPR uint32_t get_cc_clk() const
6800     {
6801         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
6802         return value;
6803     }
6804     uint32_t get_cc_clk() const volatile
6805     {
6806         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
6807         return value;
6808     }
6809     CONSTEXPR clkforce_r &set_cc_clk(uint32_t value)
6810     {
6811         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
6812         return *this;
6813     }
6814     volatile clkforce_r &set_cc_clk(uint32_t value) volatile
6815     {
6816         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
6817         return *this;
6818     }
6819     CONSTEXPR uint32_t get_dma_clk() const
6820     {
6821         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
6822         return value;
6823     }
6824     uint32_t get_dma_clk() const volatile
6825     {
6826         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
6827         return value;
6828     }
6829     CONSTEXPR clkforce_r &set_dma_clk(uint32_t value)
6830     {
6831         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
6832         return *this;
6833     }
6834     volatile clkforce_r &set_dma_clk(uint32_t value) volatile
6835     {
6836         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
6837         return *this;
6838     }
6839     CONSTEXPR uint32_t get_mac_clk() const
6840     {
6841         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
6842         return value;
6843     }
6844     uint32_t get_mac_clk() const volatile
6845     {
6846         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
6847         return value;
6848     }
6849     CONSTEXPR clkforce_r &set_mac_clk(uint32_t value)
6850     {
6851         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
6852         return *this;
6853     }
6854     volatile clkforce_r &set_mac_clk(uint32_t value) volatile
6855     {
6856         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
6857         return *this;
6858     }
6859     CONSTEXPR uint32_t get_ao_clk() const
6860     {
6861         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
6862         return value;
6863     }
6864     uint32_t get_ao_clk() const volatile
6865     {
6866         uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
6867         return value;
6868     }
6869     CONSTEXPR clkforce_r &set_ao_clk(uint32_t value)
6870     {
6871         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
6872         return *this;
6873     }
6874     volatile clkforce_r &set_ao_clk(uint32_t value) volatile
6875     {
6876         word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
6877         return *this;
6878     }
6879     CONSTEXPR uint32_t get_wd_clk() const
6880     {
6881         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
6882         return value;
6883     }
6884     uint32_t get_wd_clk() const volatile
6885     {
6886         uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
6887         return value;
6888     }
6889     CONSTEXPR clkforce_r &set_wd_clk(uint32_t value)
6890     {
6891         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
6892         return *this;
6893     }
6894     volatile clkforce_r &set_wd_clk(uint32_t value) volatile
6895     {
6896         word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
6897         return *this;
6898     }
6899 #endif
6900 };
6901 
6902 // debug_address_r - Set debug address for register reads 0x400-0x7FF. The address must be 1KB aligned
6903 struct debug_address_r
6904 {
6905 #ifndef __cplusplus
6906     union
6907     {
6908         struct
6909         {
6910             uint32_t addr : 32; // Register address
6911         };
6912         uint32_t word;
6913     };
6914 #else
6915   private:
6916     uint32_t word0;
6917 
6918   public:
6919     CONSTEXPR debug_address_r() : word0(0) {}
6920     CONSTEXPR debug_address_r(uint32_t init) : word0(init) {}
6921     CONSTEXPR void operator=(uint32_t value)
6922     {
6923         word0 = value;
6924     }
6925     void operator=(uint32_t value) volatile
6926     {
6927         word0 = value;
6928     }
6929     CONSTEXPR operator uint32_t()
6930     {
6931         return word0;
6932     }
6933     operator uint32_t() volatile
6934     {
6935         return word0;
6936     }
6937     debug_address_r copy() volatile
6938     {
6939         return *this;
6940     }
6941     CONSTEXPR uint32_t get_addr() const
6942     {
6943         uint32_t value = word0;
6944         return value;
6945     }
6946     uint32_t get_addr() const volatile
6947     {
6948         uint32_t value = word0;
6949         return value;
6950     }
6951     CONSTEXPR debug_address_r &set_addr(uint32_t value)
6952     {
6953         word0 = value;
6954         return *this;
6955     }
6956     volatile debug_address_r &set_addr(uint32_t value) volatile
6957     {
6958         word0 = value;
6959         return *this;
6960     }
6961 #endif
6962 };
6963 
6964 // debug_misc_r - 32-bit read/write register for driver debug use. This does not affect NPU function
6965 struct debug_misc_r
6966 {
6967 #ifndef __cplusplus
6968     union
6969     {
6970         struct
6971         {
6972             uint32_t misc : 32; // Debug misc
6973         };
6974         uint32_t word;
6975     };
6976 #else
6977   private:
6978     uint32_t word0;
6979 
6980   public:
6981     CONSTEXPR debug_misc_r() : word0(0) {}
6982     CONSTEXPR debug_misc_r(uint32_t init) : word0(init) {}
6983     CONSTEXPR void operator=(uint32_t value)
6984     {
6985         word0 = value;
6986     }
6987     void operator=(uint32_t value) volatile
6988     {
6989         word0 = value;
6990     }
6991     CONSTEXPR operator uint32_t()
6992     {
6993         return word0;
6994     }
6995     operator uint32_t() volatile
6996     {
6997         return word0;
6998     }
6999     debug_misc_r copy() volatile
7000     {
7001         return *this;
7002     }
7003     CONSTEXPR uint32_t get_misc() const
7004     {
7005         uint32_t value = word0;
7006         return value;
7007     }
7008     uint32_t get_misc() const volatile
7009     {
7010         uint32_t value = word0;
7011         return value;
7012     }
7013     CONSTEXPR debug_misc_r &set_misc(uint32_t value)
7014     {
7015         word0 = value;
7016         return *this;
7017     }
7018     volatile debug_misc_r &set_misc(uint32_t value) volatile
7019     {
7020         word0 = value;
7021         return *this;
7022     }
7023 #endif
7024 };
7025 
7026 // debugcore_r - Select core number for debug registers (0x200-0x2FF) and RAM reads (0x400-0x7FF). Value is 0 or 1
7027 struct debugcore_r
7028 {
7029 #ifndef __cplusplus
7030     union
7031     {
7032         struct
7033         {
7034             uint32_t core : 32; // Debug core
7035         };
7036         uint32_t word;
7037     };
7038 #else
7039   private:
7040     uint32_t word0;
7041 
7042   public:
7043     CONSTEXPR debugcore_r() : word0(0) {}
7044     CONSTEXPR debugcore_r(uint32_t init) : word0(init) {}
7045     CONSTEXPR void operator=(uint32_t value)
7046     {
7047         word0 = value;
7048     }
7049     void operator=(uint32_t value) volatile
7050     {
7051         word0 = value;
7052     }
7053     CONSTEXPR operator uint32_t()
7054     {
7055         return word0;
7056     }
7057     operator uint32_t() volatile
7058     {
7059         return word0;
7060     }
7061     debugcore_r copy() volatile
7062     {
7063         return *this;
7064     }
7065     CONSTEXPR uint32_t get_core() const
7066     {
7067         uint32_t value = word0;
7068         return value;
7069     }
7070     uint32_t get_core() const volatile
7071     {
7072         uint32_t value = word0;
7073         return value;
7074     }
7075     CONSTEXPR debugcore_r &set_core(uint32_t value)
7076     {
7077         word0 = value;
7078         return *this;
7079     }
7080     volatile debugcore_r &set_core(uint32_t value) volatile
7081     {
7082         word0 = value;
7083         return *this;
7084     }
7085 #endif
7086 };
7087 
7088 // debug_block_r - Set from which of four block banks the TSU registers are read. 0 = read from the current bank 256+n =
7089 // force to read from bank n where n is in the range 0 to 3
7090 struct debug_block_r
7091 {
7092 #ifndef __cplusplus
7093     union
7094     {
7095         struct
7096         {
7097             uint32_t block : 32; // Debug block
7098         };
7099         uint32_t word;
7100     };
7101 #else
7102   private:
7103     uint32_t word0;
7104 
7105   public:
7106     CONSTEXPR debug_block_r() : word0(0) {}
7107     CONSTEXPR debug_block_r(uint32_t init) : word0(init) {}
7108     CONSTEXPR void operator=(uint32_t value)
7109     {
7110         word0 = value;
7111     }
7112     void operator=(uint32_t value) volatile
7113     {
7114         word0 = value;
7115     }
7116     CONSTEXPR operator uint32_t()
7117     {
7118         return word0;
7119     }
7120     operator uint32_t() volatile
7121     {
7122         return word0;
7123     }
7124     debug_block_r copy() volatile
7125     {
7126         return *this;
7127     }
7128     CONSTEXPR uint32_t get_block() const
7129     {
7130         uint32_t value = word0;
7131         return value;
7132     }
7133     uint32_t get_block() const volatile
7134     {
7135         uint32_t value = word0;
7136         return value;
7137     }
7138     CONSTEXPR debug_block_r &set_block(uint32_t value)
7139     {
7140         word0 = value;
7141         return *this;
7142     }
7143     volatile debug_block_r &set_block(uint32_t value) volatile
7144     {
7145         word0 = value;
7146         return *this;
7147     }
7148 #endif
7149 };
7150 
7151 // pmcr_r - PMU Register control
7152 struct pmcr_r
7153 {
7154 #ifndef __cplusplus
7155     union
7156     {
7157         struct
7158         {
7159             uint32_t cnt_en : 1;        // Enable counter
7160             uint32_t event_cnt_rst : 1; // Reset event counter
7161             uint32_t cycle_cnt_rst : 1; // Reset cycle counter
7162             uint32_t mask_en : 1;       // PMU can be enabled/disabled by command stream operation NPU_OP_PMU_MASK
7163             uint32_t reserved0 : 7;
7164             uint32_t num_event_cnt : 5; // Number of event counters
7165             uint32_t reserved1 : 16;
7166         };
7167         uint32_t word;
7168     };
7169 #else
7170   private:
7171     uint32_t word0;
7172 
7173   public:
7174     CONSTEXPR pmcr_r() : word0(8192) {}
7175     CONSTEXPR pmcr_r(uint32_t init) : word0(init) {}
7176     CONSTEXPR void operator=(uint32_t value)
7177     {
7178         word0 = value;
7179     }
7180     void operator=(uint32_t value) volatile
7181     {
7182         word0 = value;
7183     }
7184     CONSTEXPR operator uint32_t()
7185     {
7186         return word0;
7187     }
7188     operator uint32_t() volatile
7189     {
7190         return word0;
7191     }
7192     pmcr_r copy() volatile
7193     {
7194         return *this;
7195     }
7196     CONSTEXPR uint32_t get_cnt_en() const
7197     {
7198         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7199         return value;
7200     }
7201     uint32_t get_cnt_en() const volatile
7202     {
7203         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7204         return value;
7205     }
7206     CONSTEXPR pmcr_r &set_cnt_en(uint32_t value)
7207     {
7208         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7209         return *this;
7210     }
7211     volatile pmcr_r &set_cnt_en(uint32_t value) volatile
7212     {
7213         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7214         return *this;
7215     }
7216     CONSTEXPR uint32_t get_event_cnt_rst() const
7217     {
7218         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7219         return value;
7220     }
7221     uint32_t get_event_cnt_rst() const volatile
7222     {
7223         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7224         return value;
7225     }
7226     CONSTEXPR pmcr_r &set_event_cnt_rst(uint32_t value)
7227     {
7228         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7229         return *this;
7230     }
7231     volatile pmcr_r &set_event_cnt_rst(uint32_t value) volatile
7232     {
7233         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7234         return *this;
7235     }
7236     CONSTEXPR uint32_t get_cycle_cnt_rst() const
7237     {
7238         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7239         return value;
7240     }
7241     uint32_t get_cycle_cnt_rst() const volatile
7242     {
7243         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7244         return value;
7245     }
7246     CONSTEXPR pmcr_r &set_cycle_cnt_rst(uint32_t value)
7247     {
7248         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7249         return *this;
7250     }
7251     volatile pmcr_r &set_cycle_cnt_rst(uint32_t value) volatile
7252     {
7253         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7254         return *this;
7255     }
7256     CONSTEXPR uint32_t get_mask_en() const
7257     {
7258         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7259         return value;
7260     }
7261     uint32_t get_mask_en() const volatile
7262     {
7263         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7264         return value;
7265     }
7266     CONSTEXPR pmcr_r &set_mask_en(uint32_t value)
7267     {
7268         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7269         return *this;
7270     }
7271     volatile pmcr_r &set_mask_en(uint32_t value) volatile
7272     {
7273         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7274         return *this;
7275     }
7276     CONSTEXPR uint32_t get_num_event_cnt() const
7277     {
7278         uint32_t value = ((1U << 5) - 1) & (word0 >> 11);
7279         return value;
7280     }
7281     uint32_t get_num_event_cnt() const volatile
7282     {
7283         uint32_t value = ((1U << 5) - 1) & (word0 >> 11);
7284         return value;
7285     }
7286     CONSTEXPR pmcr_r &set_num_event_cnt(uint32_t value)
7287     {
7288         word0 = (((~((1U << 5) - 1)) << 11) & word0) | ((((1U << 5) - 1) & value) << 11);
7289         return *this;
7290     }
7291     volatile pmcr_r &set_num_event_cnt(uint32_t value) volatile
7292     {
7293         word0 = (((~((1U << 5) - 1)) << 11) & word0) | ((((1U << 5) - 1) & value) << 11);
7294         return *this;
7295     }
7296 #endif
7297 };
7298 
7299 // pmcntenset_r - Count enable set register
7300 struct pmcntenset_r
7301 {
7302 #ifndef __cplusplus
7303     union
7304     {
7305         struct
7306         {
7307             uint32_t EVENT_CNT_0 : 1; // Event counter enable bit for PMEVCNTR0
7308             uint32_t EVENT_CNT_1 : 1; // Event counter enable bit for PMEVCNTR1
7309             uint32_t EVENT_CNT_2 : 1; // Event counter enable bit for PMEVCNTR2
7310             uint32_t EVENT_CNT_3 : 1; // Event counter enable bit for PMEVCNTR3
7311             uint32_t reserved0 : 27;
7312             uint32_t CYCLE_CNT : 1; // PMCCNTR enable bit
7313         };
7314         uint32_t word;
7315     };
7316 #else
7317   private:
7318     uint32_t word0;
7319 
7320   public:
7321     CONSTEXPR pmcntenset_r() : word0(0) {}
7322     CONSTEXPR pmcntenset_r(uint32_t init) : word0(init) {}
7323     CONSTEXPR void operator=(uint32_t value)
7324     {
7325         word0 = value;
7326     }
7327     void operator=(uint32_t value) volatile
7328     {
7329         word0 = value;
7330     }
7331     CONSTEXPR operator uint32_t()
7332     {
7333         return word0;
7334     }
7335     operator uint32_t() volatile
7336     {
7337         return word0;
7338     }
7339     pmcntenset_r copy() volatile
7340     {
7341         return *this;
7342     }
7343     CONSTEXPR uint32_t get_EVENT_CNT_0() const
7344     {
7345         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7346         return value;
7347     }
7348     uint32_t get_EVENT_CNT_0() const volatile
7349     {
7350         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7351         return value;
7352     }
7353     CONSTEXPR pmcntenset_r &set_EVENT_CNT_0(uint32_t value)
7354     {
7355         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7356         return *this;
7357     }
7358     volatile pmcntenset_r &set_EVENT_CNT_0(uint32_t value) volatile
7359     {
7360         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7361         return *this;
7362     }
7363     CONSTEXPR uint32_t get_EVENT_CNT_1() const
7364     {
7365         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7366         return value;
7367     }
7368     uint32_t get_EVENT_CNT_1() const volatile
7369     {
7370         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7371         return value;
7372     }
7373     CONSTEXPR pmcntenset_r &set_EVENT_CNT_1(uint32_t value)
7374     {
7375         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7376         return *this;
7377     }
7378     volatile pmcntenset_r &set_EVENT_CNT_1(uint32_t value) volatile
7379     {
7380         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7381         return *this;
7382     }
7383     CONSTEXPR uint32_t get_EVENT_CNT_2() const
7384     {
7385         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7386         return value;
7387     }
7388     uint32_t get_EVENT_CNT_2() const volatile
7389     {
7390         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7391         return value;
7392     }
7393     CONSTEXPR pmcntenset_r &set_EVENT_CNT_2(uint32_t value)
7394     {
7395         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7396         return *this;
7397     }
7398     volatile pmcntenset_r &set_EVENT_CNT_2(uint32_t value) volatile
7399     {
7400         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7401         return *this;
7402     }
7403     CONSTEXPR uint32_t get_EVENT_CNT_3() const
7404     {
7405         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7406         return value;
7407     }
7408     uint32_t get_EVENT_CNT_3() const volatile
7409     {
7410         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7411         return value;
7412     }
7413     CONSTEXPR pmcntenset_r &set_EVENT_CNT_3(uint32_t value)
7414     {
7415         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7416         return *this;
7417     }
7418     volatile pmcntenset_r &set_EVENT_CNT_3(uint32_t value) volatile
7419     {
7420         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7421         return *this;
7422     }
7423     CONSTEXPR uint32_t get_CYCLE_CNT() const
7424     {
7425         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7426         return value;
7427     }
7428     uint32_t get_CYCLE_CNT() const volatile
7429     {
7430         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7431         return value;
7432     }
7433     CONSTEXPR pmcntenset_r &set_CYCLE_CNT(uint32_t value)
7434     {
7435         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7436         return *this;
7437     }
7438     volatile pmcntenset_r &set_CYCLE_CNT(uint32_t value) volatile
7439     {
7440         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7441         return *this;
7442     }
7443 #endif
7444 };
7445 
7446 // pmcntenclr_r - Count enable clear register
7447 struct pmcntenclr_r
7448 {
7449 #ifndef __cplusplus
7450     union
7451     {
7452         struct
7453         {
7454             uint32_t EVENT_CNT_0 : 1; // Event counter disable bit for PMEVCNTR0
7455             uint32_t EVENT_CNT_1 : 1; // Event counter disable bit for PMEVCNTR1
7456             uint32_t EVENT_CNT_2 : 1; // Event counter disable bit for PMEVCNTR2
7457             uint32_t EVENT_CNT_3 : 1; // Event counter disable bit for PMEVCNTR3
7458             uint32_t reserved0 : 27;
7459             uint32_t CYCLE_CNT : 1; // PMCCNTR disable bit
7460         };
7461         uint32_t word;
7462     };
7463 #else
7464   private:
7465     uint32_t word0;
7466 
7467   public:
7468     CONSTEXPR pmcntenclr_r() : word0(0) {}
7469     CONSTEXPR pmcntenclr_r(uint32_t init) : word0(init) {}
7470     CONSTEXPR void operator=(uint32_t value)
7471     {
7472         word0 = value;
7473     }
7474     void operator=(uint32_t value) volatile
7475     {
7476         word0 = value;
7477     }
7478     CONSTEXPR operator uint32_t()
7479     {
7480         return word0;
7481     }
7482     operator uint32_t() volatile
7483     {
7484         return word0;
7485     }
7486     pmcntenclr_r copy() volatile
7487     {
7488         return *this;
7489     }
7490     CONSTEXPR uint32_t get_EVENT_CNT_0() const
7491     {
7492         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7493         return value;
7494     }
7495     uint32_t get_EVENT_CNT_0() const volatile
7496     {
7497         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7498         return value;
7499     }
7500     CONSTEXPR pmcntenclr_r &set_EVENT_CNT_0(uint32_t value)
7501     {
7502         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7503         return *this;
7504     }
7505     volatile pmcntenclr_r &set_EVENT_CNT_0(uint32_t value) volatile
7506     {
7507         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7508         return *this;
7509     }
7510     CONSTEXPR uint32_t get_EVENT_CNT_1() const
7511     {
7512         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7513         return value;
7514     }
7515     uint32_t get_EVENT_CNT_1() const volatile
7516     {
7517         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7518         return value;
7519     }
7520     CONSTEXPR pmcntenclr_r &set_EVENT_CNT_1(uint32_t value)
7521     {
7522         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7523         return *this;
7524     }
7525     volatile pmcntenclr_r &set_EVENT_CNT_1(uint32_t value) volatile
7526     {
7527         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7528         return *this;
7529     }
7530     CONSTEXPR uint32_t get_EVENT_CNT_2() const
7531     {
7532         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7533         return value;
7534     }
7535     uint32_t get_EVENT_CNT_2() const volatile
7536     {
7537         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7538         return value;
7539     }
7540     CONSTEXPR pmcntenclr_r &set_EVENT_CNT_2(uint32_t value)
7541     {
7542         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7543         return *this;
7544     }
7545     volatile pmcntenclr_r &set_EVENT_CNT_2(uint32_t value) volatile
7546     {
7547         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7548         return *this;
7549     }
7550     CONSTEXPR uint32_t get_EVENT_CNT_3() const
7551     {
7552         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7553         return value;
7554     }
7555     uint32_t get_EVENT_CNT_3() const volatile
7556     {
7557         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7558         return value;
7559     }
7560     CONSTEXPR pmcntenclr_r &set_EVENT_CNT_3(uint32_t value)
7561     {
7562         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7563         return *this;
7564     }
7565     volatile pmcntenclr_r &set_EVENT_CNT_3(uint32_t value) volatile
7566     {
7567         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7568         return *this;
7569     }
7570     CONSTEXPR uint32_t get_CYCLE_CNT() const
7571     {
7572         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7573         return value;
7574     }
7575     uint32_t get_CYCLE_CNT() const volatile
7576     {
7577         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7578         return value;
7579     }
7580     CONSTEXPR pmcntenclr_r &set_CYCLE_CNT(uint32_t value)
7581     {
7582         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7583         return *this;
7584     }
7585     volatile pmcntenclr_r &set_CYCLE_CNT(uint32_t value) volatile
7586     {
7587         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7588         return *this;
7589     }
7590 #endif
7591 };
7592 
7593 // pmovsset_r - Overflow flag status set register
7594 struct pmovsset_r
7595 {
7596 #ifndef __cplusplus
7597     union
7598     {
7599         struct
7600         {
7601             uint32_t EVENT_CNT_0_OVF : 1; // Event counter overflow set bit for PMEVCNTR0
7602             uint32_t EVENT_CNT_1_OVF : 1; // Event counter overflow set bit for PMEVCNTR1
7603             uint32_t EVENT_CNT_2_OVF : 1; // Event counter overflow set bit for PMEVCNTR2
7604             uint32_t EVENT_CNT_3_OVF : 1; // Event counter overflow set bit for PMEVCNTR3
7605             uint32_t reserved0 : 27;
7606             uint32_t CYCLE_CNT_OVF : 1; // PMCCNTR overflow set bit
7607         };
7608         uint32_t word;
7609     };
7610 #else
7611   private:
7612     uint32_t word0;
7613 
7614   public:
7615     CONSTEXPR pmovsset_r() : word0(0) {}
7616     CONSTEXPR pmovsset_r(uint32_t init) : word0(init) {}
7617     CONSTEXPR void operator=(uint32_t value)
7618     {
7619         word0 = value;
7620     }
7621     void operator=(uint32_t value) volatile
7622     {
7623         word0 = value;
7624     }
7625     CONSTEXPR operator uint32_t()
7626     {
7627         return word0;
7628     }
7629     operator uint32_t() volatile
7630     {
7631         return word0;
7632     }
7633     pmovsset_r copy() volatile
7634     {
7635         return *this;
7636     }
7637     CONSTEXPR uint32_t get_EVENT_CNT_0_OVF() const
7638     {
7639         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7640         return value;
7641     }
7642     uint32_t get_EVENT_CNT_0_OVF() const volatile
7643     {
7644         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7645         return value;
7646     }
7647     CONSTEXPR pmovsset_r &set_EVENT_CNT_0_OVF(uint32_t value)
7648     {
7649         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7650         return *this;
7651     }
7652     volatile pmovsset_r &set_EVENT_CNT_0_OVF(uint32_t value) volatile
7653     {
7654         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7655         return *this;
7656     }
7657     CONSTEXPR uint32_t get_EVENT_CNT_1_OVF() const
7658     {
7659         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7660         return value;
7661     }
7662     uint32_t get_EVENT_CNT_1_OVF() const volatile
7663     {
7664         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7665         return value;
7666     }
7667     CONSTEXPR pmovsset_r &set_EVENT_CNT_1_OVF(uint32_t value)
7668     {
7669         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7670         return *this;
7671     }
7672     volatile pmovsset_r &set_EVENT_CNT_1_OVF(uint32_t value) volatile
7673     {
7674         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7675         return *this;
7676     }
7677     CONSTEXPR uint32_t get_EVENT_CNT_2_OVF() const
7678     {
7679         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7680         return value;
7681     }
7682     uint32_t get_EVENT_CNT_2_OVF() const volatile
7683     {
7684         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7685         return value;
7686     }
7687     CONSTEXPR pmovsset_r &set_EVENT_CNT_2_OVF(uint32_t value)
7688     {
7689         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7690         return *this;
7691     }
7692     volatile pmovsset_r &set_EVENT_CNT_2_OVF(uint32_t value) volatile
7693     {
7694         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7695         return *this;
7696     }
7697     CONSTEXPR uint32_t get_EVENT_CNT_3_OVF() const
7698     {
7699         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7700         return value;
7701     }
7702     uint32_t get_EVENT_CNT_3_OVF() const volatile
7703     {
7704         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7705         return value;
7706     }
7707     CONSTEXPR pmovsset_r &set_EVENT_CNT_3_OVF(uint32_t value)
7708     {
7709         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7710         return *this;
7711     }
7712     volatile pmovsset_r &set_EVENT_CNT_3_OVF(uint32_t value) volatile
7713     {
7714         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7715         return *this;
7716     }
7717     CONSTEXPR uint32_t get_CYCLE_CNT_OVF() const
7718     {
7719         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7720         return value;
7721     }
7722     uint32_t get_CYCLE_CNT_OVF() const volatile
7723     {
7724         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7725         return value;
7726     }
7727     CONSTEXPR pmovsset_r &set_CYCLE_CNT_OVF(uint32_t value)
7728     {
7729         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7730         return *this;
7731     }
7732     volatile pmovsset_r &set_CYCLE_CNT_OVF(uint32_t value) volatile
7733     {
7734         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7735         return *this;
7736     }
7737 #endif
7738 };
7739 
7740 // pmovsclr_r - Overflow flag status clear register
7741 struct pmovsclr_r
7742 {
7743 #ifndef __cplusplus
7744     union
7745     {
7746         struct
7747         {
7748             uint32_t EVENT_CNT_0_OVF : 1; // Event counter overflow clear bit for PMEVCNTR0
7749             uint32_t EVENT_CNT_1_OVF : 1; // Event counter overflow clear bit for PMEVCNTR1
7750             uint32_t EVENT_CNT_2_OVF : 1; // Event counter overflow clear bit for PMEVCNTR2
7751             uint32_t EVENT_CNT_3_OVF : 1; // Event counter overflow clear bit for PMEVCNTR3
7752             uint32_t reserved0 : 27;
7753             uint32_t CYCLE_CNT_OVF : 1; // PMCCNTR overflow clear bit
7754         };
7755         uint32_t word;
7756     };
7757 #else
7758   private:
7759     uint32_t word0;
7760 
7761   public:
7762     CONSTEXPR pmovsclr_r() : word0(0) {}
7763     CONSTEXPR pmovsclr_r(uint32_t init) : word0(init) {}
7764     CONSTEXPR void operator=(uint32_t value)
7765     {
7766         word0 = value;
7767     }
7768     void operator=(uint32_t value) volatile
7769     {
7770         word0 = value;
7771     }
7772     CONSTEXPR operator uint32_t()
7773     {
7774         return word0;
7775     }
7776     operator uint32_t() volatile
7777     {
7778         return word0;
7779     }
7780     pmovsclr_r copy() volatile
7781     {
7782         return *this;
7783     }
7784     CONSTEXPR uint32_t get_EVENT_CNT_0_OVF() const
7785     {
7786         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7787         return value;
7788     }
7789     uint32_t get_EVENT_CNT_0_OVF() const volatile
7790     {
7791         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7792         return value;
7793     }
7794     CONSTEXPR pmovsclr_r &set_EVENT_CNT_0_OVF(uint32_t value)
7795     {
7796         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7797         return *this;
7798     }
7799     volatile pmovsclr_r &set_EVENT_CNT_0_OVF(uint32_t value) volatile
7800     {
7801         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7802         return *this;
7803     }
7804     CONSTEXPR uint32_t get_EVENT_CNT_1_OVF() const
7805     {
7806         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7807         return value;
7808     }
7809     uint32_t get_EVENT_CNT_1_OVF() const volatile
7810     {
7811         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7812         return value;
7813     }
7814     CONSTEXPR pmovsclr_r &set_EVENT_CNT_1_OVF(uint32_t value)
7815     {
7816         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7817         return *this;
7818     }
7819     volatile pmovsclr_r &set_EVENT_CNT_1_OVF(uint32_t value) volatile
7820     {
7821         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7822         return *this;
7823     }
7824     CONSTEXPR uint32_t get_EVENT_CNT_2_OVF() const
7825     {
7826         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7827         return value;
7828     }
7829     uint32_t get_EVENT_CNT_2_OVF() const volatile
7830     {
7831         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7832         return value;
7833     }
7834     CONSTEXPR pmovsclr_r &set_EVENT_CNT_2_OVF(uint32_t value)
7835     {
7836         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7837         return *this;
7838     }
7839     volatile pmovsclr_r &set_EVENT_CNT_2_OVF(uint32_t value) volatile
7840     {
7841         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7842         return *this;
7843     }
7844     CONSTEXPR uint32_t get_EVENT_CNT_3_OVF() const
7845     {
7846         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7847         return value;
7848     }
7849     uint32_t get_EVENT_CNT_3_OVF() const volatile
7850     {
7851         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7852         return value;
7853     }
7854     CONSTEXPR pmovsclr_r &set_EVENT_CNT_3_OVF(uint32_t value)
7855     {
7856         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7857         return *this;
7858     }
7859     volatile pmovsclr_r &set_EVENT_CNT_3_OVF(uint32_t value) volatile
7860     {
7861         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7862         return *this;
7863     }
7864     CONSTEXPR uint32_t get_CYCLE_CNT_OVF() const
7865     {
7866         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7867         return value;
7868     }
7869     uint32_t get_CYCLE_CNT_OVF() const volatile
7870     {
7871         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7872         return value;
7873     }
7874     CONSTEXPR pmovsclr_r &set_CYCLE_CNT_OVF(uint32_t value)
7875     {
7876         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7877         return *this;
7878     }
7879     volatile pmovsclr_r &set_CYCLE_CNT_OVF(uint32_t value) volatile
7880     {
7881         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7882         return *this;
7883     }
7884 #endif
7885 };
7886 
7887 // pmintset_r - Interrupt enable set register
7888 struct pmintset_r
7889 {
7890 #ifndef __cplusplus
7891     union
7892     {
7893         struct
7894         {
7895             uint32_t EVENT_CNT_0_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR0
7896             uint32_t EVENT_CNT_1_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR1
7897             uint32_t EVENT_CNT_2_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR2
7898             uint32_t EVENT_CNT_3_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR3
7899             uint32_t reserved0 : 27;
7900             uint32_t CYCLE_CNT_INT : 1; // PMCCNTR overflow interrupt request enable bit
7901         };
7902         uint32_t word;
7903     };
7904 #else
7905   private:
7906     uint32_t word0;
7907 
7908   public:
7909     CONSTEXPR pmintset_r() : word0(0) {}
7910     CONSTEXPR pmintset_r(uint32_t init) : word0(init) {}
7911     CONSTEXPR void operator=(uint32_t value)
7912     {
7913         word0 = value;
7914     }
7915     void operator=(uint32_t value) volatile
7916     {
7917         word0 = value;
7918     }
7919     CONSTEXPR operator uint32_t()
7920     {
7921         return word0;
7922     }
7923     operator uint32_t() volatile
7924     {
7925         return word0;
7926     }
7927     pmintset_r copy() volatile
7928     {
7929         return *this;
7930     }
7931     CONSTEXPR uint32_t get_EVENT_CNT_0_INT() const
7932     {
7933         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7934         return value;
7935     }
7936     uint32_t get_EVENT_CNT_0_INT() const volatile
7937     {
7938         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7939         return value;
7940     }
7941     CONSTEXPR pmintset_r &set_EVENT_CNT_0_INT(uint32_t value)
7942     {
7943         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7944         return *this;
7945     }
7946     volatile pmintset_r &set_EVENT_CNT_0_INT(uint32_t value) volatile
7947     {
7948         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7949         return *this;
7950     }
7951     CONSTEXPR uint32_t get_EVENT_CNT_1_INT() const
7952     {
7953         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7954         return value;
7955     }
7956     uint32_t get_EVENT_CNT_1_INT() const volatile
7957     {
7958         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7959         return value;
7960     }
7961     CONSTEXPR pmintset_r &set_EVENT_CNT_1_INT(uint32_t value)
7962     {
7963         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7964         return *this;
7965     }
7966     volatile pmintset_r &set_EVENT_CNT_1_INT(uint32_t value) volatile
7967     {
7968         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7969         return *this;
7970     }
7971     CONSTEXPR uint32_t get_EVENT_CNT_2_INT() const
7972     {
7973         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7974         return value;
7975     }
7976     uint32_t get_EVENT_CNT_2_INT() const volatile
7977     {
7978         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7979         return value;
7980     }
7981     CONSTEXPR pmintset_r &set_EVENT_CNT_2_INT(uint32_t value)
7982     {
7983         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7984         return *this;
7985     }
7986     volatile pmintset_r &set_EVENT_CNT_2_INT(uint32_t value) volatile
7987     {
7988         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7989         return *this;
7990     }
7991     CONSTEXPR uint32_t get_EVENT_CNT_3_INT() const
7992     {
7993         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7994         return value;
7995     }
7996     uint32_t get_EVENT_CNT_3_INT() const volatile
7997     {
7998         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7999         return value;
8000     }
8001     CONSTEXPR pmintset_r &set_EVENT_CNT_3_INT(uint32_t value)
8002     {
8003         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
8004         return *this;
8005     }
8006     volatile pmintset_r &set_EVENT_CNT_3_INT(uint32_t value) volatile
8007     {
8008         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
8009         return *this;
8010     }
8011     CONSTEXPR uint32_t get_CYCLE_CNT_INT() const
8012     {
8013         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
8014         return value;
8015     }
8016     uint32_t get_CYCLE_CNT_INT() const volatile
8017     {
8018         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
8019         return value;
8020     }
8021     CONSTEXPR pmintset_r &set_CYCLE_CNT_INT(uint32_t value)
8022     {
8023         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
8024         return *this;
8025     }
8026     volatile pmintset_r &set_CYCLE_CNT_INT(uint32_t value) volatile
8027     {
8028         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
8029         return *this;
8030     }
8031 #endif
8032 };
8033 
8034 // pmintclr_r - Interrupt enable clear register
8035 struct pmintclr_r
8036 {
8037 #ifndef __cplusplus
8038     union
8039     {
8040         struct
8041         {
8042             uint32_t EVENT_CNT_0_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR0
8043             uint32_t EVENT_CNT_1_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR1
8044             uint32_t EVENT_CNT_2_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR2
8045             uint32_t EVENT_CNT_3_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR3
8046             uint32_t reserved0 : 27;
8047             uint32_t CYCLE_CNT_INT : 1; // PMCCNTR overflow interrupt request disable bit
8048         };
8049         uint32_t word;
8050     };
8051 #else
8052   private:
8053     uint32_t word0;
8054 
8055   public:
8056     CONSTEXPR pmintclr_r() : word0(0) {}
8057     CONSTEXPR pmintclr_r(uint32_t init) : word0(init) {}
8058     CONSTEXPR void operator=(uint32_t value)
8059     {
8060         word0 = value;
8061     }
8062     void operator=(uint32_t value) volatile
8063     {
8064         word0 = value;
8065     }
8066     CONSTEXPR operator uint32_t()
8067     {
8068         return word0;
8069     }
8070     operator uint32_t() volatile
8071     {
8072         return word0;
8073     }
8074     pmintclr_r copy() volatile
8075     {
8076         return *this;
8077     }
8078     CONSTEXPR uint32_t get_EVENT_CNT_0_INT() const
8079     {
8080         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
8081         return value;
8082     }
8083     uint32_t get_EVENT_CNT_0_INT() const volatile
8084     {
8085         uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
8086         return value;
8087     }
8088     CONSTEXPR pmintclr_r &set_EVENT_CNT_0_INT(uint32_t value)
8089     {
8090         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
8091         return *this;
8092     }
8093     volatile pmintclr_r &set_EVENT_CNT_0_INT(uint32_t value) volatile
8094     {
8095         word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
8096         return *this;
8097     }
8098     CONSTEXPR uint32_t get_EVENT_CNT_1_INT() const
8099     {
8100         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
8101         return value;
8102     }
8103     uint32_t get_EVENT_CNT_1_INT() const volatile
8104     {
8105         uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
8106         return value;
8107     }
8108     CONSTEXPR pmintclr_r &set_EVENT_CNT_1_INT(uint32_t value)
8109     {
8110         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
8111         return *this;
8112     }
8113     volatile pmintclr_r &set_EVENT_CNT_1_INT(uint32_t value) volatile
8114     {
8115         word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
8116         return *this;
8117     }
8118     CONSTEXPR uint32_t get_EVENT_CNT_2_INT() const
8119     {
8120         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
8121         return value;
8122     }
8123     uint32_t get_EVENT_CNT_2_INT() const volatile
8124     {
8125         uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
8126         return value;
8127     }
8128     CONSTEXPR pmintclr_r &set_EVENT_CNT_2_INT(uint32_t value)
8129     {
8130         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
8131         return *this;
8132     }
8133     volatile pmintclr_r &set_EVENT_CNT_2_INT(uint32_t value) volatile
8134     {
8135         word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
8136         return *this;
8137     }
8138     CONSTEXPR uint32_t get_EVENT_CNT_3_INT() const
8139     {
8140         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
8141         return value;
8142     }
8143     uint32_t get_EVENT_CNT_3_INT() const volatile
8144     {
8145         uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
8146         return value;
8147     }
8148     CONSTEXPR pmintclr_r &set_EVENT_CNT_3_INT(uint32_t value)
8149     {
8150         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
8151         return *this;
8152     }
8153     volatile pmintclr_r &set_EVENT_CNT_3_INT(uint32_t value) volatile
8154     {
8155         word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
8156         return *this;
8157     }
8158     CONSTEXPR uint32_t get_CYCLE_CNT_INT() const
8159     {
8160         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
8161         return value;
8162     }
8163     uint32_t get_CYCLE_CNT_INT() const volatile
8164     {
8165         uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
8166         return value;
8167     }
8168     CONSTEXPR pmintclr_r &set_CYCLE_CNT_INT(uint32_t value)
8169     {
8170         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
8171         return *this;
8172     }
8173     volatile pmintclr_r &set_CYCLE_CNT_INT(uint32_t value) volatile
8174     {
8175         word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
8176         return *this;
8177     }
8178 #endif
8179 };
8180 
8181 // pmccntr_r - Performance monitor cycle count register
8182 struct pmccntr_r
8183 {
8184 #ifndef __cplusplus
8185     union
8186     {
8187         struct
8188         {
8189             uint32_t CYCLE_CNT_LO : 32; // Cycle count - LSB
8190             uint32_t CYCLE_CNT_HI : 16; // Cycle count - MSB
8191             uint32_t reserved0 : 16;
8192         };
8193         uint32_t word[2];
8194     };
8195 #else
8196   private:
8197     uint32_t word0;
8198     uint32_t word1;
8199 
8200   public:
8201     CONSTEXPR pmccntr_r() : word0(0), word1(0) {}
8202     CONSTEXPR pmccntr_r(uint64_t init) :
8203         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
8204         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
8205     {
8206     }
8207     CONSTEXPR void operator=(uint64_t value)
8208     {
8209         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
8210         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
8211     }
8212     void operator=(uint64_t value) volatile
8213     {
8214         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
8215         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
8216     }
8217     CONSTEXPR operator uint64_t()
8218     {
8219         return (static_cast<uint64_t>(word1) << 32) | word0;
8220     }
8221     operator uint64_t() volatile
8222     {
8223         return (static_cast<uint64_t>(word1) << 32) | word0;
8224     }
8225     pmccntr_r copy() volatile
8226     {
8227         return *this;
8228     }
8229 #endif
8230 };
8231 
8232 // pmccntr_cfg_r - Set start/stop event on the cycle counter
8233 struct pmccntr_cfg_r
8234 {
8235 #ifndef __cplusplus
8236     union
8237     {
8238         struct
8239         {
8240             uint32_t CYCLE_CNT_CFG_START : 10; // Cycle counter start event
8241             uint32_t reserved0 : 6;
8242             uint32_t CYCLE_CNT_CFG_STOP : 10; // Cycle counter stop event
8243             uint32_t reserved1 : 6;
8244         };
8245         uint32_t word;
8246     };
8247 #else
8248   private:
8249     uint32_t word0;
8250 
8251   public:
8252     CONSTEXPR pmccntr_cfg_r() : word0(0) {}
8253     CONSTEXPR pmccntr_cfg_r(uint32_t init) : word0(init) {}
8254     CONSTEXPR void operator=(uint32_t value)
8255     {
8256         word0 = value;
8257     }
8258     void operator=(uint32_t value) volatile
8259     {
8260         word0 = value;
8261     }
8262     CONSTEXPR operator uint32_t()
8263     {
8264         return word0;
8265     }
8266     operator uint32_t() volatile
8267     {
8268         return word0;
8269     }
8270     pmccntr_cfg_r copy() volatile
8271     {
8272         return *this;
8273     }
8274     CONSTEXPR NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_START() const
8275     {
8276         NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 0));
8277         return value;
8278     }
8279     NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_START() const volatile
8280     {
8281         NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 0));
8282         return value;
8283     }
8284     CONSTEXPR pmccntr_cfg_r &set_CYCLE_CNT_CFG_START(NPU_NAMESPACE::pmu_event value)
8285     {
8286         word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 0);
8287         return *this;
8288     }
8289     volatile pmccntr_cfg_r &set_CYCLE_CNT_CFG_START(NPU_NAMESPACE::pmu_event value) volatile
8290     {
8291         word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 0);
8292         return *this;
8293     }
8294     CONSTEXPR NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_STOP() const
8295     {
8296         NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 16));
8297         return value;
8298     }
8299     NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_STOP() const volatile
8300     {
8301         NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 16));
8302         return value;
8303     }
8304     CONSTEXPR pmccntr_cfg_r &set_CYCLE_CNT_CFG_STOP(NPU_NAMESPACE::pmu_event value)
8305     {
8306         word0 = (((~((1U << 10) - 1)) << 16) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 16);
8307         return *this;
8308     }
8309     volatile pmccntr_cfg_r &set_CYCLE_CNT_CFG_STOP(NPU_NAMESPACE::pmu_event value) volatile
8310     {
8311         word0 = (((~((1U << 10) - 1)) << 16) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 16);
8312         return *this;
8313     }
8314 #endif
8315 };
8316 
8317 // pmcaxi_chan_r - Set which AXI channel to monitor for latency measurements in PMU
8318 struct pmcaxi_chan_r
8319 {
8320 #ifndef __cplusplus
8321     union
8322     {
8323         struct
8324         {
8325             uint32_t CH_SEL : 4; // Channel select for latency measurements
8326             uint32_t reserved0 : 4;
8327             uint32_t AXI_CNT_SEL : 2;  // AXI counter to monitor for latency measurements
8328             uint32_t BW_CH_SEL_EN : 1; // Bandwidth channel selector
8329             uint32_t reserved1 : 21;
8330         };
8331         uint32_t word;
8332     };
8333 #else
8334   private:
8335     uint32_t word0;
8336 
8337   public:
8338     CONSTEXPR pmcaxi_chan_r() : word0(0) {}
8339     CONSTEXPR pmcaxi_chan_r(uint32_t init) : word0(init) {}
8340     CONSTEXPR void operator=(uint32_t value)
8341     {
8342         word0 = value;
8343     }
8344     void operator=(uint32_t value) volatile
8345     {
8346         word0 = value;
8347     }
8348     CONSTEXPR operator uint32_t()
8349     {
8350         return word0;
8351     }
8352     operator uint32_t() volatile
8353     {
8354         return word0;
8355     }
8356     pmcaxi_chan_r copy() volatile
8357     {
8358         return *this;
8359     }
8360     CONSTEXPR NPU_NAMESPACE::pmu_axi_channel get_CH_SEL() const
8361     {
8362         NPU_NAMESPACE::pmu_axi_channel value =
8363             static_cast<NPU_NAMESPACE::pmu_axi_channel>(((1U << 4) - 1) & (word0 >> 0));
8364         return value;
8365     }
8366     NPU_NAMESPACE::pmu_axi_channel get_CH_SEL() const volatile
8367     {
8368         NPU_NAMESPACE::pmu_axi_channel value =
8369             static_cast<NPU_NAMESPACE::pmu_axi_channel>(((1U << 4) - 1) & (word0 >> 0));
8370         return value;
8371     }
8372     CONSTEXPR pmcaxi_chan_r &set_CH_SEL(NPU_NAMESPACE::pmu_axi_channel value)
8373     {
8374         word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 0);
8375         return *this;
8376     }
8377     volatile pmcaxi_chan_r &set_CH_SEL(NPU_NAMESPACE::pmu_axi_channel value) volatile
8378     {
8379         word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 0);
8380         return *this;
8381     }
8382     CONSTEXPR uint32_t get_AXI_CNT_SEL() const
8383     {
8384         uint32_t value = ((1U << 2) - 1) & (word0 >> 8);
8385         return value;
8386     }
8387     uint32_t get_AXI_CNT_SEL() const volatile
8388     {
8389         uint32_t value = ((1U << 2) - 1) & (word0 >> 8);
8390         return value;
8391     }
8392     CONSTEXPR pmcaxi_chan_r &set_AXI_CNT_SEL(uint32_t value)
8393     {
8394         word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & value) << 8);
8395         return *this;
8396     }
8397     volatile pmcaxi_chan_r &set_AXI_CNT_SEL(uint32_t value) volatile
8398     {
8399         word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & value) << 8);
8400         return *this;
8401     }
8402     CONSTEXPR uint32_t get_BW_CH_SEL_EN() const
8403     {
8404         uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
8405         return value;
8406     }
8407     uint32_t get_BW_CH_SEL_EN() const volatile
8408     {
8409         uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
8410         return value;
8411     }
8412     CONSTEXPR pmcaxi_chan_r &set_BW_CH_SEL_EN(uint32_t value)
8413     {
8414         word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
8415         return *this;
8416     }
8417     volatile pmcaxi_chan_r &set_BW_CH_SEL_EN(uint32_t value) volatile
8418     {
8419         word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
8420         return *this;
8421     }
8422 #endif
8423 };
8424 
8425 // kernel_x_r - Kernel X offset of in kernel decomposition
8426 struct kernel_x_r
8427 {
8428 #ifndef __cplusplus
8429     union
8430     {
8431         struct
8432         {
8433             uint32_t value : 32; // 32-bit register value
8434         };
8435         uint32_t word;
8436     };
8437 #else
8438   private:
8439     uint32_t word0;
8440 
8441   public:
8442     CONSTEXPR kernel_x_r() : word0(0) {}
8443     CONSTEXPR kernel_x_r(uint32_t init) : word0(init) {}
8444     CONSTEXPR void operator=(uint32_t value)
8445     {
8446         word0 = value;
8447     }
8448     void operator=(uint32_t value) volatile
8449     {
8450         word0 = value;
8451     }
8452     CONSTEXPR operator uint32_t()
8453     {
8454         return word0;
8455     }
8456     operator uint32_t() volatile
8457     {
8458         return word0;
8459     }
8460     kernel_x_r copy() volatile
8461     {
8462         return *this;
8463     }
8464     CONSTEXPR uint32_t get_value() const
8465     {
8466         uint32_t value = word0;
8467         return value;
8468     }
8469     uint32_t get_value() const volatile
8470     {
8471         uint32_t value = word0;
8472         return value;
8473     }
8474     CONSTEXPR kernel_x_r &set_value(uint32_t value)
8475     {
8476         word0 = value;
8477         return *this;
8478     }
8479     volatile kernel_x_r &set_value(uint32_t value) volatile
8480     {
8481         word0 = value;
8482         return *this;
8483     }
8484 #endif
8485 };
8486 
8487 // kernel_y_r - Kernel Y offset of in kernel decomposition
8488 struct kernel_y_r
8489 {
8490 #ifndef __cplusplus
8491     union
8492     {
8493         struct
8494         {
8495             uint32_t value : 32; // 32-bit register value
8496         };
8497         uint32_t word;
8498     };
8499 #else
8500   private:
8501     uint32_t word0;
8502 
8503   public:
8504     CONSTEXPR kernel_y_r() : word0(0) {}
8505     CONSTEXPR kernel_y_r(uint32_t init) : word0(init) {}
8506     CONSTEXPR void operator=(uint32_t value)
8507     {
8508         word0 = value;
8509     }
8510     void operator=(uint32_t value) volatile
8511     {
8512         word0 = value;
8513     }
8514     CONSTEXPR operator uint32_t()
8515     {
8516         return word0;
8517     }
8518     operator uint32_t() volatile
8519     {
8520         return word0;
8521     }
8522     kernel_y_r copy() volatile
8523     {
8524         return *this;
8525     }
8526     CONSTEXPR uint32_t get_value() const
8527     {
8528         uint32_t value = word0;
8529         return value;
8530     }
8531     uint32_t get_value() const volatile
8532     {
8533         uint32_t value = word0;
8534         return value;
8535     }
8536     CONSTEXPR kernel_y_r &set_value(uint32_t value)
8537     {
8538         word0 = value;
8539         return *this;
8540     }
8541     volatile kernel_y_r &set_value(uint32_t value) volatile
8542     {
8543         word0 = value;
8544         return *this;
8545     }
8546 #endif
8547 };
8548 
8549 // kernel_w_m1_r - Kernel (width-1) of current block
8550 struct kernel_w_m1_r
8551 {
8552 #ifndef __cplusplus
8553     union
8554     {
8555         struct
8556         {
8557             uint32_t value : 32; // 32-bit register value
8558         };
8559         uint32_t word;
8560     };
8561 #else
8562   private:
8563     uint32_t word0;
8564 
8565   public:
8566     CONSTEXPR kernel_w_m1_r() : word0(0) {}
8567     CONSTEXPR kernel_w_m1_r(uint32_t init) : word0(init) {}
8568     CONSTEXPR void operator=(uint32_t value)
8569     {
8570         word0 = value;
8571     }
8572     void operator=(uint32_t value) volatile
8573     {
8574         word0 = value;
8575     }
8576     CONSTEXPR operator uint32_t()
8577     {
8578         return word0;
8579     }
8580     operator uint32_t() volatile
8581     {
8582         return word0;
8583     }
8584     kernel_w_m1_r copy() volatile
8585     {
8586         return *this;
8587     }
8588     CONSTEXPR uint32_t get_value() const
8589     {
8590         uint32_t value = word0;
8591         return value;
8592     }
8593     uint32_t get_value() const volatile
8594     {
8595         uint32_t value = word0;
8596         return value;
8597     }
8598     CONSTEXPR kernel_w_m1_r &set_value(uint32_t value)
8599     {
8600         word0 = value;
8601         return *this;
8602     }
8603     volatile kernel_w_m1_r &set_value(uint32_t value) volatile
8604     {
8605         word0 = value;
8606         return *this;
8607     }
8608 #endif
8609 };
8610 
8611 // kernel_h_m1_r - Kernel (height-1) of current block
8612 struct kernel_h_m1_r
8613 {
8614 #ifndef __cplusplus
8615     union
8616     {
8617         struct
8618         {
8619             uint32_t value : 32; // 32-bit register value
8620         };
8621         uint32_t word;
8622     };
8623 #else
8624   private:
8625     uint32_t word0;
8626 
8627   public:
8628     CONSTEXPR kernel_h_m1_r() : word0(0) {}
8629     CONSTEXPR kernel_h_m1_r(uint32_t init) : word0(init) {}
8630     CONSTEXPR void operator=(uint32_t value)
8631     {
8632         word0 = value;
8633     }
8634     void operator=(uint32_t value) volatile
8635     {
8636         word0 = value;
8637     }
8638     CONSTEXPR operator uint32_t()
8639     {
8640         return word0;
8641     }
8642     operator uint32_t() volatile
8643     {
8644         return word0;
8645     }
8646     kernel_h_m1_r copy() volatile
8647     {
8648         return *this;
8649     }
8650     CONSTEXPR uint32_t get_value() const
8651     {
8652         uint32_t value = word0;
8653         return value;
8654     }
8655     uint32_t get_value() const volatile
8656     {
8657         uint32_t value = word0;
8658         return value;
8659     }
8660     CONSTEXPR kernel_h_m1_r &set_value(uint32_t value)
8661     {
8662         word0 = value;
8663         return *this;
8664     }
8665     volatile kernel_h_m1_r &set_value(uint32_t value) volatile
8666     {
8667         word0 = value;
8668         return *this;
8669     }
8670 #endif
8671 };
8672 
8673 // ofm_cblk_width_m1_r - OFM current block (width-1)
8674 struct ofm_cblk_width_m1_r
8675 {
8676 #ifndef __cplusplus
8677     union
8678     {
8679         struct
8680         {
8681             uint32_t value : 32; // 32-bit register value
8682         };
8683         uint32_t word;
8684     };
8685 #else
8686   private:
8687     uint32_t word0;
8688 
8689   public:
8690     CONSTEXPR ofm_cblk_width_m1_r() : word0(0) {}
8691     CONSTEXPR ofm_cblk_width_m1_r(uint32_t init) : word0(init) {}
8692     CONSTEXPR void operator=(uint32_t value)
8693     {
8694         word0 = value;
8695     }
8696     void operator=(uint32_t value) volatile
8697     {
8698         word0 = value;
8699     }
8700     CONSTEXPR operator uint32_t()
8701     {
8702         return word0;
8703     }
8704     operator uint32_t() volatile
8705     {
8706         return word0;
8707     }
8708     ofm_cblk_width_m1_r copy() volatile
8709     {
8710         return *this;
8711     }
8712     CONSTEXPR uint32_t get_value() const
8713     {
8714         uint32_t value = word0;
8715         return value;
8716     }
8717     uint32_t get_value() const volatile
8718     {
8719         uint32_t value = word0;
8720         return value;
8721     }
8722     CONSTEXPR ofm_cblk_width_m1_r &set_value(uint32_t value)
8723     {
8724         word0 = value;
8725         return *this;
8726     }
8727     volatile ofm_cblk_width_m1_r &set_value(uint32_t value) volatile
8728     {
8729         word0 = value;
8730         return *this;
8731     }
8732 #endif
8733 };
8734 
8735 // ofm_cblk_height_m1_r - OFM current block (height-1)
8736 struct ofm_cblk_height_m1_r
8737 {
8738 #ifndef __cplusplus
8739     union
8740     {
8741         struct
8742         {
8743             uint32_t value : 32; // 32-bit register value
8744         };
8745         uint32_t word;
8746     };
8747 #else
8748   private:
8749     uint32_t word0;
8750 
8751   public:
8752     CONSTEXPR ofm_cblk_height_m1_r() : word0(0) {}
8753     CONSTEXPR ofm_cblk_height_m1_r(uint32_t init) : word0(init) {}
8754     CONSTEXPR void operator=(uint32_t value)
8755     {
8756         word0 = value;
8757     }
8758     void operator=(uint32_t value) volatile
8759     {
8760         word0 = value;
8761     }
8762     CONSTEXPR operator uint32_t()
8763     {
8764         return word0;
8765     }
8766     operator uint32_t() volatile
8767     {
8768         return word0;
8769     }
8770     ofm_cblk_height_m1_r copy() volatile
8771     {
8772         return *this;
8773     }
8774     CONSTEXPR uint32_t get_value() const
8775     {
8776         uint32_t value = word0;
8777         return value;
8778     }
8779     uint32_t get_value() const volatile
8780     {
8781         uint32_t value = word0;
8782         return value;
8783     }
8784     CONSTEXPR ofm_cblk_height_m1_r &set_value(uint32_t value)
8785     {
8786         word0 = value;
8787         return *this;
8788     }
8789     volatile ofm_cblk_height_m1_r &set_value(uint32_t value) volatile
8790     {
8791         word0 = value;
8792         return *this;
8793     }
8794 #endif
8795 };
8796 
8797 // ofm_cblk_depth_m1_r - OFM current block (depth-1)
8798 struct ofm_cblk_depth_m1_r
8799 {
8800 #ifndef __cplusplus
8801     union
8802     {
8803         struct
8804         {
8805             uint32_t value : 32; // 32-bit register value
8806         };
8807         uint32_t word;
8808     };
8809 #else
8810   private:
8811     uint32_t word0;
8812 
8813   public:
8814     CONSTEXPR ofm_cblk_depth_m1_r() : word0(0) {}
8815     CONSTEXPR ofm_cblk_depth_m1_r(uint32_t init) : word0(init) {}
8816     CONSTEXPR void operator=(uint32_t value)
8817     {
8818         word0 = value;
8819     }
8820     void operator=(uint32_t value) volatile
8821     {
8822         word0 = value;
8823     }
8824     CONSTEXPR operator uint32_t()
8825     {
8826         return word0;
8827     }
8828     operator uint32_t() volatile
8829     {
8830         return word0;
8831     }
8832     ofm_cblk_depth_m1_r copy() volatile
8833     {
8834         return *this;
8835     }
8836     CONSTEXPR uint32_t get_value() const
8837     {
8838         uint32_t value = word0;
8839         return value;
8840     }
8841     uint32_t get_value() const volatile
8842     {
8843         uint32_t value = word0;
8844         return value;
8845     }
8846     CONSTEXPR ofm_cblk_depth_m1_r &set_value(uint32_t value)
8847     {
8848         word0 = value;
8849         return *this;
8850     }
8851     volatile ofm_cblk_depth_m1_r &set_value(uint32_t value) volatile
8852     {
8853         word0 = value;
8854         return *this;
8855     }
8856 #endif
8857 };
8858 
8859 // ifm_cblk_depth_m1_r - IFM current block (depth-1)
8860 struct ifm_cblk_depth_m1_r
8861 {
8862 #ifndef __cplusplus
8863     union
8864     {
8865         struct
8866         {
8867             uint32_t value : 32; // 32-bit register value
8868         };
8869         uint32_t word;
8870     };
8871 #else
8872   private:
8873     uint32_t word0;
8874 
8875   public:
8876     CONSTEXPR ifm_cblk_depth_m1_r() : word0(0) {}
8877     CONSTEXPR ifm_cblk_depth_m1_r(uint32_t init) : word0(init) {}
8878     CONSTEXPR void operator=(uint32_t value)
8879     {
8880         word0 = value;
8881     }
8882     void operator=(uint32_t value) volatile
8883     {
8884         word0 = value;
8885     }
8886     CONSTEXPR operator uint32_t()
8887     {
8888         return word0;
8889     }
8890     operator uint32_t() volatile
8891     {
8892         return word0;
8893     }
8894     ifm_cblk_depth_m1_r copy() volatile
8895     {
8896         return *this;
8897     }
8898     CONSTEXPR uint32_t get_value() const
8899     {
8900         uint32_t value = word0;
8901         return value;
8902     }
8903     uint32_t get_value() const volatile
8904     {
8905         uint32_t value = word0;
8906         return value;
8907     }
8908     CONSTEXPR ifm_cblk_depth_m1_r &set_value(uint32_t value)
8909     {
8910         word0 = value;
8911         return *this;
8912     }
8913     volatile ifm_cblk_depth_m1_r &set_value(uint32_t value) volatile
8914     {
8915         word0 = value;
8916         return *this;
8917     }
8918 #endif
8919 };
8920 
8921 // ofm_x_r - Block X coordinate in OFM
8922 struct ofm_x_r
8923 {
8924 #ifndef __cplusplus
8925     union
8926     {
8927         struct
8928         {
8929             uint32_t value : 32; // 32-bit register value
8930         };
8931         uint32_t word;
8932     };
8933 #else
8934   private:
8935     uint32_t word0;
8936 
8937   public:
8938     CONSTEXPR ofm_x_r() : word0(0) {}
8939     CONSTEXPR ofm_x_r(uint32_t init) : word0(init) {}
8940     CONSTEXPR void operator=(uint32_t value)
8941     {
8942         word0 = value;
8943     }
8944     void operator=(uint32_t value) volatile
8945     {
8946         word0 = value;
8947     }
8948     CONSTEXPR operator uint32_t()
8949     {
8950         return word0;
8951     }
8952     operator uint32_t() volatile
8953     {
8954         return word0;
8955     }
8956     ofm_x_r copy() volatile
8957     {
8958         return *this;
8959     }
8960     CONSTEXPR uint32_t get_value() const
8961     {
8962         uint32_t value = word0;
8963         return value;
8964     }
8965     uint32_t get_value() const volatile
8966     {
8967         uint32_t value = word0;
8968         return value;
8969     }
8970     CONSTEXPR ofm_x_r &set_value(uint32_t value)
8971     {
8972         word0 = value;
8973         return *this;
8974     }
8975     volatile ofm_x_r &set_value(uint32_t value) volatile
8976     {
8977         word0 = value;
8978         return *this;
8979     }
8980 #endif
8981 };
8982 
8983 // ofm_y_r - Block Y coordinate in OFM
8984 struct ofm_y_r
8985 {
8986 #ifndef __cplusplus
8987     union
8988     {
8989         struct
8990         {
8991             uint32_t value : 32; // 32-bit register value
8992         };
8993         uint32_t word;
8994     };
8995 #else
8996   private:
8997     uint32_t word0;
8998 
8999   public:
9000     CONSTEXPR ofm_y_r() : word0(0) {}
9001     CONSTEXPR ofm_y_r(uint32_t init) : word0(init) {}
9002     CONSTEXPR void operator=(uint32_t value)
9003     {
9004         word0 = value;
9005     }
9006     void operator=(uint32_t value) volatile
9007     {
9008         word0 = value;
9009     }
9010     CONSTEXPR operator uint32_t()
9011     {
9012         return word0;
9013     }
9014     operator uint32_t() volatile
9015     {
9016         return word0;
9017     }
9018     ofm_y_r copy() volatile
9019     {
9020         return *this;
9021     }
9022     CONSTEXPR uint32_t get_value() const
9023     {
9024         uint32_t value = word0;
9025         return value;
9026     }
9027     uint32_t get_value() const volatile
9028     {
9029         uint32_t value = word0;
9030         return value;
9031     }
9032     CONSTEXPR ofm_y_r &set_value(uint32_t value)
9033     {
9034         word0 = value;
9035         return *this;
9036     }
9037     volatile ofm_y_r &set_value(uint32_t value) volatile
9038     {
9039         word0 = value;
9040         return *this;
9041     }
9042 #endif
9043 };
9044 
9045 // ofm_z_r - Block Z (channel) coordinate in OFM
9046 struct ofm_z_r
9047 {
9048 #ifndef __cplusplus
9049     union
9050     {
9051         struct
9052         {
9053             uint32_t value : 32; // 32-bit register value
9054         };
9055         uint32_t word;
9056     };
9057 #else
9058   private:
9059     uint32_t word0;
9060 
9061   public:
9062     CONSTEXPR ofm_z_r() : word0(0) {}
9063     CONSTEXPR ofm_z_r(uint32_t init) : word0(init) {}
9064     CONSTEXPR void operator=(uint32_t value)
9065     {
9066         word0 = value;
9067     }
9068     void operator=(uint32_t value) volatile
9069     {
9070         word0 = value;
9071     }
9072     CONSTEXPR operator uint32_t()
9073     {
9074         return word0;
9075     }
9076     operator uint32_t() volatile
9077     {
9078         return word0;
9079     }
9080     ofm_z_r copy() volatile
9081     {
9082         return *this;
9083     }
9084     CONSTEXPR uint32_t get_value() const
9085     {
9086         uint32_t value = word0;
9087         return value;
9088     }
9089     uint32_t get_value() const volatile
9090     {
9091         uint32_t value = word0;
9092         return value;
9093     }
9094     CONSTEXPR ofm_z_r &set_value(uint32_t value)
9095     {
9096         word0 = value;
9097         return *this;
9098     }
9099     volatile ofm_z_r &set_value(uint32_t value) volatile
9100     {
9101         word0 = value;
9102         return *this;
9103     }
9104 #endif
9105 };
9106 
9107 // ifm_z_r - Block Z (channel) coordinate in IFM
9108 struct ifm_z_r
9109 {
9110 #ifndef __cplusplus
9111     union
9112     {
9113         struct
9114         {
9115             uint32_t value : 32; // 32-bit register value
9116         };
9117         uint32_t word;
9118     };
9119 #else
9120   private:
9121     uint32_t word0;
9122 
9123   public:
9124     CONSTEXPR ifm_z_r() : word0(0) {}
9125     CONSTEXPR ifm_z_r(uint32_t init) : word0(init) {}
9126     CONSTEXPR void operator=(uint32_t value)
9127     {
9128         word0 = value;
9129     }
9130     void operator=(uint32_t value) volatile
9131     {
9132         word0 = value;
9133     }
9134     CONSTEXPR operator uint32_t()
9135     {
9136         return word0;
9137     }
9138     operator uint32_t() volatile
9139     {
9140         return word0;
9141     }
9142     ifm_z_r copy() volatile
9143     {
9144         return *this;
9145     }
9146     CONSTEXPR uint32_t get_value() const
9147     {
9148         uint32_t value = word0;
9149         return value;
9150     }
9151     uint32_t get_value() const volatile
9152     {
9153         uint32_t value = word0;
9154         return value;
9155     }
9156     CONSTEXPR ifm_z_r &set_value(uint32_t value)
9157     {
9158         word0 = value;
9159         return *this;
9160     }
9161     volatile ifm_z_r &set_value(uint32_t value) volatile
9162     {
9163         word0 = value;
9164         return *this;
9165     }
9166 #endif
9167 };
9168 
9169 // pad_top_r - Block top pad
9170 struct pad_top_r
9171 {
9172 #ifndef __cplusplus
9173     union
9174     {
9175         struct
9176         {
9177             uint32_t value : 32; // 32-bit register value
9178         };
9179         uint32_t word;
9180     };
9181 #else
9182   private:
9183     uint32_t word0;
9184 
9185   public:
9186     CONSTEXPR pad_top_r() : word0(0) {}
9187     CONSTEXPR pad_top_r(uint32_t init) : word0(init) {}
9188     CONSTEXPR void operator=(uint32_t value)
9189     {
9190         word0 = value;
9191     }
9192     void operator=(uint32_t value) volatile
9193     {
9194         word0 = value;
9195     }
9196     CONSTEXPR operator uint32_t()
9197     {
9198         return word0;
9199     }
9200     operator uint32_t() volatile
9201     {
9202         return word0;
9203     }
9204     pad_top_r copy() volatile
9205     {
9206         return *this;
9207     }
9208     CONSTEXPR uint32_t get_value() const
9209     {
9210         uint32_t value = word0;
9211         return value;
9212     }
9213     uint32_t get_value() const volatile
9214     {
9215         uint32_t value = word0;
9216         return value;
9217     }
9218     CONSTEXPR pad_top_r &set_value(uint32_t value)
9219     {
9220         word0 = value;
9221         return *this;
9222     }
9223     volatile pad_top_r &set_value(uint32_t value) volatile
9224     {
9225         word0 = value;
9226         return *this;
9227     }
9228 #endif
9229 };
9230 
9231 // pad_left_r - Block left pad
9232 struct pad_left_r
9233 {
9234 #ifndef __cplusplus
9235     union
9236     {
9237         struct
9238         {
9239             uint32_t value : 32; // 32-bit register value
9240         };
9241         uint32_t word;
9242     };
9243 #else
9244   private:
9245     uint32_t word0;
9246 
9247   public:
9248     CONSTEXPR pad_left_r() : word0(0) {}
9249     CONSTEXPR pad_left_r(uint32_t init) : word0(init) {}
9250     CONSTEXPR void operator=(uint32_t value)
9251     {
9252         word0 = value;
9253     }
9254     void operator=(uint32_t value) volatile
9255     {
9256         word0 = value;
9257     }
9258     CONSTEXPR operator uint32_t()
9259     {
9260         return word0;
9261     }
9262     operator uint32_t() volatile
9263     {
9264         return word0;
9265     }
9266     pad_left_r copy() volatile
9267     {
9268         return *this;
9269     }
9270     CONSTEXPR uint32_t get_value() const
9271     {
9272         uint32_t value = word0;
9273         return value;
9274     }
9275     uint32_t get_value() const volatile
9276     {
9277         uint32_t value = word0;
9278         return value;
9279     }
9280     CONSTEXPR pad_left_r &set_value(uint32_t value)
9281     {
9282         word0 = value;
9283         return *this;
9284     }
9285     volatile pad_left_r &set_value(uint32_t value) volatile
9286     {
9287         word0 = value;
9288         return *this;
9289     }
9290 #endif
9291 };
9292 
9293 // ifm_cblk_width_r - IFM current block derived width
9294 struct ifm_cblk_width_r
9295 {
9296 #ifndef __cplusplus
9297     union
9298     {
9299         struct
9300         {
9301             uint32_t value : 32; // 32-bit register value
9302         };
9303         uint32_t word;
9304     };
9305 #else
9306   private:
9307     uint32_t word0;
9308 
9309   public:
9310     CONSTEXPR ifm_cblk_width_r() : word0(0) {}
9311     CONSTEXPR ifm_cblk_width_r(uint32_t init) : word0(init) {}
9312     CONSTEXPR void operator=(uint32_t value)
9313     {
9314         word0 = value;
9315     }
9316     void operator=(uint32_t value) volatile
9317     {
9318         word0 = value;
9319     }
9320     CONSTEXPR operator uint32_t()
9321     {
9322         return word0;
9323     }
9324     operator uint32_t() volatile
9325     {
9326         return word0;
9327     }
9328     ifm_cblk_width_r copy() volatile
9329     {
9330         return *this;
9331     }
9332     CONSTEXPR uint32_t get_value() const
9333     {
9334         uint32_t value = word0;
9335         return value;
9336     }
9337     uint32_t get_value() const volatile
9338     {
9339         uint32_t value = word0;
9340         return value;
9341     }
9342     CONSTEXPR ifm_cblk_width_r &set_value(uint32_t value)
9343     {
9344         word0 = value;
9345         return *this;
9346     }
9347     volatile ifm_cblk_width_r &set_value(uint32_t value) volatile
9348     {
9349         word0 = value;
9350         return *this;
9351     }
9352 #endif
9353 };
9354 
9355 // ifm_cblk_height_r - IFM current block derived height
9356 struct ifm_cblk_height_r
9357 {
9358 #ifndef __cplusplus
9359     union
9360     {
9361         struct
9362         {
9363             uint32_t value : 32; // 32-bit register value
9364         };
9365         uint32_t word;
9366     };
9367 #else
9368   private:
9369     uint32_t word0;
9370 
9371   public:
9372     CONSTEXPR ifm_cblk_height_r() : word0(0) {}
9373     CONSTEXPR ifm_cblk_height_r(uint32_t init) : word0(init) {}
9374     CONSTEXPR void operator=(uint32_t value)
9375     {
9376         word0 = value;
9377     }
9378     void operator=(uint32_t value) volatile
9379     {
9380         word0 = value;
9381     }
9382     CONSTEXPR operator uint32_t()
9383     {
9384         return word0;
9385     }
9386     operator uint32_t() volatile
9387     {
9388         return word0;
9389     }
9390     ifm_cblk_height_r copy() volatile
9391     {
9392         return *this;
9393     }
9394     CONSTEXPR uint32_t get_value() const
9395     {
9396         uint32_t value = word0;
9397         return value;
9398     }
9399     uint32_t get_value() const volatile
9400     {
9401         uint32_t value = word0;
9402         return value;
9403     }
9404     CONSTEXPR ifm_cblk_height_r &set_value(uint32_t value)
9405     {
9406         word0 = value;
9407         return *this;
9408     }
9409     volatile ifm_cblk_height_r &set_value(uint32_t value) volatile
9410     {
9411         word0 = value;
9412         return *this;
9413     }
9414 #endif
9415 };
9416 
9417 // dma_ifm_src_r - DMA IFM channel source position on AXI
9418 struct dma_ifm_src_r
9419 {
9420 #ifndef __cplusplus
9421     union
9422     {
9423         struct
9424         {
9425             uint32_t offset_LO : 32; // Offset - LSB
9426             uint32_t offset_HI : 8;  // Offset - MSB
9427             uint32_t reserved0 : 24;
9428         };
9429         uint32_t word[2];
9430     };
9431 #else
9432   private:
9433     uint32_t word0;
9434     uint32_t word1;
9435 
9436   public:
9437     CONSTEXPR dma_ifm_src_r() : word0(0), word1(0) {}
9438     CONSTEXPR dma_ifm_src_r(uint64_t init) :
9439         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9440         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9441     {
9442     }
9443     CONSTEXPR void operator=(uint64_t value)
9444     {
9445         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9446         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9447     }
9448     void operator=(uint64_t value) volatile
9449     {
9450         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9451         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9452     }
9453     CONSTEXPR operator uint64_t()
9454     {
9455         return (static_cast<uint64_t>(word1) << 32) | word0;
9456     }
9457     operator uint64_t() volatile
9458     {
9459         return (static_cast<uint64_t>(word1) << 32) | word0;
9460     }
9461     dma_ifm_src_r copy() volatile
9462     {
9463         return *this;
9464     }
9465 #endif
9466 };
9467 
9468 // dma_ifm_dst_r - DMA IFM channel destination position in SHRAM
9469 struct dma_ifm_dst_r
9470 {
9471 #ifndef __cplusplus
9472     union
9473     {
9474         struct
9475         {
9476             uint32_t value : 32; // 32-bit register value
9477         };
9478         uint32_t word;
9479     };
9480 #else
9481   private:
9482     uint32_t word0;
9483 
9484   public:
9485     CONSTEXPR dma_ifm_dst_r() : word0(0) {}
9486     CONSTEXPR dma_ifm_dst_r(uint32_t init) : word0(init) {}
9487     CONSTEXPR void operator=(uint32_t value)
9488     {
9489         word0 = value;
9490     }
9491     void operator=(uint32_t value) volatile
9492     {
9493         word0 = value;
9494     }
9495     CONSTEXPR operator uint32_t()
9496     {
9497         return word0;
9498     }
9499     operator uint32_t() volatile
9500     {
9501         return word0;
9502     }
9503     dma_ifm_dst_r copy() volatile
9504     {
9505         return *this;
9506     }
9507     CONSTEXPR uint32_t get_value() const
9508     {
9509         uint32_t value = word0;
9510         return value;
9511     }
9512     uint32_t get_value() const volatile
9513     {
9514         uint32_t value = word0;
9515         return value;
9516     }
9517     CONSTEXPR dma_ifm_dst_r &set_value(uint32_t value)
9518     {
9519         word0 = value;
9520         return *this;
9521     }
9522     volatile dma_ifm_dst_r &set_value(uint32_t value) volatile
9523     {
9524         word0 = value;
9525         return *this;
9526     }
9527 #endif
9528 };
9529 
9530 // dma_ofm_src_r - DMA OFM channel source position in SHRAM
9531 struct dma_ofm_src_r
9532 {
9533 #ifndef __cplusplus
9534     union
9535     {
9536         struct
9537         {
9538             uint32_t value : 32; // 32-bit register value
9539         };
9540         uint32_t word;
9541     };
9542 #else
9543   private:
9544     uint32_t word0;
9545 
9546   public:
9547     CONSTEXPR dma_ofm_src_r() : word0(0) {}
9548     CONSTEXPR dma_ofm_src_r(uint32_t init) : word0(init) {}
9549     CONSTEXPR void operator=(uint32_t value)
9550     {
9551         word0 = value;
9552     }
9553     void operator=(uint32_t value) volatile
9554     {
9555         word0 = value;
9556     }
9557     CONSTEXPR operator uint32_t()
9558     {
9559         return word0;
9560     }
9561     operator uint32_t() volatile
9562     {
9563         return word0;
9564     }
9565     dma_ofm_src_r copy() volatile
9566     {
9567         return *this;
9568     }
9569     CONSTEXPR uint32_t get_value() const
9570     {
9571         uint32_t value = word0;
9572         return value;
9573     }
9574     uint32_t get_value() const volatile
9575     {
9576         uint32_t value = word0;
9577         return value;
9578     }
9579     CONSTEXPR dma_ofm_src_r &set_value(uint32_t value)
9580     {
9581         word0 = value;
9582         return *this;
9583     }
9584     volatile dma_ofm_src_r &set_value(uint32_t value) volatile
9585     {
9586         word0 = value;
9587         return *this;
9588     }
9589 #endif
9590 };
9591 
9592 // dma_ofm_dst_r - DMA OFM channel destination position on AXI
9593 struct dma_ofm_dst_r
9594 {
9595 #ifndef __cplusplus
9596     union
9597     {
9598         struct
9599         {
9600             uint32_t offset_LO : 32; // Offset - LSB
9601             uint32_t offset_HI : 8;  // Offset - MSB
9602             uint32_t reserved0 : 24;
9603         };
9604         uint32_t word[2];
9605     };
9606 #else
9607   private:
9608     uint32_t word0;
9609     uint32_t word1;
9610 
9611   public:
9612     CONSTEXPR dma_ofm_dst_r() : word0(0), word1(0) {}
9613     CONSTEXPR dma_ofm_dst_r(uint64_t init) :
9614         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9615         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9616     {
9617     }
9618     CONSTEXPR void operator=(uint64_t value)
9619     {
9620         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9621         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9622     }
9623     void operator=(uint64_t value) volatile
9624     {
9625         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9626         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9627     }
9628     CONSTEXPR operator uint64_t()
9629     {
9630         return (static_cast<uint64_t>(word1) << 32) | word0;
9631     }
9632     operator uint64_t() volatile
9633     {
9634         return (static_cast<uint64_t>(word1) << 32) | word0;
9635     }
9636     dma_ofm_dst_r copy() volatile
9637     {
9638         return *this;
9639     }
9640 #endif
9641 };
9642 
9643 // dma_weight_src_r - DMA weight channel source position on AXI
9644 struct dma_weight_src_r
9645 {
9646 #ifndef __cplusplus
9647     union
9648     {
9649         struct
9650         {
9651             uint32_t offset_LO : 32; // Offset - LSB
9652             uint32_t offset_HI : 8;  // Offset - MSB
9653             uint32_t reserved0 : 24;
9654         };
9655         uint32_t word[2];
9656     };
9657 #else
9658   private:
9659     uint32_t word0;
9660     uint32_t word1;
9661 
9662   public:
9663     CONSTEXPR dma_weight_src_r() : word0(0), word1(0) {}
9664     CONSTEXPR dma_weight_src_r(uint64_t init) :
9665         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9666         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9667     {
9668     }
9669     CONSTEXPR void operator=(uint64_t value)
9670     {
9671         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9672         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9673     }
9674     void operator=(uint64_t value) volatile
9675     {
9676         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9677         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9678     }
9679     CONSTEXPR operator uint64_t()
9680     {
9681         return (static_cast<uint64_t>(word1) << 32) | word0;
9682     }
9683     operator uint64_t() volatile
9684     {
9685         return (static_cast<uint64_t>(word1) << 32) | word0;
9686     }
9687     dma_weight_src_r copy() volatile
9688     {
9689         return *this;
9690     }
9691 #endif
9692 };
9693 
9694 // dma_cmd_src_r - DMA command channel source position on AXI
9695 struct dma_cmd_src_r
9696 {
9697 #ifndef __cplusplus
9698     union
9699     {
9700         struct
9701         {
9702             uint32_t offset_LO : 32; // Offset - LSB
9703             uint32_t offset_HI : 8;  // Offset - MSB
9704             uint32_t reserved0 : 24;
9705         };
9706         uint32_t word[2];
9707     };
9708 #else
9709   private:
9710     uint32_t word0;
9711     uint32_t word1;
9712 
9713   public:
9714     CONSTEXPR dma_cmd_src_r() : word0(0), word1(0) {}
9715     CONSTEXPR dma_cmd_src_r(uint64_t init) :
9716         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9717         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9718     {
9719     }
9720     CONSTEXPR void operator=(uint64_t value)
9721     {
9722         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9723         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9724     }
9725     void operator=(uint64_t value) volatile
9726     {
9727         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9728         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9729     }
9730     CONSTEXPR operator uint64_t()
9731     {
9732         return (static_cast<uint64_t>(word1) << 32) | word0;
9733     }
9734     operator uint64_t() volatile
9735     {
9736         return (static_cast<uint64_t>(word1) << 32) | word0;
9737     }
9738     dma_cmd_src_r copy() volatile
9739     {
9740         return *this;
9741     }
9742 #endif
9743 };
9744 
9745 // dma_cmd_size_r - DMA command channel number of bytes buffered
9746 struct dma_cmd_size_r
9747 {
9748 #ifndef __cplusplus
9749     union
9750     {
9751         struct
9752         {
9753             uint32_t value : 32; // 32-bit register value
9754         };
9755         uint32_t word;
9756     };
9757 #else
9758   private:
9759     uint32_t word0;
9760 
9761   public:
9762     CONSTEXPR dma_cmd_size_r() : word0(0) {}
9763     CONSTEXPR dma_cmd_size_r(uint32_t init) : word0(init) {}
9764     CONSTEXPR void operator=(uint32_t value)
9765     {
9766         word0 = value;
9767     }
9768     void operator=(uint32_t value) volatile
9769     {
9770         word0 = value;
9771     }
9772     CONSTEXPR operator uint32_t()
9773     {
9774         return word0;
9775     }
9776     operator uint32_t() volatile
9777     {
9778         return word0;
9779     }
9780     dma_cmd_size_r copy() volatile
9781     {
9782         return *this;
9783     }
9784     CONSTEXPR uint32_t get_value() const
9785     {
9786         uint32_t value = word0;
9787         return value;
9788     }
9789     uint32_t get_value() const volatile
9790     {
9791         uint32_t value = word0;
9792         return value;
9793     }
9794     CONSTEXPR dma_cmd_size_r &set_value(uint32_t value)
9795     {
9796         word0 = value;
9797         return *this;
9798     }
9799     volatile dma_cmd_size_r &set_value(uint32_t value) volatile
9800     {
9801         word0 = value;
9802         return *this;
9803     }
9804 #endif
9805 };
9806 
9807 // dma_m2m_src_r - DMA memory to memory source position on AXI
9808 struct dma_m2m_src_r
9809 {
9810 #ifndef __cplusplus
9811     union
9812     {
9813         struct
9814         {
9815             uint32_t offset_LO : 32; // Offset - LSB
9816             uint32_t offset_HI : 8;  // Offset - MSB
9817             uint32_t reserved0 : 24;
9818         };
9819         uint32_t word[2];
9820     };
9821 #else
9822   private:
9823     uint32_t word0;
9824     uint32_t word1;
9825 
9826   public:
9827     CONSTEXPR dma_m2m_src_r() : word0(0), word1(0) {}
9828     CONSTEXPR dma_m2m_src_r(uint64_t init) :
9829         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9830         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9831     {
9832     }
9833     CONSTEXPR void operator=(uint64_t value)
9834     {
9835         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9836         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9837     }
9838     void operator=(uint64_t value) volatile
9839     {
9840         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9841         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9842     }
9843     CONSTEXPR operator uint64_t()
9844     {
9845         return (static_cast<uint64_t>(word1) << 32) | word0;
9846     }
9847     operator uint64_t() volatile
9848     {
9849         return (static_cast<uint64_t>(word1) << 32) | word0;
9850     }
9851     dma_m2m_src_r copy() volatile
9852     {
9853         return *this;
9854     }
9855 #endif
9856 };
9857 
9858 // dma_m2m_dst_r - DMA memory to memory destination position on AXI
9859 struct dma_m2m_dst_r
9860 {
9861 #ifndef __cplusplus
9862     union
9863     {
9864         struct
9865         {
9866             uint32_t offset_LO : 32; // Offset - LSB
9867             uint32_t offset_HI : 8;  // Offset - MSB
9868             uint32_t reserved0 : 24;
9869         };
9870         uint32_t word[2];
9871     };
9872 #else
9873   private:
9874     uint32_t word0;
9875     uint32_t word1;
9876 
9877   public:
9878     CONSTEXPR dma_m2m_dst_r() : word0(0), word1(0) {}
9879     CONSTEXPR dma_m2m_dst_r(uint64_t init) :
9880         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9881         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9882     {
9883     }
9884     CONSTEXPR void operator=(uint64_t value)
9885     {
9886         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9887         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9888     }
9889     void operator=(uint64_t value) volatile
9890     {
9891         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9892         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9893     }
9894     CONSTEXPR operator uint64_t()
9895     {
9896         return (static_cast<uint64_t>(word1) << 32) | word0;
9897     }
9898     operator uint64_t() volatile
9899     {
9900         return (static_cast<uint64_t>(word1) << 32) | word0;
9901     }
9902     dma_m2m_dst_r copy() volatile
9903     {
9904         return *this;
9905     }
9906 #endif
9907 };
9908 
9909 // current_qread_r - QREAD position being issued (rather than completed)
9910 struct current_qread_r
9911 {
9912 #ifndef __cplusplus
9913     union
9914     {
9915         struct
9916         {
9917             uint32_t value : 32; // 32-bit register value
9918         };
9919         uint32_t word;
9920     };
9921 #else
9922   private:
9923     uint32_t word0;
9924 
9925   public:
9926     CONSTEXPR current_qread_r() : word0(0) {}
9927     CONSTEXPR current_qread_r(uint32_t init) : word0(init) {}
9928     CONSTEXPR void operator=(uint32_t value)
9929     {
9930         word0 = value;
9931     }
9932     void operator=(uint32_t value) volatile
9933     {
9934         word0 = value;
9935     }
9936     CONSTEXPR operator uint32_t()
9937     {
9938         return word0;
9939     }
9940     operator uint32_t() volatile
9941     {
9942         return word0;
9943     }
9944     current_qread_r copy() volatile
9945     {
9946         return *this;
9947     }
9948     CONSTEXPR uint32_t get_value() const
9949     {
9950         uint32_t value = word0;
9951         return value;
9952     }
9953     uint32_t get_value() const volatile
9954     {
9955         uint32_t value = word0;
9956         return value;
9957     }
9958     CONSTEXPR current_qread_r &set_value(uint32_t value)
9959     {
9960         word0 = value;
9961         return *this;
9962     }
9963     volatile current_qread_r &set_value(uint32_t value) volatile
9964     {
9965         word0 = value;
9966         return *this;
9967     }
9968 #endif
9969 };
9970 
9971 // dma_scale_src_r - DMA scale and bias channel source position on AXI
9972 struct dma_scale_src_r
9973 {
9974 #ifndef __cplusplus
9975     union
9976     {
9977         struct
9978         {
9979             uint32_t offset_LO : 32; // Offset - LSB
9980             uint32_t offset_HI : 8;  // Offset - MSB
9981             uint32_t reserved0 : 24;
9982         };
9983         uint32_t word[2];
9984     };
9985 #else
9986   private:
9987     uint32_t word0;
9988     uint32_t word1;
9989 
9990   public:
9991     CONSTEXPR dma_scale_src_r() : word0(0), word1(0) {}
9992     CONSTEXPR dma_scale_src_r(uint64_t init) :
9993         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9994         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9995     {
9996     }
9997     CONSTEXPR void operator=(uint64_t value)
9998     {
9999         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
10000         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
10001     }
10002     void operator=(uint64_t value) volatile
10003     {
10004         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
10005         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
10006     }
10007     CONSTEXPR operator uint64_t()
10008     {
10009         return (static_cast<uint64_t>(word1) << 32) | word0;
10010     }
10011     operator uint64_t() volatile
10012     {
10013         return (static_cast<uint64_t>(word1) << 32) | word0;
10014     }
10015     dma_scale_src_r copy() volatile
10016     {
10017         return *this;
10018     }
10019 #endif
10020 };
10021 
10022 // current_block_r - 0-3. Current block bank being executed by the TSU or last one executed if TSU is stopped
10023 struct current_block_r
10024 {
10025 #ifndef __cplusplus
10026     union
10027     {
10028         struct
10029         {
10030             uint32_t value : 32; // 32-bit register value
10031         };
10032         uint32_t word;
10033     };
10034 #else
10035   private:
10036     uint32_t word0;
10037 
10038   public:
10039     CONSTEXPR current_block_r() : word0(0) {}
10040     CONSTEXPR current_block_r(uint32_t init) : word0(init) {}
10041     CONSTEXPR void operator=(uint32_t value)
10042     {
10043         word0 = value;
10044     }
10045     void operator=(uint32_t value) volatile
10046     {
10047         word0 = value;
10048     }
10049     CONSTEXPR operator uint32_t()
10050     {
10051         return word0;
10052     }
10053     operator uint32_t() volatile
10054     {
10055         return word0;
10056     }
10057     current_block_r copy() volatile
10058     {
10059         return *this;
10060     }
10061     CONSTEXPR uint32_t get_value() const
10062     {
10063         uint32_t value = word0;
10064         return value;
10065     }
10066     uint32_t get_value() const volatile
10067     {
10068         uint32_t value = word0;
10069         return value;
10070     }
10071     CONSTEXPR current_block_r &set_value(uint32_t value)
10072     {
10073         word0 = value;
10074         return *this;
10075     }
10076     volatile current_block_r &set_value(uint32_t value) volatile
10077     {
10078         word0 = value;
10079         return *this;
10080     }
10081 #endif
10082 };
10083 
10084 // current_op_r - Current NPU OP command being executed by the TSU
10085 struct current_op_r
10086 {
10087 #ifndef __cplusplus
10088     union
10089     {
10090         struct
10091         {
10092             uint32_t value : 32; // 32-bit register value
10093         };
10094         uint32_t word;
10095     };
10096 #else
10097   private:
10098     uint32_t word0;
10099 
10100   public:
10101     CONSTEXPR current_op_r() : word0(0) {}
10102     CONSTEXPR current_op_r(uint32_t init) : word0(init) {}
10103     CONSTEXPR void operator=(uint32_t value)
10104     {
10105         word0 = value;
10106     }
10107     void operator=(uint32_t value) volatile
10108     {
10109         word0 = value;
10110     }
10111     CONSTEXPR operator uint32_t()
10112     {
10113         return word0;
10114     }
10115     operator uint32_t() volatile
10116     {
10117         return word0;
10118     }
10119     current_op_r copy() volatile
10120     {
10121         return *this;
10122     }
10123     CONSTEXPR uint32_t get_value() const
10124     {
10125         uint32_t value = word0;
10126         return value;
10127     }
10128     uint32_t get_value() const volatile
10129     {
10130         uint32_t value = word0;
10131         return value;
10132     }
10133     CONSTEXPR current_op_r &set_value(uint32_t value)
10134     {
10135         word0 = value;
10136         return *this;
10137     }
10138     volatile current_op_r &set_value(uint32_t value) volatile
10139     {
10140         word0 = value;
10141         return *this;
10142     }
10143 #endif
10144 };
10145 
10146 // current_cmd_r - Current 32-bit command being parsed by the command stream parser
10147 struct current_cmd_r
10148 {
10149 #ifndef __cplusplus
10150     union
10151     {
10152         struct
10153         {
10154             uint32_t value : 32; // 32-bit register value
10155         };
10156         uint32_t word;
10157     };
10158 #else
10159   private:
10160     uint32_t word0;
10161 
10162   public:
10163     CONSTEXPR current_cmd_r() : word0(0) {}
10164     CONSTEXPR current_cmd_r(uint32_t init) : word0(init) {}
10165     CONSTEXPR void operator=(uint32_t value)
10166     {
10167         word0 = value;
10168     }
10169     void operator=(uint32_t value) volatile
10170     {
10171         word0 = value;
10172     }
10173     CONSTEXPR operator uint32_t()
10174     {
10175         return word0;
10176     }
10177     operator uint32_t() volatile
10178     {
10179         return word0;
10180     }
10181     current_cmd_r copy() volatile
10182     {
10183         return *this;
10184     }
10185     CONSTEXPR uint32_t get_value() const
10186     {
10187         uint32_t value = word0;
10188         return value;
10189     }
10190     uint32_t get_value() const volatile
10191     {
10192         uint32_t value = word0;
10193         return value;
10194     }
10195     CONSTEXPR current_cmd_r &set_value(uint32_t value)
10196     {
10197         word0 = value;
10198         return *this;
10199     }
10200     volatile current_cmd_r &set_value(uint32_t value) volatile
10201     {
10202         word0 = value;
10203         return *this;
10204     }
10205 #endif
10206 };
10207 
10208 // pmevcntr_r - Performance monitor event 0 count register
10209 struct pmevcntr_r
10210 {
10211 #ifndef __cplusplus
10212     union
10213     {
10214         struct
10215         {
10216             uint32_t count : 32; // Count word
10217         };
10218         uint32_t word;
10219     };
10220 #else
10221   private:
10222     uint32_t word0;
10223 
10224   public:
10225     CONSTEXPR pmevcntr_r() : word0(0) {}
10226     CONSTEXPR pmevcntr_r(uint32_t init) : word0(init) {}
10227     CONSTEXPR void operator=(uint32_t value)
10228     {
10229         word0 = value;
10230     }
10231     void operator=(uint32_t value) volatile
10232     {
10233         word0 = value;
10234     }
10235     CONSTEXPR operator uint32_t()
10236     {
10237         return word0;
10238     }
10239     operator uint32_t() volatile
10240     {
10241         return word0;
10242     }
10243     pmevcntr_r copy() volatile
10244     {
10245         return *this;
10246     }
10247     CONSTEXPR uint32_t get_count() const
10248     {
10249         uint32_t value = word0;
10250         return value;
10251     }
10252     uint32_t get_count() const volatile
10253     {
10254         uint32_t value = word0;
10255         return value;
10256     }
10257     CONSTEXPR pmevcntr_r &set_count(uint32_t value)
10258     {
10259         word0 = value;
10260         return *this;
10261     }
10262     volatile pmevcntr_r &set_count(uint32_t value) volatile
10263     {
10264         word0 = value;
10265         return *this;
10266     }
10267 #endif
10268 };
10269 
10270 // pmevtyper_r - Performance monitor event type register 0
10271 struct pmevtyper_r
10272 {
10273 #ifndef __cplusplus
10274     union
10275     {
10276         struct
10277         {
10278             uint32_t EV_TYPE : 10; // Event Type
10279             uint32_t reserved0 : 22;
10280         };
10281         uint32_t word;
10282     };
10283 #else
10284   private:
10285     uint32_t word0;
10286 
10287   public:
10288     CONSTEXPR pmevtyper_r() : word0(0) {}
10289     CONSTEXPR pmevtyper_r(uint32_t init) : word0(init) {}
10290     CONSTEXPR void operator=(uint32_t value)
10291     {
10292         word0 = value;
10293     }
10294     void operator=(uint32_t value) volatile
10295     {
10296         word0 = value;
10297     }
10298     CONSTEXPR operator uint32_t()
10299     {
10300         return word0;
10301     }
10302     operator uint32_t() volatile
10303     {
10304         return word0;
10305     }
10306     pmevtyper_r copy() volatile
10307     {
10308         return *this;
10309     }
10310     CONSTEXPR NPU_NAMESPACE::pmu_event get_EV_TYPE() const
10311     {
10312         NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 0));
10313         return value;
10314     }
10315     NPU_NAMESPACE::pmu_event get_EV_TYPE() const volatile
10316     {
10317         NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 0));
10318         return value;
10319     }
10320     CONSTEXPR pmevtyper_r &set_EV_TYPE(NPU_NAMESPACE::pmu_event value)
10321     {
10322         word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 0);
10323         return *this;
10324     }
10325     volatile pmevtyper_r &set_EV_TYPE(NPU_NAMESPACE::pmu_event value) volatile
10326     {
10327         word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 0);
10328         return *this;
10329     }
10330 #endif
10331 };
10332 
10333 // shared_buffer_r - Shared buffer debug access. Only valid in STOPPED state
10334 struct shared_buffer_r
10335 {
10336 #ifndef __cplusplus
10337     union
10338     {
10339         struct
10340         {
10341             uint32_t mem_word : 32; // Memory word
10342         };
10343         uint32_t word;
10344     };
10345 #else
10346   private:
10347     uint32_t word0;
10348 
10349   public:
10350     CONSTEXPR shared_buffer_r() : word0(0) {}
10351     CONSTEXPR shared_buffer_r(uint32_t init) : word0(init) {}
10352     CONSTEXPR void operator=(uint32_t value)
10353     {
10354         word0 = value;
10355     }
10356     void operator=(uint32_t value) volatile
10357     {
10358         word0 = value;
10359     }
10360     CONSTEXPR operator uint32_t()
10361     {
10362         return word0;
10363     }
10364     operator uint32_t() volatile
10365     {
10366         return word0;
10367     }
10368     shared_buffer_r copy() volatile
10369     {
10370         return *this;
10371     }
10372     CONSTEXPR uint32_t get_mem_word() const
10373     {
10374         uint32_t value = word0;
10375         return value;
10376     }
10377     uint32_t get_mem_word() const volatile
10378     {
10379         uint32_t value = word0;
10380         return value;
10381     }
10382     CONSTEXPR shared_buffer_r &set_mem_word(uint32_t value)
10383     {
10384         word0 = value;
10385         return *this;
10386     }
10387     volatile shared_buffer_r &set_mem_word(uint32_t value) volatile
10388     {
10389         word0 = value;
10390         return *this;
10391     }
10392 #endif
10393 };
10394 
10395 // ifm_pad_top_r - None
10396 struct ifm_pad_top_r
10397 {
10398 #ifndef __cplusplus
10399     union
10400     {
10401         struct
10402         {
10403             uint32_t value : 32; // 32-bit register value
10404         };
10405         uint32_t word;
10406     };
10407 #else
10408   private:
10409     uint32_t word0;
10410 
10411   public:
10412     CONSTEXPR ifm_pad_top_r() : word0(0) {}
10413     CONSTEXPR ifm_pad_top_r(uint32_t init) : word0(init) {}
10414     CONSTEXPR void operator=(uint32_t value)
10415     {
10416         word0 = value;
10417     }
10418     void operator=(uint32_t value) volatile
10419     {
10420         word0 = value;
10421     }
10422     CONSTEXPR operator uint32_t()
10423     {
10424         return word0;
10425     }
10426     operator uint32_t() volatile
10427     {
10428         return word0;
10429     }
10430     ifm_pad_top_r copy() volatile
10431     {
10432         return *this;
10433     }
10434     CONSTEXPR uint32_t get_value() const
10435     {
10436         uint32_t value = word0;
10437         return value;
10438     }
10439     uint32_t get_value() const volatile
10440     {
10441         uint32_t value = word0;
10442         return value;
10443     }
10444     CONSTEXPR ifm_pad_top_r &set_value(uint32_t value)
10445     {
10446         word0 = value;
10447         return *this;
10448     }
10449     volatile ifm_pad_top_r &set_value(uint32_t value) volatile
10450     {
10451         word0 = value;
10452         return *this;
10453     }
10454 #endif
10455 };
10456 
10457 // ifm_pad_left_r - None
10458 struct ifm_pad_left_r
10459 {
10460 #ifndef __cplusplus
10461     union
10462     {
10463         struct
10464         {
10465             uint32_t value : 32; // 32-bit register value
10466         };
10467         uint32_t word;
10468     };
10469 #else
10470   private:
10471     uint32_t word0;
10472 
10473   public:
10474     CONSTEXPR ifm_pad_left_r() : word0(0) {}
10475     CONSTEXPR ifm_pad_left_r(uint32_t init) : word0(init) {}
10476     CONSTEXPR void operator=(uint32_t value)
10477     {
10478         word0 = value;
10479     }
10480     void operator=(uint32_t value) volatile
10481     {
10482         word0 = value;
10483     }
10484     CONSTEXPR operator uint32_t()
10485     {
10486         return word0;
10487     }
10488     operator uint32_t() volatile
10489     {
10490         return word0;
10491     }
10492     ifm_pad_left_r copy() volatile
10493     {
10494         return *this;
10495     }
10496     CONSTEXPR uint32_t get_value() const
10497     {
10498         uint32_t value = word0;
10499         return value;
10500     }
10501     uint32_t get_value() const volatile
10502     {
10503         uint32_t value = word0;
10504         return value;
10505     }
10506     CONSTEXPR ifm_pad_left_r &set_value(uint32_t value)
10507     {
10508         word0 = value;
10509         return *this;
10510     }
10511     volatile ifm_pad_left_r &set_value(uint32_t value) volatile
10512     {
10513         word0 = value;
10514         return *this;
10515     }
10516 #endif
10517 };
10518 
10519 // ifm_pad_right_r - None
10520 struct ifm_pad_right_r
10521 {
10522 #ifndef __cplusplus
10523     union
10524     {
10525         struct
10526         {
10527             uint32_t value : 32; // 32-bit register value
10528         };
10529         uint32_t word;
10530     };
10531 #else
10532   private:
10533     uint32_t word0;
10534 
10535   public:
10536     CONSTEXPR ifm_pad_right_r() : word0(0) {}
10537     CONSTEXPR ifm_pad_right_r(uint32_t init) : word0(init) {}
10538     CONSTEXPR void operator=(uint32_t value)
10539     {
10540         word0 = value;
10541     }
10542     void operator=(uint32_t value) volatile
10543     {
10544         word0 = value;
10545     }
10546     CONSTEXPR operator uint32_t()
10547     {
10548         return word0;
10549     }
10550     operator uint32_t() volatile
10551     {
10552         return word0;
10553     }
10554     ifm_pad_right_r copy() volatile
10555     {
10556         return *this;
10557     }
10558     CONSTEXPR uint32_t get_value() const
10559     {
10560         uint32_t value = word0;
10561         return value;
10562     }
10563     uint32_t get_value() const volatile
10564     {
10565         uint32_t value = word0;
10566         return value;
10567     }
10568     CONSTEXPR ifm_pad_right_r &set_value(uint32_t value)
10569     {
10570         word0 = value;
10571         return *this;
10572     }
10573     volatile ifm_pad_right_r &set_value(uint32_t value) volatile
10574     {
10575         word0 = value;
10576         return *this;
10577     }
10578 #endif
10579 };
10580 
10581 // ifm_pad_bottom_r - None
10582 struct ifm_pad_bottom_r
10583 {
10584 #ifndef __cplusplus
10585     union
10586     {
10587         struct
10588         {
10589             uint32_t value : 32; // 32-bit register value
10590         };
10591         uint32_t word;
10592     };
10593 #else
10594   private:
10595     uint32_t word0;
10596 
10597   public:
10598     CONSTEXPR ifm_pad_bottom_r() : word0(0) {}
10599     CONSTEXPR ifm_pad_bottom_r(uint32_t init) : word0(init) {}
10600     CONSTEXPR void operator=(uint32_t value)
10601     {
10602         word0 = value;
10603     }
10604     void operator=(uint32_t value) volatile
10605     {
10606         word0 = value;
10607     }
10608     CONSTEXPR operator uint32_t()
10609     {
10610         return word0;
10611     }
10612     operator uint32_t() volatile
10613     {
10614         return word0;
10615     }
10616     ifm_pad_bottom_r copy() volatile
10617     {
10618         return *this;
10619     }
10620     CONSTEXPR uint32_t get_value() const
10621     {
10622         uint32_t value = word0;
10623         return value;
10624     }
10625     uint32_t get_value() const volatile
10626     {
10627         uint32_t value = word0;
10628         return value;
10629     }
10630     CONSTEXPR ifm_pad_bottom_r &set_value(uint32_t value)
10631     {
10632         word0 = value;
10633         return *this;
10634     }
10635     volatile ifm_pad_bottom_r &set_value(uint32_t value) volatile
10636     {
10637         word0 = value;
10638         return *this;
10639     }
10640 #endif
10641 };
10642 
10643 // ifm_depth_m1_r - None
10644 struct ifm_depth_m1_r
10645 {
10646 #ifndef __cplusplus
10647     union
10648     {
10649         struct
10650         {
10651             uint32_t value : 32; // 32-bit register value
10652         };
10653         uint32_t word;
10654     };
10655 #else
10656   private:
10657     uint32_t word0;
10658 
10659   public:
10660     CONSTEXPR ifm_depth_m1_r() : word0(0) {}
10661     CONSTEXPR ifm_depth_m1_r(uint32_t init) : word0(init) {}
10662     CONSTEXPR void operator=(uint32_t value)
10663     {
10664         word0 = value;
10665     }
10666     void operator=(uint32_t value) volatile
10667     {
10668         word0 = value;
10669     }
10670     CONSTEXPR operator uint32_t()
10671     {
10672         return word0;
10673     }
10674     operator uint32_t() volatile
10675     {
10676         return word0;
10677     }
10678     ifm_depth_m1_r copy() volatile
10679     {
10680         return *this;
10681     }
10682     CONSTEXPR uint32_t get_value() const
10683     {
10684         uint32_t value = word0;
10685         return value;
10686     }
10687     uint32_t get_value() const volatile
10688     {
10689         uint32_t value = word0;
10690         return value;
10691     }
10692     CONSTEXPR ifm_depth_m1_r &set_value(uint32_t value)
10693     {
10694         word0 = value;
10695         return *this;
10696     }
10697     volatile ifm_depth_m1_r &set_value(uint32_t value) volatile
10698     {
10699         word0 = value;
10700         return *this;
10701     }
10702 #endif
10703 };
10704 
10705 // ifm_precision_r - None
10706 struct ifm_precision_r
10707 {
10708 #ifndef __cplusplus
10709     union
10710     {
10711         struct
10712         {
10713             uint32_t value : 32; // 32-bit register value
10714         };
10715         uint32_t word;
10716     };
10717 #else
10718   private:
10719     uint32_t word0;
10720 
10721   public:
10722     CONSTEXPR ifm_precision_r() : word0(0) {}
10723     CONSTEXPR ifm_precision_r(uint32_t init) : word0(init) {}
10724     CONSTEXPR void operator=(uint32_t value)
10725     {
10726         word0 = value;
10727     }
10728     void operator=(uint32_t value) volatile
10729     {
10730         word0 = value;
10731     }
10732     CONSTEXPR operator uint32_t()
10733     {
10734         return word0;
10735     }
10736     operator uint32_t() volatile
10737     {
10738         return word0;
10739     }
10740     ifm_precision_r copy() volatile
10741     {
10742         return *this;
10743     }
10744     CONSTEXPR uint32_t get_value() const
10745     {
10746         uint32_t value = word0;
10747         return value;
10748     }
10749     uint32_t get_value() const volatile
10750     {
10751         uint32_t value = word0;
10752         return value;
10753     }
10754     CONSTEXPR ifm_precision_r &set_value(uint32_t value)
10755     {
10756         word0 = value;
10757         return *this;
10758     }
10759     volatile ifm_precision_r &set_value(uint32_t value) volatile
10760     {
10761         word0 = value;
10762         return *this;
10763     }
10764 #endif
10765 };
10766 
10767 // ifm_upscale_r - None
10768 struct ifm_upscale_r
10769 {
10770 #ifndef __cplusplus
10771     union
10772     {
10773         struct
10774         {
10775             uint32_t value : 32; // 32-bit register value
10776         };
10777         uint32_t word;
10778     };
10779 #else
10780   private:
10781     uint32_t word0;
10782 
10783   public:
10784     CONSTEXPR ifm_upscale_r() : word0(0) {}
10785     CONSTEXPR ifm_upscale_r(uint32_t init) : word0(init) {}
10786     CONSTEXPR void operator=(uint32_t value)
10787     {
10788         word0 = value;
10789     }
10790     void operator=(uint32_t value) volatile
10791     {
10792         word0 = value;
10793     }
10794     CONSTEXPR operator uint32_t()
10795     {
10796         return word0;
10797     }
10798     operator uint32_t() volatile
10799     {
10800         return word0;
10801     }
10802     ifm_upscale_r copy() volatile
10803     {
10804         return *this;
10805     }
10806     CONSTEXPR uint32_t get_value() const
10807     {
10808         uint32_t value = word0;
10809         return value;
10810     }
10811     uint32_t get_value() const volatile
10812     {
10813         uint32_t value = word0;
10814         return value;
10815     }
10816     CONSTEXPR ifm_upscale_r &set_value(uint32_t value)
10817     {
10818         word0 = value;
10819         return *this;
10820     }
10821     volatile ifm_upscale_r &set_value(uint32_t value) volatile
10822     {
10823         word0 = value;
10824         return *this;
10825     }
10826 #endif
10827 };
10828 
10829 // ifm_zero_point_r - None
10830 struct ifm_zero_point_r
10831 {
10832 #ifndef __cplusplus
10833     union
10834     {
10835         struct
10836         {
10837             uint32_t value : 32; // 32-bit register value
10838         };
10839         uint32_t word;
10840     };
10841 #else
10842   private:
10843     uint32_t word0;
10844 
10845   public:
10846     CONSTEXPR ifm_zero_point_r() : word0(0) {}
10847     CONSTEXPR ifm_zero_point_r(uint32_t init) : word0(init) {}
10848     CONSTEXPR void operator=(uint32_t value)
10849     {
10850         word0 = value;
10851     }
10852     void operator=(uint32_t value) volatile
10853     {
10854         word0 = value;
10855     }
10856     CONSTEXPR operator uint32_t()
10857     {
10858         return word0;
10859     }
10860     operator uint32_t() volatile
10861     {
10862         return word0;
10863     }
10864     ifm_zero_point_r copy() volatile
10865     {
10866         return *this;
10867     }
10868     CONSTEXPR uint32_t get_value() const
10869     {
10870         uint32_t value = word0;
10871         return value;
10872     }
10873     uint32_t get_value() const volatile
10874     {
10875         uint32_t value = word0;
10876         return value;
10877     }
10878     CONSTEXPR ifm_zero_point_r &set_value(uint32_t value)
10879     {
10880         word0 = value;
10881         return *this;
10882     }
10883     volatile ifm_zero_point_r &set_value(uint32_t value) volatile
10884     {
10885         word0 = value;
10886         return *this;
10887     }
10888 #endif
10889 };
10890 
10891 // ifm_width0_m1_r - None
10892 struct ifm_width0_m1_r
10893 {
10894 #ifndef __cplusplus
10895     union
10896     {
10897         struct
10898         {
10899             uint32_t value : 32; // 32-bit register value
10900         };
10901         uint32_t word;
10902     };
10903 #else
10904   private:
10905     uint32_t word0;
10906 
10907   public:
10908     CONSTEXPR ifm_width0_m1_r() : word0(0) {}
10909     CONSTEXPR ifm_width0_m1_r(uint32_t init) : word0(init) {}
10910     CONSTEXPR void operator=(uint32_t value)
10911     {
10912         word0 = value;
10913     }
10914     void operator=(uint32_t value) volatile
10915     {
10916         word0 = value;
10917     }
10918     CONSTEXPR operator uint32_t()
10919     {
10920         return word0;
10921     }
10922     operator uint32_t() volatile
10923     {
10924         return word0;
10925     }
10926     ifm_width0_m1_r copy() volatile
10927     {
10928         return *this;
10929     }
10930     CONSTEXPR uint32_t get_value() const
10931     {
10932         uint32_t value = word0;
10933         return value;
10934     }
10935     uint32_t get_value() const volatile
10936     {
10937         uint32_t value = word0;
10938         return value;
10939     }
10940     CONSTEXPR ifm_width0_m1_r &set_value(uint32_t value)
10941     {
10942         word0 = value;
10943         return *this;
10944     }
10945     volatile ifm_width0_m1_r &set_value(uint32_t value) volatile
10946     {
10947         word0 = value;
10948         return *this;
10949     }
10950 #endif
10951 };
10952 
10953 // ifm_height0_m1_r - None
10954 struct ifm_height0_m1_r
10955 {
10956 #ifndef __cplusplus
10957     union
10958     {
10959         struct
10960         {
10961             uint32_t value : 32; // 32-bit register value
10962         };
10963         uint32_t word;
10964     };
10965 #else
10966   private:
10967     uint32_t word0;
10968 
10969   public:
10970     CONSTEXPR ifm_height0_m1_r() : word0(0) {}
10971     CONSTEXPR ifm_height0_m1_r(uint32_t init) : word0(init) {}
10972     CONSTEXPR void operator=(uint32_t value)
10973     {
10974         word0 = value;
10975     }
10976     void operator=(uint32_t value) volatile
10977     {
10978         word0 = value;
10979     }
10980     CONSTEXPR operator uint32_t()
10981     {
10982         return word0;
10983     }
10984     operator uint32_t() volatile
10985     {
10986         return word0;
10987     }
10988     ifm_height0_m1_r copy() volatile
10989     {
10990         return *this;
10991     }
10992     CONSTEXPR uint32_t get_value() const
10993     {
10994         uint32_t value = word0;
10995         return value;
10996     }
10997     uint32_t get_value() const volatile
10998     {
10999         uint32_t value = word0;
11000         return value;
11001     }
11002     CONSTEXPR ifm_height0_m1_r &set_value(uint32_t value)
11003     {
11004         word0 = value;
11005         return *this;
11006     }
11007     volatile ifm_height0_m1_r &set_value(uint32_t value) volatile
11008     {
11009         word0 = value;
11010         return *this;
11011     }
11012 #endif
11013 };
11014 
11015 // ifm_height1_m1_r - None
11016 struct ifm_height1_m1_r
11017 {
11018 #ifndef __cplusplus
11019     union
11020     {
11021         struct
11022         {
11023             uint32_t value : 32; // 32-bit register value
11024         };
11025         uint32_t word;
11026     };
11027 #else
11028   private:
11029     uint32_t word0;
11030 
11031   public:
11032     CONSTEXPR ifm_height1_m1_r() : word0(0) {}
11033     CONSTEXPR ifm_height1_m1_r(uint32_t init) : word0(init) {}
11034     CONSTEXPR void operator=(uint32_t value)
11035     {
11036         word0 = value;
11037     }
11038     void operator=(uint32_t value) volatile
11039     {
11040         word0 = value;
11041     }
11042     CONSTEXPR operator uint32_t()
11043     {
11044         return word0;
11045     }
11046     operator uint32_t() volatile
11047     {
11048         return word0;
11049     }
11050     ifm_height1_m1_r copy() volatile
11051     {
11052         return *this;
11053     }
11054     CONSTEXPR uint32_t get_value() const
11055     {
11056         uint32_t value = word0;
11057         return value;
11058     }
11059     uint32_t get_value() const volatile
11060     {
11061         uint32_t value = word0;
11062         return value;
11063     }
11064     CONSTEXPR ifm_height1_m1_r &set_value(uint32_t value)
11065     {
11066         word0 = value;
11067         return *this;
11068     }
11069     volatile ifm_height1_m1_r &set_value(uint32_t value) volatile
11070     {
11071         word0 = value;
11072         return *this;
11073     }
11074 #endif
11075 };
11076 
11077 // ifm_ib_end_r - None
11078 struct ifm_ib_end_r
11079 {
11080 #ifndef __cplusplus
11081     union
11082     {
11083         struct
11084         {
11085             uint32_t value : 32; // 32-bit register value
11086         };
11087         uint32_t word;
11088     };
11089 #else
11090   private:
11091     uint32_t word0;
11092 
11093   public:
11094     CONSTEXPR ifm_ib_end_r() : word0(0) {}
11095     CONSTEXPR ifm_ib_end_r(uint32_t init) : word0(init) {}
11096     CONSTEXPR void operator=(uint32_t value)
11097     {
11098         word0 = value;
11099     }
11100     void operator=(uint32_t value) volatile
11101     {
11102         word0 = value;
11103     }
11104     CONSTEXPR operator uint32_t()
11105     {
11106         return word0;
11107     }
11108     operator uint32_t() volatile
11109     {
11110         return word0;
11111     }
11112     ifm_ib_end_r copy() volatile
11113     {
11114         return *this;
11115     }
11116     CONSTEXPR uint32_t get_value() const
11117     {
11118         uint32_t value = word0;
11119         return value;
11120     }
11121     uint32_t get_value() const volatile
11122     {
11123         uint32_t value = word0;
11124         return value;
11125     }
11126     CONSTEXPR ifm_ib_end_r &set_value(uint32_t value)
11127     {
11128         word0 = value;
11129         return *this;
11130     }
11131     volatile ifm_ib_end_r &set_value(uint32_t value) volatile
11132     {
11133         word0 = value;
11134         return *this;
11135     }
11136 #endif
11137 };
11138 
11139 // ifm_region_r - None
11140 struct ifm_region_r
11141 {
11142 #ifndef __cplusplus
11143     union
11144     {
11145         struct
11146         {
11147             uint32_t value : 32; // 32-bit register value
11148         };
11149         uint32_t word;
11150     };
11151 #else
11152   private:
11153     uint32_t word0;
11154 
11155   public:
11156     CONSTEXPR ifm_region_r() : word0(0) {}
11157     CONSTEXPR ifm_region_r(uint32_t init) : word0(init) {}
11158     CONSTEXPR void operator=(uint32_t value)
11159     {
11160         word0 = value;
11161     }
11162     void operator=(uint32_t value) volatile
11163     {
11164         word0 = value;
11165     }
11166     CONSTEXPR operator uint32_t()
11167     {
11168         return word0;
11169     }
11170     operator uint32_t() volatile
11171     {
11172         return word0;
11173     }
11174     ifm_region_r copy() volatile
11175     {
11176         return *this;
11177     }
11178     CONSTEXPR uint32_t get_value() const
11179     {
11180         uint32_t value = word0;
11181         return value;
11182     }
11183     uint32_t get_value() const volatile
11184     {
11185         uint32_t value = word0;
11186         return value;
11187     }
11188     CONSTEXPR ifm_region_r &set_value(uint32_t value)
11189     {
11190         word0 = value;
11191         return *this;
11192     }
11193     volatile ifm_region_r &set_value(uint32_t value) volatile
11194     {
11195         word0 = value;
11196         return *this;
11197     }
11198 #endif
11199 };
11200 
11201 // ofm_width_m1_r - None
11202 struct ofm_width_m1_r
11203 {
11204 #ifndef __cplusplus
11205     union
11206     {
11207         struct
11208         {
11209             uint32_t value : 32; // 32-bit register value
11210         };
11211         uint32_t word;
11212     };
11213 #else
11214   private:
11215     uint32_t word0;
11216 
11217   public:
11218     CONSTEXPR ofm_width_m1_r() : word0(0) {}
11219     CONSTEXPR ofm_width_m1_r(uint32_t init) : word0(init) {}
11220     CONSTEXPR void operator=(uint32_t value)
11221     {
11222         word0 = value;
11223     }
11224     void operator=(uint32_t value) volatile
11225     {
11226         word0 = value;
11227     }
11228     CONSTEXPR operator uint32_t()
11229     {
11230         return word0;
11231     }
11232     operator uint32_t() volatile
11233     {
11234         return word0;
11235     }
11236     ofm_width_m1_r copy() volatile
11237     {
11238         return *this;
11239     }
11240     CONSTEXPR uint32_t get_value() const
11241     {
11242         uint32_t value = word0;
11243         return value;
11244     }
11245     uint32_t get_value() const volatile
11246     {
11247         uint32_t value = word0;
11248         return value;
11249     }
11250     CONSTEXPR ofm_width_m1_r &set_value(uint32_t value)
11251     {
11252         word0 = value;
11253         return *this;
11254     }
11255     volatile ofm_width_m1_r &set_value(uint32_t value) volatile
11256     {
11257         word0 = value;
11258         return *this;
11259     }
11260 #endif
11261 };
11262 
11263 // ofm_height_m1_r - None
11264 struct ofm_height_m1_r
11265 {
11266 #ifndef __cplusplus
11267     union
11268     {
11269         struct
11270         {
11271             uint32_t value : 32; // 32-bit register value
11272         };
11273         uint32_t word;
11274     };
11275 #else
11276   private:
11277     uint32_t word0;
11278 
11279   public:
11280     CONSTEXPR ofm_height_m1_r() : word0(0) {}
11281     CONSTEXPR ofm_height_m1_r(uint32_t init) : word0(init) {}
11282     CONSTEXPR void operator=(uint32_t value)
11283     {
11284         word0 = value;
11285     }
11286     void operator=(uint32_t value) volatile
11287     {
11288         word0 = value;
11289     }
11290     CONSTEXPR operator uint32_t()
11291     {
11292         return word0;
11293     }
11294     operator uint32_t() volatile
11295     {
11296         return word0;
11297     }
11298     ofm_height_m1_r copy() volatile
11299     {
11300         return *this;
11301     }
11302     CONSTEXPR uint32_t get_value() const
11303     {
11304         uint32_t value = word0;
11305         return value;
11306     }
11307     uint32_t get_value() const volatile
11308     {
11309         uint32_t value = word0;
11310         return value;
11311     }
11312     CONSTEXPR ofm_height_m1_r &set_value(uint32_t value)
11313     {
11314         word0 = value;
11315         return *this;
11316     }
11317     volatile ofm_height_m1_r &set_value(uint32_t value) volatile
11318     {
11319         word0 = value;
11320         return *this;
11321     }
11322 #endif
11323 };
11324 
11325 // ofm_depth_m1_r - None
11326 struct ofm_depth_m1_r
11327 {
11328 #ifndef __cplusplus
11329     union
11330     {
11331         struct
11332         {
11333             uint32_t value : 32; // 32-bit register value
11334         };
11335         uint32_t word;
11336     };
11337 #else
11338   private:
11339     uint32_t word0;
11340 
11341   public:
11342     CONSTEXPR ofm_depth_m1_r() : word0(0) {}
11343     CONSTEXPR ofm_depth_m1_r(uint32_t init) : word0(init) {}
11344     CONSTEXPR void operator=(uint32_t value)
11345     {
11346         word0 = value;
11347     }
11348     void operator=(uint32_t value) volatile
11349     {
11350         word0 = value;
11351     }
11352     CONSTEXPR operator uint32_t()
11353     {
11354         return word0;
11355     }
11356     operator uint32_t() volatile
11357     {
11358         return word0;
11359     }
11360     ofm_depth_m1_r copy() volatile
11361     {
11362         return *this;
11363     }
11364     CONSTEXPR uint32_t get_value() const
11365     {
11366         uint32_t value = word0;
11367         return value;
11368     }
11369     uint32_t get_value() const volatile
11370     {
11371         uint32_t value = word0;
11372         return value;
11373     }
11374     CONSTEXPR ofm_depth_m1_r &set_value(uint32_t value)
11375     {
11376         word0 = value;
11377         return *this;
11378     }
11379     volatile ofm_depth_m1_r &set_value(uint32_t value) volatile
11380     {
11381         word0 = value;
11382         return *this;
11383     }
11384 #endif
11385 };
11386 
11387 // ofm_precision_r - None
11388 struct ofm_precision_r
11389 {
11390 #ifndef __cplusplus
11391     union
11392     {
11393         struct
11394         {
11395             uint32_t value : 32; // 32-bit register value
11396         };
11397         uint32_t word;
11398     };
11399 #else
11400   private:
11401     uint32_t word0;
11402 
11403   public:
11404     CONSTEXPR ofm_precision_r() : word0(0) {}
11405     CONSTEXPR ofm_precision_r(uint32_t init) : word0(init) {}
11406     CONSTEXPR void operator=(uint32_t value)
11407     {
11408         word0 = value;
11409     }
11410     void operator=(uint32_t value) volatile
11411     {
11412         word0 = value;
11413     }
11414     CONSTEXPR operator uint32_t()
11415     {
11416         return word0;
11417     }
11418     operator uint32_t() volatile
11419     {
11420         return word0;
11421     }
11422     ofm_precision_r copy() volatile
11423     {
11424         return *this;
11425     }
11426     CONSTEXPR uint32_t get_value() const
11427     {
11428         uint32_t value = word0;
11429         return value;
11430     }
11431     uint32_t get_value() const volatile
11432     {
11433         uint32_t value = word0;
11434         return value;
11435     }
11436     CONSTEXPR ofm_precision_r &set_value(uint32_t value)
11437     {
11438         word0 = value;
11439         return *this;
11440     }
11441     volatile ofm_precision_r &set_value(uint32_t value) volatile
11442     {
11443         word0 = value;
11444         return *this;
11445     }
11446 #endif
11447 };
11448 
11449 // ofm_blk_width_m1_r - None
11450 struct ofm_blk_width_m1_r
11451 {
11452 #ifndef __cplusplus
11453     union
11454     {
11455         struct
11456         {
11457             uint32_t value : 32; // 32-bit register value
11458         };
11459         uint32_t word;
11460     };
11461 #else
11462   private:
11463     uint32_t word0;
11464 
11465   public:
11466     CONSTEXPR ofm_blk_width_m1_r() : word0(0) {}
11467     CONSTEXPR ofm_blk_width_m1_r(uint32_t init) : word0(init) {}
11468     CONSTEXPR void operator=(uint32_t value)
11469     {
11470         word0 = value;
11471     }
11472     void operator=(uint32_t value) volatile
11473     {
11474         word0 = value;
11475     }
11476     CONSTEXPR operator uint32_t()
11477     {
11478         return word0;
11479     }
11480     operator uint32_t() volatile
11481     {
11482         return word0;
11483     }
11484     ofm_blk_width_m1_r copy() volatile
11485     {
11486         return *this;
11487     }
11488     CONSTEXPR uint32_t get_value() const
11489     {
11490         uint32_t value = word0;
11491         return value;
11492     }
11493     uint32_t get_value() const volatile
11494     {
11495         uint32_t value = word0;
11496         return value;
11497     }
11498     CONSTEXPR ofm_blk_width_m1_r &set_value(uint32_t value)
11499     {
11500         word0 = value;
11501         return *this;
11502     }
11503     volatile ofm_blk_width_m1_r &set_value(uint32_t value) volatile
11504     {
11505         word0 = value;
11506         return *this;
11507     }
11508 #endif
11509 };
11510 
11511 // ofm_blk_height_m1_r - None
11512 struct ofm_blk_height_m1_r
11513 {
11514 #ifndef __cplusplus
11515     union
11516     {
11517         struct
11518         {
11519             uint32_t value : 32; // 32-bit register value
11520         };
11521         uint32_t word;
11522     };
11523 #else
11524   private:
11525     uint32_t word0;
11526 
11527   public:
11528     CONSTEXPR ofm_blk_height_m1_r() : word0(0) {}
11529     CONSTEXPR ofm_blk_height_m1_r(uint32_t init) : word0(init) {}
11530     CONSTEXPR void operator=(uint32_t value)
11531     {
11532         word0 = value;
11533     }
11534     void operator=(uint32_t value) volatile
11535     {
11536         word0 = value;
11537     }
11538     CONSTEXPR operator uint32_t()
11539     {
11540         return word0;
11541     }
11542     operator uint32_t() volatile
11543     {
11544         return word0;
11545     }
11546     ofm_blk_height_m1_r copy() volatile
11547     {
11548         return *this;
11549     }
11550     CONSTEXPR uint32_t get_value() const
11551     {
11552         uint32_t value = word0;
11553         return value;
11554     }
11555     uint32_t get_value() const volatile
11556     {
11557         uint32_t value = word0;
11558         return value;
11559     }
11560     CONSTEXPR ofm_blk_height_m1_r &set_value(uint32_t value)
11561     {
11562         word0 = value;
11563         return *this;
11564     }
11565     volatile ofm_blk_height_m1_r &set_value(uint32_t value) volatile
11566     {
11567         word0 = value;
11568         return *this;
11569     }
11570 #endif
11571 };
11572 
11573 // ofm_blk_depth_m1_r - None
11574 struct ofm_blk_depth_m1_r
11575 {
11576 #ifndef __cplusplus
11577     union
11578     {
11579         struct
11580         {
11581             uint32_t value : 32; // 32-bit register value
11582         };
11583         uint32_t word;
11584     };
11585 #else
11586   private:
11587     uint32_t word0;
11588 
11589   public:
11590     CONSTEXPR ofm_blk_depth_m1_r() : word0(0) {}
11591     CONSTEXPR ofm_blk_depth_m1_r(uint32_t init) : word0(init) {}
11592     CONSTEXPR void operator=(uint32_t value)
11593     {
11594         word0 = value;
11595     }
11596     void operator=(uint32_t value) volatile
11597     {
11598         word0 = value;
11599     }
11600     CONSTEXPR operator uint32_t()
11601     {
11602         return word0;
11603     }
11604     operator uint32_t() volatile
11605     {
11606         return word0;
11607     }
11608     ofm_blk_depth_m1_r copy() volatile
11609     {
11610         return *this;
11611     }
11612     CONSTEXPR uint32_t get_value() const
11613     {
11614         uint32_t value = word0;
11615         return value;
11616     }
11617     uint32_t get_value() const volatile
11618     {
11619         uint32_t value = word0;
11620         return value;
11621     }
11622     CONSTEXPR ofm_blk_depth_m1_r &set_value(uint32_t value)
11623     {
11624         word0 = value;
11625         return *this;
11626     }
11627     volatile ofm_blk_depth_m1_r &set_value(uint32_t value) volatile
11628     {
11629         word0 = value;
11630         return *this;
11631     }
11632 #endif
11633 };
11634 
11635 // ofm_zero_point_r - None
11636 struct ofm_zero_point_r
11637 {
11638 #ifndef __cplusplus
11639     union
11640     {
11641         struct
11642         {
11643             uint32_t value : 32; // 32-bit register value
11644         };
11645         uint32_t word;
11646     };
11647 #else
11648   private:
11649     uint32_t word0;
11650 
11651   public:
11652     CONSTEXPR ofm_zero_point_r() : word0(0) {}
11653     CONSTEXPR ofm_zero_point_r(uint32_t init) : word0(init) {}
11654     CONSTEXPR void operator=(uint32_t value)
11655     {
11656         word0 = value;
11657     }
11658     void operator=(uint32_t value) volatile
11659     {
11660         word0 = value;
11661     }
11662     CONSTEXPR operator uint32_t()
11663     {
11664         return word0;
11665     }
11666     operator uint32_t() volatile
11667     {
11668         return word0;
11669     }
11670     ofm_zero_point_r copy() volatile
11671     {
11672         return *this;
11673     }
11674     CONSTEXPR uint32_t get_value() const
11675     {
11676         uint32_t value = word0;
11677         return value;
11678     }
11679     uint32_t get_value() const volatile
11680     {
11681         uint32_t value = word0;
11682         return value;
11683     }
11684     CONSTEXPR ofm_zero_point_r &set_value(uint32_t value)
11685     {
11686         word0 = value;
11687         return *this;
11688     }
11689     volatile ofm_zero_point_r &set_value(uint32_t value) volatile
11690     {
11691         word0 = value;
11692         return *this;
11693     }
11694 #endif
11695 };
11696 
11697 // ofm_width0_m1_r - None
11698 struct ofm_width0_m1_r
11699 {
11700 #ifndef __cplusplus
11701     union
11702     {
11703         struct
11704         {
11705             uint32_t value : 32; // 32-bit register value
11706         };
11707         uint32_t word;
11708     };
11709 #else
11710   private:
11711     uint32_t word0;
11712 
11713   public:
11714     CONSTEXPR ofm_width0_m1_r() : word0(0) {}
11715     CONSTEXPR ofm_width0_m1_r(uint32_t init) : word0(init) {}
11716     CONSTEXPR void operator=(uint32_t value)
11717     {
11718         word0 = value;
11719     }
11720     void operator=(uint32_t value) volatile
11721     {
11722         word0 = value;
11723     }
11724     CONSTEXPR operator uint32_t()
11725     {
11726         return word0;
11727     }
11728     operator uint32_t() volatile
11729     {
11730         return word0;
11731     }
11732     ofm_width0_m1_r copy() volatile
11733     {
11734         return *this;
11735     }
11736     CONSTEXPR uint32_t get_value() const
11737     {
11738         uint32_t value = word0;
11739         return value;
11740     }
11741     uint32_t get_value() const volatile
11742     {
11743         uint32_t value = word0;
11744         return value;
11745     }
11746     CONSTEXPR ofm_width0_m1_r &set_value(uint32_t value)
11747     {
11748         word0 = value;
11749         return *this;
11750     }
11751     volatile ofm_width0_m1_r &set_value(uint32_t value) volatile
11752     {
11753         word0 = value;
11754         return *this;
11755     }
11756 #endif
11757 };
11758 
11759 // ofm_height0_m1_r - None
11760 struct ofm_height0_m1_r
11761 {
11762 #ifndef __cplusplus
11763     union
11764     {
11765         struct
11766         {
11767             uint32_t value : 32; // 32-bit register value
11768         };
11769         uint32_t word;
11770     };
11771 #else
11772   private:
11773     uint32_t word0;
11774 
11775   public:
11776     CONSTEXPR ofm_height0_m1_r() : word0(0) {}
11777     CONSTEXPR ofm_height0_m1_r(uint32_t init) : word0(init) {}
11778     CONSTEXPR void operator=(uint32_t value)
11779     {
11780         word0 = value;
11781     }
11782     void operator=(uint32_t value) volatile
11783     {
11784         word0 = value;
11785     }
11786     CONSTEXPR operator uint32_t()
11787     {
11788         return word0;
11789     }
11790     operator uint32_t() volatile
11791     {
11792         return word0;
11793     }
11794     ofm_height0_m1_r copy() volatile
11795     {
11796         return *this;
11797     }
11798     CONSTEXPR uint32_t get_value() const
11799     {
11800         uint32_t value = word0;
11801         return value;
11802     }
11803     uint32_t get_value() const volatile
11804     {
11805         uint32_t value = word0;
11806         return value;
11807     }
11808     CONSTEXPR ofm_height0_m1_r &set_value(uint32_t value)
11809     {
11810         word0 = value;
11811         return *this;
11812     }
11813     volatile ofm_height0_m1_r &set_value(uint32_t value) volatile
11814     {
11815         word0 = value;
11816         return *this;
11817     }
11818 #endif
11819 };
11820 
11821 // ofm_height1_m1_r - None
11822 struct ofm_height1_m1_r
11823 {
11824 #ifndef __cplusplus
11825     union
11826     {
11827         struct
11828         {
11829             uint32_t value : 32; // 32-bit register value
11830         };
11831         uint32_t word;
11832     };
11833 #else
11834   private:
11835     uint32_t word0;
11836 
11837   public:
11838     CONSTEXPR ofm_height1_m1_r() : word0(0) {}
11839     CONSTEXPR ofm_height1_m1_r(uint32_t init) : word0(init) {}
11840     CONSTEXPR void operator=(uint32_t value)
11841     {
11842         word0 = value;
11843     }
11844     void operator=(uint32_t value) volatile
11845     {
11846         word0 = value;
11847     }
11848     CONSTEXPR operator uint32_t()
11849     {
11850         return word0;
11851     }
11852     operator uint32_t() volatile
11853     {
11854         return word0;
11855     }
11856     ofm_height1_m1_r copy() volatile
11857     {
11858         return *this;
11859     }
11860     CONSTEXPR uint32_t get_value() const
11861     {
11862         uint32_t value = word0;
11863         return value;
11864     }
11865     uint32_t get_value() const volatile
11866     {
11867         uint32_t value = word0;
11868         return value;
11869     }
11870     CONSTEXPR ofm_height1_m1_r &set_value(uint32_t value)
11871     {
11872         word0 = value;
11873         return *this;
11874     }
11875     volatile ofm_height1_m1_r &set_value(uint32_t value) volatile
11876     {
11877         word0 = value;
11878         return *this;
11879     }
11880 #endif
11881 };
11882 
11883 // ofm_region_r - None
11884 struct ofm_region_r
11885 {
11886 #ifndef __cplusplus
11887     union
11888     {
11889         struct
11890         {
11891             uint32_t value : 32; // 32-bit register value
11892         };
11893         uint32_t word;
11894     };
11895 #else
11896   private:
11897     uint32_t word0;
11898 
11899   public:
11900     CONSTEXPR ofm_region_r() : word0(0) {}
11901     CONSTEXPR ofm_region_r(uint32_t init) : word0(init) {}
11902     CONSTEXPR void operator=(uint32_t value)
11903     {
11904         word0 = value;
11905     }
11906     void operator=(uint32_t value) volatile
11907     {
11908         word0 = value;
11909     }
11910     CONSTEXPR operator uint32_t()
11911     {
11912         return word0;
11913     }
11914     operator uint32_t() volatile
11915     {
11916         return word0;
11917     }
11918     ofm_region_r copy() volatile
11919     {
11920         return *this;
11921     }
11922     CONSTEXPR uint32_t get_value() const
11923     {
11924         uint32_t value = word0;
11925         return value;
11926     }
11927     uint32_t get_value() const volatile
11928     {
11929         uint32_t value = word0;
11930         return value;
11931     }
11932     CONSTEXPR ofm_region_r &set_value(uint32_t value)
11933     {
11934         word0 = value;
11935         return *this;
11936     }
11937     volatile ofm_region_r &set_value(uint32_t value) volatile
11938     {
11939         word0 = value;
11940         return *this;
11941     }
11942 #endif
11943 };
11944 
11945 // kernel_width_m1_r - None
11946 struct kernel_width_m1_r
11947 {
11948 #ifndef __cplusplus
11949     union
11950     {
11951         struct
11952         {
11953             uint32_t value : 32; // 32-bit register value
11954         };
11955         uint32_t word;
11956     };
11957 #else
11958   private:
11959     uint32_t word0;
11960 
11961   public:
11962     CONSTEXPR kernel_width_m1_r() : word0(0) {}
11963     CONSTEXPR kernel_width_m1_r(uint32_t init) : word0(init) {}
11964     CONSTEXPR void operator=(uint32_t value)
11965     {
11966         word0 = value;
11967     }
11968     void operator=(uint32_t value) volatile
11969     {
11970         word0 = value;
11971     }
11972     CONSTEXPR operator uint32_t()
11973     {
11974         return word0;
11975     }
11976     operator uint32_t() volatile
11977     {
11978         return word0;
11979     }
11980     kernel_width_m1_r copy() volatile
11981     {
11982         return *this;
11983     }
11984     CONSTEXPR uint32_t get_value() const
11985     {
11986         uint32_t value = word0;
11987         return value;
11988     }
11989     uint32_t get_value() const volatile
11990     {
11991         uint32_t value = word0;
11992         return value;
11993     }
11994     CONSTEXPR kernel_width_m1_r &set_value(uint32_t value)
11995     {
11996         word0 = value;
11997         return *this;
11998     }
11999     volatile kernel_width_m1_r &set_value(uint32_t value) volatile
12000     {
12001         word0 = value;
12002         return *this;
12003     }
12004 #endif
12005 };
12006 
12007 // kernel_height_m1_r - None
12008 struct kernel_height_m1_r
12009 {
12010 #ifndef __cplusplus
12011     union
12012     {
12013         struct
12014         {
12015             uint32_t value : 32; // 32-bit register value
12016         };
12017         uint32_t word;
12018     };
12019 #else
12020   private:
12021     uint32_t word0;
12022 
12023   public:
12024     CONSTEXPR kernel_height_m1_r() : word0(0) {}
12025     CONSTEXPR kernel_height_m1_r(uint32_t init) : word0(init) {}
12026     CONSTEXPR void operator=(uint32_t value)
12027     {
12028         word0 = value;
12029     }
12030     void operator=(uint32_t value) volatile
12031     {
12032         word0 = value;
12033     }
12034     CONSTEXPR operator uint32_t()
12035     {
12036         return word0;
12037     }
12038     operator uint32_t() volatile
12039     {
12040         return word0;
12041     }
12042     kernel_height_m1_r copy() volatile
12043     {
12044         return *this;
12045     }
12046     CONSTEXPR uint32_t get_value() const
12047     {
12048         uint32_t value = word0;
12049         return value;
12050     }
12051     uint32_t get_value() const volatile
12052     {
12053         uint32_t value = word0;
12054         return value;
12055     }
12056     CONSTEXPR kernel_height_m1_r &set_value(uint32_t value)
12057     {
12058         word0 = value;
12059         return *this;
12060     }
12061     volatile kernel_height_m1_r &set_value(uint32_t value) volatile
12062     {
12063         word0 = value;
12064         return *this;
12065     }
12066 #endif
12067 };
12068 
12069 // kernel_stride_r - None
12070 struct kernel_stride_r
12071 {
12072 #ifndef __cplusplus
12073     union
12074     {
12075         struct
12076         {
12077             uint32_t value : 32; // 32-bit register value
12078         };
12079         uint32_t word;
12080     };
12081 #else
12082   private:
12083     uint32_t word0;
12084 
12085   public:
12086     CONSTEXPR kernel_stride_r() : word0(0) {}
12087     CONSTEXPR kernel_stride_r(uint32_t init) : word0(init) {}
12088     CONSTEXPR void operator=(uint32_t value)
12089     {
12090         word0 = value;
12091     }
12092     void operator=(uint32_t value) volatile
12093     {
12094         word0 = value;
12095     }
12096     CONSTEXPR operator uint32_t()
12097     {
12098         return word0;
12099     }
12100     operator uint32_t() volatile
12101     {
12102         return word0;
12103     }
12104     kernel_stride_r copy() volatile
12105     {
12106         return *this;
12107     }
12108     CONSTEXPR uint32_t get_value() const
12109     {
12110         uint32_t value = word0;
12111         return value;
12112     }
12113     uint32_t get_value() const volatile
12114     {
12115         uint32_t value = word0;
12116         return value;
12117     }
12118     CONSTEXPR kernel_stride_r &set_value(uint32_t value)
12119     {
12120         word0 = value;
12121         return *this;
12122     }
12123     volatile kernel_stride_r &set_value(uint32_t value) volatile
12124     {
12125         word0 = value;
12126         return *this;
12127     }
12128 #endif
12129 };
12130 
12131 // parallel_mode_r - None
12132 struct parallel_mode_r
12133 {
12134 #ifndef __cplusplus
12135     union
12136     {
12137         struct
12138         {
12139             uint32_t value : 32; // 32-bit register value
12140         };
12141         uint32_t word;
12142     };
12143 #else
12144   private:
12145     uint32_t word0;
12146 
12147   public:
12148     CONSTEXPR parallel_mode_r() : word0(0) {}
12149     CONSTEXPR parallel_mode_r(uint32_t init) : word0(init) {}
12150     CONSTEXPR void operator=(uint32_t value)
12151     {
12152         word0 = value;
12153     }
12154     void operator=(uint32_t value) volatile
12155     {
12156         word0 = value;
12157     }
12158     CONSTEXPR operator uint32_t()
12159     {
12160         return word0;
12161     }
12162     operator uint32_t() volatile
12163     {
12164         return word0;
12165     }
12166     parallel_mode_r copy() volatile
12167     {
12168         return *this;
12169     }
12170     CONSTEXPR uint32_t get_value() const
12171     {
12172         uint32_t value = word0;
12173         return value;
12174     }
12175     uint32_t get_value() const volatile
12176     {
12177         uint32_t value = word0;
12178         return value;
12179     }
12180     CONSTEXPR parallel_mode_r &set_value(uint32_t value)
12181     {
12182         word0 = value;
12183         return *this;
12184     }
12185     volatile parallel_mode_r &set_value(uint32_t value) volatile
12186     {
12187         word0 = value;
12188         return *this;
12189     }
12190 #endif
12191 };
12192 
12193 // acc_format_r - None
12194 struct acc_format_r
12195 {
12196 #ifndef __cplusplus
12197     union
12198     {
12199         struct
12200         {
12201             uint32_t value : 32; // 32-bit register value
12202         };
12203         uint32_t word;
12204     };
12205 #else
12206   private:
12207     uint32_t word0;
12208 
12209   public:
12210     CONSTEXPR acc_format_r() : word0(0) {}
12211     CONSTEXPR acc_format_r(uint32_t init) : word0(init) {}
12212     CONSTEXPR void operator=(uint32_t value)
12213     {
12214         word0 = value;
12215     }
12216     void operator=(uint32_t value) volatile
12217     {
12218         word0 = value;
12219     }
12220     CONSTEXPR operator uint32_t()
12221     {
12222         return word0;
12223     }
12224     operator uint32_t() volatile
12225     {
12226         return word0;
12227     }
12228     acc_format_r copy() volatile
12229     {
12230         return *this;
12231     }
12232     CONSTEXPR uint32_t get_value() const
12233     {
12234         uint32_t value = word0;
12235         return value;
12236     }
12237     uint32_t get_value() const volatile
12238     {
12239         uint32_t value = word0;
12240         return value;
12241     }
12242     CONSTEXPR acc_format_r &set_value(uint32_t value)
12243     {
12244         word0 = value;
12245         return *this;
12246     }
12247     volatile acc_format_r &set_value(uint32_t value) volatile
12248     {
12249         word0 = value;
12250         return *this;
12251     }
12252 #endif
12253 };
12254 
12255 // activation_r - None
12256 struct activation_r
12257 {
12258 #ifndef __cplusplus
12259     union
12260     {
12261         struct
12262         {
12263             uint32_t value : 32; // 32-bit register value
12264         };
12265         uint32_t word;
12266     };
12267 #else
12268   private:
12269     uint32_t word0;
12270 
12271   public:
12272     CONSTEXPR activation_r() : word0(0) {}
12273     CONSTEXPR activation_r(uint32_t init) : word0(init) {}
12274     CONSTEXPR void operator=(uint32_t value)
12275     {
12276         word0 = value;
12277     }
12278     void operator=(uint32_t value) volatile
12279     {
12280         word0 = value;
12281     }
12282     CONSTEXPR operator uint32_t()
12283     {
12284         return word0;
12285     }
12286     operator uint32_t() volatile
12287     {
12288         return word0;
12289     }
12290     activation_r copy() volatile
12291     {
12292         return *this;
12293     }
12294     CONSTEXPR uint32_t get_value() const
12295     {
12296         uint32_t value = word0;
12297         return value;
12298     }
12299     uint32_t get_value() const volatile
12300     {
12301         uint32_t value = word0;
12302         return value;
12303     }
12304     CONSTEXPR activation_r &set_value(uint32_t value)
12305     {
12306         word0 = value;
12307         return *this;
12308     }
12309     volatile activation_r &set_value(uint32_t value) volatile
12310     {
12311         word0 = value;
12312         return *this;
12313     }
12314 #endif
12315 };
12316 
12317 // activation_min_r - None
12318 struct activation_min_r
12319 {
12320 #ifndef __cplusplus
12321     union
12322     {
12323         struct
12324         {
12325             uint32_t value : 32; // 32-bit register value
12326         };
12327         uint32_t word;
12328     };
12329 #else
12330   private:
12331     uint32_t word0;
12332 
12333   public:
12334     CONSTEXPR activation_min_r() : word0(0) {}
12335     CONSTEXPR activation_min_r(uint32_t init) : word0(init) {}
12336     CONSTEXPR void operator=(uint32_t value)
12337     {
12338         word0 = value;
12339     }
12340     void operator=(uint32_t value) volatile
12341     {
12342         word0 = value;
12343     }
12344     CONSTEXPR operator uint32_t()
12345     {
12346         return word0;
12347     }
12348     operator uint32_t() volatile
12349     {
12350         return word0;
12351     }
12352     activation_min_r copy() volatile
12353     {
12354         return *this;
12355     }
12356     CONSTEXPR uint32_t get_value() const
12357     {
12358         uint32_t value = word0;
12359         return value;
12360     }
12361     uint32_t get_value() const volatile
12362     {
12363         uint32_t value = word0;
12364         return value;
12365     }
12366     CONSTEXPR activation_min_r &set_value(uint32_t value)
12367     {
12368         word0 = value;
12369         return *this;
12370     }
12371     volatile activation_min_r &set_value(uint32_t value) volatile
12372     {
12373         word0 = value;
12374         return *this;
12375     }
12376 #endif
12377 };
12378 
12379 // activation_max_r - None
12380 struct activation_max_r
12381 {
12382 #ifndef __cplusplus
12383     union
12384     {
12385         struct
12386         {
12387             uint32_t value : 32; // 32-bit register value
12388         };
12389         uint32_t word;
12390     };
12391 #else
12392   private:
12393     uint32_t word0;
12394 
12395   public:
12396     CONSTEXPR activation_max_r() : word0(0) {}
12397     CONSTEXPR activation_max_r(uint32_t init) : word0(init) {}
12398     CONSTEXPR void operator=(uint32_t value)
12399     {
12400         word0 = value;
12401     }
12402     void operator=(uint32_t value) volatile
12403     {
12404         word0 = value;
12405     }
12406     CONSTEXPR operator uint32_t()
12407     {
12408         return word0;
12409     }
12410     operator uint32_t() volatile
12411     {
12412         return word0;
12413     }
12414     activation_max_r copy() volatile
12415     {
12416         return *this;
12417     }
12418     CONSTEXPR uint32_t get_value() const
12419     {
12420         uint32_t value = word0;
12421         return value;
12422     }
12423     uint32_t get_value() const volatile
12424     {
12425         uint32_t value = word0;
12426         return value;
12427     }
12428     CONSTEXPR activation_max_r &set_value(uint32_t value)
12429     {
12430         word0 = value;
12431         return *this;
12432     }
12433     volatile activation_max_r &set_value(uint32_t value) volatile
12434     {
12435         word0 = value;
12436         return *this;
12437     }
12438 #endif
12439 };
12440 
12441 // weight_region_r - None
12442 struct weight_region_r
12443 {
12444 #ifndef __cplusplus
12445     union
12446     {
12447         struct
12448         {
12449             uint32_t value : 32; // 32-bit register value
12450         };
12451         uint32_t word;
12452     };
12453 #else
12454   private:
12455     uint32_t word0;
12456 
12457   public:
12458     CONSTEXPR weight_region_r() : word0(0) {}
12459     CONSTEXPR weight_region_r(uint32_t init) : word0(init) {}
12460     CONSTEXPR void operator=(uint32_t value)
12461     {
12462         word0 = value;
12463     }
12464     void operator=(uint32_t value) volatile
12465     {
12466         word0 = value;
12467     }
12468     CONSTEXPR operator uint32_t()
12469     {
12470         return word0;
12471     }
12472     operator uint32_t() volatile
12473     {
12474         return word0;
12475     }
12476     weight_region_r copy() volatile
12477     {
12478         return *this;
12479     }
12480     CONSTEXPR uint32_t get_value() const
12481     {
12482         uint32_t value = word0;
12483         return value;
12484     }
12485     uint32_t get_value() const volatile
12486     {
12487         uint32_t value = word0;
12488         return value;
12489     }
12490     CONSTEXPR weight_region_r &set_value(uint32_t value)
12491     {
12492         word0 = value;
12493         return *this;
12494     }
12495     volatile weight_region_r &set_value(uint32_t value) volatile
12496     {
12497         word0 = value;
12498         return *this;
12499     }
12500 #endif
12501 };
12502 
12503 // scale_region_r - None
12504 struct scale_region_r
12505 {
12506 #ifndef __cplusplus
12507     union
12508     {
12509         struct
12510         {
12511             uint32_t value : 32; // 32-bit register value
12512         };
12513         uint32_t word;
12514     };
12515 #else
12516   private:
12517     uint32_t word0;
12518 
12519   public:
12520     CONSTEXPR scale_region_r() : word0(0) {}
12521     CONSTEXPR scale_region_r(uint32_t init) : word0(init) {}
12522     CONSTEXPR void operator=(uint32_t value)
12523     {
12524         word0 = value;
12525     }
12526     void operator=(uint32_t value) volatile
12527     {
12528         word0 = value;
12529     }
12530     CONSTEXPR operator uint32_t()
12531     {
12532         return word0;
12533     }
12534     operator uint32_t() volatile
12535     {
12536         return word0;
12537     }
12538     scale_region_r copy() volatile
12539     {
12540         return *this;
12541     }
12542     CONSTEXPR uint32_t get_value() const
12543     {
12544         uint32_t value = word0;
12545         return value;
12546     }
12547     uint32_t get_value() const volatile
12548     {
12549         uint32_t value = word0;
12550         return value;
12551     }
12552     CONSTEXPR scale_region_r &set_value(uint32_t value)
12553     {
12554         word0 = value;
12555         return *this;
12556     }
12557     volatile scale_region_r &set_value(uint32_t value) volatile
12558     {
12559         word0 = value;
12560         return *this;
12561     }
12562 #endif
12563 };
12564 
12565 // ab_start_r - None
12566 struct ab_start_r
12567 {
12568 #ifndef __cplusplus
12569     union
12570     {
12571         struct
12572         {
12573             uint32_t value : 32; // 32-bit register value
12574         };
12575         uint32_t word;
12576     };
12577 #else
12578   private:
12579     uint32_t word0;
12580 
12581   public:
12582     CONSTEXPR ab_start_r() : word0(0) {}
12583     CONSTEXPR ab_start_r(uint32_t init) : word0(init) {}
12584     CONSTEXPR void operator=(uint32_t value)
12585     {
12586         word0 = value;
12587     }
12588     void operator=(uint32_t value) volatile
12589     {
12590         word0 = value;
12591     }
12592     CONSTEXPR operator uint32_t()
12593     {
12594         return word0;
12595     }
12596     operator uint32_t() volatile
12597     {
12598         return word0;
12599     }
12600     ab_start_r copy() volatile
12601     {
12602         return *this;
12603     }
12604     CONSTEXPR uint32_t get_value() const
12605     {
12606         uint32_t value = word0;
12607         return value;
12608     }
12609     uint32_t get_value() const volatile
12610     {
12611         uint32_t value = word0;
12612         return value;
12613     }
12614     CONSTEXPR ab_start_r &set_value(uint32_t value)
12615     {
12616         word0 = value;
12617         return *this;
12618     }
12619     volatile ab_start_r &set_value(uint32_t value) volatile
12620     {
12621         word0 = value;
12622         return *this;
12623     }
12624 #endif
12625 };
12626 
12627 // blockdep_r - None
12628 struct blockdep_r
12629 {
12630 #ifndef __cplusplus
12631     union
12632     {
12633         struct
12634         {
12635             uint32_t value : 32; // 32-bit register value
12636         };
12637         uint32_t word;
12638     };
12639 #else
12640   private:
12641     uint32_t word0;
12642 
12643   public:
12644     CONSTEXPR blockdep_r() : word0(0) {}
12645     CONSTEXPR blockdep_r(uint32_t init) : word0(init) {}
12646     CONSTEXPR void operator=(uint32_t value)
12647     {
12648         word0 = value;
12649     }
12650     void operator=(uint32_t value) volatile
12651     {
12652         word0 = value;
12653     }
12654     CONSTEXPR operator uint32_t()
12655     {
12656         return word0;
12657     }
12658     operator uint32_t() volatile
12659     {
12660         return word0;
12661     }
12662     blockdep_r copy() volatile
12663     {
12664         return *this;
12665     }
12666     CONSTEXPR uint32_t get_value() const
12667     {
12668         uint32_t value = word0;
12669         return value;
12670     }
12671     uint32_t get_value() const volatile
12672     {
12673         uint32_t value = word0;
12674         return value;
12675     }
12676     CONSTEXPR blockdep_r &set_value(uint32_t value)
12677     {
12678         word0 = value;
12679         return *this;
12680     }
12681     volatile blockdep_r &set_value(uint32_t value) volatile
12682     {
12683         word0 = value;
12684         return *this;
12685     }
12686 #endif
12687 };
12688 
12689 // dma0_src_region_r - None
12690 struct dma0_src_region_r
12691 {
12692 #ifndef __cplusplus
12693     union
12694     {
12695         struct
12696         {
12697             uint32_t value : 32; // 32-bit register value
12698         };
12699         uint32_t word;
12700     };
12701 #else
12702   private:
12703     uint32_t word0;
12704 
12705   public:
12706     CONSTEXPR dma0_src_region_r() : word0(0) {}
12707     CONSTEXPR dma0_src_region_r(uint32_t init) : word0(init) {}
12708     CONSTEXPR void operator=(uint32_t value)
12709     {
12710         word0 = value;
12711     }
12712     void operator=(uint32_t value) volatile
12713     {
12714         word0 = value;
12715     }
12716     CONSTEXPR operator uint32_t()
12717     {
12718         return word0;
12719     }
12720     operator uint32_t() volatile
12721     {
12722         return word0;
12723     }
12724     dma0_src_region_r copy() volatile
12725     {
12726         return *this;
12727     }
12728     CONSTEXPR uint32_t get_value() const
12729     {
12730         uint32_t value = word0;
12731         return value;
12732     }
12733     uint32_t get_value() const volatile
12734     {
12735         uint32_t value = word0;
12736         return value;
12737     }
12738     CONSTEXPR dma0_src_region_r &set_value(uint32_t value)
12739     {
12740         word0 = value;
12741         return *this;
12742     }
12743     volatile dma0_src_region_r &set_value(uint32_t value) volatile
12744     {
12745         word0 = value;
12746         return *this;
12747     }
12748 #endif
12749 };
12750 
12751 // dma0_dst_region_r - None
12752 struct dma0_dst_region_r
12753 {
12754 #ifndef __cplusplus
12755     union
12756     {
12757         struct
12758         {
12759             uint32_t value : 32; // 32-bit register value
12760         };
12761         uint32_t word;
12762     };
12763 #else
12764   private:
12765     uint32_t word0;
12766 
12767   public:
12768     CONSTEXPR dma0_dst_region_r() : word0(0) {}
12769     CONSTEXPR dma0_dst_region_r(uint32_t init) : word0(init) {}
12770     CONSTEXPR void operator=(uint32_t value)
12771     {
12772         word0 = value;
12773     }
12774     void operator=(uint32_t value) volatile
12775     {
12776         word0 = value;
12777     }
12778     CONSTEXPR operator uint32_t()
12779     {
12780         return word0;
12781     }
12782     operator uint32_t() volatile
12783     {
12784         return word0;
12785     }
12786     dma0_dst_region_r copy() volatile
12787     {
12788         return *this;
12789     }
12790     CONSTEXPR uint32_t get_value() const
12791     {
12792         uint32_t value = word0;
12793         return value;
12794     }
12795     uint32_t get_value() const volatile
12796     {
12797         uint32_t value = word0;
12798         return value;
12799     }
12800     CONSTEXPR dma0_dst_region_r &set_value(uint32_t value)
12801     {
12802         word0 = value;
12803         return *this;
12804     }
12805     volatile dma0_dst_region_r &set_value(uint32_t value) volatile
12806     {
12807         word0 = value;
12808         return *this;
12809     }
12810 #endif
12811 };
12812 
12813 // dma0_size0_r - None
12814 struct dma0_size0_r
12815 {
12816 #ifndef __cplusplus
12817     union
12818     {
12819         struct
12820         {
12821             uint32_t value : 32; // 32-bit register value
12822         };
12823         uint32_t word;
12824     };
12825 #else
12826   private:
12827     uint32_t word0;
12828 
12829   public:
12830     CONSTEXPR dma0_size0_r() : word0(0) {}
12831     CONSTEXPR dma0_size0_r(uint32_t init) : word0(init) {}
12832     CONSTEXPR void operator=(uint32_t value)
12833     {
12834         word0 = value;
12835     }
12836     void operator=(uint32_t value) volatile
12837     {
12838         word0 = value;
12839     }
12840     CONSTEXPR operator uint32_t()
12841     {
12842         return word0;
12843     }
12844     operator uint32_t() volatile
12845     {
12846         return word0;
12847     }
12848     dma0_size0_r copy() volatile
12849     {
12850         return *this;
12851     }
12852     CONSTEXPR uint32_t get_value() const
12853     {
12854         uint32_t value = word0;
12855         return value;
12856     }
12857     uint32_t get_value() const volatile
12858     {
12859         uint32_t value = word0;
12860         return value;
12861     }
12862     CONSTEXPR dma0_size0_r &set_value(uint32_t value)
12863     {
12864         word0 = value;
12865         return *this;
12866     }
12867     volatile dma0_size0_r &set_value(uint32_t value) volatile
12868     {
12869         word0 = value;
12870         return *this;
12871     }
12872 #endif
12873 };
12874 
12875 // dma0_size1_r - None
12876 struct dma0_size1_r
12877 {
12878 #ifndef __cplusplus
12879     union
12880     {
12881         struct
12882         {
12883             uint32_t value : 32; // 32-bit register value
12884         };
12885         uint32_t word;
12886     };
12887 #else
12888   private:
12889     uint32_t word0;
12890 
12891   public:
12892     CONSTEXPR dma0_size1_r() : word0(0) {}
12893     CONSTEXPR dma0_size1_r(uint32_t init) : word0(init) {}
12894     CONSTEXPR void operator=(uint32_t value)
12895     {
12896         word0 = value;
12897     }
12898     void operator=(uint32_t value) volatile
12899     {
12900         word0 = value;
12901     }
12902     CONSTEXPR operator uint32_t()
12903     {
12904         return word0;
12905     }
12906     operator uint32_t() volatile
12907     {
12908         return word0;
12909     }
12910     dma0_size1_r copy() volatile
12911     {
12912         return *this;
12913     }
12914     CONSTEXPR uint32_t get_value() const
12915     {
12916         uint32_t value = word0;
12917         return value;
12918     }
12919     uint32_t get_value() const volatile
12920     {
12921         uint32_t value = word0;
12922         return value;
12923     }
12924     CONSTEXPR dma0_size1_r &set_value(uint32_t value)
12925     {
12926         word0 = value;
12927         return *this;
12928     }
12929     volatile dma0_size1_r &set_value(uint32_t value) volatile
12930     {
12931         word0 = value;
12932         return *this;
12933     }
12934 #endif
12935 };
12936 
12937 // ifm2_broadcast_r - None
12938 struct ifm2_broadcast_r
12939 {
12940 #ifndef __cplusplus
12941     union
12942     {
12943         struct
12944         {
12945             uint32_t value : 32; // 32-bit register value
12946         };
12947         uint32_t word;
12948     };
12949 #else
12950   private:
12951     uint32_t word0;
12952 
12953   public:
12954     CONSTEXPR ifm2_broadcast_r() : word0(0) {}
12955     CONSTEXPR ifm2_broadcast_r(uint32_t init) : word0(init) {}
12956     CONSTEXPR void operator=(uint32_t value)
12957     {
12958         word0 = value;
12959     }
12960     void operator=(uint32_t value) volatile
12961     {
12962         word0 = value;
12963     }
12964     CONSTEXPR operator uint32_t()
12965     {
12966         return word0;
12967     }
12968     operator uint32_t() volatile
12969     {
12970         return word0;
12971     }
12972     ifm2_broadcast_r copy() volatile
12973     {
12974         return *this;
12975     }
12976     CONSTEXPR uint32_t get_value() const
12977     {
12978         uint32_t value = word0;
12979         return value;
12980     }
12981     uint32_t get_value() const volatile
12982     {
12983         uint32_t value = word0;
12984         return value;
12985     }
12986     CONSTEXPR ifm2_broadcast_r &set_value(uint32_t value)
12987     {
12988         word0 = value;
12989         return *this;
12990     }
12991     volatile ifm2_broadcast_r &set_value(uint32_t value) volatile
12992     {
12993         word0 = value;
12994         return *this;
12995     }
12996 #endif
12997 };
12998 
12999 // ifm2_scalar_r - None
13000 struct ifm2_scalar_r
13001 {
13002 #ifndef __cplusplus
13003     union
13004     {
13005         struct
13006         {
13007             uint32_t value : 32; // 32-bit register value
13008         };
13009         uint32_t word;
13010     };
13011 #else
13012   private:
13013     uint32_t word0;
13014 
13015   public:
13016     CONSTEXPR ifm2_scalar_r() : word0(0) {}
13017     CONSTEXPR ifm2_scalar_r(uint32_t init) : word0(init) {}
13018     CONSTEXPR void operator=(uint32_t value)
13019     {
13020         word0 = value;
13021     }
13022     void operator=(uint32_t value) volatile
13023     {
13024         word0 = value;
13025     }
13026     CONSTEXPR operator uint32_t()
13027     {
13028         return word0;
13029     }
13030     operator uint32_t() volatile
13031     {
13032         return word0;
13033     }
13034     ifm2_scalar_r copy() volatile
13035     {
13036         return *this;
13037     }
13038     CONSTEXPR uint32_t get_value() const
13039     {
13040         uint32_t value = word0;
13041         return value;
13042     }
13043     uint32_t get_value() const volatile
13044     {
13045         uint32_t value = word0;
13046         return value;
13047     }
13048     CONSTEXPR ifm2_scalar_r &set_value(uint32_t value)
13049     {
13050         word0 = value;
13051         return *this;
13052     }
13053     volatile ifm2_scalar_r &set_value(uint32_t value) volatile
13054     {
13055         word0 = value;
13056         return *this;
13057     }
13058 #endif
13059 };
13060 
13061 // ifm2_precision_r - None
13062 struct ifm2_precision_r
13063 {
13064 #ifndef __cplusplus
13065     union
13066     {
13067         struct
13068         {
13069             uint32_t value : 32; // 32-bit register value
13070         };
13071         uint32_t word;
13072     };
13073 #else
13074   private:
13075     uint32_t word0;
13076 
13077   public:
13078     CONSTEXPR ifm2_precision_r() : word0(0) {}
13079     CONSTEXPR ifm2_precision_r(uint32_t init) : word0(init) {}
13080     CONSTEXPR void operator=(uint32_t value)
13081     {
13082         word0 = value;
13083     }
13084     void operator=(uint32_t value) volatile
13085     {
13086         word0 = value;
13087     }
13088     CONSTEXPR operator uint32_t()
13089     {
13090         return word0;
13091     }
13092     operator uint32_t() volatile
13093     {
13094         return word0;
13095     }
13096     ifm2_precision_r copy() volatile
13097     {
13098         return *this;
13099     }
13100     CONSTEXPR uint32_t get_value() const
13101     {
13102         uint32_t value = word0;
13103         return value;
13104     }
13105     uint32_t get_value() const volatile
13106     {
13107         uint32_t value = word0;
13108         return value;
13109     }
13110     CONSTEXPR ifm2_precision_r &set_value(uint32_t value)
13111     {
13112         word0 = value;
13113         return *this;
13114     }
13115     volatile ifm2_precision_r &set_value(uint32_t value) volatile
13116     {
13117         word0 = value;
13118         return *this;
13119     }
13120 #endif
13121 };
13122 
13123 // ifm2_zero_point_r - None
13124 struct ifm2_zero_point_r
13125 {
13126 #ifndef __cplusplus
13127     union
13128     {
13129         struct
13130         {
13131             uint32_t value : 32; // 32-bit register value
13132         };
13133         uint32_t word;
13134     };
13135 #else
13136   private:
13137     uint32_t word0;
13138 
13139   public:
13140     CONSTEXPR ifm2_zero_point_r() : word0(0) {}
13141     CONSTEXPR ifm2_zero_point_r(uint32_t init) : word0(init) {}
13142     CONSTEXPR void operator=(uint32_t value)
13143     {
13144         word0 = value;
13145     }
13146     void operator=(uint32_t value) volatile
13147     {
13148         word0 = value;
13149     }
13150     CONSTEXPR operator uint32_t()
13151     {
13152         return word0;
13153     }
13154     operator uint32_t() volatile
13155     {
13156         return word0;
13157     }
13158     ifm2_zero_point_r copy() volatile
13159     {
13160         return *this;
13161     }
13162     CONSTEXPR uint32_t get_value() const
13163     {
13164         uint32_t value = word0;
13165         return value;
13166     }
13167     uint32_t get_value() const volatile
13168     {
13169         uint32_t value = word0;
13170         return value;
13171     }
13172     CONSTEXPR ifm2_zero_point_r &set_value(uint32_t value)
13173     {
13174         word0 = value;
13175         return *this;
13176     }
13177     volatile ifm2_zero_point_r &set_value(uint32_t value) volatile
13178     {
13179         word0 = value;
13180         return *this;
13181     }
13182 #endif
13183 };
13184 
13185 // ifm2_width0_m1_r - None
13186 struct ifm2_width0_m1_r
13187 {
13188 #ifndef __cplusplus
13189     union
13190     {
13191         struct
13192         {
13193             uint32_t value : 32; // 32-bit register value
13194         };
13195         uint32_t word;
13196     };
13197 #else
13198   private:
13199     uint32_t word0;
13200 
13201   public:
13202     CONSTEXPR ifm2_width0_m1_r() : word0(0) {}
13203     CONSTEXPR ifm2_width0_m1_r(uint32_t init) : word0(init) {}
13204     CONSTEXPR void operator=(uint32_t value)
13205     {
13206         word0 = value;
13207     }
13208     void operator=(uint32_t value) volatile
13209     {
13210         word0 = value;
13211     }
13212     CONSTEXPR operator uint32_t()
13213     {
13214         return word0;
13215     }
13216     operator uint32_t() volatile
13217     {
13218         return word0;
13219     }
13220     ifm2_width0_m1_r copy() volatile
13221     {
13222         return *this;
13223     }
13224     CONSTEXPR uint32_t get_value() const
13225     {
13226         uint32_t value = word0;
13227         return value;
13228     }
13229     uint32_t get_value() const volatile
13230     {
13231         uint32_t value = word0;
13232         return value;
13233     }
13234     CONSTEXPR ifm2_width0_m1_r &set_value(uint32_t value)
13235     {
13236         word0 = value;
13237         return *this;
13238     }
13239     volatile ifm2_width0_m1_r &set_value(uint32_t value) volatile
13240     {
13241         word0 = value;
13242         return *this;
13243     }
13244 #endif
13245 };
13246 
13247 // ifm2_height0_m1_r - None
13248 struct ifm2_height0_m1_r
13249 {
13250 #ifndef __cplusplus
13251     union
13252     {
13253         struct
13254         {
13255             uint32_t value : 32; // 32-bit register value
13256         };
13257         uint32_t word;
13258     };
13259 #else
13260   private:
13261     uint32_t word0;
13262 
13263   public:
13264     CONSTEXPR ifm2_height0_m1_r() : word0(0) {}
13265     CONSTEXPR ifm2_height0_m1_r(uint32_t init) : word0(init) {}
13266     CONSTEXPR void operator=(uint32_t value)
13267     {
13268         word0 = value;
13269     }
13270     void operator=(uint32_t value) volatile
13271     {
13272         word0 = value;
13273     }
13274     CONSTEXPR operator uint32_t()
13275     {
13276         return word0;
13277     }
13278     operator uint32_t() volatile
13279     {
13280         return word0;
13281     }
13282     ifm2_height0_m1_r copy() volatile
13283     {
13284         return *this;
13285     }
13286     CONSTEXPR uint32_t get_value() const
13287     {
13288         uint32_t value = word0;
13289         return value;
13290     }
13291     uint32_t get_value() const volatile
13292     {
13293         uint32_t value = word0;
13294         return value;
13295     }
13296     CONSTEXPR ifm2_height0_m1_r &set_value(uint32_t value)
13297     {
13298         word0 = value;
13299         return *this;
13300     }
13301     volatile ifm2_height0_m1_r &set_value(uint32_t value) volatile
13302     {
13303         word0 = value;
13304         return *this;
13305     }
13306 #endif
13307 };
13308 
13309 // ifm2_height1_m1_r - None
13310 struct ifm2_height1_m1_r
13311 {
13312 #ifndef __cplusplus
13313     union
13314     {
13315         struct
13316         {
13317             uint32_t value : 32; // 32-bit register value
13318         };
13319         uint32_t word;
13320     };
13321 #else
13322   private:
13323     uint32_t word0;
13324 
13325   public:
13326     CONSTEXPR ifm2_height1_m1_r() : word0(0) {}
13327     CONSTEXPR ifm2_height1_m1_r(uint32_t init) : word0(init) {}
13328     CONSTEXPR void operator=(uint32_t value)
13329     {
13330         word0 = value;
13331     }
13332     void operator=(uint32_t value) volatile
13333     {
13334         word0 = value;
13335     }
13336     CONSTEXPR operator uint32_t()
13337     {
13338         return word0;
13339     }
13340     operator uint32_t() volatile
13341     {
13342         return word0;
13343     }
13344     ifm2_height1_m1_r copy() volatile
13345     {
13346         return *this;
13347     }
13348     CONSTEXPR uint32_t get_value() const
13349     {
13350         uint32_t value = word0;
13351         return value;
13352     }
13353     uint32_t get_value() const volatile
13354     {
13355         uint32_t value = word0;
13356         return value;
13357     }
13358     CONSTEXPR ifm2_height1_m1_r &set_value(uint32_t value)
13359     {
13360         word0 = value;
13361         return *this;
13362     }
13363     volatile ifm2_height1_m1_r &set_value(uint32_t value) volatile
13364     {
13365         word0 = value;
13366         return *this;
13367     }
13368 #endif
13369 };
13370 
13371 // ifm2_ib_start_r - None
13372 struct ifm2_ib_start_r
13373 {
13374 #ifndef __cplusplus
13375     union
13376     {
13377         struct
13378         {
13379             uint32_t value : 32; // 32-bit register value
13380         };
13381         uint32_t word;
13382     };
13383 #else
13384   private:
13385     uint32_t word0;
13386 
13387   public:
13388     CONSTEXPR ifm2_ib_start_r() : word0(0) {}
13389     CONSTEXPR ifm2_ib_start_r(uint32_t init) : word0(init) {}
13390     CONSTEXPR void operator=(uint32_t value)
13391     {
13392         word0 = value;
13393     }
13394     void operator=(uint32_t value) volatile
13395     {
13396         word0 = value;
13397     }
13398     CONSTEXPR operator uint32_t()
13399     {
13400         return word0;
13401     }
13402     operator uint32_t() volatile
13403     {
13404         return word0;
13405     }
13406     ifm2_ib_start_r copy() volatile
13407     {
13408         return *this;
13409     }
13410     CONSTEXPR uint32_t get_value() const
13411     {
13412         uint32_t value = word0;
13413         return value;
13414     }
13415     uint32_t get_value() const volatile
13416     {
13417         uint32_t value = word0;
13418         return value;
13419     }
13420     CONSTEXPR ifm2_ib_start_r &set_value(uint32_t value)
13421     {
13422         word0 = value;
13423         return *this;
13424     }
13425     volatile ifm2_ib_start_r &set_value(uint32_t value) volatile
13426     {
13427         word0 = value;
13428         return *this;
13429     }
13430 #endif
13431 };
13432 
13433 // ifm2_region_r - None
13434 struct ifm2_region_r
13435 {
13436 #ifndef __cplusplus
13437     union
13438     {
13439         struct
13440         {
13441             uint32_t value : 32; // 32-bit register value
13442         };
13443         uint32_t word;
13444     };
13445 #else
13446   private:
13447     uint32_t word0;
13448 
13449   public:
13450     CONSTEXPR ifm2_region_r() : word0(0) {}
13451     CONSTEXPR ifm2_region_r(uint32_t init) : word0(init) {}
13452     CONSTEXPR void operator=(uint32_t value)
13453     {
13454         word0 = value;
13455     }
13456     void operator=(uint32_t value) volatile
13457     {
13458         word0 = value;
13459     }
13460     CONSTEXPR operator uint32_t()
13461     {
13462         return word0;
13463     }
13464     operator uint32_t() volatile
13465     {
13466         return word0;
13467     }
13468     ifm2_region_r copy() volatile
13469     {
13470         return *this;
13471     }
13472     CONSTEXPR uint32_t get_value() const
13473     {
13474         uint32_t value = word0;
13475         return value;
13476     }
13477     uint32_t get_value() const volatile
13478     {
13479         uint32_t value = word0;
13480         return value;
13481     }
13482     CONSTEXPR ifm2_region_r &set_value(uint32_t value)
13483     {
13484         word0 = value;
13485         return *this;
13486     }
13487     volatile ifm2_region_r &set_value(uint32_t value) volatile
13488     {
13489         word0 = value;
13490         return *this;
13491     }
13492 #endif
13493 };
13494 
13495 // ifm_base0_r - None
13496 struct ifm_base0_r
13497 {
13498 #ifndef __cplusplus
13499     union
13500     {
13501         struct
13502         {
13503             uint32_t value_LO : 32; // 64-bit register value - LSB
13504             uint32_t value_HI : 32; // 64-bit register value - MSB
13505         };
13506         uint32_t word[2];
13507     };
13508 #else
13509   private:
13510     uint32_t word0;
13511     uint32_t word1;
13512 
13513   public:
13514     CONSTEXPR ifm_base0_r() : word0(0), word1(0) {}
13515     CONSTEXPR ifm_base0_r(uint64_t init) :
13516         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13517         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13518     {
13519     }
13520     CONSTEXPR void operator=(uint64_t value)
13521     {
13522         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13523         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13524     }
13525     void operator=(uint64_t value) volatile
13526     {
13527         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13528         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13529     }
13530     CONSTEXPR operator uint64_t()
13531     {
13532         return (static_cast<uint64_t>(word1) << 32) | word0;
13533     }
13534     operator uint64_t() volatile
13535     {
13536         return (static_cast<uint64_t>(word1) << 32) | word0;
13537     }
13538     ifm_base0_r copy() volatile
13539     {
13540         return *this;
13541     }
13542 #endif
13543 };
13544 
13545 // ifm_base1_r - None
13546 struct ifm_base1_r
13547 {
13548 #ifndef __cplusplus
13549     union
13550     {
13551         struct
13552         {
13553             uint32_t value_LO : 32; // 64-bit register value - LSB
13554             uint32_t value_HI : 32; // 64-bit register value - MSB
13555         };
13556         uint32_t word[2];
13557     };
13558 #else
13559   private:
13560     uint32_t word0;
13561     uint32_t word1;
13562 
13563   public:
13564     CONSTEXPR ifm_base1_r() : word0(0), word1(0) {}
13565     CONSTEXPR ifm_base1_r(uint64_t init) :
13566         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13567         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13568     {
13569     }
13570     CONSTEXPR void operator=(uint64_t value)
13571     {
13572         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13573         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13574     }
13575     void operator=(uint64_t value) volatile
13576     {
13577         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13578         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13579     }
13580     CONSTEXPR operator uint64_t()
13581     {
13582         return (static_cast<uint64_t>(word1) << 32) | word0;
13583     }
13584     operator uint64_t() volatile
13585     {
13586         return (static_cast<uint64_t>(word1) << 32) | word0;
13587     }
13588     ifm_base1_r copy() volatile
13589     {
13590         return *this;
13591     }
13592 #endif
13593 };
13594 
13595 // ifm_base2_r - None
13596 struct ifm_base2_r
13597 {
13598 #ifndef __cplusplus
13599     union
13600     {
13601         struct
13602         {
13603             uint32_t value_LO : 32; // 64-bit register value - LSB
13604             uint32_t value_HI : 32; // 64-bit register value - MSB
13605         };
13606         uint32_t word[2];
13607     };
13608 #else
13609   private:
13610     uint32_t word0;
13611     uint32_t word1;
13612 
13613   public:
13614     CONSTEXPR ifm_base2_r() : word0(0), word1(0) {}
13615     CONSTEXPR ifm_base2_r(uint64_t init) :
13616         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13617         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13618     {
13619     }
13620     CONSTEXPR void operator=(uint64_t value)
13621     {
13622         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13623         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13624     }
13625     void operator=(uint64_t value) volatile
13626     {
13627         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13628         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13629     }
13630     CONSTEXPR operator uint64_t()
13631     {
13632         return (static_cast<uint64_t>(word1) << 32) | word0;
13633     }
13634     operator uint64_t() volatile
13635     {
13636         return (static_cast<uint64_t>(word1) << 32) | word0;
13637     }
13638     ifm_base2_r copy() volatile
13639     {
13640         return *this;
13641     }
13642 #endif
13643 };
13644 
13645 // ifm_base3_r - None
13646 struct ifm_base3_r
13647 {
13648 #ifndef __cplusplus
13649     union
13650     {
13651         struct
13652         {
13653             uint32_t value_LO : 32; // 64-bit register value - LSB
13654             uint32_t value_HI : 32; // 64-bit register value - MSB
13655         };
13656         uint32_t word[2];
13657     };
13658 #else
13659   private:
13660     uint32_t word0;
13661     uint32_t word1;
13662 
13663   public:
13664     CONSTEXPR ifm_base3_r() : word0(0), word1(0) {}
13665     CONSTEXPR ifm_base3_r(uint64_t init) :
13666         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13667         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13668     {
13669     }
13670     CONSTEXPR void operator=(uint64_t value)
13671     {
13672         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13673         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13674     }
13675     void operator=(uint64_t value) volatile
13676     {
13677         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13678         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13679     }
13680     CONSTEXPR operator uint64_t()
13681     {
13682         return (static_cast<uint64_t>(word1) << 32) | word0;
13683     }
13684     operator uint64_t() volatile
13685     {
13686         return (static_cast<uint64_t>(word1) << 32) | word0;
13687     }
13688     ifm_base3_r copy() volatile
13689     {
13690         return *this;
13691     }
13692 #endif
13693 };
13694 
13695 // ifm_stride_x_r - None
13696 struct ifm_stride_x_r
13697 {
13698 #ifndef __cplusplus
13699     union
13700     {
13701         struct
13702         {
13703             uint32_t value_LO : 32; // 64-bit register value - LSB
13704             uint32_t value_HI : 32; // 64-bit register value - MSB
13705         };
13706         uint32_t word[2];
13707     };
13708 #else
13709   private:
13710     uint32_t word0;
13711     uint32_t word1;
13712 
13713   public:
13714     CONSTEXPR ifm_stride_x_r() : word0(0), word1(0) {}
13715     CONSTEXPR ifm_stride_x_r(uint64_t init) :
13716         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13717         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13718     {
13719     }
13720     CONSTEXPR void operator=(uint64_t value)
13721     {
13722         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13723         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13724     }
13725     void operator=(uint64_t value) volatile
13726     {
13727         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13728         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13729     }
13730     CONSTEXPR operator uint64_t()
13731     {
13732         return (static_cast<uint64_t>(word1) << 32) | word0;
13733     }
13734     operator uint64_t() volatile
13735     {
13736         return (static_cast<uint64_t>(word1) << 32) | word0;
13737     }
13738     ifm_stride_x_r copy() volatile
13739     {
13740         return *this;
13741     }
13742 #endif
13743 };
13744 
13745 // ifm_stride_y_r - None
13746 struct ifm_stride_y_r
13747 {
13748 #ifndef __cplusplus
13749     union
13750     {
13751         struct
13752         {
13753             uint32_t value_LO : 32; // 64-bit register value - LSB
13754             uint32_t value_HI : 32; // 64-bit register value - MSB
13755         };
13756         uint32_t word[2];
13757     };
13758 #else
13759   private:
13760     uint32_t word0;
13761     uint32_t word1;
13762 
13763   public:
13764     CONSTEXPR ifm_stride_y_r() : word0(0), word1(0) {}
13765     CONSTEXPR ifm_stride_y_r(uint64_t init) :
13766         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13767         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13768     {
13769     }
13770     CONSTEXPR void operator=(uint64_t value)
13771     {
13772         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13773         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13774     }
13775     void operator=(uint64_t value) volatile
13776     {
13777         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13778         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13779     }
13780     CONSTEXPR operator uint64_t()
13781     {
13782         return (static_cast<uint64_t>(word1) << 32) | word0;
13783     }
13784     operator uint64_t() volatile
13785     {
13786         return (static_cast<uint64_t>(word1) << 32) | word0;
13787     }
13788     ifm_stride_y_r copy() volatile
13789     {
13790         return *this;
13791     }
13792 #endif
13793 };
13794 
13795 // ifm_stride_c_r - None
13796 struct ifm_stride_c_r
13797 {
13798 #ifndef __cplusplus
13799     union
13800     {
13801         struct
13802         {
13803             uint32_t value_LO : 32; // 64-bit register value - LSB
13804             uint32_t value_HI : 32; // 64-bit register value - MSB
13805         };
13806         uint32_t word[2];
13807     };
13808 #else
13809   private:
13810     uint32_t word0;
13811     uint32_t word1;
13812 
13813   public:
13814     CONSTEXPR ifm_stride_c_r() : word0(0), word1(0) {}
13815     CONSTEXPR ifm_stride_c_r(uint64_t init) :
13816         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13817         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13818     {
13819     }
13820     CONSTEXPR void operator=(uint64_t value)
13821     {
13822         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13823         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13824     }
13825     void operator=(uint64_t value) volatile
13826     {
13827         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13828         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13829     }
13830     CONSTEXPR operator uint64_t()
13831     {
13832         return (static_cast<uint64_t>(word1) << 32) | word0;
13833     }
13834     operator uint64_t() volatile
13835     {
13836         return (static_cast<uint64_t>(word1) << 32) | word0;
13837     }
13838     ifm_stride_c_r copy() volatile
13839     {
13840         return *this;
13841     }
13842 #endif
13843 };
13844 
13845 // ofm_base0_r - None
13846 struct ofm_base0_r
13847 {
13848 #ifndef __cplusplus
13849     union
13850     {
13851         struct
13852         {
13853             uint32_t value_LO : 32; // 64-bit register value - LSB
13854             uint32_t value_HI : 32; // 64-bit register value - MSB
13855         };
13856         uint32_t word[2];
13857     };
13858 #else
13859   private:
13860     uint32_t word0;
13861     uint32_t word1;
13862 
13863   public:
13864     CONSTEXPR ofm_base0_r() : word0(0), word1(0) {}
13865     CONSTEXPR ofm_base0_r(uint64_t init) :
13866         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13867         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13868     {
13869     }
13870     CONSTEXPR void operator=(uint64_t value)
13871     {
13872         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13873         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13874     }
13875     void operator=(uint64_t value) volatile
13876     {
13877         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13878         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13879     }
13880     CONSTEXPR operator uint64_t()
13881     {
13882         return (static_cast<uint64_t>(word1) << 32) | word0;
13883     }
13884     operator uint64_t() volatile
13885     {
13886         return (static_cast<uint64_t>(word1) << 32) | word0;
13887     }
13888     ofm_base0_r copy() volatile
13889     {
13890         return *this;
13891     }
13892 #endif
13893 };
13894 
13895 // ofm_base1_r - None
13896 struct ofm_base1_r
13897 {
13898 #ifndef __cplusplus
13899     union
13900     {
13901         struct
13902         {
13903             uint32_t value_LO : 32; // 64-bit register value - LSB
13904             uint32_t value_HI : 32; // 64-bit register value - MSB
13905         };
13906         uint32_t word[2];
13907     };
13908 #else
13909   private:
13910     uint32_t word0;
13911     uint32_t word1;
13912 
13913   public:
13914     CONSTEXPR ofm_base1_r() : word0(0), word1(0) {}
13915     CONSTEXPR ofm_base1_r(uint64_t init) :
13916         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13917         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13918     {
13919     }
13920     CONSTEXPR void operator=(uint64_t value)
13921     {
13922         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13923         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13924     }
13925     void operator=(uint64_t value) volatile
13926     {
13927         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13928         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13929     }
13930     CONSTEXPR operator uint64_t()
13931     {
13932         return (static_cast<uint64_t>(word1) << 32) | word0;
13933     }
13934     operator uint64_t() volatile
13935     {
13936         return (static_cast<uint64_t>(word1) << 32) | word0;
13937     }
13938     ofm_base1_r copy() volatile
13939     {
13940         return *this;
13941     }
13942 #endif
13943 };
13944 
13945 // ofm_base2_r - None
13946 struct ofm_base2_r
13947 {
13948 #ifndef __cplusplus
13949     union
13950     {
13951         struct
13952         {
13953             uint32_t value_LO : 32; // 64-bit register value - LSB
13954             uint32_t value_HI : 32; // 64-bit register value - MSB
13955         };
13956         uint32_t word[2];
13957     };
13958 #else
13959   private:
13960     uint32_t word0;
13961     uint32_t word1;
13962 
13963   public:
13964     CONSTEXPR ofm_base2_r() : word0(0), word1(0) {}
13965     CONSTEXPR ofm_base2_r(uint64_t init) :
13966         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13967         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13968     {
13969     }
13970     CONSTEXPR void operator=(uint64_t value)
13971     {
13972         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13973         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13974     }
13975     void operator=(uint64_t value) volatile
13976     {
13977         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13978         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13979     }
13980     CONSTEXPR operator uint64_t()
13981     {
13982         return (static_cast<uint64_t>(word1) << 32) | word0;
13983     }
13984     operator uint64_t() volatile
13985     {
13986         return (static_cast<uint64_t>(word1) << 32) | word0;
13987     }
13988     ofm_base2_r copy() volatile
13989     {
13990         return *this;
13991     }
13992 #endif
13993 };
13994 
13995 // ofm_base3_r - None
13996 struct ofm_base3_r
13997 {
13998 #ifndef __cplusplus
13999     union
14000     {
14001         struct
14002         {
14003             uint32_t value_LO : 32; // 64-bit register value - LSB
14004             uint32_t value_HI : 32; // 64-bit register value - MSB
14005         };
14006         uint32_t word[2];
14007     };
14008 #else
14009   private:
14010     uint32_t word0;
14011     uint32_t word1;
14012 
14013   public:
14014     CONSTEXPR ofm_base3_r() : word0(0), word1(0) {}
14015     CONSTEXPR ofm_base3_r(uint64_t init) :
14016         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14017         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14018     {
14019     }
14020     CONSTEXPR void operator=(uint64_t value)
14021     {
14022         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14023         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14024     }
14025     void operator=(uint64_t value) volatile
14026     {
14027         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14028         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14029     }
14030     CONSTEXPR operator uint64_t()
14031     {
14032         return (static_cast<uint64_t>(word1) << 32) | word0;
14033     }
14034     operator uint64_t() volatile
14035     {
14036         return (static_cast<uint64_t>(word1) << 32) | word0;
14037     }
14038     ofm_base3_r copy() volatile
14039     {
14040         return *this;
14041     }
14042 #endif
14043 };
14044 
14045 // ofm_stride_x_r - None
14046 struct ofm_stride_x_r
14047 {
14048 #ifndef __cplusplus
14049     union
14050     {
14051         struct
14052         {
14053             uint32_t value_LO : 32; // 64-bit register value - LSB
14054             uint32_t value_HI : 32; // 64-bit register value - MSB
14055         };
14056         uint32_t word[2];
14057     };
14058 #else
14059   private:
14060     uint32_t word0;
14061     uint32_t word1;
14062 
14063   public:
14064     CONSTEXPR ofm_stride_x_r() : word0(0), word1(0) {}
14065     CONSTEXPR ofm_stride_x_r(uint64_t init) :
14066         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14067         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14068     {
14069     }
14070     CONSTEXPR void operator=(uint64_t value)
14071     {
14072         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14073         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14074     }
14075     void operator=(uint64_t value) volatile
14076     {
14077         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14078         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14079     }
14080     CONSTEXPR operator uint64_t()
14081     {
14082         return (static_cast<uint64_t>(word1) << 32) | word0;
14083     }
14084     operator uint64_t() volatile
14085     {
14086         return (static_cast<uint64_t>(word1) << 32) | word0;
14087     }
14088     ofm_stride_x_r copy() volatile
14089     {
14090         return *this;
14091     }
14092 #endif
14093 };
14094 
14095 // ofm_stride_y_r - None
14096 struct ofm_stride_y_r
14097 {
14098 #ifndef __cplusplus
14099     union
14100     {
14101         struct
14102         {
14103             uint32_t value_LO : 32; // 64-bit register value - LSB
14104             uint32_t value_HI : 32; // 64-bit register value - MSB
14105         };
14106         uint32_t word[2];
14107     };
14108 #else
14109   private:
14110     uint32_t word0;
14111     uint32_t word1;
14112 
14113   public:
14114     CONSTEXPR ofm_stride_y_r() : word0(0), word1(0) {}
14115     CONSTEXPR ofm_stride_y_r(uint64_t init) :
14116         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14117         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14118     {
14119     }
14120     CONSTEXPR void operator=(uint64_t value)
14121     {
14122         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14123         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14124     }
14125     void operator=(uint64_t value) volatile
14126     {
14127         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14128         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14129     }
14130     CONSTEXPR operator uint64_t()
14131     {
14132         return (static_cast<uint64_t>(word1) << 32) | word0;
14133     }
14134     operator uint64_t() volatile
14135     {
14136         return (static_cast<uint64_t>(word1) << 32) | word0;
14137     }
14138     ofm_stride_y_r copy() volatile
14139     {
14140         return *this;
14141     }
14142 #endif
14143 };
14144 
14145 // ofm_stride_c_r - None
14146 struct ofm_stride_c_r
14147 {
14148 #ifndef __cplusplus
14149     union
14150     {
14151         struct
14152         {
14153             uint32_t value_LO : 32; // 64-bit register value - LSB
14154             uint32_t value_HI : 32; // 64-bit register value - MSB
14155         };
14156         uint32_t word[2];
14157     };
14158 #else
14159   private:
14160     uint32_t word0;
14161     uint32_t word1;
14162 
14163   public:
14164     CONSTEXPR ofm_stride_c_r() : word0(0), word1(0) {}
14165     CONSTEXPR ofm_stride_c_r(uint64_t init) :
14166         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14167         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14168     {
14169     }
14170     CONSTEXPR void operator=(uint64_t value)
14171     {
14172         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14173         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14174     }
14175     void operator=(uint64_t value) volatile
14176     {
14177         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14178         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14179     }
14180     CONSTEXPR operator uint64_t()
14181     {
14182         return (static_cast<uint64_t>(word1) << 32) | word0;
14183     }
14184     operator uint64_t() volatile
14185     {
14186         return (static_cast<uint64_t>(word1) << 32) | word0;
14187     }
14188     ofm_stride_c_r copy() volatile
14189     {
14190         return *this;
14191     }
14192 #endif
14193 };
14194 
14195 // weight_base_r - None
14196 struct weight_base_r
14197 {
14198 #ifndef __cplusplus
14199     union
14200     {
14201         struct
14202         {
14203             uint32_t value_LO : 32; // 64-bit register value - LSB
14204             uint32_t value_HI : 32; // 64-bit register value - MSB
14205         };
14206         uint32_t word[2];
14207     };
14208 #else
14209   private:
14210     uint32_t word0;
14211     uint32_t word1;
14212 
14213   public:
14214     CONSTEXPR weight_base_r() : word0(0), word1(0) {}
14215     CONSTEXPR weight_base_r(uint64_t init) :
14216         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14217         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14218     {
14219     }
14220     CONSTEXPR void operator=(uint64_t value)
14221     {
14222         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14223         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14224     }
14225     void operator=(uint64_t value) volatile
14226     {
14227         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14228         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14229     }
14230     CONSTEXPR operator uint64_t()
14231     {
14232         return (static_cast<uint64_t>(word1) << 32) | word0;
14233     }
14234     operator uint64_t() volatile
14235     {
14236         return (static_cast<uint64_t>(word1) << 32) | word0;
14237     }
14238     weight_base_r copy() volatile
14239     {
14240         return *this;
14241     }
14242 #endif
14243 };
14244 
14245 // weight_length_r - None
14246 struct weight_length_r
14247 {
14248 #ifndef __cplusplus
14249     union
14250     {
14251         struct
14252         {
14253             uint32_t value_LO : 32; // 64-bit register value - LSB
14254             uint32_t value_HI : 32; // 64-bit register value - MSB
14255         };
14256         uint32_t word[2];
14257     };
14258 #else
14259   private:
14260     uint32_t word0;
14261     uint32_t word1;
14262 
14263   public:
14264     CONSTEXPR weight_length_r() : word0(0), word1(0) {}
14265     CONSTEXPR weight_length_r(uint64_t init) :
14266         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14267         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14268     {
14269     }
14270     CONSTEXPR void operator=(uint64_t value)
14271     {
14272         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14273         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14274     }
14275     void operator=(uint64_t value) volatile
14276     {
14277         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14278         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14279     }
14280     CONSTEXPR operator uint64_t()
14281     {
14282         return (static_cast<uint64_t>(word1) << 32) | word0;
14283     }
14284     operator uint64_t() volatile
14285     {
14286         return (static_cast<uint64_t>(word1) << 32) | word0;
14287     }
14288     weight_length_r copy() volatile
14289     {
14290         return *this;
14291     }
14292 #endif
14293 };
14294 
14295 // scale_base_r - None
14296 struct scale_base_r
14297 {
14298 #ifndef __cplusplus
14299     union
14300     {
14301         struct
14302         {
14303             uint32_t value_LO : 32; // 64-bit register value - LSB
14304             uint32_t value_HI : 32; // 64-bit register value - MSB
14305         };
14306         uint32_t word[2];
14307     };
14308 #else
14309   private:
14310     uint32_t word0;
14311     uint32_t word1;
14312 
14313   public:
14314     CONSTEXPR scale_base_r() : word0(0), word1(0) {}
14315     CONSTEXPR scale_base_r(uint64_t init) :
14316         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14317         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14318     {
14319     }
14320     CONSTEXPR void operator=(uint64_t value)
14321     {
14322         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14323         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14324     }
14325     void operator=(uint64_t value) volatile
14326     {
14327         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14328         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14329     }
14330     CONSTEXPR operator uint64_t()
14331     {
14332         return (static_cast<uint64_t>(word1) << 32) | word0;
14333     }
14334     operator uint64_t() volatile
14335     {
14336         return (static_cast<uint64_t>(word1) << 32) | word0;
14337     }
14338     scale_base_r copy() volatile
14339     {
14340         return *this;
14341     }
14342 #endif
14343 };
14344 
14345 // scale_length_r - None
14346 struct scale_length_r
14347 {
14348 #ifndef __cplusplus
14349     union
14350     {
14351         struct
14352         {
14353             uint32_t value_LO : 32; // 64-bit register value - LSB
14354             uint32_t value_HI : 32; // 64-bit register value - MSB
14355         };
14356         uint32_t word[2];
14357     };
14358 #else
14359   private:
14360     uint32_t word0;
14361     uint32_t word1;
14362 
14363   public:
14364     CONSTEXPR scale_length_r() : word0(0), word1(0) {}
14365     CONSTEXPR scale_length_r(uint64_t init) :
14366         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14367         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14368     {
14369     }
14370     CONSTEXPR void operator=(uint64_t value)
14371     {
14372         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14373         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14374     }
14375     void operator=(uint64_t value) volatile
14376     {
14377         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14378         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14379     }
14380     CONSTEXPR operator uint64_t()
14381     {
14382         return (static_cast<uint64_t>(word1) << 32) | word0;
14383     }
14384     operator uint64_t() volatile
14385     {
14386         return (static_cast<uint64_t>(word1) << 32) | word0;
14387     }
14388     scale_length_r copy() volatile
14389     {
14390         return *this;
14391     }
14392 #endif
14393 };
14394 
14395 // ofm_scale_r - None
14396 struct ofm_scale_r
14397 {
14398 #ifndef __cplusplus
14399     union
14400     {
14401         struct
14402         {
14403             uint32_t value : 32; // 32-bit register value
14404         };
14405         uint32_t word;
14406     };
14407 #else
14408   private:
14409     uint32_t word0;
14410 
14411   public:
14412     CONSTEXPR ofm_scale_r() : word0(0) {}
14413     CONSTEXPR ofm_scale_r(uint32_t init) : word0(init) {}
14414     CONSTEXPR void operator=(uint32_t value)
14415     {
14416         word0 = value;
14417     }
14418     void operator=(uint32_t value) volatile
14419     {
14420         word0 = value;
14421     }
14422     CONSTEXPR operator uint32_t()
14423     {
14424         return word0;
14425     }
14426     operator uint32_t() volatile
14427     {
14428         return word0;
14429     }
14430     ofm_scale_r copy() volatile
14431     {
14432         return *this;
14433     }
14434     CONSTEXPR uint32_t get_value() const
14435     {
14436         uint32_t value = word0;
14437         return value;
14438     }
14439     uint32_t get_value() const volatile
14440     {
14441         uint32_t value = word0;
14442         return value;
14443     }
14444     CONSTEXPR ofm_scale_r &set_value(uint32_t value)
14445     {
14446         word0 = value;
14447         return *this;
14448     }
14449     volatile ofm_scale_r &set_value(uint32_t value) volatile
14450     {
14451         word0 = value;
14452         return *this;
14453     }
14454 #endif
14455 };
14456 
14457 // ofm_scale_shift_r - None
14458 struct ofm_scale_shift_r
14459 {
14460 #ifndef __cplusplus
14461     union
14462     {
14463         struct
14464         {
14465             uint32_t value : 32; // 32-bit register value
14466         };
14467         uint32_t word;
14468     };
14469 #else
14470   private:
14471     uint32_t word0;
14472 
14473   public:
14474     CONSTEXPR ofm_scale_shift_r() : word0(0) {}
14475     CONSTEXPR ofm_scale_shift_r(uint32_t init) : word0(init) {}
14476     CONSTEXPR void operator=(uint32_t value)
14477     {
14478         word0 = value;
14479     }
14480     void operator=(uint32_t value) volatile
14481     {
14482         word0 = value;
14483     }
14484     CONSTEXPR operator uint32_t()
14485     {
14486         return word0;
14487     }
14488     operator uint32_t() volatile
14489     {
14490         return word0;
14491     }
14492     ofm_scale_shift_r copy() volatile
14493     {
14494         return *this;
14495     }
14496     CONSTEXPR uint32_t get_value() const
14497     {
14498         uint32_t value = word0;
14499         return value;
14500     }
14501     uint32_t get_value() const volatile
14502     {
14503         uint32_t value = word0;
14504         return value;
14505     }
14506     CONSTEXPR ofm_scale_shift_r &set_value(uint32_t value)
14507     {
14508         word0 = value;
14509         return *this;
14510     }
14511     volatile ofm_scale_shift_r &set_value(uint32_t value) volatile
14512     {
14513         word0 = value;
14514         return *this;
14515     }
14516 #endif
14517 };
14518 
14519 // opa_scale_r - None
14520 struct opa_scale_r
14521 {
14522 #ifndef __cplusplus
14523     union
14524     {
14525         struct
14526         {
14527             uint32_t value : 32; // 32-bit register value
14528         };
14529         uint32_t word;
14530     };
14531 #else
14532   private:
14533     uint32_t word0;
14534 
14535   public:
14536     CONSTEXPR opa_scale_r() : word0(0) {}
14537     CONSTEXPR opa_scale_r(uint32_t init) : word0(init) {}
14538     CONSTEXPR void operator=(uint32_t value)
14539     {
14540         word0 = value;
14541     }
14542     void operator=(uint32_t value) volatile
14543     {
14544         word0 = value;
14545     }
14546     CONSTEXPR operator uint32_t()
14547     {
14548         return word0;
14549     }
14550     operator uint32_t() volatile
14551     {
14552         return word0;
14553     }
14554     opa_scale_r copy() volatile
14555     {
14556         return *this;
14557     }
14558     CONSTEXPR uint32_t get_value() const
14559     {
14560         uint32_t value = word0;
14561         return value;
14562     }
14563     uint32_t get_value() const volatile
14564     {
14565         uint32_t value = word0;
14566         return value;
14567     }
14568     CONSTEXPR opa_scale_r &set_value(uint32_t value)
14569     {
14570         word0 = value;
14571         return *this;
14572     }
14573     volatile opa_scale_r &set_value(uint32_t value) volatile
14574     {
14575         word0 = value;
14576         return *this;
14577     }
14578 #endif
14579 };
14580 
14581 // opa_scale_shift_r - None
14582 struct opa_scale_shift_r
14583 {
14584 #ifndef __cplusplus
14585     union
14586     {
14587         struct
14588         {
14589             uint32_t value : 32; // 32-bit register value
14590         };
14591         uint32_t word;
14592     };
14593 #else
14594   private:
14595     uint32_t word0;
14596 
14597   public:
14598     CONSTEXPR opa_scale_shift_r() : word0(0) {}
14599     CONSTEXPR opa_scale_shift_r(uint32_t init) : word0(init) {}
14600     CONSTEXPR void operator=(uint32_t value)
14601     {
14602         word0 = value;
14603     }
14604     void operator=(uint32_t value) volatile
14605     {
14606         word0 = value;
14607     }
14608     CONSTEXPR operator uint32_t()
14609     {
14610         return word0;
14611     }
14612     operator uint32_t() volatile
14613     {
14614         return word0;
14615     }
14616     opa_scale_shift_r copy() volatile
14617     {
14618         return *this;
14619     }
14620     CONSTEXPR uint32_t get_value() const
14621     {
14622         uint32_t value = word0;
14623         return value;
14624     }
14625     uint32_t get_value() const volatile
14626     {
14627         uint32_t value = word0;
14628         return value;
14629     }
14630     CONSTEXPR opa_scale_shift_r &set_value(uint32_t value)
14631     {
14632         word0 = value;
14633         return *this;
14634     }
14635     volatile opa_scale_shift_r &set_value(uint32_t value) volatile
14636     {
14637         word0 = value;
14638         return *this;
14639     }
14640 #endif
14641 };
14642 
14643 // opb_scale_r - None
14644 struct opb_scale_r
14645 {
14646 #ifndef __cplusplus
14647     union
14648     {
14649         struct
14650         {
14651             uint32_t value : 32; // 32-bit register value
14652         };
14653         uint32_t word;
14654     };
14655 #else
14656   private:
14657     uint32_t word0;
14658 
14659   public:
14660     CONSTEXPR opb_scale_r() : word0(0) {}
14661     CONSTEXPR opb_scale_r(uint32_t init) : word0(init) {}
14662     CONSTEXPR void operator=(uint32_t value)
14663     {
14664         word0 = value;
14665     }
14666     void operator=(uint32_t value) volatile
14667     {
14668         word0 = value;
14669     }
14670     CONSTEXPR operator uint32_t()
14671     {
14672         return word0;
14673     }
14674     operator uint32_t() volatile
14675     {
14676         return word0;
14677     }
14678     opb_scale_r copy() volatile
14679     {
14680         return *this;
14681     }
14682     CONSTEXPR uint32_t get_value() const
14683     {
14684         uint32_t value = word0;
14685         return value;
14686     }
14687     uint32_t get_value() const volatile
14688     {
14689         uint32_t value = word0;
14690         return value;
14691     }
14692     CONSTEXPR opb_scale_r &set_value(uint32_t value)
14693     {
14694         word0 = value;
14695         return *this;
14696     }
14697     volatile opb_scale_r &set_value(uint32_t value) volatile
14698     {
14699         word0 = value;
14700         return *this;
14701     }
14702 #endif
14703 };
14704 
14705 // dma0_src_r - None
14706 struct dma0_src_r
14707 {
14708 #ifndef __cplusplus
14709     union
14710     {
14711         struct
14712         {
14713             uint32_t value_LO : 32; // 64-bit register value - LSB
14714             uint32_t value_HI : 32; // 64-bit register value - MSB
14715         };
14716         uint32_t word[2];
14717     };
14718 #else
14719   private:
14720     uint32_t word0;
14721     uint32_t word1;
14722 
14723   public:
14724     CONSTEXPR dma0_src_r() : word0(0), word1(0) {}
14725     CONSTEXPR dma0_src_r(uint64_t init) :
14726         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14727         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14728     {
14729     }
14730     CONSTEXPR void operator=(uint64_t value)
14731     {
14732         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14733         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14734     }
14735     void operator=(uint64_t value) volatile
14736     {
14737         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14738         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14739     }
14740     CONSTEXPR operator uint64_t()
14741     {
14742         return (static_cast<uint64_t>(word1) << 32) | word0;
14743     }
14744     operator uint64_t() volatile
14745     {
14746         return (static_cast<uint64_t>(word1) << 32) | word0;
14747     }
14748     dma0_src_r copy() volatile
14749     {
14750         return *this;
14751     }
14752 #endif
14753 };
14754 
14755 // dma0_dst_r - None
14756 struct dma0_dst_r
14757 {
14758 #ifndef __cplusplus
14759     union
14760     {
14761         struct
14762         {
14763             uint32_t value_LO : 32; // 64-bit register value - LSB
14764             uint32_t value_HI : 32; // 64-bit register value - MSB
14765         };
14766         uint32_t word[2];
14767     };
14768 #else
14769   private:
14770     uint32_t word0;
14771     uint32_t word1;
14772 
14773   public:
14774     CONSTEXPR dma0_dst_r() : word0(0), word1(0) {}
14775     CONSTEXPR dma0_dst_r(uint64_t init) :
14776         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14777         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14778     {
14779     }
14780     CONSTEXPR void operator=(uint64_t value)
14781     {
14782         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14783         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14784     }
14785     void operator=(uint64_t value) volatile
14786     {
14787         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14788         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14789     }
14790     CONSTEXPR operator uint64_t()
14791     {
14792         return (static_cast<uint64_t>(word1) << 32) | word0;
14793     }
14794     operator uint64_t() volatile
14795     {
14796         return (static_cast<uint64_t>(word1) << 32) | word0;
14797     }
14798     dma0_dst_r copy() volatile
14799     {
14800         return *this;
14801     }
14802 #endif
14803 };
14804 
14805 // dma0_len_r - None
14806 struct dma0_len_r
14807 {
14808 #ifndef __cplusplus
14809     union
14810     {
14811         struct
14812         {
14813             uint32_t value_LO : 32; // 64-bit register value - LSB
14814             uint32_t value_HI : 32; // 64-bit register value - MSB
14815         };
14816         uint32_t word[2];
14817     };
14818 #else
14819   private:
14820     uint32_t word0;
14821     uint32_t word1;
14822 
14823   public:
14824     CONSTEXPR dma0_len_r() : word0(0), word1(0) {}
14825     CONSTEXPR dma0_len_r(uint64_t init) :
14826         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14827         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14828     {
14829     }
14830     CONSTEXPR void operator=(uint64_t value)
14831     {
14832         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14833         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14834     }
14835     void operator=(uint64_t value) volatile
14836     {
14837         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14838         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14839     }
14840     CONSTEXPR operator uint64_t()
14841     {
14842         return (static_cast<uint64_t>(word1) << 32) | word0;
14843     }
14844     operator uint64_t() volatile
14845     {
14846         return (static_cast<uint64_t>(word1) << 32) | word0;
14847     }
14848     dma0_len_r copy() volatile
14849     {
14850         return *this;
14851     }
14852 #endif
14853 };
14854 
14855 // dma0_skip0_r - None
14856 struct dma0_skip0_r
14857 {
14858 #ifndef __cplusplus
14859     union
14860     {
14861         struct
14862         {
14863             uint32_t value_LO : 32; // 64-bit register value - LSB
14864             uint32_t value_HI : 32; // 64-bit register value - MSB
14865         };
14866         uint32_t word[2];
14867     };
14868 #else
14869   private:
14870     uint32_t word0;
14871     uint32_t word1;
14872 
14873   public:
14874     CONSTEXPR dma0_skip0_r() : word0(0), word1(0) {}
14875     CONSTEXPR dma0_skip0_r(uint64_t init) :
14876         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14877         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14878     {
14879     }
14880     CONSTEXPR void operator=(uint64_t value)
14881     {
14882         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14883         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14884     }
14885     void operator=(uint64_t value) volatile
14886     {
14887         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14888         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14889     }
14890     CONSTEXPR operator uint64_t()
14891     {
14892         return (static_cast<uint64_t>(word1) << 32) | word0;
14893     }
14894     operator uint64_t() volatile
14895     {
14896         return (static_cast<uint64_t>(word1) << 32) | word0;
14897     }
14898     dma0_skip0_r copy() volatile
14899     {
14900         return *this;
14901     }
14902 #endif
14903 };
14904 
14905 // dma0_skip1_r - None
14906 struct dma0_skip1_r
14907 {
14908 #ifndef __cplusplus
14909     union
14910     {
14911         struct
14912         {
14913             uint32_t value_LO : 32; // 64-bit register value - LSB
14914             uint32_t value_HI : 32; // 64-bit register value - MSB
14915         };
14916         uint32_t word[2];
14917     };
14918 #else
14919   private:
14920     uint32_t word0;
14921     uint32_t word1;
14922 
14923   public:
14924     CONSTEXPR dma0_skip1_r() : word0(0), word1(0) {}
14925     CONSTEXPR dma0_skip1_r(uint64_t init) :
14926         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14927         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14928     {
14929     }
14930     CONSTEXPR void operator=(uint64_t value)
14931     {
14932         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14933         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14934     }
14935     void operator=(uint64_t value) volatile
14936     {
14937         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14938         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14939     }
14940     CONSTEXPR operator uint64_t()
14941     {
14942         return (static_cast<uint64_t>(word1) << 32) | word0;
14943     }
14944     operator uint64_t() volatile
14945     {
14946         return (static_cast<uint64_t>(word1) << 32) | word0;
14947     }
14948     dma0_skip1_r copy() volatile
14949     {
14950         return *this;
14951     }
14952 #endif
14953 };
14954 
14955 // ifm2_base0_r - None
14956 struct ifm2_base0_r
14957 {
14958 #ifndef __cplusplus
14959     union
14960     {
14961         struct
14962         {
14963             uint32_t value_LO : 32; // 64-bit register value - LSB
14964             uint32_t value_HI : 32; // 64-bit register value - MSB
14965         };
14966         uint32_t word[2];
14967     };
14968 #else
14969   private:
14970     uint32_t word0;
14971     uint32_t word1;
14972 
14973   public:
14974     CONSTEXPR ifm2_base0_r() : word0(0), word1(0) {}
14975     CONSTEXPR ifm2_base0_r(uint64_t init) :
14976         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14977         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14978     {
14979     }
14980     CONSTEXPR void operator=(uint64_t value)
14981     {
14982         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14983         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14984     }
14985     void operator=(uint64_t value) volatile
14986     {
14987         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14988         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14989     }
14990     CONSTEXPR operator uint64_t()
14991     {
14992         return (static_cast<uint64_t>(word1) << 32) | word0;
14993     }
14994     operator uint64_t() volatile
14995     {
14996         return (static_cast<uint64_t>(word1) << 32) | word0;
14997     }
14998     ifm2_base0_r copy() volatile
14999     {
15000         return *this;
15001     }
15002 #endif
15003 };
15004 
15005 // ifm2_base1_r - None
15006 struct ifm2_base1_r
15007 {
15008 #ifndef __cplusplus
15009     union
15010     {
15011         struct
15012         {
15013             uint32_t value_LO : 32; // 64-bit register value - LSB
15014             uint32_t value_HI : 32; // 64-bit register value - MSB
15015         };
15016         uint32_t word[2];
15017     };
15018 #else
15019   private:
15020     uint32_t word0;
15021     uint32_t word1;
15022 
15023   public:
15024     CONSTEXPR ifm2_base1_r() : word0(0), word1(0) {}
15025     CONSTEXPR ifm2_base1_r(uint64_t init) :
15026         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15027         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15028     {
15029     }
15030     CONSTEXPR void operator=(uint64_t value)
15031     {
15032         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15033         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15034     }
15035     void operator=(uint64_t value) volatile
15036     {
15037         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15038         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15039     }
15040     CONSTEXPR operator uint64_t()
15041     {
15042         return (static_cast<uint64_t>(word1) << 32) | word0;
15043     }
15044     operator uint64_t() volatile
15045     {
15046         return (static_cast<uint64_t>(word1) << 32) | word0;
15047     }
15048     ifm2_base1_r copy() volatile
15049     {
15050         return *this;
15051     }
15052 #endif
15053 };
15054 
15055 // ifm2_base2_r - None
15056 struct ifm2_base2_r
15057 {
15058 #ifndef __cplusplus
15059     union
15060     {
15061         struct
15062         {
15063             uint32_t value_LO : 32; // 64-bit register value - LSB
15064             uint32_t value_HI : 32; // 64-bit register value - MSB
15065         };
15066         uint32_t word[2];
15067     };
15068 #else
15069   private:
15070     uint32_t word0;
15071     uint32_t word1;
15072 
15073   public:
15074     CONSTEXPR ifm2_base2_r() : word0(0), word1(0) {}
15075     CONSTEXPR ifm2_base2_r(uint64_t init) :
15076         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15077         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15078     {
15079     }
15080     CONSTEXPR void operator=(uint64_t value)
15081     {
15082         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15083         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15084     }
15085     void operator=(uint64_t value) volatile
15086     {
15087         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15088         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15089     }
15090     CONSTEXPR operator uint64_t()
15091     {
15092         return (static_cast<uint64_t>(word1) << 32) | word0;
15093     }
15094     operator uint64_t() volatile
15095     {
15096         return (static_cast<uint64_t>(word1) << 32) | word0;
15097     }
15098     ifm2_base2_r copy() volatile
15099     {
15100         return *this;
15101     }
15102 #endif
15103 };
15104 
15105 // ifm2_base3_r - None
15106 struct ifm2_base3_r
15107 {
15108 #ifndef __cplusplus
15109     union
15110     {
15111         struct
15112         {
15113             uint32_t value_LO : 32; // 64-bit register value - LSB
15114             uint32_t value_HI : 32; // 64-bit register value - MSB
15115         };
15116         uint32_t word[2];
15117     };
15118 #else
15119   private:
15120     uint32_t word0;
15121     uint32_t word1;
15122 
15123   public:
15124     CONSTEXPR ifm2_base3_r() : word0(0), word1(0) {}
15125     CONSTEXPR ifm2_base3_r(uint64_t init) :
15126         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15127         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15128     {
15129     }
15130     CONSTEXPR void operator=(uint64_t value)
15131     {
15132         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15133         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15134     }
15135     void operator=(uint64_t value) volatile
15136     {
15137         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15138         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15139     }
15140     CONSTEXPR operator uint64_t()
15141     {
15142         return (static_cast<uint64_t>(word1) << 32) | word0;
15143     }
15144     operator uint64_t() volatile
15145     {
15146         return (static_cast<uint64_t>(word1) << 32) | word0;
15147     }
15148     ifm2_base3_r copy() volatile
15149     {
15150         return *this;
15151     }
15152 #endif
15153 };
15154 
15155 // ifm2_stride_x_r - None
15156 struct ifm2_stride_x_r
15157 {
15158 #ifndef __cplusplus
15159     union
15160     {
15161         struct
15162         {
15163             uint32_t value_LO : 32; // 64-bit register value - LSB
15164             uint32_t value_HI : 32; // 64-bit register value - MSB
15165         };
15166         uint32_t word[2];
15167     };
15168 #else
15169   private:
15170     uint32_t word0;
15171     uint32_t word1;
15172 
15173   public:
15174     CONSTEXPR ifm2_stride_x_r() : word0(0), word1(0) {}
15175     CONSTEXPR ifm2_stride_x_r(uint64_t init) :
15176         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15177         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15178     {
15179     }
15180     CONSTEXPR void operator=(uint64_t value)
15181     {
15182         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15183         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15184     }
15185     void operator=(uint64_t value) volatile
15186     {
15187         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15188         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15189     }
15190     CONSTEXPR operator uint64_t()
15191     {
15192         return (static_cast<uint64_t>(word1) << 32) | word0;
15193     }
15194     operator uint64_t() volatile
15195     {
15196         return (static_cast<uint64_t>(word1) << 32) | word0;
15197     }
15198     ifm2_stride_x_r copy() volatile
15199     {
15200         return *this;
15201     }
15202 #endif
15203 };
15204 
15205 // ifm2_stride_y_r - None
15206 struct ifm2_stride_y_r
15207 {
15208 #ifndef __cplusplus
15209     union
15210     {
15211         struct
15212         {
15213             uint32_t value_LO : 32; // 64-bit register value - LSB
15214             uint32_t value_HI : 32; // 64-bit register value - MSB
15215         };
15216         uint32_t word[2];
15217     };
15218 #else
15219   private:
15220     uint32_t word0;
15221     uint32_t word1;
15222 
15223   public:
15224     CONSTEXPR ifm2_stride_y_r() : word0(0), word1(0) {}
15225     CONSTEXPR ifm2_stride_y_r(uint64_t init) :
15226         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15227         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15228     {
15229     }
15230     CONSTEXPR void operator=(uint64_t value)
15231     {
15232         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15233         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15234     }
15235     void operator=(uint64_t value) volatile
15236     {
15237         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15238         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15239     }
15240     CONSTEXPR operator uint64_t()
15241     {
15242         return (static_cast<uint64_t>(word1) << 32) | word0;
15243     }
15244     operator uint64_t() volatile
15245     {
15246         return (static_cast<uint64_t>(word1) << 32) | word0;
15247     }
15248     ifm2_stride_y_r copy() volatile
15249     {
15250         return *this;
15251     }
15252 #endif
15253 };
15254 
15255 // ifm2_stride_c_r - None
15256 struct ifm2_stride_c_r
15257 {
15258 #ifndef __cplusplus
15259     union
15260     {
15261         struct
15262         {
15263             uint32_t value_LO : 32; // 64-bit register value - LSB
15264             uint32_t value_HI : 32; // 64-bit register value - MSB
15265         };
15266         uint32_t word[2];
15267     };
15268 #else
15269   private:
15270     uint32_t word0;
15271     uint32_t word1;
15272 
15273   public:
15274     CONSTEXPR ifm2_stride_c_r() : word0(0), word1(0) {}
15275     CONSTEXPR ifm2_stride_c_r(uint64_t init) :
15276         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15277         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15278     {
15279     }
15280     CONSTEXPR void operator=(uint64_t value)
15281     {
15282         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15283         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15284     }
15285     void operator=(uint64_t value) volatile
15286     {
15287         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15288         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15289     }
15290     CONSTEXPR operator uint64_t()
15291     {
15292         return (static_cast<uint64_t>(word1) << 32) | word0;
15293     }
15294     operator uint64_t() volatile
15295     {
15296         return (static_cast<uint64_t>(word1) << 32) | word0;
15297     }
15298     ifm2_stride_c_r copy() volatile
15299     {
15300         return *this;
15301     }
15302 #endif
15303 };
15304 
15305 // weight1_base_r - None
15306 struct weight1_base_r
15307 {
15308 #ifndef __cplusplus
15309     union
15310     {
15311         struct
15312         {
15313             uint32_t value_LO : 32; // 64-bit register value - LSB
15314             uint32_t value_HI : 32; // 64-bit register value - MSB
15315         };
15316         uint32_t word[2];
15317     };
15318 #else
15319   private:
15320     uint32_t word0;
15321     uint32_t word1;
15322 
15323   public:
15324     CONSTEXPR weight1_base_r() : word0(0), word1(0) {}
15325     CONSTEXPR weight1_base_r(uint64_t init) :
15326         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15327         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15328     {
15329     }
15330     CONSTEXPR void operator=(uint64_t value)
15331     {
15332         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15333         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15334     }
15335     void operator=(uint64_t value) volatile
15336     {
15337         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15338         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15339     }
15340     CONSTEXPR operator uint64_t()
15341     {
15342         return (static_cast<uint64_t>(word1) << 32) | word0;
15343     }
15344     operator uint64_t() volatile
15345     {
15346         return (static_cast<uint64_t>(word1) << 32) | word0;
15347     }
15348     weight1_base_r copy() volatile
15349     {
15350         return *this;
15351     }
15352 #endif
15353 };
15354 
15355 // weight1_length_r - None
15356 struct weight1_length_r
15357 {
15358 #ifndef __cplusplus
15359     union
15360     {
15361         struct
15362         {
15363             uint32_t value_LO : 32; // 64-bit register value - LSB
15364             uint32_t value_HI : 32; // 64-bit register value - MSB
15365         };
15366         uint32_t word[2];
15367     };
15368 #else
15369   private:
15370     uint32_t word0;
15371     uint32_t word1;
15372 
15373   public:
15374     CONSTEXPR weight1_length_r() : word0(0), word1(0) {}
15375     CONSTEXPR weight1_length_r(uint64_t init) :
15376         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15377         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15378     {
15379     }
15380     CONSTEXPR void operator=(uint64_t value)
15381     {
15382         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15383         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15384     }
15385     void operator=(uint64_t value) volatile
15386     {
15387         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15388         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15389     }
15390     CONSTEXPR operator uint64_t()
15391     {
15392         return (static_cast<uint64_t>(word1) << 32) | word0;
15393     }
15394     operator uint64_t() volatile
15395     {
15396         return (static_cast<uint64_t>(word1) << 32) | word0;
15397     }
15398     weight1_length_r copy() volatile
15399     {
15400         return *this;
15401     }
15402 #endif
15403 };
15404 
15405 // scale1_base_r - None
15406 struct scale1_base_r
15407 {
15408 #ifndef __cplusplus
15409     union
15410     {
15411         struct
15412         {
15413             uint32_t value_LO : 32; // 64-bit register value - LSB
15414             uint32_t value_HI : 32; // 64-bit register value - MSB
15415         };
15416         uint32_t word[2];
15417     };
15418 #else
15419   private:
15420     uint32_t word0;
15421     uint32_t word1;
15422 
15423   public:
15424     CONSTEXPR scale1_base_r() : word0(0), word1(0) {}
15425     CONSTEXPR scale1_base_r(uint64_t init) :
15426         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15427         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15428     {
15429     }
15430     CONSTEXPR void operator=(uint64_t value)
15431     {
15432         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15433         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15434     }
15435     void operator=(uint64_t value) volatile
15436     {
15437         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15438         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15439     }
15440     CONSTEXPR operator uint64_t()
15441     {
15442         return (static_cast<uint64_t>(word1) << 32) | word0;
15443     }
15444     operator uint64_t() volatile
15445     {
15446         return (static_cast<uint64_t>(word1) << 32) | word0;
15447     }
15448     scale1_base_r copy() volatile
15449     {
15450         return *this;
15451     }
15452 #endif
15453 };
15454 
15455 // scale1_length_r - None
15456 struct scale1_length_r
15457 {
15458 #ifndef __cplusplus
15459     union
15460     {
15461         struct
15462         {
15463             uint32_t value_LO : 32; // 64-bit register value - LSB
15464             uint32_t value_HI : 32; // 64-bit register value - MSB
15465         };
15466         uint32_t word[2];
15467     };
15468 #else
15469   private:
15470     uint32_t word0;
15471     uint32_t word1;
15472 
15473   public:
15474     CONSTEXPR scale1_length_r() : word0(0), word1(0) {}
15475     CONSTEXPR scale1_length_r(uint64_t init) :
15476         word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15477         word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15478     {
15479     }
15480     CONSTEXPR void operator=(uint64_t value)
15481     {
15482         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15483         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15484     }
15485     void operator=(uint64_t value) volatile
15486     {
15487         word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15488         word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15489     }
15490     CONSTEXPR operator uint64_t()
15491     {
15492         return (static_cast<uint64_t>(word1) << 32) | word0;
15493     }
15494     operator uint64_t() volatile
15495     {
15496         return (static_cast<uint64_t>(word1) << 32) | word0;
15497     }
15498     scale1_length_r copy() volatile
15499     {
15500         return *this;
15501     }
15502 #endif
15503 };
15504 
15505 // revision_r - Internal FPGA build revision: first 32-bits of the Ultan Git hash used for the build
15506 struct revision_r
15507 {
15508 #ifndef __cplusplus
15509     union
15510     {
15511         struct
15512         {
15513             uint32_t value : 32; // 32-bit register value
15514         };
15515         uint32_t word;
15516     };
15517 #else
15518   private:
15519     uint32_t word0;
15520 
15521   public:
15522     CONSTEXPR revision_r() : word0(0) {}
15523     CONSTEXPR revision_r(uint32_t init) : word0(init) {}
15524     CONSTEXPR void operator=(uint32_t value)
15525     {
15526         word0 = value;
15527     }
15528     void operator=(uint32_t value) volatile
15529     {
15530         word0 = value;
15531     }
15532     CONSTEXPR operator uint32_t()
15533     {
15534         return word0;
15535     }
15536     operator uint32_t() volatile
15537     {
15538         return word0;
15539     }
15540     revision_r copy() volatile
15541     {
15542         return *this;
15543     }
15544     CONSTEXPR uint32_t get_value() const
15545     {
15546         uint32_t value = word0;
15547         return value;
15548     }
15549     uint32_t get_value() const volatile
15550     {
15551         uint32_t value = word0;
15552         return value;
15553     }
15554     CONSTEXPR revision_r &set_value(uint32_t value)
15555     {
15556         word0 = value;
15557         return *this;
15558     }
15559     volatile revision_r &set_value(uint32_t value) volatile
15560     {
15561         word0 = value;
15562         return *this;
15563     }
15564 #endif
15565 };
15566 
15567 // pid4_r - Peripheral ID byte 4 (Arm=code 4)
15568 struct pid4_r
15569 {
15570 #ifndef __cplusplus
15571     union
15572     {
15573         struct
15574         {
15575             uint32_t PID4 : 32; // Byte 4 of Peripheral ID (Lower 8 bits valid)
15576         };
15577         uint32_t word;
15578     };
15579 #else
15580   private:
15581     uint32_t word0;
15582 
15583   public:
15584     CONSTEXPR pid4_r() : word0(4) {}
15585     CONSTEXPR pid4_r(uint32_t init) : word0(init) {}
15586     CONSTEXPR void operator=(uint32_t value)
15587     {
15588         word0 = value;
15589     }
15590     void operator=(uint32_t value) volatile
15591     {
15592         word0 = value;
15593     }
15594     CONSTEXPR operator uint32_t()
15595     {
15596         return word0;
15597     }
15598     operator uint32_t() volatile
15599     {
15600         return word0;
15601     }
15602     pid4_r copy() volatile
15603     {
15604         return *this;
15605     }
15606     CONSTEXPR uint32_t get_PID4() const
15607     {
15608         uint32_t value = word0;
15609         return value;
15610     }
15611     uint32_t get_PID4() const volatile
15612     {
15613         uint32_t value = word0;
15614         return value;
15615     }
15616     CONSTEXPR pid4_r &set_PID4(uint32_t value)
15617     {
15618         word0 = value;
15619         return *this;
15620     }
15621     volatile pid4_r &set_PID4(uint32_t value) volatile
15622     {
15623         word0 = value;
15624         return *this;
15625     }
15626 #endif
15627 };
15628 
15629 // pid5_r - Peripheral ID byte 5 (reserved)
15630 struct pid5_r
15631 {
15632 #ifndef __cplusplus
15633     union
15634     {
15635         struct
15636         {
15637             uint32_t PID5 : 32; // Byte 5 of Peripheral ID (Lower 8 bits valid)
15638         };
15639         uint32_t word;
15640     };
15641 #else
15642   private:
15643     uint32_t word0;
15644 
15645   public:
15646     CONSTEXPR pid5_r() : word0(0) {}
15647     CONSTEXPR pid5_r(uint32_t init) : word0(init) {}
15648     CONSTEXPR void operator=(uint32_t value)
15649     {
15650         word0 = value;
15651     }
15652     void operator=(uint32_t value) volatile
15653     {
15654         word0 = value;
15655     }
15656     CONSTEXPR operator uint32_t()
15657     {
15658         return word0;
15659     }
15660     operator uint32_t() volatile
15661     {
15662         return word0;
15663     }
15664     pid5_r copy() volatile
15665     {
15666         return *this;
15667     }
15668     CONSTEXPR uint32_t get_PID5() const
15669     {
15670         uint32_t value = word0;
15671         return value;
15672     }
15673     uint32_t get_PID5() const volatile
15674     {
15675         uint32_t value = word0;
15676         return value;
15677     }
15678     CONSTEXPR pid5_r &set_PID5(uint32_t value)
15679     {
15680         word0 = value;
15681         return *this;
15682     }
15683     volatile pid5_r &set_PID5(uint32_t value) volatile
15684     {
15685         word0 = value;
15686         return *this;
15687     }
15688 #endif
15689 };
15690 
15691 // pid6_r - Peripheral ID byte 6 (reserved)
15692 struct pid6_r
15693 {
15694 #ifndef __cplusplus
15695     union
15696     {
15697         struct
15698         {
15699             uint32_t PID6 : 32; // Byte 6 of Peripheral ID (Lower 8 bits valid)
15700         };
15701         uint32_t word;
15702     };
15703 #else
15704   private:
15705     uint32_t word0;
15706 
15707   public:
15708     CONSTEXPR pid6_r() : word0(0) {}
15709     CONSTEXPR pid6_r(uint32_t init) : word0(init) {}
15710     CONSTEXPR void operator=(uint32_t value)
15711     {
15712         word0 = value;
15713     }
15714     void operator=(uint32_t value) volatile
15715     {
15716         word0 = value;
15717     }
15718     CONSTEXPR operator uint32_t()
15719     {
15720         return word0;
15721     }
15722     operator uint32_t() volatile
15723     {
15724         return word0;
15725     }
15726     pid6_r copy() volatile
15727     {
15728         return *this;
15729     }
15730     CONSTEXPR uint32_t get_PID6() const
15731     {
15732         uint32_t value = word0;
15733         return value;
15734     }
15735     uint32_t get_PID6() const volatile
15736     {
15737         uint32_t value = word0;
15738         return value;
15739     }
15740     CONSTEXPR pid6_r &set_PID6(uint32_t value)
15741     {
15742         word0 = value;
15743         return *this;
15744     }
15745     volatile pid6_r &set_PID6(uint32_t value) volatile
15746     {
15747         word0 = value;
15748         return *this;
15749     }
15750 #endif
15751 };
15752 
15753 // pid7_r - Peripheral ID byte 7 (reserved)
15754 struct pid7_r
15755 {
15756 #ifndef __cplusplus
15757     union
15758     {
15759         struct
15760         {
15761             uint32_t PID7 : 32; // Byte 7 of Peripheral ID (Lower 8 bits valid)
15762         };
15763         uint32_t word;
15764     };
15765 #else
15766   private:
15767     uint32_t word0;
15768 
15769   public:
15770     CONSTEXPR pid7_r() : word0(0) {}
15771     CONSTEXPR pid7_r(uint32_t init) : word0(init) {}
15772     CONSTEXPR void operator=(uint32_t value)
15773     {
15774         word0 = value;
15775     }
15776     void operator=(uint32_t value) volatile
15777     {
15778         word0 = value;
15779     }
15780     CONSTEXPR operator uint32_t()
15781     {
15782         return word0;
15783     }
15784     operator uint32_t() volatile
15785     {
15786         return word0;
15787     }
15788     pid7_r copy() volatile
15789     {
15790         return *this;
15791     }
15792     CONSTEXPR uint32_t get_PID7() const
15793     {
15794         uint32_t value = word0;
15795         return value;
15796     }
15797     uint32_t get_PID7() const volatile
15798     {
15799         uint32_t value = word0;
15800         return value;
15801     }
15802     CONSTEXPR pid7_r &set_PID7(uint32_t value)
15803     {
15804         word0 = value;
15805         return *this;
15806     }
15807     volatile pid7_r &set_PID7(uint32_t value) volatile
15808     {
15809         word0 = value;
15810         return *this;
15811     }
15812 #endif
15813 };
15814 
15815 // pid0_r - Peripheral ID byte 0. This is bits[7:0] of the part number
15816 struct pid0_r
15817 {
15818 #ifndef __cplusplus
15819     union
15820     {
15821         struct
15822         {
15823             uint32_t PID0 : 32; // Byte 0 of Peripheral ID (Lower 8 bits valid)
15824         };
15825         uint32_t word;
15826     };
15827 #else
15828   private:
15829     uint32_t word0;
15830 
15831   public:
15832     CONSTEXPR pid0_r() : word0(129) {}
15833     CONSTEXPR pid0_r(uint32_t init) : word0(init) {}
15834     CONSTEXPR void operator=(uint32_t value)
15835     {
15836         word0 = value;
15837     }
15838     void operator=(uint32_t value) volatile
15839     {
15840         word0 = value;
15841     }
15842     CONSTEXPR operator uint32_t()
15843     {
15844         return word0;
15845     }
15846     operator uint32_t() volatile
15847     {
15848         return word0;
15849     }
15850     pid0_r copy() volatile
15851     {
15852         return *this;
15853     }
15854     CONSTEXPR uint32_t get_PID0() const
15855     {
15856         uint32_t value = word0;
15857         return value;
15858     }
15859     uint32_t get_PID0() const volatile
15860     {
15861         uint32_t value = word0;
15862         return value;
15863     }
15864     CONSTEXPR pid0_r &set_PID0(uint32_t value)
15865     {
15866         word0 = value;
15867         return *this;
15868     }
15869     volatile pid0_r &set_PID0(uint32_t value) volatile
15870     {
15871         word0 = value;
15872         return *this;
15873     }
15874 #endif
15875 };
15876 
15877 // pid1_r - Peripheral ID byte 1. This is bits[11:8] of the part number in bits[3:0], and bits[3:0] of the Arm ID in
15878 // bits[7:4]
15879 struct pid1_r
15880 {
15881 #ifndef __cplusplus
15882     union
15883     {
15884         struct
15885         {
15886             uint32_t PID1 : 32; // Byte 1 of Peripheral ID (Lower 8 bits valid)
15887         };
15888         uint32_t word;
15889     };
15890 #else
15891   private:
15892     uint32_t word0;
15893 
15894   public:
15895     CONSTEXPR pid1_r() : word0(181) {}
15896     CONSTEXPR pid1_r(uint32_t init) : word0(init) {}
15897     CONSTEXPR void operator=(uint32_t value)
15898     {
15899         word0 = value;
15900     }
15901     void operator=(uint32_t value) volatile
15902     {
15903         word0 = value;
15904     }
15905     CONSTEXPR operator uint32_t()
15906     {
15907         return word0;
15908     }
15909     operator uint32_t() volatile
15910     {
15911         return word0;
15912     }
15913     pid1_r copy() volatile
15914     {
15915         return *this;
15916     }
15917     CONSTEXPR uint32_t get_PID1() const
15918     {
15919         uint32_t value = word0;
15920         return value;
15921     }
15922     uint32_t get_PID1() const volatile
15923     {
15924         uint32_t value = word0;
15925         return value;
15926     }
15927     CONSTEXPR pid1_r &set_PID1(uint32_t value)
15928     {
15929         word0 = value;
15930         return *this;
15931     }
15932     volatile pid1_r &set_PID1(uint32_t value) volatile
15933     {
15934         word0 = value;
15935         return *this;
15936     }
15937 #endif
15938 };
15939 
15940 // pid2_r - Peripheral ID byte 2. This is bits[6:4] of the Arm ID in bits[2:0], and bit 3 indicates format B
15941 struct pid2_r
15942 {
15943 #ifndef __cplusplus
15944     union
15945     {
15946         struct
15947         {
15948             uint32_t PID2 : 32; // Byte 2 of Peripheral ID (Lower 8 bits valid)
15949         };
15950         uint32_t word;
15951     };
15952 #else
15953   private:
15954     uint32_t word0;
15955 
15956   public:
15957     CONSTEXPR pid2_r() : word0(11) {}
15958     CONSTEXPR pid2_r(uint32_t init) : word0(init) {}
15959     CONSTEXPR void operator=(uint32_t value)
15960     {
15961         word0 = value;
15962     }
15963     void operator=(uint32_t value) volatile
15964     {
15965         word0 = value;
15966     }
15967     CONSTEXPR operator uint32_t()
15968     {
15969         return word0;
15970     }
15971     operator uint32_t() volatile
15972     {
15973         return word0;
15974     }
15975     pid2_r copy() volatile
15976     {
15977         return *this;
15978     }
15979     CONSTEXPR uint32_t get_PID2() const
15980     {
15981         uint32_t value = word0;
15982         return value;
15983     }
15984     uint32_t get_PID2() const volatile
15985     {
15986         uint32_t value = word0;
15987         return value;
15988     }
15989     CONSTEXPR pid2_r &set_PID2(uint32_t value)
15990     {
15991         word0 = value;
15992         return *this;
15993     }
15994     volatile pid2_r &set_PID2(uint32_t value) volatile
15995     {
15996         word0 = value;
15997         return *this;
15998     }
15999 #endif
16000 };
16001 
16002 // pid3_r - Peripheral ID byte 3
16003 struct pid3_r
16004 {
16005 #ifndef __cplusplus
16006     union
16007     {
16008         struct
16009         {
16010             uint32_t PID3 : 32; // Byte 1 of Peripheral ID (Lower 8 bits valid)
16011         };
16012         uint32_t word;
16013     };
16014 #else
16015   private:
16016     uint32_t word0;
16017 
16018   public:
16019     CONSTEXPR pid3_r() : word0(0) {}
16020     CONSTEXPR pid3_r(uint32_t init) : word0(init) {}
16021     CONSTEXPR void operator=(uint32_t value)
16022     {
16023         word0 = value;
16024     }
16025     void operator=(uint32_t value) volatile
16026     {
16027         word0 = value;
16028     }
16029     CONSTEXPR operator uint32_t()
16030     {
16031         return word0;
16032     }
16033     operator uint32_t() volatile
16034     {
16035         return word0;
16036     }
16037     pid3_r copy() volatile
16038     {
16039         return *this;
16040     }
16041     CONSTEXPR uint32_t get_PID3() const
16042     {
16043         uint32_t value = word0;
16044         return value;
16045     }
16046     uint32_t get_PID3() const volatile
16047     {
16048         uint32_t value = word0;
16049         return value;
16050     }
16051     CONSTEXPR pid3_r &set_PID3(uint32_t value)
16052     {
16053         word0 = value;
16054         return *this;
16055     }
16056     volatile pid3_r &set_PID3(uint32_t value) volatile
16057     {
16058         word0 = value;
16059         return *this;
16060     }
16061 #endif
16062 };
16063 
16064 // cid0_r - Component ID byte 0
16065 struct cid0_r
16066 {
16067 #ifndef __cplusplus
16068     union
16069     {
16070         struct
16071         {
16072             uint32_t CID0 : 32; // Byte 0 of Component ID (Lower 8 bits valid)
16073         };
16074         uint32_t word;
16075     };
16076 #else
16077   private:
16078     uint32_t word0;
16079 
16080   public:
16081     CONSTEXPR cid0_r() : word0(13) {}
16082     CONSTEXPR cid0_r(uint32_t init) : word0(init) {}
16083     CONSTEXPR void operator=(uint32_t value)
16084     {
16085         word0 = value;
16086     }
16087     void operator=(uint32_t value) volatile
16088     {
16089         word0 = value;
16090     }
16091     CONSTEXPR operator uint32_t()
16092     {
16093         return word0;
16094     }
16095     operator uint32_t() volatile
16096     {
16097         return word0;
16098     }
16099     cid0_r copy() volatile
16100     {
16101         return *this;
16102     }
16103     CONSTEXPR uint32_t get_CID0() const
16104     {
16105         uint32_t value = word0;
16106         return value;
16107     }
16108     uint32_t get_CID0() const volatile
16109     {
16110         uint32_t value = word0;
16111         return value;
16112     }
16113     CONSTEXPR cid0_r &set_CID0(uint32_t value)
16114     {
16115         word0 = value;
16116         return *this;
16117     }
16118     volatile cid0_r &set_CID0(uint32_t value) volatile
16119     {
16120         word0 = value;
16121         return *this;
16122     }
16123 #endif
16124 };
16125 
16126 // cid1_r - Component ID byte 1
16127 struct cid1_r
16128 {
16129 #ifndef __cplusplus
16130     union
16131     {
16132         struct
16133         {
16134             uint32_t CID1 : 32; // Byte 1 of Component ID (Lower 8 bits valid)
16135         };
16136         uint32_t word;
16137     };
16138 #else
16139   private:
16140     uint32_t word0;
16141 
16142   public:
16143     CONSTEXPR cid1_r() : word0(240) {}
16144     CONSTEXPR cid1_r(uint32_t init) : word0(init) {}
16145     CONSTEXPR void operator=(uint32_t value)
16146     {
16147         word0 = value;
16148     }
16149     void operator=(uint32_t value) volatile
16150     {
16151         word0 = value;
16152     }
16153     CONSTEXPR operator uint32_t()
16154     {
16155         return word0;
16156     }
16157     operator uint32_t() volatile
16158     {
16159         return word0;
16160     }
16161     cid1_r copy() volatile
16162     {
16163         return *this;
16164     }
16165     CONSTEXPR uint32_t get_CID1() const
16166     {
16167         uint32_t value = word0;
16168         return value;
16169     }
16170     uint32_t get_CID1() const volatile
16171     {
16172         uint32_t value = word0;
16173         return value;
16174     }
16175     CONSTEXPR cid1_r &set_CID1(uint32_t value)
16176     {
16177         word0 = value;
16178         return *this;
16179     }
16180     volatile cid1_r &set_CID1(uint32_t value) volatile
16181     {
16182         word0 = value;
16183         return *this;
16184     }
16185 #endif
16186 };
16187 
16188 // cid2_r - Component ID byte 2
16189 struct cid2_r
16190 {
16191 #ifndef __cplusplus
16192     union
16193     {
16194         struct
16195         {
16196             uint32_t CID2 : 32; // Byte 2 of Component ID (Lower 8 bits valid)
16197         };
16198         uint32_t word;
16199     };
16200 #else
16201   private:
16202     uint32_t word0;
16203 
16204   public:
16205     CONSTEXPR cid2_r() : word0(5) {}
16206     CONSTEXPR cid2_r(uint32_t init) : word0(init) {}
16207     CONSTEXPR void operator=(uint32_t value)
16208     {
16209         word0 = value;
16210     }
16211     void operator=(uint32_t value) volatile
16212     {
16213         word0 = value;
16214     }
16215     CONSTEXPR operator uint32_t()
16216     {
16217         return word0;
16218     }
16219     operator uint32_t() volatile
16220     {
16221         return word0;
16222     }
16223     cid2_r copy() volatile
16224     {
16225         return *this;
16226     }
16227     CONSTEXPR uint32_t get_CID2() const
16228     {
16229         uint32_t value = word0;
16230         return value;
16231     }
16232     uint32_t get_CID2() const volatile
16233     {
16234         uint32_t value = word0;
16235         return value;
16236     }
16237     CONSTEXPR cid2_r &set_CID2(uint32_t value)
16238     {
16239         word0 = value;
16240         return *this;
16241     }
16242     volatile cid2_r &set_CID2(uint32_t value) volatile
16243     {
16244         word0 = value;
16245         return *this;
16246     }
16247 #endif
16248 };
16249 
16250 // cid3_r - Component ID byte 3
16251 struct cid3_r
16252 {
16253 #ifndef __cplusplus
16254     union
16255     {
16256         struct
16257         {
16258             uint32_t CID3 : 32; // Byte 3 of Component ID (Lower 8 bits valid)
16259         };
16260         uint32_t word;
16261     };
16262 #else
16263   private:
16264     uint32_t word0;
16265 
16266   public:
16267     CONSTEXPR cid3_r() : word0(177) {}
16268     CONSTEXPR cid3_r(uint32_t init) : word0(init) {}
16269     CONSTEXPR void operator=(uint32_t value)
16270     {
16271         word0 = value;
16272     }
16273     void operator=(uint32_t value) volatile
16274     {
16275         word0 = value;
16276     }
16277     CONSTEXPR operator uint32_t()
16278     {
16279         return word0;
16280     }
16281     operator uint32_t() volatile
16282     {
16283         return word0;
16284     }
16285     cid3_r copy() volatile
16286     {
16287         return *this;
16288     }
16289     CONSTEXPR uint32_t get_CID3() const
16290     {
16291         uint32_t value = word0;
16292         return value;
16293     }
16294     uint32_t get_CID3() const volatile
16295     {
16296         uint32_t value = word0;
16297         return value;
16298     }
16299     CONSTEXPR cid3_r &set_CID3(uint32_t value)
16300     {
16301         word0 = value;
16302         return *this;
16303     }
16304     volatile cid3_r &set_CID3(uint32_t value) volatile
16305     {
16306         word0 = value;
16307         return *this;
16308     }
16309 #endif
16310 };
16311 
16312 struct NPU_REG
16313 {
16314     STRUCT id_r ID;           // 0x0000
16315     STRUCT status_r STATUS;   // 0x0004
16316     STRUCT cmd_r CMD;         // 0x0008
16317     STRUCT reset_r RESET;     // 0x000C
16318     STRUCT qbase_r QBASE;     // 0x0010
16319     STRUCT qread_r QREAD;     // 0x0018
16320     STRUCT qconfig_r QCONFIG; // 0x001C
16321     STRUCT qsize_r QSIZE;     // 0x0020
16322     STRUCT prot_r PROT;       // 0x0024
16323     STRUCT config_r CONFIG;   // 0x0028
16324     STRUCT lock_r LOCK;       // 0x002C
16325     uint32_t unused0[3];
16326     STRUCT regioncfg_r REGIONCFG;   // 0x003C
16327     STRUCT axi_limit0_r AXI_LIMIT0; // 0x0040
16328     STRUCT axi_limit1_r AXI_LIMIT1; // 0x0044
16329     STRUCT axi_limit2_r AXI_LIMIT2; // 0x0048
16330     STRUCT axi_limit3_r AXI_LIMIT3; // 0x004C
16331     uint32_t unused1[12];
16332     STRUCT basep_r BASEP[8]; // 0x0080
16333     uint32_t unused2[16];
16334     STRUCT wd_status_r WD_STATUS;   // 0x0100
16335     STRUCT mac_status_r MAC_STATUS; // 0x0104
16336     STRUCT ao_status_r AO_STATUS;   // 0x0108
16337     uint32_t unused3[1];
16338     STRUCT dma_status0_r DMA_STATUS0; // 0x0110
16339     STRUCT dma_status1_r DMA_STATUS1; // 0x0114
16340     uint32_t unused4[10];
16341     STRUCT clkforce_r CLKFORCE;           // 0x0140
16342     STRUCT debug_address_r DEBUG_ADDRESS; // 0x0144
16343     STRUCT debug_misc_r DEBUG_MISC;       // 0x0148
16344     STRUCT debugcore_r DEBUGCORE;         // 0x014C
16345     STRUCT debug_block_r DEBUG_BLOCK;     // 0x0150
16346     uint32_t unused5[11];
16347     STRUCT pmcr_r PMCR;             // 0x0180
16348     STRUCT pmcntenset_r PMCNTENSET; // 0x0184
16349     STRUCT pmcntenclr_r PMCNTENCLR; // 0x0188
16350     STRUCT pmovsset_r PMOVSSET;     // 0x018C
16351     STRUCT pmovsclr_r PMOVSCLR;     // 0x0190
16352     STRUCT pmintset_r PMINTSET;     // 0x0194
16353     STRUCT pmintclr_r PMINTCLR;     // 0x0198
16354     uint32_t unused6[1];
16355     STRUCT pmccntr_r PMCCNTR;         // 0x01A0
16356     STRUCT pmccntr_cfg_r PMCCNTR_CFG; // 0x01A8
16357     STRUCT pmcaxi_chan_r PMCAXI_CHAN; // 0x01AC
16358     uint32_t unused7[20];
16359     STRUCT kernel_x_r KERNEL_X;                     // 0x0200
16360     STRUCT kernel_y_r KERNEL_Y;                     // 0x0204
16361     STRUCT kernel_w_m1_r KERNEL_W_M1;               // 0x0208
16362     STRUCT kernel_h_m1_r KERNEL_H_M1;               // 0x020C
16363     STRUCT ofm_cblk_width_m1_r OFM_CBLK_WIDTH_M1;   // 0x0210
16364     STRUCT ofm_cblk_height_m1_r OFM_CBLK_HEIGHT_M1; // 0x0214
16365     STRUCT ofm_cblk_depth_m1_r OFM_CBLK_DEPTH_M1;   // 0x0218
16366     STRUCT ifm_cblk_depth_m1_r IFM_CBLK_DEPTH_M1;   // 0x021C
16367     STRUCT ofm_x_r OFM_X;                           // 0x0220
16368     STRUCT ofm_y_r OFM_Y;                           // 0x0224
16369     STRUCT ofm_z_r OFM_Z;                           // 0x0228
16370     STRUCT ifm_z_r IFM_Z;                           // 0x022C
16371     STRUCT pad_top_r PAD_TOP;                       // 0x0230
16372     STRUCT pad_left_r PAD_LEFT;                     // 0x0234
16373     STRUCT ifm_cblk_width_r IFM_CBLK_WIDTH;         // 0x0238
16374     STRUCT ifm_cblk_height_r IFM_CBLK_HEIGHT;       // 0x023C
16375     STRUCT dma_ifm_src_r DMA_IFM_SRC;               // 0x0240
16376     STRUCT dma_ifm_dst_r DMA_IFM_DST;               // 0x0248
16377     STRUCT dma_ofm_src_r DMA_OFM_SRC;               // 0x024C
16378     STRUCT dma_ofm_dst_r DMA_OFM_DST;               // 0x0250
16379     STRUCT dma_weight_src_r DMA_WEIGHT_SRC;         // 0x0258
16380     STRUCT dma_cmd_src_r DMA_CMD_SRC;               // 0x0260
16381     STRUCT dma_cmd_size_r DMA_CMD_SIZE;             // 0x0268
16382     STRUCT dma_m2m_src_r DMA_M2M_SRC;               // 0x026C
16383     STRUCT dma_m2m_dst_r DMA_M2M_DST;               // 0x0274
16384     STRUCT current_qread_r CURRENT_QREAD;           // 0x027C
16385     STRUCT dma_scale_src_r DMA_SCALE_SRC;           // 0x0280
16386     uint32_t unused8[11];
16387     STRUCT current_block_r CURRENT_BLOCK; // 0x02B4
16388     STRUCT current_op_r CURRENT_OP;       // 0x02B8
16389     STRUCT current_cmd_r CURRENT_CMD;     // 0x02BC
16390     uint32_t unused9[16];
16391     STRUCT pmevcntr_r PMEVCNTR[4]; // 0x0300
16392     uint32_t unused10[28];
16393     STRUCT pmevtyper_r PMEVTYPER[4]; // 0x0380
16394     uint32_t unused11[28];
16395     STRUCT shared_buffer_r SHARED_BUFFER[256]; // 0x0400
16396     STRUCT ifm_pad_top_r IFM_PAD_TOP;          // 0x0800
16397     STRUCT ifm_pad_left_r IFM_PAD_LEFT;        // 0x0804
16398     STRUCT ifm_pad_right_r IFM_PAD_RIGHT;      // 0x0808
16399     STRUCT ifm_pad_bottom_r IFM_PAD_BOTTOM;    // 0x080C
16400     STRUCT ifm_depth_m1_r IFM_DEPTH_M1;        // 0x0810
16401     STRUCT ifm_precision_r IFM_PRECISION;      // 0x0814
16402     uint32_t unused12[1];
16403     STRUCT ifm_upscale_r IFM_UPSCALE; // 0x081C
16404     uint32_t unused13[1];
16405     STRUCT ifm_zero_point_r IFM_ZERO_POINT; // 0x0824
16406     STRUCT ifm_width0_m1_r IFM_WIDTH0_M1;   // 0x0828
16407     STRUCT ifm_height0_m1_r IFM_HEIGHT0_M1; // 0x082C
16408     STRUCT ifm_height1_m1_r IFM_HEIGHT1_M1; // 0x0830
16409     STRUCT ifm_ib_end_r IFM_IB_END;         // 0x0834
16410     uint32_t unused14[1];
16411     STRUCT ifm_region_r IFM_REGION; // 0x083C
16412     uint32_t unused15[1];
16413     STRUCT ofm_width_m1_r OFM_WIDTH_M1;           // 0x0844
16414     STRUCT ofm_height_m1_r OFM_HEIGHT_M1;         // 0x0848
16415     STRUCT ofm_depth_m1_r OFM_DEPTH_M1;           // 0x084C
16416     STRUCT ofm_precision_r OFM_PRECISION;         // 0x0850
16417     STRUCT ofm_blk_width_m1_r OFM_BLK_WIDTH_M1;   // 0x0854
16418     STRUCT ofm_blk_height_m1_r OFM_BLK_HEIGHT_M1; // 0x0858
16419     STRUCT ofm_blk_depth_m1_r OFM_BLK_DEPTH_M1;   // 0x085C
16420     STRUCT ofm_zero_point_r OFM_ZERO_POINT;       // 0x0860
16421     uint32_t unused16[1];
16422     STRUCT ofm_width0_m1_r OFM_WIDTH0_M1;   // 0x0868
16423     STRUCT ofm_height0_m1_r OFM_HEIGHT0_M1; // 0x086C
16424     STRUCT ofm_height1_m1_r OFM_HEIGHT1_M1; // 0x0870
16425     uint32_t unused17[2];
16426     STRUCT ofm_region_r OFM_REGION;             // 0x087C
16427     STRUCT kernel_width_m1_r KERNEL_WIDTH_M1;   // 0x0880
16428     STRUCT kernel_height_m1_r KERNEL_HEIGHT_M1; // 0x0884
16429     STRUCT kernel_stride_r KERNEL_STRIDE;       // 0x0888
16430     STRUCT parallel_mode_r PARALLEL_MODE;       // 0x088C
16431     STRUCT acc_format_r ACC_FORMAT;             // 0x0890
16432     STRUCT activation_r ACTIVATION;             // 0x0894
16433     STRUCT activation_min_r ACTIVATION_MIN;     // 0x0898
16434     STRUCT activation_max_r ACTIVATION_MAX;     // 0x089C
16435     STRUCT weight_region_r WEIGHT_REGION;       // 0x08A0
16436     STRUCT scale_region_r SCALE_REGION;         // 0x08A4
16437     uint32_t unused18[3];
16438     STRUCT ab_start_r AB_START; // 0x08B4
16439     uint32_t unused19[1];
16440     STRUCT blockdep_r BLOCKDEP;               // 0x08BC
16441     STRUCT dma0_src_region_r DMA0_SRC_REGION; // 0x08C0
16442     STRUCT dma0_dst_region_r DMA0_DST_REGION; // 0x08C4
16443     STRUCT dma0_size0_r DMA0_SIZE0;           // 0x08C8
16444     STRUCT dma0_size1_r DMA0_SIZE1;           // 0x08CC
16445     uint32_t unused20[12];
16446     STRUCT ifm2_broadcast_r IFM2_BROADCAST; // 0x0900
16447     STRUCT ifm2_scalar_r IFM2_SCALAR;       // 0x0904
16448     uint32_t unused21[3];
16449     STRUCT ifm2_precision_r IFM2_PRECISION; // 0x0914
16450     uint32_t unused22[3];
16451     STRUCT ifm2_zero_point_r IFM2_ZERO_POINT; // 0x0924
16452     STRUCT ifm2_width0_m1_r IFM2_WIDTH0_M1;   // 0x0928
16453     STRUCT ifm2_height0_m1_r IFM2_HEIGHT0_M1; // 0x092C
16454     STRUCT ifm2_height1_m1_r IFM2_HEIGHT1_M1; // 0x0930
16455     STRUCT ifm2_ib_start_r IFM2_IB_START;     // 0x0934
16456     uint32_t unused23[1];
16457     STRUCT ifm2_region_r IFM2_REGION; // 0x093C
16458     uint32_t unused24[48];
16459     STRUCT ifm_base0_r IFM_BASE0;       // 0x0A00
16460     STRUCT ifm_base1_r IFM_BASE1;       // 0x0A08
16461     STRUCT ifm_base2_r IFM_BASE2;       // 0x0A10
16462     STRUCT ifm_base3_r IFM_BASE3;       // 0x0A18
16463     STRUCT ifm_stride_x_r IFM_STRIDE_X; // 0x0A20
16464     STRUCT ifm_stride_y_r IFM_STRIDE_Y; // 0x0A28
16465     STRUCT ifm_stride_c_r IFM_STRIDE_C; // 0x0A30
16466     uint32_t unused25[2];
16467     STRUCT ofm_base0_r OFM_BASE0;       // 0x0A40
16468     STRUCT ofm_base1_r OFM_BASE1;       // 0x0A48
16469     STRUCT ofm_base2_r OFM_BASE2;       // 0x0A50
16470     STRUCT ofm_base3_r OFM_BASE3;       // 0x0A58
16471     STRUCT ofm_stride_x_r OFM_STRIDE_X; // 0x0A60
16472     STRUCT ofm_stride_y_r OFM_STRIDE_Y; // 0x0A68
16473     STRUCT ofm_stride_c_r OFM_STRIDE_C; // 0x0A70
16474     uint32_t unused26[2];
16475     STRUCT weight_base_r WEIGHT_BASE;         // 0x0A80
16476     STRUCT weight_length_r WEIGHT_LENGTH;     // 0x0A88
16477     STRUCT scale_base_r SCALE_BASE;           // 0x0A90
16478     STRUCT scale_length_r SCALE_LENGTH;       // 0x0A98
16479     STRUCT ofm_scale_r OFM_SCALE;             // 0x0AA0
16480     STRUCT ofm_scale_shift_r OFM_SCALE_SHIFT; // 0x0AA4
16481     STRUCT opa_scale_r OPA_SCALE;             // 0x0AA8
16482     STRUCT opa_scale_shift_r OPA_SCALE_SHIFT; // 0x0AAC
16483     STRUCT opb_scale_r OPB_SCALE;             // 0x0AB0
16484     uint32_t unused27[3];
16485     STRUCT dma0_src_r DMA0_SRC;     // 0x0AC0
16486     STRUCT dma0_dst_r DMA0_DST;     // 0x0AC8
16487     STRUCT dma0_len_r DMA0_LEN;     // 0x0AD0
16488     STRUCT dma0_skip0_r DMA0_SKIP0; // 0x0AD8
16489     STRUCT dma0_skip1_r DMA0_SKIP1; // 0x0AE0
16490     uint32_t unused28[6];
16491     STRUCT ifm2_base0_r IFM2_BASE0;       // 0x0B00
16492     STRUCT ifm2_base1_r IFM2_BASE1;       // 0x0B08
16493     STRUCT ifm2_base2_r IFM2_BASE2;       // 0x0B10
16494     STRUCT ifm2_base3_r IFM2_BASE3;       // 0x0B18
16495     STRUCT ifm2_stride_x_r IFM2_STRIDE_X; // 0x0B20
16496     STRUCT ifm2_stride_y_r IFM2_STRIDE_Y; // 0x0B28
16497     STRUCT ifm2_stride_c_r IFM2_STRIDE_C; // 0x0B30
16498     uint32_t unused29[2];
16499     STRUCT weight1_base_r WEIGHT1_BASE;     // 0x0B40
16500     STRUCT weight1_length_r WEIGHT1_LENGTH; // 0x0B48
16501     STRUCT scale1_base_r SCALE1_BASE;       // 0x0B50
16502     STRUCT scale1_length_r SCALE1_LENGTH;   // 0x0B58
16503     uint32_t unused30[280];
16504     STRUCT revision_r REVISION; // 0x0FC0
16505     uint32_t unused31[3];
16506     STRUCT pid4_r PID4; // 0x0FD0
16507     STRUCT pid5_r PID5; // 0x0FD4
16508     STRUCT pid6_r PID6; // 0x0FD8
16509     STRUCT pid7_r PID7; // 0x0FDC
16510     STRUCT pid0_r PID0; // 0x0FE0
16511     STRUCT pid1_r PID1; // 0x0FE4
16512     STRUCT pid2_r PID2; // 0x0FE8
16513     STRUCT pid3_r PID3; // 0x0FEC
16514     STRUCT cid0_r CID0; // 0x0FF0
16515     STRUCT cid1_r CID1; // 0x0FF4
16516     STRUCT cid2_r CID2; // 0x0FF8
16517     STRUCT cid3_r CID3; // 0x0FFC
16518 
16519 #ifdef __cplusplus
16520     enum class access_type_t : uint8_t
16521     {
16522         RW,
16523         RO,
16524         WO
16525     };
NPU_REGNPU_REG16526     NPU_REG()
16527     {
16528         reset();
16529     }
resetNPU_REG16530     void reset()
16531     {
16532         ID         = 268853249;
16533         STATUS     = 8;
16534         CMD        = 12;
16535         RESET      = 0;
16536         QBASE      = 0;
16537         QREAD      = 0;
16538         QCONFIG    = 0;
16539         QSIZE      = 0;
16540         PROT       = 0;
16541         CONFIG     = 268435456;
16542         LOCK       = 0;
16543         REGIONCFG  = 0;
16544         AXI_LIMIT0 = 0;
16545         AXI_LIMIT1 = 0;
16546         AXI_LIMIT2 = 0;
16547         AXI_LIMIT3 = 0;
16548         for (size_t i = 0; i < (sizeof(BASEP) / sizeof(BASEP[0])); ++i)
16549             BASEP[i] = 0;
16550         WD_STATUS          = 0;
16551         MAC_STATUS         = 0;
16552         AO_STATUS          = 0;
16553         DMA_STATUS0        = 0;
16554         DMA_STATUS1        = 0;
16555         CLKFORCE           = 0;
16556         DEBUG_ADDRESS      = 0;
16557         DEBUG_MISC         = 0;
16558         DEBUGCORE          = 0;
16559         DEBUG_BLOCK        = 0;
16560         PMCR               = 8192;
16561         PMCNTENSET         = 0;
16562         PMCNTENCLR         = 0;
16563         PMOVSSET           = 0;
16564         PMOVSCLR           = 0;
16565         PMINTSET           = 0;
16566         PMINTCLR           = 0;
16567         PMCCNTR            = 0;
16568         PMCCNTR_CFG        = 0;
16569         PMCAXI_CHAN        = 0;
16570         KERNEL_X           = 0;
16571         KERNEL_Y           = 0;
16572         KERNEL_W_M1        = 0;
16573         KERNEL_H_M1        = 0;
16574         OFM_CBLK_WIDTH_M1  = 0;
16575         OFM_CBLK_HEIGHT_M1 = 0;
16576         OFM_CBLK_DEPTH_M1  = 0;
16577         IFM_CBLK_DEPTH_M1  = 0;
16578         OFM_X              = 0;
16579         OFM_Y              = 0;
16580         OFM_Z              = 0;
16581         IFM_Z              = 0;
16582         PAD_TOP            = 0;
16583         PAD_LEFT           = 0;
16584         IFM_CBLK_WIDTH     = 0;
16585         IFM_CBLK_HEIGHT    = 0;
16586         DMA_IFM_SRC        = 0;
16587         DMA_IFM_DST        = 0;
16588         DMA_OFM_SRC        = 0;
16589         DMA_OFM_DST        = 0;
16590         DMA_WEIGHT_SRC     = 0;
16591         DMA_CMD_SRC        = 0;
16592         DMA_CMD_SIZE       = 0;
16593         DMA_M2M_SRC        = 0;
16594         DMA_M2M_DST        = 0;
16595         CURRENT_QREAD      = 0;
16596         DMA_SCALE_SRC      = 0;
16597         CURRENT_BLOCK      = 0;
16598         CURRENT_OP         = 0;
16599         CURRENT_CMD        = 0;
16600         for (size_t i = 0; i < (sizeof(PMEVCNTR) / sizeof(PMEVCNTR[0])); ++i)
16601             PMEVCNTR[i] = 0;
16602         for (size_t i = 0; i < (sizeof(PMEVTYPER) / sizeof(PMEVTYPER[0])); ++i)
16603             PMEVTYPER[i] = 0;
16604         for (size_t i = 0; i < (sizeof(SHARED_BUFFER) / sizeof(SHARED_BUFFER[0])); ++i)
16605             SHARED_BUFFER[i] = 0;
16606         IFM_PAD_TOP       = 0;
16607         IFM_PAD_LEFT      = 0;
16608         IFM_PAD_RIGHT     = 0;
16609         IFM_PAD_BOTTOM    = 0;
16610         IFM_DEPTH_M1      = 0;
16611         IFM_PRECISION     = 0;
16612         IFM_UPSCALE       = 0;
16613         IFM_ZERO_POINT    = 0;
16614         IFM_WIDTH0_M1     = 0;
16615         IFM_HEIGHT0_M1    = 0;
16616         IFM_HEIGHT1_M1    = 0;
16617         IFM_IB_END        = 0;
16618         IFM_REGION        = 0;
16619         OFM_WIDTH_M1      = 0;
16620         OFM_HEIGHT_M1     = 0;
16621         OFM_DEPTH_M1      = 0;
16622         OFM_PRECISION     = 0;
16623         OFM_BLK_WIDTH_M1  = 0;
16624         OFM_BLK_HEIGHT_M1 = 0;
16625         OFM_BLK_DEPTH_M1  = 0;
16626         OFM_ZERO_POINT    = 0;
16627         OFM_WIDTH0_M1     = 0;
16628         OFM_HEIGHT0_M1    = 0;
16629         OFM_HEIGHT1_M1    = 0;
16630         OFM_REGION        = 0;
16631         KERNEL_WIDTH_M1   = 0;
16632         KERNEL_HEIGHT_M1  = 0;
16633         KERNEL_STRIDE     = 0;
16634         PARALLEL_MODE     = 0;
16635         ACC_FORMAT        = 0;
16636         ACTIVATION        = 0;
16637         ACTIVATION_MIN    = 0;
16638         ACTIVATION_MAX    = 0;
16639         WEIGHT_REGION     = 0;
16640         SCALE_REGION      = 0;
16641         AB_START          = 0;
16642         BLOCKDEP          = 0;
16643         DMA0_SRC_REGION   = 0;
16644         DMA0_DST_REGION   = 0;
16645         DMA0_SIZE0        = 0;
16646         DMA0_SIZE1        = 0;
16647         IFM2_BROADCAST    = 0;
16648         IFM2_SCALAR       = 0;
16649         IFM2_PRECISION    = 0;
16650         IFM2_ZERO_POINT   = 0;
16651         IFM2_WIDTH0_M1    = 0;
16652         IFM2_HEIGHT0_M1   = 0;
16653         IFM2_HEIGHT1_M1   = 0;
16654         IFM2_IB_START     = 0;
16655         IFM2_REGION       = 0;
16656         IFM_BASE0         = 0;
16657         IFM_BASE1         = 0;
16658         IFM_BASE2         = 0;
16659         IFM_BASE3         = 0;
16660         IFM_STRIDE_X      = 0;
16661         IFM_STRIDE_Y      = 0;
16662         IFM_STRIDE_C      = 0;
16663         OFM_BASE0         = 0;
16664         OFM_BASE1         = 0;
16665         OFM_BASE2         = 0;
16666         OFM_BASE3         = 0;
16667         OFM_STRIDE_X      = 0;
16668         OFM_STRIDE_Y      = 0;
16669         OFM_STRIDE_C      = 0;
16670         WEIGHT_BASE       = 0;
16671         WEIGHT_LENGTH     = 0;
16672         SCALE_BASE        = 0;
16673         SCALE_LENGTH      = 0;
16674         OFM_SCALE         = 0;
16675         OFM_SCALE_SHIFT   = 0;
16676         OPA_SCALE         = 0;
16677         OPA_SCALE_SHIFT   = 0;
16678         OPB_SCALE         = 0;
16679         DMA0_SRC          = 0;
16680         DMA0_DST          = 0;
16681         DMA0_LEN          = 0;
16682         DMA0_SKIP0        = 0;
16683         DMA0_SKIP1        = 0;
16684         IFM2_BASE0        = 0;
16685         IFM2_BASE1        = 0;
16686         IFM2_BASE2        = 0;
16687         IFM2_BASE3        = 0;
16688         IFM2_STRIDE_X     = 0;
16689         IFM2_STRIDE_Y     = 0;
16690         IFM2_STRIDE_C     = 0;
16691         WEIGHT1_BASE      = 0;
16692         WEIGHT1_LENGTH    = 0;
16693         SCALE1_BASE       = 0;
16694         SCALE1_LENGTH     = 0;
16695         REVISION          = 0;
16696         PID4              = 4;
16697         PID5              = 0;
16698         PID6              = 0;
16699         PID7              = 0;
16700         PID0              = 129;
16701         PID1              = 181;
16702         PID2              = 11;
16703         PID3              = 0;
16704         CID0              = 13;
16705         CID1              = 240;
16706         CID2              = 5;
16707         CID3              = 177;
16708     }
16709     uint32_t &operator[](const int addr_offset)
16710     {
16711         return reinterpret_cast<uint32_t *>(this)[addr_offset / 4];
16712     }
get_access_typeNPU_REG16713     access_type_t get_access_type(uint32_t offset)
16714     {
16715         switch (offset)
16716         {
16717         case 0:
16718             return access_type_t::RO;
16719         case 4:
16720             return access_type_t::RO;
16721         case 8:
16722             return access_type_t::RW;
16723         case 12:
16724             return access_type_t::RW;
16725         case 16:
16726             return access_type_t::RW;
16727         case 24:
16728             return access_type_t::RO;
16729         case 28:
16730             return access_type_t::RW;
16731         case 32:
16732             return access_type_t::RW;
16733         case 36:
16734             return access_type_t::RO;
16735         case 40:
16736             return access_type_t::RO;
16737         case 44:
16738             return access_type_t::RW;
16739         case 60:
16740             return access_type_t::RW;
16741         case 64:
16742             return access_type_t::RW;
16743         case 68:
16744             return access_type_t::RW;
16745         case 72:
16746             return access_type_t::RW;
16747         case 76:
16748             return access_type_t::RW;
16749         case 128:
16750             return access_type_t::RW;
16751         case 136:
16752             return access_type_t::RW;
16753         case 144:
16754             return access_type_t::RW;
16755         case 152:
16756             return access_type_t::RW;
16757         case 160:
16758             return access_type_t::RW;
16759         case 168:
16760             return access_type_t::RW;
16761         case 176:
16762             return access_type_t::RW;
16763         case 184:
16764             return access_type_t::RW;
16765         case 256:
16766             return access_type_t::RO;
16767         case 260:
16768             return access_type_t::RO;
16769         case 264:
16770             return access_type_t::RO;
16771         case 272:
16772             return access_type_t::RO;
16773         case 276:
16774             return access_type_t::RO;
16775         case 320:
16776             return access_type_t::RW;
16777         case 324:
16778             return access_type_t::RW;
16779         case 328:
16780             return access_type_t::RW;
16781         case 332:
16782             return access_type_t::RW;
16783         case 336:
16784             return access_type_t::RW;
16785         case 384:
16786             return access_type_t::RW;
16787         case 388:
16788             return access_type_t::RW;
16789         case 392:
16790             return access_type_t::RW;
16791         case 396:
16792             return access_type_t::RW;
16793         case 400:
16794             return access_type_t::RW;
16795         case 404:
16796             return access_type_t::RW;
16797         case 408:
16798             return access_type_t::RW;
16799         case 416:
16800             return access_type_t::RW;
16801         case 424:
16802             return access_type_t::RW;
16803         case 428:
16804             return access_type_t::RW;
16805         case 512:
16806             return access_type_t::RO;
16807         case 516:
16808             return access_type_t::RO;
16809         case 520:
16810             return access_type_t::RO;
16811         case 524:
16812             return access_type_t::RO;
16813         case 528:
16814             return access_type_t::RO;
16815         case 532:
16816             return access_type_t::RO;
16817         case 536:
16818             return access_type_t::RO;
16819         case 540:
16820             return access_type_t::RO;
16821         case 544:
16822             return access_type_t::RO;
16823         case 548:
16824             return access_type_t::RO;
16825         case 552:
16826             return access_type_t::RO;
16827         case 556:
16828             return access_type_t::RO;
16829         case 560:
16830             return access_type_t::RO;
16831         case 564:
16832             return access_type_t::RO;
16833         case 568:
16834             return access_type_t::RO;
16835         case 572:
16836             return access_type_t::RO;
16837         case 576:
16838             return access_type_t::RO;
16839         case 584:
16840             return access_type_t::RO;
16841         case 588:
16842             return access_type_t::RO;
16843         case 592:
16844             return access_type_t::RO;
16845         case 600:
16846             return access_type_t::RO;
16847         case 608:
16848             return access_type_t::RO;
16849         case 616:
16850             return access_type_t::RO;
16851         case 620:
16852             return access_type_t::RO;
16853         case 628:
16854             return access_type_t::RO;
16855         case 636:
16856             return access_type_t::RO;
16857         case 640:
16858             return access_type_t::RO;
16859         case 692:
16860             return access_type_t::RO;
16861         case 696:
16862             return access_type_t::RO;
16863         case 700:
16864             return access_type_t::RO;
16865         case 768:
16866             return access_type_t::RW;
16867         case 772:
16868             return access_type_t::RW;
16869         case 776:
16870             return access_type_t::RW;
16871         case 780:
16872             return access_type_t::RW;
16873         case 896:
16874             return access_type_t::RW;
16875         case 900:
16876             return access_type_t::RW;
16877         case 904:
16878             return access_type_t::RW;
16879         case 908:
16880             return access_type_t::RW;
16881         case 1024:
16882             return access_type_t::RW;
16883         case 1028:
16884             return access_type_t::RW;
16885         case 1032:
16886             return access_type_t::RW;
16887         case 1036:
16888             return access_type_t::RW;
16889         case 1040:
16890             return access_type_t::RW;
16891         case 1044:
16892             return access_type_t::RW;
16893         case 1048:
16894             return access_type_t::RW;
16895         case 1052:
16896             return access_type_t::RW;
16897         case 1056:
16898             return access_type_t::RW;
16899         case 1060:
16900             return access_type_t::RW;
16901         case 1064:
16902             return access_type_t::RW;
16903         case 1068:
16904             return access_type_t::RW;
16905         case 1072:
16906             return access_type_t::RW;
16907         case 1076:
16908             return access_type_t::RW;
16909         case 1080:
16910             return access_type_t::RW;
16911         case 1084:
16912             return access_type_t::RW;
16913         case 1088:
16914             return access_type_t::RW;
16915         case 1092:
16916             return access_type_t::RW;
16917         case 1096:
16918             return access_type_t::RW;
16919         case 1100:
16920             return access_type_t::RW;
16921         case 1104:
16922             return access_type_t::RW;
16923         case 1108:
16924             return access_type_t::RW;
16925         case 1112:
16926             return access_type_t::RW;
16927         case 1116:
16928             return access_type_t::RW;
16929         case 1120:
16930             return access_type_t::RW;
16931         case 1124:
16932             return access_type_t::RW;
16933         case 1128:
16934             return access_type_t::RW;
16935         case 1132:
16936             return access_type_t::RW;
16937         case 1136:
16938             return access_type_t::RW;
16939         case 1140:
16940             return access_type_t::RW;
16941         case 1144:
16942             return access_type_t::RW;
16943         case 1148:
16944             return access_type_t::RW;
16945         case 1152:
16946             return access_type_t::RW;
16947         case 1156:
16948             return access_type_t::RW;
16949         case 1160:
16950             return access_type_t::RW;
16951         case 1164:
16952             return access_type_t::RW;
16953         case 1168:
16954             return access_type_t::RW;
16955         case 1172:
16956             return access_type_t::RW;
16957         case 1176:
16958             return access_type_t::RW;
16959         case 1180:
16960             return access_type_t::RW;
16961         case 1184:
16962             return access_type_t::RW;
16963         case 1188:
16964             return access_type_t::RW;
16965         case 1192:
16966             return access_type_t::RW;
16967         case 1196:
16968             return access_type_t::RW;
16969         case 1200:
16970             return access_type_t::RW;
16971         case 1204:
16972             return access_type_t::RW;
16973         case 1208:
16974             return access_type_t::RW;
16975         case 1212:
16976             return access_type_t::RW;
16977         case 1216:
16978             return access_type_t::RW;
16979         case 1220:
16980             return access_type_t::RW;
16981         case 1224:
16982             return access_type_t::RW;
16983         case 1228:
16984             return access_type_t::RW;
16985         case 1232:
16986             return access_type_t::RW;
16987         case 1236:
16988             return access_type_t::RW;
16989         case 1240:
16990             return access_type_t::RW;
16991         case 1244:
16992             return access_type_t::RW;
16993         case 1248:
16994             return access_type_t::RW;
16995         case 1252:
16996             return access_type_t::RW;
16997         case 1256:
16998             return access_type_t::RW;
16999         case 1260:
17000             return access_type_t::RW;
17001         case 1264:
17002             return access_type_t::RW;
17003         case 1268:
17004             return access_type_t::RW;
17005         case 1272:
17006             return access_type_t::RW;
17007         case 1276:
17008             return access_type_t::RW;
17009         case 1280:
17010             return access_type_t::RW;
17011         case 1284:
17012             return access_type_t::RW;
17013         case 1288:
17014             return access_type_t::RW;
17015         case 1292:
17016             return access_type_t::RW;
17017         case 1296:
17018             return access_type_t::RW;
17019         case 1300:
17020             return access_type_t::RW;
17021         case 1304:
17022             return access_type_t::RW;
17023         case 1308:
17024             return access_type_t::RW;
17025         case 1312:
17026             return access_type_t::RW;
17027         case 1316:
17028             return access_type_t::RW;
17029         case 1320:
17030             return access_type_t::RW;
17031         case 1324:
17032             return access_type_t::RW;
17033         case 1328:
17034             return access_type_t::RW;
17035         case 1332:
17036             return access_type_t::RW;
17037         case 1336:
17038             return access_type_t::RW;
17039         case 1340:
17040             return access_type_t::RW;
17041         case 1344:
17042             return access_type_t::RW;
17043         case 1348:
17044             return access_type_t::RW;
17045         case 1352:
17046             return access_type_t::RW;
17047         case 1356:
17048             return access_type_t::RW;
17049         case 1360:
17050             return access_type_t::RW;
17051         case 1364:
17052             return access_type_t::RW;
17053         case 1368:
17054             return access_type_t::RW;
17055         case 1372:
17056             return access_type_t::RW;
17057         case 1376:
17058             return access_type_t::RW;
17059         case 1380:
17060             return access_type_t::RW;
17061         case 1384:
17062             return access_type_t::RW;
17063         case 1388:
17064             return access_type_t::RW;
17065         case 1392:
17066             return access_type_t::RW;
17067         case 1396:
17068             return access_type_t::RW;
17069         case 1400:
17070             return access_type_t::RW;
17071         case 1404:
17072             return access_type_t::RW;
17073         case 1408:
17074             return access_type_t::RW;
17075         case 1412:
17076             return access_type_t::RW;
17077         case 1416:
17078             return access_type_t::RW;
17079         case 1420:
17080             return access_type_t::RW;
17081         case 1424:
17082             return access_type_t::RW;
17083         case 1428:
17084             return access_type_t::RW;
17085         case 1432:
17086             return access_type_t::RW;
17087         case 1436:
17088             return access_type_t::RW;
17089         case 1440:
17090             return access_type_t::RW;
17091         case 1444:
17092             return access_type_t::RW;
17093         case 1448:
17094             return access_type_t::RW;
17095         case 1452:
17096             return access_type_t::RW;
17097         case 1456:
17098             return access_type_t::RW;
17099         case 1460:
17100             return access_type_t::RW;
17101         case 1464:
17102             return access_type_t::RW;
17103         case 1468:
17104             return access_type_t::RW;
17105         case 1472:
17106             return access_type_t::RW;
17107         case 1476:
17108             return access_type_t::RW;
17109         case 1480:
17110             return access_type_t::RW;
17111         case 1484:
17112             return access_type_t::RW;
17113         case 1488:
17114             return access_type_t::RW;
17115         case 1492:
17116             return access_type_t::RW;
17117         case 1496:
17118             return access_type_t::RW;
17119         case 1500:
17120             return access_type_t::RW;
17121         case 1504:
17122             return access_type_t::RW;
17123         case 1508:
17124             return access_type_t::RW;
17125         case 1512:
17126             return access_type_t::RW;
17127         case 1516:
17128             return access_type_t::RW;
17129         case 1520:
17130             return access_type_t::RW;
17131         case 1524:
17132             return access_type_t::RW;
17133         case 1528:
17134             return access_type_t::RW;
17135         case 1532:
17136             return access_type_t::RW;
17137         case 1536:
17138             return access_type_t::RW;
17139         case 1540:
17140             return access_type_t::RW;
17141         case 1544:
17142             return access_type_t::RW;
17143         case 1548:
17144             return access_type_t::RW;
17145         case 1552:
17146             return access_type_t::RW;
17147         case 1556:
17148             return access_type_t::RW;
17149         case 1560:
17150             return access_type_t::RW;
17151         case 1564:
17152             return access_type_t::RW;
17153         case 1568:
17154             return access_type_t::RW;
17155         case 1572:
17156             return access_type_t::RW;
17157         case 1576:
17158             return access_type_t::RW;
17159         case 1580:
17160             return access_type_t::RW;
17161         case 1584:
17162             return access_type_t::RW;
17163         case 1588:
17164             return access_type_t::RW;
17165         case 1592:
17166             return access_type_t::RW;
17167         case 1596:
17168             return access_type_t::RW;
17169         case 1600:
17170             return access_type_t::RW;
17171         case 1604:
17172             return access_type_t::RW;
17173         case 1608:
17174             return access_type_t::RW;
17175         case 1612:
17176             return access_type_t::RW;
17177         case 1616:
17178             return access_type_t::RW;
17179         case 1620:
17180             return access_type_t::RW;
17181         case 1624:
17182             return access_type_t::RW;
17183         case 1628:
17184             return access_type_t::RW;
17185         case 1632:
17186             return access_type_t::RW;
17187         case 1636:
17188             return access_type_t::RW;
17189         case 1640:
17190             return access_type_t::RW;
17191         case 1644:
17192             return access_type_t::RW;
17193         case 1648:
17194             return access_type_t::RW;
17195         case 1652:
17196             return access_type_t::RW;
17197         case 1656:
17198             return access_type_t::RW;
17199         case 1660:
17200             return access_type_t::RW;
17201         case 1664:
17202             return access_type_t::RW;
17203         case 1668:
17204             return access_type_t::RW;
17205         case 1672:
17206             return access_type_t::RW;
17207         case 1676:
17208             return access_type_t::RW;
17209         case 1680:
17210             return access_type_t::RW;
17211         case 1684:
17212             return access_type_t::RW;
17213         case 1688:
17214             return access_type_t::RW;
17215         case 1692:
17216             return access_type_t::RW;
17217         case 1696:
17218             return access_type_t::RW;
17219         case 1700:
17220             return access_type_t::RW;
17221         case 1704:
17222             return access_type_t::RW;
17223         case 1708:
17224             return access_type_t::RW;
17225         case 1712:
17226             return access_type_t::RW;
17227         case 1716:
17228             return access_type_t::RW;
17229         case 1720:
17230             return access_type_t::RW;
17231         case 1724:
17232             return access_type_t::RW;
17233         case 1728:
17234             return access_type_t::RW;
17235         case 1732:
17236             return access_type_t::RW;
17237         case 1736:
17238             return access_type_t::RW;
17239         case 1740:
17240             return access_type_t::RW;
17241         case 1744:
17242             return access_type_t::RW;
17243         case 1748:
17244             return access_type_t::RW;
17245         case 1752:
17246             return access_type_t::RW;
17247         case 1756:
17248             return access_type_t::RW;
17249         case 1760:
17250             return access_type_t::RW;
17251         case 1764:
17252             return access_type_t::RW;
17253         case 1768:
17254             return access_type_t::RW;
17255         case 1772:
17256             return access_type_t::RW;
17257         case 1776:
17258             return access_type_t::RW;
17259         case 1780:
17260             return access_type_t::RW;
17261         case 1784:
17262             return access_type_t::RW;
17263         case 1788:
17264             return access_type_t::RW;
17265         case 1792:
17266             return access_type_t::RW;
17267         case 1796:
17268             return access_type_t::RW;
17269         case 1800:
17270             return access_type_t::RW;
17271         case 1804:
17272             return access_type_t::RW;
17273         case 1808:
17274             return access_type_t::RW;
17275         case 1812:
17276             return access_type_t::RW;
17277         case 1816:
17278             return access_type_t::RW;
17279         case 1820:
17280             return access_type_t::RW;
17281         case 1824:
17282             return access_type_t::RW;
17283         case 1828:
17284             return access_type_t::RW;
17285         case 1832:
17286             return access_type_t::RW;
17287         case 1836:
17288             return access_type_t::RW;
17289         case 1840:
17290             return access_type_t::RW;
17291         case 1844:
17292             return access_type_t::RW;
17293         case 1848:
17294             return access_type_t::RW;
17295         case 1852:
17296             return access_type_t::RW;
17297         case 1856:
17298             return access_type_t::RW;
17299         case 1860:
17300             return access_type_t::RW;
17301         case 1864:
17302             return access_type_t::RW;
17303         case 1868:
17304             return access_type_t::RW;
17305         case 1872:
17306             return access_type_t::RW;
17307         case 1876:
17308             return access_type_t::RW;
17309         case 1880:
17310             return access_type_t::RW;
17311         case 1884:
17312             return access_type_t::RW;
17313         case 1888:
17314             return access_type_t::RW;
17315         case 1892:
17316             return access_type_t::RW;
17317         case 1896:
17318             return access_type_t::RW;
17319         case 1900:
17320             return access_type_t::RW;
17321         case 1904:
17322             return access_type_t::RW;
17323         case 1908:
17324             return access_type_t::RW;
17325         case 1912:
17326             return access_type_t::RW;
17327         case 1916:
17328             return access_type_t::RW;
17329         case 1920:
17330             return access_type_t::RW;
17331         case 1924:
17332             return access_type_t::RW;
17333         case 1928:
17334             return access_type_t::RW;
17335         case 1932:
17336             return access_type_t::RW;
17337         case 1936:
17338             return access_type_t::RW;
17339         case 1940:
17340             return access_type_t::RW;
17341         case 1944:
17342             return access_type_t::RW;
17343         case 1948:
17344             return access_type_t::RW;
17345         case 1952:
17346             return access_type_t::RW;
17347         case 1956:
17348             return access_type_t::RW;
17349         case 1960:
17350             return access_type_t::RW;
17351         case 1964:
17352             return access_type_t::RW;
17353         case 1968:
17354             return access_type_t::RW;
17355         case 1972:
17356             return access_type_t::RW;
17357         case 1976:
17358             return access_type_t::RW;
17359         case 1980:
17360             return access_type_t::RW;
17361         case 1984:
17362             return access_type_t::RW;
17363         case 1988:
17364             return access_type_t::RW;
17365         case 1992:
17366             return access_type_t::RW;
17367         case 1996:
17368             return access_type_t::RW;
17369         case 2000:
17370             return access_type_t::RW;
17371         case 2004:
17372             return access_type_t::RW;
17373         case 2008:
17374             return access_type_t::RW;
17375         case 2012:
17376             return access_type_t::RW;
17377         case 2016:
17378             return access_type_t::RW;
17379         case 2020:
17380             return access_type_t::RW;
17381         case 2024:
17382             return access_type_t::RW;
17383         case 2028:
17384             return access_type_t::RW;
17385         case 2032:
17386             return access_type_t::RW;
17387         case 2036:
17388             return access_type_t::RW;
17389         case 2040:
17390             return access_type_t::RW;
17391         case 2044:
17392             return access_type_t::RW;
17393         case 2048:
17394             return access_type_t::RW;
17395         case 2052:
17396             return access_type_t::RW;
17397         case 2056:
17398             return access_type_t::RW;
17399         case 2060:
17400             return access_type_t::RW;
17401         case 2064:
17402             return access_type_t::RW;
17403         case 2068:
17404             return access_type_t::RW;
17405         case 2076:
17406             return access_type_t::RW;
17407         case 2084:
17408             return access_type_t::RW;
17409         case 2088:
17410             return access_type_t::RW;
17411         case 2092:
17412             return access_type_t::RW;
17413         case 2096:
17414             return access_type_t::RW;
17415         case 2100:
17416             return access_type_t::RW;
17417         case 2108:
17418             return access_type_t::RW;
17419         case 2116:
17420             return access_type_t::RW;
17421         case 2120:
17422             return access_type_t::RW;
17423         case 2124:
17424             return access_type_t::RW;
17425         case 2128:
17426             return access_type_t::RW;
17427         case 2132:
17428             return access_type_t::RW;
17429         case 2136:
17430             return access_type_t::RW;
17431         case 2140:
17432             return access_type_t::RW;
17433         case 2144:
17434             return access_type_t::RW;
17435         case 2152:
17436             return access_type_t::RW;
17437         case 2156:
17438             return access_type_t::RW;
17439         case 2160:
17440             return access_type_t::RW;
17441         case 2172:
17442             return access_type_t::RW;
17443         case 2176:
17444             return access_type_t::RW;
17445         case 2180:
17446             return access_type_t::RW;
17447         case 2184:
17448             return access_type_t::RW;
17449         case 2188:
17450             return access_type_t::RW;
17451         case 2192:
17452             return access_type_t::RW;
17453         case 2196:
17454             return access_type_t::RW;
17455         case 2200:
17456             return access_type_t::RW;
17457         case 2204:
17458             return access_type_t::RW;
17459         case 2208:
17460             return access_type_t::RW;
17461         case 2212:
17462             return access_type_t::RW;
17463         case 2228:
17464             return access_type_t::RW;
17465         case 2236:
17466             return access_type_t::RW;
17467         case 2240:
17468             return access_type_t::RW;
17469         case 2244:
17470             return access_type_t::RW;
17471         case 2248:
17472             return access_type_t::RW;
17473         case 2252:
17474             return access_type_t::RW;
17475         case 2304:
17476             return access_type_t::RW;
17477         case 2308:
17478             return access_type_t::RW;
17479         case 2324:
17480             return access_type_t::RW;
17481         case 2340:
17482             return access_type_t::RW;
17483         case 2344:
17484             return access_type_t::RW;
17485         case 2348:
17486             return access_type_t::RW;
17487         case 2352:
17488             return access_type_t::RW;
17489         case 2356:
17490             return access_type_t::RW;
17491         case 2364:
17492             return access_type_t::RW;
17493         case 2560:
17494             return access_type_t::RW;
17495         case 2568:
17496             return access_type_t::RW;
17497         case 2576:
17498             return access_type_t::RW;
17499         case 2584:
17500             return access_type_t::RW;
17501         case 2592:
17502             return access_type_t::RW;
17503         case 2600:
17504             return access_type_t::RW;
17505         case 2608:
17506             return access_type_t::RW;
17507         case 2624:
17508             return access_type_t::RW;
17509         case 2632:
17510             return access_type_t::RW;
17511         case 2640:
17512             return access_type_t::RW;
17513         case 2648:
17514             return access_type_t::RW;
17515         case 2656:
17516             return access_type_t::RW;
17517         case 2664:
17518             return access_type_t::RW;
17519         case 2672:
17520             return access_type_t::RW;
17521         case 2688:
17522             return access_type_t::RW;
17523         case 2696:
17524             return access_type_t::RW;
17525         case 2704:
17526             return access_type_t::RW;
17527         case 2712:
17528             return access_type_t::RW;
17529         case 2720:
17530             return access_type_t::RW;
17531         case 2724:
17532             return access_type_t::RW;
17533         case 2728:
17534             return access_type_t::RW;
17535         case 2732:
17536             return access_type_t::RW;
17537         case 2736:
17538             return access_type_t::RW;
17539         case 2752:
17540             return access_type_t::RW;
17541         case 2760:
17542             return access_type_t::RW;
17543         case 2768:
17544             return access_type_t::RW;
17545         case 2776:
17546             return access_type_t::RW;
17547         case 2784:
17548             return access_type_t::RW;
17549         case 2816:
17550             return access_type_t::RW;
17551         case 2824:
17552             return access_type_t::RW;
17553         case 2832:
17554             return access_type_t::RW;
17555         case 2840:
17556             return access_type_t::RW;
17557         case 2848:
17558             return access_type_t::RW;
17559         case 2856:
17560             return access_type_t::RW;
17561         case 2864:
17562             return access_type_t::RW;
17563         case 2880:
17564             return access_type_t::RW;
17565         case 2888:
17566             return access_type_t::RW;
17567         case 2896:
17568             return access_type_t::RW;
17569         case 2904:
17570             return access_type_t::RW;
17571         case 4032:
17572             return access_type_t::RO;
17573         case 4048:
17574             return access_type_t::RO;
17575         case 4052:
17576             return access_type_t::RO;
17577         case 4056:
17578             return access_type_t::RO;
17579         case 4060:
17580             return access_type_t::RO;
17581         case 4064:
17582             return access_type_t::RO;
17583         case 4068:
17584             return access_type_t::RO;
17585         case 4072:
17586             return access_type_t::RO;
17587         case 4076:
17588             return access_type_t::RO;
17589         case 4080:
17590             return access_type_t::RO;
17591         case 4084:
17592             return access_type_t::RO;
17593         case 4088:
17594             return access_type_t::RO;
17595         case 4092:
17596             return access_type_t::RO;
17597         default:
17598             return access_type_t::RO;
17599         }
17600     }
17601 #endif
17602 };
17603 
17604 #ifdef __cplusplus
17605 struct isa
17606 {
17607 #ifdef NPU_DISASSEMBLE
disassembleisa17608     static int disassemble(const uint32_t *in,
17609                            std::string &op,
17610                            std::vector<std::pair<std::string, std::string>> &fields)
17611     {
17612         switch (*in & 0xffff)
17613         {
17614         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17615             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP):
17616         {
17617             const npu_op_stop_t &v = *reinterpret_cast<const npu_op_stop_t *>(in);
17618             op                     = "NPU_OP_STOP";
17619             v.disassemble(fields);
17620             break;
17621         }
17622         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17623             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ):
17624         {
17625             const npu_op_irq_t &v = *reinterpret_cast<const npu_op_irq_t *>(in);
17626             op                    = "NPU_OP_IRQ";
17627             v.disassemble(fields);
17628             break;
17629         }
17630         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17631             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV):
17632         {
17633             const npu_op_conv_t &v = *reinterpret_cast<const npu_op_conv_t *>(in);
17634             op                     = "NPU_OP_CONV";
17635             v.disassemble(fields);
17636             break;
17637         }
17638         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17639             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE):
17640         {
17641             const npu_op_depthwise_t &v = *reinterpret_cast<const npu_op_depthwise_t *>(in);
17642             op                          = "NPU_OP_DEPTHWISE";
17643             v.disassemble(fields);
17644             break;
17645         }
17646         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17647             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL):
17648         {
17649             const npu_op_pool_t &v = *reinterpret_cast<const npu_op_pool_t *>(in);
17650             op                     = "NPU_OP_POOL";
17651             v.disassemble(fields);
17652             break;
17653         }
17654         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17655             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE):
17656         {
17657             const npu_op_elementwise_t &v = *reinterpret_cast<const npu_op_elementwise_t *>(in);
17658             op                            = "NPU_OP_ELEMENTWISE";
17659             v.disassemble(fields);
17660             break;
17661         }
17662         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17663             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START):
17664         {
17665             const npu_op_dma_start_t &v = *reinterpret_cast<const npu_op_dma_start_t *>(in);
17666             op                          = "NPU_OP_DMA_START";
17667             v.disassemble(fields);
17668             break;
17669         }
17670         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17671             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT):
17672         {
17673             const npu_op_dma_wait_t &v = *reinterpret_cast<const npu_op_dma_wait_t *>(in);
17674             op                         = "NPU_OP_DMA_WAIT";
17675             v.disassemble(fields);
17676             break;
17677         }
17678         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17679             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT):
17680         {
17681             const npu_op_kernel_wait_t &v = *reinterpret_cast<const npu_op_kernel_wait_t *>(in);
17682             op                            = "NPU_OP_KERNEL_WAIT";
17683             v.disassemble(fields);
17684             break;
17685         }
17686         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17687             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK):
17688         {
17689             const npu_op_pmu_mask_t &v = *reinterpret_cast<const npu_op_pmu_mask_t *>(in);
17690             op                         = "NPU_OP_PMU_MASK";
17691             v.disassemble(fields);
17692             break;
17693         }
17694         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17695             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP):
17696         {
17697             const npu_set_ifm_pad_top_t &v = *reinterpret_cast<const npu_set_ifm_pad_top_t *>(in);
17698             op                             = "NPU_SET_IFM_PAD_TOP";
17699             v.disassemble(fields);
17700             break;
17701         }
17702         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17703             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT):
17704         {
17705             const npu_set_ifm_pad_left_t &v = *reinterpret_cast<const npu_set_ifm_pad_left_t *>(in);
17706             op                              = "NPU_SET_IFM_PAD_LEFT";
17707             v.disassemble(fields);
17708             break;
17709         }
17710         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17711             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT):
17712         {
17713             const npu_set_ifm_pad_right_t &v = *reinterpret_cast<const npu_set_ifm_pad_right_t *>(in);
17714             op                               = "NPU_SET_IFM_PAD_RIGHT";
17715             v.disassemble(fields);
17716             break;
17717         }
17718         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17719             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM):
17720         {
17721             const npu_set_ifm_pad_bottom_t &v = *reinterpret_cast<const npu_set_ifm_pad_bottom_t *>(in);
17722             op                                = "NPU_SET_IFM_PAD_BOTTOM";
17723             v.disassemble(fields);
17724             break;
17725         }
17726         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17727             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1):
17728         {
17729             const npu_set_ifm_depth_m1_t &v = *reinterpret_cast<const npu_set_ifm_depth_m1_t *>(in);
17730             op                              = "NPU_SET_IFM_DEPTH_M1";
17731             v.disassemble(fields);
17732             break;
17733         }
17734         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17735             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION):
17736         {
17737             const npu_set_ifm_precision_t &v = *reinterpret_cast<const npu_set_ifm_precision_t *>(in);
17738             op                               = "NPU_SET_IFM_PRECISION";
17739             v.disassemble(fields);
17740             break;
17741         }
17742         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17743             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE):
17744         {
17745             const npu_set_ifm_upscale_t &v = *reinterpret_cast<const npu_set_ifm_upscale_t *>(in);
17746             op                             = "NPU_SET_IFM_UPSCALE";
17747             v.disassemble(fields);
17748             break;
17749         }
17750         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17751             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT):
17752         {
17753             const npu_set_ifm_zero_point_t &v = *reinterpret_cast<const npu_set_ifm_zero_point_t *>(in);
17754             op                                = "NPU_SET_IFM_ZERO_POINT";
17755             v.disassemble(fields);
17756             break;
17757         }
17758         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17759             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1):
17760         {
17761             const npu_set_ifm_width0_m1_t &v = *reinterpret_cast<const npu_set_ifm_width0_m1_t *>(in);
17762             op                               = "NPU_SET_IFM_WIDTH0_M1";
17763             v.disassemble(fields);
17764             break;
17765         }
17766         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17767             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1):
17768         {
17769             const npu_set_ifm_height0_m1_t &v = *reinterpret_cast<const npu_set_ifm_height0_m1_t *>(in);
17770             op                                = "NPU_SET_IFM_HEIGHT0_M1";
17771             v.disassemble(fields);
17772             break;
17773         }
17774         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17775             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1):
17776         {
17777             const npu_set_ifm_height1_m1_t &v = *reinterpret_cast<const npu_set_ifm_height1_m1_t *>(in);
17778             op                                = "NPU_SET_IFM_HEIGHT1_M1";
17779             v.disassemble(fields);
17780             break;
17781         }
17782         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17783             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END):
17784         {
17785             const npu_set_ifm_ib_end_t &v = *reinterpret_cast<const npu_set_ifm_ib_end_t *>(in);
17786             op                            = "NPU_SET_IFM_IB_END";
17787             v.disassemble(fields);
17788             break;
17789         }
17790         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17791             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION):
17792         {
17793             const npu_set_ifm_region_t &v = *reinterpret_cast<const npu_set_ifm_region_t *>(in);
17794             op                            = "NPU_SET_IFM_REGION";
17795             v.disassemble(fields);
17796             break;
17797         }
17798         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17799             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1):
17800         {
17801             const npu_set_ofm_width_m1_t &v = *reinterpret_cast<const npu_set_ofm_width_m1_t *>(in);
17802             op                              = "NPU_SET_OFM_WIDTH_M1";
17803             v.disassemble(fields);
17804             break;
17805         }
17806         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17807             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1):
17808         {
17809             const npu_set_ofm_height_m1_t &v = *reinterpret_cast<const npu_set_ofm_height_m1_t *>(in);
17810             op                               = "NPU_SET_OFM_HEIGHT_M1";
17811             v.disassemble(fields);
17812             break;
17813         }
17814         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17815             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1):
17816         {
17817             const npu_set_ofm_depth_m1_t &v = *reinterpret_cast<const npu_set_ofm_depth_m1_t *>(in);
17818             op                              = "NPU_SET_OFM_DEPTH_M1";
17819             v.disassemble(fields);
17820             break;
17821         }
17822         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17823             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION):
17824         {
17825             const npu_set_ofm_precision_t &v = *reinterpret_cast<const npu_set_ofm_precision_t *>(in);
17826             op                               = "NPU_SET_OFM_PRECISION";
17827             v.disassemble(fields);
17828             break;
17829         }
17830         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17831             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1):
17832         {
17833             const npu_set_ofm_blk_width_m1_t &v = *reinterpret_cast<const npu_set_ofm_blk_width_m1_t *>(in);
17834             op                                  = "NPU_SET_OFM_BLK_WIDTH_M1";
17835             v.disassemble(fields);
17836             break;
17837         }
17838         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17839             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1):
17840         {
17841             const npu_set_ofm_blk_height_m1_t &v = *reinterpret_cast<const npu_set_ofm_blk_height_m1_t *>(in);
17842             op                                   = "NPU_SET_OFM_BLK_HEIGHT_M1";
17843             v.disassemble(fields);
17844             break;
17845         }
17846         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17847             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1):
17848         {
17849             const npu_set_ofm_blk_depth_m1_t &v = *reinterpret_cast<const npu_set_ofm_blk_depth_m1_t *>(in);
17850             op                                  = "NPU_SET_OFM_BLK_DEPTH_M1";
17851             v.disassemble(fields);
17852             break;
17853         }
17854         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17855             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT):
17856         {
17857             const npu_set_ofm_zero_point_t &v = *reinterpret_cast<const npu_set_ofm_zero_point_t *>(in);
17858             op                                = "NPU_SET_OFM_ZERO_POINT";
17859             v.disassemble(fields);
17860             break;
17861         }
17862         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17863             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1):
17864         {
17865             const npu_set_ofm_width0_m1_t &v = *reinterpret_cast<const npu_set_ofm_width0_m1_t *>(in);
17866             op                               = "NPU_SET_OFM_WIDTH0_M1";
17867             v.disassemble(fields);
17868             break;
17869         }
17870         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17871             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1):
17872         {
17873             const npu_set_ofm_height0_m1_t &v = *reinterpret_cast<const npu_set_ofm_height0_m1_t *>(in);
17874             op                                = "NPU_SET_OFM_HEIGHT0_M1";
17875             v.disassemble(fields);
17876             break;
17877         }
17878         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17879             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1):
17880         {
17881             const npu_set_ofm_height1_m1_t &v = *reinterpret_cast<const npu_set_ofm_height1_m1_t *>(in);
17882             op                                = "NPU_SET_OFM_HEIGHT1_M1";
17883             v.disassemble(fields);
17884             break;
17885         }
17886         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17887             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION):
17888         {
17889             const npu_set_ofm_region_t &v = *reinterpret_cast<const npu_set_ofm_region_t *>(in);
17890             op                            = "NPU_SET_OFM_REGION";
17891             v.disassemble(fields);
17892             break;
17893         }
17894         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17895             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1):
17896         {
17897             const npu_set_kernel_width_m1_t &v = *reinterpret_cast<const npu_set_kernel_width_m1_t *>(in);
17898             op                                 = "NPU_SET_KERNEL_WIDTH_M1";
17899             v.disassemble(fields);
17900             break;
17901         }
17902         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17903             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1):
17904         {
17905             const npu_set_kernel_height_m1_t &v = *reinterpret_cast<const npu_set_kernel_height_m1_t *>(in);
17906             op                                  = "NPU_SET_KERNEL_HEIGHT_M1";
17907             v.disassemble(fields);
17908             break;
17909         }
17910         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17911             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE):
17912         {
17913             const npu_set_kernel_stride_t &v = *reinterpret_cast<const npu_set_kernel_stride_t *>(in);
17914             op                               = "NPU_SET_KERNEL_STRIDE";
17915             v.disassemble(fields);
17916             break;
17917         }
17918         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17919             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE):
17920         {
17921             const npu_set_parallel_mode_t &v = *reinterpret_cast<const npu_set_parallel_mode_t *>(in);
17922             op                               = "NPU_SET_PARALLEL_MODE";
17923             v.disassemble(fields);
17924             break;
17925         }
17926         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17927             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT):
17928         {
17929             const npu_set_acc_format_t &v = *reinterpret_cast<const npu_set_acc_format_t *>(in);
17930             op                            = "NPU_SET_ACC_FORMAT";
17931             v.disassemble(fields);
17932             break;
17933         }
17934         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17935             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION):
17936         {
17937             const npu_set_activation_t &v = *reinterpret_cast<const npu_set_activation_t *>(in);
17938             op                            = "NPU_SET_ACTIVATION";
17939             v.disassemble(fields);
17940             break;
17941         }
17942         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17943             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN):
17944         {
17945             const npu_set_activation_min_t &v = *reinterpret_cast<const npu_set_activation_min_t *>(in);
17946             op                                = "NPU_SET_ACTIVATION_MIN";
17947             v.disassemble(fields);
17948             break;
17949         }
17950         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17951             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX):
17952         {
17953             const npu_set_activation_max_t &v = *reinterpret_cast<const npu_set_activation_max_t *>(in);
17954             op                                = "NPU_SET_ACTIVATION_MAX";
17955             v.disassemble(fields);
17956             break;
17957         }
17958         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17959             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION):
17960         {
17961             const npu_set_weight_region_t &v = *reinterpret_cast<const npu_set_weight_region_t *>(in);
17962             op                               = "NPU_SET_WEIGHT_REGION";
17963             v.disassemble(fields);
17964             break;
17965         }
17966         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17967             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION):
17968         {
17969             const npu_set_scale_region_t &v = *reinterpret_cast<const npu_set_scale_region_t *>(in);
17970             op                              = "NPU_SET_SCALE_REGION";
17971             v.disassemble(fields);
17972             break;
17973         }
17974         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17975             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START):
17976         {
17977             const npu_set_ab_start_t &v = *reinterpret_cast<const npu_set_ab_start_t *>(in);
17978             op                          = "NPU_SET_AB_START";
17979             v.disassemble(fields);
17980             break;
17981         }
17982         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17983             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP):
17984         {
17985             const npu_set_blockdep_t &v = *reinterpret_cast<const npu_set_blockdep_t *>(in);
17986             op                          = "NPU_SET_BLOCKDEP";
17987             v.disassemble(fields);
17988             break;
17989         }
17990         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17991             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION):
17992         {
17993             const npu_set_dma0_src_region_t &v = *reinterpret_cast<const npu_set_dma0_src_region_t *>(in);
17994             op                                 = "NPU_SET_DMA0_SRC_REGION";
17995             v.disassemble(fields);
17996             break;
17997         }
17998         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17999             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION):
18000         {
18001             const npu_set_dma0_dst_region_t &v = *reinterpret_cast<const npu_set_dma0_dst_region_t *>(in);
18002             op                                 = "NPU_SET_DMA0_DST_REGION";
18003             v.disassemble(fields);
18004             break;
18005         }
18006         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18007             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0):
18008         {
18009             const npu_set_dma0_size0_t &v = *reinterpret_cast<const npu_set_dma0_size0_t *>(in);
18010             op                            = "NPU_SET_DMA0_SIZE0";
18011             v.disassemble(fields);
18012             break;
18013         }
18014         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18015             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1):
18016         {
18017             const npu_set_dma0_size1_t &v = *reinterpret_cast<const npu_set_dma0_size1_t *>(in);
18018             op                            = "NPU_SET_DMA0_SIZE1";
18019             v.disassemble(fields);
18020             break;
18021         }
18022         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18023             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST):
18024         {
18025             const npu_set_ifm2_broadcast_t &v = *reinterpret_cast<const npu_set_ifm2_broadcast_t *>(in);
18026             op                                = "NPU_SET_IFM2_BROADCAST";
18027             v.disassemble(fields);
18028             break;
18029         }
18030         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18031             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR):
18032         {
18033             const npu_set_ifm2_scalar_t &v = *reinterpret_cast<const npu_set_ifm2_scalar_t *>(in);
18034             op                             = "NPU_SET_IFM2_SCALAR";
18035             v.disassemble(fields);
18036             break;
18037         }
18038         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18039             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION):
18040         {
18041             const npu_set_ifm2_precision_t &v = *reinterpret_cast<const npu_set_ifm2_precision_t *>(in);
18042             op                                = "NPU_SET_IFM2_PRECISION";
18043             v.disassemble(fields);
18044             break;
18045         }
18046         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18047             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT):
18048         {
18049             const npu_set_ifm2_zero_point_t &v = *reinterpret_cast<const npu_set_ifm2_zero_point_t *>(in);
18050             op                                 = "NPU_SET_IFM2_ZERO_POINT";
18051             v.disassemble(fields);
18052             break;
18053         }
18054         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18055             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1):
18056         {
18057             const npu_set_ifm2_width0_m1_t &v = *reinterpret_cast<const npu_set_ifm2_width0_m1_t *>(in);
18058             op                                = "NPU_SET_IFM2_WIDTH0_M1";
18059             v.disassemble(fields);
18060             break;
18061         }
18062         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18063             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1):
18064         {
18065             const npu_set_ifm2_height0_m1_t &v = *reinterpret_cast<const npu_set_ifm2_height0_m1_t *>(in);
18066             op                                 = "NPU_SET_IFM2_HEIGHT0_M1";
18067             v.disassemble(fields);
18068             break;
18069         }
18070         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18071             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1):
18072         {
18073             const npu_set_ifm2_height1_m1_t &v = *reinterpret_cast<const npu_set_ifm2_height1_m1_t *>(in);
18074             op                                 = "NPU_SET_IFM2_HEIGHT1_M1";
18075             v.disassemble(fields);
18076             break;
18077         }
18078         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18079             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START):
18080         {
18081             const npu_set_ifm2_ib_start_t &v = *reinterpret_cast<const npu_set_ifm2_ib_start_t *>(in);
18082             op                               = "NPU_SET_IFM2_IB_START";
18083             v.disassemble(fields);
18084             break;
18085         }
18086         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18087             static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION):
18088         {
18089             const npu_set_ifm2_region_t &v = *reinterpret_cast<const npu_set_ifm2_region_t *>(in);
18090             op                             = "NPU_SET_IFM2_REGION";
18091             v.disassemble(fields);
18092             break;
18093         }
18094         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18095             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0):
18096         {
18097             const npu_set_ifm_base0_t &v = *reinterpret_cast<const npu_set_ifm_base0_t *>(in);
18098             op                           = "NPU_SET_IFM_BASE0";
18099             v.disassemble(fields);
18100             break;
18101         }
18102         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18103             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1):
18104         {
18105             const npu_set_ifm_base1_t &v = *reinterpret_cast<const npu_set_ifm_base1_t *>(in);
18106             op                           = "NPU_SET_IFM_BASE1";
18107             v.disassemble(fields);
18108             break;
18109         }
18110         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18111             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2):
18112         {
18113             const npu_set_ifm_base2_t &v = *reinterpret_cast<const npu_set_ifm_base2_t *>(in);
18114             op                           = "NPU_SET_IFM_BASE2";
18115             v.disassemble(fields);
18116             break;
18117         }
18118         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18119             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3):
18120         {
18121             const npu_set_ifm_base3_t &v = *reinterpret_cast<const npu_set_ifm_base3_t *>(in);
18122             op                           = "NPU_SET_IFM_BASE3";
18123             v.disassemble(fields);
18124             break;
18125         }
18126         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18127             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X):
18128         {
18129             const npu_set_ifm_stride_x_t &v = *reinterpret_cast<const npu_set_ifm_stride_x_t *>(in);
18130             op                              = "NPU_SET_IFM_STRIDE_X";
18131             v.disassemble(fields);
18132             break;
18133         }
18134         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18135             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y):
18136         {
18137             const npu_set_ifm_stride_y_t &v = *reinterpret_cast<const npu_set_ifm_stride_y_t *>(in);
18138             op                              = "NPU_SET_IFM_STRIDE_Y";
18139             v.disassemble(fields);
18140             break;
18141         }
18142         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18143             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C):
18144         {
18145             const npu_set_ifm_stride_c_t &v = *reinterpret_cast<const npu_set_ifm_stride_c_t *>(in);
18146             op                              = "NPU_SET_IFM_STRIDE_C";
18147             v.disassemble(fields);
18148             break;
18149         }
18150         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18151             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0):
18152         {
18153             const npu_set_ofm_base0_t &v = *reinterpret_cast<const npu_set_ofm_base0_t *>(in);
18154             op                           = "NPU_SET_OFM_BASE0";
18155             v.disassemble(fields);
18156             break;
18157         }
18158         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18159             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1):
18160         {
18161             const npu_set_ofm_base1_t &v = *reinterpret_cast<const npu_set_ofm_base1_t *>(in);
18162             op                           = "NPU_SET_OFM_BASE1";
18163             v.disassemble(fields);
18164             break;
18165         }
18166         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18167             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2):
18168         {
18169             const npu_set_ofm_base2_t &v = *reinterpret_cast<const npu_set_ofm_base2_t *>(in);
18170             op                           = "NPU_SET_OFM_BASE2";
18171             v.disassemble(fields);
18172             break;
18173         }
18174         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18175             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3):
18176         {
18177             const npu_set_ofm_base3_t &v = *reinterpret_cast<const npu_set_ofm_base3_t *>(in);
18178             op                           = "NPU_SET_OFM_BASE3";
18179             v.disassemble(fields);
18180             break;
18181         }
18182         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18183             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X):
18184         {
18185             const npu_set_ofm_stride_x_t &v = *reinterpret_cast<const npu_set_ofm_stride_x_t *>(in);
18186             op                              = "NPU_SET_OFM_STRIDE_X";
18187             v.disassemble(fields);
18188             break;
18189         }
18190         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18191             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y):
18192         {
18193             const npu_set_ofm_stride_y_t &v = *reinterpret_cast<const npu_set_ofm_stride_y_t *>(in);
18194             op                              = "NPU_SET_OFM_STRIDE_Y";
18195             v.disassemble(fields);
18196             break;
18197         }
18198         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18199             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C):
18200         {
18201             const npu_set_ofm_stride_c_t &v = *reinterpret_cast<const npu_set_ofm_stride_c_t *>(in);
18202             op                              = "NPU_SET_OFM_STRIDE_C";
18203             v.disassemble(fields);
18204             break;
18205         }
18206         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18207             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE):
18208         {
18209             const npu_set_weight_base_t &v = *reinterpret_cast<const npu_set_weight_base_t *>(in);
18210             op                             = "NPU_SET_WEIGHT_BASE";
18211             v.disassemble(fields);
18212             break;
18213         }
18214         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18215             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH):
18216         {
18217             const npu_set_weight_length_t &v = *reinterpret_cast<const npu_set_weight_length_t *>(in);
18218             op                               = "NPU_SET_WEIGHT_LENGTH";
18219             v.disassemble(fields);
18220             break;
18221         }
18222         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18223             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE):
18224         {
18225             const npu_set_scale_base_t &v = *reinterpret_cast<const npu_set_scale_base_t *>(in);
18226             op                            = "NPU_SET_SCALE_BASE";
18227             v.disassemble(fields);
18228             break;
18229         }
18230         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18231             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH):
18232         {
18233             const npu_set_scale_length_t &v = *reinterpret_cast<const npu_set_scale_length_t *>(in);
18234             op                              = "NPU_SET_SCALE_LENGTH";
18235             v.disassemble(fields);
18236             break;
18237         }
18238         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18239             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE):
18240         {
18241             const npu_set_ofm_scale_t &v = *reinterpret_cast<const npu_set_ofm_scale_t *>(in);
18242             op                           = "NPU_SET_OFM_SCALE";
18243             v.disassemble(fields);
18244             break;
18245         }
18246         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18247             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE):
18248         {
18249             const npu_set_opa_scale_t &v = *reinterpret_cast<const npu_set_opa_scale_t *>(in);
18250             op                           = "NPU_SET_OPA_SCALE";
18251             v.disassemble(fields);
18252             break;
18253         }
18254         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18255             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE):
18256         {
18257             const npu_set_opb_scale_t &v = *reinterpret_cast<const npu_set_opb_scale_t *>(in);
18258             op                           = "NPU_SET_OPB_SCALE";
18259             v.disassemble(fields);
18260             break;
18261         }
18262         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18263             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC):
18264         {
18265             const npu_set_dma0_src_t &v = *reinterpret_cast<const npu_set_dma0_src_t *>(in);
18266             op                          = "NPU_SET_DMA0_SRC";
18267             v.disassemble(fields);
18268             break;
18269         }
18270         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18271             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST):
18272         {
18273             const npu_set_dma0_dst_t &v = *reinterpret_cast<const npu_set_dma0_dst_t *>(in);
18274             op                          = "NPU_SET_DMA0_DST";
18275             v.disassemble(fields);
18276             break;
18277         }
18278         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18279             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN):
18280         {
18281             const npu_set_dma0_len_t &v = *reinterpret_cast<const npu_set_dma0_len_t *>(in);
18282             op                          = "NPU_SET_DMA0_LEN";
18283             v.disassemble(fields);
18284             break;
18285         }
18286         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18287             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0):
18288         {
18289             const npu_set_dma0_skip0_t &v = *reinterpret_cast<const npu_set_dma0_skip0_t *>(in);
18290             op                            = "NPU_SET_DMA0_SKIP0";
18291             v.disassemble(fields);
18292             break;
18293         }
18294         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18295             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1):
18296         {
18297             const npu_set_dma0_skip1_t &v = *reinterpret_cast<const npu_set_dma0_skip1_t *>(in);
18298             op                            = "NPU_SET_DMA0_SKIP1";
18299             v.disassemble(fields);
18300             break;
18301         }
18302         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18303             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0):
18304         {
18305             const npu_set_ifm2_base0_t &v = *reinterpret_cast<const npu_set_ifm2_base0_t *>(in);
18306             op                            = "NPU_SET_IFM2_BASE0";
18307             v.disassemble(fields);
18308             break;
18309         }
18310         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18311             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1):
18312         {
18313             const npu_set_ifm2_base1_t &v = *reinterpret_cast<const npu_set_ifm2_base1_t *>(in);
18314             op                            = "NPU_SET_IFM2_BASE1";
18315             v.disassemble(fields);
18316             break;
18317         }
18318         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18319             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2):
18320         {
18321             const npu_set_ifm2_base2_t &v = *reinterpret_cast<const npu_set_ifm2_base2_t *>(in);
18322             op                            = "NPU_SET_IFM2_BASE2";
18323             v.disassemble(fields);
18324             break;
18325         }
18326         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18327             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3):
18328         {
18329             const npu_set_ifm2_base3_t &v = *reinterpret_cast<const npu_set_ifm2_base3_t *>(in);
18330             op                            = "NPU_SET_IFM2_BASE3";
18331             v.disassemble(fields);
18332             break;
18333         }
18334         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18335             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X):
18336         {
18337             const npu_set_ifm2_stride_x_t &v = *reinterpret_cast<const npu_set_ifm2_stride_x_t *>(in);
18338             op                               = "NPU_SET_IFM2_STRIDE_X";
18339             v.disassemble(fields);
18340             break;
18341         }
18342         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18343             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y):
18344         {
18345             const npu_set_ifm2_stride_y_t &v = *reinterpret_cast<const npu_set_ifm2_stride_y_t *>(in);
18346             op                               = "NPU_SET_IFM2_STRIDE_Y";
18347             v.disassemble(fields);
18348             break;
18349         }
18350         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18351             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C):
18352         {
18353             const npu_set_ifm2_stride_c_t &v = *reinterpret_cast<const npu_set_ifm2_stride_c_t *>(in);
18354             op                               = "NPU_SET_IFM2_STRIDE_C";
18355             v.disassemble(fields);
18356             break;
18357         }
18358         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18359             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE):
18360         {
18361             const npu_set_weight1_base_t &v = *reinterpret_cast<const npu_set_weight1_base_t *>(in);
18362             op                              = "NPU_SET_WEIGHT1_BASE";
18363             v.disassemble(fields);
18364             break;
18365         }
18366         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18367             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH):
18368         {
18369             const npu_set_weight1_length_t &v = *reinterpret_cast<const npu_set_weight1_length_t *>(in);
18370             op                                = "NPU_SET_WEIGHT1_LENGTH";
18371             v.disassemble(fields);
18372             break;
18373         }
18374         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18375             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE):
18376         {
18377             const npu_set_scale1_base_t &v = *reinterpret_cast<const npu_set_scale1_base_t *>(in);
18378             op                             = "NPU_SET_SCALE1_BASE";
18379             v.disassemble(fields);
18380             break;
18381         }
18382         case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18383             static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH):
18384         {
18385             const npu_set_scale1_length_t &v = *reinterpret_cast<const npu_set_scale1_length_t *>(in);
18386             op                               = "NPU_SET_SCALE1_LENGTH";
18387             v.disassemble(fields);
18388             break;
18389         }
18390         }
18391         return (*in & (3 << 14)) != 0 ? 2 : 1;
18392     }
18393 #endif
18394 #endif
18395     // Signal the end of command stream
18396     struct npu_op_stop_t
18397     {
18398 #ifdef __cplusplus
18399       private:
18400 #endif
18401         uint32_t opcode : 10; //  opcode
18402         uint32_t reserved0 : 4;
18403         uint32_t control : 2; //  control
18404         uint32_t mask : 16;   //  Encoding for 16-bit mask value
18405 #ifdef __cplusplus
18406       public:
npu_op_stop_tisa::npu_op_stop_t18407         npu_op_stop_t(uint32_t _mask) :
18408             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP)), reserved0(0),
18409             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(_mask & ((1U << 16) - 1))
18410         {
18411         }
npu_op_stop_tisa::npu_op_stop_t18412         CONSTEXPR npu_op_stop_t() :
18413             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP)), reserved0(0),
18414             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(0)
18415         {
18416         }
validisa::npu_op_stop_t18417         CONSTEXPR bool valid() const
18418         {
18419             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP) &&
18420                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18421         }
initisa::npu_op_stop_t18422         CONSTEXPR void init()
18423         {
18424             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP);
18425             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18426         }
uint32_tisa::npu_op_stop_t18427         operator uint32_t()
18428         {
18429             uint32_t word;
18430             std::memcpy(&word, this, sizeof(word));
18431             return word;
18432         }
get_opcodeisa::npu_op_stop_t18433         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18434         {
18435             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18436         }
set_opcodeisa::npu_op_stop_t18437         CONSTEXPR npu_op_stop_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18438         {
18439             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18440             return *this;
18441         }
get_controlisa::npu_op_stop_t18442         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18443         {
18444             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18445         }
set_controlisa::npu_op_stop_t18446         CONSTEXPR npu_op_stop_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18447         {
18448             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18449             return *this;
18450         }
get_maskisa::npu_op_stop_t18451         CONSTEXPR uint32_t get_mask() const
18452         {
18453             return static_cast<uint32_t>(mask);
18454         }
set_maskisa::npu_op_stop_t18455         CONSTEXPR npu_op_stop_t &set_mask(uint32_t value)
18456         {
18457             mask = static_cast<uint16_t>(value) & ((1U << 16) - 1);
18458             return *this;
18459         }
18460 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_op_stop_t18461         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
18462         {
18463             fields.push_back(std::make_pair<std::string, std::string>("mask", std::to_string(mask)));
18464         }
18465 #endif
18466 #endif
18467     };
18468     // Raises an IRQ to the host
18469     struct npu_op_irq_t
18470     {
18471 #ifdef __cplusplus
18472       private:
18473 #endif
18474         uint32_t opcode : 10; //  opcode
18475         uint32_t reserved0 : 4;
18476         uint32_t control : 2; //  control
18477         uint32_t mask : 16;   //  Encoding for 16-bit mask value
18478 #ifdef __cplusplus
18479       public:
npu_op_irq_tisa::npu_op_irq_t18480         npu_op_irq_t(uint32_t _mask) :
18481             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ)), reserved0(0),
18482             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(_mask & ((1U << 16) - 1))
18483         {
18484         }
npu_op_irq_tisa::npu_op_irq_t18485         CONSTEXPR npu_op_irq_t() :
18486             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ)), reserved0(0),
18487             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(0)
18488         {
18489         }
validisa::npu_op_irq_t18490         CONSTEXPR bool valid() const
18491         {
18492             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ) &&
18493                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18494         }
initisa::npu_op_irq_t18495         CONSTEXPR void init()
18496         {
18497             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ);
18498             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18499         }
uint32_tisa::npu_op_irq_t18500         operator uint32_t()
18501         {
18502             uint32_t word;
18503             std::memcpy(&word, this, sizeof(word));
18504             return word;
18505         }
get_opcodeisa::npu_op_irq_t18506         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18507         {
18508             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18509         }
set_opcodeisa::npu_op_irq_t18510         CONSTEXPR npu_op_irq_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18511         {
18512             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18513             return *this;
18514         }
get_controlisa::npu_op_irq_t18515         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18516         {
18517             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18518         }
set_controlisa::npu_op_irq_t18519         CONSTEXPR npu_op_irq_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18520         {
18521             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18522             return *this;
18523         }
get_maskisa::npu_op_irq_t18524         CONSTEXPR uint32_t get_mask() const
18525         {
18526             return static_cast<uint32_t>(mask);
18527         }
set_maskisa::npu_op_irq_t18528         CONSTEXPR npu_op_irq_t &set_mask(uint32_t value)
18529         {
18530             mask = static_cast<uint16_t>(value) & ((1U << 16) - 1);
18531             return *this;
18532         }
18533 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_op_irq_t18534         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
18535         {
18536             fields.push_back(std::make_pair<std::string, std::string>("mask", std::to_string(mask)));
18537         }
18538 #endif
18539 #endif
18540     };
18541     // 2D convolution
18542     struct npu_op_conv_t
18543     {
18544 #ifdef __cplusplus
18545       private:
18546 #endif
18547         uint32_t opcode : 10; //  opcode
18548         uint32_t reserved0 : 4;
18549         uint32_t control : 2; //  control
18550         uint32_t reserved1 : 16;
18551 #ifdef __cplusplus
18552       public:
npu_op_conv_tisa::npu_op_conv_t18553         CONSTEXPR npu_op_conv_t() :
18554             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV)), reserved0(0),
18555             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0)
18556         {
18557         }
validisa::npu_op_conv_t18558         CONSTEXPR bool valid() const
18559         {
18560             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV) &&
18561                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18562         }
initisa::npu_op_conv_t18563         CONSTEXPR void init()
18564         {
18565             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV);
18566             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18567         }
uint32_tisa::npu_op_conv_t18568         operator uint32_t()
18569         {
18570             uint32_t word;
18571             std::memcpy(&word, this, sizeof(word));
18572             return word;
18573         }
get_opcodeisa::npu_op_conv_t18574         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18575         {
18576             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18577         }
set_opcodeisa::npu_op_conv_t18578         CONSTEXPR npu_op_conv_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18579         {
18580             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18581             return *this;
18582         }
get_controlisa::npu_op_conv_t18583         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18584         {
18585             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18586         }
set_controlisa::npu_op_conv_t18587         CONSTEXPR npu_op_conv_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18588         {
18589             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18590             return *this;
18591         }
18592 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_op_conv_t18593         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const {}
18594 #endif
18595 #endif
18596     };
18597     // Depth-wise 2D convolution
18598     struct npu_op_depthwise_t
18599     {
18600 #ifdef __cplusplus
18601       private:
18602 #endif
18603         uint32_t opcode : 10; //  opcode
18604         uint32_t reserved0 : 4;
18605         uint32_t control : 2; //  control
18606         uint32_t reserved1 : 16;
18607 #ifdef __cplusplus
18608       public:
npu_op_depthwise_tisa::npu_op_depthwise_t18609         CONSTEXPR npu_op_depthwise_t() :
18610             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE)), reserved0(0),
18611             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0)
18612         {
18613         }
validisa::npu_op_depthwise_t18614         CONSTEXPR bool valid() const
18615         {
18616             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE) &&
18617                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18618         }
initisa::npu_op_depthwise_t18619         CONSTEXPR void init()
18620         {
18621             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE);
18622             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18623         }
uint32_tisa::npu_op_depthwise_t18624         operator uint32_t()
18625         {
18626             uint32_t word;
18627             std::memcpy(&word, this, sizeof(word));
18628             return word;
18629         }
get_opcodeisa::npu_op_depthwise_t18630         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18631         {
18632             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18633         }
set_opcodeisa::npu_op_depthwise_t18634         CONSTEXPR npu_op_depthwise_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18635         {
18636             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18637             return *this;
18638         }
get_controlisa::npu_op_depthwise_t18639         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18640         {
18641             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18642         }
set_controlisa::npu_op_depthwise_t18643         CONSTEXPR npu_op_depthwise_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18644         {
18645             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18646             return *this;
18647         }
18648 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_op_depthwise_t18649         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const {}
18650 #endif
18651 #endif
18652     };
18653     // Pooling
18654     struct npu_op_pool_t
18655     {
18656 #ifdef __cplusplus
18657       private:
18658 #endif
18659         uint32_t opcode : 10; //  opcode
18660         uint32_t reserved0 : 4;
18661         uint32_t control : 2;      //  control
18662         uint32_t pooling_mode : 3; //  Pooling mode
18663         uint32_t reserved1 : 13;
18664 #ifdef __cplusplus
18665       public:
npu_op_pool_tisa::npu_op_pool_t18666         npu_op_pool_t(NPU_NAMESPACE::pooling_mode _pooling_mode) :
18667             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL)), reserved0(0),
18668             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
18669             pooling_mode(static_cast<uint8_t>(_pooling_mode) & ((1U << 3) - 1)), reserved1(0)
18670         {
18671         }
npu_op_pool_tisa::npu_op_pool_t18672         CONSTEXPR npu_op_pool_t() :
18673             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL)), reserved0(0),
18674             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pooling_mode(0), reserved1(0)
18675         {
18676         }
validisa::npu_op_pool_t18677         CONSTEXPR bool valid() const
18678         {
18679             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL) &&
18680                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18681         }
initisa::npu_op_pool_t18682         CONSTEXPR void init()
18683         {
18684             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL);
18685             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18686         }
uint32_tisa::npu_op_pool_t18687         operator uint32_t()
18688         {
18689             uint32_t word;
18690             std::memcpy(&word, this, sizeof(word));
18691             return word;
18692         }
get_opcodeisa::npu_op_pool_t18693         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18694         {
18695             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18696         }
set_opcodeisa::npu_op_pool_t18697         CONSTEXPR npu_op_pool_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18698         {
18699             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18700             return *this;
18701         }
get_controlisa::npu_op_pool_t18702         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18703         {
18704             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18705         }
set_controlisa::npu_op_pool_t18706         CONSTEXPR npu_op_pool_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18707         {
18708             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18709             return *this;
18710         }
get_pooling_modeisa::npu_op_pool_t18711         CONSTEXPR NPU_NAMESPACE::pooling_mode get_pooling_mode() const
18712         {
18713             return static_cast<NPU_NAMESPACE::pooling_mode>(pooling_mode);
18714         }
set_pooling_modeisa::npu_op_pool_t18715         CONSTEXPR npu_op_pool_t &set_pooling_mode(NPU_NAMESPACE::pooling_mode value)
18716         {
18717             pooling_mode = static_cast<uint8_t>(value) & ((1U << 3) - 1);
18718             return *this;
18719         }
18720 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_op_pool_t18721         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
18722         {
18723             fields.push_back(std::make_pair<std::string, std::string>(
18724                 "pooling_mode",
18725                 (pooling_mode < (sizeof(pooling_mode_str) / sizeof(pooling_mode_str[0])) ?
18726                      pooling_mode_str[pooling_mode] :
18727                      "****")));
18728         }
18729 #endif
18730 #endif
18731     };
18732     // Elementwise operation
18733     struct npu_op_elementwise_t
18734     {
18735 #ifdef __cplusplus
18736       private:
18737 #endif
18738         uint32_t opcode : 10; //  opcode
18739         uint32_t reserved0 : 4;
18740         uint32_t control : 2;          //  control
18741         uint32_t elementwise_mode : 6; //  Elementwise mode
18742         uint32_t reserved1 : 10;
18743 #ifdef __cplusplus
18744       public:
npu_op_elementwise_tisa::npu_op_elementwise_t18745         npu_op_elementwise_t(NPU_NAMESPACE::elementwise_mode _elementwise_mode) :
18746             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE)), reserved0(0),
18747             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
18748             elementwise_mode(static_cast<uint8_t>(_elementwise_mode) & ((1U << 6) - 1)), reserved1(0)
18749         {
18750         }
npu_op_elementwise_tisa::npu_op_elementwise_t18751         CONSTEXPR npu_op_elementwise_t() :
18752             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE)), reserved0(0),
18753             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), elementwise_mode(0), reserved1(0)
18754         {
18755         }
validisa::npu_op_elementwise_t18756         CONSTEXPR bool valid() const
18757         {
18758             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE) &&
18759                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18760         }
initisa::npu_op_elementwise_t18761         CONSTEXPR void init()
18762         {
18763             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE);
18764             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18765         }
uint32_tisa::npu_op_elementwise_t18766         operator uint32_t()
18767         {
18768             uint32_t word;
18769             std::memcpy(&word, this, sizeof(word));
18770             return word;
18771         }
get_opcodeisa::npu_op_elementwise_t18772         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18773         {
18774             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18775         }
set_opcodeisa::npu_op_elementwise_t18776         CONSTEXPR npu_op_elementwise_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18777         {
18778             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18779             return *this;
18780         }
get_controlisa::npu_op_elementwise_t18781         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18782         {
18783             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18784         }
set_controlisa::npu_op_elementwise_t18785         CONSTEXPR npu_op_elementwise_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18786         {
18787             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18788             return *this;
18789         }
get_elementwise_modeisa::npu_op_elementwise_t18790         CONSTEXPR NPU_NAMESPACE::elementwise_mode get_elementwise_mode() const
18791         {
18792             return static_cast<NPU_NAMESPACE::elementwise_mode>(elementwise_mode);
18793         }
set_elementwise_modeisa::npu_op_elementwise_t18794         CONSTEXPR npu_op_elementwise_t &set_elementwise_mode(NPU_NAMESPACE::elementwise_mode value)
18795         {
18796             elementwise_mode = static_cast<uint8_t>(value) & ((1U << 6) - 1);
18797             return *this;
18798         }
18799 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_op_elementwise_t18800         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
18801         {
18802             fields.push_back(std::make_pair<std::string, std::string>(
18803                 "elementwise_mode",
18804                 (elementwise_mode < (sizeof(elementwise_mode_str) / sizeof(elementwise_mode_str[0])) ?
18805                      elementwise_mode_str[elementwise_mode] :
18806                      "****")));
18807         }
18808 #endif
18809 #endif
18810     };
18811     // Queue new DMA for the given channel
18812     struct npu_op_dma_start_t
18813     {
18814 #ifdef __cplusplus
18815       private:
18816 #endif
18817         uint32_t opcode : 10; //  opcode
18818         uint32_t reserved0 : 4;
18819         uint32_t control : 2; //  control
18820         uint32_t reserved1 : 16;
18821 #ifdef __cplusplus
18822       public:
npu_op_dma_start_tisa::npu_op_dma_start_t18823         CONSTEXPR npu_op_dma_start_t() :
18824             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START)), reserved0(0),
18825             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0)
18826         {
18827         }
validisa::npu_op_dma_start_t18828         CONSTEXPR bool valid() const
18829         {
18830             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START) &&
18831                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18832         }
initisa::npu_op_dma_start_t18833         CONSTEXPR void init()
18834         {
18835             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START);
18836             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18837         }
uint32_tisa::npu_op_dma_start_t18838         operator uint32_t()
18839         {
18840             uint32_t word;
18841             std::memcpy(&word, this, sizeof(word));
18842             return word;
18843         }
get_opcodeisa::npu_op_dma_start_t18844         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18845         {
18846             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18847         }
set_opcodeisa::npu_op_dma_start_t18848         CONSTEXPR npu_op_dma_start_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18849         {
18850             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18851             return *this;
18852         }
get_controlisa::npu_op_dma_start_t18853         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18854         {
18855             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18856         }
set_controlisa::npu_op_dma_start_t18857         CONSTEXPR npu_op_dma_start_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18858         {
18859             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18860             return *this;
18861         }
18862 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_op_dma_start_t18863         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const {}
18864 #endif
18865 #endif
18866     };
18867     // Wait for the DMA channel to have k or fewer active descriptors outstanding
18868     struct npu_op_dma_wait_t
18869     {
18870 #ifdef __cplusplus
18871       private:
18872 #endif
18873         uint32_t opcode : 10; //  opcode
18874         uint32_t reserved0 : 4;
18875         uint32_t control : 2; //  control
18876         uint32_t k : 4;       //  Number of outstanding descriptors
18877         uint32_t reserved1 : 12;
18878 #ifdef __cplusplus
18879       public:
npu_op_dma_wait_tisa::npu_op_dma_wait_t18880         npu_op_dma_wait_t(uint32_t _k) :
18881             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT)), reserved0(0),
18882             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), k(_k & ((1U << 4) - 1)), reserved1(0)
18883         {
18884         }
npu_op_dma_wait_tisa::npu_op_dma_wait_t18885         CONSTEXPR npu_op_dma_wait_t() :
18886             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT)), reserved0(0),
18887             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), k(0), reserved1(0)
18888         {
18889         }
validisa::npu_op_dma_wait_t18890         CONSTEXPR bool valid() const
18891         {
18892             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT) &&
18893                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18894         }
initisa::npu_op_dma_wait_t18895         CONSTEXPR void init()
18896         {
18897             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT);
18898             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18899         }
uint32_tisa::npu_op_dma_wait_t18900         operator uint32_t()
18901         {
18902             uint32_t word;
18903             std::memcpy(&word, this, sizeof(word));
18904             return word;
18905         }
get_opcodeisa::npu_op_dma_wait_t18906         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18907         {
18908             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18909         }
set_opcodeisa::npu_op_dma_wait_t18910         CONSTEXPR npu_op_dma_wait_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18911         {
18912             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18913             return *this;
18914         }
get_controlisa::npu_op_dma_wait_t18915         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18916         {
18917             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18918         }
set_controlisa::npu_op_dma_wait_t18919         CONSTEXPR npu_op_dma_wait_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18920         {
18921             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18922             return *this;
18923         }
get_kisa::npu_op_dma_wait_t18924         CONSTEXPR uint32_t get_k() const
18925         {
18926             return static_cast<uint32_t>(k);
18927         }
set_kisa::npu_op_dma_wait_t18928         CONSTEXPR npu_op_dma_wait_t &set_k(uint32_t value)
18929         {
18930             k = static_cast<uint8_t>(value) & ((1U << 4) - 1);
18931             return *this;
18932         }
18933 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_op_dma_wait_t18934         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
18935         {
18936             fields.push_back(std::make_pair<std::string, std::string>("k", std::to_string(k)));
18937         }
18938 #endif
18939 #endif
18940     };
18941     // Wait for n or fewer kernel operations to be remaining
18942     struct npu_op_kernel_wait_t
18943     {
18944 #ifdef __cplusplus
18945       private:
18946 #endif
18947         uint32_t opcode : 10; //  opcode
18948         uint32_t reserved0 : 4;
18949         uint32_t control : 2; //  control
18950         uint32_t n : 2;       //  Number of kernel operations in range 0-3
18951         uint32_t reserved1 : 14;
18952 #ifdef __cplusplus
18953       public:
npu_op_kernel_wait_tisa::npu_op_kernel_wait_t18954         npu_op_kernel_wait_t(uint32_t _n) :
18955             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT)), reserved0(0),
18956             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), n(_n & ((1U << 2) - 1)), reserved1(0)
18957         {
18958         }
npu_op_kernel_wait_tisa::npu_op_kernel_wait_t18959         CONSTEXPR npu_op_kernel_wait_t() :
18960             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT)), reserved0(0),
18961             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), n(0), reserved1(0)
18962         {
18963         }
validisa::npu_op_kernel_wait_t18964         CONSTEXPR bool valid() const
18965         {
18966             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT) &&
18967                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18968         }
initisa::npu_op_kernel_wait_t18969         CONSTEXPR void init()
18970         {
18971             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT);
18972             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18973         }
uint32_tisa::npu_op_kernel_wait_t18974         operator uint32_t()
18975         {
18976             uint32_t word;
18977             std::memcpy(&word, this, sizeof(word));
18978             return word;
18979         }
get_opcodeisa::npu_op_kernel_wait_t18980         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18981         {
18982             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18983         }
set_opcodeisa::npu_op_kernel_wait_t18984         CONSTEXPR npu_op_kernel_wait_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18985         {
18986             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18987             return *this;
18988         }
get_controlisa::npu_op_kernel_wait_t18989         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18990         {
18991             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18992         }
set_controlisa::npu_op_kernel_wait_t18993         CONSTEXPR npu_op_kernel_wait_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18994         {
18995             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18996             return *this;
18997         }
get_nisa::npu_op_kernel_wait_t18998         CONSTEXPR uint32_t get_n() const
18999         {
19000             return static_cast<uint32_t>(n);
19001         }
set_nisa::npu_op_kernel_wait_t19002         CONSTEXPR npu_op_kernel_wait_t &set_n(uint32_t value)
19003         {
19004             n = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19005             return *this;
19006         }
19007 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_op_kernel_wait_t19008         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19009         {
19010             fields.push_back(std::make_pair<std::string, std::string>("n", std::to_string(n)));
19011         }
19012 #endif
19013 #endif
19014     };
19015     // Enable or disable PMU counting (debug feature only)
19016     struct npu_op_pmu_mask_t
19017     {
19018 #ifdef __cplusplus
19019       private:
19020 #endif
19021         uint32_t opcode : 10; //  opcode
19022         uint32_t reserved0 : 4;
19023         uint32_t control : 2; //  control
19024         uint32_t enable : 1;  //  Enable or disable PMU mask
19025         uint32_t reserved1 : 15;
19026 #ifdef __cplusplus
19027       public:
npu_op_pmu_mask_tisa::npu_op_pmu_mask_t19028         npu_op_pmu_mask_t(uint32_t _enable) :
19029             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK)), reserved0(0),
19030             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), enable(_enable & ((1U << 1) - 1)),
19031             reserved1(0)
19032         {
19033         }
npu_op_pmu_mask_tisa::npu_op_pmu_mask_t19034         CONSTEXPR npu_op_pmu_mask_t() :
19035             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK)), reserved0(0),
19036             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), enable(0), reserved1(0)
19037         {
19038         }
validisa::npu_op_pmu_mask_t19039         CONSTEXPR bool valid() const
19040         {
19041             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK) &&
19042                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19043         }
initisa::npu_op_pmu_mask_t19044         CONSTEXPR void init()
19045         {
19046             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK);
19047             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19048         }
uint32_tisa::npu_op_pmu_mask_t19049         operator uint32_t()
19050         {
19051             uint32_t word;
19052             std::memcpy(&word, this, sizeof(word));
19053             return word;
19054         }
get_opcodeisa::npu_op_pmu_mask_t19055         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19056         {
19057             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19058         }
set_opcodeisa::npu_op_pmu_mask_t19059         CONSTEXPR npu_op_pmu_mask_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19060         {
19061             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19062             return *this;
19063         }
get_controlisa::npu_op_pmu_mask_t19064         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19065         {
19066             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19067         }
set_controlisa::npu_op_pmu_mask_t19068         CONSTEXPR npu_op_pmu_mask_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19069         {
19070             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19071             return *this;
19072         }
get_enableisa::npu_op_pmu_mask_t19073         CONSTEXPR uint32_t get_enable() const
19074         {
19075             return static_cast<uint32_t>(enable);
19076         }
set_enableisa::npu_op_pmu_mask_t19077         CONSTEXPR npu_op_pmu_mask_t &set_enable(uint32_t value)
19078         {
19079             enable = static_cast<uint8_t>(value) & ((1U << 1) - 1);
19080             return *this;
19081         }
19082 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_op_pmu_mask_t19083         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19084         {
19085             fields.push_back(std::make_pair<std::string, std::string>("enable", std::to_string(enable)));
19086         }
19087 #endif
19088 #endif
19089     };
19090     // IFM top pad
19091     struct npu_set_ifm_pad_top_t
19092     {
19093 #ifdef __cplusplus
19094       private:
19095 #endif
19096         uint32_t opcode : 10; //  opcode
19097         uint32_t reserved0 : 4;
19098         uint32_t control : 2; //  control
19099         uint32_t pad : 7;     //  IFM top pad
19100         uint32_t reserved1 : 9;
19101 #ifdef __cplusplus
19102       public:
npu_set_ifm_pad_top_tisa::npu_set_ifm_pad_top_t19103         npu_set_ifm_pad_top_t(uint32_t _pad) :
19104             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP)), reserved0(0),
19105             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 7) - 1)), reserved1(0)
19106         {
19107         }
npu_set_ifm_pad_top_tisa::npu_set_ifm_pad_top_t19108         CONSTEXPR npu_set_ifm_pad_top_t() :
19109             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP)), reserved0(0),
19110             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19111         {
19112         }
validisa::npu_set_ifm_pad_top_t19113         CONSTEXPR bool valid() const
19114         {
19115             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP) &&
19116                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19117         }
initisa::npu_set_ifm_pad_top_t19118         CONSTEXPR void init()
19119         {
19120             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP);
19121             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19122         }
uint32_tisa::npu_set_ifm_pad_top_t19123         operator uint32_t()
19124         {
19125             uint32_t word;
19126             std::memcpy(&word, this, sizeof(word));
19127             return word;
19128         }
get_opcodeisa::npu_set_ifm_pad_top_t19129         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19130         {
19131             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19132         }
set_opcodeisa::npu_set_ifm_pad_top_t19133         CONSTEXPR npu_set_ifm_pad_top_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19134         {
19135             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19136             return *this;
19137         }
get_controlisa::npu_set_ifm_pad_top_t19138         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19139         {
19140             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19141         }
set_controlisa::npu_set_ifm_pad_top_t19142         CONSTEXPR npu_set_ifm_pad_top_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19143         {
19144             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19145             return *this;
19146         }
get_padisa::npu_set_ifm_pad_top_t19147         CONSTEXPR uint32_t get_pad() const
19148         {
19149             return static_cast<uint32_t>(pad);
19150         }
set_padisa::npu_set_ifm_pad_top_t19151         CONSTEXPR npu_set_ifm_pad_top_t &set_pad(uint32_t value)
19152         {
19153             pad = static_cast<uint8_t>(value) & ((1U << 7) - 1);
19154             return *this;
19155         }
19156 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_pad_top_t19157         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19158         {
19159             fields.push_back(std::make_pair<std::string, std::string>("pad", std::to_string(pad)));
19160         }
19161 #endif
19162 #endif
19163     };
19164     // IFM left pad
19165     struct npu_set_ifm_pad_left_t
19166     {
19167 #ifdef __cplusplus
19168       private:
19169 #endif
19170         uint32_t opcode : 10; //  opcode
19171         uint32_t reserved0 : 4;
19172         uint32_t control : 2; //  control
19173         uint32_t pad : 7;     //  IFM left pad
19174         uint32_t reserved1 : 9;
19175 #ifdef __cplusplus
19176       public:
npu_set_ifm_pad_left_tisa::npu_set_ifm_pad_left_t19177         npu_set_ifm_pad_left_t(uint32_t _pad) :
19178             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT)), reserved0(0),
19179             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 7) - 1)), reserved1(0)
19180         {
19181         }
npu_set_ifm_pad_left_tisa::npu_set_ifm_pad_left_t19182         CONSTEXPR npu_set_ifm_pad_left_t() :
19183             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT)), reserved0(0),
19184             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19185         {
19186         }
validisa::npu_set_ifm_pad_left_t19187         CONSTEXPR bool valid() const
19188         {
19189             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT) &&
19190                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19191         }
initisa::npu_set_ifm_pad_left_t19192         CONSTEXPR void init()
19193         {
19194             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT);
19195             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19196         }
uint32_tisa::npu_set_ifm_pad_left_t19197         operator uint32_t()
19198         {
19199             uint32_t word;
19200             std::memcpy(&word, this, sizeof(word));
19201             return word;
19202         }
get_opcodeisa::npu_set_ifm_pad_left_t19203         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19204         {
19205             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19206         }
set_opcodeisa::npu_set_ifm_pad_left_t19207         CONSTEXPR npu_set_ifm_pad_left_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19208         {
19209             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19210             return *this;
19211         }
get_controlisa::npu_set_ifm_pad_left_t19212         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19213         {
19214             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19215         }
set_controlisa::npu_set_ifm_pad_left_t19216         CONSTEXPR npu_set_ifm_pad_left_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19217         {
19218             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19219             return *this;
19220         }
get_padisa::npu_set_ifm_pad_left_t19221         CONSTEXPR uint32_t get_pad() const
19222         {
19223             return static_cast<uint32_t>(pad);
19224         }
set_padisa::npu_set_ifm_pad_left_t19225         CONSTEXPR npu_set_ifm_pad_left_t &set_pad(uint32_t value)
19226         {
19227             pad = static_cast<uint8_t>(value) & ((1U << 7) - 1);
19228             return *this;
19229         }
19230 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_pad_left_t19231         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19232         {
19233             fields.push_back(std::make_pair<std::string, std::string>("pad", std::to_string(pad)));
19234         }
19235 #endif
19236 #endif
19237     };
19238     // IFM right pad
19239     struct npu_set_ifm_pad_right_t
19240     {
19241 #ifdef __cplusplus
19242       private:
19243 #endif
19244         uint32_t opcode : 10; //  opcode
19245         uint32_t reserved0 : 4;
19246         uint32_t control : 2; //  control
19247         uint32_t pad : 8;     //  IFM right pad. Max value is 128
19248         uint32_t reserved1 : 8;
19249 #ifdef __cplusplus
19250       public:
npu_set_ifm_pad_right_tisa::npu_set_ifm_pad_right_t19251         npu_set_ifm_pad_right_t(uint32_t _pad) :
19252             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT)), reserved0(0),
19253             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 8) - 1)), reserved1(0)
19254         {
19255         }
npu_set_ifm_pad_right_tisa::npu_set_ifm_pad_right_t19256         CONSTEXPR npu_set_ifm_pad_right_t() :
19257             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT)), reserved0(0),
19258             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19259         {
19260         }
validisa::npu_set_ifm_pad_right_t19261         CONSTEXPR bool valid() const
19262         {
19263             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT) &&
19264                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19265         }
initisa::npu_set_ifm_pad_right_t19266         CONSTEXPR void init()
19267         {
19268             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT);
19269             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19270         }
uint32_tisa::npu_set_ifm_pad_right_t19271         operator uint32_t()
19272         {
19273             uint32_t word;
19274             std::memcpy(&word, this, sizeof(word));
19275             return word;
19276         }
get_opcodeisa::npu_set_ifm_pad_right_t19277         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19278         {
19279             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19280         }
set_opcodeisa::npu_set_ifm_pad_right_t19281         CONSTEXPR npu_set_ifm_pad_right_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19282         {
19283             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19284             return *this;
19285         }
get_controlisa::npu_set_ifm_pad_right_t19286         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19287         {
19288             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19289         }
set_controlisa::npu_set_ifm_pad_right_t19290         CONSTEXPR npu_set_ifm_pad_right_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19291         {
19292             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19293             return *this;
19294         }
get_padisa::npu_set_ifm_pad_right_t19295         CONSTEXPR uint32_t get_pad() const
19296         {
19297             return static_cast<uint32_t>(pad);
19298         }
set_padisa::npu_set_ifm_pad_right_t19299         CONSTEXPR npu_set_ifm_pad_right_t &set_pad(uint32_t value)
19300         {
19301             pad = static_cast<uint8_t>(value) & ((1U << 8) - 1);
19302             return *this;
19303         }
19304 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_pad_right_t19305         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19306         {
19307             fields.push_back(std::make_pair<std::string, std::string>("pad", std::to_string(pad)));
19308         }
19309 #endif
19310 #endif
19311     };
19312     // IFM bottom pad
19313     struct npu_set_ifm_pad_bottom_t
19314     {
19315 #ifdef __cplusplus
19316       private:
19317 #endif
19318         uint32_t opcode : 10; //  opcode
19319         uint32_t reserved0 : 4;
19320         uint32_t control : 2; //  control
19321         uint32_t pad : 8;     //  IFM bottom pad. Max value is 128
19322         uint32_t reserved1 : 8;
19323 #ifdef __cplusplus
19324       public:
npu_set_ifm_pad_bottom_tisa::npu_set_ifm_pad_bottom_t19325         npu_set_ifm_pad_bottom_t(uint32_t _pad) :
19326             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM)), reserved0(0),
19327             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 8) - 1)), reserved1(0)
19328         {
19329         }
npu_set_ifm_pad_bottom_tisa::npu_set_ifm_pad_bottom_t19330         CONSTEXPR npu_set_ifm_pad_bottom_t() :
19331             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM)), reserved0(0),
19332             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19333         {
19334         }
validisa::npu_set_ifm_pad_bottom_t19335         CONSTEXPR bool valid() const
19336         {
19337             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM) &&
19338                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19339         }
initisa::npu_set_ifm_pad_bottom_t19340         CONSTEXPR void init()
19341         {
19342             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM);
19343             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19344         }
uint32_tisa::npu_set_ifm_pad_bottom_t19345         operator uint32_t()
19346         {
19347             uint32_t word;
19348             std::memcpy(&word, this, sizeof(word));
19349             return word;
19350         }
get_opcodeisa::npu_set_ifm_pad_bottom_t19351         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19352         {
19353             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19354         }
set_opcodeisa::npu_set_ifm_pad_bottom_t19355         CONSTEXPR npu_set_ifm_pad_bottom_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19356         {
19357             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19358             return *this;
19359         }
get_controlisa::npu_set_ifm_pad_bottom_t19360         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19361         {
19362             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19363         }
set_controlisa::npu_set_ifm_pad_bottom_t19364         CONSTEXPR npu_set_ifm_pad_bottom_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19365         {
19366             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19367             return *this;
19368         }
get_padisa::npu_set_ifm_pad_bottom_t19369         CONSTEXPR uint32_t get_pad() const
19370         {
19371             return static_cast<uint32_t>(pad);
19372         }
set_padisa::npu_set_ifm_pad_bottom_t19373         CONSTEXPR npu_set_ifm_pad_bottom_t &set_pad(uint32_t value)
19374         {
19375             pad = static_cast<uint8_t>(value) & ((1U << 8) - 1);
19376             return *this;
19377         }
19378 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_pad_bottom_t19379         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19380         {
19381             fields.push_back(std::make_pair<std::string, std::string>("pad", std::to_string(pad)));
19382         }
19383 #endif
19384 #endif
19385     };
19386     // Number of input channels for convolution
19387     struct npu_set_ifm_depth_m1_t
19388     {
19389 #ifdef __cplusplus
19390       private:
19391 #endif
19392         uint32_t opcode : 10; //  opcode
19393         uint32_t reserved0 : 4;
19394         uint32_t control : 2;   //  control
19395         uint32_t depth_m1 : 16; //  Number of input channels for convolution
19396 #ifdef __cplusplus
19397       public:
npu_set_ifm_depth_m1_tisa::npu_set_ifm_depth_m1_t19398         npu_set_ifm_depth_m1_t(uint32_t _depth_m1) :
19399             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1)), reserved0(0),
19400             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 16) - 1))
19401         {
19402         }
npu_set_ifm_depth_m1_tisa::npu_set_ifm_depth_m1_t19403         CONSTEXPR npu_set_ifm_depth_m1_t() :
19404             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1)), reserved0(0),
19405             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0)
19406         {
19407         }
validisa::npu_set_ifm_depth_m1_t19408         CONSTEXPR bool valid() const
19409         {
19410             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1) &&
19411                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19412         }
initisa::npu_set_ifm_depth_m1_t19413         CONSTEXPR void init()
19414         {
19415             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1);
19416             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19417         }
uint32_tisa::npu_set_ifm_depth_m1_t19418         operator uint32_t()
19419         {
19420             uint32_t word;
19421             std::memcpy(&word, this, sizeof(word));
19422             return word;
19423         }
get_opcodeisa::npu_set_ifm_depth_m1_t19424         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19425         {
19426             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19427         }
set_opcodeisa::npu_set_ifm_depth_m1_t19428         CONSTEXPR npu_set_ifm_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19429         {
19430             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19431             return *this;
19432         }
get_controlisa::npu_set_ifm_depth_m1_t19433         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19434         {
19435             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19436         }
set_controlisa::npu_set_ifm_depth_m1_t19437         CONSTEXPR npu_set_ifm_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19438         {
19439             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19440             return *this;
19441         }
get_depth_m1isa::npu_set_ifm_depth_m1_t19442         CONSTEXPR uint32_t get_depth_m1() const
19443         {
19444             return static_cast<uint32_t>(depth_m1);
19445         }
set_depth_m1isa::npu_set_ifm_depth_m1_t19446         CONSTEXPR npu_set_ifm_depth_m1_t &set_depth_m1(uint32_t value)
19447         {
19448             depth_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
19449             return *this;
19450         }
19451 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_depth_m1_t19452         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19453         {
19454             fields.push_back(std::make_pair<std::string, std::string>("depth_m1", std::to_string(depth_m1)));
19455         }
19456 #endif
19457 #endif
19458     };
19459     // IFM Precision
19460     struct npu_set_ifm_precision_t
19461     {
19462 #ifdef __cplusplus
19463       private:
19464 #endif
19465         uint32_t opcode : 10; //  opcode
19466         uint32_t reserved0 : 4;
19467         uint32_t control : 2;         //  control
19468         uint32_t activation_type : 1; //  IFM type
19469         uint32_t reserved1 : 1;
19470         uint32_t activation_precision : 2; //  IFM precision
19471         uint32_t reserved2 : 2;
19472         uint32_t activation_format : 2; //  IFM format
19473         uint32_t scale_mode : 2;        //  IFM scale mode
19474         uint32_t reserved3 : 4;
19475         uint32_t round_mode : 2; //  IFM round mode
19476 #ifdef __cplusplus
19477       public:
npu_set_ifm_precision_tisa::npu_set_ifm_precision_t19478         npu_set_ifm_precision_t(NPU_NAMESPACE::activation_type _activation_type,
19479                                 NPU_NAMESPACE::activation_precision _activation_precision,
19480                                 NPU_NAMESPACE::activation_format _activation_format,
19481                                 NPU_NAMESPACE::ifm_scale_mode _scale_mode,
19482                                 NPU_NAMESPACE::round_mode _round_mode) :
19483             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION)),
19484             reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
19485             activation_type(static_cast<uint8_t>(_activation_type) & ((1U << 1) - 1)), reserved1(0),
19486             activation_precision(static_cast<uint8_t>(_activation_precision) & ((1U << 2) - 1)), reserved2(0),
19487             activation_format(static_cast<uint8_t>(_activation_format) & ((1U << 2) - 1)),
19488             scale_mode(static_cast<uint8_t>(_scale_mode) & ((1U << 2) - 1)), reserved3(0),
19489             round_mode(static_cast<uint8_t>(_round_mode) & ((1U << 2) - 1))
19490         {
19491         }
npu_set_ifm_precision_tisa::npu_set_ifm_precision_t19492         CONSTEXPR npu_set_ifm_precision_t() :
19493             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION)), reserved0(0),
19494             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_type(0), reserved1(0),
19495             activation_precision(0), reserved2(0), activation_format(0), scale_mode(0), reserved3(0), round_mode(0)
19496         {
19497         }
validisa::npu_set_ifm_precision_t19498         CONSTEXPR bool valid() const
19499         {
19500             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION) &&
19501                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19502         }
initisa::npu_set_ifm_precision_t19503         CONSTEXPR void init()
19504         {
19505             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION);
19506             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19507         }
uint32_tisa::npu_set_ifm_precision_t19508         operator uint32_t()
19509         {
19510             uint32_t word;
19511             std::memcpy(&word, this, sizeof(word));
19512             return word;
19513         }
get_opcodeisa::npu_set_ifm_precision_t19514         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19515         {
19516             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19517         }
set_opcodeisa::npu_set_ifm_precision_t19518         CONSTEXPR npu_set_ifm_precision_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19519         {
19520             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19521             return *this;
19522         }
get_controlisa::npu_set_ifm_precision_t19523         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19524         {
19525             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19526         }
set_controlisa::npu_set_ifm_precision_t19527         CONSTEXPR npu_set_ifm_precision_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19528         {
19529             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19530             return *this;
19531         }
get_activation_typeisa::npu_set_ifm_precision_t19532         CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type() const
19533         {
19534             return static_cast<NPU_NAMESPACE::activation_type>(activation_type);
19535         }
set_activation_typeisa::npu_set_ifm_precision_t19536         CONSTEXPR npu_set_ifm_precision_t &set_activation_type(NPU_NAMESPACE::activation_type value)
19537         {
19538             activation_type = static_cast<uint8_t>(value) & ((1U << 1) - 1);
19539             return *this;
19540         }
get_activation_precisionisa::npu_set_ifm_precision_t19541         CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision() const
19542         {
19543             return static_cast<NPU_NAMESPACE::activation_precision>(activation_precision);
19544         }
set_activation_precisionisa::npu_set_ifm_precision_t19545         CONSTEXPR npu_set_ifm_precision_t &set_activation_precision(NPU_NAMESPACE::activation_precision value)
19546         {
19547             activation_precision = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19548             return *this;
19549         }
get_activation_formatisa::npu_set_ifm_precision_t19550         CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format() const
19551         {
19552             return static_cast<NPU_NAMESPACE::activation_format>(activation_format);
19553         }
set_activation_formatisa::npu_set_ifm_precision_t19554         CONSTEXPR npu_set_ifm_precision_t &set_activation_format(NPU_NAMESPACE::activation_format value)
19555         {
19556             activation_format = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19557             return *this;
19558         }
get_scale_modeisa::npu_set_ifm_precision_t19559         CONSTEXPR NPU_NAMESPACE::ifm_scale_mode get_scale_mode() const
19560         {
19561             return static_cast<NPU_NAMESPACE::ifm_scale_mode>(scale_mode);
19562         }
set_scale_modeisa::npu_set_ifm_precision_t19563         CONSTEXPR npu_set_ifm_precision_t &set_scale_mode(NPU_NAMESPACE::ifm_scale_mode value)
19564         {
19565             scale_mode = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19566             return *this;
19567         }
get_round_modeisa::npu_set_ifm_precision_t19568         CONSTEXPR NPU_NAMESPACE::round_mode get_round_mode() const
19569         {
19570             return static_cast<NPU_NAMESPACE::round_mode>(round_mode);
19571         }
set_round_modeisa::npu_set_ifm_precision_t19572         CONSTEXPR npu_set_ifm_precision_t &set_round_mode(NPU_NAMESPACE::round_mode value)
19573         {
19574             round_mode = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19575             return *this;
19576         }
19577 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_precision_t19578         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19579         {
19580             fields.push_back(std::make_pair<std::string, std::string>(
19581                 "activation_type",
19582                 (activation_type < (sizeof(activation_type_str) / sizeof(activation_type_str[0])) ?
19583                      activation_type_str[activation_type] :
19584                      "****")));
19585             fields.push_back(std::make_pair<std::string, std::string>(
19586                 "activation_precision",
19587                 (activation_precision < (sizeof(activation_precision_str) / sizeof(activation_precision_str[0])) ?
19588                      activation_precision_str[activation_precision] :
19589                      "****")));
19590             fields.push_back(std::make_pair<std::string, std::string>(
19591                 "activation_format",
19592                 (activation_format < (sizeof(activation_format_str) / sizeof(activation_format_str[0])) ?
19593                      activation_format_str[activation_format] :
19594                      "****")));
19595             fields.push_back(std::make_pair<std::string, std::string>(
19596                 "scale_mode",
19597                 (scale_mode < (sizeof(ifm_scale_mode_str) / sizeof(ifm_scale_mode_str[0])) ?
19598                      ifm_scale_mode_str[scale_mode] :
19599                      "****")));
19600             fields.push_back(std::make_pair<std::string, std::string>(
19601                 "round_mode",
19602                 (round_mode < (sizeof(round_mode_str) / sizeof(round_mode_str[0])) ? round_mode_str[round_mode] :
19603                                                                                      "****")));
19604         }
19605 #endif
19606 #endif
19607     };
19608     // IFM upscale mode
19609     struct npu_set_ifm_upscale_t
19610     {
19611 #ifdef __cplusplus
19612       private:
19613 #endif
19614         uint32_t opcode : 10; //  opcode
19615         uint32_t reserved0 : 4;
19616         uint32_t control : 2; //  control
19617         uint32_t mode : 2;    //  IFM upscale mode
19618         uint32_t reserved1 : 14;
19619 #ifdef __cplusplus
19620       public:
npu_set_ifm_upscale_tisa::npu_set_ifm_upscale_t19621         npu_set_ifm_upscale_t(NPU_NAMESPACE::ifm_upscale_mode _mode) :
19622             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE)), reserved0(0),
19623             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
19624             mode(static_cast<uint8_t>(_mode) & ((1U << 2) - 1)), reserved1(0)
19625         {
19626         }
npu_set_ifm_upscale_tisa::npu_set_ifm_upscale_t19627         CONSTEXPR npu_set_ifm_upscale_t() :
19628             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE)), reserved0(0),
19629             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mode(0), reserved1(0)
19630         {
19631         }
validisa::npu_set_ifm_upscale_t19632         CONSTEXPR bool valid() const
19633         {
19634             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE) &&
19635                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19636         }
initisa::npu_set_ifm_upscale_t19637         CONSTEXPR void init()
19638         {
19639             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE);
19640             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19641         }
uint32_tisa::npu_set_ifm_upscale_t19642         operator uint32_t()
19643         {
19644             uint32_t word;
19645             std::memcpy(&word, this, sizeof(word));
19646             return word;
19647         }
get_opcodeisa::npu_set_ifm_upscale_t19648         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19649         {
19650             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19651         }
set_opcodeisa::npu_set_ifm_upscale_t19652         CONSTEXPR npu_set_ifm_upscale_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19653         {
19654             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19655             return *this;
19656         }
get_controlisa::npu_set_ifm_upscale_t19657         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19658         {
19659             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19660         }
set_controlisa::npu_set_ifm_upscale_t19661         CONSTEXPR npu_set_ifm_upscale_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19662         {
19663             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19664             return *this;
19665         }
get_modeisa::npu_set_ifm_upscale_t19666         CONSTEXPR NPU_NAMESPACE::ifm_upscale_mode get_mode() const
19667         {
19668             return static_cast<NPU_NAMESPACE::ifm_upscale_mode>(mode);
19669         }
set_modeisa::npu_set_ifm_upscale_t19670         CONSTEXPR npu_set_ifm_upscale_t &set_mode(NPU_NAMESPACE::ifm_upscale_mode value)
19671         {
19672             mode = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19673             return *this;
19674         }
19675 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_upscale_t19676         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19677         {
19678             fields.push_back(std::make_pair<std::string, std::string>(
19679                 "mode",
19680                 (mode < (sizeof(ifm_upscale_mode_str) / sizeof(ifm_upscale_mode_str[0])) ? ifm_upscale_mode_str[mode] :
19681                                                                                            "****")));
19682         }
19683 #endif
19684 #endif
19685     };
19686     // IFM zero point
19687     struct npu_set_ifm_zero_point_t
19688     {
19689 #ifdef __cplusplus
19690       private:
19691 #endif
19692         uint32_t opcode : 10; //  opcode
19693         uint32_t reserved0 : 4;
19694         uint32_t control : 2;     //  control
19695         uint32_t zero_point : 16; //  Zero point offset
19696 #ifdef __cplusplus
19697       public:
npu_set_ifm_zero_point_tisa::npu_set_ifm_zero_point_t19698         npu_set_ifm_zero_point_t(uint32_t _zero_point) :
19699             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT)), reserved0(0),
19700             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
19701             zero_point(_zero_point & ((1U << 16) - 1))
19702         {
19703         }
npu_set_ifm_zero_point_tisa::npu_set_ifm_zero_point_t19704         CONSTEXPR npu_set_ifm_zero_point_t() :
19705             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT)), reserved0(0),
19706             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), zero_point(0)
19707         {
19708         }
validisa::npu_set_ifm_zero_point_t19709         CONSTEXPR bool valid() const
19710         {
19711             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT) &&
19712                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19713         }
initisa::npu_set_ifm_zero_point_t19714         CONSTEXPR void init()
19715         {
19716             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT);
19717             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19718         }
uint32_tisa::npu_set_ifm_zero_point_t19719         operator uint32_t()
19720         {
19721             uint32_t word;
19722             std::memcpy(&word, this, sizeof(word));
19723             return word;
19724         }
get_opcodeisa::npu_set_ifm_zero_point_t19725         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19726         {
19727             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19728         }
set_opcodeisa::npu_set_ifm_zero_point_t19729         CONSTEXPR npu_set_ifm_zero_point_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19730         {
19731             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19732             return *this;
19733         }
get_controlisa::npu_set_ifm_zero_point_t19734         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19735         {
19736             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19737         }
set_controlisa::npu_set_ifm_zero_point_t19738         CONSTEXPR npu_set_ifm_zero_point_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19739         {
19740             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19741             return *this;
19742         }
get_zero_pointisa::npu_set_ifm_zero_point_t19743         CONSTEXPR uint32_t get_zero_point() const
19744         {
19745             return static_cast<uint32_t>(zero_point);
19746         }
set_zero_pointisa::npu_set_ifm_zero_point_t19747         CONSTEXPR npu_set_ifm_zero_point_t &set_zero_point(uint32_t value)
19748         {
19749             zero_point = static_cast<uint16_t>(value) & ((1U << 16) - 1);
19750             return *this;
19751         }
19752 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_zero_point_t19753         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19754         {
19755             fields.push_back(std::make_pair<std::string, std::string>("zero_point", std::to_string(zero_point)));
19756         }
19757 #endif
19758 #endif
19759     };
19760     // IFM Tile 0 and tile 2 width
19761     struct npu_set_ifm_width0_m1_t
19762     {
19763 #ifdef __cplusplus
19764       private:
19765 #endif
19766         uint32_t opcode : 10; //  opcode
19767         uint32_t reserved0 : 4;
19768         uint32_t control : 2;   //  control
19769         uint32_t width_m1 : 16; //  IFM Tile 0 and tile 2 width
19770 #ifdef __cplusplus
19771       public:
npu_set_ifm_width0_m1_tisa::npu_set_ifm_width0_m1_t19772         npu_set_ifm_width0_m1_t(uint32_t _width_m1) :
19773             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1)), reserved0(0),
19774             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
19775         {
19776         }
npu_set_ifm_width0_m1_tisa::npu_set_ifm_width0_m1_t19777         CONSTEXPR npu_set_ifm_width0_m1_t() :
19778             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1)), reserved0(0),
19779             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0)
19780         {
19781         }
validisa::npu_set_ifm_width0_m1_t19782         CONSTEXPR bool valid() const
19783         {
19784             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1) &&
19785                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19786         }
initisa::npu_set_ifm_width0_m1_t19787         CONSTEXPR void init()
19788         {
19789             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1);
19790             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19791         }
uint32_tisa::npu_set_ifm_width0_m1_t19792         operator uint32_t()
19793         {
19794             uint32_t word;
19795             std::memcpy(&word, this, sizeof(word));
19796             return word;
19797         }
get_opcodeisa::npu_set_ifm_width0_m1_t19798         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19799         {
19800             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19801         }
set_opcodeisa::npu_set_ifm_width0_m1_t19802         CONSTEXPR npu_set_ifm_width0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19803         {
19804             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19805             return *this;
19806         }
get_controlisa::npu_set_ifm_width0_m1_t19807         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19808         {
19809             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19810         }
set_controlisa::npu_set_ifm_width0_m1_t19811         CONSTEXPR npu_set_ifm_width0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19812         {
19813             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19814             return *this;
19815         }
get_width_m1isa::npu_set_ifm_width0_m1_t19816         CONSTEXPR uint32_t get_width_m1() const
19817         {
19818             return static_cast<uint32_t>(width_m1);
19819         }
set_width_m1isa::npu_set_ifm_width0_m1_t19820         CONSTEXPR npu_set_ifm_width0_m1_t &set_width_m1(uint32_t value)
19821         {
19822             width_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
19823             return *this;
19824         }
19825 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_width0_m1_t19826         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19827         {
19828             fields.push_back(std::make_pair<std::string, std::string>("width_m1", std::to_string(width_m1)));
19829         }
19830 #endif
19831 #endif
19832     };
19833     // IFM Tile 0 height
19834     struct npu_set_ifm_height0_m1_t
19835     {
19836 #ifdef __cplusplus
19837       private:
19838 #endif
19839         uint32_t opcode : 10; //  opcode
19840         uint32_t reserved0 : 4;
19841         uint32_t control : 2;    //  control
19842         uint32_t height_m1 : 16; //  IFM Tile 0 height
19843 #ifdef __cplusplus
19844       public:
npu_set_ifm_height0_m1_tisa::npu_set_ifm_height0_m1_t19845         npu_set_ifm_height0_m1_t(uint32_t _height_m1) :
19846             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1)), reserved0(0),
19847             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
19848         {
19849         }
npu_set_ifm_height0_m1_tisa::npu_set_ifm_height0_m1_t19850         CONSTEXPR npu_set_ifm_height0_m1_t() :
19851             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1)), reserved0(0),
19852             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
19853         {
19854         }
validisa::npu_set_ifm_height0_m1_t19855         CONSTEXPR bool valid() const
19856         {
19857             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1) &&
19858                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19859         }
initisa::npu_set_ifm_height0_m1_t19860         CONSTEXPR void init()
19861         {
19862             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1);
19863             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19864         }
uint32_tisa::npu_set_ifm_height0_m1_t19865         operator uint32_t()
19866         {
19867             uint32_t word;
19868             std::memcpy(&word, this, sizeof(word));
19869             return word;
19870         }
get_opcodeisa::npu_set_ifm_height0_m1_t19871         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19872         {
19873             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19874         }
set_opcodeisa::npu_set_ifm_height0_m1_t19875         CONSTEXPR npu_set_ifm_height0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19876         {
19877             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19878             return *this;
19879         }
get_controlisa::npu_set_ifm_height0_m1_t19880         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19881         {
19882             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19883         }
set_controlisa::npu_set_ifm_height0_m1_t19884         CONSTEXPR npu_set_ifm_height0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19885         {
19886             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19887             return *this;
19888         }
get_height_m1isa::npu_set_ifm_height0_m1_t19889         CONSTEXPR uint32_t get_height_m1() const
19890         {
19891             return static_cast<uint32_t>(height_m1);
19892         }
set_height_m1isa::npu_set_ifm_height0_m1_t19893         CONSTEXPR npu_set_ifm_height0_m1_t &set_height_m1(uint32_t value)
19894         {
19895             height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
19896             return *this;
19897         }
19898 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_height0_m1_t19899         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19900         {
19901             fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
19902         }
19903 #endif
19904 #endif
19905     };
19906     // IFM Tile 1 height
19907     struct npu_set_ifm_height1_m1_t
19908     {
19909 #ifdef __cplusplus
19910       private:
19911 #endif
19912         uint32_t opcode : 10; //  opcode
19913         uint32_t reserved0 : 4;
19914         uint32_t control : 2;    //  control
19915         uint32_t height_m1 : 16; //  IFM Tile 1 height
19916 #ifdef __cplusplus
19917       public:
npu_set_ifm_height1_m1_tisa::npu_set_ifm_height1_m1_t19918         npu_set_ifm_height1_m1_t(uint32_t _height_m1) :
19919             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1)), reserved0(0),
19920             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
19921         {
19922         }
npu_set_ifm_height1_m1_tisa::npu_set_ifm_height1_m1_t19923         CONSTEXPR npu_set_ifm_height1_m1_t() :
19924             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1)), reserved0(0),
19925             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
19926         {
19927         }
validisa::npu_set_ifm_height1_m1_t19928         CONSTEXPR bool valid() const
19929         {
19930             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1) &&
19931                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19932         }
initisa::npu_set_ifm_height1_m1_t19933         CONSTEXPR void init()
19934         {
19935             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1);
19936             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19937         }
uint32_tisa::npu_set_ifm_height1_m1_t19938         operator uint32_t()
19939         {
19940             uint32_t word;
19941             std::memcpy(&word, this, sizeof(word));
19942             return word;
19943         }
get_opcodeisa::npu_set_ifm_height1_m1_t19944         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19945         {
19946             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19947         }
set_opcodeisa::npu_set_ifm_height1_m1_t19948         CONSTEXPR npu_set_ifm_height1_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19949         {
19950             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19951             return *this;
19952         }
get_controlisa::npu_set_ifm_height1_m1_t19953         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19954         {
19955             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19956         }
set_controlisa::npu_set_ifm_height1_m1_t19957         CONSTEXPR npu_set_ifm_height1_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19958         {
19959             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19960             return *this;
19961         }
get_height_m1isa::npu_set_ifm_height1_m1_t19962         CONSTEXPR uint32_t get_height_m1() const
19963         {
19964             return static_cast<uint32_t>(height_m1);
19965         }
set_height_m1isa::npu_set_ifm_height1_m1_t19966         CONSTEXPR npu_set_ifm_height1_m1_t &set_height_m1(uint32_t value)
19967         {
19968             height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
19969             return *this;
19970         }
19971 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_height1_m1_t19972         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19973         {
19974             fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
19975         }
19976 #endif
19977 #endif
19978     };
19979     // End of IB0,IB1 buffers
19980     struct npu_set_ifm_ib_end_t
19981     {
19982 #ifdef __cplusplus
19983       private:
19984 #endif
19985         uint32_t opcode : 10; //  opcode
19986         uint32_t reserved0 : 4;
19987         uint32_t control : 2; //  control
19988         uint32_t ib_end : 6;  //  End of IB0,IB1 buffers in the SHRAM in KB units. Multiple of 2
19989         uint32_t reserved1 : 10;
19990 #ifdef __cplusplus
19991       public:
npu_set_ifm_ib_end_tisa::npu_set_ifm_ib_end_t19992         npu_set_ifm_ib_end_t(uint32_t _ib_end) :
19993             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END)), reserved0(0),
19994             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_end(_ib_end & ((1U << 6) - 1)),
19995             reserved1(0)
19996         {
19997         }
npu_set_ifm_ib_end_tisa::npu_set_ifm_ib_end_t19998         CONSTEXPR npu_set_ifm_ib_end_t() :
19999             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END)), reserved0(0),
20000             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_end(0), reserved1(0)
20001         {
20002         }
validisa::npu_set_ifm_ib_end_t20003         CONSTEXPR bool valid() const
20004         {
20005             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END) &&
20006                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20007         }
initisa::npu_set_ifm_ib_end_t20008         CONSTEXPR void init()
20009         {
20010             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END);
20011             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20012         }
uint32_tisa::npu_set_ifm_ib_end_t20013         operator uint32_t()
20014         {
20015             uint32_t word;
20016             std::memcpy(&word, this, sizeof(word));
20017             return word;
20018         }
get_opcodeisa::npu_set_ifm_ib_end_t20019         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20020         {
20021             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20022         }
set_opcodeisa::npu_set_ifm_ib_end_t20023         CONSTEXPR npu_set_ifm_ib_end_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20024         {
20025             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20026             return *this;
20027         }
get_controlisa::npu_set_ifm_ib_end_t20028         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20029         {
20030             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20031         }
set_controlisa::npu_set_ifm_ib_end_t20032         CONSTEXPR npu_set_ifm_ib_end_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20033         {
20034             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20035             return *this;
20036         }
get_ib_endisa::npu_set_ifm_ib_end_t20037         CONSTEXPR uint32_t get_ib_end() const
20038         {
20039             return static_cast<uint32_t>(ib_end);
20040         }
set_ib_endisa::npu_set_ifm_ib_end_t20041         CONSTEXPR npu_set_ifm_ib_end_t &set_ib_end(uint32_t value)
20042         {
20043             ib_end = static_cast<uint8_t>(value) & ((1U << 6) - 1);
20044             return *this;
20045         }
20046 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_ib_end_t20047         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20048         {
20049             fields.push_back(std::make_pair<std::string, std::string>("ib_end", std::to_string(ib_end)));
20050         }
20051 #endif
20052 #endif
20053     };
20054     // Index n for IFM access
20055     struct npu_set_ifm_region_t
20056     {
20057 #ifdef __cplusplus
20058       private:
20059 #endif
20060         uint32_t opcode : 10; //  opcode
20061         uint32_t reserved0 : 4;
20062         uint32_t control : 2; //  control
20063         uint32_t region : 3;  //  Region number n
20064         uint32_t reserved1 : 13;
20065 #ifdef __cplusplus
20066       public:
npu_set_ifm_region_tisa::npu_set_ifm_region_t20067         npu_set_ifm_region_t(uint32_t _region) :
20068             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION)), reserved0(0),
20069             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
20070             reserved1(0)
20071         {
20072         }
npu_set_ifm_region_tisa::npu_set_ifm_region_t20073         CONSTEXPR npu_set_ifm_region_t() :
20074             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION)), reserved0(0),
20075             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
20076         {
20077         }
validisa::npu_set_ifm_region_t20078         CONSTEXPR bool valid() const
20079         {
20080             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION) &&
20081                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20082         }
initisa::npu_set_ifm_region_t20083         CONSTEXPR void init()
20084         {
20085             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION);
20086             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20087         }
uint32_tisa::npu_set_ifm_region_t20088         operator uint32_t()
20089         {
20090             uint32_t word;
20091             std::memcpy(&word, this, sizeof(word));
20092             return word;
20093         }
get_opcodeisa::npu_set_ifm_region_t20094         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20095         {
20096             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20097         }
set_opcodeisa::npu_set_ifm_region_t20098         CONSTEXPR npu_set_ifm_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20099         {
20100             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20101             return *this;
20102         }
get_controlisa::npu_set_ifm_region_t20103         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20104         {
20105             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20106         }
set_controlisa::npu_set_ifm_region_t20107         CONSTEXPR npu_set_ifm_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20108         {
20109             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20110             return *this;
20111         }
get_regionisa::npu_set_ifm_region_t20112         CONSTEXPR uint32_t get_region() const
20113         {
20114             return static_cast<uint32_t>(region);
20115         }
set_regionisa::npu_set_ifm_region_t20116         CONSTEXPR npu_set_ifm_region_t &set_region(uint32_t value)
20117         {
20118             region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
20119             return *this;
20120         }
20121 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ifm_region_t20122         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20123         {
20124             fields.push_back(std::make_pair<std::string, std::string>("region", std::to_string(region)));
20125         }
20126 #endif
20127 #endif
20128     };
20129     // Output feature map width
20130     struct npu_set_ofm_width_m1_t
20131     {
20132 #ifdef __cplusplus
20133       private:
20134 #endif
20135         uint32_t opcode : 10; //  opcode
20136         uint32_t reserved0 : 4;
20137         uint32_t control : 2;   //  control
20138         uint32_t width_m1 : 16; //  Output feature map width
20139 #ifdef __cplusplus
20140       public:
npu_set_ofm_width_m1_tisa::npu_set_ofm_width_m1_t20141         npu_set_ofm_width_m1_t(uint32_t _width_m1) :
20142             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1)), reserved0(0),
20143             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
20144         {
20145         }
npu_set_ofm_width_m1_tisa::npu_set_ofm_width_m1_t20146         CONSTEXPR npu_set_ofm_width_m1_t() :
20147             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1)), reserved0(0),
20148             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0)
20149         {
20150         }
validisa::npu_set_ofm_width_m1_t20151         CONSTEXPR bool valid() const
20152         {
20153             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1) &&
20154                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20155         }
initisa::npu_set_ofm_width_m1_t20156         CONSTEXPR void init()
20157         {
20158             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1);
20159             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20160         }
uint32_tisa::npu_set_ofm_width_m1_t20161         operator uint32_t()
20162         {
20163             uint32_t word;
20164             std::memcpy(&word, this, sizeof(word));
20165             return word;
20166         }
get_opcodeisa::npu_set_ofm_width_m1_t20167         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20168         {
20169             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20170         }
set_opcodeisa::npu_set_ofm_width_m1_t20171         CONSTEXPR npu_set_ofm_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20172         {
20173             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20174             return *this;
20175         }
get_controlisa::npu_set_ofm_width_m1_t20176         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20177         {
20178             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20179         }
set_controlisa::npu_set_ofm_width_m1_t20180         CONSTEXPR npu_set_ofm_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20181         {
20182             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20183             return *this;
20184         }
get_width_m1isa::npu_set_ofm_width_m1_t20185         CONSTEXPR uint32_t get_width_m1() const
20186         {
20187             return static_cast<uint32_t>(width_m1);
20188         }
set_width_m1isa::npu_set_ofm_width_m1_t20189         CONSTEXPR npu_set_ofm_width_m1_t &set_width_m1(uint32_t value)
20190         {
20191             width_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20192             return *this;
20193         }
20194 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_width_m1_t20195         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20196         {
20197             fields.push_back(std::make_pair<std::string, std::string>("width_m1", std::to_string(width_m1)));
20198         }
20199 #endif
20200 #endif
20201     };
20202     // Output feature map height
20203     struct npu_set_ofm_height_m1_t
20204     {
20205 #ifdef __cplusplus
20206       private:
20207 #endif
20208         uint32_t opcode : 10; //  opcode
20209         uint32_t reserved0 : 4;
20210         uint32_t control : 2;    //  control
20211         uint32_t height_m1 : 16; //  Output feature map height
20212 #ifdef __cplusplus
20213       public:
npu_set_ofm_height_m1_tisa::npu_set_ofm_height_m1_t20214         npu_set_ofm_height_m1_t(uint32_t _height_m1) :
20215             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1)), reserved0(0),
20216             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
20217         {
20218         }
npu_set_ofm_height_m1_tisa::npu_set_ofm_height_m1_t20219         CONSTEXPR npu_set_ofm_height_m1_t() :
20220             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1)), reserved0(0),
20221             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
20222         {
20223         }
validisa::npu_set_ofm_height_m1_t20224         CONSTEXPR bool valid() const
20225         {
20226             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1) &&
20227                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20228         }
initisa::npu_set_ofm_height_m1_t20229         CONSTEXPR void init()
20230         {
20231             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1);
20232             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20233         }
uint32_tisa::npu_set_ofm_height_m1_t20234         operator uint32_t()
20235         {
20236             uint32_t word;
20237             std::memcpy(&word, this, sizeof(word));
20238             return word;
20239         }
get_opcodeisa::npu_set_ofm_height_m1_t20240         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20241         {
20242             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20243         }
set_opcodeisa::npu_set_ofm_height_m1_t20244         CONSTEXPR npu_set_ofm_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20245         {
20246             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20247             return *this;
20248         }
get_controlisa::npu_set_ofm_height_m1_t20249         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20250         {
20251             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20252         }
set_controlisa::npu_set_ofm_height_m1_t20253         CONSTEXPR npu_set_ofm_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20254         {
20255             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20256             return *this;
20257         }
get_height_m1isa::npu_set_ofm_height_m1_t20258         CONSTEXPR uint32_t get_height_m1() const
20259         {
20260             return static_cast<uint32_t>(height_m1);
20261         }
set_height_m1isa::npu_set_ofm_height_m1_t20262         CONSTEXPR npu_set_ofm_height_m1_t &set_height_m1(uint32_t value)
20263         {
20264             height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20265             return *this;
20266         }
20267 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_height_m1_t20268         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20269         {
20270             fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
20271         }
20272 #endif
20273 #endif
20274     };
20275     // Output feature map depth
20276     struct npu_set_ofm_depth_m1_t
20277     {
20278 #ifdef __cplusplus
20279       private:
20280 #endif
20281         uint32_t opcode : 10; //  opcode
20282         uint32_t reserved0 : 4;
20283         uint32_t control : 2;   //  control
20284         uint32_t depth_m1 : 16; //  Output feature map depth
20285 #ifdef __cplusplus
20286       public:
npu_set_ofm_depth_m1_tisa::npu_set_ofm_depth_m1_t20287         npu_set_ofm_depth_m1_t(uint32_t _depth_m1) :
20288             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1)), reserved0(0),
20289             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 16) - 1))
20290         {
20291         }
npu_set_ofm_depth_m1_tisa::npu_set_ofm_depth_m1_t20292         CONSTEXPR npu_set_ofm_depth_m1_t() :
20293             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1)), reserved0(0),
20294             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0)
20295         {
20296         }
validisa::npu_set_ofm_depth_m1_t20297         CONSTEXPR bool valid() const
20298         {
20299             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1) &&
20300                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20301         }
initisa::npu_set_ofm_depth_m1_t20302         CONSTEXPR void init()
20303         {
20304             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1);
20305             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20306         }
uint32_tisa::npu_set_ofm_depth_m1_t20307         operator uint32_t()
20308         {
20309             uint32_t word;
20310             std::memcpy(&word, this, sizeof(word));
20311             return word;
20312         }
get_opcodeisa::npu_set_ofm_depth_m1_t20313         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20314         {
20315             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20316         }
set_opcodeisa::npu_set_ofm_depth_m1_t20317         CONSTEXPR npu_set_ofm_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20318         {
20319             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20320             return *this;
20321         }
get_controlisa::npu_set_ofm_depth_m1_t20322         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20323         {
20324             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20325         }
set_controlisa::npu_set_ofm_depth_m1_t20326         CONSTEXPR npu_set_ofm_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20327         {
20328             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20329             return *this;
20330         }
get_depth_m1isa::npu_set_ofm_depth_m1_t20331         CONSTEXPR uint32_t get_depth_m1() const
20332         {
20333             return static_cast<uint32_t>(depth_m1);
20334         }
set_depth_m1isa::npu_set_ofm_depth_m1_t20335         CONSTEXPR npu_set_ofm_depth_m1_t &set_depth_m1(uint32_t value)
20336         {
20337             depth_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20338             return *this;
20339         }
20340 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_depth_m1_t20341         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20342         {
20343             fields.push_back(std::make_pair<std::string, std::string>("depth_m1", std::to_string(depth_m1)));
20344         }
20345 #endif
20346 #endif
20347     };
20348     // OFM Precision
20349     struct npu_set_ofm_precision_t
20350     {
20351 #ifdef __cplusplus
20352       private:
20353 #endif
20354         uint32_t opcode : 10; //  opcode
20355         uint32_t reserved0 : 4;
20356         uint32_t control : 2;              //  control
20357         uint32_t activation_type : 1;      //  OFM type
20358         uint32_t activation_precision : 2; //  OFM precision
20359         uint32_t reserved1 : 3;
20360         uint32_t activation_format : 2; //  OFM format
20361         uint32_t scale_mode : 1;        //  OFM scale mode
20362         uint32_t reserved2 : 5;
20363         uint32_t round_mode : 2; //  OFM round mode
20364 #ifdef __cplusplus
20365       public:
npu_set_ofm_precision_tisa::npu_set_ofm_precision_t20366         npu_set_ofm_precision_t(NPU_NAMESPACE::activation_type _activation_type,
20367                                 NPU_NAMESPACE::activation_precision _activation_precision,
20368                                 NPU_NAMESPACE::activation_format _activation_format,
20369                                 NPU_NAMESPACE::ofm_scale_mode _scale_mode,
20370                                 NPU_NAMESPACE::round_mode _round_mode) :
20371             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION)),
20372             reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
20373             activation_type(static_cast<uint8_t>(_activation_type) & ((1U << 1) - 1)),
20374             activation_precision(static_cast<uint8_t>(_activation_precision) & ((1U << 2) - 1)), reserved1(0),
20375             activation_format(static_cast<uint8_t>(_activation_format) & ((1U << 2) - 1)),
20376             scale_mode(static_cast<uint8_t>(_scale_mode) & ((1U << 1) - 1)), reserved2(0),
20377             round_mode(static_cast<uint8_t>(_round_mode) & ((1U << 2) - 1))
20378         {
20379         }
npu_set_ofm_precision_tisa::npu_set_ofm_precision_t20380         CONSTEXPR npu_set_ofm_precision_t() :
20381             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION)), reserved0(0),
20382             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_type(0),
20383             activation_precision(0), reserved1(0), activation_format(0), scale_mode(0), reserved2(0), round_mode(0)
20384         {
20385         }
validisa::npu_set_ofm_precision_t20386         CONSTEXPR bool valid() const
20387         {
20388             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION) &&
20389                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20390         }
initisa::npu_set_ofm_precision_t20391         CONSTEXPR void init()
20392         {
20393             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION);
20394             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20395         }
uint32_tisa::npu_set_ofm_precision_t20396         operator uint32_t()
20397         {
20398             uint32_t word;
20399             std::memcpy(&word, this, sizeof(word));
20400             return word;
20401         }
get_opcodeisa::npu_set_ofm_precision_t20402         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20403         {
20404             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20405         }
set_opcodeisa::npu_set_ofm_precision_t20406         CONSTEXPR npu_set_ofm_precision_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20407         {
20408             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20409             return *this;
20410         }
get_controlisa::npu_set_ofm_precision_t20411         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20412         {
20413             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20414         }
set_controlisa::npu_set_ofm_precision_t20415         CONSTEXPR npu_set_ofm_precision_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20416         {
20417             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20418             return *this;
20419         }
get_activation_typeisa::npu_set_ofm_precision_t20420         CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type() const
20421         {
20422             return static_cast<NPU_NAMESPACE::activation_type>(activation_type);
20423         }
set_activation_typeisa::npu_set_ofm_precision_t20424         CONSTEXPR npu_set_ofm_precision_t &set_activation_type(NPU_NAMESPACE::activation_type value)
20425         {
20426             activation_type = static_cast<uint8_t>(value) & ((1U << 1) - 1);
20427             return *this;
20428         }
get_activation_precisionisa::npu_set_ofm_precision_t20429         CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision() const
20430         {
20431             return static_cast<NPU_NAMESPACE::activation_precision>(activation_precision);
20432         }
set_activation_precisionisa::npu_set_ofm_precision_t20433         CONSTEXPR npu_set_ofm_precision_t &set_activation_precision(NPU_NAMESPACE::activation_precision value)
20434         {
20435             activation_precision = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20436             return *this;
20437         }
get_activation_formatisa::npu_set_ofm_precision_t20438         CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format() const
20439         {
20440             return static_cast<NPU_NAMESPACE::activation_format>(activation_format);
20441         }
set_activation_formatisa::npu_set_ofm_precision_t20442         CONSTEXPR npu_set_ofm_precision_t &set_activation_format(NPU_NAMESPACE::activation_format value)
20443         {
20444             activation_format = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20445             return *this;
20446         }
get_scale_modeisa::npu_set_ofm_precision_t20447         CONSTEXPR NPU_NAMESPACE::ofm_scale_mode get_scale_mode() const
20448         {
20449             return static_cast<NPU_NAMESPACE::ofm_scale_mode>(scale_mode);
20450         }
set_scale_modeisa::npu_set_ofm_precision_t20451         CONSTEXPR npu_set_ofm_precision_t &set_scale_mode(NPU_NAMESPACE::ofm_scale_mode value)
20452         {
20453             scale_mode = static_cast<uint8_t>(value) & ((1U << 1) - 1);
20454             return *this;
20455         }
get_round_modeisa::npu_set_ofm_precision_t20456         CONSTEXPR NPU_NAMESPACE::round_mode get_round_mode() const
20457         {
20458             return static_cast<NPU_NAMESPACE::round_mode>(round_mode);
20459         }
set_round_modeisa::npu_set_ofm_precision_t20460         CONSTEXPR npu_set_ofm_precision_t &set_round_mode(NPU_NAMESPACE::round_mode value)
20461         {
20462             round_mode = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20463             return *this;
20464         }
20465 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_precision_t20466         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20467         {
20468             fields.push_back(std::make_pair<std::string, std::string>(
20469                 "activation_type",
20470                 (activation_type < (sizeof(activation_type_str) / sizeof(activation_type_str[0])) ?
20471                      activation_type_str[activation_type] :
20472                      "****")));
20473             fields.push_back(std::make_pair<std::string, std::string>(
20474                 "activation_precision",
20475                 (activation_precision < (sizeof(activation_precision_str) / sizeof(activation_precision_str[0])) ?
20476                      activation_precision_str[activation_precision] :
20477                      "****")));
20478             fields.push_back(std::make_pair<std::string, std::string>(
20479                 "activation_format",
20480                 (activation_format < (sizeof(activation_format_str) / sizeof(activation_format_str[0])) ?
20481                      activation_format_str[activation_format] :
20482                      "****")));
20483             fields.push_back(std::make_pair<std::string, std::string>(
20484                 "scale_mode",
20485                 (scale_mode < (sizeof(ofm_scale_mode_str) / sizeof(ofm_scale_mode_str[0])) ?
20486                      ofm_scale_mode_str[scale_mode] :
20487                      "****")));
20488             fields.push_back(std::make_pair<std::string, std::string>(
20489                 "round_mode",
20490                 (round_mode < (sizeof(round_mode_str) / sizeof(round_mode_str[0])) ? round_mode_str[round_mode] :
20491                                                                                      "****")));
20492         }
20493 #endif
20494 #endif
20495     };
20496     // OFM block width
20497     struct npu_set_ofm_blk_width_m1_t
20498     {
20499 #ifdef __cplusplus
20500       private:
20501 #endif
20502         uint32_t opcode : 10; //  opcode
20503         uint32_t reserved0 : 4;
20504         uint32_t control : 2;  //  control
20505         uint32_t width_m1 : 6; //  OFM block width
20506         uint32_t reserved1 : 10;
20507 #ifdef __cplusplus
20508       public:
npu_set_ofm_blk_width_m1_tisa::npu_set_ofm_blk_width_m1_t20509         npu_set_ofm_blk_width_m1_t(uint32_t _width_m1) :
20510             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1)), reserved0(0),
20511             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 6) - 1)),
20512             reserved1(0)
20513         {
20514         }
npu_set_ofm_blk_width_m1_tisa::npu_set_ofm_blk_width_m1_t20515         CONSTEXPR npu_set_ofm_blk_width_m1_t() :
20516             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1)), reserved0(0),
20517             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0), reserved1(0)
20518         {
20519         }
validisa::npu_set_ofm_blk_width_m1_t20520         CONSTEXPR bool valid() const
20521         {
20522             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1) &&
20523                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20524         }
initisa::npu_set_ofm_blk_width_m1_t20525         CONSTEXPR void init()
20526         {
20527             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1);
20528             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20529         }
uint32_tisa::npu_set_ofm_blk_width_m1_t20530         operator uint32_t()
20531         {
20532             uint32_t word;
20533             std::memcpy(&word, this, sizeof(word));
20534             return word;
20535         }
get_opcodeisa::npu_set_ofm_blk_width_m1_t20536         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20537         {
20538             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20539         }
set_opcodeisa::npu_set_ofm_blk_width_m1_t20540         CONSTEXPR npu_set_ofm_blk_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20541         {
20542             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20543             return *this;
20544         }
get_controlisa::npu_set_ofm_blk_width_m1_t20545         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20546         {
20547             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20548         }
set_controlisa::npu_set_ofm_blk_width_m1_t20549         CONSTEXPR npu_set_ofm_blk_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20550         {
20551             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20552             return *this;
20553         }
get_width_m1isa::npu_set_ofm_blk_width_m1_t20554         CONSTEXPR uint32_t get_width_m1() const
20555         {
20556             return static_cast<uint32_t>(width_m1);
20557         }
set_width_m1isa::npu_set_ofm_blk_width_m1_t20558         CONSTEXPR npu_set_ofm_blk_width_m1_t &set_width_m1(uint32_t value)
20559         {
20560             width_m1 = static_cast<uint8_t>(value) & ((1U << 6) - 1);
20561             return *this;
20562         }
20563 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_blk_width_m1_t20564         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20565         {
20566             fields.push_back(std::make_pair<std::string, std::string>("width_m1", std::to_string(width_m1)));
20567         }
20568 #endif
20569 #endif
20570     };
20571     // OFM block height
20572     struct npu_set_ofm_blk_height_m1_t
20573     {
20574 #ifdef __cplusplus
20575       private:
20576 #endif
20577         uint32_t opcode : 10; //  opcode
20578         uint32_t reserved0 : 4;
20579         uint32_t control : 2;   //  control
20580         uint32_t height_m1 : 5; //  OFM block height
20581         uint32_t reserved1 : 11;
20582 #ifdef __cplusplus
20583       public:
npu_set_ofm_blk_height_m1_tisa::npu_set_ofm_blk_height_m1_t20584         npu_set_ofm_blk_height_m1_t(uint32_t _height_m1) :
20585             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1)), reserved0(0),
20586             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 5) - 1)),
20587             reserved1(0)
20588         {
20589         }
npu_set_ofm_blk_height_m1_tisa::npu_set_ofm_blk_height_m1_t20590         CONSTEXPR npu_set_ofm_blk_height_m1_t() :
20591             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1)), reserved0(0),
20592             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0), reserved1(0)
20593         {
20594         }
validisa::npu_set_ofm_blk_height_m1_t20595         CONSTEXPR bool valid() const
20596         {
20597             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1) &&
20598                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20599         }
initisa::npu_set_ofm_blk_height_m1_t20600         CONSTEXPR void init()
20601         {
20602             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1);
20603             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20604         }
uint32_tisa::npu_set_ofm_blk_height_m1_t20605         operator uint32_t()
20606         {
20607             uint32_t word;
20608             std::memcpy(&word, this, sizeof(word));
20609             return word;
20610         }
get_opcodeisa::npu_set_ofm_blk_height_m1_t20611         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20612         {
20613             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20614         }
set_opcodeisa::npu_set_ofm_blk_height_m1_t20615         CONSTEXPR npu_set_ofm_blk_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20616         {
20617             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20618             return *this;
20619         }
get_controlisa::npu_set_ofm_blk_height_m1_t20620         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20621         {
20622             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20623         }
set_controlisa::npu_set_ofm_blk_height_m1_t20624         CONSTEXPR npu_set_ofm_blk_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20625         {
20626             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20627             return *this;
20628         }
get_height_m1isa::npu_set_ofm_blk_height_m1_t20629         CONSTEXPR uint32_t get_height_m1() const
20630         {
20631             return static_cast<uint32_t>(height_m1);
20632         }
set_height_m1isa::npu_set_ofm_blk_height_m1_t20633         CONSTEXPR npu_set_ofm_blk_height_m1_t &set_height_m1(uint32_t value)
20634         {
20635             height_m1 = static_cast<uint8_t>(value) & ((1U << 5) - 1);
20636             return *this;
20637         }
20638 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_blk_height_m1_t20639         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20640         {
20641             fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
20642         }
20643 #endif
20644 #endif
20645     };
20646     // OFM block depth
20647     struct npu_set_ofm_blk_depth_m1_t
20648     {
20649 #ifdef __cplusplus
20650       private:
20651 #endif
20652         uint32_t opcode : 10; //  opcode
20653         uint32_t reserved0 : 4;
20654         uint32_t control : 2;  //  control
20655         uint32_t depth_m1 : 7; //  OFM block depth
20656         uint32_t reserved1 : 9;
20657 #ifdef __cplusplus
20658       public:
npu_set_ofm_blk_depth_m1_tisa::npu_set_ofm_blk_depth_m1_t20659         npu_set_ofm_blk_depth_m1_t(uint32_t _depth_m1) :
20660             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1)), reserved0(0),
20661             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 7) - 1)),
20662             reserved1(0)
20663         {
20664         }
npu_set_ofm_blk_depth_m1_tisa::npu_set_ofm_blk_depth_m1_t20665         CONSTEXPR npu_set_ofm_blk_depth_m1_t() :
20666             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1)), reserved0(0),
20667             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0), reserved1(0)
20668         {
20669         }
validisa::npu_set_ofm_blk_depth_m1_t20670         CONSTEXPR bool valid() const
20671         {
20672             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1) &&
20673                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20674         }
initisa::npu_set_ofm_blk_depth_m1_t20675         CONSTEXPR void init()
20676         {
20677             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1);
20678             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20679         }
uint32_tisa::npu_set_ofm_blk_depth_m1_t20680         operator uint32_t()
20681         {
20682             uint32_t word;
20683             std::memcpy(&word, this, sizeof(word));
20684             return word;
20685         }
get_opcodeisa::npu_set_ofm_blk_depth_m1_t20686         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20687         {
20688             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20689         }
set_opcodeisa::npu_set_ofm_blk_depth_m1_t20690         CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20691         {
20692             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20693             return *this;
20694         }
get_controlisa::npu_set_ofm_blk_depth_m1_t20695         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20696         {
20697             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20698         }
set_controlisa::npu_set_ofm_blk_depth_m1_t20699         CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20700         {
20701             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20702             return *this;
20703         }
get_depth_m1isa::npu_set_ofm_blk_depth_m1_t20704         CONSTEXPR uint32_t get_depth_m1() const
20705         {
20706             return static_cast<uint32_t>(depth_m1);
20707         }
set_depth_m1isa::npu_set_ofm_blk_depth_m1_t20708         CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_depth_m1(uint32_t value)
20709         {
20710             depth_m1 = static_cast<uint8_t>(value) & ((1U << 7) - 1);
20711             return *this;
20712         }
20713 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_blk_depth_m1_t20714         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20715         {
20716             fields.push_back(std::make_pair<std::string, std::string>("depth_m1", std::to_string(depth_m1)));
20717         }
20718 #endif
20719 #endif
20720     };
20721     // OFM zero point
20722     struct npu_set_ofm_zero_point_t
20723     {
20724 #ifdef __cplusplus
20725       private:
20726 #endif
20727         uint32_t opcode : 10; //  opcode
20728         uint32_t reserved0 : 4;
20729         uint32_t control : 2;     //  control
20730         uint32_t zero_point : 16; //  Zero point offset
20731 #ifdef __cplusplus
20732       public:
npu_set_ofm_zero_point_tisa::npu_set_ofm_zero_point_t20733         npu_set_ofm_zero_point_t(uint32_t _zero_point) :
20734             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT)), reserved0(0),
20735             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
20736             zero_point(_zero_point & ((1U << 16) - 1))
20737         {
20738         }
npu_set_ofm_zero_point_tisa::npu_set_ofm_zero_point_t20739         CONSTEXPR npu_set_ofm_zero_point_t() :
20740             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT)), reserved0(0),
20741             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), zero_point(0)
20742         {
20743         }
validisa::npu_set_ofm_zero_point_t20744         CONSTEXPR bool valid() const
20745         {
20746             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT) &&
20747                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20748         }
initisa::npu_set_ofm_zero_point_t20749         CONSTEXPR void init()
20750         {
20751             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT);
20752             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20753         }
uint32_tisa::npu_set_ofm_zero_point_t20754         operator uint32_t()
20755         {
20756             uint32_t word;
20757             std::memcpy(&word, this, sizeof(word));
20758             return word;
20759         }
get_opcodeisa::npu_set_ofm_zero_point_t20760         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20761         {
20762             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20763         }
set_opcodeisa::npu_set_ofm_zero_point_t20764         CONSTEXPR npu_set_ofm_zero_point_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20765         {
20766             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20767             return *this;
20768         }
get_controlisa::npu_set_ofm_zero_point_t20769         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20770         {
20771             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20772         }
set_controlisa::npu_set_ofm_zero_point_t20773         CONSTEXPR npu_set_ofm_zero_point_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20774         {
20775             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20776             return *this;
20777         }
get_zero_pointisa::npu_set_ofm_zero_point_t20778         CONSTEXPR uint32_t get_zero_point() const
20779         {
20780             return static_cast<uint32_t>(zero_point);
20781         }
set_zero_pointisa::npu_set_ofm_zero_point_t20782         CONSTEXPR npu_set_ofm_zero_point_t &set_zero_point(uint32_t value)
20783         {
20784             zero_point = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20785             return *this;
20786         }
20787 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_zero_point_t20788         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20789         {
20790             fields.push_back(std::make_pair<std::string, std::string>("zero_point", std::to_string(zero_point)));
20791         }
20792 #endif
20793 #endif
20794     };
20795     // OFM Tile 0 and tile 2 width
20796     struct npu_set_ofm_width0_m1_t
20797     {
20798 #ifdef __cplusplus
20799       private:
20800 #endif
20801         uint32_t opcode : 10; //  opcode
20802         uint32_t reserved0 : 4;
20803         uint32_t control : 2;   //  control
20804         uint32_t width_m1 : 16; //  OFM Tile 0 and tile 2 width
20805 #ifdef __cplusplus
20806       public:
npu_set_ofm_width0_m1_tisa::npu_set_ofm_width0_m1_t20807         npu_set_ofm_width0_m1_t(uint32_t _width_m1) :
20808             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1)), reserved0(0),
20809             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
20810         {
20811         }
npu_set_ofm_width0_m1_tisa::npu_set_ofm_width0_m1_t20812         CONSTEXPR npu_set_ofm_width0_m1_t() :
20813             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1)), reserved0(0),
20814             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0)
20815         {
20816         }
validisa::npu_set_ofm_width0_m1_t20817         CONSTEXPR bool valid() const
20818         {
20819             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1) &&
20820                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20821         }
initisa::npu_set_ofm_width0_m1_t20822         CONSTEXPR void init()
20823         {
20824             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1);
20825             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20826         }
uint32_tisa::npu_set_ofm_width0_m1_t20827         operator uint32_t()
20828         {
20829             uint32_t word;
20830             std::memcpy(&word, this, sizeof(word));
20831             return word;
20832         }
get_opcodeisa::npu_set_ofm_width0_m1_t20833         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20834         {
20835             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20836         }
set_opcodeisa::npu_set_ofm_width0_m1_t20837         CONSTEXPR npu_set_ofm_width0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20838         {
20839             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20840             return *this;
20841         }
get_controlisa::npu_set_ofm_width0_m1_t20842         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20843         {
20844             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20845         }
set_controlisa::npu_set_ofm_width0_m1_t20846         CONSTEXPR npu_set_ofm_width0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20847         {
20848             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20849             return *this;
20850         }
get_width_m1isa::npu_set_ofm_width0_m1_t20851         CONSTEXPR uint32_t get_width_m1() const
20852         {
20853             return static_cast<uint32_t>(width_m1);
20854         }
set_width_m1isa::npu_set_ofm_width0_m1_t20855         CONSTEXPR npu_set_ofm_width0_m1_t &set_width_m1(uint32_t value)
20856         {
20857             width_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20858             return *this;
20859         }
20860 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_width0_m1_t20861         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20862         {
20863             fields.push_back(std::make_pair<std::string, std::string>("width_m1", std::to_string(width_m1)));
20864         }
20865 #endif
20866 #endif
20867     };
20868     // OFM Tile 0 height
20869     struct npu_set_ofm_height0_m1_t
20870     {
20871 #ifdef __cplusplus
20872       private:
20873 #endif
20874         uint32_t opcode : 10; //  opcode
20875         uint32_t reserved0 : 4;
20876         uint32_t control : 2;    //  control
20877         uint32_t height_m1 : 16; //  OFM Tile 0 height
20878 #ifdef __cplusplus
20879       public:
npu_set_ofm_height0_m1_tisa::npu_set_ofm_height0_m1_t20880         npu_set_ofm_height0_m1_t(uint32_t _height_m1) :
20881             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1)), reserved0(0),
20882             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
20883         {
20884         }
npu_set_ofm_height0_m1_tisa::npu_set_ofm_height0_m1_t20885         CONSTEXPR npu_set_ofm_height0_m1_t() :
20886             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1)), reserved0(0),
20887             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
20888         {
20889         }
validisa::npu_set_ofm_height0_m1_t20890         CONSTEXPR bool valid() const
20891         {
20892             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1) &&
20893                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20894         }
initisa::npu_set_ofm_height0_m1_t20895         CONSTEXPR void init()
20896         {
20897             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1);
20898             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20899         }
uint32_tisa::npu_set_ofm_height0_m1_t20900         operator uint32_t()
20901         {
20902             uint32_t word;
20903             std::memcpy(&word, this, sizeof(word));
20904             return word;
20905         }
get_opcodeisa::npu_set_ofm_height0_m1_t20906         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20907         {
20908             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20909         }
set_opcodeisa::npu_set_ofm_height0_m1_t20910         CONSTEXPR npu_set_ofm_height0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20911         {
20912             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20913             return *this;
20914         }
get_controlisa::npu_set_ofm_height0_m1_t20915         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20916         {
20917             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20918         }
set_controlisa::npu_set_ofm_height0_m1_t20919         CONSTEXPR npu_set_ofm_height0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20920         {
20921             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20922             return *this;
20923         }
get_height_m1isa::npu_set_ofm_height0_m1_t20924         CONSTEXPR uint32_t get_height_m1() const
20925         {
20926             return static_cast<uint32_t>(height_m1);
20927         }
set_height_m1isa::npu_set_ofm_height0_m1_t20928         CONSTEXPR npu_set_ofm_height0_m1_t &set_height_m1(uint32_t value)
20929         {
20930             height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20931             return *this;
20932         }
20933 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_height0_m1_t20934         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20935         {
20936             fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
20937         }
20938 #endif
20939 #endif
20940     };
20941     // OFM Tile 1 height
20942     struct npu_set_ofm_height1_m1_t
20943     {
20944 #ifdef __cplusplus
20945       private:
20946 #endif
20947         uint32_t opcode : 10; //  opcode
20948         uint32_t reserved0 : 4;
20949         uint32_t control : 2;    //  control
20950         uint32_t height_m1 : 16; //  OFM Tile 1 height
20951 #ifdef __cplusplus
20952       public:
npu_set_ofm_height1_m1_tisa::npu_set_ofm_height1_m1_t20953         npu_set_ofm_height1_m1_t(uint32_t _height_m1) :
20954             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1)), reserved0(0),
20955             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
20956         {
20957         }
npu_set_ofm_height1_m1_tisa::npu_set_ofm_height1_m1_t20958         CONSTEXPR npu_set_ofm_height1_m1_t() :
20959             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1)), reserved0(0),
20960             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
20961         {
20962         }
validisa::npu_set_ofm_height1_m1_t20963         CONSTEXPR bool valid() const
20964         {
20965             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1) &&
20966                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20967         }
initisa::npu_set_ofm_height1_m1_t20968         CONSTEXPR void init()
20969         {
20970             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1);
20971             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20972         }
uint32_tisa::npu_set_ofm_height1_m1_t20973         operator uint32_t()
20974         {
20975             uint32_t word;
20976             std::memcpy(&word, this, sizeof(word));
20977             return word;
20978         }
get_opcodeisa::npu_set_ofm_height1_m1_t20979         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20980         {
20981             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20982         }
set_opcodeisa::npu_set_ofm_height1_m1_t20983         CONSTEXPR npu_set_ofm_height1_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20984         {
20985             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20986             return *this;
20987         }
get_controlisa::npu_set_ofm_height1_m1_t20988         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20989         {
20990             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20991         }
set_controlisa::npu_set_ofm_height1_m1_t20992         CONSTEXPR npu_set_ofm_height1_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20993         {
20994             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20995             return *this;
20996         }
get_height_m1isa::npu_set_ofm_height1_m1_t20997         CONSTEXPR uint32_t get_height_m1() const
20998         {
20999             return static_cast<uint32_t>(height_m1);
21000         }
set_height_m1isa::npu_set_ofm_height1_m1_t21001         CONSTEXPR npu_set_ofm_height1_m1_t &set_height_m1(uint32_t value)
21002         {
21003             height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
21004             return *this;
21005         }
21006 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_height1_m1_t21007         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21008         {
21009             fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
21010         }
21011 #endif
21012 #endif
21013     };
21014     // Index n for OFM access
21015     struct npu_set_ofm_region_t
21016     {
21017 #ifdef __cplusplus
21018       private:
21019 #endif
21020         uint32_t opcode : 10; //  opcode
21021         uint32_t reserved0 : 4;
21022         uint32_t control : 2; //  control
21023         uint32_t region : 3;  //  Index n for OFM access
21024         uint32_t reserved1 : 13;
21025 #ifdef __cplusplus
21026       public:
npu_set_ofm_region_tisa::npu_set_ofm_region_t21027         npu_set_ofm_region_t(uint32_t _region) :
21028             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION)), reserved0(0),
21029             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
21030             reserved1(0)
21031         {
21032         }
npu_set_ofm_region_tisa::npu_set_ofm_region_t21033         CONSTEXPR npu_set_ofm_region_t() :
21034             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION)), reserved0(0),
21035             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
21036         {
21037         }
validisa::npu_set_ofm_region_t21038         CONSTEXPR bool valid() const
21039         {
21040             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION) &&
21041                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21042         }
initisa::npu_set_ofm_region_t21043         CONSTEXPR void init()
21044         {
21045             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION);
21046             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21047         }
uint32_tisa::npu_set_ofm_region_t21048         operator uint32_t()
21049         {
21050             uint32_t word;
21051             std::memcpy(&word, this, sizeof(word));
21052             return word;
21053         }
get_opcodeisa::npu_set_ofm_region_t21054         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21055         {
21056             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21057         }
set_opcodeisa::npu_set_ofm_region_t21058         CONSTEXPR npu_set_ofm_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21059         {
21060             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21061             return *this;
21062         }
get_controlisa::npu_set_ofm_region_t21063         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21064         {
21065             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21066         }
set_controlisa::npu_set_ofm_region_t21067         CONSTEXPR npu_set_ofm_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21068         {
21069             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21070             return *this;
21071         }
get_regionisa::npu_set_ofm_region_t21072         CONSTEXPR uint32_t get_region() const
21073         {
21074             return static_cast<uint32_t>(region);
21075         }
set_regionisa::npu_set_ofm_region_t21076         CONSTEXPR npu_set_ofm_region_t &set_region(uint32_t value)
21077         {
21078             region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
21079             return *this;
21080         }
21081 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ofm_region_t21082         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21083         {
21084             fields.push_back(std::make_pair<std::string, std::string>("region", std::to_string(region)));
21085         }
21086 #endif
21087 #endif
21088     };
21089     // Kernel width
21090     struct npu_set_kernel_width_m1_t
21091     {
21092 #ifdef __cplusplus
21093       private:
21094 #endif
21095         uint32_t opcode : 10; //  opcode
21096         uint32_t reserved0 : 4;
21097         uint32_t control : 2;   //  control
21098         uint32_t width_m1 : 16; //  Kernel width
21099 #ifdef __cplusplus
21100       public:
npu_set_kernel_width_m1_tisa::npu_set_kernel_width_m1_t21101         npu_set_kernel_width_m1_t(uint32_t _width_m1) :
21102             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1)), reserved0(0),
21103             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
21104         {
21105         }
npu_set_kernel_width_m1_tisa::npu_set_kernel_width_m1_t21106         CONSTEXPR npu_set_kernel_width_m1_t() :
21107             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1)), reserved0(0),
21108             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0)
21109         {
21110         }
validisa::npu_set_kernel_width_m1_t21111         CONSTEXPR bool valid() const
21112         {
21113             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1) &&
21114                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21115         }
initisa::npu_set_kernel_width_m1_t21116         CONSTEXPR void init()
21117         {
21118             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1);
21119             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21120         }
uint32_tisa::npu_set_kernel_width_m1_t21121         operator uint32_t()
21122         {
21123             uint32_t word;
21124             std::memcpy(&word, this, sizeof(word));
21125             return word;
21126         }
get_opcodeisa::npu_set_kernel_width_m1_t21127         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21128         {
21129             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21130         }
set_opcodeisa::npu_set_kernel_width_m1_t21131         CONSTEXPR npu_set_kernel_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21132         {
21133             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21134             return *this;
21135         }
get_controlisa::npu_set_kernel_width_m1_t21136         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21137         {
21138             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21139         }
set_controlisa::npu_set_kernel_width_m1_t21140         CONSTEXPR npu_set_kernel_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21141         {
21142             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21143             return *this;
21144         }
get_width_m1isa::npu_set_kernel_width_m1_t21145         CONSTEXPR uint32_t get_width_m1() const
21146         {
21147             return static_cast<uint32_t>(width_m1);
21148         }
set_width_m1isa::npu_set_kernel_width_m1_t21149         CONSTEXPR npu_set_kernel_width_m1_t &set_width_m1(uint32_t value)
21150         {
21151             width_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
21152             return *this;
21153         }
21154 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_kernel_width_m1_t21155         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21156         {
21157             fields.push_back(std::make_pair<std::string, std::string>("width_m1", std::to_string(width_m1)));
21158         }
21159 #endif
21160 #endif
21161     };
21162     // Kernel height
21163     struct npu_set_kernel_height_m1_t
21164     {
21165 #ifdef __cplusplus
21166       private:
21167 #endif
21168         uint32_t opcode : 10; //  opcode
21169         uint32_t reserved0 : 4;
21170         uint32_t control : 2;    //  control
21171         uint32_t height_m1 : 16; //  Kernel height
21172 #ifdef __cplusplus
21173       public:
npu_set_kernel_height_m1_tisa::npu_set_kernel_height_m1_t21174         npu_set_kernel_height_m1_t(uint32_t _height_m1) :
21175             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1)), reserved0(0),
21176             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
21177         {
21178         }
npu_set_kernel_height_m1_tisa::npu_set_kernel_height_m1_t21179         CONSTEXPR npu_set_kernel_height_m1_t() :
21180             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1)), reserved0(0),
21181             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
21182         {
21183         }
validisa::npu_set_kernel_height_m1_t21184         CONSTEXPR bool valid() const
21185         {
21186             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1) &&
21187                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21188         }
initisa::npu_set_kernel_height_m1_t21189         CONSTEXPR void init()
21190         {
21191             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1);
21192             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21193         }
uint32_tisa::npu_set_kernel_height_m1_t21194         operator uint32_t()
21195         {
21196             uint32_t word;
21197             std::memcpy(&word, this, sizeof(word));
21198             return word;
21199         }
get_opcodeisa::npu_set_kernel_height_m1_t21200         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21201         {
21202             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21203         }
set_opcodeisa::npu_set_kernel_height_m1_t21204         CONSTEXPR npu_set_kernel_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21205         {
21206             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21207             return *this;
21208         }
get_controlisa::npu_set_kernel_height_m1_t21209         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21210         {
21211             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21212         }
set_controlisa::npu_set_kernel_height_m1_t21213         CONSTEXPR npu_set_kernel_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21214         {
21215             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21216             return *this;
21217         }
get_height_m1isa::npu_set_kernel_height_m1_t21218         CONSTEXPR uint32_t get_height_m1() const
21219         {
21220             return static_cast<uint32_t>(height_m1);
21221         }
set_height_m1isa::npu_set_kernel_height_m1_t21222         CONSTEXPR npu_set_kernel_height_m1_t &set_height_m1(uint32_t value)
21223         {
21224             height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
21225             return *this;
21226         }
21227 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_kernel_height_m1_t21228         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21229         {
21230             fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
21231         }
21232 #endif
21233 #endif
21234     };
21235     // Kernel stride
21236     struct npu_set_kernel_stride_t
21237     {
21238 #ifdef __cplusplus
21239       private:
21240 #endif
21241         uint32_t opcode : 10; //  opcode
21242         uint32_t reserved0 : 4;
21243         uint32_t control : 2;       //  control
21244         uint32_t stride_x_lsb : 1;  //  Stride x LSB. (kernel_x_stride - 1)[0]
21245         uint32_t stride_y_lsb : 1;  //  Stride y LSB. (kernel_y_stride - 1)[0]
21246         uint32_t weight_order : 1;  //  Weight ordering mode
21247         uint32_t dilation_x : 1;    //  Kernel x dilation
21248         uint32_t dilation_y : 1;    //  Kernel y dilation
21249         uint32_t decomposition : 1; //  Kernel decomposition
21250         uint32_t stride_x_msb : 1;  //  Stride x MSB. (kernel_x_stride - 1) >> 1
21251         uint32_t reserved1 : 2;
21252         uint32_t stride_y_msb : 1; //  Stride y MSB. (kernel_y_stride - 1) >> 1
21253         uint32_t reserved2 : 6;
21254 #ifdef __cplusplus
21255       public:
npu_set_kernel_stride_tisa::npu_set_kernel_stride_t21256         npu_set_kernel_stride_t(uint32_t _stride_x_lsb,
21257                                 uint32_t _stride_y_lsb,
21258                                 NPU_NAMESPACE::weight_order _weight_order,
21259                                 NPU_NAMESPACE::kernel_dilation _dilation_x,
21260                                 NPU_NAMESPACE::kernel_dilation _dilation_y,
21261                                 NPU_NAMESPACE::kernel_decomposition _decomposition,
21262                                 uint32_t _stride_x_msb,
21263                                 uint32_t _stride_y_msb) :
21264             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE)),
21265             reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21266             stride_x_lsb(_stride_x_lsb & ((1U << 1) - 1)), stride_y_lsb(_stride_y_lsb & ((1U << 1) - 1)),
21267             weight_order(static_cast<uint8_t>(_weight_order) & ((1U << 1) - 1)),
21268             dilation_x(static_cast<uint8_t>(_dilation_x) & ((1U << 1) - 1)),
21269             dilation_y(static_cast<uint8_t>(_dilation_y) & ((1U << 1) - 1)),
21270             decomposition(static_cast<uint8_t>(_decomposition) & ((1U << 1) - 1)),
21271             stride_x_msb(_stride_x_msb & ((1U << 1) - 1)), reserved1(0), stride_y_msb(_stride_y_msb & ((1U << 1) - 1)),
21272             reserved2(0)
21273         {
21274         }
npu_set_kernel_stride_tisa::npu_set_kernel_stride_t21275         CONSTEXPR npu_set_kernel_stride_t() :
21276             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE)), reserved0(0),
21277             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), stride_x_lsb(0), stride_y_lsb(0),
21278             weight_order(0), dilation_x(0), dilation_y(0), decomposition(0), stride_x_msb(0), reserved1(0),
21279             stride_y_msb(0), reserved2(0)
21280         {
21281         }
validisa::npu_set_kernel_stride_t21282         CONSTEXPR bool valid() const
21283         {
21284             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE) &&
21285                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21286         }
initisa::npu_set_kernel_stride_t21287         CONSTEXPR void init()
21288         {
21289             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE);
21290             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21291         }
uint32_tisa::npu_set_kernel_stride_t21292         operator uint32_t()
21293         {
21294             uint32_t word;
21295             std::memcpy(&word, this, sizeof(word));
21296             return word;
21297         }
get_opcodeisa::npu_set_kernel_stride_t21298         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21299         {
21300             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21301         }
set_opcodeisa::npu_set_kernel_stride_t21302         CONSTEXPR npu_set_kernel_stride_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21303         {
21304             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21305             return *this;
21306         }
get_controlisa::npu_set_kernel_stride_t21307         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21308         {
21309             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21310         }
set_controlisa::npu_set_kernel_stride_t21311         CONSTEXPR npu_set_kernel_stride_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21312         {
21313             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21314             return *this;
21315         }
get_stride_x_lsbisa::npu_set_kernel_stride_t21316         CONSTEXPR uint32_t get_stride_x_lsb() const
21317         {
21318             return static_cast<uint32_t>(stride_x_lsb);
21319         }
set_stride_x_lsbisa::npu_set_kernel_stride_t21320         CONSTEXPR npu_set_kernel_stride_t &set_stride_x_lsb(uint32_t value)
21321         {
21322             stride_x_lsb = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21323             return *this;
21324         }
get_stride_y_lsbisa::npu_set_kernel_stride_t21325         CONSTEXPR uint32_t get_stride_y_lsb() const
21326         {
21327             return static_cast<uint32_t>(stride_y_lsb);
21328         }
set_stride_y_lsbisa::npu_set_kernel_stride_t21329         CONSTEXPR npu_set_kernel_stride_t &set_stride_y_lsb(uint32_t value)
21330         {
21331             stride_y_lsb = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21332             return *this;
21333         }
get_weight_orderisa::npu_set_kernel_stride_t21334         CONSTEXPR NPU_NAMESPACE::weight_order get_weight_order() const
21335         {
21336             return static_cast<NPU_NAMESPACE::weight_order>(weight_order);
21337         }
set_weight_orderisa::npu_set_kernel_stride_t21338         CONSTEXPR npu_set_kernel_stride_t &set_weight_order(NPU_NAMESPACE::weight_order value)
21339         {
21340             weight_order = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21341             return *this;
21342         }
get_dilation_xisa::npu_set_kernel_stride_t21343         CONSTEXPR NPU_NAMESPACE::kernel_dilation get_dilation_x() const
21344         {
21345             return static_cast<NPU_NAMESPACE::kernel_dilation>(dilation_x);
21346         }
set_dilation_xisa::npu_set_kernel_stride_t21347         CONSTEXPR npu_set_kernel_stride_t &set_dilation_x(NPU_NAMESPACE::kernel_dilation value)
21348         {
21349             dilation_x = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21350             return *this;
21351         }
get_dilation_yisa::npu_set_kernel_stride_t21352         CONSTEXPR NPU_NAMESPACE::kernel_dilation get_dilation_y() const
21353         {
21354             return static_cast<NPU_NAMESPACE::kernel_dilation>(dilation_y);
21355         }
set_dilation_yisa::npu_set_kernel_stride_t21356         CONSTEXPR npu_set_kernel_stride_t &set_dilation_y(NPU_NAMESPACE::kernel_dilation value)
21357         {
21358             dilation_y = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21359             return *this;
21360         }
get_decompositionisa::npu_set_kernel_stride_t21361         CONSTEXPR NPU_NAMESPACE::kernel_decomposition get_decomposition() const
21362         {
21363             return static_cast<NPU_NAMESPACE::kernel_decomposition>(decomposition);
21364         }
set_decompositionisa::npu_set_kernel_stride_t21365         CONSTEXPR npu_set_kernel_stride_t &set_decomposition(NPU_NAMESPACE::kernel_decomposition value)
21366         {
21367             decomposition = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21368             return *this;
21369         }
get_stride_x_msbisa::npu_set_kernel_stride_t21370         CONSTEXPR uint32_t get_stride_x_msb() const
21371         {
21372             return static_cast<uint32_t>(stride_x_msb);
21373         }
set_stride_x_msbisa::npu_set_kernel_stride_t21374         CONSTEXPR npu_set_kernel_stride_t &set_stride_x_msb(uint32_t value)
21375         {
21376             stride_x_msb = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21377             return *this;
21378         }
get_stride_y_msbisa::npu_set_kernel_stride_t21379         CONSTEXPR uint32_t get_stride_y_msb() const
21380         {
21381             return static_cast<uint32_t>(stride_y_msb);
21382         }
set_stride_y_msbisa::npu_set_kernel_stride_t21383         CONSTEXPR npu_set_kernel_stride_t &set_stride_y_msb(uint32_t value)
21384         {
21385             stride_y_msb = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21386             return *this;
21387         }
21388 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_kernel_stride_t21389         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21390         {
21391             fields.push_back(std::make_pair<std::string, std::string>("stride_x_lsb", std::to_string(stride_x_lsb)));
21392             fields.push_back(std::make_pair<std::string, std::string>("stride_y_lsb", std::to_string(stride_y_lsb)));
21393             fields.push_back(std::make_pair<std::string, std::string>(
21394                 "weight_order",
21395                 (weight_order < (sizeof(weight_order_str) / sizeof(weight_order_str[0])) ?
21396                      weight_order_str[weight_order] :
21397                      "****")));
21398             fields.push_back(std::make_pair<std::string, std::string>(
21399                 "dilation_x",
21400                 (dilation_x < (sizeof(kernel_dilation_str) / sizeof(kernel_dilation_str[0])) ?
21401                      kernel_dilation_str[dilation_x] :
21402                      "****")));
21403             fields.push_back(std::make_pair<std::string, std::string>(
21404                 "dilation_y",
21405                 (dilation_y < (sizeof(kernel_dilation_str) / sizeof(kernel_dilation_str[0])) ?
21406                      kernel_dilation_str[dilation_y] :
21407                      "****")));
21408             fields.push_back(std::make_pair<std::string, std::string>(
21409                 "decomposition",
21410                 (decomposition < (sizeof(kernel_decomposition_str) / sizeof(kernel_decomposition_str[0])) ?
21411                      kernel_decomposition_str[decomposition] :
21412                      "****")));
21413             fields.push_back(std::make_pair<std::string, std::string>("stride_x_msb", std::to_string(stride_x_msb)));
21414             fields.push_back(std::make_pair<std::string, std::string>("stride_y_msb", std::to_string(stride_y_msb)));
21415         }
21416 #endif
21417 #endif
21418     };
21419     // Multi-core parallel mode
21420     struct npu_set_parallel_mode_t
21421     {
21422 #ifdef __cplusplus
21423       private:
21424 #endif
21425         uint32_t opcode : 10; //  opcode
21426         uint32_t reserved0 : 4;
21427         uint32_t control : 2;       //  control
21428         uint32_t parallel_mode : 1; //  Multi-core parallel mode
21429         uint32_t reserved1 : 15;
21430 #ifdef __cplusplus
21431       public:
npu_set_parallel_mode_tisa::npu_set_parallel_mode_t21432         npu_set_parallel_mode_t(NPU_NAMESPACE::parallel_mode _parallel_mode) :
21433             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE)), reserved0(0),
21434             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21435             parallel_mode(static_cast<uint8_t>(_parallel_mode) & ((1U << 1) - 1)), reserved1(0)
21436         {
21437         }
npu_set_parallel_mode_tisa::npu_set_parallel_mode_t21438         CONSTEXPR npu_set_parallel_mode_t() :
21439             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE)), reserved0(0),
21440             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), parallel_mode(0), reserved1(0)
21441         {
21442         }
validisa::npu_set_parallel_mode_t21443         CONSTEXPR bool valid() const
21444         {
21445             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE) &&
21446                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21447         }
initisa::npu_set_parallel_mode_t21448         CONSTEXPR void init()
21449         {
21450             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE);
21451             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21452         }
uint32_tisa::npu_set_parallel_mode_t21453         operator uint32_t()
21454         {
21455             uint32_t word;
21456             std::memcpy(&word, this, sizeof(word));
21457             return word;
21458         }
get_opcodeisa::npu_set_parallel_mode_t21459         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21460         {
21461             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21462         }
set_opcodeisa::npu_set_parallel_mode_t21463         CONSTEXPR npu_set_parallel_mode_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21464         {
21465             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21466             return *this;
21467         }
get_controlisa::npu_set_parallel_mode_t21468         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21469         {
21470             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21471         }
set_controlisa::npu_set_parallel_mode_t21472         CONSTEXPR npu_set_parallel_mode_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21473         {
21474             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21475             return *this;
21476         }
get_parallel_modeisa::npu_set_parallel_mode_t21477         CONSTEXPR NPU_NAMESPACE::parallel_mode get_parallel_mode() const
21478         {
21479             return static_cast<NPU_NAMESPACE::parallel_mode>(parallel_mode);
21480         }
set_parallel_modeisa::npu_set_parallel_mode_t21481         CONSTEXPR npu_set_parallel_mode_t &set_parallel_mode(NPU_NAMESPACE::parallel_mode value)
21482         {
21483             parallel_mode = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21484             return *this;
21485         }
21486 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_parallel_mode_t21487         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21488         {
21489             fields.push_back(std::make_pair<std::string, std::string>(
21490                 "parallel_mode",
21491                 (parallel_mode < (sizeof(parallel_mode_str) / sizeof(parallel_mode_str[0])) ?
21492                      parallel_mode_str[parallel_mode] :
21493                      "****")));
21494         }
21495 #endif
21496 #endif
21497     };
21498     // Accumulator format
21499     struct npu_set_acc_format_t
21500     {
21501 #ifdef __cplusplus
21502       private:
21503 #endif
21504         uint32_t opcode : 10; //  opcode
21505         uint32_t reserved0 : 4;
21506         uint32_t control : 2;    //  control
21507         uint32_t acc_format : 2; //  Accumulator format
21508         uint32_t reserved1 : 14;
21509 #ifdef __cplusplus
21510       public:
npu_set_acc_format_tisa::npu_set_acc_format_t21511         npu_set_acc_format_t(NPU_NAMESPACE::acc_format _acc_format) :
21512             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT)), reserved0(0),
21513             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21514             acc_format(static_cast<uint8_t>(_acc_format) & ((1U << 2) - 1)), reserved1(0)
21515         {
21516         }
npu_set_acc_format_tisa::npu_set_acc_format_t21517         CONSTEXPR npu_set_acc_format_t() :
21518             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT)), reserved0(0),
21519             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), acc_format(0), reserved1(0)
21520         {
21521         }
validisa::npu_set_acc_format_t21522         CONSTEXPR bool valid() const
21523         {
21524             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT) &&
21525                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21526         }
initisa::npu_set_acc_format_t21527         CONSTEXPR void init()
21528         {
21529             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT);
21530             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21531         }
uint32_tisa::npu_set_acc_format_t21532         operator uint32_t()
21533         {
21534             uint32_t word;
21535             std::memcpy(&word, this, sizeof(word));
21536             return word;
21537         }
get_opcodeisa::npu_set_acc_format_t21538         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21539         {
21540             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21541         }
set_opcodeisa::npu_set_acc_format_t21542         CONSTEXPR npu_set_acc_format_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21543         {
21544             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21545             return *this;
21546         }
get_controlisa::npu_set_acc_format_t21547         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21548         {
21549             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21550         }
set_controlisa::npu_set_acc_format_t21551         CONSTEXPR npu_set_acc_format_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21552         {
21553             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21554             return *this;
21555         }
get_acc_formatisa::npu_set_acc_format_t21556         CONSTEXPR NPU_NAMESPACE::acc_format get_acc_format() const
21557         {
21558             return static_cast<NPU_NAMESPACE::acc_format>(acc_format);
21559         }
set_acc_formatisa::npu_set_acc_format_t21560         CONSTEXPR npu_set_acc_format_t &set_acc_format(NPU_NAMESPACE::acc_format value)
21561         {
21562             acc_format = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21563             return *this;
21564         }
21565 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_acc_format_t21566         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21567         {
21568             fields.push_back(std::make_pair<std::string, std::string>(
21569                 "acc_format",
21570                 (acc_format < (sizeof(acc_format_str) / sizeof(acc_format_str[0])) ? acc_format_str[acc_format] :
21571                                                                                      "****")));
21572         }
21573 #endif
21574 #endif
21575     };
21576     // Activation function and clip range
21577     struct npu_set_activation_t
21578     {
21579 #ifdef __cplusplus
21580       private:
21581 #endif
21582         uint32_t opcode : 10; //  opcode
21583         uint32_t reserved0 : 4;
21584         uint32_t control : 2;             //  control
21585         uint32_t activation_function : 5; //  Activation function (before table lookup)
21586         uint32_t reserved1 : 7;
21587         uint32_t activation_clip_range : 3; //  Activation clip range. This must be set to 0 if table lookup is not used
21588         uint32_t reserved2 : 1;
21589 #ifdef __cplusplus
21590       public:
npu_set_activation_tisa::npu_set_activation_t21591         npu_set_activation_t(NPU_NAMESPACE::activation_function _activation_function,
21592                              NPU_NAMESPACE::activation_clip_range _activation_clip_range) :
21593             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION)),
21594             reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21595             activation_function(static_cast<uint8_t>(_activation_function) & ((1U << 5) - 1)), reserved1(0),
21596             activation_clip_range(static_cast<uint8_t>(_activation_clip_range) & ((1U << 3) - 1)), reserved2(0)
21597         {
21598         }
npu_set_activation_tisa::npu_set_activation_t21599         CONSTEXPR npu_set_activation_t() :
21600             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION)), reserved0(0),
21601             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_function(0), reserved1(0),
21602             activation_clip_range(0), reserved2(0)
21603         {
21604         }
validisa::npu_set_activation_t21605         CONSTEXPR bool valid() const
21606         {
21607             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION) &&
21608                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21609         }
initisa::npu_set_activation_t21610         CONSTEXPR void init()
21611         {
21612             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION);
21613             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21614         }
uint32_tisa::npu_set_activation_t21615         operator uint32_t()
21616         {
21617             uint32_t word;
21618             std::memcpy(&word, this, sizeof(word));
21619             return word;
21620         }
get_opcodeisa::npu_set_activation_t21621         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21622         {
21623             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21624         }
set_opcodeisa::npu_set_activation_t21625         CONSTEXPR npu_set_activation_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21626         {
21627             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21628             return *this;
21629         }
get_controlisa::npu_set_activation_t21630         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21631         {
21632             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21633         }
set_controlisa::npu_set_activation_t21634         CONSTEXPR npu_set_activation_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21635         {
21636             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21637             return *this;
21638         }
get_activation_functionisa::npu_set_activation_t21639         CONSTEXPR NPU_NAMESPACE::activation_function get_activation_function() const
21640         {
21641             return static_cast<NPU_NAMESPACE::activation_function>(activation_function);
21642         }
set_activation_functionisa::npu_set_activation_t21643         CONSTEXPR npu_set_activation_t &set_activation_function(NPU_NAMESPACE::activation_function value)
21644         {
21645             activation_function = static_cast<uint8_t>(value) & ((1U << 5) - 1);
21646             return *this;
21647         }
get_activation_clip_rangeisa::npu_set_activation_t21648         CONSTEXPR NPU_NAMESPACE::activation_clip_range get_activation_clip_range() const
21649         {
21650             return static_cast<NPU_NAMESPACE::activation_clip_range>(activation_clip_range);
21651         }
set_activation_clip_rangeisa::npu_set_activation_t21652         CONSTEXPR npu_set_activation_t &set_activation_clip_range(NPU_NAMESPACE::activation_clip_range value)
21653         {
21654             activation_clip_range = static_cast<uint8_t>(value) & ((1U << 3) - 1);
21655             return *this;
21656         }
21657 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_activation_t21658         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21659         {
21660             fields.push_back(std::make_pair<std::string, std::string>(
21661                 "activation_function",
21662                 (activation_function < (sizeof(activation_function_str) / sizeof(activation_function_str[0])) ?
21663                      activation_function_str[activation_function] :
21664                      "****")));
21665             fields.push_back(std::make_pair<std::string, std::string>(
21666                 "activation_clip_range",
21667                 (activation_clip_range < (sizeof(activation_clip_range_str) / sizeof(activation_clip_range_str[0])) ?
21668                      activation_clip_range_str[activation_clip_range] :
21669                      "****")));
21670         }
21671 #endif
21672 #endif
21673     };
21674     // Lower bound clip
21675     struct npu_set_activation_min_t
21676     {
21677 #ifdef __cplusplus
21678       private:
21679 #endif
21680         uint32_t opcode : 10; //  opcode
21681         uint32_t reserved0 : 4;
21682         uint32_t control : 2;        //  control
21683         uint32_t clip_boundary : 16; //  Clip boundary for OFM activations
21684 #ifdef __cplusplus
21685       public:
npu_set_activation_min_tisa::npu_set_activation_min_t21686         npu_set_activation_min_t(uint32_t _clip_boundary) :
21687             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN)), reserved0(0),
21688             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21689             clip_boundary(_clip_boundary & ((1U << 16) - 1))
21690         {
21691         }
npu_set_activation_min_tisa::npu_set_activation_min_t21692         CONSTEXPR npu_set_activation_min_t() :
21693             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN)), reserved0(0),
21694             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), clip_boundary(0)
21695         {
21696         }
validisa::npu_set_activation_min_t21697         CONSTEXPR bool valid() const
21698         {
21699             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN) &&
21700                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21701         }
initisa::npu_set_activation_min_t21702         CONSTEXPR void init()
21703         {
21704             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN);
21705             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21706         }
uint32_tisa::npu_set_activation_min_t21707         operator uint32_t()
21708         {
21709             uint32_t word;
21710             std::memcpy(&word, this, sizeof(word));
21711             return word;
21712         }
get_opcodeisa::npu_set_activation_min_t21713         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21714         {
21715             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21716         }
set_opcodeisa::npu_set_activation_min_t21717         CONSTEXPR npu_set_activation_min_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21718         {
21719             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21720             return *this;
21721         }
get_controlisa::npu_set_activation_min_t21722         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21723         {
21724             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21725         }
set_controlisa::npu_set_activation_min_t21726         CONSTEXPR npu_set_activation_min_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21727         {
21728             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21729             return *this;
21730         }
get_clip_boundaryisa::npu_set_activation_min_t21731         CONSTEXPR uint32_t get_clip_boundary() const
21732         {
21733             return static_cast<uint32_t>(clip_boundary);
21734         }
set_clip_boundaryisa::npu_set_activation_min_t21735         CONSTEXPR npu_set_activation_min_t &set_clip_boundary(uint32_t value)
21736         {
21737             clip_boundary = static_cast<uint16_t>(value) & ((1U << 16) - 1);
21738             return *this;
21739         }
21740 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_activation_min_t21741         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21742         {
21743             fields.push_back(std::make_pair<std::string, std::string>("clip_boundary", std::to_string(clip_boundary)));
21744         }
21745 #endif
21746 #endif
21747     };
21748     // Upper bound clip
21749     struct npu_set_activation_max_t
21750     {
21751 #ifdef __cplusplus
21752       private:
21753 #endif
21754         uint32_t opcode : 10; //  opcode
21755         uint32_t reserved0 : 4;
21756         uint32_t control : 2;        //  control
21757         uint32_t clip_boundary : 16; //  Clip boundary for OFM activations
21758 #ifdef __cplusplus
21759       public:
npu_set_activation_max_tisa::npu_set_activation_max_t21760         npu_set_activation_max_t(uint32_t _clip_boundary) :
21761             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX)), reserved0(0),
21762             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21763             clip_boundary(_clip_boundary & ((1U << 16) - 1))
21764         {
21765         }
npu_set_activation_max_tisa::npu_set_activation_max_t21766         CONSTEXPR npu_set_activation_max_t() :
21767             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX)), reserved0(0),
21768             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), clip_boundary(0)
21769         {
21770         }
validisa::npu_set_activation_max_t21771         CONSTEXPR bool valid() const
21772         {
21773             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX) &&
21774                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21775         }
initisa::npu_set_activation_max_t21776         CONSTEXPR void init()
21777         {
21778             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX);
21779             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21780         }
uint32_tisa::npu_set_activation_max_t21781         operator uint32_t()
21782         {
21783             uint32_t word;
21784             std::memcpy(&word, this, sizeof(word));
21785             return word;
21786         }
get_opcodeisa::npu_set_activation_max_t21787         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21788         {
21789             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21790         }
set_opcodeisa::npu_set_activation_max_t21791         CONSTEXPR npu_set_activation_max_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21792         {
21793             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21794             return *this;
21795         }
get_controlisa::npu_set_activation_max_t21796         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21797         {
21798             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21799         }
set_controlisa::npu_set_activation_max_t21800         CONSTEXPR npu_set_activation_max_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21801         {
21802             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21803             return *this;
21804         }
get_clip_boundaryisa::npu_set_activation_max_t21805         CONSTEXPR uint32_t get_clip_boundary() const
21806         {
21807             return static_cast<uint32_t>(clip_boundary);
21808         }
set_clip_boundaryisa::npu_set_activation_max_t21809         CONSTEXPR npu_set_activation_max_t &set_clip_boundary(uint32_t value)
21810         {
21811             clip_boundary = static_cast<uint16_t>(value) & ((1U << 16) - 1);
21812             return *this;
21813         }
21814 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_activation_max_t21815         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21816         {
21817             fields.push_back(std::make_pair<std::string, std::string>("clip_boundary", std::to_string(clip_boundary)));
21818         }
21819 #endif
21820 #endif
21821     };
21822     // Index n for weight stream access
21823     struct npu_set_weight_region_t
21824     {
21825 #ifdef __cplusplus
21826       private:
21827 #endif
21828         uint32_t opcode : 10; //  opcode
21829         uint32_t reserved0 : 4;
21830         uint32_t control : 2; //  control
21831         uint32_t region : 3;  //  Index n for weight stream access
21832         uint32_t reserved1 : 13;
21833 #ifdef __cplusplus
21834       public:
npu_set_weight_region_tisa::npu_set_weight_region_t21835         npu_set_weight_region_t(uint32_t _region) :
21836             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION)), reserved0(0),
21837             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
21838             reserved1(0)
21839         {
21840         }
npu_set_weight_region_tisa::npu_set_weight_region_t21841         CONSTEXPR npu_set_weight_region_t() :
21842             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION)), reserved0(0),
21843             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
21844         {
21845         }
validisa::npu_set_weight_region_t21846         CONSTEXPR bool valid() const
21847         {
21848             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION) &&
21849                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21850         }
initisa::npu_set_weight_region_t21851         CONSTEXPR void init()
21852         {
21853             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION);
21854             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21855         }
uint32_tisa::npu_set_weight_region_t21856         operator uint32_t()
21857         {
21858             uint32_t word;
21859             std::memcpy(&word, this, sizeof(word));
21860             return word;
21861         }
get_opcodeisa::npu_set_weight_region_t21862         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21863         {
21864             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21865         }
set_opcodeisa::npu_set_weight_region_t21866         CONSTEXPR npu_set_weight_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21867         {
21868             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21869             return *this;
21870         }
get_controlisa::npu_set_weight_region_t21871         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21872         {
21873             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21874         }
set_controlisa::npu_set_weight_region_t21875         CONSTEXPR npu_set_weight_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21876         {
21877             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21878             return *this;
21879         }
get_regionisa::npu_set_weight_region_t21880         CONSTEXPR uint32_t get_region() const
21881         {
21882             return static_cast<uint32_t>(region);
21883         }
set_regionisa::npu_set_weight_region_t21884         CONSTEXPR npu_set_weight_region_t &set_region(uint32_t value)
21885         {
21886             region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
21887             return *this;
21888         }
21889 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_weight_region_t21890         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21891         {
21892             fields.push_back(std::make_pair<std::string, std::string>("region", std::to_string(region)));
21893         }
21894 #endif
21895 #endif
21896     };
21897     // Index n for scale stream access
21898     struct npu_set_scale_region_t
21899     {
21900 #ifdef __cplusplus
21901       private:
21902 #endif
21903         uint32_t opcode : 10; //  opcode
21904         uint32_t reserved0 : 4;
21905         uint32_t control : 2; //  control
21906         uint32_t region : 3;  //  Index n for scale stream access
21907         uint32_t reserved1 : 13;
21908 #ifdef __cplusplus
21909       public:
npu_set_scale_region_tisa::npu_set_scale_region_t21910         npu_set_scale_region_t(uint32_t _region) :
21911             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION)), reserved0(0),
21912             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
21913             reserved1(0)
21914         {
21915         }
npu_set_scale_region_tisa::npu_set_scale_region_t21916         CONSTEXPR npu_set_scale_region_t() :
21917             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION)), reserved0(0),
21918             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
21919         {
21920         }
validisa::npu_set_scale_region_t21921         CONSTEXPR bool valid() const
21922         {
21923             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION) &&
21924                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21925         }
initisa::npu_set_scale_region_t21926         CONSTEXPR void init()
21927         {
21928             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION);
21929             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21930         }
uint32_tisa::npu_set_scale_region_t21931         operator uint32_t()
21932         {
21933             uint32_t word;
21934             std::memcpy(&word, this, sizeof(word));
21935             return word;
21936         }
get_opcodeisa::npu_set_scale_region_t21937         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21938         {
21939             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21940         }
set_opcodeisa::npu_set_scale_region_t21941         CONSTEXPR npu_set_scale_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21942         {
21943             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21944             return *this;
21945         }
get_controlisa::npu_set_scale_region_t21946         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21947         {
21948             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21949         }
set_controlisa::npu_set_scale_region_t21950         CONSTEXPR npu_set_scale_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21951         {
21952             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21953             return *this;
21954         }
get_regionisa::npu_set_scale_region_t21955         CONSTEXPR uint32_t get_region() const
21956         {
21957             return static_cast<uint32_t>(region);
21958         }
set_regionisa::npu_set_scale_region_t21959         CONSTEXPR npu_set_scale_region_t &set_region(uint32_t value)
21960         {
21961             region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
21962             return *this;
21963         }
21964 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_scale_region_t21965         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21966         {
21967             fields.push_back(std::make_pair<std::string, std::string>("region", std::to_string(region)));
21968         }
21969 #endif
21970 #endif
21971     };
21972     // Start of ACC0,ACC1 buffers
21973     struct npu_set_ab_start_t
21974     {
21975 #ifdef __cplusplus
21976       private:
21977 #endif
21978         uint32_t opcode : 10; //  opcode
21979         uint32_t reserved0 : 4;
21980         uint32_t control : 2;  //  control
21981         uint32_t ab_start : 6; //  Start of ACC0,ACC1 buffers in the SHRAM in KB units. Multiple of 2
21982         uint32_t reserved1 : 10;
21983 #ifdef __cplusplus
21984       public:
npu_set_ab_start_tisa::npu_set_ab_start_t21985         npu_set_ab_start_t(uint32_t _ab_start) :
21986             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START)), reserved0(0),
21987             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ab_start(_ab_start & ((1U << 6) - 1)),
21988             reserved1(0)
21989         {
21990         }
npu_set_ab_start_tisa::npu_set_ab_start_t21991         CONSTEXPR npu_set_ab_start_t() :
21992             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START)), reserved0(0),
21993             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ab_start(0), reserved1(0)
21994         {
21995         }
validisa::npu_set_ab_start_t21996         CONSTEXPR bool valid() const
21997         {
21998             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START) &&
21999                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22000         }
initisa::npu_set_ab_start_t22001         CONSTEXPR void init()
22002         {
22003             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START);
22004             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22005         }
uint32_tisa::npu_set_ab_start_t22006         operator uint32_t()
22007         {
22008             uint32_t word;
22009             std::memcpy(&word, this, sizeof(word));
22010             return word;
22011         }
get_opcodeisa::npu_set_ab_start_t22012         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22013         {
22014             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22015         }
set_opcodeisa::npu_set_ab_start_t22016         CONSTEXPR npu_set_ab_start_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22017         {
22018             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22019             return *this;
22020         }
get_controlisa::npu_set_ab_start_t22021         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22022         {
22023             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22024         }
set_controlisa::npu_set_ab_start_t22025         CONSTEXPR npu_set_ab_start_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22026         {
22027             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22028             return *this;
22029         }
get_ab_startisa::npu_set_ab_start_t22030         CONSTEXPR uint32_t get_ab_start() const
22031         {
22032             return static_cast<uint32_t>(ab_start);
22033         }
set_ab_startisa::npu_set_ab_start_t22034         CONSTEXPR npu_set_ab_start_t &set_ab_start(uint32_t value)
22035         {
22036             ab_start = static_cast<uint8_t>(value) & ((1U << 6) - 1);
22037             return *this;
22038         }
22039 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_ab_start_t22040         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22041         {
22042             fields.push_back(std::make_pair<std::string, std::string>("ab_start", std::to_string(ab_start)));
22043         }
22044 #endif
22045 #endif
22046     };
22047     // Block number of blocks dependency
22048     struct npu_set_blockdep_t
22049     {
22050 #ifdef __cplusplus
22051       private:
22052 #endif
22053         uint32_t opcode : 10; //  opcode
22054         uint32_t reserved0 : 4;
22055         uint32_t control : 2;  //  control
22056         uint32_t blockdep : 2; //  Block number of blocks dependency between kernel operations
22057         uint32_t reserved1 : 14;
22058 #ifdef __cplusplus
22059       public:
npu_set_blockdep_tisa::npu_set_blockdep_t22060         npu_set_blockdep_t(uint32_t _blockdep) :
22061             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP)), reserved0(0),
22062             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), blockdep(_blockdep & ((1U << 2) - 1)),
22063             reserved1(0)
22064         {
22065         }
npu_set_blockdep_tisa::npu_set_blockdep_t22066         CONSTEXPR npu_set_blockdep_t() :
22067             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP)), reserved0(0),
22068             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), blockdep(0), reserved1(0)
22069         {
22070         }
validisa::npu_set_blockdep_t22071         CONSTEXPR bool valid() const
22072         {
22073             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP) &&
22074                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22075         }
initisa::npu_set_blockdep_t22076         CONSTEXPR void init()
22077         {
22078             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP);
22079             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22080         }
uint32_tisa::npu_set_blockdep_t22081         operator uint32_t()
22082         {
22083             uint32_t word;
22084             std::memcpy(&word, this, sizeof(word));
22085             return word;
22086         }
get_opcodeisa::npu_set_blockdep_t22087         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22088         {
22089             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22090         }
set_opcodeisa::npu_set_blockdep_t22091         CONSTEXPR npu_set_blockdep_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22092         {
22093             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22094             return *this;
22095         }
get_controlisa::npu_set_blockdep_t22096         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22097         {
22098             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22099         }
set_controlisa::npu_set_blockdep_t22100         CONSTEXPR npu_set_blockdep_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22101         {
22102             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22103             return *this;
22104         }
get_blockdepisa::npu_set_blockdep_t22105         CONSTEXPR uint32_t get_blockdep() const
22106         {
22107             return static_cast<uint32_t>(blockdep);
22108         }
set_blockdepisa::npu_set_blockdep_t22109         CONSTEXPR npu_set_blockdep_t &set_blockdep(uint32_t value)
22110         {
22111             blockdep = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22112             return *this;
22113         }
22114 #ifdef NPU_DISASSEMBLE
disassembleisa::npu_set_blockdep_t22115         void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22116         {
22117             fields.push_back(std::make_pair<std::string, std::string>("blockdep", std::to_string(blockdep)));
22118         }
22119 #endif
22120 #endif
22121     };
22122     // DMA0 source region
22123     struct npu_set_dma0_src_region_t
22124     {
22125 #ifdef __cplusplus
22126       private:
22127 #endif
22128         uint32_t opcode : 10; //  opcode
22129         uint32_t reserved0 : 4;
22130         uint32_t control : 2; //  control
22131         uint32_t region : 3;  //  Region number
22132         uint32_t reserved1 : 5;
22133         uint32_t region_mode : 1; //  Region mode
22134         uint32_t stride_mode : 2; //  Stride mode
22135         uint32_t reserved2 : 5;
22136 #ifdef __cplusplus
22137       public:
npu_set_dma0_src_region_tisa::npu_set_dma0_src_region_t22138         npu_set_dma0_src_region_t(uint32_t _region,
22139                                   NPU_NAMESPACE::dma_region_mode _region_mode,
22140                                   NPU_NAMESPACE::dma_stride_mode _stride_mode) :
22141             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION)),
22142             reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
22143             region(_region & ((1U << 3) - 1)), reserved1(0),
22144             region_mode(static_cast<uint8_t>(_region_mode) & ((1U << 1) - 1)),
22145             stride_mode(static_cast<uint8_t>(_stride_mode) & ((1U << 2) - 1)), reserved2(0)
22146         {
22147         }
npu_set_dma0_src_region_tisa::npu_set_dma0_src_region_t22148         CONSTEXPR npu_set_dma0_src_region_t() :
22149             opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION)), reserved0(0),
22150             control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), region_mode(0),
22151             stride_mode(0), reserved2(0)
22152         {
22153         }
validisa::npu_set_dma0_src_region_t22154         CONSTEXPR bool valid() const
22155         {
22156             return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION) &&
22157                    control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22158         }
initisa::npu_set_dma0_src_region_t22159         CONSTEXPR void init()
22160         {
22161             opcode  = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION);
22162             control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22163         }
uint32_tisa::npu_set_dma0_src_region_t22164         operator uint32_t()
22165         {
22166             uint32_t word;
22167             std::memcpy(&word, this, sizeof(word));
22168             return word;
22169         }
get_opcodeisa::npu_set_dma0_src_region_t22170         CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22171         {
22172             return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22173         }
set_opcodeisa::npu_set_dma0_src_region_t22174         CONSTEXPR npu_set_dma0_src_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22175         {
22176             opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22177             return *this;
22178         }
get_controlisa::npu_set_dma0_src_region_t22179         CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22180         {
22181             return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22182         }
set_controlisa::npu_set_dma0_src_region_t22183         CONSTEXPR npu_set_dma0_src_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22184         {
22185             control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22186             return *this;
22187         }
get_regionisa::npu_set_dma0_src_region_t22188         CONSTEXPR uint32_t get_region() const
22189         {
22190             return static_cast<uint32_t>(region);
22191         }
set_regionisa::npu_set_dma0_src_region_t22192         CONSTEXPR npu_set_dma0_src_region_t &set_region(uint32_t value)
22193         {
22194             region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
22195             return *this;
22196         }
get_region_modeisa::npu_set_dma0_src_region_t22197         CONSTEXPR NPU_NAMESPACE::dma_region_mode get_region_mode() const
22198         {
22199             return static_cast<NPU_NAMESPACE::dma_region_mode>(region_mode);
22200         }
          &(:: )set_region_modeisa::npu_set_dma0_src_region_t22201 CONSTEXPRnpu_set_dma0_src_region_tset_region_modeNPU_NAMESPACEdma_region_modevalue
        {
             = <>() & (( << ) - );
             *;
        }

22202 22203 region_modestatic_castuint8_tvalue1U1122204 returnthis22205          :: () get_stride_modeisa::npu_set_dma0_src_region_t22206 CONSTEXPRNPU_NAMESPACEdma_stride_modeget_stride_modeconst        {
             <::>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
                             
          : ;
          : ; 
          : ; 
          : ;
# 
      :

22207 22208 returnstatic_castNPU_NAMESPACEdma_stride_modestride_mode22209           &(:: )set_stride_modeisa::npu_set_dma0_src_region_t22210 CONSTEXPRnpu_set_dma0_src_region_tset_stride_modeNPU_NAMESPACEdma_stride_modevalue        {
             = <>() & (( << ) - );
             *;
        }
22211 22212 stride_modestatic_castuint8_tvalue1U2122213 returnthis22214 22215 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_dma0_src_region_t22216 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
        }
22217 22218 fieldspush_backstdmake_pairstdstringstdstring"region"stdto_stringregion22219 fieldspush_backstdmake_pairstdstringstdstring22220 "region_mode"22221 region_modesizeofdma_region_mode_strsizeofdma_region_mode_str22222 dma_region_mode_strregion_mode22223 "****"22224 fieldspush_backstdmake_pairstdstringstdstring22225 "stride_mode"22226 stride_modesizeofdma_stride_mode_strsizeofdma_stride_mode_str22227 dma_stride_mode_strstride_mode22228 "****"22229 22230 endif22231 endif22232 22233 // DMA0 destination region22234 structnpu_set_dma0_dst_region_t22235 22236 ifdef__cplusplus22237 private22238 endif22239 uint32_topcode10//  opcode22240 uint32_treserved0422241 uint32_tcontrol2//  control22242 uint32_tregion3//  Region number if region_mode is region_mode_external. Else core mask to write to (bit k22243 //  set for core k=0,1)22244 uint32_treserved1522245 uint32_tregion_mode1//  Region mode22246 uint32_tstride_mode2//  Stride mode22247 uint32_treserved2522248 ifdef__cplusplus22249 public        ( ,npu_set_dma0_dst_region_tisa::npu_set_dma0_dst_region_t22250 npu_set_dma0_dst_region_tuint32_t_region                                  :: ,
                                  :: ) :
            (<>(::::)),
            (0), (<>(::::)),
            ( & (( << ) - )), (0),
            (<>() & (( << ) - )),
            (<>() & (( << ) - )), (0)
        {
        }

22251 NPU_NAMESPACEdma_region_mode_region_mode22252 NPU_NAMESPACEdma_stride_mode_stride_mode22253 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_DST_REGION22254 reserved0controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22255 region_region1U31reserved122256 region_modestatic_castuint8_t_region_mode1U1122257 stride_modestatic_castuint8_t_stride_mode1U21reserved222258 22259          () :npu_set_dma0_dst_region_tisa::npu_set_dma0_dst_region_t22260 CONSTEXPRnpu_set_dma0_dst_region_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0),
            (0), (0)
        {
        }

22261 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_DST_REGIONreserved022262 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLregionreserved1region_mode22263 stride_modereserved222264 22265           () validisa::npu_set_dma0_dst_region_t22266 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

22267 22268 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_DST_REGION22269 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22270           ()initisa::npu_set_dma0_dst_region_t22271 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

22272 22273 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_DST_REGION22274 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22275          ()uint32_tisa::npu_set_dma0_dst_region_t22276 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

22277 22278 uint32_tword22279 stdmemcpywordthissizeofword22280 returnword22281          :: () get_opcodeisa::npu_set_dma0_dst_region_t22282 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

22283 22284 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode22285           &(:: )set_opcodeisa::npu_set_dma0_dst_region_t22286 CONSTEXPRnpu_set_dma0_dst_region_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

22287 22288 opcodestatic_castuint16_tvalue1U10122289 returnthis22290          :: () get_controlisa::npu_set_dma0_dst_region_t22291 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

22292 22293 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol22294           &(:: )set_controlisa::npu_set_dma0_dst_region_t22295 CONSTEXPRnpu_set_dma0_dst_region_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

22296 22297 controlstatic_castuint8_tvalue1U2122298 returnthis22299           () get_regionisa::npu_set_dma0_dst_region_t22300 CONSTEXPRuint32_tget_regionconst        {
             <>();
        }

22301 22302 returnstatic_castuint32_tregion22303           &( )set_regionisa::npu_set_dma0_dst_region_t22304 CONSTEXPRnpu_set_dma0_dst_region_tset_regionuint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }

22305 22306 regionstatic_castuint8_tvalue1U3122307 returnthis22308          :: () get_region_modeisa::npu_set_dma0_dst_region_t22309 CONSTEXPRNPU_NAMESPACEdma_region_modeget_region_modeconst        {
             <::>();
        }

22310 22311 returnstatic_castNPU_NAMESPACEdma_region_moderegion_mode22312           &(:: )set_region_modeisa::npu_set_dma0_dst_region_t22313 CONSTEXPRnpu_set_dma0_dst_region_tset_region_modeNPU_NAMESPACEdma_region_modevalue        {
             = <>() & (( << ) - );
             *;
        }

22314 22315 region_modestatic_castuint8_tvalue1U1122316 returnthis22317          :: () get_stride_modeisa::npu_set_dma0_dst_region_t22318 CONSTEXPRNPU_NAMESPACEdma_stride_modeget_stride_modeconst        {
             <::>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ;   
# 
      :

22319 22320 returnstatic_castNPU_NAMESPACEdma_stride_modestride_mode22321           &(:: )set_stride_modeisa::npu_set_dma0_dst_region_t22322 CONSTEXPRnpu_set_dma0_dst_region_tset_stride_modeNPU_NAMESPACEdma_stride_modevalue        {
             = <>() & (( << ) - );
             *;
        }
22323 22324 stride_modestatic_castuint8_tvalue1U2122325 returnthis22326 22327 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_dma0_dst_region_t22328 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
        }
22329 22330 fieldspush_backstdmake_pairstdstringstdstring"region"stdto_stringregion22331 fieldspush_backstdmake_pairstdstringstdstring22332 "region_mode"22333 region_modesizeofdma_region_mode_strsizeofdma_region_mode_str22334 dma_region_mode_strregion_mode22335 "****"22336 fieldspush_backstdmake_pairstdstringstdstring22337 "stride_mode"22338 stride_modesizeofdma_stride_mode_strsizeofdma_stride_mode_str22339 dma_stride_mode_strstride_mode22340 "****"22341 22342 endif22343 endif22344 22345 // Size of second dimension for 2D/3D transfers22346 structnpu_set_dma0_size0_t22347 22348 ifdef__cplusplus22349 private22350 endif22351 uint32_topcode10//  opcode22352 uint32_treserved0422353 uint32_tcontrol2//  control22354 uint32_tsize16//  Size of second dimension for 2D/3D transfers22355 ifdef__cplusplus22356 public        ( ) :npu_set_dma0_size0_tisa::npu_set_dma0_size0_t22357 npu_set_dma0_size0_tuint32_t_size            (<>(::::)), (0),
            (<>(::::)), ( & (( << ) - ))
        {
        }

22358 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_SIZE0reserved022359 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLsize_size1U16122360 22361          () :npu_set_dma0_size0_tisa::npu_set_dma0_size0_t22362 CONSTEXPRnpu_set_dma0_size0_t            (<>(::::)), (0),
            (<>(::::)), (0)
        {
        }

22363 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_SIZE0reserved022364 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLsize22365 22366           () validisa::npu_set_dma0_size0_t22367 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

22368 22369 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_SIZE022370 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22371           ()initisa::npu_set_dma0_size0_t22372 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

22373 22374 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_SIZE022375 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22376          ()uint32_tisa::npu_set_dma0_size0_t22377 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

22378 22379 uint32_tword22380 stdmemcpywordthissizeofword22381 returnword22382          :: () get_opcodeisa::npu_set_dma0_size0_t22383 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

22384 22385 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode22386           &(:: )set_opcodeisa::npu_set_dma0_size0_t22387 CONSTEXPRnpu_set_dma0_size0_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

22388 22389 opcodestatic_castuint16_tvalue1U10122390 returnthis22391          :: () get_controlisa::npu_set_dma0_size0_t22392 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

22393 22394 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol22395           &(:: )set_controlisa::npu_set_dma0_size0_t22396 CONSTEXPRnpu_set_dma0_size0_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

22397 22398 controlstatic_castuint8_tvalue1U2122399 returnthis22400           () get_sizeisa::npu_set_dma0_size0_t22401 CONSTEXPRuint32_tget_sizeconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ;   
# 
      :

22402 22403 returnstatic_castuint32_tsize22404           &( )set_sizeisa::npu_set_dma0_size0_t22405 CONSTEXPRnpu_set_dma0_size0_tset_sizeuint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }
22406 22407 sizestatic_castuint16_tvalue1U16122408 returnthis22409 22410 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_dma0_size0_t22411 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
22412 22413 fieldspush_backstdmake_pairstdstringstdstring"size"stdto_stringsize22414 22415 endif22416 endif22417 22418 // Size of third dimension for 3D transfers22419 structnpu_set_dma0_size1_t22420 22421 ifdef__cplusplus22422 private22423 endif22424 uint32_topcode10//  opcode22425 uint32_treserved0422426 uint32_tcontrol2//  control22427 uint32_tsize16//  Size of third dimension for 3D transfers22428 ifdef__cplusplus22429 public        ( ) :npu_set_dma0_size1_tisa::npu_set_dma0_size1_t22430 npu_set_dma0_size1_tuint32_t_size            (<>(::::)), (0),
            (<>(::::)), ( & (( << ) - ))
        {
        }

22431 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_SIZE1reserved022432 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLsize_size1U16122433 22434          () :npu_set_dma0_size1_tisa::npu_set_dma0_size1_t22435 CONSTEXPRnpu_set_dma0_size1_t            (<>(::::)), (0),
            (<>(::::)), (0)
        {
        }

22436 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_SIZE1reserved022437 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLsize22438 22439           () validisa::npu_set_dma0_size1_t22440 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

22441 22442 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_SIZE122443 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22444           ()initisa::npu_set_dma0_size1_t22445 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

22446 22447 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_DMA0_SIZE122448 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22449          ()uint32_tisa::npu_set_dma0_size1_t22450 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

22451 22452 uint32_tword22453 stdmemcpywordthissizeofword22454 returnword22455          :: () get_opcodeisa::npu_set_dma0_size1_t22456 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

22457 22458 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode22459           &(:: )set_opcodeisa::npu_set_dma0_size1_t22460 CONSTEXPRnpu_set_dma0_size1_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

22461 22462 opcodestatic_castuint16_tvalue1U10122463 returnthis22464          :: () get_controlisa::npu_set_dma0_size1_t22465 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

22466 22467 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol22468           &(:: )set_controlisa::npu_set_dma0_size1_t22469 CONSTEXPRnpu_set_dma0_size1_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

22470 22471 controlstatic_castuint8_tvalue1U2122472 returnthis22473           () get_sizeisa::npu_set_dma0_size1_t22474 CONSTEXPRuint32_tget_sizeconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
        
             : ; 
          : ; 
          : ; 
          : ;
          : ;      
          : ; 
          : ;
# 
      :

22475 22476 returnstatic_castuint32_tsize22477           &( )set_sizeisa::npu_set_dma0_size1_t22478 CONSTEXPRnpu_set_dma0_size1_tset_sizeuint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }
22479 22480 sizestatic_castuint16_tvalue1U16122481 returnthis22482 22483 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_dma0_size1_t22484 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
22485 22486 fieldspush_backstdmake_pairstdstringstdstring"size"stdto_stringsize22487 22488 endif22489 endif22490 22491 // IFM2 broadcast configuration22492 structnpu_set_ifm2_broadcast_t22493 22494 ifdef__cplusplus22495 private22496 endif22497 uint32_topcode10//  opcode22498 uint32_treserved0422499 uint32_tcontrol2//  control22500 uint32_t22501 broadcast_h1//  Broadcast H dimension (if set then any accesses to IFM2 sets y=0 and IFM2 height=1)22502 uint32_tbroadcast_w1//  Broadcast W dimension (if set then any accesses to IFM2 sets x=0 and IFM2 width=1)22503 uint32_tbroadcast_c1//  Broadcast C dimension (if set then any accesses to IFM2 sets c=0 and IFM2 depth=1)22504 uint32_treserved1322505 uint32_toperand_order1//  Operand order22506 uint32_tbroadcast_constant1//  Broadcast constant given by NPU_SET_IFM2_SCALAR and so ignore BH, BW and BC22507 uint32_treserved2822508 ifdef__cplusplus22509 public        (:: ,npu_set_ifm2_broadcast_tisa::npu_set_ifm2_broadcast_t22510 npu_set_ifm2_broadcast_tNPU_NAMESPACEbroadcast_mode_broadcast_h                                 :: ,
                                 :: ,
                                 :: ,
                                 :: ) :
            (<>(::::)),
            (0), (<>(::::)),
            (<>() & (( << ) - )),
            (<>() & (( << ) - )),
            (<>() & (( << ) - )), (0),
            (<>() & (( << ) - )),
            (<>() & (( << ) - )), (0)
        {
        }

22511 NPU_NAMESPACEbroadcast_mode_broadcast_w22512 NPU_NAMESPACEbroadcast_mode_broadcast_c22513 NPU_NAMESPACEifm2_operand_order_operand_order22514 NPU_NAMESPACEbroadcast_mode_broadcast_constant22515 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_BROADCAST22516 reserved0controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22517 broadcast_hstatic_castuint8_t_broadcast_h1U1122518 broadcast_wstatic_castuint8_t_broadcast_w1U1122519 broadcast_cstatic_castuint8_t_broadcast_c1U11reserved122520 operand_orderstatic_castuint8_t_operand_order1U1122521 broadcast_constantstatic_castuint8_t_broadcast_constant1U11reserved222522 22523          () :npu_set_ifm2_broadcast_tisa::npu_set_ifm2_broadcast_t22524 CONSTEXPRnpu_set_ifm2_broadcast_t            (<>(::::)), (0),
            (<>(::::)), (0), (0),
            (0), (0), (0), (0), (0)
        {
        }

22525 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_BROADCASTreserved022526 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLbroadcast_hbroadcast_w22527 broadcast_creserved1operand_orderbroadcast_constantreserved222528 22529           () validisa::npu_set_ifm2_broadcast_t22530 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

22531 22532 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_BROADCAST22533 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22534           ()initisa::npu_set_ifm2_broadcast_t22535 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

22536 22537 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_BROADCAST22538 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22539          ()uint32_tisa::npu_set_ifm2_broadcast_t22540 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

22541 22542 uint32_tword22543 stdmemcpywordthissizeofword22544 returnword22545          :: () get_opcodeisa::npu_set_ifm2_broadcast_t22546 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

22547 22548 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode22549           &(:: )set_opcodeisa::npu_set_ifm2_broadcast_t22550 CONSTEXPRnpu_set_ifm2_broadcast_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

22551 22552 opcodestatic_castuint16_tvalue1U10122553 returnthis22554          :: () get_controlisa::npu_set_ifm2_broadcast_t22555 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

22556 22557 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol22558           &(:: )set_controlisa::npu_set_ifm2_broadcast_t22559 CONSTEXPRnpu_set_ifm2_broadcast_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

22560 22561 controlstatic_castuint8_tvalue1U2122562 returnthis22563          :: () get_broadcast_hisa::npu_set_ifm2_broadcast_t22564 CONSTEXPRNPU_NAMESPACEbroadcast_modeget_broadcast_hconst        {
             <::>();
        }

22565 22566 returnstatic_castNPU_NAMESPACEbroadcast_modebroadcast_h22567           &(:: )set_broadcast_hisa::npu_set_ifm2_broadcast_t22568 CONSTEXPRnpu_set_ifm2_broadcast_tset_broadcast_hNPU_NAMESPACEbroadcast_modevalue        {
             = <>() & (( << ) - );
             *;
        }

22569 22570 broadcast_hstatic_castuint8_tvalue1U1122571 returnthis22572          :: () get_broadcast_wisa::npu_set_ifm2_broadcast_t22573 CONSTEXPRNPU_NAMESPACEbroadcast_modeget_broadcast_wconst        {
             <::>();
        }

22574 22575 returnstatic_castNPU_NAMESPACEbroadcast_modebroadcast_w22576           &(:: )set_broadcast_wisa::npu_set_ifm2_broadcast_t22577 CONSTEXPRnpu_set_ifm2_broadcast_tset_broadcast_wNPU_NAMESPACEbroadcast_modevalue        {
             = <>() & (( << ) - );
             *;
        }

22578 22579 broadcast_wstatic_castuint8_tvalue1U1122580 returnthis22581          :: () get_broadcast_cisa::npu_set_ifm2_broadcast_t22582 CONSTEXPRNPU_NAMESPACEbroadcast_modeget_broadcast_cconst        {
             <::>();
        }

22583 22584 returnstatic_castNPU_NAMESPACEbroadcast_modebroadcast_c22585           &(:: )set_broadcast_cisa::npu_set_ifm2_broadcast_t22586 CONSTEXPRnpu_set_ifm2_broadcast_tset_broadcast_cNPU_NAMESPACEbroadcast_modevalue        {
             = <>() & (( << ) - );
             *;
        }

22587 22588 broadcast_cstatic_castuint8_tvalue1U1122589 returnthis22590          :: () get_operand_orderisa::npu_set_ifm2_broadcast_t22591 CONSTEXPRNPU_NAMESPACEifm2_operand_orderget_operand_orderconst        {
             <::>();
        }

22592 22593 returnstatic_castNPU_NAMESPACEifm2_operand_orderoperand_order22594           &(:: )set_operand_orderisa::npu_set_ifm2_broadcast_t22595 CONSTEXPRnpu_set_ifm2_broadcast_tset_operand_orderNPU_NAMESPACEifm2_operand_ordervalue        {
             = <>() & (( << ) - );
             *;
        }

22596 22597 operand_orderstatic_castuint8_tvalue1U1122598 returnthis22599          :: () get_broadcast_constantisa::npu_set_ifm2_broadcast_t22600 CONSTEXPRNPU_NAMESPACEbroadcast_modeget_broadcast_constantconst        {
             <::>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
# 
      :

22601 22602 returnstatic_castNPU_NAMESPACEbroadcast_modebroadcast_constant22603           &(:: )set_broadcast_constantisa::npu_set_ifm2_broadcast_t22604 CONSTEXPRnpu_set_ifm2_broadcast_tset_broadcast_constantNPU_NAMESPACEbroadcast_modevalue        {
             = <>() & (( << ) - );
             *;
        }
22605 22606 broadcast_constantstatic_castuint8_tvalue1U1122607 returnthis22608 22609 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_broadcast_t22610 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
        }
22611 22612 fieldspush_backstdmake_pairstdstringstdstring22613 "broadcast_h"22614 broadcast_hsizeofbroadcast_mode_strsizeofbroadcast_mode_str22615 broadcast_mode_strbroadcast_h22616 "****"22617 fieldspush_backstdmake_pairstdstringstdstring22618 "broadcast_w"22619 broadcast_wsizeofbroadcast_mode_strsizeofbroadcast_mode_str22620 broadcast_mode_strbroadcast_w22621 "****"22622 fieldspush_backstdmake_pairstdstringstdstring22623 "broadcast_c"22624 broadcast_csizeofbroadcast_mode_strsizeofbroadcast_mode_str22625 broadcast_mode_strbroadcast_c22626 "****"22627 fieldspush_backstdmake_pairstdstringstdstring22628 "operand_order"22629 operand_ordersizeofifm2_operand_order_strsizeofifm2_operand_order_str22630 ifm2_operand_order_stroperand_order22631 "****"22632 fieldspush_backstdmake_pairstdstringstdstring22633 "broadcast_constant"22634 broadcast_constantsizeofbroadcast_mode_strsizeofbroadcast_mode_str22635 broadcast_mode_strbroadcast_constant22636 "****"22637 22638 endif22639 endif22640 22641 // IFM2 scalar value22642 structnpu_set_ifm2_scalar_t22643 22644 ifdef__cplusplus22645 private22646 endif22647 uint32_topcode10//  opcode22648 uint32_treserved0422649 uint32_tcontrol2//  control22650 uint32_tscalar16//  int16 or uint16 depending on ypeifm2_precision.t22651 ifdef__cplusplus22652 public        ( ) :npu_set_ifm2_scalar_tisa::npu_set_ifm2_scalar_t22653 npu_set_ifm2_scalar_tuint32_t_scalar            (<>(::::)), (0),
            (<>(::::)), ( & (( << ) - ))
        {
        }

22654 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_SCALARreserved022655 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLscalar_scalar1U16122656 22657          () :npu_set_ifm2_scalar_tisa::npu_set_ifm2_scalar_t22658 CONSTEXPRnpu_set_ifm2_scalar_t            (<>(::::)), (0),
            (<>(::::)), (0)
        {
        }

22659 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_SCALARreserved022660 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLscalar22661 22662           () validisa::npu_set_ifm2_scalar_t22663 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

22664 22665 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_SCALAR22666 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22667           ()initisa::npu_set_ifm2_scalar_t22668 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

22669 22670 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_SCALAR22671 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22672          ()uint32_tisa::npu_set_ifm2_scalar_t22673 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

22674 22675 uint32_tword22676 stdmemcpywordthissizeofword22677 returnword22678          :: () get_opcodeisa::npu_set_ifm2_scalar_t22679 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

22680 22681 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode22682           &(:: )set_opcodeisa::npu_set_ifm2_scalar_t22683 CONSTEXPRnpu_set_ifm2_scalar_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

22684 22685 opcodestatic_castuint16_tvalue1U10122686 returnthis22687          :: () get_controlisa::npu_set_ifm2_scalar_t22688 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

22689 22690 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol22691           &(:: )set_controlisa::npu_set_ifm2_scalar_t22692 CONSTEXPRnpu_set_ifm2_scalar_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

22693 22694 controlstatic_castuint8_tvalue1U2122695 returnthis22696           () get_scalarisa::npu_set_ifm2_scalar_t22697 CONSTEXPRuint32_tget_scalarconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ;         
          : ; 
          : ;
          : ; 
          : ;
          : ; 
          : ;
# 
      :

22698 22699 returnstatic_castuint32_tscalar22700           &( )set_scalarisa::npu_set_ifm2_scalar_t22701 CONSTEXPRnpu_set_ifm2_scalar_tset_scalaruint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }
22702 22703 scalarstatic_castuint16_tvalue1U16122704 returnthis22705 22706 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_scalar_t22707 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
22708 22709 fieldspush_backstdmake_pairstdstringstdstring"scalar"stdto_stringscalar22710 22711 endif22712 endif22713 22714 // IFM2 Precision22715 structnpu_set_ifm2_precision_t22716 22717 ifdef__cplusplus22718 private22719 endif22720 uint32_topcode10//  opcode22721 uint32_treserved0422722 uint32_tcontrol2//  control22723 uint32_tactivation_type1//  IFM type - MUST MATCH IFM22724 uint32_treserved1122725 uint32_tactivation_precision2//  IFM precision - MUST MATCH IFM22726 uint32_treserved2222727 uint32_tactivation_format2//  IFM format22728 uint32_treserved3822729 ifdef__cplusplus22730 public        (:: ,npu_set_ifm2_precision_tisa::npu_set_ifm2_precision_t22731 npu_set_ifm2_precision_tNPU_NAMESPACEactivation_type_activation_type                                 :: ,
                                 :: ) :
            (<>(::::)),
            (0), (<>(::::)),
            (<>() & (( << ) - )), (0),
            (<>() & (( << ) - )), (0),
            (<>() & (( << ) - )), (0)
        {
        }

22732 NPU_NAMESPACEactivation_precision_activation_precision22733 NPU_NAMESPACEactivation_format_activation_format22734 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_PRECISION22735 reserved0controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22736 activation_typestatic_castuint8_t_activation_type1U11reserved122737 activation_precisionstatic_castuint8_t_activation_precision1U21reserved222738 activation_formatstatic_castuint8_t_activation_format1U21reserved322739 22740          () :npu_set_ifm2_precision_tisa::npu_set_ifm2_precision_t22741 CONSTEXPRnpu_set_ifm2_precision_t            (<>(::::)), (0),
            (<>(::::)), (0), (0),
            (0), (0), (0), (0)
        {
        }

22742 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_PRECISIONreserved022743 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLactivation_typereserved122744 activation_precisionreserved2activation_formatreserved322745 22746           () validisa::npu_set_ifm2_precision_t22747 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

22748 22749 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_PRECISION22750 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22751           ()initisa::npu_set_ifm2_precision_t22752 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

22753 22754 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_PRECISION22755 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22756          ()uint32_tisa::npu_set_ifm2_precision_t22757 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

22758 22759 uint32_tword22760 stdmemcpywordthissizeofword22761 returnword22762          :: () get_opcodeisa::npu_set_ifm2_precision_t22763 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

22764 22765 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode22766           &(:: )set_opcodeisa::npu_set_ifm2_precision_t22767 CONSTEXPRnpu_set_ifm2_precision_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

22768 22769 opcodestatic_castuint16_tvalue1U10122770 returnthis22771          :: () get_controlisa::npu_set_ifm2_precision_t22772 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

22773 22774 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol22775           &(:: )set_controlisa::npu_set_ifm2_precision_t22776 CONSTEXPRnpu_set_ifm2_precision_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

22777 22778 controlstatic_castuint8_tvalue1U2122779 returnthis22780          :: () get_activation_typeisa::npu_set_ifm2_precision_t22781 CONSTEXPRNPU_NAMESPACEactivation_typeget_activation_typeconst        {
             <::>();
        }

22782 22783 returnstatic_castNPU_NAMESPACEactivation_typeactivation_type22784           &(:: )set_activation_typeisa::npu_set_ifm2_precision_t22785 CONSTEXPRnpu_set_ifm2_precision_tset_activation_typeNPU_NAMESPACEactivation_typevalue        {
             = <>() & (( << ) - );
             *;
        }

22786 22787 activation_typestatic_castuint8_tvalue1U1122788 returnthis22789          :: () get_activation_precisionisa::npu_set_ifm2_precision_t22790 CONSTEXPRNPU_NAMESPACEactivation_precisionget_activation_precisionconst        {
             <::>();
        }

22791 22792 returnstatic_castNPU_NAMESPACEactivation_precisionactivation_precision22793           &(:: )set_activation_precisionisa::npu_set_ifm2_precision_t22794 CONSTEXPRnpu_set_ifm2_precision_tset_activation_precisionNPU_NAMESPACEactivation_precisionvalue        {
             = <>() & (( << ) - );
             *;
        }

22795 22796 activation_precisionstatic_castuint8_tvalue1U2122797 returnthis22798          :: () get_activation_formatisa::npu_set_ifm2_precision_t22799 CONSTEXPRNPU_NAMESPACEactivation_formatget_activation_formatconst        {
             <::>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ;     
          : ; 
# 
      :

22800 22801 returnstatic_castNPU_NAMESPACEactivation_formatactivation_format22802           &(:: )set_activation_formatisa::npu_set_ifm2_precision_t22803 CONSTEXPRnpu_set_ifm2_precision_tset_activation_formatNPU_NAMESPACEactivation_formatvalue        {
             = <>() & (( << ) - );
             *;
        }
22804 22805 activation_formatstatic_castuint8_tvalue1U2122806 returnthis22807 22808 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_precision_t22809 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
            .(::<::, ::>(
                ,
                ( < (() / ([0])) ?
                     [] :
                     )));
        }
22810 22811 fieldspush_backstdmake_pairstdstringstdstring22812 "activation_type"22813 activation_typesizeofactivation_type_strsizeofactivation_type_str22814 activation_type_stractivation_type22815 "****"22816 fieldspush_backstdmake_pairstdstringstdstring22817 "activation_precision"22818 activation_precisionsizeofactivation_precision_strsizeofactivation_precision_str22819 activation_precision_stractivation_precision22820 "****"22821 fieldspush_backstdmake_pairstdstringstdstring22822 "activation_format"22823 activation_formatsizeofactivation_format_strsizeofactivation_format_str22824 activation_format_stractivation_format22825 "****"22826 22827 endif22828 endif22829 22830 // IFM2 zero point22831 structnpu_set_ifm2_zero_point_t22832 22833 ifdef__cplusplus22834 private22835 endif22836 uint32_topcode10//  opcode22837 uint32_treserved0422838 uint32_tcontrol2//  control22839 uint32_tzero_point16//  Zero point offset22840 ifdef__cplusplus22841 public        ( ) :npu_set_ifm2_zero_point_tisa::npu_set_ifm2_zero_point_t22842 npu_set_ifm2_zero_point_tuint32_t_zero_point            (<>(::::)), (0),
            (<>(::::)),
            ( & (( << ) - ))
        {
        }

22843 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_ZERO_POINTreserved022844 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22845 zero_point_zero_point1U16122846 22847          () :npu_set_ifm2_zero_point_tisa::npu_set_ifm2_zero_point_t22848 CONSTEXPRnpu_set_ifm2_zero_point_t            (<>(::::)), (0),
            (<>(::::)), (0)
        {
        }

22849 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_ZERO_POINTreserved022850 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLzero_point22851 22852           () validisa::npu_set_ifm2_zero_point_t22853 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

22854 22855 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_ZERO_POINT22856 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22857           ()initisa::npu_set_ifm2_zero_point_t22858 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

22859 22860 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_ZERO_POINT22861 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22862          ()uint32_tisa::npu_set_ifm2_zero_point_t22863 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

22864 22865 uint32_tword22866 stdmemcpywordthissizeofword22867 returnword22868          :: () get_opcodeisa::npu_set_ifm2_zero_point_t22869 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

22870 22871 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode22872           &(:: )set_opcodeisa::npu_set_ifm2_zero_point_t22873 CONSTEXPRnpu_set_ifm2_zero_point_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

22874 22875 opcodestatic_castuint16_tvalue1U10122876 returnthis22877          :: () get_controlisa::npu_set_ifm2_zero_point_t22878 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

22879 22880 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol22881           &(:: )set_controlisa::npu_set_ifm2_zero_point_t22882 CONSTEXPRnpu_set_ifm2_zero_point_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

22883 22884 controlstatic_castuint8_tvalue1U2122885 returnthis22886           () get_zero_pointisa::npu_set_ifm2_zero_point_t22887 CONSTEXPRuint32_tget_zero_pointconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ;   
          : ; 
# 
      :

22888 22889 returnstatic_castuint32_tzero_point22890           &( )set_zero_pointisa::npu_set_ifm2_zero_point_t22891 CONSTEXPRnpu_set_ifm2_zero_point_tset_zero_pointuint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }
22892 22893 zero_pointstatic_castuint16_tvalue1U16122894 returnthis22895 22896 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_zero_point_t22897 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
22898 22899 fieldspush_backstdmake_pairstdstringstdstring"zero_point"stdto_stringzero_point22900 22901 endif22902 endif22903 22904 // IFM2 Tile 0 and tile 2 width22905 structnpu_set_ifm2_width0_m1_t22906 22907 ifdef__cplusplus22908 private22909 endif22910 uint32_topcode10//  opcode22911 uint32_treserved0422912 uint32_tcontrol2//  control22913 uint32_twidth_m116//  IFM2 Tile 0 and tile 2 width22914 ifdef__cplusplus22915 public        ( ) :npu_set_ifm2_width0_m1_tisa::npu_set_ifm2_width0_m1_t22916 npu_set_ifm2_width0_m1_tuint32_t_width_m1            (<>(::::)), (0),
            (<>(::::)), ( & (( << ) - ))
        {
        }

22917 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_WIDTH0_M1reserved022918 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLwidth_m1_width_m11U16122919 22920          () :npu_set_ifm2_width0_m1_tisa::npu_set_ifm2_width0_m1_t22921 CONSTEXPRnpu_set_ifm2_width0_m1_t            (<>(::::)), (0),
            (<>(::::)), (0)
        {
        }

22922 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_WIDTH0_M1reserved022923 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLwidth_m122924 22925           () validisa::npu_set_ifm2_width0_m1_t22926 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

22927 22928 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_WIDTH0_M122929 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22930           ()initisa::npu_set_ifm2_width0_m1_t22931 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

22932 22933 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_WIDTH0_M122934 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL22935          ()uint32_tisa::npu_set_ifm2_width0_m1_t22936 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

22937 22938 uint32_tword22939 stdmemcpywordthissizeofword22940 returnword22941          :: () get_opcodeisa::npu_set_ifm2_width0_m1_t22942 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

22943 22944 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode22945           &(:: )set_opcodeisa::npu_set_ifm2_width0_m1_t22946 CONSTEXPRnpu_set_ifm2_width0_m1_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

22947 22948 opcodestatic_castuint16_tvalue1U10122949 returnthis22950          :: () get_controlisa::npu_set_ifm2_width0_m1_t22951 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

22952 22953 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol22954           &(:: )set_controlisa::npu_set_ifm2_width0_m1_t22955 CONSTEXPRnpu_set_ifm2_width0_m1_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

22956 22957 controlstatic_castuint8_tvalue1U2122958 returnthis22959           () get_width_m1isa::npu_set_ifm2_width0_m1_t22960 CONSTEXPRuint32_tget_width_m1const        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ;    
          : ; 
# 
      :

22961 22962 returnstatic_castuint32_twidth_m122963           &( )set_width_m1isa::npu_set_ifm2_width0_m1_t22964 CONSTEXPRnpu_set_ifm2_width0_m1_tset_width_m1uint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }
22965 22966 width_m1static_castuint16_tvalue1U16122967 returnthis22968 22969 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_width0_m1_t22970 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
22971 22972 fieldspush_backstdmake_pairstdstringstdstring"width_m1"stdto_stringwidth_m122973 22974 endif22975 endif22976 22977 // IFM2 Tile 0 height22978 structnpu_set_ifm2_height0_m1_t22979 22980 ifdef__cplusplus22981 private22982 endif22983 uint32_topcode10//  opcode22984 uint32_treserved0422985 uint32_tcontrol2//  control22986 uint32_theight_m116//  IFM2 Tile 0 height22987 ifdef__cplusplus22988 public        ( ) :npu_set_ifm2_height0_m1_tisa::npu_set_ifm2_height0_m1_t22989 npu_set_ifm2_height0_m1_tuint32_t_height_m1            (<>(::::)), (0),
            (<>(::::)), ( & (( << ) - ))
        {
        }

22990 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_HEIGHT0_M1reserved022991 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLheight_m1_height_m11U16122992 22993          () :npu_set_ifm2_height0_m1_tisa::npu_set_ifm2_height0_m1_t22994 CONSTEXPRnpu_set_ifm2_height0_m1_t            (<>(::::)), (0),
            (<>(::::)), (0)
        {
        }

22995 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_HEIGHT0_M1reserved022996 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLheight_m122997 22998           () validisa::npu_set_ifm2_height0_m1_t22999 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

23000 23001 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_HEIGHT0_M123002 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL23003           ()initisa::npu_set_ifm2_height0_m1_t23004 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23005 23006 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_HEIGHT0_M123007 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL23008          ()uint32_tisa::npu_set_ifm2_height0_m1_t23009 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

23010 23011 uint32_tword23012 stdmemcpywordthissizeofword23013 returnword23014          :: () get_opcodeisa::npu_set_ifm2_height0_m1_t23015 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

23016 23017 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode23018           &(:: )set_opcodeisa::npu_set_ifm2_height0_m1_t23019 CONSTEXPRnpu_set_ifm2_height0_m1_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

23020 23021 opcodestatic_castuint16_tvalue1U10123022 returnthis23023          :: () get_controlisa::npu_set_ifm2_height0_m1_t23024 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

23025 23026 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol23027           &(:: )set_controlisa::npu_set_ifm2_height0_m1_t23028 CONSTEXPRnpu_set_ifm2_height0_m1_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

23029 23030 controlstatic_castuint8_tvalue1U2123031 returnthis23032           () get_height_m1isa::npu_set_ifm2_height0_m1_t23033 CONSTEXPRuint32_tget_height_m1const        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ;    
          : ; 
# 
      :

23034 23035 returnstatic_castuint32_theight_m123036           &( )set_height_m1isa::npu_set_ifm2_height0_m1_t23037 CONSTEXPRnpu_set_ifm2_height0_m1_tset_height_m1uint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }
23038 23039 height_m1static_castuint16_tvalue1U16123040 returnthis23041 23042 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_height0_m1_t23043 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
23044 23045 fieldspush_backstdmake_pairstdstringstdstring"height_m1"stdto_stringheight_m123046 23047 endif23048 endif23049 23050 // IFM2 Tile 1 height23051 structnpu_set_ifm2_height1_m1_t23052 23053 ifdef__cplusplus23054 private23055 endif23056 uint32_topcode10//  opcode23057 uint32_treserved0423058 uint32_tcontrol2//  control23059 uint32_theight_m116//  IFM2 Tile 1 height23060 ifdef__cplusplus23061 public        ( ) :npu_set_ifm2_height1_m1_tisa::npu_set_ifm2_height1_m1_t23062 npu_set_ifm2_height1_m1_tuint32_t_height_m1            (<>(::::)), (0),
            (<>(::::)), ( & (( << ) - ))
        {
        }

23063 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_HEIGHT1_M1reserved023064 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLheight_m1_height_m11U16123065 23066          () :npu_set_ifm2_height1_m1_tisa::npu_set_ifm2_height1_m1_t23067 CONSTEXPRnpu_set_ifm2_height1_m1_t            (<>(::::)), (0),
            (<>(::::)), (0)
        {
        }

23068 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_HEIGHT1_M1reserved023069 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLheight_m123070 23071           () validisa::npu_set_ifm2_height1_m1_t23072 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

23073 23074 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_HEIGHT1_M123075 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL23076           ()initisa::npu_set_ifm2_height1_m1_t23077 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23078 23079 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_HEIGHT1_M123080 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL23081          ()uint32_tisa::npu_set_ifm2_height1_m1_t23082 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

23083 23084 uint32_tword23085 stdmemcpywordthissizeofword23086 returnword23087          :: () get_opcodeisa::npu_set_ifm2_height1_m1_t23088 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

23089 23090 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode23091           &(:: )set_opcodeisa::npu_set_ifm2_height1_m1_t23092 CONSTEXPRnpu_set_ifm2_height1_m1_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

23093 23094 opcodestatic_castuint16_tvalue1U10123095 returnthis23096          :: () get_controlisa::npu_set_ifm2_height1_m1_t23097 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

23098 23099 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol23100           &(:: )set_controlisa::npu_set_ifm2_height1_m1_t23101 CONSTEXPRnpu_set_ifm2_height1_m1_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

23102 23103 controlstatic_castuint8_tvalue1U2123104 returnthis23105           () get_height_m1isa::npu_set_ifm2_height1_m1_t23106 CONSTEXPRuint32_tget_height_m1const        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ;  
          : ; 
          : ;
# 
      :

23107 23108 returnstatic_castuint32_theight_m123109           &( )set_height_m1isa::npu_set_ifm2_height1_m1_t23110 CONSTEXPRnpu_set_ifm2_height1_m1_tset_height_m1uint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }
23111 23112 height_m1static_castuint16_tvalue1U16123113 returnthis23114 23115 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_height1_m1_t23116 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
23117 23118 fieldspush_backstdmake_pairstdstringstdstring"height_m1"stdto_stringheight_m123119 23120 endif23121 endif23122 23123 // Start of IB0,IB1 buffers for IFM223124 structnpu_set_ifm2_ib_start_t23125 23126 ifdef__cplusplus23127 private23128 endif23129 uint32_topcode10//  opcode23130 uint32_treserved0423131 uint32_tcontrol2//  control23132 uint32_tib_start6//  Start of IB0,IB1 buffers for IFM2 in the SHRAM in KB units. Multiple of 223133 uint32_treserved11023134 ifdef__cplusplus23135 public        ( ) :npu_set_ifm2_ib_start_tisa::npu_set_ifm2_ib_start_t23136 npu_set_ifm2_ib_start_tuint32_t_ib_start            (<>(::::)), (0),
            (<>(::::)), ( & (( << ) - )),
            (0)
        {
        }

23137 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_IB_STARTreserved023138 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLib_start_ib_start1U6123139 reserved123140 23141          () :npu_set_ifm2_ib_start_tisa::npu_set_ifm2_ib_start_t23142 CONSTEXPRnpu_set_ifm2_ib_start_t            (<>(::::)), (0),
            (<>(::::)), (0), (0)
        {
        }

23143 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_IB_STARTreserved023144 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLib_startreserved123145 23146           () validisa::npu_set_ifm2_ib_start_t23147 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

23148 23149 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_IB_START23150 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL23151           ()initisa::npu_set_ifm2_ib_start_t23152 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23153 23154 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_IB_START23155 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL23156          ()uint32_tisa::npu_set_ifm2_ib_start_t23157 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

23158 23159 uint32_tword23160 stdmemcpywordthissizeofword23161 returnword23162          :: () get_opcodeisa::npu_set_ifm2_ib_start_t23163 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

23164 23165 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode23166           &(:: )set_opcodeisa::npu_set_ifm2_ib_start_t23167 CONSTEXPRnpu_set_ifm2_ib_start_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

23168 23169 opcodestatic_castuint16_tvalue1U10123170 returnthis23171          :: () get_controlisa::npu_set_ifm2_ib_start_t23172 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

23173 23174 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol23175           &(:: )set_controlisa::npu_set_ifm2_ib_start_t23176 CONSTEXPRnpu_set_ifm2_ib_start_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

23177 23178 controlstatic_castuint8_tvalue1U2123179 returnthis23180           () get_ib_startisa::npu_set_ifm2_ib_start_t23181 CONSTEXPRuint32_tget_ib_startconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ;  
          : ;
# 
      :

23182 23183 returnstatic_castuint32_tib_start23184           &( )set_ib_startisa::npu_set_ifm2_ib_start_t23185 CONSTEXPRnpu_set_ifm2_ib_start_tset_ib_startuint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }
23186 23187 ib_startstatic_castuint8_tvalue1U6123188 returnthis23189 23190 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_ib_start_t23191 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
23192 23193 fieldspush_backstdmake_pairstdstringstdstring"ib_start"stdto_stringib_start23194 23195 endif23196 endif23197 23198 // Index n for IFM2 access23199 structnpu_set_ifm2_region_t23200 23201 ifdef__cplusplus23202 private23203 endif23204 uint32_topcode10//  opcode23205 uint32_treserved0423206 uint32_tcontrol2//  control23207 uint32_tregion3//  Index n for IFM2 access23208 uint32_treserved11323209 ifdef__cplusplus23210 public        ( ) :npu_set_ifm2_region_tisa::npu_set_ifm2_region_t23211 npu_set_ifm2_region_tuint32_t_region            (<>(::::)), (0),
            (<>(::::)), ( & (( << ) - )),
            (0)
        {
        }

23212 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_REGIONreserved023213 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLregion_region1U3123214 reserved123215 23216          () :npu_set_ifm2_region_tisa::npu_set_ifm2_region_t23217 CONSTEXPRnpu_set_ifm2_region_t            (<>(::::)), (0),
            (<>(::::)), (0), (0)
        {
        }

23218 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_REGIONreserved023219 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRLregionreserved123220 23221           () validisa::npu_set_ifm2_region_t23222 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    == <>(::::);
        }

23223 23224 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_REGION23225 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL23226           ()initisa::npu_set_ifm2_region_t23227 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23228 23229 opcodestatic_castuint16_tNPU_NAMESPACEcmd0_opcodeNPU_SET_IFM2_REGION23230 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD0_CTRL23231          ()uint32_tisa::npu_set_ifm2_region_t23232 operatoruint32_t        {
             ;
            ::(&, , ());
             ;
        }

23233 23234 uint32_tword23235 stdmemcpywordthissizeofword23236 returnword23237          :: () get_opcodeisa::npu_set_ifm2_region_t23238 CONSTEXPRNPU_NAMESPACEcmd0_opcodeget_opcodeconst        {
             <::>();
        }

23239 23240 returnstatic_castNPU_NAMESPACEcmd0_opcodeopcode23241           &(:: )set_opcodeisa::npu_set_ifm2_region_t23242 CONSTEXPRnpu_set_ifm2_region_tset_opcodeNPU_NAMESPACEcmd0_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

23243 23244 opcodestatic_castuint16_tvalue1U10123245 returnthis23246          :: () get_controlisa::npu_set_ifm2_region_t23247 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

23248 23249 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol23250           &(:: )set_controlisa::npu_set_ifm2_region_t23251 CONSTEXPRnpu_set_ifm2_region_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

23252 23253 controlstatic_castuint8_tvalue1U2123254 returnthis23255           () get_regionisa::npu_set_ifm2_region_t23256 CONSTEXPRuint32_tget_regionconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23257 23258 returnstatic_castuint32_tregion23259           &( )set_regionisa::npu_set_ifm2_region_t23260 CONSTEXPRnpu_set_ifm2_region_tset_regionuint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }
23261 23262 regionstatic_castuint8_tvalue1U3123263 returnthis23264 23265 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_region_t23266 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
23267 23268 fieldspush_backstdmake_pairstdstringstdstring"region"stdto_stringregion23269 23270 endif23271 endif23272 23273 // IFM Tile 0 address23274 structnpu_set_ifm_base0_t23275 23276 ifdef__cplusplus23277 private23278 endif23279 uint32_topcode10//  opcode23280 uint32_treserved0423281 uint32_tcontrol2//  control23282 uint32_taddr_hi8//  address extension23283 uint32_treserved1823284 uint32_taddr_lo32//  address offset23285 ifdef__cplusplus23286 public        ( ) :npu_set_ifm_base0_tisa::npu_set_ifm_base0_t23287 npu_set_ifm_base0_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23288 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE0reserved023289 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23290 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123291 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23292 23293          () :npu_set_ifm_base0_tisa::npu_set_ifm_base0_t23294 CONSTEXPRnpu_set_ifm_base0_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23295 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE0reserved023296 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23297 23298           () validisa::npu_set_ifm_base0_t23299 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23300 23301 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE0control123302 control223303           ()initisa::npu_set_ifm_base0_t23304 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23305 23306 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE023307 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23308          ()uint64_tisa::npu_set_ifm_base0_t23309 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23310 23311 uint64_tword23312 stdmemcpywordthissizeofword23313 returnword23314           () get_addrisa::npu_set_ifm_base0_t23315 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23316 23317 returnstatic_castuint64_taddr_hi32addr_lo23318           &( )set_addrisa::npu_set_ifm_base0_t23319 CONSTEXPRnpu_set_ifm_base0_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
23320 23321 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax23322 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax23323 returnthis23324 23325 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm_base0_t23326 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
23327 23328 stdstringstreamsaddr23329 saddrstdhex"0x"get_addr23330 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr23331 23332 endif23333 endif23334 23335 // IFM Tile 1 address23336 structnpu_set_ifm_base1_t23337 23338 ifdef__cplusplus23339 private23340 endif23341 uint32_topcode10//  opcode23342 uint32_treserved0423343 uint32_tcontrol2//  control23344 uint32_taddr_hi8//  address extension23345 uint32_treserved1823346 uint32_taddr_lo32//  address offset23347 ifdef__cplusplus23348 public        ( ) :npu_set_ifm_base1_tisa::npu_set_ifm_base1_t23349 npu_set_ifm_base1_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23350 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE1reserved023351 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23352 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123353 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23354 23355          () :npu_set_ifm_base1_tisa::npu_set_ifm_base1_t23356 CONSTEXPRnpu_set_ifm_base1_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23357 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE1reserved023358 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23359 23360           () validisa::npu_set_ifm_base1_t23361 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23362 23363 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE1control123364 control223365           ()initisa::npu_set_ifm_base1_t23366 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23367 23368 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE123369 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23370          ()uint64_tisa::npu_set_ifm_base1_t23371 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23372 23373 uint64_tword23374 stdmemcpywordthissizeofword23375 returnword23376           () get_addrisa::npu_set_ifm_base1_t23377 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23378 23379 returnstatic_castuint64_taddr_hi32addr_lo23380           &( )set_addrisa::npu_set_ifm_base1_t23381 CONSTEXPRnpu_set_ifm_base1_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
23382 23383 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax23384 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax23385 returnthis23386 23387 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm_base1_t23388 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
23389 23390 stdstringstreamsaddr23391 saddrstdhex"0x"get_addr23392 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr23393 23394 endif23395 endif23396 23397 // IFM Tile 2 address23398 structnpu_set_ifm_base2_t23399 23400 ifdef__cplusplus23401 private23402 endif23403 uint32_topcode10//  opcode23404 uint32_treserved0423405 uint32_tcontrol2//  control23406 uint32_taddr_hi8//  address extension23407 uint32_treserved1823408 uint32_taddr_lo32//  address offset23409 ifdef__cplusplus23410 public        ( ) :npu_set_ifm_base2_tisa::npu_set_ifm_base2_t23411 npu_set_ifm_base2_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23412 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE2reserved023413 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23414 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123415 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23416 23417          () :npu_set_ifm_base2_tisa::npu_set_ifm_base2_t23418 CONSTEXPRnpu_set_ifm_base2_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23419 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE2reserved023420 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23421 23422           () validisa::npu_set_ifm_base2_t23423 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23424 23425 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE2control123426 control223427           ()initisa::npu_set_ifm_base2_t23428 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23429 23430 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE223431 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23432          ()uint64_tisa::npu_set_ifm_base2_t23433 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23434 23435 uint64_tword23436 stdmemcpywordthissizeofword23437 returnword23438           () get_addrisa::npu_set_ifm_base2_t23439 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23440 23441 returnstatic_castuint64_taddr_hi32addr_lo23442           &( )set_addrisa::npu_set_ifm_base2_t23443 CONSTEXPRnpu_set_ifm_base2_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
23444 23445 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax23446 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax23447 returnthis23448 23449 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm_base2_t23450 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
23451 23452 stdstringstreamsaddr23453 saddrstdhex"0x"get_addr23454 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr23455 23456 endif23457 endif23458 23459 // IFM Tile 3 address23460 structnpu_set_ifm_base3_t23461 23462 ifdef__cplusplus23463 private23464 endif23465 uint32_topcode10//  opcode23466 uint32_treserved0423467 uint32_tcontrol2//  control23468 uint32_taddr_hi8//  address extension23469 uint32_treserved1823470 uint32_taddr_lo32//  address offset23471 ifdef__cplusplus23472 public        ( ) :npu_set_ifm_base3_tisa::npu_set_ifm_base3_t23473 npu_set_ifm_base3_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23474 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE3reserved023475 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23476 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123477 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23478 23479          () :npu_set_ifm_base3_tisa::npu_set_ifm_base3_t23480 CONSTEXPRnpu_set_ifm_base3_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23481 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE3reserved023482 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23483 23484           () validisa::npu_set_ifm_base3_t23485 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23486 23487 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE3control123488 control223489           ()initisa::npu_set_ifm_base3_t23490 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23491 23492 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_BASE323493 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23494          ()uint64_tisa::npu_set_ifm_base3_t23495 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23496 23497 uint64_tword23498 stdmemcpywordthissizeofword23499 returnword23500           () get_addrisa::npu_set_ifm_base3_t23501 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23502 23503 returnstatic_castuint64_taddr_hi32addr_lo23504           &( )set_addrisa::npu_set_ifm_base3_t23505 CONSTEXPRnpu_set_ifm_base3_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
23506 23507 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax23508 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax23509 returnthis23510 23511 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm_base3_t23512 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
23513 23514 stdstringstreamsaddr23515 saddrstdhex"0x"get_addr23516 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr23517 23518 endif23519 endif23520 23521 // IFM byte stride between horizontal values23522 structnpu_set_ifm_stride_x_t23523 23524 ifdef__cplusplus23525 private23526 endif23527 uint32_topcode10//  opcode23528 uint32_treserved0423529 uint32_tcontrol2//  control23530 uint32_taddr_hi8//  address extension23531 uint32_treserved1823532 uint32_taddr_lo32//  address offset23533 ifdef__cplusplus23534 public        ( ) :npu_set_ifm_stride_x_tisa::npu_set_ifm_stride_x_t23535 npu_set_ifm_stride_x_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23536 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_Xreserved023537 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23538 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123539 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23540 23541          () :npu_set_ifm_stride_x_tisa::npu_set_ifm_stride_x_t23542 CONSTEXPRnpu_set_ifm_stride_x_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23543 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_Xreserved023544 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23545 23546           () validisa::npu_set_ifm_stride_x_t23547 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23548 23549 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_Xcontrol123550 control223551           ()initisa::npu_set_ifm_stride_x_t23552 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23553 23554 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_X23555 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23556          ()uint64_tisa::npu_set_ifm_stride_x_t23557 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23558 23559 uint64_tword23560 stdmemcpywordthissizeofword23561 returnword23562           () get_addrisa::npu_set_ifm_stride_x_t23563 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23564 23565 returnstatic_castuint64_taddr_hi32addr_lo23566           &( )set_addrisa::npu_set_ifm_stride_x_t23567 CONSTEXPRnpu_set_ifm_stride_x_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
23568 23569 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax23570 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax23571 returnthis23572 23573 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm_stride_x_t23574 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
23575 23576 stdstringstreamsaddr23577 saddrstdhex"0x"get_addr23578 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr23579 23580 endif23581 endif23582 23583 // IFM byte stride between vertical values23584 structnpu_set_ifm_stride_y_t23585 23586 ifdef__cplusplus23587 private23588 endif23589 uint32_topcode10//  opcode23590 uint32_treserved0423591 uint32_tcontrol2//  control23592 uint32_taddr_hi8//  address extension23593 uint32_treserved1823594 uint32_taddr_lo32//  address offset23595 ifdef__cplusplus23596 public        ( ) :npu_set_ifm_stride_y_tisa::npu_set_ifm_stride_y_t23597 npu_set_ifm_stride_y_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23598 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_Yreserved023599 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23600 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123601 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23602 23603          () :npu_set_ifm_stride_y_tisa::npu_set_ifm_stride_y_t23604 CONSTEXPRnpu_set_ifm_stride_y_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23605 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_Yreserved023606 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23607 23608           () validisa::npu_set_ifm_stride_y_t23609 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23610 23611 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_Ycontrol123612 control223613           ()initisa::npu_set_ifm_stride_y_t23614 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23615 23616 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_Y23617 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23618          ()uint64_tisa::npu_set_ifm_stride_y_t23619 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23620 23621 uint64_tword23622 stdmemcpywordthissizeofword23623 returnword23624           () get_addrisa::npu_set_ifm_stride_y_t23625 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23626 23627 returnstatic_castuint64_taddr_hi32addr_lo23628           &( )set_addrisa::npu_set_ifm_stride_y_t23629 CONSTEXPRnpu_set_ifm_stride_y_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
23630 23631 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax23632 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax23633 returnthis23634 23635 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm_stride_y_t23636 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
23637 23638 stdstringstreamsaddr23639 saddrstdhex"0x"get_addr23640 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr23641 23642 endif23643 endif23644 23645 // IFM byte stride between channel blocks (of 16 bytes each block)23646 structnpu_set_ifm_stride_c_t23647 23648 ifdef__cplusplus23649 private23650 endif23651 uint32_topcode10//  opcode23652 uint32_treserved0423653 uint32_tcontrol2//  control23654 uint32_taddr_hi8//  address extension23655 uint32_treserved1823656 uint32_taddr_lo32//  address offset23657 ifdef__cplusplus23658 public        ( ) :npu_set_ifm_stride_c_tisa::npu_set_ifm_stride_c_t23659 npu_set_ifm_stride_c_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23660 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_Creserved023661 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23662 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123663 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23664 23665          () :npu_set_ifm_stride_c_tisa::npu_set_ifm_stride_c_t23666 CONSTEXPRnpu_set_ifm_stride_c_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23667 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_Creserved023668 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23669 23670           () validisa::npu_set_ifm_stride_c_t23671 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23672 23673 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_Ccontrol123674 control223675           ()initisa::npu_set_ifm_stride_c_t23676 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23677 23678 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM_STRIDE_C23679 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23680          ()uint64_tisa::npu_set_ifm_stride_c_t23681 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23682 23683 uint64_tword23684 stdmemcpywordthissizeofword23685 returnword23686           () get_addrisa::npu_set_ifm_stride_c_t23687 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23688 23689 returnstatic_castuint64_taddr_hi32addr_lo23690           &( )set_addrisa::npu_set_ifm_stride_c_t23691 CONSTEXPRnpu_set_ifm_stride_c_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
23692 23693 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax23694 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax23695 returnthis23696 23697 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm_stride_c_t23698 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
23699 23700 stdstringstreamsaddr23701 saddrstdhex"0x"get_addr23702 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr23703 23704 endif23705 endif23706 23707 // OFM Tile 0 address23708 structnpu_set_ofm_base0_t23709 23710 ifdef__cplusplus23711 private23712 endif23713 uint32_topcode10//  opcode23714 uint32_treserved0423715 uint32_tcontrol2//  control23716 uint32_taddr_hi8//  address extension23717 uint32_treserved1823718 uint32_taddr_lo32//  address offset23719 ifdef__cplusplus23720 public        ( ) :npu_set_ofm_base0_tisa::npu_set_ofm_base0_t23721 npu_set_ofm_base0_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23722 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE0reserved023723 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23724 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123725 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23726 23727          () :npu_set_ofm_base0_tisa::npu_set_ofm_base0_t23728 CONSTEXPRnpu_set_ofm_base0_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23729 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE0reserved023730 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23731 23732           () validisa::npu_set_ofm_base0_t23733 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23734 23735 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE0control123736 control223737           ()initisa::npu_set_ofm_base0_t23738 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23739 23740 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE023741 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23742          ()uint64_tisa::npu_set_ofm_base0_t23743 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23744 23745 uint64_tword23746 stdmemcpywordthissizeofword23747 returnword23748           () get_addrisa::npu_set_ofm_base0_t23749 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23750 23751 returnstatic_castuint64_taddr_hi32addr_lo23752           &( )set_addrisa::npu_set_ofm_base0_t23753 CONSTEXPRnpu_set_ofm_base0_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
23754 23755 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax23756 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax23757 returnthis23758 23759 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ofm_base0_t23760 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
23761 23762 stdstringstreamsaddr23763 saddrstdhex"0x"get_addr23764 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr23765 23766 endif23767 endif23768 23769 // OFM Tile 1 address23770 structnpu_set_ofm_base1_t23771 23772 ifdef__cplusplus23773 private23774 endif23775 uint32_topcode10//  opcode23776 uint32_treserved0423777 uint32_tcontrol2//  control23778 uint32_taddr_hi8//  address extension23779 uint32_treserved1823780 uint32_taddr_lo32//  address offset23781 ifdef__cplusplus23782 public        ( ) :npu_set_ofm_base1_tisa::npu_set_ofm_base1_t23783 npu_set_ofm_base1_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23784 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE1reserved023785 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23786 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123787 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23788 23789          () :npu_set_ofm_base1_tisa::npu_set_ofm_base1_t23790 CONSTEXPRnpu_set_ofm_base1_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23791 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE1reserved023792 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23793 23794           () validisa::npu_set_ofm_base1_t23795 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23796 23797 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE1control123798 control223799           ()initisa::npu_set_ofm_base1_t23800 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23801 23802 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE123803 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23804          ()uint64_tisa::npu_set_ofm_base1_t23805 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23806 23807 uint64_tword23808 stdmemcpywordthissizeofword23809 returnword23810           () get_addrisa::npu_set_ofm_base1_t23811 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23812 23813 returnstatic_castuint64_taddr_hi32addr_lo23814           &( )set_addrisa::npu_set_ofm_base1_t23815 CONSTEXPRnpu_set_ofm_base1_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
23816 23817 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax23818 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax23819 returnthis23820 23821 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ofm_base1_t23822 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
23823 23824 stdstringstreamsaddr23825 saddrstdhex"0x"get_addr23826 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr23827 23828 endif23829 endif23830 23831 // OFM Tile 2 address23832 structnpu_set_ofm_base2_t23833 23834 ifdef__cplusplus23835 private23836 endif23837 uint32_topcode10//  opcode23838 uint32_treserved0423839 uint32_tcontrol2//  control23840 uint32_taddr_hi8//  address extension23841 uint32_treserved1823842 uint32_taddr_lo32//  address offset23843 ifdef__cplusplus23844 public        ( ) :npu_set_ofm_base2_tisa::npu_set_ofm_base2_t23845 npu_set_ofm_base2_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23846 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE2reserved023847 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23848 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123849 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23850 23851          () :npu_set_ofm_base2_tisa::npu_set_ofm_base2_t23852 CONSTEXPRnpu_set_ofm_base2_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23853 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE2reserved023854 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23855 23856           () validisa::npu_set_ofm_base2_t23857 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23858 23859 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE2control123860 control223861           ()initisa::npu_set_ofm_base2_t23862 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23863 23864 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE223865 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23866          ()uint64_tisa::npu_set_ofm_base2_t23867 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23868 23869 uint64_tword23870 stdmemcpywordthissizeofword23871 returnword23872           () get_addrisa::npu_set_ofm_base2_t23873 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23874 23875 returnstatic_castuint64_taddr_hi32addr_lo23876           &( )set_addrisa::npu_set_ofm_base2_t23877 CONSTEXPRnpu_set_ofm_base2_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
23878 23879 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax23880 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax23881 returnthis23882 23883 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ofm_base2_t23884 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
23885 23886 stdstringstreamsaddr23887 saddrstdhex"0x"get_addr23888 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr23889 23890 endif23891 endif23892 23893 // OFM Tile 3 address23894 structnpu_set_ofm_base3_t23895 23896 ifdef__cplusplus23897 private23898 endif23899 uint32_topcode10//  opcode23900 uint32_treserved0423901 uint32_tcontrol2//  control23902 uint32_taddr_hi8//  address extension23903 uint32_treserved1823904 uint32_taddr_lo32//  address offset23905 ifdef__cplusplus23906 public        ( ) :npu_set_ofm_base3_tisa::npu_set_ofm_base3_t23907 npu_set_ofm_base3_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23908 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE3reserved023909 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23910 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123911 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23912 23913          () :npu_set_ofm_base3_tisa::npu_set_ofm_base3_t23914 CONSTEXPRnpu_set_ofm_base3_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23915 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE3reserved023916 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23917 23918           () validisa::npu_set_ofm_base3_t23919 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23920 23921 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE3control123922 control223923           ()initisa::npu_set_ofm_base3_t23924 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23925 23926 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_BASE323927 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23928          ()uint64_tisa::npu_set_ofm_base3_t23929 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23930 23931 uint64_tword23932 stdmemcpywordthissizeofword23933 returnword23934           () get_addrisa::npu_set_ofm_base3_t23935 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23936 23937 returnstatic_castuint64_taddr_hi32addr_lo23938           &( )set_addrisa::npu_set_ofm_base3_t23939 CONSTEXPRnpu_set_ofm_base3_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
23940 23941 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax23942 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax23943 returnthis23944 23945 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ofm_base3_t23946 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
23947 23948 stdstringstreamsaddr23949 saddrstdhex"0x"get_addr23950 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr23951 23952 endif23953 endif23954 23955 // OFM byte stride between horizontal values23956 structnpu_set_ofm_stride_x_t23957 23958 ifdef__cplusplus23959 private23960 endif23961 uint32_topcode10//  opcode23962 uint32_treserved0423963 uint32_tcontrol2//  control23964 uint32_taddr_hi8//  address extension23965 uint32_treserved1823966 uint32_taddr_lo32//  address offset23967 ifdef__cplusplus23968 public        ( ) :npu_set_ofm_stride_x_tisa::npu_set_ofm_stride_x_t23969 npu_set_ofm_stride_x_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

23970 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_Xreserved023971 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23972 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved123973 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax23974 23975          () :npu_set_ofm_stride_x_tisa::npu_set_ofm_stride_x_t23976 CONSTEXPRnpu_set_ofm_stride_x_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

23977 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_Xreserved023978 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo23979 23980           () validisa::npu_set_ofm_stride_x_t23981 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

23982 23983 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_Xcontrol123984 control223985           ()initisa::npu_set_ofm_stride_x_t23986 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

23987 23988 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_X23989 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL23990          ()uint64_tisa::npu_set_ofm_stride_x_t23991 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

23992 23993 uint64_tword23994 stdmemcpywordthissizeofword23995 returnword23996           () get_addrisa::npu_set_ofm_stride_x_t23997 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

23998 23999 returnstatic_castuint64_taddr_hi32addr_lo24000           &( )set_addrisa::npu_set_ofm_stride_x_t24001 CONSTEXPRnpu_set_ofm_stride_x_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
24002 24003 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax24004 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax24005 returnthis24006 24007 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ofm_stride_x_t24008 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
24009 24010 stdstringstreamsaddr24011 saddrstdhex"0x"get_addr24012 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr24013 24014 endif24015 endif24016 24017 // OFM byte stride between vertical values24018 structnpu_set_ofm_stride_y_t24019 24020 ifdef__cplusplus24021 private24022 endif24023 uint32_topcode10//  opcode24024 uint32_treserved0424025 uint32_tcontrol2//  control24026 uint32_taddr_hi8//  address extension24027 uint32_treserved1824028 uint32_taddr_lo32//  address offset24029 ifdef__cplusplus24030 public        ( ) :npu_set_ofm_stride_y_tisa::npu_set_ofm_stride_y_t24031 npu_set_ofm_stride_y_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

24032 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_Yreserved024033 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24034 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved124035 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax24036 24037          () :npu_set_ofm_stride_y_tisa::npu_set_ofm_stride_y_t24038 CONSTEXPRnpu_set_ofm_stride_y_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24039 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_Yreserved024040 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo24041 24042           () validisa::npu_set_ofm_stride_y_t24043 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24044 24045 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_Ycontrol124046 control224047           ()initisa::npu_set_ofm_stride_y_t24048 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24049 24050 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_Y24051 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24052          ()uint64_tisa::npu_set_ofm_stride_y_t24053 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24054 24055 uint64_tword24056 stdmemcpywordthissizeofword24057 returnword24058           () get_addrisa::npu_set_ofm_stride_y_t24059 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

24060 24061 returnstatic_castuint64_taddr_hi32addr_lo24062           &( )set_addrisa::npu_set_ofm_stride_y_t24063 CONSTEXPRnpu_set_ofm_stride_y_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
24064 24065 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax24066 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax24067 returnthis24068 24069 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ofm_stride_y_t24070 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
24071 24072 stdstringstreamsaddr24073 saddrstdhex"0x"get_addr24074 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr24075 24076 endif24077 endif24078 24079 // OFM byte stride between channel blocks (of 16 bytes each block)24080 structnpu_set_ofm_stride_c_t24081 24082 ifdef__cplusplus24083 private24084 endif24085 uint32_topcode10//  opcode24086 uint32_treserved0424087 uint32_tcontrol2//  control24088 uint32_taddr_hi8//  address extension24089 uint32_treserved1824090 uint32_taddr_lo32//  address offset24091 ifdef__cplusplus24092 public        ( ) :npu_set_ofm_stride_c_tisa::npu_set_ofm_stride_c_t24093 npu_set_ofm_stride_c_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

24094 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_Creserved024095 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24096 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved124097 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax24098 24099          () :npu_set_ofm_stride_c_tisa::npu_set_ofm_stride_c_t24100 CONSTEXPRnpu_set_ofm_stride_c_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24101 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_Creserved024102 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo24103 24104           () validisa::npu_set_ofm_stride_c_t24105 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24106 24107 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_Ccontrol124108 control224109           ()initisa::npu_set_ofm_stride_c_t24110 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24111 24112 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_STRIDE_C24113 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24114          ()uint64_tisa::npu_set_ofm_stride_c_t24115 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24116 24117 uint64_tword24118 stdmemcpywordthissizeofword24119 returnword24120           () get_addrisa::npu_set_ofm_stride_c_t24121 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

24122 24123 returnstatic_castuint64_taddr_hi32addr_lo24124           &( )set_addrisa::npu_set_ofm_stride_c_t24125 CONSTEXPRnpu_set_ofm_stride_c_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
24126 24127 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax24128 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax24129 returnthis24130 24131 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ofm_stride_c_t24132 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
24133 24134 stdstringstreamsaddr24135 saddrstdhex"0x"get_addr24136 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr24137 24138 endif24139 endif24140 24141 // Weight stream byte offset in WEIGHT_REGION24142 structnpu_set_weight_base_t24143 24144 ifdef__cplusplus24145 private24146 endif24147 uint32_topcode10//  opcode24148 uint32_treserved0424149 uint32_tcontrol2//  control24150 uint32_taddr_hi8//  address extension24151 uint32_treserved1824152 uint32_taddr_lo32//  address offset24153 ifdef__cplusplus24154 public        ( ) :npu_set_weight_base_tisa::npu_set_weight_base_t24155 npu_set_weight_base_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

24156 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT_BASEreserved024157 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24158 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved124159 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax24160 24161          () :npu_set_weight_base_tisa::npu_set_weight_base_t24162 CONSTEXPRnpu_set_weight_base_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24163 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT_BASEreserved024164 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo24165 24166           () validisa::npu_set_weight_base_t24167 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24168 24169 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT_BASEcontrol124170 control224171           ()initisa::npu_set_weight_base_t24172 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24173 24174 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT_BASE24175 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24176          ()uint64_tisa::npu_set_weight_base_t24177 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24178 24179 uint64_tword24180 stdmemcpywordthissizeofword24181 returnword24182           () get_addrisa::npu_set_weight_base_t24183 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ;
          : ; 
# 
      :

24184 24185 returnstatic_castuint64_taddr_hi32addr_lo24186           &( )set_addrisa::npu_set_weight_base_t24187 CONSTEXPRnpu_set_weight_base_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
24188 24189 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax24190 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax24191 returnthis24192 24193 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_weight_base_t24194 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
24195 24196 stdstringstreamsaddr24197 saddrstdhex"0x"get_addr24198 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr24199 24200 endif24201 endif24202 24203 // Weight stream byte length24204 structnpu_set_weight_length_t24205 24206 ifdef__cplusplus24207 private24208 endif24209 uint32_topcode10//  opcode24210 uint32_treserved0424211 uint32_tcontrol2//  control24212 uint32_treserved11624213 uint32_tlength32//  Weight stream byte length24214 ifdef__cplusplus24215 public        ( ) :npu_set_weight_length_tisa::npu_set_weight_length_t24216 npu_set_weight_length_tuint32_t_length            (<>(::::)), (0),
            (<>(::::)), (0), ()
        {
        }

24217 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT_LENGTHreserved024218 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLreserved1length_length24219 24220          () :npu_set_weight_length_tisa::npu_set_weight_length_t24221 CONSTEXPRnpu_set_weight_length_t            (<>(::::)), (0),
            (<>(::::)), (0), (0)
        {
        }

24222 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT_LENGTHreserved024223 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLreserved1length24224 24225           () validisa::npu_set_weight_length_t24226 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24227 24228 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT_LENGTHcontrol124229 control224230           ()initisa::npu_set_weight_length_t24231 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24232 24233 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT_LENGTH24234 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24235          ()uint64_tisa::npu_set_weight_length_t24236 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24237 24238 uint64_tword24239 stdmemcpywordthissizeofword24240 returnword24241          :: () get_opcodeisa::npu_set_weight_length_t24242 CONSTEXPRNPU_NAMESPACEcmd1_opcodeget_opcodeconst        {
             <::>();
        }

24243 24244 returnstatic_castNPU_NAMESPACEcmd1_opcodeopcode24245           &(:: )set_opcodeisa::npu_set_weight_length_t24246 CONSTEXPRnpu_set_weight_length_tset_opcodeNPU_NAMESPACEcmd1_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

24247 24248 opcodestatic_castuint16_tvalue1U10124249 returnthis24250          :: () get_controlisa::npu_set_weight_length_t24251 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

24252 24253 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol24254           &(:: )set_controlisa::npu_set_weight_length_t24255 CONSTEXPRnpu_set_weight_length_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

24256 24257 controlstatic_castuint8_tvalue1U2124258 returnthis24259           () get_lengthisa::npu_set_weight_length_t24260 CONSTEXPRuint32_tget_lengthconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

24261 24262 returnstatic_castuint32_tlength24263           &( )set_lengthisa::npu_set_weight_length_t24264 CONSTEXPRnpu_set_weight_length_tset_lengthuint32_tvalue        {
             = ;
             *;
        }
24265 24266 lengthvalue24267 returnthis24268 24269 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_weight_length_t24270 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
24271 24272 fieldspush_backstdmake_pairstdstringstdstring"length"stdto_stringlength24273 24274 endif24275 endif24276 24277 // Scale and bias stream input byte offset from SCALE_REGION24278 structnpu_set_scale_base_t24279 24280 ifdef__cplusplus24281 private24282 endif24283 uint32_topcode10//  opcode24284 uint32_treserved0424285 uint32_tcontrol2//  control24286 uint32_taddr_hi8//  address extension24287 uint32_treserved1824288 uint32_taddr_lo32//  address offset24289 ifdef__cplusplus24290 public        ( ) :npu_set_scale_base_tisa::npu_set_scale_base_t24291 npu_set_scale_base_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

24292 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE_BASEreserved024293 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24294 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved124295 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax24296 24297          () :npu_set_scale_base_tisa::npu_set_scale_base_t24298 CONSTEXPRnpu_set_scale_base_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24299 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE_BASEreserved024300 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo24301 24302           () validisa::npu_set_scale_base_t24303 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24304 24305 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE_BASEcontrol124306 control224307           ()initisa::npu_set_scale_base_t24308 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24309 24310 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE_BASE24311 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24312          ()uint64_tisa::npu_set_scale_base_t24313 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24314 24315 uint64_tword24316 stdmemcpywordthissizeofword24317 returnword24318           () get_addrisa::npu_set_scale_base_t24319 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ;
          : ; 
          : ;
# 
      :

24320 24321 returnstatic_castuint64_taddr_hi32addr_lo24322           &( )set_addrisa::npu_set_scale_base_t24323 CONSTEXPRnpu_set_scale_base_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
24324 24325 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax24326 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax24327 returnthis24328 24329 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_scale_base_t24330 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
24331 24332 stdstringstreamsaddr24333 saddrstdhex"0x"get_addr24334 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr24335 24336 endif24337 endif24338 24339 // Scale and bias stream input byte length24340 structnpu_set_scale_length_t24341 24342 ifdef__cplusplus24343 private24344 endif24345 uint32_topcode10//  opcode24346 uint32_treserved0424347 uint32_tcontrol2//  control24348 uint32_treserved11624349 uint32_tlength20//  Scale and bias stream byte length24350 uint32_treserved21224351 ifdef__cplusplus24352 public        ( ) :npu_set_scale_length_tisa::npu_set_scale_length_t24353 npu_set_scale_length_tuint32_t_length            (<>(::::)), (0),
            (<>(::::)), (0),
            ( & (( << ) - )), (0)
        {
        }

24354 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE_LENGTHreserved024355 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLreserved124356 length_length1U201reserved224357 24358          () :npu_set_scale_length_tisa::npu_set_scale_length_t24359 CONSTEXPRnpu_set_scale_length_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24360 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE_LENGTHreserved024361 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLreserved1lengthreserved224362 24363           () validisa::npu_set_scale_length_t24364 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24365 24366 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE_LENGTHcontrol124367 control224368           ()initisa::npu_set_scale_length_t24369 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24370 24371 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE_LENGTH24372 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24373          ()uint64_tisa::npu_set_scale_length_t24374 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24375 24376 uint64_tword24377 stdmemcpywordthissizeofword24378 returnword24379          :: () get_opcodeisa::npu_set_scale_length_t24380 CONSTEXPRNPU_NAMESPACEcmd1_opcodeget_opcodeconst        {
             <::>();
        }

24381 24382 returnstatic_castNPU_NAMESPACEcmd1_opcodeopcode24383           &(:: )set_opcodeisa::npu_set_scale_length_t24384 CONSTEXPRnpu_set_scale_length_tset_opcodeNPU_NAMESPACEcmd1_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

24385 24386 opcodestatic_castuint16_tvalue1U10124387 returnthis24388          :: () get_controlisa::npu_set_scale_length_t24389 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

24390 24391 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol24392           &(:: )set_controlisa::npu_set_scale_length_t24393 CONSTEXPRnpu_set_scale_length_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

24394 24395 controlstatic_castuint8_tvalue1U2124396 returnthis24397           () get_lengthisa::npu_set_scale_length_t24398 CONSTEXPRuint32_tget_lengthconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ;   
          : ;
          : ; 
# 
      :

24399 24400 returnstatic_castuint32_tlength24401           &( )set_lengthisa::npu_set_scale_length_t24402 CONSTEXPRnpu_set_scale_length_tset_lengthuint32_tvalue        {
             =  & (( << ) - );
             *;
        }
24403 24404 lengthvalue1U20124405 returnthis24406 24407 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_scale_length_t24408 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
24409 24410 fieldspush_backstdmake_pairstdstringstdstring"length"stdto_stringlength24411 24412 endif24413 endif24414 24415 // OFM scale24416 structnpu_set_ofm_scale_t24417 24418 ifdef__cplusplus24419 private24420 endif24421 uint32_topcode10//  opcode24422 uint32_treserved0424423 uint32_tcontrol2//  control24424 uint32_tshift6//  Shift24425 uint32_treserved11024426 uint32_tscale32//  Scale. Not applied for 32-bit operations24427 ifdef__cplusplus24428 public        ( ,  ) :npu_set_ofm_scale_tisa::npu_set_ofm_scale_t24429 npu_set_ofm_scale_tuint32_t_shiftuint32_t_scale            (<>(::::)), (0),
            (<>(::::)), ( & (( << ) - )),
            (0), ()
        {
        }

24430 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_SCALEreserved024431 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLshift_shift1U6124432 reserved1scale_scale24433 24434          () :npu_set_ofm_scale_tisa::npu_set_ofm_scale_t24435 CONSTEXPRnpu_set_ofm_scale_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24436 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_SCALEreserved024437 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLshiftreserved1scale24438 24439           () validisa::npu_set_ofm_scale_t24440 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24441 24442 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_SCALEcontrol124443 control224444           ()initisa::npu_set_ofm_scale_t24445 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24446 24447 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OFM_SCALE24448 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24449          ()uint64_tisa::npu_set_ofm_scale_t24450 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24451 24452 uint64_tword24453 stdmemcpywordthissizeofword24454 returnword24455          :: () get_opcodeisa::npu_set_ofm_scale_t24456 CONSTEXPRNPU_NAMESPACEcmd1_opcodeget_opcodeconst        {
             <::>();
        }

24457 24458 returnstatic_castNPU_NAMESPACEcmd1_opcodeopcode24459           &(:: )set_opcodeisa::npu_set_ofm_scale_t24460 CONSTEXPRnpu_set_ofm_scale_tset_opcodeNPU_NAMESPACEcmd1_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

24461 24462 opcodestatic_castuint16_tvalue1U10124463 returnthis24464          :: () get_controlisa::npu_set_ofm_scale_t24465 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

24466 24467 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol24468           &(:: )set_controlisa::npu_set_ofm_scale_t24469 CONSTEXPRnpu_set_ofm_scale_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

24470 24471 controlstatic_castuint8_tvalue1U2124472 returnthis24473           () get_shiftisa::npu_set_ofm_scale_t24474 CONSTEXPRuint32_tget_shiftconst        {
             <>();
        }

24475 24476 returnstatic_castuint32_tshift24477           &( )set_shiftisa::npu_set_ofm_scale_t24478 CONSTEXPRnpu_set_ofm_scale_tset_shiftuint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }

24479 24480 shiftstatic_castuint8_tvalue1U6124481 returnthis24482           () get_scaleisa::npu_set_ofm_scale_t24483 CONSTEXPRuint32_tget_scaleconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ;   
          : ;
          : ; 
# 
      :

24484 24485 returnstatic_castuint32_tscale24486           &( )set_scaleisa::npu_set_ofm_scale_t24487 CONSTEXPRnpu_set_ofm_scale_tset_scaleuint32_tvalue        {
             = ;
             *;
        }
24488 24489 scalevalue24490 returnthis24491 24492 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ofm_scale_t24493 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
            .(::<::, ::>(, ::()));
        }
24494 24495 fieldspush_backstdmake_pairstdstringstdstring"shift"stdto_stringshift24496 fieldspush_backstdmake_pairstdstringstdstring"scale"stdto_stringscale24497 24498 endif24499 endif24500 24501 // Input operand A scale24502 structnpu_set_opa_scale_t24503 24504 ifdef__cplusplus24505 private24506 endif24507 uint32_topcode10//  opcode24508 uint32_treserved0424509 uint32_tcontrol2//  control24510 uint32_tshift6//  Shift. Ignored if IFM scale mode is 024511 uint32_treserved11024512 uint32_tscale32//  Scale. 16-bit if IFM scale mode is 024513 ifdef__cplusplus24514 public        ( ,  ) :npu_set_opa_scale_tisa::npu_set_opa_scale_t24515 npu_set_opa_scale_tuint32_t_shiftuint32_t_scale            (<>(::::)), (0),
            (<>(::::)), ( & (( << ) - )),
            (0), ()
        {
        }

24516 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OPA_SCALEreserved024517 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLshift_shift1U6124518 reserved1scale_scale24519 24520          () :npu_set_opa_scale_tisa::npu_set_opa_scale_t24521 CONSTEXPRnpu_set_opa_scale_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24522 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OPA_SCALEreserved024523 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLshiftreserved1scale24524 24525           () validisa::npu_set_opa_scale_t24526 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24527 24528 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OPA_SCALEcontrol124529 control224530           ()initisa::npu_set_opa_scale_t24531 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24532 24533 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OPA_SCALE24534 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24535          ()uint64_tisa::npu_set_opa_scale_t24536 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24537 24538 uint64_tword24539 stdmemcpywordthissizeofword24540 returnword24541          :: () get_opcodeisa::npu_set_opa_scale_t24542 CONSTEXPRNPU_NAMESPACEcmd1_opcodeget_opcodeconst        {
             <::>();
        }

24543 24544 returnstatic_castNPU_NAMESPACEcmd1_opcodeopcode24545           &(:: )set_opcodeisa::npu_set_opa_scale_t24546 CONSTEXPRnpu_set_opa_scale_tset_opcodeNPU_NAMESPACEcmd1_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

24547 24548 opcodestatic_castuint16_tvalue1U10124549 returnthis24550          :: () get_controlisa::npu_set_opa_scale_t24551 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

24552 24553 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol24554           &(:: )set_controlisa::npu_set_opa_scale_t24555 CONSTEXPRnpu_set_opa_scale_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

24556 24557 controlstatic_castuint8_tvalue1U2124558 returnthis24559           () get_shiftisa::npu_set_opa_scale_t24560 CONSTEXPRuint32_tget_shiftconst        {
             <>();
        }

24561 24562 returnstatic_castuint32_tshift24563           &( )set_shiftisa::npu_set_opa_scale_t24564 CONSTEXPRnpu_set_opa_scale_tset_shiftuint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }

24565 24566 shiftstatic_castuint8_tvalue1U6124567 returnthis24568           () get_scaleisa::npu_set_opa_scale_t24569 CONSTEXPRuint32_tget_scaleconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ;
          : ; 
          : ;
# 
      :

24570 24571 returnstatic_castuint32_tscale24572           &( )set_scaleisa::npu_set_opa_scale_t24573 CONSTEXPRnpu_set_opa_scale_tset_scaleuint32_tvalue        {
             = ;
             *;
        }
24574 24575 scalevalue24576 returnthis24577 24578 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_opa_scale_t24579 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
            .(::<::, ::>(, ::()));
        }
24580 24581 fieldspush_backstdmake_pairstdstringstdstring"shift"stdto_stringshift24582 fieldspush_backstdmake_pairstdstringstdstring"scale"stdto_stringscale24583 24584 endif24585 endif24586 24587 // Input operand B scale24588 structnpu_set_opb_scale_t24589 24590 ifdef__cplusplus24591 private24592 endif24593 uint32_topcode10//  opcode24594 uint32_treserved0424595 uint32_tcontrol2//  control24596 uint32_treserved11624597 uint32_tscale16//  Scale. Not used if IFM scale mode is 1 or 224598 uint32_treserved21624599 ifdef__cplusplus24600 public        ( ) :npu_set_opb_scale_tisa::npu_set_opb_scale_t24601 npu_set_opb_scale_tuint32_t_scale            (<>(::::)), (0),
            (<>(::::)), (0),
            ( & (( << ) - )), (0)
        {
        }

24602 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OPB_SCALEreserved024603 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLreserved124604 scale_scale1U161reserved224605 24606          () :npu_set_opb_scale_tisa::npu_set_opb_scale_t24607 CONSTEXPRnpu_set_opb_scale_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24608 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OPB_SCALEreserved024609 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLreserved1scalereserved224610 24611           () validisa::npu_set_opb_scale_t24612 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24613 24614 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OPB_SCALEcontrol124615 control224616           ()initisa::npu_set_opb_scale_t24617 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24618 24619 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_OPB_SCALE24620 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24621          ()uint64_tisa::npu_set_opb_scale_t24622 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24623 24624 uint64_tword24625 stdmemcpywordthissizeofword24626 returnword24627          :: () get_opcodeisa::npu_set_opb_scale_t24628 CONSTEXPRNPU_NAMESPACEcmd1_opcodeget_opcodeconst        {
             <::>();
        }

24629 24630 returnstatic_castNPU_NAMESPACEcmd1_opcodeopcode24631           &(:: )set_opcodeisa::npu_set_opb_scale_t24632 CONSTEXPRnpu_set_opb_scale_tset_opcodeNPU_NAMESPACEcmd1_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

24633 24634 opcodestatic_castuint16_tvalue1U10124635 returnthis24636          :: () get_controlisa::npu_set_opb_scale_t24637 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

24638 24639 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol24640           &(:: )set_controlisa::npu_set_opb_scale_t24641 CONSTEXPRnpu_set_opb_scale_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

24642 24643 controlstatic_castuint8_tvalue1U2124644 returnthis24645           () get_scaleisa::npu_set_opb_scale_t24646 CONSTEXPRuint32_tget_scaleconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

24647 24648 returnstatic_castuint32_tscale24649           &( )set_scaleisa::npu_set_opb_scale_t24650 CONSTEXPRnpu_set_opb_scale_tset_scaleuint32_tvalue        {
             = <>() & (( << ) - );
             *;
        }
24651 24652 scalestatic_castuint16_tvalue1U16124653 returnthis24654 24655 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_opb_scale_t24656 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
24657 24658 fieldspush_backstdmake_pairstdstringstdstring"scale"stdto_stringscale24659 24660 endif24661 endif24662 24663 // DMA user channel 0 source byte offset from DMA0_SRC_REGION24664 structnpu_set_dma0_src_t24665 24666 ifdef__cplusplus24667 private24668 endif24669 uint32_topcode10//  opcode24670 uint32_treserved0424671 uint32_tcontrol2//  control24672 uint32_taddr_hi8//  address extension24673 uint32_treserved1824674 uint32_taddr_lo32//  address offset24675 ifdef__cplusplus24676 public        ( ) :npu_set_dma0_src_tisa::npu_set_dma0_src_t24677 npu_set_dma0_src_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

24678 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SRCreserved024679 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24680 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved124681 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax24682 24683          () :npu_set_dma0_src_tisa::npu_set_dma0_src_t24684 CONSTEXPRnpu_set_dma0_src_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24685 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SRCreserved024686 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo24687 24688           () validisa::npu_set_dma0_src_t24689 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24690 24691 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SRCcontrol124692 control224693           ()initisa::npu_set_dma0_src_t24694 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24695 24696 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SRC24697 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24698          ()uint64_tisa::npu_set_dma0_src_t24699 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24700 24701 uint64_tword24702 stdmemcpywordthissizeofword24703 returnword24704           () get_addrisa::npu_set_dma0_src_t24705 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

24706 24707 returnstatic_castuint64_taddr_hi32addr_lo24708           &( )set_addrisa::npu_set_dma0_src_t24709 CONSTEXPRnpu_set_dma0_src_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
24710 24711 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax24712 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax24713 returnthis24714 24715 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_dma0_src_t24716 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
24717 24718 stdstringstreamsaddr24719 saddrstdhex"0x"get_addr24720 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr24721 24722 endif24723 endif24724 24725 // DMA user channel 0 destination byte offset from DMA0_DST_REGION24726 structnpu_set_dma0_dst_t24727 24728 ifdef__cplusplus24729 private24730 endif24731 uint32_topcode10//  opcode24732 uint32_treserved0424733 uint32_tcontrol2//  control24734 uint32_taddr_hi8//  address extension24735 uint32_treserved1824736 uint32_taddr_lo32//  address offset24737 ifdef__cplusplus24738 public        ( ) :npu_set_dma0_dst_tisa::npu_set_dma0_dst_t24739 npu_set_dma0_dst_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

24740 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_DSTreserved024741 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24742 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved124743 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax24744 24745          () :npu_set_dma0_dst_tisa::npu_set_dma0_dst_t24746 CONSTEXPRnpu_set_dma0_dst_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24747 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_DSTreserved024748 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo24749 24750           () validisa::npu_set_dma0_dst_t24751 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24752 24753 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_DSTcontrol124754 control224755           ()initisa::npu_set_dma0_dst_t24756 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24757 24758 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_DST24759 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24760          ()uint64_tisa::npu_set_dma0_dst_t24761 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24762 24763 uint64_tword24764 stdmemcpywordthissizeofword24765 returnword24766           () get_addrisa::npu_set_dma0_dst_t24767 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

24768 24769 returnstatic_castuint64_taddr_hi32addr_lo24770           &( )set_addrisa::npu_set_dma0_dst_t24771 CONSTEXPRnpu_set_dma0_dst_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
24772 24773 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax24774 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax24775 returnthis24776 24777 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_dma0_dst_t24778 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
24779 24780 stdstringstreamsaddr24781 saddrstdhex"0x"get_addr24782 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr24783 24784 endif24785 endif24786 24787 // DMA user channel 0 transfer length in bytes for each 1D transfer24788 structnpu_set_dma0_len_t24789 24790 ifdef__cplusplus24791 private24792 endif24793 uint32_topcode10//  opcode24794 uint32_treserved0424795 uint32_tcontrol2//  control24796 uint32_taddr_hi8//  address extension24797 uint32_treserved1824798 uint32_taddr_lo32//  address offset24799 ifdef__cplusplus24800 public        ( ) :npu_set_dma0_len_tisa::npu_set_dma0_len_t24801 npu_set_dma0_len_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

24802 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_LENreserved024803 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24804 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved124805 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax24806 24807          () :npu_set_dma0_len_tisa::npu_set_dma0_len_t24808 CONSTEXPRnpu_set_dma0_len_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24809 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_LENreserved024810 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo24811 24812           () validisa::npu_set_dma0_len_t24813 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24814 24815 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_LENcontrol124816 control224817           ()initisa::npu_set_dma0_len_t24818 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24819 24820 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_LEN24821 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24822          ()uint64_tisa::npu_set_dma0_len_t24823 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24824 24825 uint64_tword24826 stdmemcpywordthissizeofword24827 returnword24828           () get_addrisa::npu_set_dma0_len_t24829 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

24830 24831 returnstatic_castuint64_taddr_hi32addr_lo24832           &( )set_addrisa::npu_set_dma0_len_t24833 CONSTEXPRnpu_set_dma0_len_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
24834 24835 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax24836 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax24837 returnthis24838 24839 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_dma0_len_t24840 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
24841 24842 stdstringstreamsaddr24843 saddrstdhex"0x"get_addr24844 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr24845 24846 endif24847 endif24848 24849 // byte distance to skip after each inner (1D) transfer (2D/3D mode) (any alignment)24850 structnpu_set_dma0_skip0_t24851 24852 ifdef__cplusplus24853 private24854 endif24855 uint32_topcode10//  opcode24856 uint32_treserved0424857 uint32_tcontrol2//  control24858 uint32_taddr_hi8//  address extension24859 uint32_treserved1824860 uint32_taddr_lo32//  address offset24861 ifdef__cplusplus24862 public        ( ) :npu_set_dma0_skip0_tisa::npu_set_dma0_skip0_t24863 npu_set_dma0_skip0_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

24864 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SKIP0reserved024865 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24866 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved124867 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax24868 24869          () :npu_set_dma0_skip0_tisa::npu_set_dma0_skip0_t24870 CONSTEXPRnpu_set_dma0_skip0_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24871 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SKIP0reserved024872 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo24873 24874           () validisa::npu_set_dma0_skip0_t24875 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24876 24877 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SKIP0control124878 control224879           ()initisa::npu_set_dma0_skip0_t24880 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24881 24882 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SKIP024883 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24884          ()uint64_tisa::npu_set_dma0_skip0_t24885 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24886 24887 uint64_tword24888 stdmemcpywordthissizeofword24889 returnword24890           () get_addrisa::npu_set_dma0_skip0_t24891 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

24892 24893 returnstatic_castuint64_taddr_hi32addr_lo24894           &( )set_addrisa::npu_set_dma0_skip0_t24895 CONSTEXPRnpu_set_dma0_skip0_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
24896 24897 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax24898 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax24899 returnthis24900 24901 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_dma0_skip0_t24902 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
24903 24904 stdstringstreamsaddr24905 saddrstdhex"0x"get_addr24906 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr24907 24908 endif24909 endif24910 24911 // byte distance to skip after each 2D transfer (3D mode) (any alignment)24912 structnpu_set_dma0_skip1_t24913 24914 ifdef__cplusplus24915 private24916 endif24917 uint32_topcode10//  opcode24918 uint32_treserved0424919 uint32_tcontrol2//  control24920 uint32_taddr_hi8//  address extension24921 uint32_treserved1824922 uint32_taddr_lo32//  address offset24923 ifdef__cplusplus24924 public        ( ) :npu_set_dma0_skip1_tisa::npu_set_dma0_skip1_t24925 npu_set_dma0_skip1_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

24926 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SKIP1reserved024927 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24928 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved124929 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax24930 24931          () :npu_set_dma0_skip1_tisa::npu_set_dma0_skip1_t24932 CONSTEXPRnpu_set_dma0_skip1_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24933 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SKIP1reserved024934 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo24935 24936           () validisa::npu_set_dma0_skip1_t24937 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

24938 24939 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SKIP1control124940 control224941           ()initisa::npu_set_dma0_skip1_t24942 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

24943 24944 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_DMA0_SKIP124945 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24946          ()uint64_tisa::npu_set_dma0_skip1_t24947 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

24948 24949 uint64_tword24950 stdmemcpywordthissizeofword24951 returnword24952           () get_addrisa::npu_set_dma0_skip1_t24953 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

24954 24955 returnstatic_castuint64_taddr_hi32addr_lo24956           &( )set_addrisa::npu_set_dma0_skip1_t24957 CONSTEXPRnpu_set_dma0_skip1_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
24958 24959 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax24960 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax24961 returnthis24962 24963 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_dma0_skip1_t24964 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
24965 24966 stdstringstreamsaddr24967 saddrstdhex"0x"get_addr24968 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr24969 24970 endif24971 endif24972 24973 // IFM2 Tile 0 address24974 structnpu_set_ifm2_base0_t24975 24976 ifdef__cplusplus24977 private24978 endif24979 uint32_topcode10//  opcode24980 uint32_treserved0424981 uint32_tcontrol2//  control24982 uint32_taddr_hi8//  address extension24983 uint32_treserved1824984 uint32_taddr_lo32//  address offset24985 ifdef__cplusplus24986 public        ( ) :npu_set_ifm2_base0_tisa::npu_set_ifm2_base0_t24987 npu_set_ifm2_base0_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

24988 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE0reserved024989 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL24990 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved124991 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax24992 24993          () :npu_set_ifm2_base0_tisa::npu_set_ifm2_base0_t24994 CONSTEXPRnpu_set_ifm2_base0_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

24995 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE0reserved024996 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo24997 24998           () validisa::npu_set_ifm2_base0_t24999 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

25000 25001 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE0control125002 control225003           ()initisa::npu_set_ifm2_base0_t25004 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

25005 25006 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE025007 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25008          ()uint64_tisa::npu_set_ifm2_base0_t25009 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

25010 25011 uint64_tword25012 stdmemcpywordthissizeofword25013 returnword25014           () get_addrisa::npu_set_ifm2_base0_t25015 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

25016 25017 returnstatic_castuint64_taddr_hi32addr_lo25018           &( )set_addrisa::npu_set_ifm2_base0_t25019 CONSTEXPRnpu_set_ifm2_base0_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
25020 25021 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax25022 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax25023 returnthis25024 25025 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_base0_t25026 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
25027 25028 stdstringstreamsaddr25029 saddrstdhex"0x"get_addr25030 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr25031 25032 endif25033 endif25034 25035 // IFM2 Tile 1 address25036 structnpu_set_ifm2_base1_t25037 25038 ifdef__cplusplus25039 private25040 endif25041 uint32_topcode10//  opcode25042 uint32_treserved0425043 uint32_tcontrol2//  control25044 uint32_taddr_hi8//  address extension25045 uint32_treserved1825046 uint32_taddr_lo32//  address offset25047 ifdef__cplusplus25048 public        ( ) :npu_set_ifm2_base1_tisa::npu_set_ifm2_base1_t25049 npu_set_ifm2_base1_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

25050 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE1reserved025051 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25052 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved125053 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax25054 25055          () :npu_set_ifm2_base1_tisa::npu_set_ifm2_base1_t25056 CONSTEXPRnpu_set_ifm2_base1_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

25057 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE1reserved025058 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo25059 25060           () validisa::npu_set_ifm2_base1_t25061 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

25062 25063 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE1control125064 control225065           ()initisa::npu_set_ifm2_base1_t25066 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

25067 25068 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE125069 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25070          ()uint64_tisa::npu_set_ifm2_base1_t25071 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

25072 25073 uint64_tword25074 stdmemcpywordthissizeofword25075 returnword25076           () get_addrisa::npu_set_ifm2_base1_t25077 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

25078 25079 returnstatic_castuint64_taddr_hi32addr_lo25080           &( )set_addrisa::npu_set_ifm2_base1_t25081 CONSTEXPRnpu_set_ifm2_base1_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
25082 25083 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax25084 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax25085 returnthis25086 25087 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_base1_t25088 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
25089 25090 stdstringstreamsaddr25091 saddrstdhex"0x"get_addr25092 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr25093 25094 endif25095 endif25096 25097 // IFM2 Tile 2 address25098 structnpu_set_ifm2_base2_t25099 25100 ifdef__cplusplus25101 private25102 endif25103 uint32_topcode10//  opcode25104 uint32_treserved0425105 uint32_tcontrol2//  control25106 uint32_taddr_hi8//  address extension25107 uint32_treserved1825108 uint32_taddr_lo32//  address offset25109 ifdef__cplusplus25110 public        ( ) :npu_set_ifm2_base2_tisa::npu_set_ifm2_base2_t25111 npu_set_ifm2_base2_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

25112 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE2reserved025113 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25114 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved125115 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax25116 25117          () :npu_set_ifm2_base2_tisa::npu_set_ifm2_base2_t25118 CONSTEXPRnpu_set_ifm2_base2_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

25119 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE2reserved025120 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo25121 25122           () validisa::npu_set_ifm2_base2_t25123 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

25124 25125 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE2control125126 control225127           ()initisa::npu_set_ifm2_base2_t25128 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

25129 25130 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE225131 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25132          ()uint64_tisa::npu_set_ifm2_base2_t25133 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

25134 25135 uint64_tword25136 stdmemcpywordthissizeofword25137 returnword25138           () get_addrisa::npu_set_ifm2_base2_t25139 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

25140 25141 returnstatic_castuint64_taddr_hi32addr_lo25142           &( )set_addrisa::npu_set_ifm2_base2_t25143 CONSTEXPRnpu_set_ifm2_base2_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
25144 25145 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax25146 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax25147 returnthis25148 25149 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_base2_t25150 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
25151 25152 stdstringstreamsaddr25153 saddrstdhex"0x"get_addr25154 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr25155 25156 endif25157 endif25158 25159 // IFM2 Tile 3 address25160 structnpu_set_ifm2_base3_t25161 25162 ifdef__cplusplus25163 private25164 endif25165 uint32_topcode10//  opcode25166 uint32_treserved0425167 uint32_tcontrol2//  control25168 uint32_taddr_hi8//  address extension25169 uint32_treserved1825170 uint32_taddr_lo32//  address offset25171 ifdef__cplusplus25172 public        ( ) :npu_set_ifm2_base3_tisa::npu_set_ifm2_base3_t25173 npu_set_ifm2_base3_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

25174 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE3reserved025175 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25176 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved125177 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax25178 25179          () :npu_set_ifm2_base3_tisa::npu_set_ifm2_base3_t25180 CONSTEXPRnpu_set_ifm2_base3_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

25181 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE3reserved025182 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo25183 25184           () validisa::npu_set_ifm2_base3_t25185 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

25186 25187 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE3control125188 control225189           ()initisa::npu_set_ifm2_base3_t25190 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

25191 25192 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_BASE325193 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25194          ()uint64_tisa::npu_set_ifm2_base3_t25195 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

25196 25197 uint64_tword25198 stdmemcpywordthissizeofword25199 returnword25200           () get_addrisa::npu_set_ifm2_base3_t25201 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

25202 25203 returnstatic_castuint64_taddr_hi32addr_lo25204           &( )set_addrisa::npu_set_ifm2_base3_t25205 CONSTEXPRnpu_set_ifm2_base3_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
25206 25207 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax25208 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax25209 returnthis25210 25211 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_base3_t25212 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
25213 25214 stdstringstreamsaddr25215 saddrstdhex"0x"get_addr25216 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr25217 25218 endif25219 endif25220 25221 // IFM2 byte stride between horizontal values25222 structnpu_set_ifm2_stride_x_t25223 25224 ifdef__cplusplus25225 private25226 endif25227 uint32_topcode10//  opcode25228 uint32_treserved0425229 uint32_tcontrol2//  control25230 uint32_taddr_hi8//  address extension25231 uint32_treserved1825232 uint32_taddr_lo32//  address offset25233 ifdef__cplusplus25234 public        ( ) :npu_set_ifm2_stride_x_tisa::npu_set_ifm2_stride_x_t25235 npu_set_ifm2_stride_x_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

25236 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_Xreserved025237 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25238 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved125239 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax25240 25241          () :npu_set_ifm2_stride_x_tisa::npu_set_ifm2_stride_x_t25242 CONSTEXPRnpu_set_ifm2_stride_x_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

25243 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_Xreserved025244 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo25245 25246           () validisa::npu_set_ifm2_stride_x_t25247 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

25248 25249 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_Xcontrol125250 control225251           ()initisa::npu_set_ifm2_stride_x_t25252 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

25253 25254 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_X25255 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25256          ()uint64_tisa::npu_set_ifm2_stride_x_t25257 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

25258 25259 uint64_tword25260 stdmemcpywordthissizeofword25261 returnword25262           () get_addrisa::npu_set_ifm2_stride_x_t25263 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

25264 25265 returnstatic_castuint64_taddr_hi32addr_lo25266           &( )set_addrisa::npu_set_ifm2_stride_x_t25267 CONSTEXPRnpu_set_ifm2_stride_x_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
25268 25269 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax25270 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax25271 returnthis25272 25273 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_stride_x_t25274 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
25275 25276 stdstringstreamsaddr25277 saddrstdhex"0x"get_addr25278 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr25279 25280 endif25281 endif25282 25283 // IFM2 byte stride between vertical values25284 structnpu_set_ifm2_stride_y_t25285 25286 ifdef__cplusplus25287 private25288 endif25289 uint32_topcode10//  opcode25290 uint32_treserved0425291 uint32_tcontrol2//  control25292 uint32_taddr_hi8//  address extension25293 uint32_treserved1825294 uint32_taddr_lo32//  address offset25295 ifdef__cplusplus25296 public        ( ) :npu_set_ifm2_stride_y_tisa::npu_set_ifm2_stride_y_t25297 npu_set_ifm2_stride_y_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

25298 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_Yreserved025299 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25300 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved125301 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax25302 25303          () :npu_set_ifm2_stride_y_tisa::npu_set_ifm2_stride_y_t25304 CONSTEXPRnpu_set_ifm2_stride_y_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

25305 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_Yreserved025306 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo25307 25308           () validisa::npu_set_ifm2_stride_y_t25309 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

25310 25311 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_Ycontrol125312 control225313           ()initisa::npu_set_ifm2_stride_y_t25314 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

25315 25316 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_Y25317 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25318          ()uint64_tisa::npu_set_ifm2_stride_y_t25319 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

25320 25321 uint64_tword25322 stdmemcpywordthissizeofword25323 returnword25324           () get_addrisa::npu_set_ifm2_stride_y_t25325 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

25326 25327 returnstatic_castuint64_taddr_hi32addr_lo25328           &( )set_addrisa::npu_set_ifm2_stride_y_t25329 CONSTEXPRnpu_set_ifm2_stride_y_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
25330 25331 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax25332 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax25333 returnthis25334 25335 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_stride_y_t25336 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
25337 25338 stdstringstreamsaddr25339 saddrstdhex"0x"get_addr25340 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr25341 25342 endif25343 endif25344 25345 // IFM2 byte stride between channel blocks (of 16 bytes each block)25346 structnpu_set_ifm2_stride_c_t25347 25348 ifdef__cplusplus25349 private25350 endif25351 uint32_topcode10//  opcode25352 uint32_treserved0425353 uint32_tcontrol2//  control25354 uint32_taddr_hi8//  address extension25355 uint32_treserved1825356 uint32_taddr_lo32//  address offset25357 ifdef__cplusplus25358 public        ( ) :npu_set_ifm2_stride_c_tisa::npu_set_ifm2_stride_c_t25359 npu_set_ifm2_stride_c_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

25360 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_Creserved025361 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25362 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved125363 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax25364 25365          () :npu_set_ifm2_stride_c_tisa::npu_set_ifm2_stride_c_t25366 CONSTEXPRnpu_set_ifm2_stride_c_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

25367 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_Creserved025368 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo25369 25370           () validisa::npu_set_ifm2_stride_c_t25371 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

25372 25373 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_Ccontrol125374 control225375           ()initisa::npu_set_ifm2_stride_c_t25376 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

25377 25378 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_IFM2_STRIDE_C25379 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25380          ()uint64_tisa::npu_set_ifm2_stride_c_t25381 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

25382 25383 uint64_tword25384 stdmemcpywordthissizeofword25385 returnword25386           () get_addrisa::npu_set_ifm2_stride_c_t25387 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

25388 25389 returnstatic_castuint64_taddr_hi32addr_lo25390           &( )set_addrisa::npu_set_ifm2_stride_c_t25391 CONSTEXPRnpu_set_ifm2_stride_c_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
25392 25393 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax25394 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax25395 returnthis25396 25397 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_ifm2_stride_c_t25398 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
25399 25400 stdstringstreamsaddr25401 saddrstdhex"0x"get_addr25402 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr25403 25404 endif25405 endif25406 25407 // Weight stream byte offset in WEIGHT_REGION for core 125408 structnpu_set_weight1_base_t25409 25410 ifdef__cplusplus25411 private25412 endif25413 uint32_topcode10//  opcode25414 uint32_treserved0425415 uint32_tcontrol2//  control25416 uint32_taddr_hi8//  address extension25417 uint32_treserved1825418 uint32_taddr_lo32//  address offset25419 ifdef__cplusplus25420 public        ( ) :npu_set_weight1_base_tisa::npu_set_weight1_base_t25421 npu_set_weight1_base_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

25422 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT1_BASEreserved025423 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25424 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved125425 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax25426 25427          () :npu_set_weight1_base_tisa::npu_set_weight1_base_t25428 CONSTEXPRnpu_set_weight1_base_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

25429 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT1_BASEreserved025430 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo25431 25432           () validisa::npu_set_weight1_base_t25433 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

25434 25435 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT1_BASEcontrol125436 control225437           ()initisa::npu_set_weight1_base_t25438 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

25439 25440 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT1_BASE25441 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25442          ()uint64_tisa::npu_set_weight1_base_t25443 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

25444 25445 uint64_tword25446 stdmemcpywordthissizeofword25447 returnword25448           () get_addrisa::npu_set_weight1_base_t25449 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ;
          : ; 
# 
      :

25450 25451 returnstatic_castuint64_taddr_hi32addr_lo25452           &( )set_addrisa::npu_set_weight1_base_t25453 CONSTEXPRnpu_set_weight1_base_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
25454 25455 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax25456 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax25457 returnthis25458 25459 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_weight1_base_t25460 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
25461 25462 stdstringstreamsaddr25463 saddrstdhex"0x"get_addr25464 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr25465 25466 endif25467 endif25468 25469 // Weight stream byte length for core 125470 structnpu_set_weight1_length_t25471 25472 ifdef__cplusplus25473 private25474 endif25475 uint32_topcode10//  opcode25476 uint32_treserved0425477 uint32_tcontrol2//  control25478 uint32_treserved11625479 uint32_tlength32//  Weight stream byte length25480 ifdef__cplusplus25481 public        ( ) :npu_set_weight1_length_tisa::npu_set_weight1_length_t25482 npu_set_weight1_length_tuint32_t_length            (<>(::::)), (0),
            (<>(::::)), (0), ()
        {
        }

25483 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT1_LENGTHreserved025484 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLreserved1length_length25485 25486          () :npu_set_weight1_length_tisa::npu_set_weight1_length_t25487 CONSTEXPRnpu_set_weight1_length_t            (<>(::::)), (0),
            (<>(::::)), (0), (0)
        {
        }

25488 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT1_LENGTHreserved025489 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLreserved1length25490 25491           () validisa::npu_set_weight1_length_t25492 CONSTEXPRboolvalidconst        {
              == <>(::::) &&
                    >=  &&  <= ;
        }

25493 25494 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT1_LENGTH25495 control1control225496           ()initisa::npu_set_weight1_length_t25497 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

25498 25499 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_WEIGHT1_LENGTH25500 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25501          ()uint64_tisa::npu_set_weight1_length_t25502 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

25503 25504 uint64_tword25505 stdmemcpywordthissizeofword25506 returnword25507          :: () get_opcodeisa::npu_set_weight1_length_t25508 CONSTEXPRNPU_NAMESPACEcmd1_opcodeget_opcodeconst        {
             <::>();
        }

25509 25510 returnstatic_castNPU_NAMESPACEcmd1_opcodeopcode25511           &(:: )set_opcodeisa::npu_set_weight1_length_t25512 CONSTEXPRnpu_set_weight1_length_tset_opcodeNPU_NAMESPACEcmd1_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

25513 25514 opcodestatic_castuint16_tvalue1U10125515 returnthis25516          :: () get_controlisa::npu_set_weight1_length_t25517 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

25518 25519 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol25520           &(:: )set_controlisa::npu_set_weight1_length_t25521 CONSTEXPRnpu_set_weight1_length_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

25522 25523 controlstatic_castuint8_tvalue1U2125524 returnthis25525           () get_lengthisa::npu_set_weight1_length_t25526 CONSTEXPRuint32_tget_lengthconst        {
             <>();
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ; 
          : ;
          : ; 
# 
      :

25527 25528 returnstatic_castuint32_tlength25529           &( )set_lengthisa::npu_set_weight1_length_t25530 CONSTEXPRnpu_set_weight1_length_tset_lengthuint32_tvalue        {
             = ;
             *;
        }
25531 25532 lengthvalue25533 returnthis25534 25535 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_weight1_length_t25536 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
25537 25538 fieldspush_backstdmake_pairstdstringstdstring"length"stdto_stringlength25539 25540 endif25541 endif25542 25543 // Scale and bias stream input byte offset from SCALE_REGION for core 125544 structnpu_set_scale1_base_t25545 25546 ifdef__cplusplus25547 private25548 endif25549 uint32_topcode10//  opcode25550 uint32_treserved0425551 uint32_tcontrol2//  control25552 uint32_taddr_hi8//  address extension25553 uint32_treserved1825554 uint32_taddr_lo32//  address offset25555 ifdef__cplusplus25556 public        ( ) :npu_set_scale1_base_tisa::npu_set_scale1_base_t25557 npu_set_scale1_base_tuint64_t_addr            (<>(::::)), (0),
            (<>(::::)),
            (<>(( >> ) & ::<>::())), (0),
            (<>(()&::<>::()))
        {
        }

25558 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE1_BASEreserved025559 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25560 addr_histatic_castuint8_t_addr32stdnumeric_limitsuint64_tmaxreserved125561 addr_lostatic_castuint32_t_addrstdnumeric_limitsuint64_tmax25562 25563          () :npu_set_scale1_base_tisa::npu_set_scale1_base_t25564 CONSTEXPRnpu_set_scale1_base_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

25565 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE1_BASEreserved025566 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLaddr_hireserved1addr_lo25567 25568           () validisa::npu_set_scale1_base_t25569 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

25570 25571 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE1_BASEcontrol125572 control225573           ()initisa::npu_set_scale1_base_t25574 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

25575 25576 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE1_BASE25577 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25578          ()uint64_tisa::npu_set_scale1_base_t25579 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

25580 25581 uint64_tword25582 stdmemcpywordthissizeofword25583 returnword25584           () get_addrisa::npu_set_scale1_base_t25585 CONSTEXPRuint64_tget_addrconst        {
             (<>() << ) | ;
        }

# 

#
#
    };
    
     
    {
# 
      :
#
          : ; 
          : ;
          : ; 
          : ;
          : ; 
          : ;
# 
      :

25586 25587 returnstatic_castuint64_taddr_hi32addr_lo25588           &( )set_addrisa::npu_set_scale1_base_t25589 CONSTEXPRnpu_set_scale1_base_tset_addruint64_tvalue        {
             = <>(()&::<>::());
             = <>(( >> ) & ::<>::());
             *;
        }
25590 25591 addr_lostatic_castuint32_tvaluestdnumeric_limitsuint64_tmax25592 addr_histatic_castuint8_tvalue32stdnumeric_limitsuint64_tmax25593 returnthis25594 25595 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_scale1_base_t25596 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            :: ;
             << :: <<  << ();
            .(::<::, ::>(, .()));
        }
25597 25598 stdstringstreamsaddr25599 saddrstdhex"0x"get_addr25600 fieldspush_backstdmake_pairstdstringstdstring"addr"saddrstr25601 25602 endif25603 endif25604 25605 // Scale and bias stream input byte length for core 125606 structnpu_set_scale1_length_t25607 25608 ifdef__cplusplus25609 private25610 endif25611 uint32_topcode10//  opcode25612 uint32_treserved0425613 uint32_tcontrol2//  control25614 uint32_treserved11625615 uint32_tlength20//  Scale and bias stream byte length25616 uint32_treserved21225617 ifdef__cplusplus25618 public        ( ) :npu_set_scale1_length_tisa::npu_set_scale1_length_t25619 npu_set_scale1_length_tuint32_t_length            (<>(::::)), (0),
            (<>(::::)), (0),
            ( & (( << ) - )), (0)
        {
        }

25620 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE1_LENGTHreserved025621 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLreserved125622 length_length1U201reserved225623 25624          () :npu_set_scale1_length_tisa::npu_set_scale1_length_t25625 CONSTEXPRnpu_set_scale1_length_t            (<>(::::)), (0),
            (<>(::::)), (0), (0), (0)
        {
        }

25626 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE1_LENGTHreserved025627 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRLreserved1lengthreserved225628 25629           () validisa::npu_set_scale1_length_t25630 CONSTEXPRboolvalidconst        {
              == <>(::::) &&  >=  &&
                    <= ;
        }

25631 25632 returnopcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE1_LENGTHcontrol125633 control225634           ()initisa::npu_set_scale1_length_t25635 CONSTEXPRvoidinit        {
              = <>(::::);
             = <>(::::);
        }

25636 25637 opcodestatic_castuint16_tNPU_NAMESPACEcmd1_opcodeNPU_SET_SCALE1_LENGTH25638 controlstatic_castuint8_tNPU_NAMESPACEcmd_ctrlCMD1_CTRL25639          ()uint64_tisa::npu_set_scale1_length_t25640 operatoruint64_t        {
             ;
            ::(&, , ());
             ;
        }

25641 25642 uint64_tword25643 stdmemcpywordthissizeofword25644 returnword25645          :: () get_opcodeisa::npu_set_scale1_length_t25646 CONSTEXPRNPU_NAMESPACEcmd1_opcodeget_opcodeconst        {
             <::>();
        }

25647 25648 returnstatic_castNPU_NAMESPACEcmd1_opcodeopcode25649           &(:: )set_opcodeisa::npu_set_scale1_length_t25650 CONSTEXPRnpu_set_scale1_length_tset_opcodeNPU_NAMESPACEcmd1_opcodevalue        {
             = <>() & (( << ) - );
             *;
        }

25651 25652 opcodestatic_castuint16_tvalue1U10125653 returnthis25654          :: () get_controlisa::npu_set_scale1_length_t25655 CONSTEXPRNPU_NAMESPACEcmd_ctrlget_controlconst        {
             <::>();
        }

25656 25657 returnstatic_castNPU_NAMESPACEcmd_ctrlcontrol25658           &(:: )set_controlisa::npu_set_scale1_length_t25659 CONSTEXPRnpu_set_scale1_length_tset_controlNPU_NAMESPACEcmd_ctrlvalue        {
             = <>() & (( << ) - );
             *;
        }

25660 25661 controlstatic_castuint8_tvalue1U2125662 returnthis25663           () get_lengthisa::npu_set_scale1_length_t25664 CONSTEXPRuint32_tget_lengthconst        {
             <>();
        }

# 

#
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    };
# 
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#
25665 25666 returnstatic_castuint32_tlength25667           &( )set_lengthisa::npu_set_scale1_length_t25668 CONSTEXPRnpu_set_scale1_length_tset_lengthuint32_tvalue        {
             =  & (( << ) - );
             *;
        }
25669 25670 lengthvalue1U20125671 returnthis25672 25673 ifdefNPU_DISASSEMBLE         (::<::<::, ::>> &) disassembleisa::npu_set_scale1_length_t25674 voiddisassemblestdvectorstdpairstdstringstdstringfieldsconst        {
            .(::<::, ::>(, ::()));
        }
25675 25676 fieldspush_backstdmake_pairstdstringstdstring"length"stdto_stringlength25677 25678 endif25679 endif25680 25681 ifdef__cplusplus25682 25683 endif25684 defineNPU_OP_STRUCTS25685 NPU_OP_stop25686 NPU_OP_irq25687 NPU_OP_conv25688 NPU_OP_depthwise25689 NPU_OP_pool25690 NPU_OP_elementwise25691 NPU_OP_dma_start25692 NPU_OP_dma_wait25693 NPU_OP_kernel_wait25694 NPU_OP_pmu_mask25695 25696 defineNPU_SET_STRUCTS25697 NPU_SET_ifm_pad_top25698 NPU_SET_ifm_pad_left25699 NPU_SET_ifm_pad_right25700 NPU_SET_ifm_pad_bottom25701 NPU_SET_ifm_depth_m125702 NPU_SET_ifm_precision25703 NPU_SET_ifm_upscale25704 NPU_SET_ifm_zero_point25705 NPU_SET_ifm_width0_m125706 NPU_SET_ifm_height0_m125707 NPU_SET_ifm_height1_m125708 NPU_SET_ifm_ib_end25709 NPU_SET_ifm_region25710 NPU_SET_ofm_width_m125711 NPU_SET_ofm_height_m125712 NPU_SET_ofm_depth_m125713 NPU_SET_ofm_precision25714 NPU_SET_ofm_blk_width_m125715 NPU_SET_ofm_blk_height_m125716 NPU_SET_ofm_blk_depth_m125717 NPU_SET_ofm_zero_point25718 NPU_SET_ofm_width0_m125719 NPU_SET_ofm_height0_m125720 NPU_SET_ofm_height1_m125721 NPU_SET_ofm_region25722 NPU_SET_kernel_width_m125723 NPU_SET_kernel_height_m125724 NPU_SET_kernel_stride25725 NPU_SET_parallel_mode25726 NPU_SET_acc_format25727 NPU_SET_activation25728 NPU_SET_activation_min25729 NPU_SET_activation_max25730 NPU_SET_weight_region25731 NPU_SET_scale_region25732 NPU_SET_ab_start25733 NPU_SET_blockdep25734 NPU_SET_dma0_src_region25735 NPU_SET_dma0_dst_region25736 NPU_SET_dma0_size025737 NPU_SET_dma0_size125738 NPU_SET_ifm2_broadcast25739 NPU_SET_ifm2_scalar25740 NPU_SET_ifm2_precision25741 NPU_SET_ifm2_zero_point25742 NPU_SET_ifm2_width0_m125743 NPU_SET_ifm2_height0_m125744 NPU_SET_ifm2_height1_m125745 NPU_SET_ifm2_ib_start25746 NPU_SET_ifm2_region25747 NPU_SET_ifm_base025748 NPU_SET_ifm_base125749 NPU_SET_ifm_base225750 NPU_SET_ifm_base325751 NPU_SET_ifm_stride_x25752 NPU_SET_ifm_stride_y25753 NPU_SET_ifm_stride_c25754 NPU_SET_ofm_base025755 NPU_SET_ofm_base125756 NPU_SET_ofm_base225757 NPU_SET_ofm_base325758 NPU_SET_ofm_stride_x25759 NPU_SET_ofm_stride_y25760 NPU_SET_ofm_stride_c25761 NPU_SET_weight_base25762 NPU_SET_weight_length25763 NPU_SET_scale_base25764 NPU_SET_scale_length25765 NPU_SET_ofm_scale25766 NPU_SET_opa_scale25767 NPU_SET_opb_scale25768 NPU_SET_dma0_src25769 NPU_SET_dma0_dst25770 NPU_SET_dma0_len25771 NPU_SET_dma0_skip025772 NPU_SET_dma0_skip125773 NPU_SET_ifm2_base025774 NPU_SET_ifm2_base125775 NPU_SET_ifm2_base225776 NPU_SET_ifm2_base325777 NPU_SET_ifm2_stride_x25778 NPU_SET_ifm2_stride_y25779 NPU_SET_ifm2_stride_c25780 NPU_SET_weight1_base25781 NPU_SET_weight1_length25782 NPU_SET_scale1_base25783 NPU_SET_scale1_length25784 25785 defineEXPAND_ACC_FORMATFUNCSEPFUNCacc_formatI32SEPFUNCacc_formatI40SEPFUNCacc_formatF1625786 25787 defineEXPAND_ACTIVATION_CLIP_RANGEFUNCSEP25788 FUNCactivation_clip_rangeOFM_PRECISION25789 SEPFUNCactivation_clip_rangeFORCE_UINT8SEPFUNCactivation_clip_rangeFORCE_INT825790 SEPFUNCactivation_clip_rangeFORCE_INT1625791 25792 defineEXPAND_ACTIVATION_FORMATFUNCSEPFUNCactivation_formatNHWCSEPFUNCactivation_formatNHCWB1625793 25794 defineEXPAND_ACTIVATION_FUNCTIONFUNCSEP25795 FUNCactivation_functionRELU25796 SEPFUNCactivation_functionTANHSEPFUNCactivation_functionSIGMOIDSEPFUNCactivation_functionTABLE_025797 SEPFUNCactivation_functionTABLE_1SEPFUNCactivation_functionTABLE_225798 SEPFUNCactivation_functionTABLE_3SEPFUNCactivation_functionTABLE_425799 SEPFUNCactivation_functionTABLE_5SEPFUNCactivation_functionTABLE_625800 SEPFUNCactivation_functionTABLE_725801 25802 defineEXPAND_ACTIVATION_PRECISIONFUNCSEP25803 FUNCactivation_precisionB825804 SEPFUNCactivation_precisionB16SEPFUNCactivation_precisionB32SEPFUNCactivation_precisionB6425805 25806 defineEXPAND_ACTIVATION_TYPEFUNCSEPFUNCactivation_typeUNSIGNEDSEPFUNCactivation_typeSIGNED25807 25808 defineEXPAND_AXI_MEM_ENCODINGFUNCSEP25809 FUNCaxi_mem_encodingDEVICE_NON_BUFFERABLE25810 SEPFUNCaxi_mem_encodingDEVICE_BUFFERABLESEPFUNCaxi_mem_encodingNORMAL_NON_CACHEABLE_NON_BUFFERABLE25811 SEPFUNCaxi_mem_encodingNORMAL_NON_CACHEABLE_BUFFERABLE25812 SEPFUNCaxi_mem_encodingWRITE_THROUGH_NO_ALLOCATE25813 SEPFUNCaxi_mem_encodingWRITE_THROUGH_READ_ALLOCATE25814 SEPFUNCaxi_mem_encodingWRITE_THROUGH_WRITE_ALLOCATE25815 SEPFUNCaxi_mem_encodingWRITE_THROUGH_READ_AND_WRITE_ALLOCATE25816 SEPFUNCaxi_mem_encodingWRITE_BACK_NO_ALLOCATE25817 SEPFUNCaxi_mem_encodingWRITE_BACK_READ_ALLOCATE25818 SEPFUNCaxi_mem_encodingWRITE_BACK_WRITE_ALLOCATE25819 SEPFUNCaxi_mem_encodingWRITE_BACK_READ_AND_WRITE_ALLOCATE25820 25821 defineEXPAND_BROADCAST_MODEFUNCSEPFUNCbroadcast_modeDISABLESEPFUNCbroadcast_modeENABLE25822 25823 defineEXPAND_CMD0_OPCODEFUNCSEP25824 FUNCcmd0_opcodeNPU_OP_STOP25825 SEPFUNCcmd0_opcodeNPU_OP_IRQSEPFUNCcmd0_opcodeNPU_OP_CONVSEPFUNC25826 cmd0_opcodeNPU_OP_DEPTHWISESEPFUNCcmd0_opcodeNPU_OP_POOLSEPFUNCcmd0_opcodeNPU_OP_ELEMENTWISE25827 SEPFUNCcmd0_opcodeNPU_OP_DMA_STARTSEPFUNCcmd0_opcodeNPU_OP_DMA_WAITSEPFUNC25828 cmd0_opcodeNPU_OP_KERNEL_WAITSEPFUNCcmd0_opcodeNPU_OP_PMU_MASKSEPFUNCcmd0_opcode25829 NPU_SET_IFM_PAD_TOP25830 SEPFUNCcmd0_opcodeNPU_SET_IFM_PAD_LEFTSEPFUNCcmd0_opcodeNPU_SET_IFM_PAD_RIGHTSEPFUNC25831 cmd0_opcodeNPU_SET_IFM_PAD_BOTTOMSEPFUNCcmd0_opcode25832 NPU_SET_IFM_DEPTH_M1SEPFUNCcmd0_opcode25833 NPU_SET_IFM_PRECISION25834 SEPFUNCcmd0_opcodeNPU_SET_IFM_UPSCALESEPFUNCcmd0_opcodeNPU_SET_IFM_ZERO_POINTSEPFUNC25835 cmd0_opcodeNPU_SET_IFM_WIDTH0_M1SEPFUNCcmd0_opcodeNPU_SET_IFM_HEIGHT0_M125836 SEPFUNCcmd0_opcodeNPU_SET_IFM_HEIGHT1_M1SEPFUNCcmd0_opcodeNPU_SET_IFM_IB_ENDSEPFUNC25837 cmd0_opcodeNPU_SET_IFM_REGIONSEPFUNCcmd0_opcodeNPU_SET_OFM_WIDTH_M125838 SEPFUNCcmd0_opcodeNPU_SET_OFM_HEIGHT_M1SEPFUNCcmd0_opcodeNPU_SET_OFM_DEPTH_M125839 SEPFUNCcmd0_opcodeNPU_SET_OFM_PRECISIONSEPFUNC25840 cmd0_opcodeNPU_SET_OFM_BLK_WIDTH_M1SEPFUNCcmd0_opcode25841 NPU_SET_OFM_BLK_HEIGHT_M125842 SEPFUNCcmd0_opcodeNPU_SET_OFM_BLK_DEPTH_M1SEPFUNC25843 cmd0_opcodeNPU_SET_OFM_ZERO_POINTSEPFUNCcmd0_opcodeNPU_SET_OFM_WIDTH0_M125844 SEPFUNCcmd0_opcodeNPU_SET_OFM_HEIGHT0_M1SEPFUNC25845 cmd0_opcode25846 NPU_SET_OFM_HEIGHT1_M1SEPFUNCcmd0_opcodeNPU_SET_OFM_REGION25847 SEPFUNCcmd0_opcodeNPU_SET_KERNEL_WIDTH_M1SEPFUNC25848 cmd0_opcode25849 NPU_SET_KERNEL_HEIGHT_M1SEPFUNCcmd0_opcodeNPU_SET_KERNEL_STRIDE25850 SEPFUNCcmd0_opcodeNPU_SET_PARALLEL_MODESEPFUNC25851 cmd0_opcode25852 NPU_SET_ACC_FORMATSEPFUNCcmd0_opcodeNPU_SET_ACTIVATION25853 SEPFUNCcmd0_opcode25854 NPU_SET_ACTIVATION_MINSEPFUNCcmd0_opcode25855 NPU_SET_ACTIVATION_MAX25856 SEPFUNCcmd0_opcodeNPU_SET_WEIGHT_REGIONSEPFUNC25857 cmd0_opcode25858 NPU_SET_SCALE_REGIONSEPFUNCcmd0_opcodeNPU_SET_AB_START25859 SEPFUNCcmd0_opcodeNPU_SET_BLOCKDEP25860 SEPFUNCcmd0_opcodeNPU_SET_DMA0_SRC_REGIONSEPFUNC25861 cmd0_opcode25862 NPU_SET_DMA0_DST_REGIONSEPFUNCcmd0_opcode25863 NPU_SET_DMA0_SIZE025864 SEPFUNCcmd0_opcodeNPU_SET_DMA0_SIZE1SEPFUNC25865 cmd0_opcode25866 NPU_SET_IFM2_BROADCASTSEP25867 FUNCcmd0_opcodeNPU_SET_IFM2_SCALARSEPFUNC25868 cmd0_opcode25869 NPU_SET_IFM2_PRECISIONSEP25870 FUNCcmd0_opcodeNPU_SET_IFM2_ZERO_POINTSEP25871 FUNCcmd0_opcode25872 NPU_SET_IFM2_WIDTH0_M1SEP25873 FUNCcmd0_opcode25874 NPU_SET_IFM2_HEIGHT0_M1SEP25875 FUNCcmd0_opcode25876 NPU_SET_IFM2_HEIGHT1_M125877 SEPFUNC25878 cmd0_opcode25879 NPU_SET_IFM2_IB_START25880 SEPFUNC25881 cmd0_opcode25882 NPU_SET_IFM2_REGION25883 25884 defineEXPAND_CMD1_OPCODEFUNCSEP25885 FUNCcmd1_opcodeNPU_SET_IFM_BASE025886 SEPFUNCcmd1_opcodeNPU_SET_IFM_BASE1SEPFUNCcmd1_opcodeNPU_SET_IFM_BASE225887 SEPFUNCcmd1_opcodeNPU_SET_IFM_BASE3SEPFUNCcmd1_opcodeNPU_SET_IFM_STRIDE_X25888 SEPFUNCcmd1_opcodeNPU_SET_IFM_STRIDE_YSEPFUNCcmd1_opcodeNPU_SET_IFM_STRIDE_CSEPFUNC25889 cmd1_opcodeNPU_SET_OFM_BASE0SEPFUNCcmd1_opcodeNPU_SET_OFM_BASE125890 SEPFUNCcmd1_opcodeNPU_SET_OFM_BASE2SEPFUNCcmd1_opcodeNPU_SET_OFM_BASE3SEPFUNC25891 cmd1_opcodeNPU_SET_OFM_STRIDE_XSEPFUNCcmd1_opcodeNPU_SET_OFM_STRIDE_Y25892 SEPFUNCcmd1_opcodeNPU_SET_OFM_STRIDE_CSEPFUNCcmd1_opcodeNPU_SET_WEIGHT_BASESEPFUNC25893 cmd1_opcodeNPU_SET_WEIGHT_LENGTHSEPFUNCcmd1_opcodeNPU_SET_SCALE_BASE25894 SEPFUNCcmd1_opcodeNPU_SET_SCALE_LENGTHSEPFUNCcmd1_opcodeNPU_SET_OFM_SCALE25895 SEPFUNCcmd1_opcodeNPU_SET_OPA_SCALESEPFUNCcmd1_opcodeNPU_SET_OPB_SCALE25896 SEPFUNCcmd1_opcodeNPU_SET_DMA0_SRCSEPFUNCcmd1_opcodeNPU_SET_DMA0_DST25897 SEPFUNCcmd1_opcodeNPU_SET_DMA0_LENSEPFUNCcmd1_opcodeNPU_SET_DMA0_SKIP025898 SEPFUNCcmd1_opcodeNPU_SET_DMA0_SKIP1SEPFUNC25899 cmd1_opcodeNPU_SET_IFM2_BASE0SEPFUNCcmd1_opcodeNPU_SET_IFM2_BASE125900 SEPFUNCcmd1_opcodeNPU_SET_IFM2_BASE2SEPFUNCcmd1_opcode25901 NPU_SET_IFM2_BASE325902 SEPFUNCcmd1_opcodeNPU_SET_IFM2_STRIDE_X25903 SEPFUNCcmd1_opcodeNPU_SET_IFM2_STRIDE_Y25904 SEPFUNCcmd1_opcodeNPU_SET_IFM2_STRIDE_C25905 SEPFUNCcmd1_opcodeNPU_SET_WEIGHT1_BASE25906 SEPFUNCcmd1_opcodeNPU_SET_WEIGHT1_LENGTH25907 SEPFUNCcmd1_opcodeNPU_SET_SCALE1_BASE25908 SEPFUNCcmd1_opcodeNPU_SET_SCALE1_LENGTH25909 25910 defineEXPAND_CMD_CTRLFUNCSEPFUNCcmd_ctrlCMD0_CTRLSEPFUNCcmd_ctrlCMD1_CTRL25911 25912 defineEXPAND_CUSTOM_DMAFUNCSEPFUNCcustom_dmaNOT_IMPLEMENTEDSEPFUNCcustom_dmaIMPLEMENTED25913 25914 defineEXPAND_DMA_FAULT_SRCFUNCSEPFUNCdma_fault_srcAXI_M0SEPFUNCdma_fault_srcAXI_M125915 25916 defineEXPAND_DMA_REGION_MODEFUNCSEPFUNCdma_region_modeEXTERNALSEPFUNCdma_region_modeINTERNAL25917 25918 defineEXPAND_DMA_STRIDE_MODEFUNCSEP25919 FUNCdma_stride_modeD1SEPFUNCdma_stride_modeD2SEPFUNCdma_stride_modeD325920 25921 defineEXPAND_ELEMENTWISE_MODEFUNCSEP25922 FUNCelementwise_modeMUL25923 SEPFUNCelementwise_modeADDSEPFUNCelementwise_modeSUBSEPFUNCelementwise_modeMIN25924 SEPFUNCelementwise_modeMAXSEPFUNCelementwise_modeLRELUSEPFUNCelementwise_modeABS25925 SEPFUNCelementwise_modeCLZSEPFUNCelementwise_modeSHRSEPFUNCelementwise_modeSHL25926 25927 defineEXPAND_FUNCTIONAL_SAFETYFUNCSEP25928 FUNCfunctional_safetyNOT_IMPLEMENTEDSEPFUNCfunctional_safetyIMPLEMENTED25929 25930 defineEXPAND_IFM2_OPERAND_ORDERFUNCSEPFUNCifm2_operand_orderORDER_BSEPFUNCifm2_operand_orderORDER_A25931 25932 defineEXPAND_IFM_SCALE_MODEFUNCSEP25933 FUNCifm_scale_modeOPA_OPB_16SEPFUNCifm_scale_modeOPA_32SEPFUNCifm_scale_modeOPB_3225934 25935 defineEXPAND_IFM_UPSCALE_MODEFUNCSEP25936 FUNCifm_upscale_modeNONESEPFUNCifm_upscale_modeNEARESTSEPFUNCifm_upscale_modeZEROS25937 25938 defineEXPAND_KERNEL_DECOMPOSITIONFUNCSEPFUNCkernel_decompositionD8X8SEPFUNCkernel_decompositionD4X425939 25940 defineEXPAND_KERNEL_DILATIONFUNCSEPFUNCkernel_dilationNONESEPFUNCkernel_dilationX225941 25942 defineEXPAND_MAX_BEATSFUNCSEPFUNCmax_beatsB64SEPFUNCmax_beatsB128SEPFUNCmax_beatsB25625943 25944 defineEXPAND_MEM_ATTRFUNCSEP25945 FUNCmem_attrAXI0_OUTSTANDING_COUNTER025946 SEPFUNCmem_attrAXI0_OUTSTANDING_COUNTER1SEPFUNCmem_attrAXI1_OUTSTANDING_COUNTER225947 SEPFUNCmem_attrAXI1_OUTSTANDING_COUNTER325948 25949 defineEXPAND_OFM_SCALE_MODEFUNCSEPFUNCofm_scale_modePER_CHANNELSEPFUNCofm_scale_modeGLOBAL25950 25951 defineEXPAND_PARALLEL_MODEFUNCSEPFUNCparallel_modeSINGLE_CORESEPFUNCparallel_modeDUAL_CORE_DEPTH25952 25953 defineEXPAND_PMU_AXI_CHANNELFUNCSEP25954 FUNCpmu_axi_channelRD_CMD25955 SEPFUNCpmu_axi_channelRD_IFMSEPFUNCpmu_axi_channelRD_WEIGHTSSEPFUNCpmu_axi_channelRD_SCALE_BIAS25956 SEPFUNCpmu_axi_channelRD_MEM2MEMSEPFUNCpmu_axi_channelWR_OFMSEPFUNCpmu_axi_channelWR_MEM2MEM25957 25958 defineEXPAND_PMU_EVENTFUNCSEP25959 FUNCpmu_eventNO_EVENT25960 SEPFUNCpmu_eventCYCLESEPFUNCpmu_eventNPU_IDLESEPFUNCpmu_eventCC_STALLED_ON_BLOCKDEPSEPFUNC25961 pmu_eventCC_STALLED_ON_SHRAM_RECONFIGSEPFUNCpmu_eventNPU_ACTIVESEPFUNCpmu_eventMAC_ACTIVE25962 SEPFUNCpmu_eventMAC_ACTIVE_8BITSEPFUNCpmu_eventMAC_ACTIVE_16BITSEPFUNC25963 pmu_eventMAC_DPU_ACTIVESEPFUNCpmu_eventMAC_STALLED_BY_WD_ACCSEPFUNCpmu_event25964 MAC_STALLED_BY_WD25965 SEPFUNCpmu_eventMAC_STALLED_BY_ACCSEPFUNCpmu_eventMAC_STALLED_BY_IBSEPFUNC25966 pmu_event25967 MAC_ACTIVE_32BITSEPFUNCpmu_event25968 MAC_STALLED_BY_INT_WSEPFUNCpmu_event25969 MAC_STALLED_BY_INT_ACCSEPFUNCpmu_event25970 AO_ACTIVE25971 SEPFUNCpmu_eventAO_ACTIVE_8BITSEPFUNCpmu_eventAO_ACTIVE_16BITSEPFUNC25972 pmu_eventAO_STALLED_BY_OFMP_OBSEPFUNCpmu_eventAO_STALLED_BY_OFMPSEP25973 FUNCpmu_eventAO_STALLED_BY_OBSEPFUNCpmu_eventAO_STALLED_BY_ACC_IBSEPFUNC25974 pmu_eventAO_STALLED_BY_ACCSEPFUNCpmu_eventAO_STALLED_BY_IBSEP25975 FUNCpmu_eventWD_ACTIVESEPFUNCpmu_eventWD_STALLEDSEPFUNCpmu_eventWD_STALLED_BY_WSSEPFUNC25976 pmu_eventWD_STALLED_BY_WD_BUFSEPFUNCpmu_event25977 WD_PARSE_ACTIVESEP25978 FUNCpmu_eventWD_PARSE_STALLEDSEPFUNCpmu_eventWD_PARSE_STALLED_INSEPFUNC25979 pmu_eventWD_PARSE_STALLED_OUTSEPFUNCpmu_event25980 WD_TRANS_WSSEP25981 FUNCpmu_eventWD_TRANS_WBSEPFUNCpmu_eventWD_TRANS_DW0SEPFUNC25982 pmu_eventWD_TRANS_DW1SEPFUNCpmu_event25983 AXI0_RD_TRANS_ACCEPTEDSEP25984 FUNCpmu_eventAXI0_RD_TRANS_COMPLETEDSEPFUNCpmu_eventAXI0_RD_DATA_BEAT_RECEIVEDSEPFUNC25985 pmu_eventAXI0_RD_TRAN_REQ_STALLEDSEPFUNCpmu_event25986 AXI0_WR_TRANS_ACCEPTEDSEP25987 FUNCpmu_eventAXI0_WR_TRANS_COMPLETED_MSEPFUNC25988 pmu_eventAXI0_WR_TRANS_COMPLETED_SSEP25989 FUNCpmu_eventAXI0_WR_DATA_BEAT_WRITTENSEPFUNC25990 pmu_eventAXI0_WR_TRAN_REQ_STALLEDSEP25991 FUNCpmu_eventAXI0_WR_DATA_BEAT_STALLEDSEPFUNC25992 pmu_event25993 AXI0_ENABLED_CYCLESSEPFUNCpmu_event25994 AXI0_RD_STALL_LIMITSEP25995 FUNCpmu_eventAXI0_WR_STALL_LIMITSEPFUNC25996 pmu_event25997 AXI_LATENCY_ANYSEPFUNCpmu_event25998 AXI_LATENCY_32SEP25999 FUNCpmu_event26000 AXI_LATENCY_64SEPFUNCpmu_event26001 AXI_LATENCY_128SEP26002 FUNCpmu_eventAXI_LATENCY_256SEPFUNC26003 pmu_event26004 AXI_LATENCY_512SEPFUNCpmu_event26005 AXI_LATENCY_1024SEP26006 FUNCpmu_eventECC_DMASEPFUNC26007 pmu_event26008 ECC_SB0SEPFUNCpmu_event26009 AXI1_RD_TRANS_ACCEPTEDSEP26010 FUNCpmu_eventAXI1_RD_TRANS_COMPLETEDSEPFUNC26011 pmu_eventAXI1_RD_DATA_BEAT_RECEIVEDSEP26012 FUNCpmu_eventAXI1_RD_TRAN_REQ_STALLEDSEPFUNC26013 pmu_eventAXI1_WR_TRANS_ACCEPTEDSEP26014 FUNCpmu_eventAXI1_WR_TRANS_COMPLETED_MSEPFUNC26015 pmu_event26016 AXI1_WR_TRANS_COMPLETED_SSEP26017 FUNCpmu_event26018 AXI1_WR_DATA_BEAT_WRITTENSEP26019 FUNCpmu_event26020 AXI1_WR_TRAN_REQ_STALLEDSEP26021 FUNC26022 pmu_event26023 AXI1_WR_DATA_BEAT_STALLEDSEP26024 FUNC26025 pmu_event26026 AXI1_ENABLED_CYCLESSEP26027 FUNC26028 pmu_event26029 AXI1_RD_STALL_LIMITSEP26030 FUNC26031 pmu_event26032 AXI1_WR_STALL_LIMIT26033 SEPFUNC26034 pmu_event26035 ECC_SB126036 26037 defineEXPAND_POOLING_MODEFUNCSEP26038 FUNCpooling_modeMAXSEPFUNCpooling_modeAVERAGESEPFUNCpooling_modeREDUCE_SUM26039 26040 defineEXPAND_PRIVILEGE_LEVELFUNCSEPFUNCprivilege_levelUSERSEPFUNCprivilege_levelPRIVILEGED26041 26042 defineEXPAND_ROUND_MODEFUNCSEPFUNCround_modeDBLSEPFUNCround_modeTRUNCATESEPFUNCround_modeNATURAL26043 26044 defineEXPAND_SECURITY_LEVELFUNCSEPFUNCsecurity_levelSECURESEPFUNCsecurity_levelNON_SECURE26045 26046 defineEXPAND_STATEFUNCSEPFUNCstateSTOPPEDSEPFUNCstateRUNNING26047 26048 defineEXPAND_WD_CORE_SLICE_STATEFUNCSEP26049 FUNCwd_core_slice_stateHEADERSEPFUNCwd_core_slice_statePALETTESEPFUNCwd_core_slice_stateWEIGHTS26050 26051 defineEXPAND_WD_CTRL_STATEFUNCSEP26052 FUNCwd_ctrl_stateIDLE26053 SEPFUNCwd_ctrl_stateDRAINSEPFUNCwd_ctrl_stateOFD_INITSEPFUNCwd_ctrl_stateOFD_RUN26054 26055 defineEXPAND_WEIGHT_ORDERFUNCSEPFUNCweight_orderDEPTH_FIRSTSEPFUNCweight_orderPART_KERNEL_FIRST26056 26057 ifdef__cplusplus26058 26059 endif26060 endif26061