1 /*
2  * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #include <string.h>
7 #include <sys/param.h>
8 #include "esp_types.h"
9 #include "esp_attr.h"
10 #include "esp_intr_alloc.h"
11 #include "esp_log.h"
12 #include "esp_err.h"
13 #include "esp_check.h"
14 #include "malloc.h"
15 #include "freertos/FreeRTOS.h"
16 #include "freertos/semphr.h"
17 #include "freertos/ringbuf.h"
18 #include "esp_private/critical_section.h"
19 #include "hal/uart_hal.h"
20 #include "hal/gpio_hal.h"
21 #include "hal/clk_tree_ll.h"
22 #include "soc/uart_periph.h"
23 #include "driver/uart.h"
24 #include "driver/gpio.h"
25 #include "driver/uart_select.h"
26 #include "esp_private/periph_ctrl.h"
27 #include "esp_clk_tree.h"
28 #include "sdkconfig.h"
29 #include "esp_rom_gpio.h"
30 #include "clk_ctrl_os.h"
31 
32 #ifdef CONFIG_UART_ISR_IN_IRAM
33 #define UART_ISR_ATTR     IRAM_ATTR
34 #define UART_MALLOC_CAPS  (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
35 #else
36 #define UART_ISR_ATTR
37 #define UART_MALLOC_CAPS  MALLOC_CAP_DEFAULT
38 #endif
39 
40 #define XOFF (0x13)
41 #define XON (0x11)
42 
43 static const char *UART_TAG = "uart";
44 
45 #define UART_EMPTY_THRESH_DEFAULT       (10)
46 #define UART_FULL_THRESH_DEFAULT        (120)
47 #define UART_TOUT_THRESH_DEFAULT        (10)
48 #define UART_CLKDIV_FRAG_BIT_WIDTH      (3)
49 #define UART_TX_IDLE_NUM_DEFAULT        (0)
50 #define UART_PATTERN_DET_QLEN_DEFAULT   (10)
51 #define UART_MIN_WAKEUP_THRESH          (UART_LL_MIN_WAKEUP_THRESH)
52 
53 #if SOC_UART_SUPPORT_WAKEUP_INT
54 #define UART_INTR_CONFIG_FLAG ((UART_INTR_RXFIFO_FULL) \
55                             | (UART_INTR_RXFIFO_TOUT) \
56                             | (UART_INTR_RXFIFO_OVF) \
57                             | (UART_INTR_BRK_DET) \
58                             | (UART_INTR_PARITY_ERR)) \
59                             | (UART_INTR_WAKEUP)
60 #else
61 #define UART_INTR_CONFIG_FLAG ((UART_INTR_RXFIFO_FULL) \
62                             | (UART_INTR_RXFIFO_TOUT) \
63                             | (UART_INTR_RXFIFO_OVF) \
64                             | (UART_INTR_BRK_DET) \
65                             | (UART_INTR_PARITY_ERR))
66 #endif
67 
68 
69 #define UART_ENTER_CRITICAL_SAFE(spinlock)   esp_os_enter_critical_safe(spinlock)
70 #define UART_EXIT_CRITICAL_SAFE(spinlock)    esp_os_exit_critical_safe(spinlock)
71 #define UART_ENTER_CRITICAL_ISR(spinlock)    esp_os_enter_critical_isr(spinlock)
72 #define UART_EXIT_CRITICAL_ISR(spinlock)     esp_os_exit_critical_isr(spinlock)
73 #define UART_ENTER_CRITICAL(spinlock)        esp_os_enter_critical(spinlock)
74 #define UART_EXIT_CRITICAL(spinlock)         esp_os_exit_critical(spinlock)
75 
76 
77 // Check actual UART mode set
78 #define UART_IS_MODE_SET(uart_number, mode) ((p_uart_obj[uart_number]->uart_mode == mode))
79 
80 #define UART_CONTEX_INIT_DEF(uart_num) {\
81     .hal.dev = UART_LL_GET_HW(uart_num),\
82     INIT_CRIT_SECTION_LOCK_IN_STRUCT(spinlock)\
83     .hw_enabled = false,\
84 }
85 
86 typedef struct {
87     uart_event_type_t type;        /*!< UART TX data type */
88     struct {
89         int brk_len;
90         size_t size;
91         uint8_t data[0];
92     } tx_data;
93 } uart_tx_data_t;
94 
95 typedef struct {
96     int wr;
97     int rd;
98     int len;
99     int *data;
100 } uart_pat_rb_t;
101 
102 typedef struct {
103     uart_port_t uart_num;               /*!< UART port number*/
104     int event_queue_size;               /*!< UART event queue size*/
105     intr_handle_t intr_handle;          /*!< UART interrupt handle*/
106     uart_mode_t uart_mode;              /*!< UART controller actual mode set by uart_set_mode() */
107     bool coll_det_flg;                  /*!< UART collision detection flag */
108     bool rx_always_timeout_flg;         /*!< UART always detect rx timeout flag */
109     int rx_buffered_len;                /*!< UART cached data length */
110     int rx_buf_size;                    /*!< RX ring buffer size */
111     bool rx_buffer_full_flg;            /*!< RX ring buffer full flag. */
112     uint32_t rx_cur_remain;             /*!< Data number that waiting to be read out in ring buffer item*/
113     uint8_t *rx_ptr;                    /*!< pointer to the current data in ring buffer*/
114     uint8_t *rx_head_ptr;               /*!< pointer to the head of RX item*/
115     uint8_t rx_data_buf[SOC_UART_FIFO_LEN]; /*!< Data buffer to stash FIFO data*/
116     uint8_t rx_stash_len;               /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */
117     uint32_t rx_int_usr_mask;           /*!< RX interrupt status. Valid at any time, regardless of RX buffer status. */
118     uart_pat_rb_t rx_pattern_pos;
119     int tx_buf_size;                    /*!< TX ring buffer size */
120     bool tx_waiting_fifo;               /*!< this flag indicates that some task is waiting for FIFO empty interrupt, used to send all data without any data buffer*/
121     uint8_t *tx_ptr;                    /*!< TX data pointer to push to FIFO in TX buffer mode*/
122     uart_tx_data_t *tx_head;            /*!< TX data pointer to head of the current buffer in TX ring buffer*/
123     uint32_t tx_len_tot;                /*!< Total length of current item in ring buffer*/
124     uint32_t tx_len_cur;
125     uint8_t tx_brk_flg;                 /*!< Flag to indicate to send a break signal in the end of the item sending procedure */
126     uint8_t tx_brk_len;                 /*!< TX break signal cycle length/number */
127     uint8_t tx_waiting_brk;             /*!< Flag to indicate that TX FIFO is ready to send break signal after FIFO is empty, do not push data into TX FIFO right now.*/
128     uart_select_notif_callback_t uart_select_notif_callback; /*!< Notification about select() events */
129     QueueHandle_t event_queue;          /*!< UART event queue handler*/
130     RingbufHandle_t rx_ring_buf;        /*!< RX ring buffer handler*/
131     RingbufHandle_t tx_ring_buf;        /*!< TX ring buffer handler*/
132     SemaphoreHandle_t rx_mux;           /*!< UART RX data mutex*/
133     SemaphoreHandle_t tx_mux;           /*!< UART TX mutex*/
134     SemaphoreHandle_t tx_fifo_sem;      /*!< UART TX FIFO semaphore*/
135     SemaphoreHandle_t tx_done_sem;      /*!< UART TX done semaphore*/
136     SemaphoreHandle_t tx_brk_sem;       /*!< UART TX send break done semaphore*/
137 #if CONFIG_UART_ISR_IN_IRAM
138     void *event_queue_storage;
139     void *event_queue_struct;
140     void *rx_ring_buf_storage;
141     void *rx_ring_buf_struct;
142     void *tx_ring_buf_storage;
143     void *tx_ring_buf_struct;
144     void *rx_mux_struct;
145     void *tx_mux_struct;
146     void *tx_fifo_sem_struct;
147     void *tx_done_sem_struct;
148     void *tx_brk_sem_struct;
149 #endif
150 } uart_obj_t;
151 
152 typedef struct {
153     uart_hal_context_t hal;        /*!< UART hal context*/
154     DECLARE_CRIT_SECTION_LOCK_IN_STRUCT(spinlock)
155     bool hw_enabled;
156 } uart_context_t;
157 
158 static uart_obj_t *p_uart_obj[UART_NUM_MAX] = {0};
159 
160 static uart_context_t uart_context[UART_NUM_MAX] = {
161     UART_CONTEX_INIT_DEF(UART_NUM_0),
162     UART_CONTEX_INIT_DEF(UART_NUM_1),
163 #if UART_NUM_MAX > 2
164     UART_CONTEX_INIT_DEF(UART_NUM_2),
165 #endif
166 };
167 
168 static portMUX_TYPE uart_selectlock = portMUX_INITIALIZER_UNLOCKED;
169 
uart_module_enable(uart_port_t uart_num)170 static void uart_module_enable(uart_port_t uart_num)
171 {
172     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
173     if (uart_context[uart_num].hw_enabled != true) {
174         periph_module_enable(uart_periph_signal[uart_num].module);
175         if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
176             // Workaround for ESP32C3/S3: enable core reset before enabling uart module clock to prevent uart output
177             // garbage value.
178 #if SOC_UART_REQUIRE_CORE_RESET
179             uart_hal_set_reset_core(&(uart_context[uart_num].hal), true);
180             periph_module_reset(uart_periph_signal[uart_num].module);
181             uart_hal_set_reset_core(&(uart_context[uart_num].hal), false);
182 #else
183             periph_module_reset(uart_periph_signal[uart_num].module);
184 #endif
185         }
186         uart_context[uart_num].hw_enabled = true;
187     }
188     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
189 }
190 
uart_module_disable(uart_port_t uart_num)191 static void uart_module_disable(uart_port_t uart_num)
192 {
193     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
194     if (uart_context[uart_num].hw_enabled != false) {
195         if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM ) {
196             periph_module_disable(uart_periph_signal[uart_num].module);
197         }
198         uart_context[uart_num].hw_enabled = false;
199     }
200     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
201 }
202 
uart_get_sclk_freq(uart_sclk_t sclk,uint32_t * out_freq_hz)203 esp_err_t uart_get_sclk_freq(uart_sclk_t sclk, uint32_t *out_freq_hz)
204 {
205     return esp_clk_tree_src_get_freq_hz((soc_module_clk_t)sclk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, out_freq_hz);
206 }
207 
uart_set_word_length(uart_port_t uart_num,uart_word_length_t data_bit)208 esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit)
209 {
210     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
211     ESP_RETURN_ON_FALSE((data_bit < UART_DATA_BITS_MAX), ESP_FAIL, UART_TAG, "data bit error");
212     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
213     uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), data_bit);
214     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
215     return ESP_OK;
216 }
217 
uart_get_word_length(uart_port_t uart_num,uart_word_length_t * data_bit)218 esp_err_t uart_get_word_length(uart_port_t uart_num, uart_word_length_t *data_bit)
219 {
220     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
221     uart_hal_get_data_bit_num(&(uart_context[uart_num].hal), data_bit);
222     return ESP_OK;
223 }
224 
uart_set_stop_bits(uart_port_t uart_num,uart_stop_bits_t stop_bit)225 esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bit)
226 {
227     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
228     ESP_RETURN_ON_FALSE((stop_bit < UART_STOP_BITS_MAX), ESP_FAIL, UART_TAG, "stop bit error");
229     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
230     uart_hal_set_stop_bits(&(uart_context[uart_num].hal), stop_bit);
231     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
232     return ESP_OK;
233 }
234 
uart_get_stop_bits(uart_port_t uart_num,uart_stop_bits_t * stop_bit)235 esp_err_t uart_get_stop_bits(uart_port_t uart_num, uart_stop_bits_t *stop_bit)
236 {
237     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
238     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
239     uart_hal_get_stop_bits(&(uart_context[uart_num].hal), stop_bit);
240     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
241     return ESP_OK;
242 }
243 
uart_set_parity(uart_port_t uart_num,uart_parity_t parity_mode)244 esp_err_t uart_set_parity(uart_port_t uart_num, uart_parity_t parity_mode)
245 {
246     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
247     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
248     uart_hal_set_parity(&(uart_context[uart_num].hal), parity_mode);
249     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
250     return ESP_OK;
251 }
252 
uart_get_parity(uart_port_t uart_num,uart_parity_t * parity_mode)253 esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t *parity_mode)
254 {
255     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
256     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
257     uart_hal_get_parity(&(uart_context[uart_num].hal), parity_mode);
258     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
259     return ESP_OK;
260 }
261 
uart_set_baudrate(uart_port_t uart_num,uint32_t baud_rate)262 esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate)
263 {
264     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
265 
266     uart_sclk_t src_clk;
267     uint32_t sclk_freq;
268 
269     uart_hal_get_sclk(&(uart_context[uart_num].hal), &src_clk);
270     ESP_RETURN_ON_ERROR(uart_get_sclk_freq(src_clk, &sclk_freq), UART_TAG, "Invalid src_clk");
271 
272     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
273     uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq);
274     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
275     return ESP_OK;
276 }
277 
uart_get_baudrate(uart_port_t uart_num,uint32_t * baudrate)278 esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t *baudrate)
279 {
280     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
281 
282     uart_sclk_t src_clk;
283     uint32_t sclk_freq;
284 
285     uart_hal_get_sclk(&(uart_context[uart_num].hal), &src_clk);
286     ESP_RETURN_ON_ERROR(uart_get_sclk_freq(src_clk, &sclk_freq), UART_TAG, "Invalid src_clk");
287 
288     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
289     uart_hal_get_baudrate(&(uart_context[uart_num].hal), baudrate, sclk_freq);
290     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
291     return ESP_OK;
292 }
293 
uart_set_line_inverse(uart_port_t uart_num,uint32_t inverse_mask)294 esp_err_t uart_set_line_inverse(uart_port_t uart_num, uint32_t inverse_mask)
295 {
296     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
297     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
298     uart_hal_inverse_signal(&(uart_context[uart_num].hal), inverse_mask);
299     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
300     return ESP_OK;
301 }
302 
uart_set_sw_flow_ctrl(uart_port_t uart_num,bool enable,uint8_t rx_thresh_xon,uint8_t rx_thresh_xoff)303 esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable,  uint8_t rx_thresh_xon,  uint8_t rx_thresh_xoff)
304 {
305     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
306     ESP_RETURN_ON_FALSE((rx_thresh_xon < SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "rx flow xon thresh error");
307     ESP_RETURN_ON_FALSE((rx_thresh_xoff < SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "rx flow xoff thresh error");
308     uart_sw_flowctrl_t sw_flow_ctl = {
309         .xon_char = XON,
310         .xoff_char = XOFF,
311         .xon_thrd = rx_thresh_xon,
312         .xoff_thrd = rx_thresh_xoff,
313     };
314     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
315     uart_hal_set_sw_flow_ctrl(&(uart_context[uart_num].hal), &sw_flow_ctl, enable);
316     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
317     return ESP_OK;
318 }
319 
uart_set_hw_flow_ctrl(uart_port_t uart_num,uart_hw_flowcontrol_t flow_ctrl,uint8_t rx_thresh)320 esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow_ctrl, uint8_t rx_thresh)
321 {
322     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
323     ESP_RETURN_ON_FALSE((rx_thresh < SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "rx flow thresh error");
324     ESP_RETURN_ON_FALSE((flow_ctrl < UART_HW_FLOWCTRL_MAX), ESP_FAIL, UART_TAG, "hw_flowctrl mode error");
325     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
326     uart_hal_set_hw_flow_ctrl(&(uart_context[uart_num].hal), flow_ctrl, rx_thresh);
327     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
328     return ESP_OK;
329 }
330 
uart_get_hw_flow_ctrl(uart_port_t uart_num,uart_hw_flowcontrol_t * flow_ctrl)331 esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t *flow_ctrl)
332 {
333     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
334     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
335     uart_hal_get_hw_flow_ctrl(&(uart_context[uart_num].hal), flow_ctrl);
336     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
337     return ESP_OK;
338 }
339 
uart_clear_intr_status(uart_port_t uart_num,uint32_t clr_mask)340 esp_err_t UART_ISR_ATTR uart_clear_intr_status(uart_port_t uart_num, uint32_t clr_mask)
341 {
342     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
343     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), clr_mask);
344     return ESP_OK;
345 }
346 
uart_enable_intr_mask(uart_port_t uart_num,uint32_t enable_mask)347 esp_err_t uart_enable_intr_mask(uart_port_t uart_num, uint32_t enable_mask)
348 {
349     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
350     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
351     /* Keep track of the interrupt toggling. In fact, without such variable,
352      * once the RX buffer is full and the RX interrupts disabled, it is
353      * impossible what was the previous state (enabled/disabled) of these
354      * interrupt masks. Thus, this will be very particularly handy when
355      * emptying a filled RX buffer. */
356     p_uart_obj[uart_num]->rx_int_usr_mask |= enable_mask;
357     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), enable_mask);
358     uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), enable_mask);
359     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
360     return ESP_OK;
361 }
362 
363 /**
364  * @brief Function re-enabling the given interrupts (mask) if and only if
365  *        they have not been disabled by the user.
366  *
367  * @param uart_num      UART number to perform the operation on
368  * @param enable_mask   Interrupts (flags) to be re-enabled
369  *
370  * @return ESP_OK in success, ESP_FAIL if uart_num is incorrect
371  */
uart_reenable_intr_mask(uart_port_t uart_num,uint32_t enable_mask)372 static esp_err_t uart_reenable_intr_mask(uart_port_t uart_num, uint32_t enable_mask)
373 {
374     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
375     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
376     /* Mask will only contain the interrupt flags that needs to be re-enabled
377      * AND which have NOT been explicitly disabled by the user. */
378     uint32_t mask = p_uart_obj[uart_num]->rx_int_usr_mask & enable_mask;
379     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), mask);
380     uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), mask);
381     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
382     return ESP_OK;
383 }
384 
uart_disable_intr_mask(uart_port_t uart_num,uint32_t disable_mask)385 esp_err_t uart_disable_intr_mask(uart_port_t uart_num, uint32_t disable_mask)
386 {
387     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
388     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
389     p_uart_obj[uart_num]->rx_int_usr_mask &= ~disable_mask;
390     uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), disable_mask);
391     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
392     return ESP_OK;
393 }
394 
uart_pattern_link_free(uart_port_t uart_num)395 static esp_err_t uart_pattern_link_free(uart_port_t uart_num)
396 {
397     int *pdata = NULL;
398     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
399     if (p_uart_obj[uart_num]->rx_pattern_pos.data != NULL) {
400         pdata = p_uart_obj[uart_num]->rx_pattern_pos.data;
401         p_uart_obj[uart_num]->rx_pattern_pos.data = NULL;
402         p_uart_obj[uart_num]->rx_pattern_pos.wr = 0;
403         p_uart_obj[uart_num]->rx_pattern_pos.rd = 0;
404     }
405     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
406     free(pdata);
407     return ESP_OK;
408 }
409 
uart_pattern_enqueue(uart_port_t uart_num,int pos)410 static esp_err_t UART_ISR_ATTR uart_pattern_enqueue(uart_port_t uart_num, int pos)
411 {
412     esp_err_t ret = ESP_OK;
413     uart_pat_rb_t *p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
414     int next = p_pos->wr + 1;
415     if (next >= p_pos->len) {
416         next = 0;
417     }
418     if (next == p_pos->rd) {
419 #ifndef CONFIG_UART_ISR_IN_IRAM     //Only log if ISR is not in IRAM
420         ESP_EARLY_LOGW(UART_TAG, "Fail to enqueue pattern position, pattern queue is full.");
421 #endif
422         ret = ESP_FAIL;
423     } else {
424         p_pos->data[p_pos->wr] = pos;
425         p_pos->wr = next;
426         ret = ESP_OK;
427     }
428     return ret;
429 }
430 
uart_pattern_dequeue(uart_port_t uart_num)431 static esp_err_t uart_pattern_dequeue(uart_port_t uart_num)
432 {
433     if (p_uart_obj[uart_num]->rx_pattern_pos.data == NULL) {
434         return ESP_ERR_INVALID_STATE;
435     } else {
436         esp_err_t ret = ESP_OK;
437         uart_pat_rb_t *p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
438         if (p_pos->rd == p_pos->wr) {
439             ret = ESP_FAIL;
440         } else {
441             p_pos->rd++;
442         }
443         if (p_pos->rd >= p_pos->len) {
444             p_pos->rd = 0;
445         }
446         return ret;
447     }
448 }
449 
uart_pattern_queue_update(uart_port_t uart_num,int diff_len)450 static esp_err_t uart_pattern_queue_update(uart_port_t uart_num, int diff_len)
451 {
452     uart_pat_rb_t *p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
453     int rd = p_pos->rd;
454     while (rd != p_pos->wr) {
455         p_pos->data[rd] -= diff_len;
456         int rd_rec = rd;
457         rd ++;
458         if (rd >= p_pos->len) {
459             rd = 0;
460         }
461         if (p_pos->data[rd_rec] < 0) {
462             p_pos->rd = rd;
463         }
464     }
465     return ESP_OK;
466 }
467 
uart_pattern_pop_pos(uart_port_t uart_num)468 int uart_pattern_pop_pos(uart_port_t uart_num)
469 {
470     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), (-1), UART_TAG, "uart driver error");
471     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
472     uart_pat_rb_t *pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
473     int pos = -1;
474     if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) {
475         pos = pat_pos->data[pat_pos->rd];
476         uart_pattern_dequeue(uart_num);
477     }
478     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
479     return pos;
480 }
481 
uart_pattern_get_pos(uart_port_t uart_num)482 int uart_pattern_get_pos(uart_port_t uart_num)
483 {
484     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), (-1), UART_TAG, "uart driver error");
485     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
486     uart_pat_rb_t *pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
487     int pos = -1;
488     if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) {
489         pos = pat_pos->data[pat_pos->rd];
490     }
491     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
492     return pos;
493 }
494 
uart_pattern_queue_reset(uart_port_t uart_num,int queue_length)495 esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length)
496 {
497     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
498     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), ESP_ERR_INVALID_STATE, UART_TAG, "uart driver error");
499 
500     int *pdata = (int *) malloc(queue_length * sizeof(int));
501     if (pdata == NULL) {
502         return ESP_ERR_NO_MEM;
503     }
504     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
505     int *ptmp = p_uart_obj[uart_num]->rx_pattern_pos.data;
506     p_uart_obj[uart_num]->rx_pattern_pos.data = pdata;
507     p_uart_obj[uart_num]->rx_pattern_pos.len = queue_length;
508     p_uart_obj[uart_num]->rx_pattern_pos.rd = 0;
509     p_uart_obj[uart_num]->rx_pattern_pos.wr = 0;
510     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
511     free(ptmp);
512     return ESP_OK;
513 }
514 
uart_enable_pattern_det_baud_intr(uart_port_t uart_num,char pattern_chr,uint8_t chr_num,int chr_tout,int post_idle,int pre_idle)515 esp_err_t uart_enable_pattern_det_baud_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle)
516 {
517     ESP_RETURN_ON_FALSE(uart_num < UART_NUM_MAX, ESP_FAIL, UART_TAG, "uart_num error");
518     ESP_RETURN_ON_FALSE(chr_tout >= 0 && chr_tout <= UART_RX_GAP_TOUT_V, ESP_FAIL, UART_TAG, "uart pattern set error\n");
519     ESP_RETURN_ON_FALSE(post_idle >= 0 && post_idle <= UART_POST_IDLE_NUM_V, ESP_FAIL, UART_TAG, "uart pattern set error\n");
520     ESP_RETURN_ON_FALSE(pre_idle >= 0 && pre_idle <= UART_PRE_IDLE_NUM_V, ESP_FAIL, UART_TAG, "uart pattern set error\n");
521     uart_at_cmd_t at_cmd = {0};
522     at_cmd.cmd_char = pattern_chr;
523     at_cmd.char_num = chr_num;
524 
525 #if CONFIG_IDF_TARGET_ESP32
526     uint32_t apb_clk_freq = 0;
527     uint32_t uart_baud = 0;
528     uint32_t uart_div = 0;
529     uart_get_baudrate(uart_num, &uart_baud);
530     esp_clk_tree_src_get_freq_hz((soc_module_clk_t)UART_SCLK_APB, ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT, &apb_clk_freq);
531     uart_div = apb_clk_freq / uart_baud;
532 
533     at_cmd.gap_tout = chr_tout * uart_div;
534     at_cmd.pre_idle = pre_idle * uart_div;
535     at_cmd.post_idle = post_idle * uart_div;
536 #else
537     at_cmd.gap_tout = chr_tout;
538     at_cmd.pre_idle = pre_idle;
539     at_cmd.post_idle = post_idle;
540 #endif
541     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
542     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
543     uart_hal_set_at_cmd_char(&(uart_context[uart_num].hal), &at_cmd);
544     uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
545     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
546     return ESP_OK;
547 }
548 
549 
uart_disable_pattern_det_intr(uart_port_t uart_num)550 esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num)
551 {
552     return uart_disable_intr_mask(uart_num, UART_INTR_CMD_CHAR_DET);
553 }
554 
uart_enable_rx_intr(uart_port_t uart_num)555 esp_err_t uart_enable_rx_intr(uart_port_t uart_num)
556 {
557     return uart_enable_intr_mask(uart_num, UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT);
558 }
559 
uart_disable_rx_intr(uart_port_t uart_num)560 esp_err_t uart_disable_rx_intr(uart_port_t uart_num)
561 {
562     return uart_disable_intr_mask(uart_num, UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT);
563 }
564 
uart_disable_tx_intr(uart_port_t uart_num)565 esp_err_t uart_disable_tx_intr(uart_port_t uart_num)
566 {
567     return uart_disable_intr_mask(uart_num, UART_INTR_TXFIFO_EMPTY);
568 }
569 
uart_enable_tx_intr(uart_port_t uart_num,int enable,int thresh)570 esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh)
571 {
572     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
573     ESP_RETURN_ON_FALSE((thresh < SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "empty intr threshold error");
574     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
575     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
576     uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), thresh);
577     uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
578     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
579     return ESP_OK;
580 }
581 
uart_try_set_iomux_pin(uart_port_t uart_num,int io_num,uint32_t idx)582 static bool uart_try_set_iomux_pin(uart_port_t uart_num, int io_num, uint32_t idx)
583 {
584     /* Store a pointer to the default pin, to optimize access to its fields. */
585     const uart_periph_sig_t *upin = &uart_periph_signal[uart_num].pins[idx];
586 
587     /* In theory, if default_gpio is -1, iomux_func should also be -1, but
588      * let's be safe and test both. */
589     if (upin->iomux_func == -1 || upin->default_gpio == -1 || upin->default_gpio != io_num) {
590         return false;
591     }
592 
593     /* Assign the correct funct to the GPIO. */
594     assert (upin->iomux_func != -1);
595     gpio_iomux_out(io_num, upin->iomux_func, false);
596 
597     /* If the pin is input, we also have to redirect the signal,
598      * in order to bypasse the GPIO matrix. */
599     if (upin->input) {
600         gpio_iomux_in(io_num, upin->signal);
601     }
602 
603     return true;
604 }
605 
606 //internal signal can be output to multiple GPIO pads
607 //only one GPIO pad can connect with input signal
uart_set_pin(uart_port_t uart_num,int tx_io_num,int rx_io_num,int rts_io_num,int cts_io_num)608 esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num)
609 {
610     ESP_RETURN_ON_FALSE((uart_num >= 0), ESP_FAIL, UART_TAG, "uart_num error");
611     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
612     ESP_RETURN_ON_FALSE((tx_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(tx_io_num))), ESP_FAIL, UART_TAG, "tx_io_num error");
613     ESP_RETURN_ON_FALSE((rx_io_num < 0 || (GPIO_IS_VALID_GPIO(rx_io_num))), ESP_FAIL, UART_TAG, "rx_io_num error");
614     ESP_RETURN_ON_FALSE((rts_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(rts_io_num))), ESP_FAIL, UART_TAG, "rts_io_num error");
615     ESP_RETURN_ON_FALSE((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), ESP_FAIL, UART_TAG, "cts_io_num error");
616 
617     /* In the following statements, if the io_num is negative, no need to configure anything. */
618     if (tx_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, tx_io_num, SOC_UART_TX_PIN_IDX)) {
619         gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
620         gpio_set_level(tx_io_num, 1);
621         esp_rom_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX), 0, 0);
622     }
623 
624     if (rx_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, rx_io_num, SOC_UART_RX_PIN_IDX)) {
625         gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO);
626         gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY);
627         gpio_set_direction(rx_io_num, GPIO_MODE_INPUT);
628         esp_rom_gpio_connect_in_signal(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), 0);
629     }
630 
631     if (rts_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, rts_io_num, SOC_UART_RTS_PIN_IDX)) {
632         gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO);
633         gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT);
634         esp_rom_gpio_connect_out_signal(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RTS_PIN_IDX), 0, 0);
635     }
636 
637     if (cts_io_num >= 0  && !uart_try_set_iomux_pin(uart_num, cts_io_num, SOC_UART_CTS_PIN_IDX)) {
638         gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO);
639         gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY);
640         gpio_set_direction(cts_io_num, GPIO_MODE_INPUT);
641         esp_rom_gpio_connect_in_signal(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), 0);
642     }
643 
644     return ESP_OK;
645 }
646 
uart_set_rts(uart_port_t uart_num,int level)647 esp_err_t uart_set_rts(uart_port_t uart_num, int level)
648 {
649     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
650     ESP_RETURN_ON_FALSE((!uart_hal_is_hw_rts_en(&(uart_context[uart_num].hal))), ESP_FAIL, UART_TAG, "disable hw flowctrl before using sw control");
651     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
652     uart_hal_set_rts(&(uart_context[uart_num].hal), level);
653     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
654     return ESP_OK;
655 }
656 
uart_set_dtr(uart_port_t uart_num,int level)657 esp_err_t uart_set_dtr(uart_port_t uart_num, int level)
658 {
659     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
660     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
661     uart_hal_set_dtr(&(uart_context[uart_num].hal), level);
662     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
663     return ESP_OK;
664 }
665 
uart_set_tx_idle_num(uart_port_t uart_num,uint16_t idle_num)666 esp_err_t uart_set_tx_idle_num(uart_port_t uart_num, uint16_t idle_num)
667 {
668     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
669     ESP_RETURN_ON_FALSE((idle_num <= UART_TX_IDLE_NUM_V), ESP_FAIL, UART_TAG, "uart idle num error");
670     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
671     uart_hal_set_tx_idle_num(&(uart_context[uart_num].hal), idle_num);
672     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
673     return ESP_OK;
674 }
675 
uart_param_config(uart_port_t uart_num,const uart_config_t * uart_config)676 esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_config)
677 {
678     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
679     ESP_RETURN_ON_FALSE((uart_config), ESP_FAIL, UART_TAG, "param null");
680     ESP_RETURN_ON_FALSE((uart_config->rx_flow_ctrl_thresh < SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "rx flow thresh error");
681     ESP_RETURN_ON_FALSE((uart_config->flow_ctrl < UART_HW_FLOWCTRL_MAX), ESP_FAIL, UART_TAG, "hw_flowctrl mode error");
682     ESP_RETURN_ON_FALSE((uart_config->data_bits < UART_DATA_BITS_MAX), ESP_FAIL, UART_TAG, "data bit error");
683     uart_module_enable(uart_num);
684     uart_sclk_t clk_src = (uart_config->source_clk) ? uart_config->source_clk : UART_SCLK_DEFAULT; // if no specifying the clock source (soc_module_clk_t starts from 1), then just use the default clock
685 #if SOC_UART_SUPPORT_RTC_CLK
686     if (clk_src == UART_SCLK_RTC) {
687         periph_rtc_dig_clk8m_enable();
688     }
689 #endif
690     uint32_t sclk_freq;
691     ESP_RETURN_ON_ERROR(uart_get_sclk_freq(clk_src, &sclk_freq), UART_TAG, "Invalid src_clk");
692 
693     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
694     uart_hal_init(&(uart_context[uart_num].hal), uart_num);
695     uart_hal_set_sclk(&(uart_context[uart_num].hal), clk_src);
696     uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq);
697     uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity);
698     uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), uart_config->data_bits);
699     uart_hal_set_stop_bits(&(uart_context[uart_num].hal), uart_config->stop_bits);
700     uart_hal_set_tx_idle_num(&(uart_context[uart_num].hal), UART_TX_IDLE_NUM_DEFAULT);
701     uart_hal_set_hw_flow_ctrl(&(uart_context[uart_num].hal), uart_config->flow_ctrl, uart_config->rx_flow_ctrl_thresh);
702     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
703     uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
704     uart_hal_txfifo_rst(&(uart_context[uart_num].hal));
705     return ESP_OK;
706 }
707 
uart_intr_config(uart_port_t uart_num,const uart_intr_config_t * intr_conf)708 esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_conf)
709 {
710     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
711     ESP_RETURN_ON_FALSE((intr_conf), ESP_FAIL, UART_TAG, "param null");
712     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
713     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
714     if (intr_conf->intr_enable_mask & UART_INTR_RXFIFO_TOUT) {
715         uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), intr_conf->rx_timeout_thresh);
716     } else {
717         //Disable rx_tout intr
718         uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), 0);
719     }
720     if (intr_conf->intr_enable_mask & UART_INTR_RXFIFO_FULL) {
721         uart_hal_set_rxfifo_full_thr(&(uart_context[uart_num].hal), intr_conf->rxfifo_full_thresh);
722     }
723     if (intr_conf->intr_enable_mask & UART_INTR_TXFIFO_EMPTY) {
724         uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), intr_conf->txfifo_empty_intr_thresh);
725     }
726     uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), intr_conf->intr_enable_mask);
727     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
728     return ESP_OK;
729 }
730 
uart_find_pattern_from_last(uint8_t * buf,int length,uint8_t pat_chr,uint8_t pat_num)731 static int UART_ISR_ATTR uart_find_pattern_from_last(uint8_t *buf, int length, uint8_t pat_chr, uint8_t pat_num)
732 {
733     int cnt = 0;
734     int len = length;
735     while (len >= 0) {
736         if (buf[len] == pat_chr) {
737             cnt++;
738         } else {
739             cnt = 0;
740         }
741         if (cnt >= pat_num) {
742             break;
743         }
744         len --;
745     }
746     return len;
747 }
748 
uart_enable_tx_write_fifo(uart_port_t uart_num,const uint8_t * pbuf,uint32_t len)749 static uint32_t UART_ISR_ATTR uart_enable_tx_write_fifo(uart_port_t uart_num, const uint8_t *pbuf, uint32_t len)
750 {
751     uint32_t sent_len = 0;
752     UART_ENTER_CRITICAL_SAFE(&(uart_context[uart_num].spinlock));
753     if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
754         uart_hal_set_rts(&(uart_context[uart_num].hal), 0);
755         // If any new things are written to fifo, then we can always clear the previous TX_DONE interrupt bit (if it was set)
756         // Old TX_DONE bit might reset the RTS, leading new tx transmission failure for rs485 mode
757         uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
758         uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
759     }
760     uart_hal_write_txfifo(&(uart_context[uart_num].hal), pbuf, len, &sent_len);
761     UART_EXIT_CRITICAL_SAFE(&(uart_context[uart_num].spinlock));
762     return sent_len;
763 }
764 
765 //internal isr handler for default driver code.
uart_rx_intr_handler_default(void * param)766 static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
767 {
768     uart_obj_t *p_uart = (uart_obj_t *) param;
769     uint8_t uart_num = p_uart->uart_num;
770     int rx_fifo_len = 0;
771     uint32_t uart_intr_status = 0;
772     uart_event_t uart_event;
773     portBASE_TYPE HPTaskAwoken = 0;
774     static uint8_t pat_flg = 0;
775     while (1) {
776         // The `continue statement` may cause the interrupt to loop infinitely
777         // we exit the interrupt here
778         uart_intr_status = uart_hal_get_intsts_mask(&(uart_context[uart_num].hal));
779         //Exit form while loop
780         if (uart_intr_status == 0) {
781             break;
782         }
783         uart_event.type = UART_EVENT_MAX;
784         if (uart_intr_status & UART_INTR_TXFIFO_EMPTY) {
785             UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
786             uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
787             UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
788             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
789             if (p_uart->tx_waiting_brk) {
790                 continue;
791             }
792             //TX semaphore will only be used when tx_buf_size is zero.
793             if (p_uart->tx_waiting_fifo == true && p_uart->tx_buf_size == 0) {
794                 p_uart->tx_waiting_fifo = false;
795                 xSemaphoreGiveFromISR(p_uart->tx_fifo_sem, &HPTaskAwoken);
796             } else {
797                 //We don't use TX ring buffer, because the size is zero.
798                 if (p_uart->tx_buf_size == 0) {
799                     continue;
800                 }
801                 bool en_tx_flg = false;
802                 uint32_t tx_fifo_rem = uart_hal_get_txfifo_len(&(uart_context[uart_num].hal));
803                 //We need to put a loop here, in case all the buffer items are very short.
804                 //That would cause a watch_dog reset because empty interrupt happens so often.
805                 //Although this is a loop in ISR, this loop will execute at most 128 turns.
806                 while (tx_fifo_rem) {
807                     if (p_uart->tx_len_tot == 0 || p_uart->tx_ptr == NULL || p_uart->tx_len_cur == 0) {
808                         size_t size;
809                         p_uart->tx_head = (uart_tx_data_t *) xRingbufferReceiveFromISR(p_uart->tx_ring_buf, &size);
810                         if (p_uart->tx_head) {
811                             //The first item is the data description
812                             //Get the first item to get the data information
813                             if (p_uart->tx_len_tot == 0) {
814                                 p_uart->tx_ptr = NULL;
815                                 p_uart->tx_len_tot = p_uart->tx_head->tx_data.size;
816                                 if (p_uart->tx_head->type == UART_DATA_BREAK) {
817                                     p_uart->tx_brk_flg = 1;
818                                     p_uart->tx_brk_len = p_uart->tx_head->tx_data.brk_len;
819                                 }
820                                 //We have saved the data description from the 1st item, return buffer.
821                                 vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken);
822                             } else if (p_uart->tx_ptr == NULL) {
823                                 //Update the TX item pointer, we will need this to return item to buffer.
824                                 p_uart->tx_ptr = (uint8_t *)p_uart->tx_head;
825                                 en_tx_flg = true;
826                                 p_uart->tx_len_cur = size;
827                             }
828                         } else {
829                             //Can not get data from ring buffer, return;
830                             break;
831                         }
832                     }
833                     if (p_uart->tx_len_tot > 0 && p_uart->tx_ptr && p_uart->tx_len_cur > 0) {
834                         // To fill the TX FIFO.
835                         uint32_t send_len = uart_enable_tx_write_fifo(uart_num, (const uint8_t *) p_uart->tx_ptr,
836                                                                       MIN(p_uart->tx_len_cur, tx_fifo_rem));
837                         p_uart->tx_ptr += send_len;
838                         p_uart->tx_len_tot -= send_len;
839                         p_uart->tx_len_cur -= send_len;
840                         tx_fifo_rem -= send_len;
841                         if (p_uart->tx_len_cur == 0) {
842                             //Return item to ring buffer.
843                             vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken);
844                             p_uart->tx_head = NULL;
845                             p_uart->tx_ptr = NULL;
846                             //Sending item done, now we need to send break if there is a record.
847                             //Set TX break signal after FIFO is empty
848                             if (p_uart->tx_len_tot == 0 && p_uart->tx_brk_flg == 1) {
849                                 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
850                                 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
851                                 uart_hal_tx_break(&(uart_context[uart_num].hal), p_uart->tx_brk_len);
852                                 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
853                                 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
854                                 p_uart->tx_waiting_brk = 1;
855                                 //do not enable TX empty interrupt
856                                 en_tx_flg = false;
857                             } else {
858                                 //enable TX empty interrupt
859                                 en_tx_flg = true;
860                             }
861                         } else {
862                             //enable TX empty interrupt
863                             en_tx_flg = true;
864                         }
865                     }
866                 }
867                 if (en_tx_flg) {
868                     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
869                     UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
870                     uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
871                     UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
872                 }
873             }
874         } else if ((uart_intr_status & UART_INTR_RXFIFO_TOUT)
875                    || (uart_intr_status & UART_INTR_RXFIFO_FULL)
876                    || (uart_intr_status & UART_INTR_CMD_CHAR_DET)
877                   ) {
878             if (pat_flg == 1) {
879                 uart_intr_status |= UART_INTR_CMD_CHAR_DET;
880                 pat_flg = 0;
881             }
882             if (p_uart->rx_buffer_full_flg == false) {
883                 rx_fifo_len = uart_hal_get_rxfifo_len(&(uart_context[uart_num].hal));
884                 if ((p_uart_obj[uart_num]->rx_always_timeout_flg) && !(uart_intr_status & UART_INTR_RXFIFO_TOUT)) {
885                     rx_fifo_len--; // leave one byte in the fifo in order to trigger uart_intr_rxfifo_tout
886                 }
887                 uart_hal_read_rxfifo(&(uart_context[uart_num].hal), p_uart->rx_data_buf, &rx_fifo_len);
888                 uint8_t pat_chr = 0;
889                 uint8_t pat_num = 0;
890                 int pat_idx = -1;
891                 uart_hal_get_at_cmd_char(&(uart_context[uart_num].hal), &pat_chr, &pat_num);
892 
893                 //Get the buffer from the FIFO
894                 if (uart_intr_status & UART_INTR_CMD_CHAR_DET) {
895                     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
896                     uart_event.type = UART_PATTERN_DET;
897                     uart_event.size = rx_fifo_len;
898                     pat_idx = uart_find_pattern_from_last(p_uart->rx_data_buf, rx_fifo_len - 1, pat_chr, pat_num);
899                 } else {
900                     //After Copying the Data From FIFO ,Clear intr_status
901                     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_TOUT | UART_INTR_RXFIFO_FULL);
902                     uart_event.type = UART_DATA;
903                     uart_event.size = rx_fifo_len;
904                     uart_event.timeout_flag = (uart_intr_status & UART_INTR_RXFIFO_TOUT) ? true : false;
905                     UART_ENTER_CRITICAL_ISR(&uart_selectlock);
906                     if (p_uart->uart_select_notif_callback) {
907                         p_uart->uart_select_notif_callback(uart_num, UART_SELECT_READ_NOTIF, &HPTaskAwoken);
908                     }
909                     UART_EXIT_CRITICAL_ISR(&uart_selectlock);
910                 }
911                 p_uart->rx_stash_len = rx_fifo_len;
912                 //If we fail to push data to ring buffer, we will have to stash the data, and send next time.
913                 //Mainly for applications that uses flow control or small ring buffer.
914                 if (pdFALSE == xRingbufferSendFromISR(p_uart->rx_ring_buf, p_uart->rx_data_buf, p_uart->rx_stash_len, &HPTaskAwoken)) {
915                     p_uart->rx_buffer_full_flg = true;
916                     UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
917                     uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_TOUT | UART_INTR_RXFIFO_FULL);
918                     UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
919                     if (uart_event.type == UART_PATTERN_DET) {
920                         UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
921                         if (rx_fifo_len < pat_num) {
922                             //some of the characters are read out in last interrupt
923                             uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
924                         } else {
925                             uart_pattern_enqueue(uart_num,
926                                                  pat_idx <= -1 ?
927                                                  //can not find the pattern in buffer,
928                                                  p_uart->rx_buffered_len + p_uart->rx_stash_len :
929                                                  // find the pattern in buffer
930                                                  p_uart->rx_buffered_len + pat_idx);
931                         }
932                         UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
933                         if ((p_uart->event_queue != NULL) && (pdFALSE == xQueueSendFromISR(p_uart->event_queue, (void * )&uart_event, &HPTaskAwoken))) {
934 #ifndef CONFIG_UART_ISR_IN_IRAM     //Only log if ISR is not in IRAM
935                             ESP_EARLY_LOGV(UART_TAG, "UART event queue full");
936 #endif
937                         }
938                     }
939                     uart_event.type = UART_BUFFER_FULL;
940                 } else {
941                     UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
942                     if (uart_intr_status & UART_INTR_CMD_CHAR_DET) {
943                         if (rx_fifo_len < pat_num) {
944                             //some of the characters are read out in last interrupt
945                             uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
946                         } else if (pat_idx >= 0) {
947                             // find the pattern in stash buffer.
948                             uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len + pat_idx);
949                         }
950                     }
951                     p_uart->rx_buffered_len += p_uart->rx_stash_len;
952                     UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
953                 }
954             } else {
955                 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
956                 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT);
957                 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
958                 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT);
959                 if (uart_intr_status & UART_INTR_CMD_CHAR_DET) {
960                     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
961                     uart_event.type = UART_PATTERN_DET;
962                     uart_event.size = rx_fifo_len;
963                     pat_flg = 1;
964                 }
965             }
966         } else if (uart_intr_status & UART_INTR_RXFIFO_OVF) {
967             // When fifo overflows, we reset the fifo.
968             UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
969             uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
970             UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
971             UART_ENTER_CRITICAL_ISR(&uart_selectlock);
972             if (p_uart->uart_select_notif_callback) {
973                 p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken);
974             }
975             UART_EXIT_CRITICAL_ISR(&uart_selectlock);
976             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_OVF);
977             uart_event.type = UART_FIFO_OVF;
978         } else if (uart_intr_status & UART_INTR_BRK_DET) {
979             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_BRK_DET);
980             uart_event.type = UART_BREAK;
981         } else if (uart_intr_status & UART_INTR_FRAM_ERR) {
982             UART_ENTER_CRITICAL_ISR(&uart_selectlock);
983             if (p_uart->uart_select_notif_callback) {
984                 p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken);
985             }
986             UART_EXIT_CRITICAL_ISR(&uart_selectlock);
987             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_FRAM_ERR);
988             uart_event.type = UART_FRAME_ERR;
989         } else if (uart_intr_status & UART_INTR_PARITY_ERR) {
990             UART_ENTER_CRITICAL_ISR(&uart_selectlock);
991             if (p_uart->uart_select_notif_callback) {
992                 p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken);
993             }
994             UART_EXIT_CRITICAL_ISR(&uart_selectlock);
995             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_PARITY_ERR);
996             uart_event.type = UART_PARITY_ERR;
997         } else if (uart_intr_status & UART_INTR_TX_BRK_DONE) {
998             UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
999             uart_hal_tx_break(&(uart_context[uart_num].hal), 0);
1000             uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
1001             if (p_uart->tx_brk_flg == 1) {
1002                 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
1003             }
1004             UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
1005             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
1006             if (p_uart->tx_brk_flg == 1) {
1007                 p_uart->tx_brk_flg = 0;
1008                 p_uart->tx_waiting_brk = 0;
1009             } else {
1010                 xSemaphoreGiveFromISR(p_uart->tx_brk_sem, &HPTaskAwoken);
1011             }
1012         } else if (uart_intr_status & UART_INTR_TX_BRK_IDLE) {
1013             UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
1014             uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_IDLE);
1015             UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
1016             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_IDLE);
1017         } else if (uart_intr_status & UART_INTR_CMD_CHAR_DET) {
1018             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
1019             uart_event.type = UART_PATTERN_DET;
1020         } else if ((uart_intr_status & UART_INTR_RS485_PARITY_ERR)
1021                    || (uart_intr_status & UART_INTR_RS485_FRM_ERR)
1022                    || (uart_intr_status & UART_INTR_RS485_CLASH)) {
1023             // RS485 collision or frame error interrupt triggered
1024             UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
1025             uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
1026             // Set collision detection flag
1027             p_uart_obj[uart_num]->coll_det_flg = true;
1028             UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
1029             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RS485_CLASH | UART_INTR_RS485_FRM_ERR | UART_INTR_RS485_PARITY_ERR);
1030             uart_event.type = UART_EVENT_MAX;
1031         } else if (uart_intr_status & UART_INTR_TX_DONE) {
1032             if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX) && uart_hal_is_tx_idle(&(uart_context[uart_num].hal)) != true) {
1033                 // The TX_DONE interrupt is triggered but transmit is active
1034                 // then postpone interrupt processing for next interrupt
1035                 uart_event.type = UART_EVENT_MAX;
1036             } else {
1037                 // Workaround for RS485: If the RS485 half duplex mode is active
1038                 // and transmitter is in idle state then reset received buffer and reset RTS pin
1039                 // skip this behavior for other UART modes
1040                 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
1041                 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
1042                 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
1043                 if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
1044                     uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
1045                     uart_hal_set_rts(&(uart_context[uart_num].hal), 1);
1046                 }
1047                 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
1048                 xSemaphoreGiveFromISR(p_uart_obj[uart_num]->tx_done_sem, &HPTaskAwoken);
1049             }
1050         }
1051     #if SOC_UART_SUPPORT_WAKEUP_INT
1052         else if (uart_intr_status & UART_INTR_WAKEUP) {
1053             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_WAKEUP);
1054             uart_event.type = UART_WAKEUP;
1055         }
1056     #endif
1057         else {
1058             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), uart_intr_status); /*simply clear all other intr status*/
1059             uart_event.type = UART_EVENT_MAX;
1060         }
1061 
1062         if (uart_event.type != UART_EVENT_MAX && p_uart->event_queue) {
1063             if (pdFALSE == xQueueSendFromISR(p_uart->event_queue, (void * )&uart_event, &HPTaskAwoken)) {
1064 #ifndef CONFIG_UART_ISR_IN_IRAM     //Only log if ISR is not in IRAM
1065                 ESP_EARLY_LOGV(UART_TAG, "UART event queue full");
1066 #endif
1067             }
1068         }
1069     }
1070     if (HPTaskAwoken == pdTRUE) {
1071         portYIELD_FROM_ISR();
1072     }
1073 }
1074 
1075 /**************************************************************/
uart_wait_tx_done(uart_port_t uart_num,TickType_t ticks_to_wait)1076 esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait)
1077 {
1078     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
1079     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), ESP_FAIL, UART_TAG, "uart driver error");
1080     BaseType_t res;
1081     TickType_t ticks_start = xTaskGetTickCount();
1082     //Take tx_mux
1083     res = xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (TickType_t)ticks_to_wait);
1084     if (res == pdFALSE) {
1085         return ESP_ERR_TIMEOUT;
1086     }
1087 
1088     // Check the enable status of TX_DONE: If already enabled, then let the isr handle the status bit;
1089     // If not enabled, then make sure to clear the status bit before enabling the TX_DONE interrupt bit
1090     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1091     bool is_rs485_mode = UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX);
1092     bool disabled = !(uart_hal_get_intr_ena_status(&(uart_context[uart_num].hal)) & UART_INTR_TX_DONE);
1093     // For RS485 mode, TX_DONE interrupt is enabled for every tx transmission, so there shouldn't be a case of
1094     // interrupt not enabled but raw bit is set.
1095     assert(!(is_rs485_mode &&
1096              disabled &&
1097              uart_hal_get_intraw_mask(&(uart_context[uart_num].hal)) & UART_INTR_TX_DONE));
1098     // If decided to register for the TX_DONE event, then we should clear any possible old tx transmission status.
1099     // The clear operation of RS485 mode should only be handled in isr or when writing to tx fifo.
1100     if (disabled && !is_rs485_mode) {
1101         uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
1102     }
1103     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1104     xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, 0);
1105     // FSM status register update comes later than TX_DONE interrupt raw bit raise
1106     // The maximum time takes for FSM status register to update is (6 APB clock cycles + 3 UART core clock cycles)
1107     // Therefore, to avoid the situation of TX_DONE bit being cleared but FSM didn't be recognized as IDLE (which
1108     // would lead to timeout), a delay of 2us is added in between.
1109     esp_rom_delay_us(2);
1110     if (uart_hal_is_tx_idle(&(uart_context[uart_num].hal))) {
1111         xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1112         return ESP_OK;
1113     }
1114     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1115     uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
1116     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1117 
1118     TickType_t ticks_end = xTaskGetTickCount();
1119     if (ticks_end - ticks_start > ticks_to_wait) {
1120         ticks_to_wait = 0;
1121     } else {
1122         ticks_to_wait = ticks_to_wait - (ticks_end - ticks_start);
1123     }
1124     //take 2nd tx_done_sem, wait given from ISR
1125     res = xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, (TickType_t)ticks_to_wait);
1126     if (res == pdFALSE) {
1127         // The TX_DONE interrupt will be disabled in ISR
1128         xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1129         return ESP_ERR_TIMEOUT;
1130     }
1131     xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1132     return ESP_OK;
1133 }
1134 
uart_tx_chars(uart_port_t uart_num,const char * buffer,uint32_t len)1135 int uart_tx_chars(uart_port_t uart_num, const char *buffer, uint32_t len)
1136 {
1137     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), (-1), UART_TAG, "uart_num error");
1138     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), (-1), UART_TAG, "uart driver error");
1139     ESP_RETURN_ON_FALSE(buffer, (-1), UART_TAG, "buffer null");
1140     if (len == 0) {
1141         return 0;
1142     }
1143     int tx_len = 0;
1144     xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (TickType_t)portMAX_DELAY);
1145     tx_len = (int)uart_enable_tx_write_fifo(uart_num, (const uint8_t *) buffer, len);
1146     xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1147     return tx_len;
1148 }
1149 
uart_tx_all(uart_port_t uart_num,const char * src,size_t size,bool brk_en,int brk_len)1150 static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool brk_en, int brk_len)
1151 {
1152     if (size == 0) {
1153         return 0;
1154     }
1155     size_t original_size = size;
1156 
1157     //lock for uart_tx
1158     xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (TickType_t)portMAX_DELAY);
1159     p_uart_obj[uart_num]->coll_det_flg = false;
1160     if (p_uart_obj[uart_num]->tx_buf_size > 0) {
1161         size_t max_size = xRingbufferGetMaxItemSize(p_uart_obj[uart_num]->tx_ring_buf);
1162         int offset = 0;
1163         uart_tx_data_t evt;
1164         evt.tx_data.size = size;
1165         evt.tx_data.brk_len = brk_len;
1166         if (brk_en) {
1167             evt.type = UART_DATA_BREAK;
1168         } else {
1169             evt.type = UART_DATA;
1170         }
1171         xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *) &evt, sizeof(uart_tx_data_t), portMAX_DELAY);
1172         while (size > 0) {
1173             size_t send_size = size > max_size / 2 ? max_size / 2 : size;
1174             xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *) (src + offset), send_size, portMAX_DELAY);
1175             size -= send_size;
1176             offset += send_size;
1177             uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
1178         }
1179     } else {
1180         while (size) {
1181             //semaphore for tx_fifo available
1182             if (pdTRUE == xSemaphoreTake(p_uart_obj[uart_num]->tx_fifo_sem, (TickType_t)portMAX_DELAY)) {
1183                 uint32_t sent = uart_enable_tx_write_fifo(uart_num, (const uint8_t *) src, size);
1184                 if (sent < size) {
1185                     p_uart_obj[uart_num]->tx_waiting_fifo = true;
1186                     uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
1187                 }
1188                 size -= sent;
1189                 src += sent;
1190             }
1191         }
1192         if (brk_en) {
1193             uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
1194             UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1195             uart_hal_tx_break(&(uart_context[uart_num].hal), brk_len);
1196             uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
1197             UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1198             xSemaphoreTake(p_uart_obj[uart_num]->tx_brk_sem, (TickType_t)portMAX_DELAY);
1199         }
1200         xSemaphoreGive(p_uart_obj[uart_num]->tx_fifo_sem);
1201     }
1202     xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1203     return original_size;
1204 }
1205 
uart_write_bytes(uart_port_t uart_num,const void * src,size_t size)1206 int uart_write_bytes(uart_port_t uart_num, const void *src, size_t size)
1207 {
1208     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), (-1), UART_TAG, "uart_num error");
1209     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num] != NULL), (-1), UART_TAG, "uart driver error");
1210     ESP_RETURN_ON_FALSE(src, (-1), UART_TAG, "buffer null");
1211     return uart_tx_all(uart_num, src, size, 0, 0);
1212 }
1213 
uart_write_bytes_with_break(uart_port_t uart_num,const void * src,size_t size,int brk_len)1214 int uart_write_bytes_with_break(uart_port_t uart_num, const void *src, size_t size, int brk_len)
1215 {
1216     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), (-1), UART_TAG, "uart_num error");
1217     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), (-1), UART_TAG, "uart driver error");
1218     ESP_RETURN_ON_FALSE((size > 0), (-1), UART_TAG, "uart size error");
1219     ESP_RETURN_ON_FALSE((src), (-1), UART_TAG, "uart data null");
1220     ESP_RETURN_ON_FALSE((brk_len > 0 && brk_len < 256), (-1), UART_TAG, "break_num error");
1221     return uart_tx_all(uart_num, src, size, 1, brk_len);
1222 }
1223 
uart_check_buf_full(uart_port_t uart_num)1224 static bool uart_check_buf_full(uart_port_t uart_num)
1225 {
1226     if (p_uart_obj[uart_num]->rx_buffer_full_flg) {
1227         BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_data_buf, p_uart_obj[uart_num]->rx_stash_len, 1);
1228         if (res == pdTRUE) {
1229             UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1230             p_uart_obj[uart_num]->rx_buffered_len += p_uart_obj[uart_num]->rx_stash_len;
1231             p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1232             UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1233             /* Only re-activate UART_INTR_RXFIFO_TOUT or UART_INTR_RXFIFO_FULL
1234              * interrupts if they were NOT explicitly disabled by the user. */
1235             uart_reenable_intr_mask(p_uart_obj[uart_num]->uart_num, UART_INTR_RXFIFO_TOUT | UART_INTR_RXFIFO_FULL);
1236             return true;
1237         }
1238     }
1239     return false;
1240 }
1241 
uart_read_bytes(uart_port_t uart_num,void * buf,uint32_t length,TickType_t ticks_to_wait)1242 int uart_read_bytes(uart_port_t uart_num, void *buf, uint32_t length, TickType_t ticks_to_wait)
1243 {
1244     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), (-1), UART_TAG, "uart_num error");
1245     ESP_RETURN_ON_FALSE((buf), (-1), UART_TAG, "uart data null");
1246     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), (-1), UART_TAG, "uart driver error");
1247     uint8_t *data = NULL;
1248     size_t size;
1249     size_t copy_len = 0;
1250     int len_tmp;
1251     if (xSemaphoreTake(p_uart_obj[uart_num]->rx_mux, (TickType_t)ticks_to_wait) != pdTRUE) {
1252         return -1;
1253     }
1254     while (length) {
1255         if (p_uart_obj[uart_num]->rx_cur_remain == 0) {
1256             data = (uint8_t *) xRingbufferReceive(p_uart_obj[uart_num]->rx_ring_buf, &size, (TickType_t) ticks_to_wait);
1257             if (data) {
1258                 p_uart_obj[uart_num]->rx_head_ptr = data;
1259                 p_uart_obj[uart_num]->rx_ptr = data;
1260                 p_uart_obj[uart_num]->rx_cur_remain = size;
1261             } else {
1262                 //When using dual cores, `rx_buffer_full_flg` may read and write on different cores at same time,
1263                 //which may lose synchronization. So we also need to call `uart_check_buf_full` once when ringbuffer is empty
1264                 //to solve the possible asynchronous issues.
1265                 if (uart_check_buf_full(uart_num)) {
1266                     //This condition will never be true if `uart_read_bytes`
1267                     //and `uart_rx_intr_handler_default` are scheduled on the same core.
1268                     continue;
1269                 } else {
1270                     xSemaphoreGive(p_uart_obj[uart_num]->rx_mux);
1271                     return copy_len;
1272                 }
1273             }
1274         }
1275         if (p_uart_obj[uart_num]->rx_cur_remain > length) {
1276             len_tmp = length;
1277         } else {
1278             len_tmp = p_uart_obj[uart_num]->rx_cur_remain;
1279         }
1280         memcpy((uint8_t *)buf + copy_len, p_uart_obj[uart_num]->rx_ptr, len_tmp);
1281         UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1282         p_uart_obj[uart_num]->rx_buffered_len -= len_tmp;
1283         uart_pattern_queue_update(uart_num, len_tmp);
1284         p_uart_obj[uart_num]->rx_ptr += len_tmp;
1285         UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1286         p_uart_obj[uart_num]->rx_cur_remain -= len_tmp;
1287         copy_len += len_tmp;
1288         length -= len_tmp;
1289         if (p_uart_obj[uart_num]->rx_cur_remain == 0) {
1290             vRingbufferReturnItem(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_head_ptr);
1291             p_uart_obj[uart_num]->rx_head_ptr = NULL;
1292             p_uart_obj[uart_num]->rx_ptr = NULL;
1293             uart_check_buf_full(uart_num);
1294         }
1295     }
1296 
1297     xSemaphoreGive(p_uart_obj[uart_num]->rx_mux);
1298     return copy_len;
1299 }
1300 
uart_get_buffered_data_len(uart_port_t uart_num,size_t * size)1301 esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t *size)
1302 {
1303     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
1304     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), ESP_FAIL, UART_TAG, "uart driver error");
1305     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1306     *size = p_uart_obj[uart_num]->rx_buffered_len;
1307     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1308     return ESP_OK;
1309 }
1310 
uart_get_tx_buffer_free_size(uart_port_t uart_num,size_t * size)1311 esp_err_t uart_get_tx_buffer_free_size(uart_port_t uart_num, size_t *size)
1312 {
1313     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
1314     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), ESP_ERR_INVALID_ARG, UART_TAG, "uart driver error");
1315     ESP_RETURN_ON_FALSE((size != NULL), ESP_ERR_INVALID_ARG, UART_TAG, "arg pointer is NULL");
1316     *size = p_uart_obj[uart_num]->tx_buf_size - p_uart_obj[uart_num]->tx_len_tot;
1317     return ESP_OK;
1318 }
1319 
1320 esp_err_t uart_flush(uart_port_t uart_num) __attribute__((alias("uart_flush_input")));
1321 
uart_flush_input(uart_port_t uart_num)1322 esp_err_t uart_flush_input(uart_port_t uart_num)
1323 {
1324     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
1325     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), ESP_FAIL, UART_TAG, "uart driver error");
1326     uart_obj_t *p_uart = p_uart_obj[uart_num];
1327     uint8_t *data;
1328     size_t size;
1329 
1330     //rx sem protect the ring buffer read related functions
1331     xSemaphoreTake(p_uart->rx_mux, (TickType_t)portMAX_DELAY);
1332     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1333     uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT);
1334     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1335     while (true) {
1336         if (p_uart->rx_head_ptr) {
1337             vRingbufferReturnItem(p_uart->rx_ring_buf, p_uart->rx_head_ptr);
1338             UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1339             p_uart_obj[uart_num]->rx_buffered_len -= p_uart->rx_cur_remain;
1340             uart_pattern_queue_update(uart_num, p_uart->rx_cur_remain);
1341             UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1342             p_uart->rx_ptr = NULL;
1343             p_uart->rx_cur_remain = 0;
1344             p_uart->rx_head_ptr = NULL;
1345         }
1346         data = (uint8_t*) xRingbufferReceive(p_uart->rx_ring_buf, &size, (TickType_t) 0);
1347         if(data == NULL) {
1348             bool error = false;
1349             UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1350             if( p_uart_obj[uart_num]->rx_buffered_len != 0 ) {
1351                 p_uart_obj[uart_num]->rx_buffered_len = 0;
1352                 error = true;
1353             }
1354             //We also need to clear the `rx_buffer_full_flg` here.
1355             p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1356             UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1357             if (error) {
1358                 // this must be called outside the critical section
1359                 ESP_LOGE(UART_TAG, "rx_buffered_len error");
1360             }
1361             break;
1362         }
1363         UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1364         p_uart_obj[uart_num]->rx_buffered_len -= size;
1365         uart_pattern_queue_update(uart_num, size);
1366         UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1367         vRingbufferReturnItem(p_uart->rx_ring_buf, data);
1368         if (p_uart_obj[uart_num]->rx_buffer_full_flg) {
1369             BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_data_buf, p_uart_obj[uart_num]->rx_stash_len, 1);
1370             if (res == pdTRUE) {
1371                 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1372                 p_uart_obj[uart_num]->rx_buffered_len += p_uart_obj[uart_num]->rx_stash_len;
1373                 p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1374                 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1375             }
1376         }
1377     }
1378     p_uart->rx_ptr = NULL;
1379     p_uart->rx_cur_remain = 0;
1380     p_uart->rx_head_ptr = NULL;
1381     uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
1382     /* Only re-enable UART_INTR_RXFIFO_TOUT or UART_INTR_RXFIFO_FULL if they
1383      * were explicitly enabled by the user. */
1384     uart_reenable_intr_mask(uart_num, UART_INTR_RXFIFO_TOUT | UART_INTR_RXFIFO_FULL);
1385     xSemaphoreGive(p_uart->rx_mux);
1386     return ESP_OK;
1387 }
1388 
uart_free_driver_obj(uart_obj_t * uart_obj)1389 static void uart_free_driver_obj(uart_obj_t *uart_obj)
1390 {
1391     if (uart_obj->tx_fifo_sem) {
1392         vSemaphoreDelete(uart_obj->tx_fifo_sem);
1393     }
1394     if (uart_obj->tx_done_sem) {
1395         vSemaphoreDelete(uart_obj->tx_done_sem);
1396     }
1397     if (uart_obj->tx_brk_sem) {
1398         vSemaphoreDelete(uart_obj->tx_brk_sem);
1399     }
1400     if (uart_obj->tx_mux) {
1401         vSemaphoreDelete(uart_obj->tx_mux);
1402     }
1403     if (uart_obj->rx_mux) {
1404         vSemaphoreDelete(uart_obj->rx_mux);
1405     }
1406     if (uart_obj->event_queue) {
1407         vQueueDelete(uart_obj->event_queue);
1408     }
1409     if (uart_obj->rx_ring_buf) {
1410         vRingbufferDelete(uart_obj->rx_ring_buf);
1411     }
1412     if (uart_obj->tx_ring_buf) {
1413         vRingbufferDelete(uart_obj->tx_ring_buf);
1414     }
1415 #if CONFIG_UART_ISR_IN_IRAM
1416     free(uart_obj->event_queue_storage);
1417     free(uart_obj->event_queue_struct);
1418     free(uart_obj->tx_ring_buf_storage);
1419     free(uart_obj->tx_ring_buf_struct);
1420     free(uart_obj->rx_ring_buf_storage);
1421     free(uart_obj->rx_ring_buf_struct);
1422     free(uart_obj->rx_mux_struct);
1423     free(uart_obj->tx_mux_struct);
1424     free(uart_obj->tx_brk_sem_struct);
1425     free(uart_obj->tx_done_sem_struct);
1426     free(uart_obj->tx_fifo_sem_struct);
1427 #endif
1428     free(uart_obj);
1429 }
1430 
uart_alloc_driver_obj(int event_queue_size,int tx_buffer_size,int rx_buffer_size)1431 static uart_obj_t *uart_alloc_driver_obj(int event_queue_size, int tx_buffer_size, int rx_buffer_size)
1432 {
1433     uart_obj_t *uart_obj = heap_caps_calloc(1, sizeof(uart_obj_t), UART_MALLOC_CAPS);
1434     if (!uart_obj) {
1435         return NULL;
1436     }
1437 #if CONFIG_UART_ISR_IN_IRAM
1438     if (event_queue_size > 0) {
1439         uart_obj->event_queue_storage = heap_caps_calloc(event_queue_size, sizeof(uart_event_t), UART_MALLOC_CAPS);
1440         uart_obj->event_queue_struct = heap_caps_calloc(1, sizeof(StaticQueue_t), UART_MALLOC_CAPS);
1441         if (!uart_obj->event_queue_storage || !uart_obj->event_queue_struct) {
1442             goto err;
1443         }
1444     }
1445     if (tx_buffer_size > 0) {
1446         uart_obj->tx_ring_buf_storage = heap_caps_calloc(1, tx_buffer_size, UART_MALLOC_CAPS);
1447         uart_obj->tx_ring_buf_struct = heap_caps_calloc(1, sizeof(StaticRingbuffer_t), UART_MALLOC_CAPS);
1448         if (!uart_obj->tx_ring_buf_storage || !uart_obj->tx_ring_buf_struct) {
1449             goto err;
1450         }
1451     }
1452     uart_obj->rx_ring_buf_storage = heap_caps_calloc(1, rx_buffer_size, UART_MALLOC_CAPS);
1453     uart_obj->rx_ring_buf_struct = heap_caps_calloc(1, sizeof(StaticRingbuffer_t), UART_MALLOC_CAPS);
1454     uart_obj->rx_mux_struct = heap_caps_calloc(1, sizeof(StaticSemaphore_t), UART_MALLOC_CAPS);
1455     uart_obj->tx_mux_struct = heap_caps_calloc(1, sizeof(StaticSemaphore_t), UART_MALLOC_CAPS);
1456     uart_obj->tx_brk_sem_struct = heap_caps_calloc(1, sizeof(StaticSemaphore_t), UART_MALLOC_CAPS);
1457     uart_obj->tx_done_sem_struct = heap_caps_calloc(1, sizeof(StaticSemaphore_t), UART_MALLOC_CAPS);
1458     uart_obj->tx_fifo_sem_struct = heap_caps_calloc(1, sizeof(StaticSemaphore_t), UART_MALLOC_CAPS);
1459     if (!uart_obj->rx_ring_buf_storage || !uart_obj->rx_ring_buf_struct || !uart_obj->rx_mux_struct ||
1460             !uart_obj->tx_mux_struct || !uart_obj->tx_brk_sem_struct || !uart_obj->tx_done_sem_struct ||
1461             !uart_obj->tx_fifo_sem_struct) {
1462         goto err;
1463     }
1464     if (event_queue_size > 0) {
1465         uart_obj->event_queue = xQueueCreateStatic(event_queue_size, sizeof(uart_event_t),
1466                                 uart_obj->event_queue_storage, uart_obj->event_queue_struct);
1467         if (!uart_obj->event_queue) {
1468             goto err;
1469         }
1470     }
1471     if (tx_buffer_size > 0) {
1472         uart_obj->tx_ring_buf = xRingbufferCreateStatic(tx_buffer_size, RINGBUF_TYPE_NOSPLIT,
1473                                 uart_obj->tx_ring_buf_storage, uart_obj->tx_ring_buf_struct);
1474         if (!uart_obj->tx_ring_buf) {
1475             goto err;
1476         }
1477     }
1478     uart_obj->rx_ring_buf = xRingbufferCreateStatic(rx_buffer_size, RINGBUF_TYPE_BYTEBUF,
1479                             uart_obj->rx_ring_buf_storage, uart_obj->rx_ring_buf_struct);
1480     uart_obj->rx_mux = xSemaphoreCreateMutexStatic(uart_obj->rx_mux_struct);
1481     uart_obj->tx_mux = xSemaphoreCreateMutexStatic(uart_obj->tx_mux_struct);
1482     uart_obj->tx_brk_sem = xSemaphoreCreateBinaryStatic(uart_obj->tx_brk_sem_struct);
1483     uart_obj->tx_done_sem = xSemaphoreCreateBinaryStatic(uart_obj->tx_done_sem_struct);
1484     uart_obj->tx_fifo_sem = xSemaphoreCreateBinaryStatic(uart_obj->tx_fifo_sem_struct);
1485     if (!uart_obj->rx_ring_buf || !uart_obj->rx_mux || !uart_obj->tx_mux || !uart_obj->tx_brk_sem ||
1486             !uart_obj->tx_done_sem || !uart_obj->tx_fifo_sem) {
1487         goto err;
1488     }
1489 #else
1490     if (event_queue_size > 0) {
1491         uart_obj->event_queue = xQueueCreate(event_queue_size, sizeof(uart_event_t));
1492         if (!uart_obj->event_queue) {
1493             goto err;
1494         }
1495     }
1496     if (tx_buffer_size > 0) {
1497         uart_obj->tx_ring_buf = xRingbufferCreate(tx_buffer_size, RINGBUF_TYPE_NOSPLIT);
1498         if (!uart_obj->tx_ring_buf) {
1499             goto err;
1500         }
1501     }
1502     uart_obj->rx_ring_buf = xRingbufferCreate(rx_buffer_size, RINGBUF_TYPE_BYTEBUF);
1503     uart_obj->tx_mux = xSemaphoreCreateMutex();
1504     uart_obj->rx_mux = xSemaphoreCreateMutex();
1505     uart_obj->tx_brk_sem = xSemaphoreCreateBinary();
1506     uart_obj->tx_done_sem = xSemaphoreCreateBinary();
1507     uart_obj->tx_fifo_sem = xSemaphoreCreateBinary();
1508     if (!uart_obj->rx_ring_buf || !uart_obj->rx_mux || !uart_obj->tx_mux || !uart_obj->tx_brk_sem ||
1509             !uart_obj->tx_done_sem || !uart_obj->tx_fifo_sem) {
1510         goto err;
1511     }
1512 #endif
1513     return uart_obj;
1514 
1515 err:
1516     uart_free_driver_obj(uart_obj);
1517     return NULL;
1518 }
1519 
uart_driver_install(uart_port_t uart_num,int rx_buffer_size,int tx_buffer_size,int event_queue_size,QueueHandle_t * uart_queue,int intr_alloc_flags)1520 esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_buffer_size, int event_queue_size, QueueHandle_t *uart_queue, int intr_alloc_flags)
1521 {
1522     esp_err_t ret;
1523 #ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
1524     ESP_RETURN_ON_FALSE((uart_num != CONFIG_ESP_CONSOLE_UART_NUM), ESP_FAIL, UART_TAG, "UART used by GDB-stubs! Please disable GDB in menuconfig.");
1525 #endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
1526     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
1527     ESP_RETURN_ON_FALSE((rx_buffer_size > SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "uart rx buffer length error");
1528     ESP_RETURN_ON_FALSE((tx_buffer_size > SOC_UART_FIFO_LEN) || (tx_buffer_size == 0), ESP_FAIL, UART_TAG, "uart tx buffer length error");
1529 #if CONFIG_UART_ISR_IN_IRAM
1530     if ((intr_alloc_flags & ESP_INTR_FLAG_IRAM) == 0) {
1531         ESP_LOGI(UART_TAG, "ESP_INTR_FLAG_IRAM flag not set while CONFIG_UART_ISR_IN_IRAM is enabled, flag updated");
1532         intr_alloc_flags |= ESP_INTR_FLAG_IRAM;
1533     }
1534 #else
1535     if ((intr_alloc_flags & ESP_INTR_FLAG_IRAM) != 0) {
1536         ESP_LOGW(UART_TAG, "ESP_INTR_FLAG_IRAM flag is set while CONFIG_UART_ISR_IN_IRAM is not enabled, flag updated");
1537         intr_alloc_flags &= ~ESP_INTR_FLAG_IRAM;
1538     }
1539 #endif
1540 
1541     if (p_uart_obj[uart_num] == NULL) {
1542         p_uart_obj[uart_num] = uart_alloc_driver_obj(event_queue_size, tx_buffer_size, rx_buffer_size);
1543         if (p_uart_obj[uart_num] == NULL) {
1544             ESP_LOGE(UART_TAG, "UART driver malloc error");
1545             return ESP_FAIL;
1546         }
1547         p_uart_obj[uart_num]->uart_num = uart_num;
1548         p_uart_obj[uart_num]->uart_mode = UART_MODE_UART;
1549         p_uart_obj[uart_num]->coll_det_flg = false;
1550         p_uart_obj[uart_num]->rx_always_timeout_flg = false;
1551         p_uart_obj[uart_num]->event_queue_size = event_queue_size;
1552         p_uart_obj[uart_num]->tx_ptr = NULL;
1553         p_uart_obj[uart_num]->tx_head = NULL;
1554         p_uart_obj[uart_num]->tx_len_tot = 0;
1555         p_uart_obj[uart_num]->tx_brk_flg = 0;
1556         p_uart_obj[uart_num]->tx_brk_len = 0;
1557         p_uart_obj[uart_num]->tx_waiting_brk = 0;
1558         p_uart_obj[uart_num]->rx_buffered_len = 0;
1559         p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1560         p_uart_obj[uart_num]->tx_waiting_fifo = false;
1561         p_uart_obj[uart_num]->rx_ptr = NULL;
1562         p_uart_obj[uart_num]->rx_cur_remain = 0;
1563         p_uart_obj[uart_num]->rx_int_usr_mask = UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT;
1564         p_uart_obj[uart_num]->rx_head_ptr = NULL;
1565         p_uart_obj[uart_num]->tx_buf_size = tx_buffer_size;
1566         p_uart_obj[uart_num]->uart_select_notif_callback = NULL;
1567         xSemaphoreGive(p_uart_obj[uart_num]->tx_fifo_sem);
1568         uart_pattern_queue_reset(uart_num, UART_PATTERN_DET_QLEN_DEFAULT);
1569         if (uart_queue) {
1570             *uart_queue = p_uart_obj[uart_num]->event_queue;
1571             ESP_LOGI(UART_TAG, "queue free spaces: %d", uxQueueSpacesAvailable(p_uart_obj[uart_num]->event_queue));
1572         }
1573     } else {
1574         ESP_LOGE(UART_TAG, "UART driver already installed");
1575         return ESP_FAIL;
1576     }
1577 
1578     uart_intr_config_t uart_intr = {
1579         .intr_enable_mask = UART_INTR_CONFIG_FLAG,
1580         .rxfifo_full_thresh = UART_FULL_THRESH_DEFAULT,
1581         .rx_timeout_thresh = UART_TOUT_THRESH_DEFAULT,
1582         .txfifo_empty_intr_thresh = UART_EMPTY_THRESH_DEFAULT,
1583     };
1584     uart_module_enable(uart_num);
1585     uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
1586     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
1587 
1588     ret = esp_intr_alloc(uart_periph_signal[uart_num].irq, intr_alloc_flags,
1589                        uart_rx_intr_handler_default, p_uart_obj[uart_num],
1590                        &p_uart_obj[uart_num]->intr_handle);
1591     ESP_GOTO_ON_ERROR(ret, err, UART_TAG, "Could not allocate an interrupt for UART");
1592 
1593     ret = uart_intr_config(uart_num, &uart_intr);
1594     ESP_GOTO_ON_ERROR(ret, err, UART_TAG, "Could not configure the interrupt for UART");
1595 
1596     return ret;
1597 
1598 err:
1599     uart_driver_delete(uart_num);
1600     return ret;
1601 }
1602 
1603 //Make sure no other tasks are still using UART before you call this function
uart_driver_delete(uart_port_t uart_num)1604 esp_err_t uart_driver_delete(uart_port_t uart_num)
1605 {
1606     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
1607     if (p_uart_obj[uart_num] == NULL) {
1608         ESP_LOGI(UART_TAG, "ALREADY NULL");
1609         return ESP_OK;
1610     }
1611     esp_intr_free(p_uart_obj[uart_num]->intr_handle);
1612     uart_disable_rx_intr(uart_num);
1613     uart_disable_tx_intr(uart_num);
1614     uart_pattern_link_free(uart_num);
1615     uart_free_driver_obj(p_uart_obj[uart_num]);
1616     p_uart_obj[uart_num] = NULL;
1617 
1618 #if SOC_UART_SUPPORT_RTC_CLK
1619     uart_sclk_t sclk = 0;
1620     uart_hal_get_sclk(&(uart_context[uart_num].hal), &sclk);
1621     if (sclk == UART_SCLK_RTC) {
1622         periph_rtc_dig_clk8m_disable();
1623     }
1624 #endif
1625     uart_module_disable(uart_num);
1626     return ESP_OK;
1627 }
1628 
uart_is_driver_installed(uart_port_t uart_num)1629 bool uart_is_driver_installed(uart_port_t uart_num)
1630 {
1631     return uart_num < UART_NUM_MAX && (p_uart_obj[uart_num] != NULL);
1632 }
1633 
uart_set_select_notif_callback(uart_port_t uart_num,uart_select_notif_callback_t uart_select_notif_callback)1634 void uart_set_select_notif_callback(uart_port_t uart_num, uart_select_notif_callback_t uart_select_notif_callback)
1635 {
1636     if (uart_num < UART_NUM_MAX && p_uart_obj[uart_num]) {
1637         p_uart_obj[uart_num]->uart_select_notif_callback = (uart_select_notif_callback_t) uart_select_notif_callback;
1638     }
1639 }
1640 
uart_get_selectlock(void)1641 portMUX_TYPE *uart_get_selectlock(void)
1642 {
1643     return &uart_selectlock;
1644 }
1645 
1646 // Set UART mode
uart_set_mode(uart_port_t uart_num,uart_mode_t mode)1647 esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode)
1648 {
1649     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
1650     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), ESP_ERR_INVALID_STATE, UART_TAG, "uart driver error");
1651     if ((mode == UART_MODE_RS485_COLLISION_DETECT) || (mode == UART_MODE_RS485_APP_CTRL)
1652             || (mode == UART_MODE_RS485_HALF_DUPLEX)) {
1653         ESP_RETURN_ON_FALSE((!uart_hal_is_hw_rts_en(&(uart_context[uart_num].hal))), ESP_ERR_INVALID_ARG, UART_TAG,
1654                             "disable hw flowctrl before using RS485 mode");
1655     }
1656     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1657     uart_hal_set_mode(&(uart_context[uart_num].hal), mode);
1658     if (mode ==  UART_MODE_RS485_COLLISION_DETECT) {
1659         // This mode allows read while transmitting that allows collision detection
1660         p_uart_obj[uart_num]->coll_det_flg = false;
1661         // Enable collision detection interrupts
1662         uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_TOUT
1663                                | UART_INTR_RXFIFO_FULL
1664                                | UART_INTR_RS485_CLASH
1665                                | UART_INTR_RS485_FRM_ERR
1666                                | UART_INTR_RS485_PARITY_ERR);
1667     }
1668     p_uart_obj[uart_num]->uart_mode = mode;
1669     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1670     return ESP_OK;
1671 }
1672 
uart_set_rx_full_threshold(uart_port_t uart_num,int threshold)1673 esp_err_t uart_set_rx_full_threshold(uart_port_t uart_num, int threshold)
1674 {
1675     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
1676     ESP_RETURN_ON_FALSE((threshold < UART_RXFIFO_FULL_THRHD_V) && (threshold > 0), ESP_ERR_INVALID_ARG, UART_TAG,
1677                         "rx fifo full threshold value error");
1678     if (p_uart_obj[uart_num] == NULL) {
1679         ESP_LOGE(UART_TAG, "call uart_driver_install API first");
1680         return ESP_ERR_INVALID_STATE;
1681     }
1682     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1683     if (uart_hal_get_intr_ena_status(&(uart_context[uart_num].hal)) & UART_INTR_RXFIFO_FULL) {
1684         uart_hal_set_rxfifo_full_thr(&(uart_context[uart_num].hal), threshold);
1685     }
1686     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1687     return ESP_OK;
1688 }
1689 
uart_set_tx_empty_threshold(uart_port_t uart_num,int threshold)1690 esp_err_t uart_set_tx_empty_threshold(uart_port_t uart_num, int threshold)
1691 {
1692     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
1693     ESP_RETURN_ON_FALSE((threshold < UART_TXFIFO_EMPTY_THRHD_V) && (threshold > 0), ESP_ERR_INVALID_ARG, UART_TAG,
1694                         "tx fifo empty threshold value error");
1695     if (p_uart_obj[uart_num] == NULL) {
1696         ESP_LOGE(UART_TAG, "call uart_driver_install API first");
1697         return ESP_ERR_INVALID_STATE;
1698     }
1699     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1700     if (uart_hal_get_intr_ena_status(&(uart_context[uart_num].hal)) & UART_INTR_TXFIFO_EMPTY) {
1701         uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), threshold);
1702     }
1703     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1704     return ESP_OK;
1705 }
1706 
uart_set_rx_timeout(uart_port_t uart_num,const uint8_t tout_thresh)1707 esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh)
1708 {
1709     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
1710     // get maximum timeout threshold
1711     uint16_t tout_max_thresh = uart_hal_get_max_rx_timeout_thrd(&(uart_context[uart_num].hal));
1712     if (tout_thresh > tout_max_thresh) {
1713         ESP_LOGE(UART_TAG, "tout_thresh = %d > maximum value = %d", tout_thresh, tout_max_thresh);
1714         return ESP_ERR_INVALID_ARG;
1715     }
1716     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1717     uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), tout_thresh);
1718     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1719     return ESP_OK;
1720 }
1721 
uart_get_collision_flag(uart_port_t uart_num,bool * collision_flag)1722 esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool *collision_flag)
1723 {
1724     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
1725     ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), ESP_FAIL, UART_TAG, "uart driver error");
1726     ESP_RETURN_ON_FALSE((collision_flag != NULL), ESP_ERR_INVALID_ARG, UART_TAG, "wrong parameter pointer");
1727     ESP_RETURN_ON_FALSE((UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX) || UART_IS_MODE_SET(uart_num, UART_MODE_RS485_COLLISION_DETECT)),
1728                         ESP_ERR_INVALID_ARG, UART_TAG, "wrong mode");
1729     *collision_flag = p_uart_obj[uart_num]->coll_det_flg;
1730     return ESP_OK;
1731 }
1732 
uart_set_wakeup_threshold(uart_port_t uart_num,int wakeup_threshold)1733 esp_err_t uart_set_wakeup_threshold(uart_port_t uart_num, int wakeup_threshold)
1734 {
1735     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
1736     ESP_RETURN_ON_FALSE((wakeup_threshold <= UART_ACTIVE_THRESHOLD_V && wakeup_threshold > UART_MIN_WAKEUP_THRESH), ESP_ERR_INVALID_ARG, UART_TAG,
1737                         "wakeup_threshold out of bounds");
1738     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1739     uart_hal_set_wakeup_thrd(&(uart_context[uart_num].hal), wakeup_threshold);
1740     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1741     return ESP_OK;
1742 }
1743 
uart_get_wakeup_threshold(uart_port_t uart_num,int * out_wakeup_threshold)1744 esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int *out_wakeup_threshold)
1745 {
1746     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
1747     ESP_RETURN_ON_FALSE((out_wakeup_threshold != NULL), ESP_ERR_INVALID_ARG, UART_TAG, "argument is NULL");
1748     uart_hal_get_wakeup_thrd(&(uart_context[uart_num].hal), (uint32_t *)out_wakeup_threshold);
1749     return ESP_OK;
1750 }
1751 
uart_wait_tx_idle_polling(uart_port_t uart_num)1752 esp_err_t uart_wait_tx_idle_polling(uart_port_t uart_num)
1753 {
1754     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
1755     while (!uart_hal_is_tx_idle(&(uart_context[uart_num].hal)));
1756     return ESP_OK;
1757 }
1758 
uart_set_loop_back(uart_port_t uart_num,bool loop_back_en)1759 esp_err_t uart_set_loop_back(uart_port_t uart_num, bool loop_back_en)
1760 {
1761     ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
1762     uart_hal_set_loop_back(&(uart_context[uart_num].hal), loop_back_en);
1763     return ESP_OK;
1764 }
1765 
uart_set_always_rx_timeout(uart_port_t uart_num,bool always_rx_timeout)1766 void uart_set_always_rx_timeout(uart_port_t uart_num, bool always_rx_timeout)
1767 {
1768     uint16_t rx_tout = uart_hal_get_rx_tout_thr(&(uart_context[uart_num].hal));
1769     if (rx_tout) {
1770         p_uart_obj[uart_num]->rx_always_timeout_flg = always_rx_timeout;
1771     } else {
1772         p_uart_obj[uart_num]->rx_always_timeout_flg = false;
1773     }
1774 }
1775