1 /** 2 * \file 3 * 4 * \brief Component description for BPM 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_BPM_COMPONENT_ 30 #define _SAM4L_BPM_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR BPM */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_BPM Backup Power Manager */ 36 /*@{*/ 37 38 #define BPM_I7197 39 #define REV_BPM 0x120 40 41 /* -------- BPM_IER : (BPM Offset: 0x00) ( /W 32) Interrupt Enable Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t PSOK:1; /*!< bit: 0 Power Scaling OK Interrupt Enable */ 46 uint32_t :30; /*!< bit: 1..30 Reserved */ 47 uint32_t AE:1; /*!< bit: 31 Access Error Interrupt Enable */ 48 } bit; /*!< Structure used for bit access */ 49 uint32_t reg; /*!< Type used for register access */ 50 } BPM_IER_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define BPM_IER_OFFSET 0x00 /**< \brief (BPM_IER offset) Interrupt Enable Register */ 54 #define BPM_IER_RESETVALUE _U_(0x00000000); /**< \brief (BPM_IER reset_value) Interrupt Enable Register */ 55 56 #define BPM_IER_PSOK_Pos 0 /**< \brief (BPM_IER) Power Scaling OK Interrupt Enable */ 57 #define BPM_IER_PSOK (_U_(0x1) << BPM_IER_PSOK_Pos) 58 #define BPM_IER_AE_Pos 31 /**< \brief (BPM_IER) Access Error Interrupt Enable */ 59 #define BPM_IER_AE (_U_(0x1) << BPM_IER_AE_Pos) 60 #define BPM_IER_MASK _U_(0x80000001) /**< \brief (BPM_IER) MASK Register */ 61 62 /* -------- BPM_IDR : (BPM Offset: 0x04) ( /W 32) Interrupt Disable Register -------- */ 63 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 64 typedef union { 65 struct { 66 uint32_t PSOK:1; /*!< bit: 0 Power Scaling OK Interrupt Disable */ 67 uint32_t :30; /*!< bit: 1..30 Reserved */ 68 uint32_t AE:1; /*!< bit: 31 Access Error Interrupt Disable */ 69 } bit; /*!< Structure used for bit access */ 70 uint32_t reg; /*!< Type used for register access */ 71 } BPM_IDR_Type; 72 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 73 74 #define BPM_IDR_OFFSET 0x04 /**< \brief (BPM_IDR offset) Interrupt Disable Register */ 75 #define BPM_IDR_RESETVALUE _U_(0x00000000); /**< \brief (BPM_IDR reset_value) Interrupt Disable Register */ 76 77 #define BPM_IDR_PSOK_Pos 0 /**< \brief (BPM_IDR) Power Scaling OK Interrupt Disable */ 78 #define BPM_IDR_PSOK (_U_(0x1) << BPM_IDR_PSOK_Pos) 79 #define BPM_IDR_AE_Pos 31 /**< \brief (BPM_IDR) Access Error Interrupt Disable */ 80 #define BPM_IDR_AE (_U_(0x1) << BPM_IDR_AE_Pos) 81 #define BPM_IDR_MASK _U_(0x80000001) /**< \brief (BPM_IDR) MASK Register */ 82 83 /* -------- BPM_IMR : (BPM Offset: 0x08) (R/ 32) Interrupt Mask Register -------- */ 84 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 85 typedef union { 86 struct { 87 uint32_t PSOK:1; /*!< bit: 0 Power Scaling OK Interrupt Mask */ 88 uint32_t :30; /*!< bit: 1..30 Reserved */ 89 uint32_t AE:1; /*!< bit: 31 Access Error Interrupt Mask */ 90 } bit; /*!< Structure used for bit access */ 91 uint32_t reg; /*!< Type used for register access */ 92 } BPM_IMR_Type; 93 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 94 95 #define BPM_IMR_OFFSET 0x08 /**< \brief (BPM_IMR offset) Interrupt Mask Register */ 96 #define BPM_IMR_RESETVALUE _U_(0x00000000); /**< \brief (BPM_IMR reset_value) Interrupt Mask Register */ 97 98 #define BPM_IMR_PSOK_Pos 0 /**< \brief (BPM_IMR) Power Scaling OK Interrupt Mask */ 99 #define BPM_IMR_PSOK (_U_(0x1) << BPM_IMR_PSOK_Pos) 100 #define BPM_IMR_AE_Pos 31 /**< \brief (BPM_IMR) Access Error Interrupt Mask */ 101 #define BPM_IMR_AE (_U_(0x1) << BPM_IMR_AE_Pos) 102 #define BPM_IMR_MASK _U_(0x80000001) /**< \brief (BPM_IMR) MASK Register */ 103 104 /* -------- BPM_ISR : (BPM Offset: 0x0C) (R/ 32) Interrupt Status Register -------- */ 105 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 106 typedef union { 107 struct { 108 uint32_t PSOK:1; /*!< bit: 0 Power Scaling OK Interrupt Status */ 109 uint32_t :30; /*!< bit: 1..30 Reserved */ 110 uint32_t AE:1; /*!< bit: 31 Access Error Interrupt Status */ 111 } bit; /*!< Structure used for bit access */ 112 uint32_t reg; /*!< Type used for register access */ 113 } BPM_ISR_Type; 114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 115 116 #define BPM_ISR_OFFSET 0x0C /**< \brief (BPM_ISR offset) Interrupt Status Register */ 117 #define BPM_ISR_RESETVALUE _U_(0x00000000); /**< \brief (BPM_ISR reset_value) Interrupt Status Register */ 118 119 #define BPM_ISR_PSOK_Pos 0 /**< \brief (BPM_ISR) Power Scaling OK Interrupt Status */ 120 #define BPM_ISR_PSOK (_U_(0x1) << BPM_ISR_PSOK_Pos) 121 #define BPM_ISR_AE_Pos 31 /**< \brief (BPM_ISR) Access Error Interrupt Status */ 122 #define BPM_ISR_AE (_U_(0x1) << BPM_ISR_AE_Pos) 123 #define BPM_ISR_MASK _U_(0x80000001) /**< \brief (BPM_ISR) MASK Register */ 124 125 /* -------- BPM_ICR : (BPM Offset: 0x10) ( /W 32) Interrupt Clear Register -------- */ 126 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 127 typedef union { 128 struct { 129 uint32_t PSOK:1; /*!< bit: 0 Power Scaling OK Interrupt Status Clear */ 130 uint32_t :30; /*!< bit: 1..30 Reserved */ 131 uint32_t AE:1; /*!< bit: 31 Access Error Interrupt Status Clear */ 132 } bit; /*!< Structure used for bit access */ 133 uint32_t reg; /*!< Type used for register access */ 134 } BPM_ICR_Type; 135 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 #define BPM_ICR_OFFSET 0x10 /**< \brief (BPM_ICR offset) Interrupt Clear Register */ 138 #define BPM_ICR_RESETVALUE _U_(0x00000000); /**< \brief (BPM_ICR reset_value) Interrupt Clear Register */ 139 140 #define BPM_ICR_PSOK_Pos 0 /**< \brief (BPM_ICR) Power Scaling OK Interrupt Status Clear */ 141 #define BPM_ICR_PSOK (_U_(0x1) << BPM_ICR_PSOK_Pos) 142 #define BPM_ICR_AE_Pos 31 /**< \brief (BPM_ICR) Access Error Interrupt Status Clear */ 143 #define BPM_ICR_AE (_U_(0x1) << BPM_ICR_AE_Pos) 144 #define BPM_ICR_MASK _U_(0x80000001) /**< \brief (BPM_ICR) MASK Register */ 145 146 /* -------- BPM_SR : (BPM Offset: 0x14) (R/ 32) Status Register -------- */ 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 148 typedef union { 149 struct { 150 uint32_t PSOK:1; /*!< bit: 0 Power Scaling OK Status */ 151 uint32_t :30; /*!< bit: 1..30 Reserved */ 152 uint32_t AE:1; /*!< bit: 31 Access Error */ 153 } bit; /*!< Structure used for bit access */ 154 uint32_t reg; /*!< Type used for register access */ 155 } BPM_SR_Type; 156 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 157 158 #define BPM_SR_OFFSET 0x14 /**< \brief (BPM_SR offset) Status Register */ 159 #define BPM_SR_RESETVALUE _U_(0x00000000); /**< \brief (BPM_SR reset_value) Status Register */ 160 161 #define BPM_SR_PSOK_Pos 0 /**< \brief (BPM_SR) Power Scaling OK Status */ 162 #define BPM_SR_PSOK (_U_(0x1) << BPM_SR_PSOK_Pos) 163 #define BPM_SR_AE_Pos 31 /**< \brief (BPM_SR) Access Error */ 164 #define BPM_SR_AE (_U_(0x1) << BPM_SR_AE_Pos) 165 #define BPM_SR_MASK _U_(0x80000001) /**< \brief (BPM_SR) MASK Register */ 166 167 /* -------- BPM_UNLOCK : (BPM Offset: 0x18) ( /W 32) Unlock Register -------- */ 168 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 169 typedef union { 170 struct { 171 uint32_t ADDR:10; /*!< bit: 0.. 9 Unlock Address */ 172 uint32_t :14; /*!< bit: 10..23 Reserved */ 173 uint32_t KEY:8; /*!< bit: 24..31 Unlock Key */ 174 } bit; /*!< Structure used for bit access */ 175 uint32_t reg; /*!< Type used for register access */ 176 } BPM_UNLOCK_Type; 177 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 178 179 #define BPM_UNLOCK_OFFSET 0x18 /**< \brief (BPM_UNLOCK offset) Unlock Register */ 180 #define BPM_UNLOCK_RESETVALUE _U_(0x00000000); /**< \brief (BPM_UNLOCK reset_value) Unlock Register */ 181 182 #define BPM_UNLOCK_ADDR_Pos 0 /**< \brief (BPM_UNLOCK) Unlock Address */ 183 #define BPM_UNLOCK_ADDR_Msk (_U_(0x3FF) << BPM_UNLOCK_ADDR_Pos) 184 #define BPM_UNLOCK_ADDR(value) (BPM_UNLOCK_ADDR_Msk & ((value) << BPM_UNLOCK_ADDR_Pos)) 185 #define BPM_UNLOCK_KEY_Pos 24 /**< \brief (BPM_UNLOCK) Unlock Key */ 186 #define BPM_UNLOCK_KEY_Msk (_U_(0xFF) << BPM_UNLOCK_KEY_Pos) 187 #define BPM_UNLOCK_KEY(value) (BPM_UNLOCK_KEY_Msk & ((value) << BPM_UNLOCK_KEY_Pos)) 188 #define BPM_UNLOCK_MASK _U_(0xFF0003FF) /**< \brief (BPM_UNLOCK) MASK Register */ 189 190 /* -------- BPM_PMCON : (BPM Offset: 0x1C) (R/W 32) Power Mode Control Register -------- */ 191 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 192 typedef union { 193 struct { 194 uint32_t PS:2; /*!< bit: 0.. 1 Power Scaling Configuration Value */ 195 uint32_t PSCREQ:1; /*!< bit: 2 Power Scaling Change Request */ 196 uint32_t PSCM:1; /*!< bit: 3 Power Scaling Change Mode */ 197 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 198 uint32_t BKUP:1; /*!< bit: 8 BACKUP Mode */ 199 uint32_t RET:1; /*!< bit: 9 RETENTION Mode */ 200 uint32_t :2; /*!< bit: 10..11 Reserved */ 201 uint32_t SLEEP:2; /*!< bit: 12..13 SLEEP mode Configuration */ 202 uint32_t :2; /*!< bit: 14..15 Reserved */ 203 uint32_t CK32S:1; /*!< bit: 16 32Khz-1Khz Clock Source Selection */ 204 uint32_t :7; /*!< bit: 17..23 Reserved */ 205 uint32_t FASTWKUP:1; /*!< bit: 24 Fast Wakeup */ 206 uint32_t :7; /*!< bit: 25..31 Reserved */ 207 } bit; /*!< Structure used for bit access */ 208 uint32_t reg; /*!< Type used for register access */ 209 } BPM_PMCON_Type; 210 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 211 212 #define BPM_PMCON_OFFSET 0x1C /**< \brief (BPM_PMCON offset) Power Mode Control Register */ 213 #define BPM_PMCON_RESETVALUE _U_(0x00000000); /**< \brief (BPM_PMCON reset_value) Power Mode Control Register */ 214 215 #define BPM_PMCON_PS_Pos 0 /**< \brief (BPM_PMCON) Power Scaling Configuration Value */ 216 #define BPM_PMCON_PS_Msk (_U_(0x3) << BPM_PMCON_PS_Pos) 217 #define BPM_PMCON_PS(value) (BPM_PMCON_PS_Msk & ((value) << BPM_PMCON_PS_Pos)) 218 #define BPM_PMCON_PSCREQ_Pos 2 /**< \brief (BPM_PMCON) Power Scaling Change Request */ 219 #define BPM_PMCON_PSCREQ (_U_(0x1) << BPM_PMCON_PSCREQ_Pos) 220 #define BPM_PMCON_PSCM_Pos 3 /**< \brief (BPM_PMCON) Power Scaling Change Mode */ 221 #define BPM_PMCON_PSCM (_U_(0x1) << BPM_PMCON_PSCM_Pos) 222 #define BPM_PMCON_BKUP_Pos 8 /**< \brief (BPM_PMCON) BACKUP Mode */ 223 #define BPM_PMCON_BKUP (_U_(0x1) << BPM_PMCON_BKUP_Pos) 224 #define BPM_PMCON_RET_Pos 9 /**< \brief (BPM_PMCON) RETENTION Mode */ 225 #define BPM_PMCON_RET (_U_(0x1) << BPM_PMCON_RET_Pos) 226 #define BPM_PMCON_SLEEP_Pos 12 /**< \brief (BPM_PMCON) SLEEP mode Configuration */ 227 #define BPM_PMCON_SLEEP_Msk (_U_(0x3) << BPM_PMCON_SLEEP_Pos) 228 #define BPM_PMCON_SLEEP(value) (BPM_PMCON_SLEEP_Msk & ((value) << BPM_PMCON_SLEEP_Pos)) 229 #define BPM_PMCON_CK32S_Pos 16 /**< \brief (BPM_PMCON) 32Khz-1Khz Clock Source Selection */ 230 #define BPM_PMCON_CK32S (_U_(0x1) << BPM_PMCON_CK32S_Pos) 231 #define BPM_PMCON_FASTWKUP_Pos 24 /**< \brief (BPM_PMCON) Fast Wakeup */ 232 #define BPM_PMCON_FASTWKUP (_U_(0x1) << BPM_PMCON_FASTWKUP_Pos) 233 #define BPM_PMCON_MASK _U_(0x0101330F) /**< \brief (BPM_PMCON) MASK Register */ 234 235 /* -------- BPM_BKUPWCAUSE : (BPM Offset: 0x28) (R/ 32) Backup Wake up Cause Register -------- */ 236 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 237 typedef union { 238 uint32_t reg; /*!< Type used for register access */ 239 } BPM_BKUPWCAUSE_Type; 240 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 241 242 #define BPM_BKUPWCAUSE_OFFSET 0x28 /**< \brief (BPM_BKUPWCAUSE offset) Backup Wake up Cause Register */ 243 #define BPM_BKUPWCAUSE_RESETVALUE _U_(0x00000000); /**< \brief (BPM_BKUPWCAUSE reset_value) Backup Wake up Cause Register */ 244 #define BPM_BKUPWCAUSE_MASK _U_(0xFFFFFFFF) /**< \brief (BPM_BKUPWCAUSE) MASK Register */ 245 246 /* -------- BPM_BKUPWEN : (BPM Offset: 0x2C) (R/W 32) Backup Wake up Enable Register -------- */ 247 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 248 typedef union { 249 uint32_t reg; /*!< Type used for register access */ 250 } BPM_BKUPWEN_Type; 251 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 252 253 #define BPM_BKUPWEN_OFFSET 0x2C /**< \brief (BPM_BKUPWEN offset) Backup Wake up Enable Register */ 254 #define BPM_BKUPWEN_RESETVALUE _U_(0x00000000); /**< \brief (BPM_BKUPWEN reset_value) Backup Wake up Enable Register */ 255 #define BPM_BKUPWEN_MASK _U_(0xFFFFFFFF) /**< \brief (BPM_BKUPWEN) MASK Register */ 256 257 /* -------- BPM_BKUPPMUX : (BPM Offset: 0x30) (R/W 32) Backup Pin Muxing Register -------- */ 258 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 259 typedef union { 260 struct { 261 uint32_t BKUPPMUX:9; /*!< bit: 0.. 8 Backup Pin Muxing */ 262 uint32_t :23; /*!< bit: 9..31 Reserved */ 263 } bit; /*!< Structure used for bit access */ 264 uint32_t reg; /*!< Type used for register access */ 265 } BPM_BKUPPMUX_Type; 266 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 267 268 #define BPM_BKUPPMUX_OFFSET 0x30 /**< \brief (BPM_BKUPPMUX offset) Backup Pin Muxing Register */ 269 #define BPM_BKUPPMUX_RESETVALUE _U_(0x00000000); /**< \brief (BPM_BKUPPMUX reset_value) Backup Pin Muxing Register */ 270 271 #define BPM_BKUPPMUX_BKUPPMUX_Pos 0 /**< \brief (BPM_BKUPPMUX) Backup Pin Muxing */ 272 #define BPM_BKUPPMUX_BKUPPMUX_Msk (_U_(0x1FF) << BPM_BKUPPMUX_BKUPPMUX_Pos) 273 #define BPM_BKUPPMUX_BKUPPMUX(value) (BPM_BKUPPMUX_BKUPPMUX_Msk & ((value) << BPM_BKUPPMUX_BKUPPMUX_Pos)) 274 #define BPM_BKUPPMUX_MASK _U_(0x000001FF) /**< \brief (BPM_BKUPPMUX) MASK Register */ 275 276 /* -------- BPM_IORET : (BPM Offset: 0x34) (R/W 32) Input Output Retention Register -------- */ 277 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 278 typedef union { 279 struct { 280 uint32_t RET:1; /*!< bit: 0 Retention on I/O lines after waking up from the BACKUP mode */ 281 uint32_t :31; /*!< bit: 1..31 Reserved */ 282 } bit; /*!< Structure used for bit access */ 283 uint32_t reg; /*!< Type used for register access */ 284 } BPM_IORET_Type; 285 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 286 287 #define BPM_IORET_OFFSET 0x34 /**< \brief (BPM_IORET offset) Input Output Retention Register */ 288 #define BPM_IORET_RESETVALUE _U_(0x00000000); /**< \brief (BPM_IORET reset_value) Input Output Retention Register */ 289 290 #define BPM_IORET_RET_Pos 0 /**< \brief (BPM_IORET) Retention on I/O lines after waking up from the BACKUP mode */ 291 #define BPM_IORET_RET (_U_(0x1) << BPM_IORET_RET_Pos) 292 #define BPM_IORET_MASK _U_(0x00000001) /**< \brief (BPM_IORET) MASK Register */ 293 294 /* -------- BPM_BPR : (BPM Offset: 0x40) (R/W 32) Bypass Register -------- */ 295 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 296 typedef union { 297 struct { 298 uint32_t RUNPSPB:1; /*!< bit: 0 Run Mode Power Scaling Preset Bypass */ 299 uint32_t PSMPSPB:1; /*!< bit: 1 Power Save Mode Power Scaling Preset Bypass */ 300 uint32_t SEQSTN:1; /*!< bit: 2 Sequencial Startup from ULP (Active Low) */ 301 uint32_t PSBTD:1; /*!< bit: 3 Power Scaling Bias Timing Disable */ 302 uint32_t PSHFD:1; /*!< bit: 4 Power Scaling Halt Flash Until VREGOK Disable */ 303 uint32_t DLYRSTD:1; /*!< bit: 5 Delaying Reset Disable */ 304 uint32_t BIASSEN:1; /*!< bit: 6 Bias Switch Enable */ 305 uint32_t LATSEN:1; /*!< bit: 7 Latdel Switch Enable */ 306 uint32_t BOD18CONT:1; /*!< bit: 8 BOD18 in continuous mode not disabled in WAIT/RET/BACKUP modes */ 307 uint32_t POBS:1; /*!< bit: 9 Pico Uart Observability */ 308 uint32_t FFFW:1; /*!< bit: 10 Force Flash Fast Wakeup */ 309 uint32_t FBRDYEN:1; /*!< bit: 11 Flash Bias Ready Enable */ 310 uint32_t FVREFSEN:1; /*!< bit: 12 Flash Vref Switch Enable */ 311 uint32_t :19; /*!< bit: 13..31 Reserved */ 312 } bit; /*!< Structure used for bit access */ 313 uint32_t reg; /*!< Type used for register access */ 314 } BPM_BPR_Type; 315 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 316 317 #define BPM_BPR_OFFSET 0x40 /**< \brief (BPM_BPR offset) Bypass Register */ 318 #define BPM_BPR_RESETVALUE _U_(0x00000000); /**< \brief (BPM_BPR reset_value) Bypass Register */ 319 320 #define BPM_BPR_RUNPSPB_Pos 0 /**< \brief (BPM_BPR) Run Mode Power Scaling Preset Bypass */ 321 #define BPM_BPR_RUNPSPB (_U_(0x1) << BPM_BPR_RUNPSPB_Pos) 322 #define BPM_BPR_PSMPSPB_Pos 1 /**< \brief (BPM_BPR) Power Save Mode Power Scaling Preset Bypass */ 323 #define BPM_BPR_PSMPSPB (_U_(0x1) << BPM_BPR_PSMPSPB_Pos) 324 #define BPM_BPR_SEQSTN_Pos 2 /**< \brief (BPM_BPR) Sequencial Startup from ULP (Active Low) */ 325 #define BPM_BPR_SEQSTN (_U_(0x1) << BPM_BPR_SEQSTN_Pos) 326 #define BPM_BPR_PSBTD_Pos 3 /**< \brief (BPM_BPR) Power Scaling Bias Timing Disable */ 327 #define BPM_BPR_PSBTD (_U_(0x1) << BPM_BPR_PSBTD_Pos) 328 #define BPM_BPR_PSHFD_Pos 4 /**< \brief (BPM_BPR) Power Scaling Halt Flash Until VREGOK Disable */ 329 #define BPM_BPR_PSHFD (_U_(0x1) << BPM_BPR_PSHFD_Pos) 330 #define BPM_BPR_DLYRSTD_Pos 5 /**< \brief (BPM_BPR) Delaying Reset Disable */ 331 #define BPM_BPR_DLYRSTD (_U_(0x1) << BPM_BPR_DLYRSTD_Pos) 332 #define BPM_BPR_BIASSEN_Pos 6 /**< \brief (BPM_BPR) Bias Switch Enable */ 333 #define BPM_BPR_BIASSEN (_U_(0x1) << BPM_BPR_BIASSEN_Pos) 334 #define BPM_BPR_LATSEN_Pos 7 /**< \brief (BPM_BPR) Latdel Switch Enable */ 335 #define BPM_BPR_LATSEN (_U_(0x1) << BPM_BPR_LATSEN_Pos) 336 #define BPM_BPR_BOD18CONT_Pos 8 /**< \brief (BPM_BPR) BOD18 in continuous mode not disabled in WAIT/RET/BACKUP modes */ 337 #define BPM_BPR_BOD18CONT (_U_(0x1) << BPM_BPR_BOD18CONT_Pos) 338 #define BPM_BPR_POBS_Pos 9 /**< \brief (BPM_BPR) Pico Uart Observability */ 339 #define BPM_BPR_POBS (_U_(0x1) << BPM_BPR_POBS_Pos) 340 #define BPM_BPR_FFFW_Pos 10 /**< \brief (BPM_BPR) Force Flash Fast Wakeup */ 341 #define BPM_BPR_FFFW (_U_(0x1) << BPM_BPR_FFFW_Pos) 342 #define BPM_BPR_FBRDYEN_Pos 11 /**< \brief (BPM_BPR) Flash Bias Ready Enable */ 343 #define BPM_BPR_FBRDYEN (_U_(0x1) << BPM_BPR_FBRDYEN_Pos) 344 #define BPM_BPR_FVREFSEN_Pos 12 /**< \brief (BPM_BPR) Flash Vref Switch Enable */ 345 #define BPM_BPR_FVREFSEN (_U_(0x1) << BPM_BPR_FVREFSEN_Pos) 346 #define BPM_BPR_MASK _U_(0x00001FFF) /**< \brief (BPM_BPR) MASK Register */ 347 348 /* -------- BPM_FWRUNPS : (BPM Offset: 0x44) (R/ 32) Factory Word Run PS Register -------- */ 349 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 350 typedef union { 351 struct { 352 uint32_t REGLEVEL:4; /*!< bit: 0.. 3 Regulator Voltage Level */ 353 uint32_t REGTYPE:2; /*!< bit: 4.. 5 Regulator Type */ 354 uint32_t REFTYPE:2; /*!< bit: 6.. 7 Reference Type */ 355 uint32_t FLASHLATDEL:5; /*!< bit: 8..12 Flash Latch Delay Value */ 356 uint32_t FLASHBIAS:4; /*!< bit: 13..16 Flash Bias Value */ 357 uint32_t FPPW:1; /*!< bit: 17 Flash Pico Power Mode */ 358 uint32_t RC115:7; /*!< bit: 18..24 RC 115KHZ Calibration Value */ 359 uint32_t RCFAST:7; /*!< bit: 25..31 RCFAST Calibration Value */ 360 } bit; /*!< Structure used for bit access */ 361 uint32_t reg; /*!< Type used for register access */ 362 } BPM_FWRUNPS_Type; 363 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 364 365 #define BPM_FWRUNPS_OFFSET 0x44 /**< \brief (BPM_FWRUNPS offset) Factory Word Run PS Register */ 366 367 #define BPM_FWRUNPS_REGLEVEL_Pos 0 /**< \brief (BPM_FWRUNPS) Regulator Voltage Level */ 368 #define BPM_FWRUNPS_REGLEVEL_Msk (_U_(0xF) << BPM_FWRUNPS_REGLEVEL_Pos) 369 #define BPM_FWRUNPS_REGLEVEL(value) (BPM_FWRUNPS_REGLEVEL_Msk & ((value) << BPM_FWRUNPS_REGLEVEL_Pos)) 370 #define BPM_FWRUNPS_REGTYPE_Pos 4 /**< \brief (BPM_FWRUNPS) Regulator Type */ 371 #define BPM_FWRUNPS_REGTYPE_Msk (_U_(0x3) << BPM_FWRUNPS_REGTYPE_Pos) 372 #define BPM_FWRUNPS_REGTYPE(value) (BPM_FWRUNPS_REGTYPE_Msk & ((value) << BPM_FWRUNPS_REGTYPE_Pos)) 373 #define BPM_FWRUNPS_REGTYPE_NORMAL_Val _U_(0x0) /**< \brief (BPM_FWRUNPS) */ 374 #define BPM_FWRUNPS_REGTYPE_LP_Val _U_(0x1) /**< \brief (BPM_FWRUNPS) */ 375 #define BPM_FWRUNPS_REGTYPE_XULP_Val _U_(0x2) /**< \brief (BPM_FWRUNPS) */ 376 #define BPM_FWRUNPS_REGTYPE_NORMAL (BPM_FWRUNPS_REGTYPE_NORMAL_Val << BPM_FWRUNPS_REGTYPE_Pos) 377 #define BPM_FWRUNPS_REGTYPE_LP (BPM_FWRUNPS_REGTYPE_LP_Val << BPM_FWRUNPS_REGTYPE_Pos) 378 #define BPM_FWRUNPS_REGTYPE_XULP (BPM_FWRUNPS_REGTYPE_XULP_Val << BPM_FWRUNPS_REGTYPE_Pos) 379 #define BPM_FWRUNPS_REFTYPE_Pos 6 /**< \brief (BPM_FWRUNPS) Reference Type */ 380 #define BPM_FWRUNPS_REFTYPE_Msk (_U_(0x3) << BPM_FWRUNPS_REFTYPE_Pos) 381 #define BPM_FWRUNPS_REFTYPE(value) (BPM_FWRUNPS_REFTYPE_Msk & ((value) << BPM_FWRUNPS_REFTYPE_Pos)) 382 #define BPM_FWRUNPS_REFTYPE_BOTH_Val _U_(0x0) /**< \brief (BPM_FWRUNPS) */ 383 #define BPM_FWRUNPS_REFTYPE_BG_Val _U_(0x1) /**< \brief (BPM_FWRUNPS) */ 384 #define BPM_FWRUNPS_REFTYPE_LPBG_Val _U_(0x2) /**< \brief (BPM_FWRUNPS) */ 385 #define BPM_FWRUNPS_REFTYPE_INTERNAL_Val _U_(0x3) /**< \brief (BPM_FWRUNPS) */ 386 #define BPM_FWRUNPS_REFTYPE_BOTH (BPM_FWRUNPS_REFTYPE_BOTH_Val << BPM_FWRUNPS_REFTYPE_Pos) 387 #define BPM_FWRUNPS_REFTYPE_BG (BPM_FWRUNPS_REFTYPE_BG_Val << BPM_FWRUNPS_REFTYPE_Pos) 388 #define BPM_FWRUNPS_REFTYPE_LPBG (BPM_FWRUNPS_REFTYPE_LPBG_Val << BPM_FWRUNPS_REFTYPE_Pos) 389 #define BPM_FWRUNPS_REFTYPE_INTERNAL (BPM_FWRUNPS_REFTYPE_INTERNAL_Val << BPM_FWRUNPS_REFTYPE_Pos) 390 #define BPM_FWRUNPS_FLASHLATDEL_Pos 8 /**< \brief (BPM_FWRUNPS) Flash Latch Delay Value */ 391 #define BPM_FWRUNPS_FLASHLATDEL_Msk (_U_(0x1F) << BPM_FWRUNPS_FLASHLATDEL_Pos) 392 #define BPM_FWRUNPS_FLASHLATDEL(value) (BPM_FWRUNPS_FLASHLATDEL_Msk & ((value) << BPM_FWRUNPS_FLASHLATDEL_Pos)) 393 #define BPM_FWRUNPS_FLASHBIAS_Pos 13 /**< \brief (BPM_FWRUNPS) Flash Bias Value */ 394 #define BPM_FWRUNPS_FLASHBIAS_Msk (_U_(0xF) << BPM_FWRUNPS_FLASHBIAS_Pos) 395 #define BPM_FWRUNPS_FLASHBIAS(value) (BPM_FWRUNPS_FLASHBIAS_Msk & ((value) << BPM_FWRUNPS_FLASHBIAS_Pos)) 396 #define BPM_FWRUNPS_FPPW_Pos 17 /**< \brief (BPM_FWRUNPS) Flash Pico Power Mode */ 397 #define BPM_FWRUNPS_FPPW (_U_(0x1) << BPM_FWRUNPS_FPPW_Pos) 398 #define BPM_FWRUNPS_RC115_Pos 18 /**< \brief (BPM_FWRUNPS) RC 115KHZ Calibration Value */ 399 #define BPM_FWRUNPS_RC115_Msk (_U_(0x7F) << BPM_FWRUNPS_RC115_Pos) 400 #define BPM_FWRUNPS_RC115(value) (BPM_FWRUNPS_RC115_Msk & ((value) << BPM_FWRUNPS_RC115_Pos)) 401 #define BPM_FWRUNPS_RCFAST_Pos 25 /**< \brief (BPM_FWRUNPS) RCFAST Calibration Value */ 402 #define BPM_FWRUNPS_RCFAST_Msk (_U_(0x7F) << BPM_FWRUNPS_RCFAST_Pos) 403 #define BPM_FWRUNPS_RCFAST(value) (BPM_FWRUNPS_RCFAST_Msk & ((value) << BPM_FWRUNPS_RCFAST_Pos)) 404 #define BPM_FWRUNPS_MASK _U_(0xFFFFFFFF) /**< \brief (BPM_FWRUNPS) MASK Register */ 405 406 /* -------- BPM_FWPSAVEPS : (BPM Offset: 0x48) (R/ 32) Factory Word Power Save PS Register -------- */ 407 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 408 typedef union { 409 struct { 410 uint32_t WREGLEVEL:4; /*!< bit: 0.. 3 Wait mode Regulator Level */ 411 uint32_t WBIAS:4; /*!< bit: 4.. 7 Bias in wait mode */ 412 uint32_t WLATDEL:5; /*!< bit: 8..12 Flash Latdel in wait mode */ 413 uint32_t RREGLEVEL:4; /*!< bit: 13..16 Retention mode Regulator Level */ 414 uint32_t RBIAS:4; /*!< bit: 17..20 Bias in Retention mode */ 415 uint32_t RLATDEL:5; /*!< bit: 21..25 Flash Latdel in Retention mode */ 416 uint32_t BREGLEVEL:4; /*!< bit: 26..29 Backup mode Regulator Level */ 417 uint32_t POR18DIS:1; /*!< bit: 30 POR 18 Disable */ 418 uint32_t FWSAS:1; /*!< bit: 31 Flash Wait State Automatic Switching */ 419 } bit; /*!< Structure used for bit access */ 420 uint32_t reg; /*!< Type used for register access */ 421 } BPM_FWPSAVEPS_Type; 422 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 423 424 #define BPM_FWPSAVEPS_OFFSET 0x48 /**< \brief (BPM_FWPSAVEPS offset) Factory Word Power Save PS Register */ 425 426 #define BPM_FWPSAVEPS_WREGLEVEL_Pos 0 /**< \brief (BPM_FWPSAVEPS) Wait mode Regulator Level */ 427 #define BPM_FWPSAVEPS_WREGLEVEL_Msk (_U_(0xF) << BPM_FWPSAVEPS_WREGLEVEL_Pos) 428 #define BPM_FWPSAVEPS_WREGLEVEL(value) (BPM_FWPSAVEPS_WREGLEVEL_Msk & ((value) << BPM_FWPSAVEPS_WREGLEVEL_Pos)) 429 #define BPM_FWPSAVEPS_WBIAS_Pos 4 /**< \brief (BPM_FWPSAVEPS) Bias in wait mode */ 430 #define BPM_FWPSAVEPS_WBIAS_Msk (_U_(0xF) << BPM_FWPSAVEPS_WBIAS_Pos) 431 #define BPM_FWPSAVEPS_WBIAS(value) (BPM_FWPSAVEPS_WBIAS_Msk & ((value) << BPM_FWPSAVEPS_WBIAS_Pos)) 432 #define BPM_FWPSAVEPS_WLATDEL_Pos 8 /**< \brief (BPM_FWPSAVEPS) Flash Latdel in wait mode */ 433 #define BPM_FWPSAVEPS_WLATDEL_Msk (_U_(0x1F) << BPM_FWPSAVEPS_WLATDEL_Pos) 434 #define BPM_FWPSAVEPS_WLATDEL(value) (BPM_FWPSAVEPS_WLATDEL_Msk & ((value) << BPM_FWPSAVEPS_WLATDEL_Pos)) 435 #define BPM_FWPSAVEPS_RREGLEVEL_Pos 13 /**< \brief (BPM_FWPSAVEPS) Retention mode Regulator Level */ 436 #define BPM_FWPSAVEPS_RREGLEVEL_Msk (_U_(0xF) << BPM_FWPSAVEPS_RREGLEVEL_Pos) 437 #define BPM_FWPSAVEPS_RREGLEVEL(value) (BPM_FWPSAVEPS_RREGLEVEL_Msk & ((value) << BPM_FWPSAVEPS_RREGLEVEL_Pos)) 438 #define BPM_FWPSAVEPS_RBIAS_Pos 17 /**< \brief (BPM_FWPSAVEPS) Bias in Retention mode */ 439 #define BPM_FWPSAVEPS_RBIAS_Msk (_U_(0xF) << BPM_FWPSAVEPS_RBIAS_Pos) 440 #define BPM_FWPSAVEPS_RBIAS(value) (BPM_FWPSAVEPS_RBIAS_Msk & ((value) << BPM_FWPSAVEPS_RBIAS_Pos)) 441 #define BPM_FWPSAVEPS_RLATDEL_Pos 21 /**< \brief (BPM_FWPSAVEPS) Flash Latdel in Retention mode */ 442 #define BPM_FWPSAVEPS_RLATDEL_Msk (_U_(0x1F) << BPM_FWPSAVEPS_RLATDEL_Pos) 443 #define BPM_FWPSAVEPS_RLATDEL(value) (BPM_FWPSAVEPS_RLATDEL_Msk & ((value) << BPM_FWPSAVEPS_RLATDEL_Pos)) 444 #define BPM_FWPSAVEPS_BREGLEVEL_Pos 26 /**< \brief (BPM_FWPSAVEPS) Backup mode Regulator Level */ 445 #define BPM_FWPSAVEPS_BREGLEVEL_Msk (_U_(0xF) << BPM_FWPSAVEPS_BREGLEVEL_Pos) 446 #define BPM_FWPSAVEPS_BREGLEVEL(value) (BPM_FWPSAVEPS_BREGLEVEL_Msk & ((value) << BPM_FWPSAVEPS_BREGLEVEL_Pos)) 447 #define BPM_FWPSAVEPS_POR18DIS_Pos 30 /**< \brief (BPM_FWPSAVEPS) POR 18 Disable */ 448 #define BPM_FWPSAVEPS_POR18DIS (_U_(0x1) << BPM_FWPSAVEPS_POR18DIS_Pos) 449 #define BPM_FWPSAVEPS_FWSAS_Pos 31 /**< \brief (BPM_FWPSAVEPS) Flash Wait State Automatic Switching */ 450 #define BPM_FWPSAVEPS_FWSAS (_U_(0x1) << BPM_FWPSAVEPS_FWSAS_Pos) 451 #define BPM_FWPSAVEPS_MASK _U_(0xFFFFFFFF) /**< \brief (BPM_FWPSAVEPS) MASK Register */ 452 453 /* -------- BPM_VERSION : (BPM Offset: 0xFC) (R/ 32) Version Register -------- */ 454 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 455 typedef union { 456 struct { 457 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 458 uint32_t :4; /*!< bit: 12..15 Reserved */ 459 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 460 uint32_t :12; /*!< bit: 20..31 Reserved */ 461 } bit; /*!< Structure used for bit access */ 462 uint32_t reg; /*!< Type used for register access */ 463 } BPM_VERSION_Type; 464 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 465 466 #define BPM_VERSION_OFFSET 0xFC /**< \brief (BPM_VERSION offset) Version Register */ 467 #define BPM_VERSION_RESETVALUE _U_(0x00000120); /**< \brief (BPM_VERSION reset_value) Version Register */ 468 469 #define BPM_VERSION_VERSION_Pos 0 /**< \brief (BPM_VERSION) Version Number */ 470 #define BPM_VERSION_VERSION_Msk (_U_(0xFFF) << BPM_VERSION_VERSION_Pos) 471 #define BPM_VERSION_VERSION(value) (BPM_VERSION_VERSION_Msk & ((value) << BPM_VERSION_VERSION_Pos)) 472 #define BPM_VERSION_VARIANT_Pos 16 /**< \brief (BPM_VERSION) Variant Number */ 473 #define BPM_VERSION_VARIANT_Msk (_U_(0xF) << BPM_VERSION_VARIANT_Pos) 474 #define BPM_VERSION_VARIANT(value) (BPM_VERSION_VARIANT_Msk & ((value) << BPM_VERSION_VARIANT_Pos)) 475 #define BPM_VERSION_MASK _U_(0x000F0FFF) /**< \brief (BPM_VERSION) MASK Register */ 476 477 /** \brief BPM hardware registers */ 478 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 479 typedef struct { 480 __O uint32_t IER; /**< \brief Offset: 0x00 ( /W 32) Interrupt Enable Register */ 481 __O uint32_t IDR; /**< \brief Offset: 0x04 ( /W 32) Interrupt Disable Register */ 482 __I uint32_t IMR; /**< \brief Offset: 0x08 (R/ 32) Interrupt Mask Register */ 483 __I uint32_t ISR; /**< \brief Offset: 0x0C (R/ 32) Interrupt Status Register */ 484 __O uint32_t ICR; /**< \brief Offset: 0x10 ( /W 32) Interrupt Clear Register */ 485 __I uint32_t SR; /**< \brief Offset: 0x14 (R/ 32) Status Register */ 486 __O uint32_t UNLOCK; /**< \brief Offset: 0x18 ( /W 32) Unlock Register */ 487 __IO uint32_t PMCON; /**< \brief Offset: 0x1C (R/W 32) Power Mode Control Register */ 488 RoReg8 Reserved1[0x8]; 489 __I uint32_t BKUPWCAUSE; /**< \brief Offset: 0x28 (R/ 32) Backup Wake up Cause Register */ 490 __IO uint32_t BKUPWEN; /**< \brief Offset: 0x2C (R/W 32) Backup Wake up Enable Register */ 491 __IO uint32_t BKUPPMUX; /**< \brief Offset: 0x30 (R/W 32) Backup Pin Muxing Register */ 492 __IO uint32_t IORET; /**< \brief Offset: 0x34 (R/W 32) Input Output Retention Register */ 493 RoReg8 Reserved2[0x8]; 494 __IO uint32_t BPR; /**< \brief Offset: 0x40 (R/W 32) Bypass Register */ 495 __I uint32_t FWRUNPS; /**< \brief Offset: 0x44 (R/ 32) Factory Word Run PS Register */ 496 __I uint32_t FWPSAVEPS; /**< \brief Offset: 0x48 (R/ 32) Factory Word Power Save PS Register */ 497 RoReg8 Reserved3[0xB0]; 498 __I uint32_t VERSION; /**< \brief Offset: 0xFC (R/ 32) Version Register */ 499 } Bpm; 500 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 501 502 /*@}*/ 503 504 #endif /* _SAM4L_BPM_COMPONENT_ */ 505
