1 /** 2 * \file 3 * 4 * \brief Component description for TWIS 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_TWIS_COMPONENT_ 30 #define _SAM4L_TWIS_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR TWIS */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_TWIS Two-wire Slave Interface */ 36 /*@{*/ 37 38 #define TWIS_I7537 39 #define REV_TWIS 0x140 40 41 /* -------- TWIS_CR : (TWIS Offset: 0x00) (R/W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t SEN:1; /*!< bit: 0 Slave Enable */ 46 uint32_t SMEN:1; /*!< bit: 1 SMBus Mode Enable */ 47 uint32_t SMATCH:1; /*!< bit: 2 Slave Address Match */ 48 uint32_t GCMATCH:1; /*!< bit: 3 General Call Address Match */ 49 uint32_t STREN:1; /*!< bit: 4 Clock Stretch Enable */ 50 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 51 uint32_t SWRST:1; /*!< bit: 7 Software Reset */ 52 uint32_t SMBALERT:1; /*!< bit: 8 SMBus Alert */ 53 uint32_t SMDA:1; /*!< bit: 9 SMBus Default Address */ 54 uint32_t SMHH:1; /*!< bit: 10 SMBus Host Header */ 55 uint32_t PECEN:1; /*!< bit: 11 Packet Error Checking Enable */ 56 uint32_t ACK:1; /*!< bit: 12 Slave Receiver Data Phase ACK Value */ 57 uint32_t CUP:1; /*!< bit: 13 NBYTES Count Up */ 58 uint32_t SOAM:1; /*!< bit: 14 Stretch Clock on Address Match */ 59 uint32_t SODR:1; /*!< bit: 15 Stretch Clock on Data Byte Reception */ 60 uint32_t ADR:10; /*!< bit: 16..25 Slave Address */ 61 uint32_t TENBIT:1; /*!< bit: 26 Ten Bit Address Match */ 62 uint32_t BRIDGE:1; /*!< bit: 27 Bridge Control Enable */ 63 uint32_t :4; /*!< bit: 28..31 Reserved */ 64 } bit; /*!< Structure used for bit access */ 65 uint32_t reg; /*!< Type used for register access */ 66 } TWIS_CR_Type; 67 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 68 69 #define TWIS_CR_OFFSET 0x00 /**< \brief (TWIS_CR offset) Control Register */ 70 #define TWIS_CR_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_CR reset_value) Control Register */ 71 72 #define TWIS_CR_SEN_Pos 0 /**< \brief (TWIS_CR) Slave Enable */ 73 #define TWIS_CR_SEN (_U_(0x1) << TWIS_CR_SEN_Pos) 74 #define TWIS_CR_SMEN_Pos 1 /**< \brief (TWIS_CR) SMBus Mode Enable */ 75 #define TWIS_CR_SMEN (_U_(0x1) << TWIS_CR_SMEN_Pos) 76 #define TWIS_CR_SMATCH_Pos 2 /**< \brief (TWIS_CR) Slave Address Match */ 77 #define TWIS_CR_SMATCH (_U_(0x1) << TWIS_CR_SMATCH_Pos) 78 #define TWIS_CR_GCMATCH_Pos 3 /**< \brief (TWIS_CR) General Call Address Match */ 79 #define TWIS_CR_GCMATCH (_U_(0x1) << TWIS_CR_GCMATCH_Pos) 80 #define TWIS_CR_STREN_Pos 4 /**< \brief (TWIS_CR) Clock Stretch Enable */ 81 #define TWIS_CR_STREN (_U_(0x1) << TWIS_CR_STREN_Pos) 82 #define TWIS_CR_SWRST_Pos 7 /**< \brief (TWIS_CR) Software Reset */ 83 #define TWIS_CR_SWRST (_U_(0x1) << TWIS_CR_SWRST_Pos) 84 #define TWIS_CR_SMBALERT_Pos 8 /**< \brief (TWIS_CR) SMBus Alert */ 85 #define TWIS_CR_SMBALERT (_U_(0x1) << TWIS_CR_SMBALERT_Pos) 86 #define TWIS_CR_SMDA_Pos 9 /**< \brief (TWIS_CR) SMBus Default Address */ 87 #define TWIS_CR_SMDA (_U_(0x1) << TWIS_CR_SMDA_Pos) 88 #define TWIS_CR_SMHH_Pos 10 /**< \brief (TWIS_CR) SMBus Host Header */ 89 #define TWIS_CR_SMHH (_U_(0x1) << TWIS_CR_SMHH_Pos) 90 #define TWIS_CR_PECEN_Pos 11 /**< \brief (TWIS_CR) Packet Error Checking Enable */ 91 #define TWIS_CR_PECEN (_U_(0x1) << TWIS_CR_PECEN_Pos) 92 #define TWIS_CR_ACK_Pos 12 /**< \brief (TWIS_CR) Slave Receiver Data Phase ACK Value */ 93 #define TWIS_CR_ACK (_U_(0x1) << TWIS_CR_ACK_Pos) 94 #define TWIS_CR_CUP_Pos 13 /**< \brief (TWIS_CR) NBYTES Count Up */ 95 #define TWIS_CR_CUP (_U_(0x1) << TWIS_CR_CUP_Pos) 96 #define TWIS_CR_SOAM_Pos 14 /**< \brief (TWIS_CR) Stretch Clock on Address Match */ 97 #define TWIS_CR_SOAM (_U_(0x1) << TWIS_CR_SOAM_Pos) 98 #define TWIS_CR_SODR_Pos 15 /**< \brief (TWIS_CR) Stretch Clock on Data Byte Reception */ 99 #define TWIS_CR_SODR (_U_(0x1) << TWIS_CR_SODR_Pos) 100 #define TWIS_CR_ADR_Pos 16 /**< \brief (TWIS_CR) Slave Address */ 101 #define TWIS_CR_ADR_Msk (_U_(0x3FF) << TWIS_CR_ADR_Pos) 102 #define TWIS_CR_ADR(value) (TWIS_CR_ADR_Msk & ((value) << TWIS_CR_ADR_Pos)) 103 #define TWIS_CR_TENBIT_Pos 26 /**< \brief (TWIS_CR) Ten Bit Address Match */ 104 #define TWIS_CR_TENBIT (_U_(0x1) << TWIS_CR_TENBIT_Pos) 105 #define TWIS_CR_BRIDGE_Pos 27 /**< \brief (TWIS_CR) Bridge Control Enable */ 106 #define TWIS_CR_BRIDGE (_U_(0x1) << TWIS_CR_BRIDGE_Pos) 107 #define TWIS_CR_MASK _U_(0x0FFFFF9F) /**< \brief (TWIS_CR) MASK Register */ 108 109 /* -------- TWIS_NBYTES : (TWIS Offset: 0x04) (R/W 32) NBYTES Register -------- */ 110 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 111 typedef union { 112 struct { 113 uint32_t NBYTES:8; /*!< bit: 0.. 7 Number of Bytes to Transfer */ 114 uint32_t :24; /*!< bit: 8..31 Reserved */ 115 } bit; /*!< Structure used for bit access */ 116 uint32_t reg; /*!< Type used for register access */ 117 } TWIS_NBYTES_Type; 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 #define TWIS_NBYTES_OFFSET 0x04 /**< \brief (TWIS_NBYTES offset) NBYTES Register */ 121 #define TWIS_NBYTES_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_NBYTES reset_value) NBYTES Register */ 122 123 #define TWIS_NBYTES_NBYTES_Pos 0 /**< \brief (TWIS_NBYTES) Number of Bytes to Transfer */ 124 #define TWIS_NBYTES_NBYTES_Msk (_U_(0xFF) << TWIS_NBYTES_NBYTES_Pos) 125 #define TWIS_NBYTES_NBYTES(value) (TWIS_NBYTES_NBYTES_Msk & ((value) << TWIS_NBYTES_NBYTES_Pos)) 126 #define TWIS_NBYTES_MASK _U_(0x000000FF) /**< \brief (TWIS_NBYTES) MASK Register */ 127 128 /* -------- TWIS_TR : (TWIS Offset: 0x08) (R/W 32) Timing Register -------- */ 129 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 130 typedef union { 131 struct { 132 uint32_t TLOWS:8; /*!< bit: 0.. 7 SMBus Tlow:sext Cycles */ 133 uint32_t TTOUT:8; /*!< bit: 8..15 SMBus Ttimeout Cycles */ 134 uint32_t SUDAT:8; /*!< bit: 16..23 Data Setup Cycles */ 135 uint32_t :4; /*!< bit: 24..27 Reserved */ 136 uint32_t EXP:4; /*!< bit: 28..31 Clock Prescaler */ 137 } bit; /*!< Structure used for bit access */ 138 uint32_t reg; /*!< Type used for register access */ 139 } TWIS_TR_Type; 140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 141 142 #define TWIS_TR_OFFSET 0x08 /**< \brief (TWIS_TR offset) Timing Register */ 143 #define TWIS_TR_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_TR reset_value) Timing Register */ 144 145 #define TWIS_TR_TLOWS_Pos 0 /**< \brief (TWIS_TR) SMBus Tlow:sext Cycles */ 146 #define TWIS_TR_TLOWS_Msk (_U_(0xFF) << TWIS_TR_TLOWS_Pos) 147 #define TWIS_TR_TLOWS(value) (TWIS_TR_TLOWS_Msk & ((value) << TWIS_TR_TLOWS_Pos)) 148 #define TWIS_TR_TTOUT_Pos 8 /**< \brief (TWIS_TR) SMBus Ttimeout Cycles */ 149 #define TWIS_TR_TTOUT_Msk (_U_(0xFF) << TWIS_TR_TTOUT_Pos) 150 #define TWIS_TR_TTOUT(value) (TWIS_TR_TTOUT_Msk & ((value) << TWIS_TR_TTOUT_Pos)) 151 #define TWIS_TR_SUDAT_Pos 16 /**< \brief (TWIS_TR) Data Setup Cycles */ 152 #define TWIS_TR_SUDAT_Msk (_U_(0xFF) << TWIS_TR_SUDAT_Pos) 153 #define TWIS_TR_SUDAT(value) (TWIS_TR_SUDAT_Msk & ((value) << TWIS_TR_SUDAT_Pos)) 154 #define TWIS_TR_EXP_Pos 28 /**< \brief (TWIS_TR) Clock Prescaler */ 155 #define TWIS_TR_EXP_Msk (_U_(0xF) << TWIS_TR_EXP_Pos) 156 #define TWIS_TR_EXP(value) (TWIS_TR_EXP_Msk & ((value) << TWIS_TR_EXP_Pos)) 157 #define TWIS_TR_MASK _U_(0xF0FFFFFF) /**< \brief (TWIS_TR) MASK Register */ 158 159 /* -------- TWIS_RHR : (TWIS Offset: 0x0C) (R/ 32) Receive Holding Register -------- */ 160 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 161 typedef union { 162 struct { 163 uint32_t RXDATA:8; /*!< bit: 0.. 7 Received Data Byte */ 164 uint32_t :24; /*!< bit: 8..31 Reserved */ 165 } bit; /*!< Structure used for bit access */ 166 uint32_t reg; /*!< Type used for register access */ 167 } TWIS_RHR_Type; 168 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 169 170 #define TWIS_RHR_OFFSET 0x0C /**< \brief (TWIS_RHR offset) Receive Holding Register */ 171 #define TWIS_RHR_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_RHR reset_value) Receive Holding Register */ 172 173 #define TWIS_RHR_RXDATA_Pos 0 /**< \brief (TWIS_RHR) Received Data Byte */ 174 #define TWIS_RHR_RXDATA_Msk (_U_(0xFF) << TWIS_RHR_RXDATA_Pos) 175 #define TWIS_RHR_RXDATA(value) (TWIS_RHR_RXDATA_Msk & ((value) << TWIS_RHR_RXDATA_Pos)) 176 #define TWIS_RHR_MASK _U_(0x000000FF) /**< \brief (TWIS_RHR) MASK Register */ 177 178 /* -------- TWIS_THR : (TWIS Offset: 0x10) ( /W 32) Transmit Holding Register -------- */ 179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 180 typedef union { 181 struct { 182 uint32_t TXDATA:8; /*!< bit: 0.. 7 Data Byte to Transmit */ 183 uint32_t :24; /*!< bit: 8..31 Reserved */ 184 } bit; /*!< Structure used for bit access */ 185 uint32_t reg; /*!< Type used for register access */ 186 } TWIS_THR_Type; 187 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 188 189 #define TWIS_THR_OFFSET 0x10 /**< \brief (TWIS_THR offset) Transmit Holding Register */ 190 #define TWIS_THR_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_THR reset_value) Transmit Holding Register */ 191 192 #define TWIS_THR_TXDATA_Pos 0 /**< \brief (TWIS_THR) Data Byte to Transmit */ 193 #define TWIS_THR_TXDATA_Msk (_U_(0xFF) << TWIS_THR_TXDATA_Pos) 194 #define TWIS_THR_TXDATA(value) (TWIS_THR_TXDATA_Msk & ((value) << TWIS_THR_TXDATA_Pos)) 195 #define TWIS_THR_MASK _U_(0x000000FF) /**< \brief (TWIS_THR) MASK Register */ 196 197 /* -------- TWIS_PECR : (TWIS Offset: 0x14) (R/ 32) Packet Error Check Register -------- */ 198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 199 typedef union { 200 struct { 201 uint32_t PEC:8; /*!< bit: 0.. 7 Calculated PEC Value */ 202 uint32_t :24; /*!< bit: 8..31 Reserved */ 203 } bit; /*!< Structure used for bit access */ 204 uint32_t reg; /*!< Type used for register access */ 205 } TWIS_PECR_Type; 206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 207 208 #define TWIS_PECR_OFFSET 0x14 /**< \brief (TWIS_PECR offset) Packet Error Check Register */ 209 #define TWIS_PECR_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_PECR reset_value) Packet Error Check Register */ 210 211 #define TWIS_PECR_PEC_Pos 0 /**< \brief (TWIS_PECR) Calculated PEC Value */ 212 #define TWIS_PECR_PEC_Msk (_U_(0xFF) << TWIS_PECR_PEC_Pos) 213 #define TWIS_PECR_PEC(value) (TWIS_PECR_PEC_Msk & ((value) << TWIS_PECR_PEC_Pos)) 214 #define TWIS_PECR_MASK _U_(0x000000FF) /**< \brief (TWIS_PECR) MASK Register */ 215 216 /* -------- TWIS_SR : (TWIS Offset: 0x18) (R/ 32) Status Register -------- */ 217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 218 typedef union { 219 struct { 220 uint32_t RXRDY:1; /*!< bit: 0 RX Buffer Ready */ 221 uint32_t TXRDY:1; /*!< bit: 1 TX Buffer Ready */ 222 uint32_t SEN:1; /*!< bit: 2 Slave Enabled */ 223 uint32_t TCOMP:1; /*!< bit: 3 Transmission Complete */ 224 uint32_t :1; /*!< bit: 4 Reserved */ 225 uint32_t TRA:1; /*!< bit: 5 Transmitter Mode */ 226 uint32_t URUN:1; /*!< bit: 6 Underrun */ 227 uint32_t ORUN:1; /*!< bit: 7 Overrun */ 228 uint32_t NAK:1; /*!< bit: 8 NAK Received */ 229 uint32_t :3; /*!< bit: 9..11 Reserved */ 230 uint32_t SMBTOUT:1; /*!< bit: 12 SMBus Timeout */ 231 uint32_t SMBPECERR:1; /*!< bit: 13 SMBus PEC Error */ 232 uint32_t BUSERR:1; /*!< bit: 14 Bus Error */ 233 uint32_t :1; /*!< bit: 15 Reserved */ 234 uint32_t SAM:1; /*!< bit: 16 Slave Address Match */ 235 uint32_t GCM:1; /*!< bit: 17 General Call Match */ 236 uint32_t SMBALERTM:1; /*!< bit: 18 SMBus Alert Response Address Match */ 237 uint32_t SMBHHM:1; /*!< bit: 19 SMBus Host Header Address Match */ 238 uint32_t SMBDAM:1; /*!< bit: 20 SMBus Default Address Match */ 239 uint32_t STO:1; /*!< bit: 21 Stop Received */ 240 uint32_t REP:1; /*!< bit: 22 Repeated Start Received */ 241 uint32_t BTF:1; /*!< bit: 23 Byte Transfer Finished */ 242 uint32_t :8; /*!< bit: 24..31 Reserved */ 243 } bit; /*!< Structure used for bit access */ 244 uint32_t reg; /*!< Type used for register access */ 245 } TWIS_SR_Type; 246 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 247 248 #define TWIS_SR_OFFSET 0x18 /**< \brief (TWIS_SR offset) Status Register */ 249 #define TWIS_SR_RESETVALUE _U_(0x00000002); /**< \brief (TWIS_SR reset_value) Status Register */ 250 251 #define TWIS_SR_RXRDY_Pos 0 /**< \brief (TWIS_SR) RX Buffer Ready */ 252 #define TWIS_SR_RXRDY (_U_(0x1) << TWIS_SR_RXRDY_Pos) 253 #define TWIS_SR_TXRDY_Pos 1 /**< \brief (TWIS_SR) TX Buffer Ready */ 254 #define TWIS_SR_TXRDY (_U_(0x1) << TWIS_SR_TXRDY_Pos) 255 #define TWIS_SR_SEN_Pos 2 /**< \brief (TWIS_SR) Slave Enabled */ 256 #define TWIS_SR_SEN (_U_(0x1) << TWIS_SR_SEN_Pos) 257 #define TWIS_SR_TCOMP_Pos 3 /**< \brief (TWIS_SR) Transmission Complete */ 258 #define TWIS_SR_TCOMP (_U_(0x1) << TWIS_SR_TCOMP_Pos) 259 #define TWIS_SR_TRA_Pos 5 /**< \brief (TWIS_SR) Transmitter Mode */ 260 #define TWIS_SR_TRA (_U_(0x1) << TWIS_SR_TRA_Pos) 261 #define TWIS_SR_URUN_Pos 6 /**< \brief (TWIS_SR) Underrun */ 262 #define TWIS_SR_URUN (_U_(0x1) << TWIS_SR_URUN_Pos) 263 #define TWIS_SR_ORUN_Pos 7 /**< \brief (TWIS_SR) Overrun */ 264 #define TWIS_SR_ORUN (_U_(0x1) << TWIS_SR_ORUN_Pos) 265 #define TWIS_SR_NAK_Pos 8 /**< \brief (TWIS_SR) NAK Received */ 266 #define TWIS_SR_NAK (_U_(0x1) << TWIS_SR_NAK_Pos) 267 #define TWIS_SR_SMBTOUT_Pos 12 /**< \brief (TWIS_SR) SMBus Timeout */ 268 #define TWIS_SR_SMBTOUT (_U_(0x1) << TWIS_SR_SMBTOUT_Pos) 269 #define TWIS_SR_SMBPECERR_Pos 13 /**< \brief (TWIS_SR) SMBus PEC Error */ 270 #define TWIS_SR_SMBPECERR (_U_(0x1) << TWIS_SR_SMBPECERR_Pos) 271 #define TWIS_SR_BUSERR_Pos 14 /**< \brief (TWIS_SR) Bus Error */ 272 #define TWIS_SR_BUSERR (_U_(0x1) << TWIS_SR_BUSERR_Pos) 273 #define TWIS_SR_SAM_Pos 16 /**< \brief (TWIS_SR) Slave Address Match */ 274 #define TWIS_SR_SAM (_U_(0x1) << TWIS_SR_SAM_Pos) 275 #define TWIS_SR_GCM_Pos 17 /**< \brief (TWIS_SR) General Call Match */ 276 #define TWIS_SR_GCM (_U_(0x1) << TWIS_SR_GCM_Pos) 277 #define TWIS_SR_SMBALERTM_Pos 18 /**< \brief (TWIS_SR) SMBus Alert Response Address Match */ 278 #define TWIS_SR_SMBALERTM (_U_(0x1) << TWIS_SR_SMBALERTM_Pos) 279 #define TWIS_SR_SMBHHM_Pos 19 /**< \brief (TWIS_SR) SMBus Host Header Address Match */ 280 #define TWIS_SR_SMBHHM (_U_(0x1) << TWIS_SR_SMBHHM_Pos) 281 #define TWIS_SR_SMBDAM_Pos 20 /**< \brief (TWIS_SR) SMBus Default Address Match */ 282 #define TWIS_SR_SMBDAM (_U_(0x1) << TWIS_SR_SMBDAM_Pos) 283 #define TWIS_SR_STO_Pos 21 /**< \brief (TWIS_SR) Stop Received */ 284 #define TWIS_SR_STO (_U_(0x1) << TWIS_SR_STO_Pos) 285 #define TWIS_SR_REP_Pos 22 /**< \brief (TWIS_SR) Repeated Start Received */ 286 #define TWIS_SR_REP (_U_(0x1) << TWIS_SR_REP_Pos) 287 #define TWIS_SR_BTF_Pos 23 /**< \brief (TWIS_SR) Byte Transfer Finished */ 288 #define TWIS_SR_BTF (_U_(0x1) << TWIS_SR_BTF_Pos) 289 #define TWIS_SR_MASK _U_(0x00FF71EF) /**< \brief (TWIS_SR) MASK Register */ 290 291 /* -------- TWIS_IER : (TWIS Offset: 0x1C) ( /W 32) Interrupt Enable Register -------- */ 292 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 293 typedef union { 294 struct { 295 uint32_t RXRDY:1; /*!< bit: 0 RX Buffer Ready */ 296 uint32_t TXRDY:1; /*!< bit: 1 TX Buffer Ready */ 297 uint32_t :1; /*!< bit: 2 Reserved */ 298 uint32_t TCOMP:1; /*!< bit: 3 Transmission Complete */ 299 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 300 uint32_t URUN:1; /*!< bit: 6 Underrun */ 301 uint32_t ORUN:1; /*!< bit: 7 Overrun */ 302 uint32_t NAK:1; /*!< bit: 8 NAK Received */ 303 uint32_t :3; /*!< bit: 9..11 Reserved */ 304 uint32_t SMBTOUT:1; /*!< bit: 12 SMBus Timeout */ 305 uint32_t SMBPECERR:1; /*!< bit: 13 SMBus PEC Error */ 306 uint32_t BUSERR:1; /*!< bit: 14 Bus Error */ 307 uint32_t :1; /*!< bit: 15 Reserved */ 308 uint32_t SAM:1; /*!< bit: 16 Slave Address Match */ 309 uint32_t GCM:1; /*!< bit: 17 General Call Match */ 310 uint32_t SMBALERTM:1; /*!< bit: 18 SMBus Alert Response Address Match */ 311 uint32_t SMBHHM:1; /*!< bit: 19 SMBus Host Header Address Match */ 312 uint32_t SMBDAM:1; /*!< bit: 20 SMBus Default Address Match */ 313 uint32_t STO:1; /*!< bit: 21 Stop Received */ 314 uint32_t REP:1; /*!< bit: 22 Repeated Start Received */ 315 uint32_t BTF:1; /*!< bit: 23 Byte Transfer Finished */ 316 uint32_t :8; /*!< bit: 24..31 Reserved */ 317 } bit; /*!< Structure used for bit access */ 318 uint32_t reg; /*!< Type used for register access */ 319 } TWIS_IER_Type; 320 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 321 322 #define TWIS_IER_OFFSET 0x1C /**< \brief (TWIS_IER offset) Interrupt Enable Register */ 323 #define TWIS_IER_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_IER reset_value) Interrupt Enable Register */ 324 325 #define TWIS_IER_RXRDY_Pos 0 /**< \brief (TWIS_IER) RX Buffer Ready */ 326 #define TWIS_IER_RXRDY (_U_(0x1) << TWIS_IER_RXRDY_Pos) 327 #define TWIS_IER_TXRDY_Pos 1 /**< \brief (TWIS_IER) TX Buffer Ready */ 328 #define TWIS_IER_TXRDY (_U_(0x1) << TWIS_IER_TXRDY_Pos) 329 #define TWIS_IER_TCOMP_Pos 3 /**< \brief (TWIS_IER) Transmission Complete */ 330 #define TWIS_IER_TCOMP (_U_(0x1) << TWIS_IER_TCOMP_Pos) 331 #define TWIS_IER_URUN_Pos 6 /**< \brief (TWIS_IER) Underrun */ 332 #define TWIS_IER_URUN (_U_(0x1) << TWIS_IER_URUN_Pos) 333 #define TWIS_IER_ORUN_Pos 7 /**< \brief (TWIS_IER) Overrun */ 334 #define TWIS_IER_ORUN (_U_(0x1) << TWIS_IER_ORUN_Pos) 335 #define TWIS_IER_NAK_Pos 8 /**< \brief (TWIS_IER) NAK Received */ 336 #define TWIS_IER_NAK (_U_(0x1) << TWIS_IER_NAK_Pos) 337 #define TWIS_IER_SMBTOUT_Pos 12 /**< \brief (TWIS_IER) SMBus Timeout */ 338 #define TWIS_IER_SMBTOUT (_U_(0x1) << TWIS_IER_SMBTOUT_Pos) 339 #define TWIS_IER_SMBPECERR_Pos 13 /**< \brief (TWIS_IER) SMBus PEC Error */ 340 #define TWIS_IER_SMBPECERR (_U_(0x1) << TWIS_IER_SMBPECERR_Pos) 341 #define TWIS_IER_BUSERR_Pos 14 /**< \brief (TWIS_IER) Bus Error */ 342 #define TWIS_IER_BUSERR (_U_(0x1) << TWIS_IER_BUSERR_Pos) 343 #define TWIS_IER_SAM_Pos 16 /**< \brief (TWIS_IER) Slave Address Match */ 344 #define TWIS_IER_SAM (_U_(0x1) << TWIS_IER_SAM_Pos) 345 #define TWIS_IER_GCM_Pos 17 /**< \brief (TWIS_IER) General Call Match */ 346 #define TWIS_IER_GCM (_U_(0x1) << TWIS_IER_GCM_Pos) 347 #define TWIS_IER_SMBALERTM_Pos 18 /**< \brief (TWIS_IER) SMBus Alert Response Address Match */ 348 #define TWIS_IER_SMBALERTM (_U_(0x1) << TWIS_IER_SMBALERTM_Pos) 349 #define TWIS_IER_SMBHHM_Pos 19 /**< \brief (TWIS_IER) SMBus Host Header Address Match */ 350 #define TWIS_IER_SMBHHM (_U_(0x1) << TWIS_IER_SMBHHM_Pos) 351 #define TWIS_IER_SMBDAM_Pos 20 /**< \brief (TWIS_IER) SMBus Default Address Match */ 352 #define TWIS_IER_SMBDAM (_U_(0x1) << TWIS_IER_SMBDAM_Pos) 353 #define TWIS_IER_STO_Pos 21 /**< \brief (TWIS_IER) Stop Received */ 354 #define TWIS_IER_STO (_U_(0x1) << TWIS_IER_STO_Pos) 355 #define TWIS_IER_REP_Pos 22 /**< \brief (TWIS_IER) Repeated Start Received */ 356 #define TWIS_IER_REP (_U_(0x1) << TWIS_IER_REP_Pos) 357 #define TWIS_IER_BTF_Pos 23 /**< \brief (TWIS_IER) Byte Transfer Finished */ 358 #define TWIS_IER_BTF (_U_(0x1) << TWIS_IER_BTF_Pos) 359 #define TWIS_IER_MASK _U_(0x00FF71CB) /**< \brief (TWIS_IER) MASK Register */ 360 361 /* -------- TWIS_IDR : (TWIS Offset: 0x20) ( /W 32) Interrupt Disable Register -------- */ 362 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 363 typedef union { 364 struct { 365 uint32_t RXRDY:1; /*!< bit: 0 RX Buffer Ready */ 366 uint32_t TXRDY:1; /*!< bit: 1 TX Buffer Ready */ 367 uint32_t :1; /*!< bit: 2 Reserved */ 368 uint32_t TCOMP:1; /*!< bit: 3 Transmission Complete */ 369 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 370 uint32_t URUN:1; /*!< bit: 6 Underrun */ 371 uint32_t ORUN:1; /*!< bit: 7 Overrun */ 372 uint32_t NAK:1; /*!< bit: 8 NAK Received */ 373 uint32_t :3; /*!< bit: 9..11 Reserved */ 374 uint32_t SMBTOUT:1; /*!< bit: 12 SMBus Timeout */ 375 uint32_t SMBPECERR:1; /*!< bit: 13 SMBus PEC Error */ 376 uint32_t BUSERR:1; /*!< bit: 14 Bus Error */ 377 uint32_t :1; /*!< bit: 15 Reserved */ 378 uint32_t SAM:1; /*!< bit: 16 Slave Address Match */ 379 uint32_t GCM:1; /*!< bit: 17 General Call Match */ 380 uint32_t SMBALERTM:1; /*!< bit: 18 SMBus Alert Response Address Match */ 381 uint32_t SMBHHM:1; /*!< bit: 19 SMBus Host Header Address Match */ 382 uint32_t SMBDAM:1; /*!< bit: 20 SMBus Default Address Match */ 383 uint32_t STO:1; /*!< bit: 21 Stop Received */ 384 uint32_t REP:1; /*!< bit: 22 Repeated Start Received */ 385 uint32_t BTF:1; /*!< bit: 23 Byte Transfer Finished */ 386 uint32_t :8; /*!< bit: 24..31 Reserved */ 387 } bit; /*!< Structure used for bit access */ 388 uint32_t reg; /*!< Type used for register access */ 389 } TWIS_IDR_Type; 390 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 391 392 #define TWIS_IDR_OFFSET 0x20 /**< \brief (TWIS_IDR offset) Interrupt Disable Register */ 393 #define TWIS_IDR_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_IDR reset_value) Interrupt Disable Register */ 394 395 #define TWIS_IDR_RXRDY_Pos 0 /**< \brief (TWIS_IDR) RX Buffer Ready */ 396 #define TWIS_IDR_RXRDY (_U_(0x1) << TWIS_IDR_RXRDY_Pos) 397 #define TWIS_IDR_TXRDY_Pos 1 /**< \brief (TWIS_IDR) TX Buffer Ready */ 398 #define TWIS_IDR_TXRDY (_U_(0x1) << TWIS_IDR_TXRDY_Pos) 399 #define TWIS_IDR_TCOMP_Pos 3 /**< \brief (TWIS_IDR) Transmission Complete */ 400 #define TWIS_IDR_TCOMP (_U_(0x1) << TWIS_IDR_TCOMP_Pos) 401 #define TWIS_IDR_URUN_Pos 6 /**< \brief (TWIS_IDR) Underrun */ 402 #define TWIS_IDR_URUN (_U_(0x1) << TWIS_IDR_URUN_Pos) 403 #define TWIS_IDR_ORUN_Pos 7 /**< \brief (TWIS_IDR) Overrun */ 404 #define TWIS_IDR_ORUN (_U_(0x1) << TWIS_IDR_ORUN_Pos) 405 #define TWIS_IDR_NAK_Pos 8 /**< \brief (TWIS_IDR) NAK Received */ 406 #define TWIS_IDR_NAK (_U_(0x1) << TWIS_IDR_NAK_Pos) 407 #define TWIS_IDR_SMBTOUT_Pos 12 /**< \brief (TWIS_IDR) SMBus Timeout */ 408 #define TWIS_IDR_SMBTOUT (_U_(0x1) << TWIS_IDR_SMBTOUT_Pos) 409 #define TWIS_IDR_SMBPECERR_Pos 13 /**< \brief (TWIS_IDR) SMBus PEC Error */ 410 #define TWIS_IDR_SMBPECERR (_U_(0x1) << TWIS_IDR_SMBPECERR_Pos) 411 #define TWIS_IDR_BUSERR_Pos 14 /**< \brief (TWIS_IDR) Bus Error */ 412 #define TWIS_IDR_BUSERR (_U_(0x1) << TWIS_IDR_BUSERR_Pos) 413 #define TWIS_IDR_SAM_Pos 16 /**< \brief (TWIS_IDR) Slave Address Match */ 414 #define TWIS_IDR_SAM (_U_(0x1) << TWIS_IDR_SAM_Pos) 415 #define TWIS_IDR_GCM_Pos 17 /**< \brief (TWIS_IDR) General Call Match */ 416 #define TWIS_IDR_GCM (_U_(0x1) << TWIS_IDR_GCM_Pos) 417 #define TWIS_IDR_SMBALERTM_Pos 18 /**< \brief (TWIS_IDR) SMBus Alert Response Address Match */ 418 #define TWIS_IDR_SMBALERTM (_U_(0x1) << TWIS_IDR_SMBALERTM_Pos) 419 #define TWIS_IDR_SMBHHM_Pos 19 /**< \brief (TWIS_IDR) SMBus Host Header Address Match */ 420 #define TWIS_IDR_SMBHHM (_U_(0x1) << TWIS_IDR_SMBHHM_Pos) 421 #define TWIS_IDR_SMBDAM_Pos 20 /**< \brief (TWIS_IDR) SMBus Default Address Match */ 422 #define TWIS_IDR_SMBDAM (_U_(0x1) << TWIS_IDR_SMBDAM_Pos) 423 #define TWIS_IDR_STO_Pos 21 /**< \brief (TWIS_IDR) Stop Received */ 424 #define TWIS_IDR_STO (_U_(0x1) << TWIS_IDR_STO_Pos) 425 #define TWIS_IDR_REP_Pos 22 /**< \brief (TWIS_IDR) Repeated Start Received */ 426 #define TWIS_IDR_REP (_U_(0x1) << TWIS_IDR_REP_Pos) 427 #define TWIS_IDR_BTF_Pos 23 /**< \brief (TWIS_IDR) Byte Transfer Finished */ 428 #define TWIS_IDR_BTF (_U_(0x1) << TWIS_IDR_BTF_Pos) 429 #define TWIS_IDR_MASK _U_(0x00FF71CB) /**< \brief (TWIS_IDR) MASK Register */ 430 431 /* -------- TWIS_IMR : (TWIS Offset: 0x24) (R/ 32) Interrupt Mask Register -------- */ 432 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 433 typedef union { 434 struct { 435 uint32_t RXRDY:1; /*!< bit: 0 RX Buffer Ready */ 436 uint32_t TXRDY:1; /*!< bit: 1 TX Buffer Ready */ 437 uint32_t :1; /*!< bit: 2 Reserved */ 438 uint32_t TCOMP:1; /*!< bit: 3 Transmission Complete */ 439 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 440 uint32_t URUN:1; /*!< bit: 6 Underrun */ 441 uint32_t ORUN:1; /*!< bit: 7 Overrun */ 442 uint32_t NAK:1; /*!< bit: 8 NAK Received */ 443 uint32_t :3; /*!< bit: 9..11 Reserved */ 444 uint32_t SMBTOUT:1; /*!< bit: 12 SMBus Timeout */ 445 uint32_t SMBPECERR:1; /*!< bit: 13 SMBus PEC Error */ 446 uint32_t BUSERR:1; /*!< bit: 14 Bus Error */ 447 uint32_t :1; /*!< bit: 15 Reserved */ 448 uint32_t SAM:1; /*!< bit: 16 Slave Address Match */ 449 uint32_t GCM:1; /*!< bit: 17 General Call Match */ 450 uint32_t SMBALERTM:1; /*!< bit: 18 SMBus Alert Response Address Match */ 451 uint32_t SMBHHM:1; /*!< bit: 19 SMBus Host Header Address Match */ 452 uint32_t SMBDAM:1; /*!< bit: 20 SMBus Default Address Match */ 453 uint32_t STO:1; /*!< bit: 21 Stop Received */ 454 uint32_t REP:1; /*!< bit: 22 Repeated Start Received */ 455 uint32_t BTF:1; /*!< bit: 23 Byte Transfer Finished */ 456 uint32_t :8; /*!< bit: 24..31 Reserved */ 457 } bit; /*!< Structure used for bit access */ 458 uint32_t reg; /*!< Type used for register access */ 459 } TWIS_IMR_Type; 460 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 461 462 #define TWIS_IMR_OFFSET 0x24 /**< \brief (TWIS_IMR offset) Interrupt Mask Register */ 463 #define TWIS_IMR_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_IMR reset_value) Interrupt Mask Register */ 464 465 #define TWIS_IMR_RXRDY_Pos 0 /**< \brief (TWIS_IMR) RX Buffer Ready */ 466 #define TWIS_IMR_RXRDY (_U_(0x1) << TWIS_IMR_RXRDY_Pos) 467 #define TWIS_IMR_TXRDY_Pos 1 /**< \brief (TWIS_IMR) TX Buffer Ready */ 468 #define TWIS_IMR_TXRDY (_U_(0x1) << TWIS_IMR_TXRDY_Pos) 469 #define TWIS_IMR_TCOMP_Pos 3 /**< \brief (TWIS_IMR) Transmission Complete */ 470 #define TWIS_IMR_TCOMP (_U_(0x1) << TWIS_IMR_TCOMP_Pos) 471 #define TWIS_IMR_URUN_Pos 6 /**< \brief (TWIS_IMR) Underrun */ 472 #define TWIS_IMR_URUN (_U_(0x1) << TWIS_IMR_URUN_Pos) 473 #define TWIS_IMR_ORUN_Pos 7 /**< \brief (TWIS_IMR) Overrun */ 474 #define TWIS_IMR_ORUN (_U_(0x1) << TWIS_IMR_ORUN_Pos) 475 #define TWIS_IMR_NAK_Pos 8 /**< \brief (TWIS_IMR) NAK Received */ 476 #define TWIS_IMR_NAK (_U_(0x1) << TWIS_IMR_NAK_Pos) 477 #define TWIS_IMR_SMBTOUT_Pos 12 /**< \brief (TWIS_IMR) SMBus Timeout */ 478 #define TWIS_IMR_SMBTOUT (_U_(0x1) << TWIS_IMR_SMBTOUT_Pos) 479 #define TWIS_IMR_SMBPECERR_Pos 13 /**< \brief (TWIS_IMR) SMBus PEC Error */ 480 #define TWIS_IMR_SMBPECERR (_U_(0x1) << TWIS_IMR_SMBPECERR_Pos) 481 #define TWIS_IMR_BUSERR_Pos 14 /**< \brief (TWIS_IMR) Bus Error */ 482 #define TWIS_IMR_BUSERR (_U_(0x1) << TWIS_IMR_BUSERR_Pos) 483 #define TWIS_IMR_SAM_Pos 16 /**< \brief (TWIS_IMR) Slave Address Match */ 484 #define TWIS_IMR_SAM (_U_(0x1) << TWIS_IMR_SAM_Pos) 485 #define TWIS_IMR_GCM_Pos 17 /**< \brief (TWIS_IMR) General Call Match */ 486 #define TWIS_IMR_GCM (_U_(0x1) << TWIS_IMR_GCM_Pos) 487 #define TWIS_IMR_SMBALERTM_Pos 18 /**< \brief (TWIS_IMR) SMBus Alert Response Address Match */ 488 #define TWIS_IMR_SMBALERTM (_U_(0x1) << TWIS_IMR_SMBALERTM_Pos) 489 #define TWIS_IMR_SMBHHM_Pos 19 /**< \brief (TWIS_IMR) SMBus Host Header Address Match */ 490 #define TWIS_IMR_SMBHHM (_U_(0x1) << TWIS_IMR_SMBHHM_Pos) 491 #define TWIS_IMR_SMBDAM_Pos 20 /**< \brief (TWIS_IMR) SMBus Default Address Match */ 492 #define TWIS_IMR_SMBDAM (_U_(0x1) << TWIS_IMR_SMBDAM_Pos) 493 #define TWIS_IMR_STO_Pos 21 /**< \brief (TWIS_IMR) Stop Received */ 494 #define TWIS_IMR_STO (_U_(0x1) << TWIS_IMR_STO_Pos) 495 #define TWIS_IMR_REP_Pos 22 /**< \brief (TWIS_IMR) Repeated Start Received */ 496 #define TWIS_IMR_REP (_U_(0x1) << TWIS_IMR_REP_Pos) 497 #define TWIS_IMR_BTF_Pos 23 /**< \brief (TWIS_IMR) Byte Transfer Finished */ 498 #define TWIS_IMR_BTF (_U_(0x1) << TWIS_IMR_BTF_Pos) 499 #define TWIS_IMR_MASK _U_(0x00FF71CB) /**< \brief (TWIS_IMR) MASK Register */ 500 501 /* -------- TWIS_SCR : (TWIS Offset: 0x28) ( /W 32) Status Clear Register -------- */ 502 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 503 typedef union { 504 struct { 505 uint32_t :3; /*!< bit: 0.. 2 Reserved */ 506 uint32_t TCOMP:1; /*!< bit: 3 Transmission Complete */ 507 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 508 uint32_t URUN:1; /*!< bit: 6 Underrun */ 509 uint32_t ORUN:1; /*!< bit: 7 Overrun */ 510 uint32_t NAK:1; /*!< bit: 8 NAK Received */ 511 uint32_t :3; /*!< bit: 9..11 Reserved */ 512 uint32_t SMBTOUT:1; /*!< bit: 12 SMBus Timeout */ 513 uint32_t SMBPECERR:1; /*!< bit: 13 SMBus PEC Error */ 514 uint32_t BUSERR:1; /*!< bit: 14 Bus Error */ 515 uint32_t :1; /*!< bit: 15 Reserved */ 516 uint32_t SAM:1; /*!< bit: 16 Slave Address Match */ 517 uint32_t GCM:1; /*!< bit: 17 General Call Match */ 518 uint32_t SMBALERTM:1; /*!< bit: 18 SMBus Alert Response Address Match */ 519 uint32_t SMBHHM:1; /*!< bit: 19 SMBus Host Header Address Match */ 520 uint32_t SMBDAM:1; /*!< bit: 20 SMBus Default Address Match */ 521 uint32_t STO:1; /*!< bit: 21 Stop Received */ 522 uint32_t REP:1; /*!< bit: 22 Repeated Start Received */ 523 uint32_t BTF:1; /*!< bit: 23 Byte Transfer Finished */ 524 uint32_t :8; /*!< bit: 24..31 Reserved */ 525 } bit; /*!< Structure used for bit access */ 526 uint32_t reg; /*!< Type used for register access */ 527 } TWIS_SCR_Type; 528 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 529 530 #define TWIS_SCR_OFFSET 0x28 /**< \brief (TWIS_SCR offset) Status Clear Register */ 531 #define TWIS_SCR_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_SCR reset_value) Status Clear Register */ 532 533 #define TWIS_SCR_TCOMP_Pos 3 /**< \brief (TWIS_SCR) Transmission Complete */ 534 #define TWIS_SCR_TCOMP (_U_(0x1) << TWIS_SCR_TCOMP_Pos) 535 #define TWIS_SCR_URUN_Pos 6 /**< \brief (TWIS_SCR) Underrun */ 536 #define TWIS_SCR_URUN (_U_(0x1) << TWIS_SCR_URUN_Pos) 537 #define TWIS_SCR_ORUN_Pos 7 /**< \brief (TWIS_SCR) Overrun */ 538 #define TWIS_SCR_ORUN (_U_(0x1) << TWIS_SCR_ORUN_Pos) 539 #define TWIS_SCR_NAK_Pos 8 /**< \brief (TWIS_SCR) NAK Received */ 540 #define TWIS_SCR_NAK (_U_(0x1) << TWIS_SCR_NAK_Pos) 541 #define TWIS_SCR_SMBTOUT_Pos 12 /**< \brief (TWIS_SCR) SMBus Timeout */ 542 #define TWIS_SCR_SMBTOUT (_U_(0x1) << TWIS_SCR_SMBTOUT_Pos) 543 #define TWIS_SCR_SMBPECERR_Pos 13 /**< \brief (TWIS_SCR) SMBus PEC Error */ 544 #define TWIS_SCR_SMBPECERR (_U_(0x1) << TWIS_SCR_SMBPECERR_Pos) 545 #define TWIS_SCR_BUSERR_Pos 14 /**< \brief (TWIS_SCR) Bus Error */ 546 #define TWIS_SCR_BUSERR (_U_(0x1) << TWIS_SCR_BUSERR_Pos) 547 #define TWIS_SCR_SAM_Pos 16 /**< \brief (TWIS_SCR) Slave Address Match */ 548 #define TWIS_SCR_SAM (_U_(0x1) << TWIS_SCR_SAM_Pos) 549 #define TWIS_SCR_GCM_Pos 17 /**< \brief (TWIS_SCR) General Call Match */ 550 #define TWIS_SCR_GCM (_U_(0x1) << TWIS_SCR_GCM_Pos) 551 #define TWIS_SCR_SMBALERTM_Pos 18 /**< \brief (TWIS_SCR) SMBus Alert Response Address Match */ 552 #define TWIS_SCR_SMBALERTM (_U_(0x1) << TWIS_SCR_SMBALERTM_Pos) 553 #define TWIS_SCR_SMBHHM_Pos 19 /**< \brief (TWIS_SCR) SMBus Host Header Address Match */ 554 #define TWIS_SCR_SMBHHM (_U_(0x1) << TWIS_SCR_SMBHHM_Pos) 555 #define TWIS_SCR_SMBDAM_Pos 20 /**< \brief (TWIS_SCR) SMBus Default Address Match */ 556 #define TWIS_SCR_SMBDAM (_U_(0x1) << TWIS_SCR_SMBDAM_Pos) 557 #define TWIS_SCR_STO_Pos 21 /**< \brief (TWIS_SCR) Stop Received */ 558 #define TWIS_SCR_STO (_U_(0x1) << TWIS_SCR_STO_Pos) 559 #define TWIS_SCR_REP_Pos 22 /**< \brief (TWIS_SCR) Repeated Start Received */ 560 #define TWIS_SCR_REP (_U_(0x1) << TWIS_SCR_REP_Pos) 561 #define TWIS_SCR_BTF_Pos 23 /**< \brief (TWIS_SCR) Byte Transfer Finished */ 562 #define TWIS_SCR_BTF (_U_(0x1) << TWIS_SCR_BTF_Pos) 563 #define TWIS_SCR_MASK _U_(0x00FF71C8) /**< \brief (TWIS_SCR) MASK Register */ 564 565 /* -------- TWIS_PR : (TWIS Offset: 0x2C) (R/ 32) Parameter Register -------- */ 566 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 567 typedef union { 568 struct { 569 uint32_t HS:1; /*!< bit: 0 HS-mode */ 570 uint32_t :31; /*!< bit: 1..31 Reserved */ 571 } bit; /*!< Structure used for bit access */ 572 uint32_t reg; /*!< Type used for register access */ 573 } TWIS_PR_Type; 574 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 575 576 #define TWIS_PR_OFFSET 0x2C /**< \brief (TWIS_PR offset) Parameter Register */ 577 #define TWIS_PR_RESETVALUE _U_(0x00000001); /**< \brief (TWIS_PR reset_value) Parameter Register */ 578 579 #define TWIS_PR_HS_Pos 0 /**< \brief (TWIS_PR) HS-mode */ 580 #define TWIS_PR_HS (_U_(0x1) << TWIS_PR_HS_Pos) 581 #define TWIS_PR_MASK _U_(0x00000001) /**< \brief (TWIS_PR) MASK Register */ 582 583 /* -------- TWIS_VR : (TWIS Offset: 0x30) (R/ 32) Version Register -------- */ 584 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 585 typedef union { 586 struct { 587 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 588 uint32_t :4; /*!< bit: 12..15 Reserved */ 589 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 590 uint32_t :12; /*!< bit: 20..31 Reserved */ 591 } bit; /*!< Structure used for bit access */ 592 uint32_t reg; /*!< Type used for register access */ 593 } TWIS_VR_Type; 594 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 595 596 #define TWIS_VR_OFFSET 0x30 /**< \brief (TWIS_VR offset) Version Register */ 597 #define TWIS_VR_RESETVALUE _U_(0x00000140); /**< \brief (TWIS_VR reset_value) Version Register */ 598 599 #define TWIS_VR_VERSION_Pos 0 /**< \brief (TWIS_VR) Version Number */ 600 #define TWIS_VR_VERSION_Msk (_U_(0xFFF) << TWIS_VR_VERSION_Pos) 601 #define TWIS_VR_VERSION(value) (TWIS_VR_VERSION_Msk & ((value) << TWIS_VR_VERSION_Pos)) 602 #define TWIS_VR_VARIANT_Pos 16 /**< \brief (TWIS_VR) Variant Number */ 603 #define TWIS_VR_VARIANT_Msk (_U_(0xF) << TWIS_VR_VARIANT_Pos) 604 #define TWIS_VR_VARIANT(value) (TWIS_VR_VARIANT_Msk & ((value) << TWIS_VR_VARIANT_Pos)) 605 #define TWIS_VR_MASK _U_(0x000F0FFF) /**< \brief (TWIS_VR) MASK Register */ 606 607 /* -------- TWIS_HSTR : (TWIS Offset: 0x34) (R/W 32) HS-mode Timing Register -------- */ 608 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 609 typedef union { 610 struct { 611 uint32_t :16; /*!< bit: 0..15 Reserved */ 612 uint32_t HDDAT:8; /*!< bit: 16..23 Data Hold Cycles */ 613 uint32_t :8; /*!< bit: 24..31 Reserved */ 614 } bit; /*!< Structure used for bit access */ 615 uint32_t reg; /*!< Type used for register access */ 616 } TWIS_HSTR_Type; 617 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 618 619 #define TWIS_HSTR_OFFSET 0x34 /**< \brief (TWIS_HSTR offset) HS-mode Timing Register */ 620 #define TWIS_HSTR_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_HSTR reset_value) HS-mode Timing Register */ 621 622 #define TWIS_HSTR_HDDAT_Pos 16 /**< \brief (TWIS_HSTR) Data Hold Cycles */ 623 #define TWIS_HSTR_HDDAT_Msk (_U_(0xFF) << TWIS_HSTR_HDDAT_Pos) 624 #define TWIS_HSTR_HDDAT(value) (TWIS_HSTR_HDDAT_Msk & ((value) << TWIS_HSTR_HDDAT_Pos)) 625 #define TWIS_HSTR_MASK _U_(0x00FF0000) /**< \brief (TWIS_HSTR) MASK Register */ 626 627 /* -------- TWIS_SRR : (TWIS Offset: 0x38) (R/W 32) Slew Rate Register -------- */ 628 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 629 typedef union { 630 struct { 631 uint32_t DADRIVEL:3; /*!< bit: 0.. 2 Data Drive Strength LOW */ 632 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 633 uint32_t DASLEW:2; /*!< bit: 8.. 9 Data Slew Limit */ 634 uint32_t :18; /*!< bit: 10..27 Reserved */ 635 uint32_t FILTER:2; /*!< bit: 28..29 Input Spike Filter Control */ 636 uint32_t :2; /*!< bit: 30..31 Reserved */ 637 } bit; /*!< Structure used for bit access */ 638 uint32_t reg; /*!< Type used for register access */ 639 } TWIS_SRR_Type; 640 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 641 642 #define TWIS_SRR_OFFSET 0x38 /**< \brief (TWIS_SRR offset) Slew Rate Register */ 643 #define TWIS_SRR_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_SRR reset_value) Slew Rate Register */ 644 645 #define TWIS_SRR_DADRIVEL_Pos 0 /**< \brief (TWIS_SRR) Data Drive Strength LOW */ 646 #define TWIS_SRR_DADRIVEL_Msk (_U_(0x7) << TWIS_SRR_DADRIVEL_Pos) 647 #define TWIS_SRR_DADRIVEL(value) (TWIS_SRR_DADRIVEL_Msk & ((value) << TWIS_SRR_DADRIVEL_Pos)) 648 #define TWIS_SRR_DASLEW_Pos 8 /**< \brief (TWIS_SRR) Data Slew Limit */ 649 #define TWIS_SRR_DASLEW_Msk (_U_(0x3) << TWIS_SRR_DASLEW_Pos) 650 #define TWIS_SRR_DASLEW(value) (TWIS_SRR_DASLEW_Msk & ((value) << TWIS_SRR_DASLEW_Pos)) 651 #define TWIS_SRR_FILTER_Pos 28 /**< \brief (TWIS_SRR) Input Spike Filter Control */ 652 #define TWIS_SRR_FILTER_Msk (_U_(0x3) << TWIS_SRR_FILTER_Pos) 653 #define TWIS_SRR_FILTER(value) (TWIS_SRR_FILTER_Msk & ((value) << TWIS_SRR_FILTER_Pos)) 654 #define TWIS_SRR_MASK _U_(0x30000307) /**< \brief (TWIS_SRR) MASK Register */ 655 656 /* -------- TWIS_HSSRR : (TWIS Offset: 0x3C) (R/W 32) HS-mode Slew Rate Register -------- */ 657 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 658 typedef union { 659 struct { 660 uint32_t DADRIVEL:3; /*!< bit: 0.. 2 Data Drive Strength LOW */ 661 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 662 uint32_t DASLEW:2; /*!< bit: 8.. 9 Data Slew Limit */ 663 uint32_t :18; /*!< bit: 10..27 Reserved */ 664 uint32_t FILTER:2; /*!< bit: 28..29 Input Spike Filter Control */ 665 uint32_t :2; /*!< bit: 30..31 Reserved */ 666 } bit; /*!< Structure used for bit access */ 667 uint32_t reg; /*!< Type used for register access */ 668 } TWIS_HSSRR_Type; 669 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 670 671 #define TWIS_HSSRR_OFFSET 0x3C /**< \brief (TWIS_HSSRR offset) HS-mode Slew Rate Register */ 672 #define TWIS_HSSRR_RESETVALUE _U_(0x00000000); /**< \brief (TWIS_HSSRR reset_value) HS-mode Slew Rate Register */ 673 674 #define TWIS_HSSRR_DADRIVEL_Pos 0 /**< \brief (TWIS_HSSRR) Data Drive Strength LOW */ 675 #define TWIS_HSSRR_DADRIVEL_Msk (_U_(0x7) << TWIS_HSSRR_DADRIVEL_Pos) 676 #define TWIS_HSSRR_DADRIVEL(value) (TWIS_HSSRR_DADRIVEL_Msk & ((value) << TWIS_HSSRR_DADRIVEL_Pos)) 677 #define TWIS_HSSRR_DASLEW_Pos 8 /**< \brief (TWIS_HSSRR) Data Slew Limit */ 678 #define TWIS_HSSRR_DASLEW_Msk (_U_(0x3) << TWIS_HSSRR_DASLEW_Pos) 679 #define TWIS_HSSRR_DASLEW(value) (TWIS_HSSRR_DASLEW_Msk & ((value) << TWIS_HSSRR_DASLEW_Pos)) 680 #define TWIS_HSSRR_FILTER_Pos 28 /**< \brief (TWIS_HSSRR) Input Spike Filter Control */ 681 #define TWIS_HSSRR_FILTER_Msk (_U_(0x3) << TWIS_HSSRR_FILTER_Pos) 682 #define TWIS_HSSRR_FILTER(value) (TWIS_HSSRR_FILTER_Msk & ((value) << TWIS_HSSRR_FILTER_Pos)) 683 #define TWIS_HSSRR_MASK _U_(0x30000307) /**< \brief (TWIS_HSSRR) MASK Register */ 684 685 /** \brief TWIS hardware registers */ 686 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 687 typedef struct { 688 __IO uint32_t CR; /**< \brief Offset: 0x00 (R/W 32) Control Register */ 689 __IO uint32_t NBYTES; /**< \brief Offset: 0x04 (R/W 32) NBYTES Register */ 690 __IO uint32_t TR; /**< \brief Offset: 0x08 (R/W 32) Timing Register */ 691 __I uint32_t RHR; /**< \brief Offset: 0x0C (R/ 32) Receive Holding Register */ 692 __O uint32_t THR; /**< \brief Offset: 0x10 ( /W 32) Transmit Holding Register */ 693 __I uint32_t PECR; /**< \brief Offset: 0x14 (R/ 32) Packet Error Check Register */ 694 __I uint32_t SR; /**< \brief Offset: 0x18 (R/ 32) Status Register */ 695 __O uint32_t IER; /**< \brief Offset: 0x1C ( /W 32) Interrupt Enable Register */ 696 __O uint32_t IDR; /**< \brief Offset: 0x20 ( /W 32) Interrupt Disable Register */ 697 __I uint32_t IMR; /**< \brief Offset: 0x24 (R/ 32) Interrupt Mask Register */ 698 __O uint32_t SCR; /**< \brief Offset: 0x28 ( /W 32) Status Clear Register */ 699 __I uint32_t PR; /**< \brief Offset: 0x2C (R/ 32) Parameter Register */ 700 __I uint32_t VR; /**< \brief Offset: 0x30 (R/ 32) Version Register */ 701 __IO uint32_t HSTR; /**< \brief Offset: 0x34 (R/W 32) HS-mode Timing Register */ 702 __IO uint32_t SRR; /**< \brief Offset: 0x38 (R/W 32) Slew Rate Register */ 703 __IO uint32_t HSSRR; /**< \brief Offset: 0x3C (R/W 32) HS-mode Slew Rate Register */ 704 } Twis; 705 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 706 707 /*@}*/ 708 709 #endif /* _SAM4L_TWIS_COMPONENT_ */ 710
