1 /** 2 * \file 3 * 4 * \brief Component description for PDCA 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_PDCA_COMPONENT_ 30 #define _SAM4L_PDCA_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR PDCA */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_PDCA Peripheral DMA Controller */ 36 /*@{*/ 37 38 #define PDCA_I7514 39 #define REV_PDCA 0x124 40 41 /* -------- PDCA_MAR : (PDCA Offset: 0x000) (R/W 32) channel Memory Address Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t MADDR:32; /*!< bit: 0..31 Memory Address */ 46 } bit; /*!< Structure used for bit access */ 47 uint32_t reg; /*!< Type used for register access */ 48 } PDCA_MAR_Type; 49 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 50 51 #define PDCA_MAR_OFFSET 0x000 /**< \brief (PDCA_MAR offset) Memory Address Register */ 52 #define PDCA_MAR_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_MAR reset_value) Memory Address Register */ 53 54 #define PDCA_MAR_MADDR_Pos 0 /**< \brief (PDCA_MAR) Memory Address */ 55 #define PDCA_MAR_MADDR_Msk (_U_(0xFFFFFFFF) << PDCA_MAR_MADDR_Pos) 56 #define PDCA_MAR_MADDR(value) (PDCA_MAR_MADDR_Msk & ((value) << PDCA_MAR_MADDR_Pos)) 57 #define PDCA_MAR_MASK _U_(0xFFFFFFFF) /**< \brief (PDCA_MAR) MASK Register */ 58 59 /* -------- PDCA_PSR : (PDCA Offset: 0x004) (R/W 32) channel Peripheral Select Register -------- */ 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 61 typedef union { 62 struct { 63 uint32_t PID:8; /*!< bit: 0.. 7 Peripheral Identifier */ 64 uint32_t :24; /*!< bit: 8..31 Reserved */ 65 } bit; /*!< Structure used for bit access */ 66 uint32_t reg; /*!< Type used for register access */ 67 } PDCA_PSR_Type; 68 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 70 #define PDCA_PSR_OFFSET 0x004 /**< \brief (PDCA_PSR offset) Peripheral Select Register */ 71 72 #define PDCA_PSR_PID_Pos 0 /**< \brief (PDCA_PSR) Peripheral Identifier */ 73 #define PDCA_PSR_PID_Msk (_U_(0xFF) << PDCA_PSR_PID_Pos) 74 #define PDCA_PSR_PID(value) (PDCA_PSR_PID_Msk & ((value) << PDCA_PSR_PID_Pos)) 75 #define PDCA_PSR_MASK _U_(0x000000FF) /**< \brief (PDCA_PSR) MASK Register */ 76 77 /* -------- PDCA_TCR : (PDCA Offset: 0x008) (R/W 32) channel Transfer Counter Register -------- */ 78 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 79 typedef union { 80 struct { 81 uint32_t TCV:16; /*!< bit: 0..15 Transfer Counter Value */ 82 uint32_t :16; /*!< bit: 16..31 Reserved */ 83 } bit; /*!< Structure used for bit access */ 84 uint32_t reg; /*!< Type used for register access */ 85 } PDCA_TCR_Type; 86 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 87 88 #define PDCA_TCR_OFFSET 0x008 /**< \brief (PDCA_TCR offset) Transfer Counter Register */ 89 #define PDCA_TCR_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_TCR reset_value) Transfer Counter Register */ 90 91 #define PDCA_TCR_TCV_Pos 0 /**< \brief (PDCA_TCR) Transfer Counter Value */ 92 #define PDCA_TCR_TCV_Msk (_U_(0xFFFF) << PDCA_TCR_TCV_Pos) 93 #define PDCA_TCR_TCV(value) (PDCA_TCR_TCV_Msk & ((value) << PDCA_TCR_TCV_Pos)) 94 #define PDCA_TCR_MASK _U_(0x0000FFFF) /**< \brief (PDCA_TCR) MASK Register */ 95 96 /* -------- PDCA_MARR : (PDCA Offset: 0x00C) (R/W 32) channel Memory Address Reload Register -------- */ 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 typedef union { 99 struct { 100 uint32_t MARV:32; /*!< bit: 0..31 Memory Address Reload Value */ 101 } bit; /*!< Structure used for bit access */ 102 uint32_t reg; /*!< Type used for register access */ 103 } PDCA_MARR_Type; 104 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 105 106 #define PDCA_MARR_OFFSET 0x00C /**< \brief (PDCA_MARR offset) Memory Address Reload Register */ 107 #define PDCA_MARR_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_MARR reset_value) Memory Address Reload Register */ 108 109 #define PDCA_MARR_MARV_Pos 0 /**< \brief (PDCA_MARR) Memory Address Reload Value */ 110 #define PDCA_MARR_MARV_Msk (_U_(0xFFFFFFFF) << PDCA_MARR_MARV_Pos) 111 #define PDCA_MARR_MARV(value) (PDCA_MARR_MARV_Msk & ((value) << PDCA_MARR_MARV_Pos)) 112 #define PDCA_MARR_MASK _U_(0xFFFFFFFF) /**< \brief (PDCA_MARR) MASK Register */ 113 114 /* -------- PDCA_TCRR : (PDCA Offset: 0x010) (R/W 32) channel Transfer Counter Reload Register -------- */ 115 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 116 typedef union { 117 struct { 118 uint32_t TCRV:16; /*!< bit: 0..15 Transfer Counter Reload Value */ 119 uint32_t :16; /*!< bit: 16..31 Reserved */ 120 } bit; /*!< Structure used for bit access */ 121 uint32_t reg; /*!< Type used for register access */ 122 } PDCA_TCRR_Type; 123 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 124 125 #define PDCA_TCRR_OFFSET 0x010 /**< \brief (PDCA_TCRR offset) Transfer Counter Reload Register */ 126 #define PDCA_TCRR_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_TCRR reset_value) Transfer Counter Reload Register */ 127 128 #define PDCA_TCRR_TCRV_Pos 0 /**< \brief (PDCA_TCRR) Transfer Counter Reload Value */ 129 #define PDCA_TCRR_TCRV_Msk (_U_(0xFFFF) << PDCA_TCRR_TCRV_Pos) 130 #define PDCA_TCRR_TCRV(value) (PDCA_TCRR_TCRV_Msk & ((value) << PDCA_TCRR_TCRV_Pos)) 131 #define PDCA_TCRR_MASK _U_(0x0000FFFF) /**< \brief (PDCA_TCRR) MASK Register */ 132 133 /* -------- PDCA_CR : (PDCA Offset: 0x014) ( /W 32) channel Control Register -------- */ 134 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 135 typedef union { 136 struct { 137 uint32_t TEN:1; /*!< bit: 0 Transfer Enable */ 138 uint32_t TDIS:1; /*!< bit: 1 Transfer Disable */ 139 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 140 uint32_t ECLR:1; /*!< bit: 8 Error Clear */ 141 uint32_t :23; /*!< bit: 9..31 Reserved */ 142 } bit; /*!< Structure used for bit access */ 143 uint32_t reg; /*!< Type used for register access */ 144 } PDCA_CR_Type; 145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 146 147 #define PDCA_CR_OFFSET 0x014 /**< \brief (PDCA_CR offset) Control Register */ 148 #define PDCA_CR_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_CR reset_value) Control Register */ 149 150 #define PDCA_CR_TEN_Pos 0 /**< \brief (PDCA_CR) Transfer Enable */ 151 #define PDCA_CR_TEN (_U_(0x1) << PDCA_CR_TEN_Pos) 152 #define PDCA_CR_TDIS_Pos 1 /**< \brief (PDCA_CR) Transfer Disable */ 153 #define PDCA_CR_TDIS (_U_(0x1) << PDCA_CR_TDIS_Pos) 154 #define PDCA_CR_ECLR_Pos 8 /**< \brief (PDCA_CR) Error Clear */ 155 #define PDCA_CR_ECLR (_U_(0x1) << PDCA_CR_ECLR_Pos) 156 #define PDCA_CR_MASK _U_(0x00000103) /**< \brief (PDCA_CR) MASK Register */ 157 158 /* -------- PDCA_MR : (PDCA Offset: 0x018) (R/W 32) channel Mode Register -------- */ 159 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 160 typedef union { 161 struct { 162 uint32_t SIZE:2; /*!< bit: 0.. 1 Transfer size */ 163 uint32_t ETRIG:1; /*!< bit: 2 Event trigger */ 164 uint32_t RING:1; /*!< bit: 3 Ring Buffer */ 165 uint32_t :28; /*!< bit: 4..31 Reserved */ 166 } bit; /*!< Structure used for bit access */ 167 uint32_t reg; /*!< Type used for register access */ 168 } PDCA_MR_Type; 169 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 170 171 #define PDCA_MR_OFFSET 0x018 /**< \brief (PDCA_MR offset) Mode Register */ 172 #define PDCA_MR_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_MR reset_value) Mode Register */ 173 174 #define PDCA_MR_SIZE_Pos 0 /**< \brief (PDCA_MR) Transfer size */ 175 #define PDCA_MR_SIZE_Msk (_U_(0x3) << PDCA_MR_SIZE_Pos) 176 #define PDCA_MR_SIZE(value) (PDCA_MR_SIZE_Msk & ((value) << PDCA_MR_SIZE_Pos)) 177 #define PDCA_MR_SIZE_BYTE_Val _U_(0x0) /**< \brief (PDCA_MR) */ 178 #define PDCA_MR_SIZE_HALF_WORD_Val _U_(0x1) /**< \brief (PDCA_MR) */ 179 #define PDCA_MR_SIZE_WORD_Val _U_(0x2) /**< \brief (PDCA_MR) */ 180 #define PDCA_MR_SIZE_BYTE (PDCA_MR_SIZE_BYTE_Val << PDCA_MR_SIZE_Pos) 181 #define PDCA_MR_SIZE_HALF_WORD (PDCA_MR_SIZE_HALF_WORD_Val << PDCA_MR_SIZE_Pos) 182 #define PDCA_MR_SIZE_WORD (PDCA_MR_SIZE_WORD_Val << PDCA_MR_SIZE_Pos) 183 #define PDCA_MR_ETRIG_Pos 2 /**< \brief (PDCA_MR) Event trigger */ 184 #define PDCA_MR_ETRIG (_U_(0x1) << PDCA_MR_ETRIG_Pos) 185 #define PDCA_MR_RING_Pos 3 /**< \brief (PDCA_MR) Ring Buffer */ 186 #define PDCA_MR_RING (_U_(0x1) << PDCA_MR_RING_Pos) 187 #define PDCA_MR_MASK _U_(0x0000000F) /**< \brief (PDCA_MR) MASK Register */ 188 189 /* -------- PDCA_SR : (PDCA Offset: 0x01C) (R/ 32) channel Status Register -------- */ 190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 191 typedef union { 192 struct { 193 uint32_t TEN:1; /*!< bit: 0 Transfer Enabled */ 194 uint32_t :31; /*!< bit: 1..31 Reserved */ 195 } bit; /*!< Structure used for bit access */ 196 uint32_t reg; /*!< Type used for register access */ 197 } PDCA_SR_Type; 198 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 199 200 #define PDCA_SR_OFFSET 0x01C /**< \brief (PDCA_SR offset) Status Register */ 201 #define PDCA_SR_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_SR reset_value) Status Register */ 202 203 #define PDCA_SR_TEN_Pos 0 /**< \brief (PDCA_SR) Transfer Enabled */ 204 #define PDCA_SR_TEN (_U_(0x1) << PDCA_SR_TEN_Pos) 205 #define PDCA_SR_MASK _U_(0x00000001) /**< \brief (PDCA_SR) MASK Register */ 206 207 /* -------- PDCA_IER : (PDCA Offset: 0x020) ( /W 32) channel Interrupt Enable Register -------- */ 208 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 209 typedef union { 210 struct { 211 uint32_t RCZ:1; /*!< bit: 0 Reload Counter Zero */ 212 uint32_t TRC:1; /*!< bit: 1 Transfer Complete */ 213 uint32_t TERR:1; /*!< bit: 2 Transfer Error */ 214 uint32_t :29; /*!< bit: 3..31 Reserved */ 215 } bit; /*!< Structure used for bit access */ 216 uint32_t reg; /*!< Type used for register access */ 217 } PDCA_IER_Type; 218 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 219 220 #define PDCA_IER_OFFSET 0x020 /**< \brief (PDCA_IER offset) Interrupt Enable Register */ 221 #define PDCA_IER_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_IER reset_value) Interrupt Enable Register */ 222 223 #define PDCA_IER_RCZ_Pos 0 /**< \brief (PDCA_IER) Reload Counter Zero */ 224 #define PDCA_IER_RCZ (_U_(0x1) << PDCA_IER_RCZ_Pos) 225 #define PDCA_IER_TRC_Pos 1 /**< \brief (PDCA_IER) Transfer Complete */ 226 #define PDCA_IER_TRC (_U_(0x1) << PDCA_IER_TRC_Pos) 227 #define PDCA_IER_TERR_Pos 2 /**< \brief (PDCA_IER) Transfer Error */ 228 #define PDCA_IER_TERR (_U_(0x1) << PDCA_IER_TERR_Pos) 229 #define PDCA_IER_MASK _U_(0x00000007) /**< \brief (PDCA_IER) MASK Register */ 230 231 /* -------- PDCA_IDR : (PDCA Offset: 0x024) ( /W 32) channel Interrupt Disable Register -------- */ 232 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 233 typedef union { 234 struct { 235 uint32_t RCZ:1; /*!< bit: 0 Reload Counter Zero */ 236 uint32_t TRC:1; /*!< bit: 1 Transfer Complete */ 237 uint32_t TERR:1; /*!< bit: 2 Transfer Error */ 238 uint32_t :29; /*!< bit: 3..31 Reserved */ 239 } bit; /*!< Structure used for bit access */ 240 uint32_t reg; /*!< Type used for register access */ 241 } PDCA_IDR_Type; 242 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 243 244 #define PDCA_IDR_OFFSET 0x024 /**< \brief (PDCA_IDR offset) Interrupt Disable Register */ 245 #define PDCA_IDR_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_IDR reset_value) Interrupt Disable Register */ 246 247 #define PDCA_IDR_RCZ_Pos 0 /**< \brief (PDCA_IDR) Reload Counter Zero */ 248 #define PDCA_IDR_RCZ (_U_(0x1) << PDCA_IDR_RCZ_Pos) 249 #define PDCA_IDR_TRC_Pos 1 /**< \brief (PDCA_IDR) Transfer Complete */ 250 #define PDCA_IDR_TRC (_U_(0x1) << PDCA_IDR_TRC_Pos) 251 #define PDCA_IDR_TERR_Pos 2 /**< \brief (PDCA_IDR) Transfer Error */ 252 #define PDCA_IDR_TERR (_U_(0x1) << PDCA_IDR_TERR_Pos) 253 #define PDCA_IDR_MASK _U_(0x00000007) /**< \brief (PDCA_IDR) MASK Register */ 254 255 /* -------- PDCA_IMR : (PDCA Offset: 0x028) (R/ 32) channel Interrupt Mask Register -------- */ 256 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 257 typedef union { 258 struct { 259 uint32_t RCZ:1; /*!< bit: 0 Reload Counter Zero */ 260 uint32_t TRC:1; /*!< bit: 1 Transfer Complete */ 261 uint32_t TERR:1; /*!< bit: 2 Transfer Error */ 262 uint32_t :29; /*!< bit: 3..31 Reserved */ 263 } bit; /*!< Structure used for bit access */ 264 uint32_t reg; /*!< Type used for register access */ 265 } PDCA_IMR_Type; 266 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 267 268 #define PDCA_IMR_OFFSET 0x028 /**< \brief (PDCA_IMR offset) Interrupt Mask Register */ 269 #define PDCA_IMR_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_IMR reset_value) Interrupt Mask Register */ 270 271 #define PDCA_IMR_RCZ_Pos 0 /**< \brief (PDCA_IMR) Reload Counter Zero */ 272 #define PDCA_IMR_RCZ (_U_(0x1) << PDCA_IMR_RCZ_Pos) 273 #define PDCA_IMR_TRC_Pos 1 /**< \brief (PDCA_IMR) Transfer Complete */ 274 #define PDCA_IMR_TRC (_U_(0x1) << PDCA_IMR_TRC_Pos) 275 #define PDCA_IMR_TERR_Pos 2 /**< \brief (PDCA_IMR) Transfer Error */ 276 #define PDCA_IMR_TERR (_U_(0x1) << PDCA_IMR_TERR_Pos) 277 #define PDCA_IMR_MASK _U_(0x00000007) /**< \brief (PDCA_IMR) MASK Register */ 278 279 /* -------- PDCA_ISR : (PDCA Offset: 0x02C) (R/ 32) channel Interrupt Status Register -------- */ 280 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 281 typedef union { 282 struct { 283 uint32_t RCZ:1; /*!< bit: 0 Reload Counter Zero */ 284 uint32_t TRC:1; /*!< bit: 1 Transfer Complete */ 285 uint32_t TERR:1; /*!< bit: 2 Transfer Error */ 286 uint32_t :29; /*!< bit: 3..31 Reserved */ 287 } bit; /*!< Structure used for bit access */ 288 uint32_t reg; /*!< Type used for register access */ 289 } PDCA_ISR_Type; 290 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 291 292 #define PDCA_ISR_OFFSET 0x02C /**< \brief (PDCA_ISR offset) Interrupt Status Register */ 293 #define PDCA_ISR_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_ISR reset_value) Interrupt Status Register */ 294 295 #define PDCA_ISR_RCZ_Pos 0 /**< \brief (PDCA_ISR) Reload Counter Zero */ 296 #define PDCA_ISR_RCZ (_U_(0x1) << PDCA_ISR_RCZ_Pos) 297 #define PDCA_ISR_TRC_Pos 1 /**< \brief (PDCA_ISR) Transfer Complete */ 298 #define PDCA_ISR_TRC (_U_(0x1) << PDCA_ISR_TRC_Pos) 299 #define PDCA_ISR_TERR_Pos 2 /**< \brief (PDCA_ISR) Transfer Error */ 300 #define PDCA_ISR_TERR (_U_(0x1) << PDCA_ISR_TERR_Pos) 301 #define PDCA_ISR_MASK _U_(0x00000007) /**< \brief (PDCA_ISR) MASK Register */ 302 303 /* -------- PDCA_PCONTROL : (PDCA Offset: 0x800) (R/W 32) Performance Control Register -------- */ 304 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 305 typedef union { 306 struct { 307 uint32_t CH0EN:1; /*!< bit: 0 Channel 0 Enabled */ 308 uint32_t CH1EN:1; /*!< bit: 1 Channel 1 Enabled. */ 309 uint32_t :2; /*!< bit: 2.. 3 Reserved */ 310 uint32_t CH0OF:1; /*!< bit: 4 Channel 0 Overflow Freeze */ 311 uint32_t CH1OF:1; /*!< bit: 5 Channel 1 overflow freeze */ 312 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 313 uint32_t CH0RES:1; /*!< bit: 8 Channel 0 counter reset */ 314 uint32_t CH1RES:1; /*!< bit: 9 Channel 1 counter reset */ 315 uint32_t :6; /*!< bit: 10..15 Reserved */ 316 uint32_t MON0CH:6; /*!< bit: 16..21 PDCA Channel to monitor with counter 0 */ 317 uint32_t :2; /*!< bit: 22..23 Reserved */ 318 uint32_t MON1CH:6; /*!< bit: 24..29 PDCA Channel to monitor with counter 1 */ 319 uint32_t :2; /*!< bit: 30..31 Reserved */ 320 } bit; /*!< Structure used for bit access */ 321 uint32_t reg; /*!< Type used for register access */ 322 } PDCA_PCONTROL_Type; 323 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 324 325 #define PDCA_PCONTROL_OFFSET 0x800 /**< \brief (PDCA_PCONTROL offset) Performance Control Register */ 326 #define PDCA_PCONTROL_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PCONTROL reset_value) Performance Control Register */ 327 328 #define PDCA_PCONTROL_CH0EN_Pos 0 /**< \brief (PDCA_PCONTROL) Channel 0 Enabled */ 329 #define PDCA_PCONTROL_CH0EN (_U_(0x1) << PDCA_PCONTROL_CH0EN_Pos) 330 #define PDCA_PCONTROL_CH1EN_Pos 1 /**< \brief (PDCA_PCONTROL) Channel 1 Enabled. */ 331 #define PDCA_PCONTROL_CH1EN (_U_(0x1) << PDCA_PCONTROL_CH1EN_Pos) 332 #define PDCA_PCONTROL_CH0OF_Pos 4 /**< \brief (PDCA_PCONTROL) Channel 0 Overflow Freeze */ 333 #define PDCA_PCONTROL_CH0OF (_U_(0x1) << PDCA_PCONTROL_CH0OF_Pos) 334 #define PDCA_PCONTROL_CH1OF_Pos 5 /**< \brief (PDCA_PCONTROL) Channel 1 overflow freeze */ 335 #define PDCA_PCONTROL_CH1OF (_U_(0x1) << PDCA_PCONTROL_CH1OF_Pos) 336 #define PDCA_PCONTROL_CH0RES_Pos 8 /**< \brief (PDCA_PCONTROL) Channel 0 counter reset */ 337 #define PDCA_PCONTROL_CH0RES (_U_(0x1) << PDCA_PCONTROL_CH0RES_Pos) 338 #define PDCA_PCONTROL_CH1RES_Pos 9 /**< \brief (PDCA_PCONTROL) Channel 1 counter reset */ 339 #define PDCA_PCONTROL_CH1RES (_U_(0x1) << PDCA_PCONTROL_CH1RES_Pos) 340 #define PDCA_PCONTROL_MON0CH_Pos 16 /**< \brief (PDCA_PCONTROL) PDCA Channel to monitor with counter 0 */ 341 #define PDCA_PCONTROL_MON0CH_Msk (_U_(0x3F) << PDCA_PCONTROL_MON0CH_Pos) 342 #define PDCA_PCONTROL_MON0CH(value) (PDCA_PCONTROL_MON0CH_Msk & ((value) << PDCA_PCONTROL_MON0CH_Pos)) 343 #define PDCA_PCONTROL_MON1CH_Pos 24 /**< \brief (PDCA_PCONTROL) PDCA Channel to monitor with counter 1 */ 344 #define PDCA_PCONTROL_MON1CH_Msk (_U_(0x3F) << PDCA_PCONTROL_MON1CH_Pos) 345 #define PDCA_PCONTROL_MON1CH(value) (PDCA_PCONTROL_MON1CH_Msk & ((value) << PDCA_PCONTROL_MON1CH_Pos)) 346 #define PDCA_PCONTROL_MASK _U_(0x3F3F0333) /**< \brief (PDCA_PCONTROL) MASK Register */ 347 348 /* -------- PDCA_PRDATA0 : (PDCA Offset: 0x804) (R/ 32) Channel 0 Read Data Cycles -------- */ 349 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 350 typedef union { 351 struct { 352 uint32_t DATA:32; /*!< bit: 0..31 Data Cycles Counted Since Last reset */ 353 } bit; /*!< Structure used for bit access */ 354 uint32_t reg; /*!< Type used for register access */ 355 } PDCA_PRDATA0_Type; 356 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 357 358 #define PDCA_PRDATA0_OFFSET 0x804 /**< \brief (PDCA_PRDATA0 offset) Channel 0 Read Data Cycles */ 359 #define PDCA_PRDATA0_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PRDATA0 reset_value) Channel 0 Read Data Cycles */ 360 361 #define PDCA_PRDATA0_DATA_Pos 0 /**< \brief (PDCA_PRDATA0) Data Cycles Counted Since Last reset */ 362 #define PDCA_PRDATA0_DATA_Msk (_U_(0xFFFFFFFF) << PDCA_PRDATA0_DATA_Pos) 363 #define PDCA_PRDATA0_DATA(value) (PDCA_PRDATA0_DATA_Msk & ((value) << PDCA_PRDATA0_DATA_Pos)) 364 #define PDCA_PRDATA0_MASK _U_(0xFFFFFFFF) /**< \brief (PDCA_PRDATA0) MASK Register */ 365 366 /* -------- PDCA_PRSTALL0 : (PDCA Offset: 0x808) (R/ 32) Channel 0 Read Stall Cycles -------- */ 367 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 368 typedef union { 369 struct { 370 uint32_t STALL:32; /*!< bit: 0..31 Stall Cycles counted since last reset */ 371 } bit; /*!< Structure used for bit access */ 372 uint32_t reg; /*!< Type used for register access */ 373 } PDCA_PRSTALL0_Type; 374 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 375 376 #define PDCA_PRSTALL0_OFFSET 0x808 /**< \brief (PDCA_PRSTALL0 offset) Channel 0 Read Stall Cycles */ 377 #define PDCA_PRSTALL0_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PRSTALL0 reset_value) Channel 0 Read Stall Cycles */ 378 379 #define PDCA_PRSTALL0_STALL_Pos 0 /**< \brief (PDCA_PRSTALL0) Stall Cycles counted since last reset */ 380 #define PDCA_PRSTALL0_STALL_Msk (_U_(0xFFFFFFFF) << PDCA_PRSTALL0_STALL_Pos) 381 #define PDCA_PRSTALL0_STALL(value) (PDCA_PRSTALL0_STALL_Msk & ((value) << PDCA_PRSTALL0_STALL_Pos)) 382 #define PDCA_PRSTALL0_MASK _U_(0xFFFFFFFF) /**< \brief (PDCA_PRSTALL0) MASK Register */ 383 384 /* -------- PDCA_PRLAT0 : (PDCA Offset: 0x80C) (R/ 32) Channel 0 Read Max Latency -------- */ 385 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 386 typedef union { 387 struct { 388 uint32_t LAT:16; /*!< bit: 0..15 Maximum Transfer Initiation cycles counted since last reset */ 389 uint32_t :16; /*!< bit: 16..31 Reserved */ 390 } bit; /*!< Structure used for bit access */ 391 uint32_t reg; /*!< Type used for register access */ 392 } PDCA_PRLAT0_Type; 393 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 394 395 #define PDCA_PRLAT0_OFFSET 0x80C /**< \brief (PDCA_PRLAT0 offset) Channel 0 Read Max Latency */ 396 #define PDCA_PRLAT0_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PRLAT0 reset_value) Channel 0 Read Max Latency */ 397 398 #define PDCA_PRLAT0_LAT_Pos 0 /**< \brief (PDCA_PRLAT0) Maximum Transfer Initiation cycles counted since last reset */ 399 #define PDCA_PRLAT0_LAT_Msk (_U_(0xFFFF) << PDCA_PRLAT0_LAT_Pos) 400 #define PDCA_PRLAT0_LAT(value) (PDCA_PRLAT0_LAT_Msk & ((value) << PDCA_PRLAT0_LAT_Pos)) 401 #define PDCA_PRLAT0_MASK _U_(0x0000FFFF) /**< \brief (PDCA_PRLAT0) MASK Register */ 402 403 /* -------- PDCA_PWDATA0 : (PDCA Offset: 0x810) (R/ 32) Channel 0 Write Data Cycles -------- */ 404 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 405 typedef union { 406 struct { 407 uint32_t DATA:32; /*!< bit: 0..31 Data Cycles Counted since last Reset */ 408 } bit; /*!< Structure used for bit access */ 409 uint32_t reg; /*!< Type used for register access */ 410 } PDCA_PWDATA0_Type; 411 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 412 413 #define PDCA_PWDATA0_OFFSET 0x810 /**< \brief (PDCA_PWDATA0 offset) Channel 0 Write Data Cycles */ 414 #define PDCA_PWDATA0_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PWDATA0 reset_value) Channel 0 Write Data Cycles */ 415 416 #define PDCA_PWDATA0_DATA_Pos 0 /**< \brief (PDCA_PWDATA0) Data Cycles Counted since last Reset */ 417 #define PDCA_PWDATA0_DATA_Msk (_U_(0xFFFFFFFF) << PDCA_PWDATA0_DATA_Pos) 418 #define PDCA_PWDATA0_DATA(value) (PDCA_PWDATA0_DATA_Msk & ((value) << PDCA_PWDATA0_DATA_Pos)) 419 #define PDCA_PWDATA0_MASK _U_(0xFFFFFFFF) /**< \brief (PDCA_PWDATA0) MASK Register */ 420 421 /* -------- PDCA_PWSTALL0 : (PDCA Offset: 0x814) (R/ 32) Channel 0 Write Stall Cycles -------- */ 422 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 423 typedef union { 424 struct { 425 uint32_t STALL:32; /*!< bit: 0..31 Stall cycles counted since last reset */ 426 } bit; /*!< Structure used for bit access */ 427 uint32_t reg; /*!< Type used for register access */ 428 } PDCA_PWSTALL0_Type; 429 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 430 431 #define PDCA_PWSTALL0_OFFSET 0x814 /**< \brief (PDCA_PWSTALL0 offset) Channel 0 Write Stall Cycles */ 432 #define PDCA_PWSTALL0_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PWSTALL0 reset_value) Channel 0 Write Stall Cycles */ 433 434 #define PDCA_PWSTALL0_STALL_Pos 0 /**< \brief (PDCA_PWSTALL0) Stall cycles counted since last reset */ 435 #define PDCA_PWSTALL0_STALL_Msk (_U_(0xFFFFFFFF) << PDCA_PWSTALL0_STALL_Pos) 436 #define PDCA_PWSTALL0_STALL(value) (PDCA_PWSTALL0_STALL_Msk & ((value) << PDCA_PWSTALL0_STALL_Pos)) 437 #define PDCA_PWSTALL0_MASK _U_(0xFFFFFFFF) /**< \brief (PDCA_PWSTALL0) MASK Register */ 438 439 /* -------- PDCA_PWLAT0 : (PDCA Offset: 0x818) (R/ 32) Channel0 Write Max Latency -------- */ 440 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 441 typedef union { 442 struct { 443 uint32_t LAT:16; /*!< bit: 0..15 Maximum transfer initiation cycles counted since last reset */ 444 uint32_t :16; /*!< bit: 16..31 Reserved */ 445 } bit; /*!< Structure used for bit access */ 446 uint32_t reg; /*!< Type used for register access */ 447 } PDCA_PWLAT0_Type; 448 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 449 450 #define PDCA_PWLAT0_OFFSET 0x818 /**< \brief (PDCA_PWLAT0 offset) Channel0 Write Max Latency */ 451 #define PDCA_PWLAT0_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PWLAT0 reset_value) Channel0 Write Max Latency */ 452 453 #define PDCA_PWLAT0_LAT_Pos 0 /**< \brief (PDCA_PWLAT0) Maximum transfer initiation cycles counted since last reset */ 454 #define PDCA_PWLAT0_LAT_Msk (_U_(0xFFFF) << PDCA_PWLAT0_LAT_Pos) 455 #define PDCA_PWLAT0_LAT(value) (PDCA_PWLAT0_LAT_Msk & ((value) << PDCA_PWLAT0_LAT_Pos)) 456 #define PDCA_PWLAT0_MASK _U_(0x0000FFFF) /**< \brief (PDCA_PWLAT0) MASK Register */ 457 458 /* -------- PDCA_PRDATA1 : (PDCA Offset: 0x81C) (R/ 32) Channel 1 Read Data Cycles -------- */ 459 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 460 typedef union { 461 struct { 462 uint32_t DATA:32; /*!< bit: 0..31 Data Cycles Counted Since Last reset */ 463 } bit; /*!< Structure used for bit access */ 464 uint32_t reg; /*!< Type used for register access */ 465 } PDCA_PRDATA1_Type; 466 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 467 468 #define PDCA_PRDATA1_OFFSET 0x81C /**< \brief (PDCA_PRDATA1 offset) Channel 1 Read Data Cycles */ 469 #define PDCA_PRDATA1_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PRDATA1 reset_value) Channel 1 Read Data Cycles */ 470 471 #define PDCA_PRDATA1_DATA_Pos 0 /**< \brief (PDCA_PRDATA1) Data Cycles Counted Since Last reset */ 472 #define PDCA_PRDATA1_DATA_Msk (_U_(0xFFFFFFFF) << PDCA_PRDATA1_DATA_Pos) 473 #define PDCA_PRDATA1_DATA(value) (PDCA_PRDATA1_DATA_Msk & ((value) << PDCA_PRDATA1_DATA_Pos)) 474 #define PDCA_PRDATA1_MASK _U_(0xFFFFFFFF) /**< \brief (PDCA_PRDATA1) MASK Register */ 475 476 /* -------- PDCA_PRSTALL1 : (PDCA Offset: 0x820) (R/ 32) Channel Read Stall Cycles -------- */ 477 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 478 typedef union { 479 struct { 480 uint32_t STALL:32; /*!< bit: 0..31 Stall Cycles Counted since last reset */ 481 } bit; /*!< Structure used for bit access */ 482 uint32_t reg; /*!< Type used for register access */ 483 } PDCA_PRSTALL1_Type; 484 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 485 486 #define PDCA_PRSTALL1_OFFSET 0x820 /**< \brief (PDCA_PRSTALL1 offset) Channel Read Stall Cycles */ 487 #define PDCA_PRSTALL1_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PRSTALL1 reset_value) Channel Read Stall Cycles */ 488 489 #define PDCA_PRSTALL1_STALL_Pos 0 /**< \brief (PDCA_PRSTALL1) Stall Cycles Counted since last reset */ 490 #define PDCA_PRSTALL1_STALL_Msk (_U_(0xFFFFFFFF) << PDCA_PRSTALL1_STALL_Pos) 491 #define PDCA_PRSTALL1_STALL(value) (PDCA_PRSTALL1_STALL_Msk & ((value) << PDCA_PRSTALL1_STALL_Pos)) 492 #define PDCA_PRSTALL1_MASK _U_(0xFFFFFFFF) /**< \brief (PDCA_PRSTALL1) MASK Register */ 493 494 /* -------- PDCA_PRLAT1 : (PDCA Offset: 0x824) (R/ 32) Channel 1 Read Max Latency -------- */ 495 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 496 typedef union { 497 struct { 498 uint32_t LAT:16; /*!< bit: 0..15 Maximum Transfer initiation cycles counted since last reset */ 499 uint32_t :16; /*!< bit: 16..31 Reserved */ 500 } bit; /*!< Structure used for bit access */ 501 uint32_t reg; /*!< Type used for register access */ 502 } PDCA_PRLAT1_Type; 503 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 504 505 #define PDCA_PRLAT1_OFFSET 0x824 /**< \brief (PDCA_PRLAT1 offset) Channel 1 Read Max Latency */ 506 #define PDCA_PRLAT1_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PRLAT1 reset_value) Channel 1 Read Max Latency */ 507 508 #define PDCA_PRLAT1_LAT_Pos 0 /**< \brief (PDCA_PRLAT1) Maximum Transfer initiation cycles counted since last reset */ 509 #define PDCA_PRLAT1_LAT_Msk (_U_(0xFFFF) << PDCA_PRLAT1_LAT_Pos) 510 #define PDCA_PRLAT1_LAT(value) (PDCA_PRLAT1_LAT_Msk & ((value) << PDCA_PRLAT1_LAT_Pos)) 511 #define PDCA_PRLAT1_MASK _U_(0x0000FFFF) /**< \brief (PDCA_PRLAT1) MASK Register */ 512 513 /* -------- PDCA_PWDATA1 : (PDCA Offset: 0x828) (R/ 32) Channel 1 Write Data Cycles -------- */ 514 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 515 typedef union { 516 struct { 517 uint32_t DATA:32; /*!< bit: 0..31 Data cycles Counted Since last reset */ 518 } bit; /*!< Structure used for bit access */ 519 uint32_t reg; /*!< Type used for register access */ 520 } PDCA_PWDATA1_Type; 521 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 522 523 #define PDCA_PWDATA1_OFFSET 0x828 /**< \brief (PDCA_PWDATA1 offset) Channel 1 Write Data Cycles */ 524 #define PDCA_PWDATA1_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PWDATA1 reset_value) Channel 1 Write Data Cycles */ 525 526 #define PDCA_PWDATA1_DATA_Pos 0 /**< \brief (PDCA_PWDATA1) Data cycles Counted Since last reset */ 527 #define PDCA_PWDATA1_DATA_Msk (_U_(0xFFFFFFFF) << PDCA_PWDATA1_DATA_Pos) 528 #define PDCA_PWDATA1_DATA(value) (PDCA_PWDATA1_DATA_Msk & ((value) << PDCA_PWDATA1_DATA_Pos)) 529 #define PDCA_PWDATA1_MASK _U_(0xFFFFFFFF) /**< \brief (PDCA_PWDATA1) MASK Register */ 530 531 /* -------- PDCA_PWSTALL1 : (PDCA Offset: 0x82C) (R/ 32) Channel 1 Write stall Cycles -------- */ 532 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 533 typedef union { 534 struct { 535 uint32_t STALL:32; /*!< bit: 0..31 Stall cycles counted since last reset */ 536 } bit; /*!< Structure used for bit access */ 537 uint32_t reg; /*!< Type used for register access */ 538 } PDCA_PWSTALL1_Type; 539 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 540 541 #define PDCA_PWSTALL1_OFFSET 0x82C /**< \brief (PDCA_PWSTALL1 offset) Channel 1 Write stall Cycles */ 542 #define PDCA_PWSTALL1_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PWSTALL1 reset_value) Channel 1 Write stall Cycles */ 543 544 #define PDCA_PWSTALL1_STALL_Pos 0 /**< \brief (PDCA_PWSTALL1) Stall cycles counted since last reset */ 545 #define PDCA_PWSTALL1_STALL_Msk (_U_(0xFFFFFFFF) << PDCA_PWSTALL1_STALL_Pos) 546 #define PDCA_PWSTALL1_STALL(value) (PDCA_PWSTALL1_STALL_Msk & ((value) << PDCA_PWSTALL1_STALL_Pos)) 547 #define PDCA_PWSTALL1_MASK _U_(0xFFFFFFFF) /**< \brief (PDCA_PWSTALL1) MASK Register */ 548 549 /* -------- PDCA_PWLAT1 : (PDCA Offset: 0x830) (R/ 32) Channel 1 Read Max Latency -------- */ 550 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 551 typedef union { 552 struct { 553 uint32_t LAT:16; /*!< bit: 0..15 Maximum transfer initiation cycles counted since last reset */ 554 uint32_t :16; /*!< bit: 16..31 Reserved */ 555 } bit; /*!< Structure used for bit access */ 556 uint32_t reg; /*!< Type used for register access */ 557 } PDCA_PWLAT1_Type; 558 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 559 560 #define PDCA_PWLAT1_OFFSET 0x830 /**< \brief (PDCA_PWLAT1 offset) Channel 1 Read Max Latency */ 561 #define PDCA_PWLAT1_RESETVALUE _U_(0x00000000); /**< \brief (PDCA_PWLAT1 reset_value) Channel 1 Read Max Latency */ 562 563 #define PDCA_PWLAT1_LAT_Pos 0 /**< \brief (PDCA_PWLAT1) Maximum transfer initiation cycles counted since last reset */ 564 #define PDCA_PWLAT1_LAT_Msk (_U_(0xFFFF) << PDCA_PWLAT1_LAT_Pos) 565 #define PDCA_PWLAT1_LAT(value) (PDCA_PWLAT1_LAT_Msk & ((value) << PDCA_PWLAT1_LAT_Pos)) 566 #define PDCA_PWLAT1_MASK _U_(0x0000FFFF) /**< \brief (PDCA_PWLAT1) MASK Register */ 567 568 /* -------- PDCA_VERSION : (PDCA Offset: 0x834) (R/ 32) Version Register -------- */ 569 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 570 typedef union { 571 struct { 572 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 573 uint32_t :4; /*!< bit: 12..15 Reserved */ 574 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 575 uint32_t :12; /*!< bit: 20..31 Reserved */ 576 } bit; /*!< Structure used for bit access */ 577 uint32_t reg; /*!< Type used for register access */ 578 } PDCA_VERSION_Type; 579 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 580 581 #define PDCA_VERSION_OFFSET 0x834 /**< \brief (PDCA_VERSION offset) Version Register */ 582 #define PDCA_VERSION_RESETVALUE _U_(0x00000124); /**< \brief (PDCA_VERSION reset_value) Version Register */ 583 584 #define PDCA_VERSION_VERSION_Pos 0 /**< \brief (PDCA_VERSION) Version Number */ 585 #define PDCA_VERSION_VERSION_Msk (_U_(0xFFF) << PDCA_VERSION_VERSION_Pos) 586 #define PDCA_VERSION_VERSION(value) (PDCA_VERSION_VERSION_Msk & ((value) << PDCA_VERSION_VERSION_Pos)) 587 #define PDCA_VERSION_VARIANT_Pos 16 /**< \brief (PDCA_VERSION) Variant Number */ 588 #define PDCA_VERSION_VARIANT_Msk (_U_(0xF) << PDCA_VERSION_VARIANT_Pos) 589 #define PDCA_VERSION_VARIANT(value) (PDCA_VERSION_VARIANT_Msk & ((value) << PDCA_VERSION_VARIANT_Pos)) 590 #define PDCA_VERSION_MASK _U_(0x000F0FFF) /**< \brief (PDCA_VERSION) MASK Register */ 591 592 /** \brief PdcaChannel hardware registers */ 593 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 594 typedef union { 595 struct { 596 __IO PDCA_MAR_Type MAR; /**< \brief Offset: 0x000 (R/W 32) Memory Address Register */ 597 __IO PDCA_PSR_Type PSR; /**< \brief Offset: 0x004 (R/W 32) Peripheral Select Register */ 598 __IO PDCA_TCR_Type TCR; /**< \brief Offset: 0x008 (R/W 32) Transfer Counter Register */ 599 __IO PDCA_MARR_Type MARR; /**< \brief Offset: 0x00C (R/W 32) Memory Address Reload Register */ 600 __IO PDCA_TCRR_Type TCRR; /**< \brief Offset: 0x010 (R/W 32) Transfer Counter Reload Register */ 601 __O PDCA_CR_Type CR; /**< \brief Offset: 0x014 ( /W 32) Control Register */ 602 __IO PDCA_MR_Type MR; /**< \brief Offset: 0x018 (R/W 32) Mode Register */ 603 __I PDCA_SR_Type SR; /**< \brief Offset: 0x01C (R/ 32) Status Register */ 604 __O PDCA_IER_Type IER; /**< \brief Offset: 0x020 ( /W 32) Interrupt Enable Register */ 605 __O PDCA_IDR_Type IDR; /**< \brief Offset: 0x024 ( /W 32) Interrupt Disable Register */ 606 __I PDCA_IMR_Type IMR; /**< \brief Offset: 0x028 (R/ 32) Interrupt Mask Register */ 607 __I PDCA_ISR_Type ISR; /**< \brief Offset: 0x02C (R/ 32) Interrupt Status Register */ 608 RoReg8 Reserved1[0x10]; 609 } bf; 610 struct { 611 RwReg PDCA_MAR; /**< \brief (PDCA Offset: 0x000) Memory Address Register */ 612 RwReg PDCA_PSR; /**< \brief (PDCA Offset: 0x004) Peripheral Select Register */ 613 RwReg PDCA_TCR; /**< \brief (PDCA Offset: 0x008) Transfer Counter Register */ 614 RwReg PDCA_MARR; /**< \brief (PDCA Offset: 0x00C) Memory Address Reload Register */ 615 RwReg PDCA_TCRR; /**< \brief (PDCA Offset: 0x010) Transfer Counter Reload Register */ 616 WoReg PDCA_CR; /**< \brief (PDCA Offset: 0x014) Control Register */ 617 RwReg PDCA_MR; /**< \brief (PDCA Offset: 0x018) Mode Register */ 618 RoReg PDCA_SR; /**< \brief (PDCA Offset: 0x01C) Status Register */ 619 WoReg PDCA_IER; /**< \brief (PDCA Offset: 0x020) Interrupt Enable Register */ 620 WoReg PDCA_IDR; /**< \brief (PDCA Offset: 0x024) Interrupt Disable Register */ 621 RoReg PDCA_IMR; /**< \brief (PDCA Offset: 0x028) Interrupt Mask Register */ 622 RoReg PDCA_ISR; /**< \brief (PDCA Offset: 0x02C) Interrupt Status Register */ 623 RoReg8 Reserved2[0x10]; 624 } reg; 625 } PdcaChannel; 626 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 627 628 /** \brief PDCA hardware registers */ 629 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 630 typedef struct { 631 __IO uint32_t Channel[16]; /**< \brief Offset: 0x000 PdcaChannel groups [CHANNEL_LENGTH] */ 632 RoReg8 Reserved1[0x400]; 633 __IO uint32_t PCONTROL; /**< \brief Offset: 0x800 (R/W 32) Performance Control Register */ 634 __I uint32_t PRDATA0; /**< \brief Offset: 0x804 (R/ 32) Channel 0 Read Data Cycles */ 635 __I uint32_t PRSTALL0; /**< \brief Offset: 0x808 (R/ 32) Channel 0 Read Stall Cycles */ 636 __I uint32_t PRLAT0; /**< \brief Offset: 0x80C (R/ 32) Channel 0 Read Max Latency */ 637 __I uint32_t PWDATA0; /**< \brief Offset: 0x810 (R/ 32) Channel 0 Write Data Cycles */ 638 __I uint32_t PWSTALL0; /**< \brief Offset: 0x814 (R/ 32) Channel 0 Write Stall Cycles */ 639 __I uint32_t PWLAT0; /**< \brief Offset: 0x818 (R/ 32) Channel0 Write Max Latency */ 640 __I uint32_t PRDATA1; /**< \brief Offset: 0x81C (R/ 32) Channel 1 Read Data Cycles */ 641 __I uint32_t PRSTALL1; /**< \brief Offset: 0x820 (R/ 32) Channel Read Stall Cycles */ 642 __I uint32_t PRLAT1; /**< \brief Offset: 0x824 (R/ 32) Channel 1 Read Max Latency */ 643 __I uint32_t PWDATA1; /**< \brief Offset: 0x828 (R/ 32) Channel 1 Write Data Cycles */ 644 __I uint32_t PWSTALL1; /**< \brief Offset: 0x82C (R/ 32) Channel 1 Write stall Cycles */ 645 __I uint32_t PWLAT1; /**< \brief Offset: 0x830 (R/ 32) Channel 1 Read Max Latency */ 646 __I uint32_t VERSION; /**< \brief Offset: 0x834 (R/ 32) Version Register */ 647 } Pdca; 648 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 649 650 /*@}*/ 651 652 #endif /* _SAM4L_PDCA_COMPONENT_ */ 653
