1 /*
2  * Copyright (c) 2024, Ambiq Micro, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  *
31  * @file     apollo3p.h
32  * @brief    CMSIS HeaderFile
33  * @version  1.0
34  * @date     20. May 2024
35  * @note     Generated by SVDConv V3.3.42 on Monday, 20.05.2024 14:15:54
36  *           from File './apollo3p.svd',
37  *           last modified on Monday, 20.05.2024 19:15:54
38  */
39 
40 
41 
42 /** @addtogroup Ambiq Micro
43   * @{
44   */
45 
46 
47 /** @addtogroup apollo3p
48   * @{
49   */
50 
51 
52 #ifndef APOLLO3P_H
53 #define APOLLO3P_H
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 
60 /** @addtogroup Configuration_of_CMSIS
61   * @{
62   */
63 
64 
65 
66 /* =========================================================================================================================== */
67 /* ================                                Interrupt Number Definition                                ================ */
68 /* =========================================================================================================================== */
69 
70 typedef enum {
71 /* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
72   Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
73   NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
74   HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
75   MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
76                                                      and No Match                                                              */
77   BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
78                                                      related Fault                                                             */
79   UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
80   SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
81   DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
82   PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
83   SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
84 /* ==========================================  apollo3p Specific Interrupt Numbers  ========================================== */
85   BROWNOUT_IRQn             =   0,              /*!< 0  BROWNOUT_IRQ                                                           */
86   WDT_IRQn                  =   1,              /*!< 1  WDT_IRQ                                                                */
87   RTC_IRQn                  =   2,              /*!< 2  RTC_IRQ                                                                */
88   VCOMP_IRQn                =   3,              /*!< 3  VCOMP_IRQ                                                              */
89   IOSLAVE_IRQn              =   4,              /*!< 4  IOSLAVE_IRQ                                                            */
90   IOSLAVEACC_IRQn           =   5,              /*!< 5  IOSLAVEACC_IRQ                                                         */
91   IOMSTR0_IRQn              =   6,              /*!< 6  IOMSTR0_IRQ                                                            */
92   IOMSTR1_IRQn              =   7,              /*!< 7  IOMSTR1_IRQ                                                            */
93   IOMSTR2_IRQn              =   8,              /*!< 8  IOMSTR2_IRQ                                                            */
94   IOMSTR3_IRQn              =   9,              /*!< 9  IOMSTR3_IRQ                                                            */
95   IOMSTR4_IRQn              =  10,              /*!< 10 IOMSTR4_IRQ                                                            */
96   IOMSTR5_IRQn              =  11,              /*!< 11 IOMSTR5_IRQ                                                            */
97   BLE_IRQn                  =  12,              /*!< 12 BLE_IRQ                                                                */
98   GPIO_IRQn                 =  13,              /*!< 13 GPIO_IRQ                                                               */
99   CTIMER_IRQn               =  14,              /*!< 14 CTIMER_IRQ                                                             */
100   UART0_IRQn                =  15,              /*!< 15 UART0_IRQ                                                              */
101   UART1_IRQn                =  16,              /*!< 16 UART1_IRQ                                                              */
102   SCARD_IRQn                =  17,              /*!< 17 SCARD_IRQ                                                              */
103   ADC_IRQn                  =  18,              /*!< 18 ADC_IRQ                                                                */
104   PDM_IRQn                  =  19,              /*!< 19 PDM_IRQ                                                                */
105   MSPI0_IRQn                =  20,              /*!< 20 MSPI0_IRQ                                                              */
106   STIMER_IRQn               =  22,              /*!< 22 STIMER_IRQ                                                             */
107   STIMER_CMPR0_IRQn         =  23,              /*!< 23 STIMER_CMPR0_IRQ                                                       */
108   STIMER_CMPR1_IRQn         =  24,              /*!< 24 STIMER_CMPR1_IRQ                                                       */
109   STIMER_CMPR2_IRQn         =  25,              /*!< 25 STIMER_CMPR2_IRQ                                                       */
110   STIMER_CMPR3_IRQn         =  26,              /*!< 26 STIMER_CMPR3_IRQ                                                       */
111   STIMER_CMPR4_IRQn         =  27,              /*!< 27 STIMER_CMPR4_IRQ                                                       */
112   STIMER_CMPR5_IRQn         =  28,              /*!< 28 STIMER_CMPR5_IRQ                                                       */
113   STIMER_CMPR6_IRQn         =  29,              /*!< 29 STIMER_CMPR6_IRQ                                                       */
114   STIMER_CMPR7_IRQn         =  30,              /*!< 30 STIMER_CMPR7_IRQ                                                       */
115   CLKGEN_IRQn               =  31,              /*!< 31 CLKGEN_IRQ                                                             */
116   MSPI1_IRQn                =  32,              /*!< 32 MSPI1_IRQ                                                              */
117   MSPI2_IRQn                =  33,              /*!< 33 MSPI2_IRQ                                                              */
118   MAX_IRQn                  =  34               /*!< 34 Not a valid IRQ. The maximum IRQ is this value - 1.                    */
119 } IRQn_Type;
120 
121 
122 
123 /* =========================================================================================================================== */
124 /* ================                           Processor and Core Peripheral Section                           ================ */
125 /* =========================================================================================================================== */
126 
127 /* ===========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  =========================== */
128 #define __CM4_REV                 0x0100U       /*!< CM4 Core Revision                                                         */
129 #define __NVIC_PRIO_BITS               3        /*!< Number of Bits used for Priority Levels                                   */
130 #define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
131 #define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
132 #define __MPU_PRESENT                  1        /*!< MPU present                                                               */
133 #define __FPU_PRESENT                  1        /*!< FPU present                                                               */
134 #define __FPU_DP                       0        /*!< Double Precision FPU                                                      */
135 #define __DSP_PRESENT                  0        /*!< DSP extension present                                                     */
136 #define __ICACHE_PRESENT               0        /*!< Instruction Cache present                                                 */
137 #define __DCACHE_PRESENT               0        /*!< Data Cache present                                                        */
138 #define __ITCM_PRESENT                 1        /*!< Instruction TCM present                                                   */
139 #define __DTCM_PRESENT                 1        /*!< Data TCM present                                                          */
140 #define __SAUREGION_PRESENT            0        /*!< SAU region present                                                        */
141 #define __PMU_PRESENT                  0        /*!< PMU present                                                               */
142 #define __PMU_NUM_EVENTCNT             0        /*!< PMU Event Counters                                                        */
143 
144 
145 /** @} */ /* End of group Configuration_of_CMSIS */
146 
147 #include "core_cm4.h"                           /*!< ARM Cortex-M4 processor and core peripherals                              */
148 #include "system_apollo3p.h"                    /*!< apollo3p System                                                           */
149 
150 #ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
151   #define __IM   __I
152 #endif
153 #ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
154   #define __OM   __O
155 #endif
156 #ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
157   #define __IOM  __IO
158 #endif
159 
160 
161 /* ========================================  Start of section using anonymous unions  ======================================== */
162 #if defined (__CC_ARM)
163   #pragma push
164   #pragma anon_unions
165 #elif defined (__ICCARM__)
166   #pragma language=extended
167 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
168   #pragma clang diagnostic push
169   #pragma clang diagnostic ignored "-Wc11-extensions"
170   #pragma clang diagnostic ignored "-Wreserved-id-macro"
171   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
172   #pragma clang diagnostic ignored "-Wnested-anon-types"
173 #elif defined (__GNUC__)
174   /* anonymous unions are enabled by default */
175 #elif defined (__TMS470__)
176   /* anonymous unions are enabled by default */
177 #elif defined (__TASKING__)
178   #pragma warning 586
179 #elif defined (__CSMC__)
180   /* anonymous unions are enabled by default */
181 #else
182   #warning Not supported compiler type
183 #endif
184 
185 
186 /* =========================================================================================================================== */
187 /* ================                            Device Specific Peripheral Section                             ================ */
188 /* =========================================================================================================================== */
189 
190 
191 /** @addtogroup Device_Peripheral_peripherals
192   * @{
193   */
194 
195 
196 
197 /* =========================================================================================================================== */
198 /* ================                                            ADC                                            ================ */
199 /* =========================================================================================================================== */
200 
201 
202 /**
203   * @brief Analog Digital Converter Control (ADC)
204   */
205 
206 typedef struct {                                /*!< (@ 0x50010000) ADC Structure                                              */
207 
208   union {
209     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The ADC Configuration Register contains the software
210                                                                     control for selecting the clock frequency
211                                                                     used for the SAR conversions, the trigger
212                                                                     polarity, the trigger select, the reference
213                                                                     voltage select, the low power mode, the
214                                                                     operating mode (single scan per trigger
215                                                                     vs. repeating mode) and ADC enable.                        */
216 
217     struct {
218       __IOM uint32_t ADCEN      : 1;            /*!< [0..0] This bit enables the ADC module. While the ADC is enabled,
219                                                      the ADCCFG and SLOT Configuration register settings must
220                                                      remain stable and unchanged. All configuration register
221                                                      settings, slot configuration settings and window comparison
222                                                      settings should be written prior to setting the ADCEN bit
223                                                      to '1'.                                                                   */
224             uint32_t            : 1;
225       __IOM uint32_t RPTEN      : 1;            /*!< [2..2] This bit enables Repeating Scan Mode.                              */
226       __IOM uint32_t LPMODE     : 1;            /*!< [3..3] Select power mode to enter between active scans.                   */
227       __IOM uint32_t CKMODE     : 1;            /*!< [4..4] Clock mode register                                                */
228             uint32_t            : 3;
229       __IOM uint32_t REFSEL     : 2;            /*!< [9..8] Select the ADC reference voltage.                                  */
230             uint32_t            : 2;
231       __IOM uint32_t DFIFORDEN  : 1;            /*!< [12..12] Destructive FIFO Read Enable. Setting this will enable
232                                                      FIFO pop upon reading the FIFOPR register.                                */
233             uint32_t            : 3;
234       __IOM uint32_t TRIGSEL    : 3;            /*!< [18..16] Select the ADC trigger source.                                   */
235       __IOM uint32_t TRIGPOL    : 1;            /*!< [19..19] This bit selects the ADC trigger polarity for external
236                                                      off chip triggers.                                                        */
237             uint32_t            : 4;
238       __IOM uint32_t CLKSEL     : 2;            /*!< [25..24] Select the source and frequency for the ADC clock.
239                                                      All values not enumerated below are undefined.                            */
240             uint32_t            : 6;
241     } CFG_b;
242   } ;
243 
244   union {
245     __IOM uint32_t STAT;                        /*!< (@ 0x00000004) This register indicates the basic power status
246                                                                     for the ADC. For detailed power status,
247                                                                     see the power control power status register.
248                                                                     ADC power mode 0 indicates the ADC is in
249                                                                     it's full power state and is ready to process
250                                                                     scans. ADC Power mode 1 indicates the ADC
251                                                                     enabled and in a low power state.                          */
252 
253     struct {
254       __IOM uint32_t PWDSTAT    : 1;            /*!< [0..0] Indicates the power-status of the ADC.                             */
255             uint32_t            : 31;
256     } STAT_b;
257   } ;
258 
259   union {
260     __IOM uint32_t SWT;                         /*!< (@ 0x00000008) This register enables initiating an ADC scan
261                                                                     through software.                                          */
262 
263     struct {
264       __IOM uint32_t SWT        : 8;            /*!< [7..0] Writing 0x37 to this register generates a software trigger.        */
265             uint32_t            : 24;
266     } SWT_b;
267   } ;
268 
269   union {
270     __IOM uint32_t SL0CFG;                      /*!< (@ 0x0000000C) Slot 0 Configuration Register                              */
271 
272     struct {
273       __IOM uint32_t SLEN0      : 1;            /*!< [0..0] This bit enables slot 0 for ADC conversions.                       */
274       __IOM uint32_t WCEN0      : 1;            /*!< [1..1] This bit enables the window compare function for slot
275                                                      0.                                                                        */
276             uint32_t            : 6;
277       __IOM uint32_t CHSEL0     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
278             uint32_t            : 4;
279       __IOM uint32_t PRMODE0    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
280             uint32_t            : 6;
281       __IOM uint32_t ADSEL0     : 3;            /*!< [26..24] Select the number of measurements to average in the
282                                                      accumulate divide module for this slot.                                   */
283             uint32_t            : 5;
284     } SL0CFG_b;
285   } ;
286 
287   union {
288     __IOM uint32_t SL1CFG;                      /*!< (@ 0x00000010) Slot 1 Configuration Register                              */
289 
290     struct {
291       __IOM uint32_t SLEN1      : 1;            /*!< [0..0] This bit enables slot 1 for ADC conversions.                       */
292       __IOM uint32_t WCEN1      : 1;            /*!< [1..1] This bit enables the window compare function for slot
293                                                      1.                                                                        */
294             uint32_t            : 6;
295       __IOM uint32_t CHSEL1     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
296             uint32_t            : 4;
297       __IOM uint32_t PRMODE1    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
298             uint32_t            : 6;
299       __IOM uint32_t ADSEL1     : 3;            /*!< [26..24] Select the number of measurements to average in the
300                                                      accumulate divide module for this slot.                                   */
301             uint32_t            : 5;
302     } SL1CFG_b;
303   } ;
304 
305   union {
306     __IOM uint32_t SL2CFG;                      /*!< (@ 0x00000014) Slot 2 Configuration Register                              */
307 
308     struct {
309       __IOM uint32_t SLEN2      : 1;            /*!< [0..0] This bit enables slot 2 for ADC conversions.                       */
310       __IOM uint32_t WCEN2      : 1;            /*!< [1..1] This bit enables the window compare function for slot
311                                                      2.                                                                        */
312             uint32_t            : 6;
313       __IOM uint32_t CHSEL2     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
314             uint32_t            : 4;
315       __IOM uint32_t PRMODE2    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
316             uint32_t            : 6;
317       __IOM uint32_t ADSEL2     : 3;            /*!< [26..24] Select the number of measurements to average in the
318                                                      accumulate divide module for this slot.                                   */
319             uint32_t            : 5;
320     } SL2CFG_b;
321   } ;
322 
323   union {
324     __IOM uint32_t SL3CFG;                      /*!< (@ 0x00000018) Slot 3 Configuration Register                              */
325 
326     struct {
327       __IOM uint32_t SLEN3      : 1;            /*!< [0..0] This bit enables slot 3 for ADC conversions.                       */
328       __IOM uint32_t WCEN3      : 1;            /*!< [1..1] This bit enables the window compare function for slot
329                                                      3.                                                                        */
330             uint32_t            : 6;
331       __IOM uint32_t CHSEL3     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
332             uint32_t            : 4;
333       __IOM uint32_t PRMODE3    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
334             uint32_t            : 6;
335       __IOM uint32_t ADSEL3     : 3;            /*!< [26..24] Select the number of measurements to average in the
336                                                      accumulate divide module for this slot.                                   */
337             uint32_t            : 5;
338     } SL3CFG_b;
339   } ;
340 
341   union {
342     __IOM uint32_t SL4CFG;                      /*!< (@ 0x0000001C) Slot 4 Configuration Register                              */
343 
344     struct {
345       __IOM uint32_t SLEN4      : 1;            /*!< [0..0] This bit enables slot 4 for ADC conversions.                       */
346       __IOM uint32_t WCEN4      : 1;            /*!< [1..1] This bit enables the window compare function for slot
347                                                      4.                                                                        */
348             uint32_t            : 6;
349       __IOM uint32_t CHSEL4     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
350             uint32_t            : 4;
351       __IOM uint32_t PRMODE4    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
352             uint32_t            : 6;
353       __IOM uint32_t ADSEL4     : 3;            /*!< [26..24] Select the number of measurements to average in the
354                                                      accumulate divide module for this slot.                                   */
355             uint32_t            : 5;
356     } SL4CFG_b;
357   } ;
358 
359   union {
360     __IOM uint32_t SL5CFG;                      /*!< (@ 0x00000020) Slot 5 Configuration Register                              */
361 
362     struct {
363       __IOM uint32_t SLEN5      : 1;            /*!< [0..0] This bit enables slot 5 for ADC conversions.                       */
364       __IOM uint32_t WCEN5      : 1;            /*!< [1..1] This bit enables the window compare function for slot
365                                                      5.                                                                        */
366             uint32_t            : 6;
367       __IOM uint32_t CHSEL5     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
368             uint32_t            : 4;
369       __IOM uint32_t PRMODE5    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
370             uint32_t            : 6;
371       __IOM uint32_t ADSEL5     : 3;            /*!< [26..24] Select number of measurements to average in the accumulate
372                                                      divide module for this slot.                                              */
373             uint32_t            : 5;
374     } SL5CFG_b;
375   } ;
376 
377   union {
378     __IOM uint32_t SL6CFG;                      /*!< (@ 0x00000024) Slot 6 Configuration Register                              */
379 
380     struct {
381       __IOM uint32_t SLEN6      : 1;            /*!< [0..0] This bit enables slot 6 for ADC conversions.                       */
382       __IOM uint32_t WCEN6      : 1;            /*!< [1..1] This bit enables the window compare function for slot
383                                                      6.                                                                        */
384             uint32_t            : 6;
385       __IOM uint32_t CHSEL6     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
386             uint32_t            : 4;
387       __IOM uint32_t PRMODE6    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
388             uint32_t            : 6;
389       __IOM uint32_t ADSEL6     : 3;            /*!< [26..24] Select the number of measurements to average in the
390                                                      accumulate divide module for this slot.                                   */
391             uint32_t            : 5;
392     } SL6CFG_b;
393   } ;
394 
395   union {
396     __IOM uint32_t SL7CFG;                      /*!< (@ 0x00000028) Slot 7 Configuration Register                              */
397 
398     struct {
399       __IOM uint32_t SLEN7      : 1;            /*!< [0..0] This bit enables slot 7 for ADC conversions.                       */
400       __IOM uint32_t WCEN7      : 1;            /*!< [1..1] This bit enables the window compare function for slot
401                                                      7.                                                                        */
402             uint32_t            : 6;
403       __IOM uint32_t CHSEL7     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
404             uint32_t            : 4;
405       __IOM uint32_t PRMODE7    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
406             uint32_t            : 6;
407       __IOM uint32_t ADSEL7     : 3;            /*!< [26..24] Select the number of measurements to average in the
408                                                      accumulate divide module for this slot.                                   */
409             uint32_t            : 5;
410     } SL7CFG_b;
411   } ;
412 
413   union {
414     __IOM uint32_t WULIM;                       /*!< (@ 0x0000002C) Window Comparator Upper Limits Register                    */
415 
416     struct {
417       __IOM uint32_t ULIM       : 20;           /*!< [19..0] Sets the upper limit for the window comparator.                   */
418             uint32_t            : 12;
419     } WULIM_b;
420   } ;
421 
422   union {
423     __IOM uint32_t WLLIM;                       /*!< (@ 0x00000030) Window Comparator Lower Limits Register                    */
424 
425     struct {
426       __IOM uint32_t LLIM       : 20;           /*!< [19..0] Sets the lower limit for the window comparator.                   */
427             uint32_t            : 12;
428     } WLLIM_b;
429   } ;
430 
431   union {
432     __IOM uint32_t SCWLIM;                      /*!< (@ 0x00000034) Scale Window Comparator Limits                             */
433 
434     struct {
435       __IOM uint32_t SCWLIMEN   : 1;            /*!< [0..0] Scale the window limits compare values per precision
436                                                      mode. When set to 0x0 (default), the values in the 20-bit
437                                                      limits registers will compare directly with the FIFO values
438                                                      regardless of the precision mode the slot is configured
439                                                      to. When set to 0x1, the compare values will be divided
440                                                      by the difference in precision bits while performing the
441                                                      window limit comparisons.                                                 */
442             uint32_t            : 31;
443     } SCWLIM_b;
444   } ;
445 
446   union {
447     __IOM uint32_t FIFO;                        /*!< (@ 0x00000038) The ADC FIFO Register contains the slot number
448                                                                     and FIFO data for the oldest conversion
449                                                                     data in the FIFO. The COUNT field indicates
450                                                                     the total number of valid entries in the
451                                                                     FIFO. A write to this register will pop
452                                                                     one of the FIFO entries off the FIFO and
453                                                                     decrease the COUNT by 1 if the COUNT is
454                                                                     greater than zero.                                         */
455 
456     struct {
457       __IOM uint32_t DATA       : 20;           /*!< [19..0] Oldest data in the FIFO.                                          */
458       __IOM uint32_t COUNT      : 8;            /*!< [27..20] Number of valid entries in the ADC FIFO.                         */
459       __IOM uint32_t SLOTNUM    : 3;            /*!< [30..28] Slot number associated with this FIFO data.                      */
460       __IOM uint32_t RSVD       : 1;            /*!< [31..31] RESERVED.                                                        */
461     } FIFO_b;
462   } ;
463 
464   union {
465     __IOM uint32_t FIFOPR;                      /*!< (@ 0x0000003C) This is a Pop Read mirrored copy of the ADCFIFO
466                                                                     register with the only difference being
467                                                                     that reading this register will result in
468                                                                     a simultaneous FIFO POP which is also achieved
469                                                                     by writing to the ADCFIFO Register. Note:
470                                                                     The DFIFORDEN bit must be set in the CFG
471                                                                     register for the the destructive read to
472                                                                     be enabled.                                                */
473 
474     struct {
475       __IOM uint32_t DATA       : 20;           /*!< [19..0] Oldest data in the FIFO.                                          */
476       __IOM uint32_t COUNT      : 8;            /*!< [27..20] Number of valid entries in the ADC FIFO.                         */
477       __IOM uint32_t SLOTNUMPR  : 3;            /*!< [30..28] Slot number associated with this FIFO data.                      */
478       __IOM uint32_t RSVDPR     : 1;            /*!< [31..31] RESERVED.                                                        */
479     } FIFOPR_b;
480   } ;
481   __IM  uint32_t  RESERVED[112];
482 
483   union {
484     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
485                                                                     to generate the corresponding interrupt.                   */
486 
487     struct {
488       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
489       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
490       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
491       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
492       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
493       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
494       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
495       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
496             uint32_t            : 24;
497     } INTEN_b;
498   } ;
499 
500   union {
501     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
502                                                                     cause of a recent interrupt.                               */
503 
504     struct {
505       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
506       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
507       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
508       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
509       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
510       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
511       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
512       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
513             uint32_t            : 24;
514     } INTSTAT_b;
515   } ;
516 
517   union {
518     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
519                                                                     the interrupt status associated with that
520                                                                     bit.                                                       */
521 
522     struct {
523       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
524       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
525       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
526       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
527       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
528       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
529       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
530       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
531             uint32_t            : 24;
532     } INTCLR_b;
533   } ;
534 
535   union {
536     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
537                                                                     generate an interrupt from this module.
538                                                                     (Generally used for testing purposes).                     */
539 
540     struct {
541       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
542       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
543       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
544       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
545       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
546       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
547       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
548       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
549             uint32_t            : 24;
550     } INTSET_b;
551   } ;
552   __IM  uint32_t  RESERVED1[12];
553 
554   union {
555     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000240) DMA Trigger Enable Register                                */
556 
557     struct {
558       __IOM uint32_t DFIFO75    : 1;            /*!< [0..0] Trigger DMA upon FIFO 75 percent Full                              */
559       __IOM uint32_t DFIFOFULL  : 1;            /*!< [1..1] Trigger DMA upon FIFO 100 percent Full                             */
560             uint32_t            : 30;
561     } DMATRIGEN_b;
562   } ;
563 
564   union {
565     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000244) DMA Trigger Status Register                                */
566 
567     struct {
568       __IOM uint32_t D75STAT    : 1;            /*!< [0..0] Triggered DMA from FIFO 75 percent Full                            */
569       __IOM uint32_t DFULLSTAT  : 1;            /*!< [1..1] Triggered DMA from FIFO 100 percent Full                           */
570             uint32_t            : 30;
571     } DMATRIGSTAT_b;
572   } ;
573   __IM  uint32_t  RESERVED2[14];
574 
575   union {
576     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000280) DMA Configuration Register                                 */
577 
578     struct {
579       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
580             uint32_t            : 1;
581       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
582             uint32_t            : 5;
583       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
584       __IOM uint32_t DMADYNPRI  : 1;            /*!< [9..9] Enables dynamic priority based on FIFO fullness. When
585                                                      FIFO is full, priority is automatically set to HIGH. Otherwise,
586                                                      DMAPRI is used.                                                           */
587             uint32_t            : 6;
588       __IOM uint32_t DMAHONSTAT : 1;            /*!< [16..16] Halt New ADC conversions until DMA Status DMAERR and
589                                                      DMACPL Cleared.                                                           */
590       __IOM uint32_t DMAMSK     : 1;            /*!< [17..17] Mask the FIFOCNT and SLOTNUM when transferring FIFO
591                                                      contents to memory                                                        */
592       __IOM uint32_t DPWROFF    : 1;            /*!< [18..18] Power Off the ADC System upon DMACPL.                            */
593             uint32_t            : 13;
594     } DMACFG_b;
595   } ;
596   __IM  uint32_t  RESERVED3;
597 
598   union {
599     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000288) DMA Total Transfer Count                                   */
600 
601     struct {
602             uint32_t            : 2;
603       __IOM uint32_t TOTCOUNT   : 16;           /*!< [17..2] Total Transfer Count                                              */
604             uint32_t            : 14;
605     } DMATOTCOUNT_b;
606   } ;
607 
608   union {
609     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x0000028C) DMA Target Address Register                                */
610 
611     struct {
612       __IOM uint32_t LTARGADDR  : 20;           /*!< [19..0] DMA Target Address                                                */
613       __IOM uint32_t UTARGADDR  : 12;           /*!< [31..20] SRAM Target                                                      */
614     } DMATARGADDR_b;
615   } ;
616 
617   union {
618     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000290) DMA Status Register                                        */
619 
620     struct {
621       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
622       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
623       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
624             uint32_t            : 29;
625     } DMASTAT_b;
626   } ;
627 } ADC_Type;                                     /*!< Size = 660 (0x294)                                                        */
628 
629 
630 
631 /* =========================================================================================================================== */
632 /* ================                                          APBDMA                                           ================ */
633 /* =========================================================================================================================== */
634 
635 
636 /**
637   * @brief APB DMA Register Interfaces (APBDMA)
638   */
639 
640 typedef struct {                                /*!< (@ 0x40011000) APBDMA Structure                                           */
641 
642   union {
643     __IOM uint32_t BBVALUE;                     /*!< (@ 0x00000000) Control Register                                           */
644 
645     struct {
646       __IOM uint32_t DATAOUT    : 8;            /*!< [7..0] Data Output Values                                                 */
647             uint32_t            : 8;
648       __IOM uint32_t PIN        : 8;            /*!< [23..16] PIO values                                                       */
649             uint32_t            : 8;
650     } BBVALUE_b;
651   } ;
652 
653   union {
654     __IOM uint32_t BBSETCLEAR;                  /*!< (@ 0x00000004) Set/Clear Register                                         */
655 
656     struct {
657       __IOM uint32_t SET        : 8;            /*!< [7..0] Write 1 to set PIO value (set higher priority then clear
658                                                      if both bits are set)                                                     */
659             uint32_t            : 8;
660       __IOM uint32_t CLEAR      : 8;            /*!< [23..16] Write 1 to clear PIO value                                       */
661             uint32_t            : 8;
662     } BBSETCLEAR_b;
663   } ;
664 
665   union {
666     __IOM uint32_t BBINPUT;                     /*!< (@ 0x00000008) PIO Input Values                                           */
667 
668     struct {
669       __IOM uint32_t DATAIN     : 8;            /*!< [7..0] PIO values                                                         */
670             uint32_t            : 24;
671     } BBINPUT_b;
672   } ;
673   __IM  uint32_t  RESERVED[5];
674 
675   union {
676     __IOM uint32_t DEBUGDATA;                   /*!< (@ 0x00000020) PIO Input Values                                           */
677 
678     struct {
679       __IOM uint32_t DEBUGDATA  : 32;           /*!< [31..0] Debug Data                                                        */
680     } DEBUGDATA_b;
681   } ;
682   __IM  uint32_t  RESERVED1[7];
683 
684   union {
685     __IOM uint32_t DEBUG;                       /*!< (@ 0x00000040) PIO Input Values                                           */
686 
687     struct {
688       __IOM uint32_t DEBUGEN    : 4;            /*!< [3..0] Debug Enable                                                       */
689             uint32_t            : 28;
690     } DEBUG_b;
691   } ;
692 } APBDMA_Type;                                  /*!< Size = 68 (0x44)                                                          */
693 
694 
695 
696 /* =========================================================================================================================== */
697 /* ================                                           BLEIF                                           ================ */
698 /* =========================================================================================================================== */
699 
700 
701 /**
702   * @brief BLE Interface (BLEIF)
703   */
704 
705 typedef struct {                                /*!< (@ 0x5000C000) BLEIF Structure                                            */
706 
707   union {
708     __IOM uint32_t FIFO;                        /*!< (@ 0x00000000) Provides direct random access to both input and
709                                                                     output FIFOs. The state of the FIFO is not
710                                                                     disturbed by reading these locations (i.e.,
711                                                                     no POP will occur). FIFO0 is accessible
712                                                                     from addresses 0x0 - 0x1C, and is used for
713                                                                     data output from the IOM to external devices.
714                                                                     These FIFO locations can be read and written
715                                                                     directly.FIFO locations 0x20 - 0x3C provide
716                                                                     read only access to the input FIFO. These
717                                                                     FIFO locations cannot be directly written
718                                                                     by the MCU, and are updated only by the
719                                                                     internal hardware                                          */
720 
721     struct {
722       __IOM uint32_t FIFO       : 32;           /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return
723                                                      valid information.                                                        */
724     } FIFO_b;
725   } ;
726   __IM  uint32_t  RESERVED[63];
727 
728   union {
729     __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Provides the current valid byte count of data
730                                                                     within the FIFO as seen from the internal
731                                                                     state machines. FIFO0 is dedicated to outgoing
732                                                                     transactions and FIFO1 is dedicated to incoming
733                                                                     transactions. All counts are specified in
734                                                                     units of bytes.                                            */
735 
736     struct {
737       __IOM uint32_t FIFO0SIZ   : 8;            /*!< [7..0] The number of valid data bytes currently in the FIFO
738                                                      0 (written by MCU, read by interface)                                     */
739       __IOM uint32_t FIFO0REM   : 8;            /*!< [15..8] The number of remaining data bytes slots currently in
740                                                      FIFO 0 (written by MCU, read by interface)                                */
741       __IOM uint32_t FIFO1SIZ   : 8;            /*!< [23..16] The number of valid data bytes currently in FIFO 1
742                                                      (written by interface, read by MCU)                                       */
743       __IOM uint32_t FIFO1REM   : 8;            /*!< [31..24] The number of remaining data bytes slots currently
744                                                      in FIFO 1 (written by interface, read by MCU)                             */
745     } FIFOPTR_b;
746   } ;
747 
748   union {
749     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000104) Sets the threshold values for incoming and outgoing
750                                                                     transactions. The threshold values are used
751                                                                     to assert the interrupt if enabled, and
752                                                                     also used during DMA to set the transfer
753                                                                     size as a result of DMATHR trigger.The WTHR
754                                                                     is used to indicate when there are more
755                                                                     than WTHR bytes of open FIFO locations available
756                                                                     in the outgoing FIFO (FIFO0). The intended
757                                                                     use to invoke an interrupt or DMA transfer
758                                                                     that will refill the FIFO with a byte count
759                                                                     up to this value.The RTHR is used to indicate
760                                                                     when t                                                     */
761 
762     struct {
763       __IOM uint32_t FIFORTHR   : 6;            /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable
764                                                      the read FIFO level from activating the threshold interrupt.
765                                                      If this field is non-zero, it will trigger a threshold
766                                                      interrupt when the read FIFO contains FIFORTHR valid bytes
767                                                      of data, as indicated by the FIFO1SIZ field. This is intended
768                                                      to signal when a data transfer of FIFORTHR bytes can be
769                                                      done from the IOM module to the host via the read FIFO
770                                                      to support large IOM read operations.                                     */
771             uint32_t            : 2;
772       __IOM uint32_t FIFOWTHR   : 6;            /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable
773                                                      the write FIFO level from activating the threshold interrupt.
774                                                      If this field is non-zero, it will trigger a threshold
775                                                      interrupt when the write FIFO contains FIFOWTHR free bytes,
776                                                      as indicated by the FIFO0REM field. This is intended to
777                                                      signal when a transfer of FIFOWTHR bytes can be done from
778                                                      the host to the IOM write FIFO to support large IOM write
779                                                      operations.                                                               */
780             uint32_t            : 18;
781     } FIFOTHR_b;
782   } ;
783 
784   union {
785     __IOM uint32_t FIFOPOP;                     /*!< (@ 0x00000108) Will advance the internal read pointer of the
786                                                                     incoming FIFO (FIFO1) when read, if POPWR
787                                                                     is not active. If POPWR is active, a write
788                                                                     to this register is needed to advance the
789                                                                     internal FIFO pointer.                                     */
790 
791     struct {
792       __IOM uint32_t FIFODOUT   : 32;           /*!< [31..0] This register will return the read data indicated by
793                                                      the current read pointer on reads. If the POPWR control
794                                                      bit in the FIFOCTRL register is reset (0), the FIFO read
795                                                      pointer will be advanced by one word as a result of the
796                                                      read.If the POPWR bit is set (1), the FIFO read pointer
797                                                      will only be advanced after a write operation to this register.
798                                                      The write data is ignored for this register.If less than
799                                                      a even word multiple is available, and the command is completed,
800                                                      the module will return the word containing                                */
801     } FIFOPOP_b;
802   } ;
803 
804   union {
805     __IOM uint32_t FIFOPUSH;                    /*!< (@ 0x0000010C) Will write new data into the outgoing FIFO and
806                                                                     advance the internal write pointer.                        */
807 
808     struct {
809       __IOM uint32_t FIFODIN    : 32;           /*!< [31..0] This register is used to write the FIFORAM in FIFO mode
810                                                      and will cause a push event to occur to the next open slot
811                                                      within the FIFORAM. Writing to this register will cause
812                                                      the write point to increment by 1 word(4 bytes).                          */
813     } FIFOPUSH_b;
814   } ;
815 
816   union {
817     __IOM uint32_t FIFOCTRL;                    /*!< (@ 0x00000110) Provides controls for the operation of the internal
818                                                                     FIFOs. Contains fields used to control the
819                                                                     operation of the POP register, and also
820                                                                     controls to reset the internal pointers
821                                                                     of the FIFOs.                                              */
822 
823     struct {
824       __IOM uint32_t POPWR      : 1;            /*!< [0..0] Selects the mode in which 'pop' events are done for the
825                                                      FIFO read operations. A value of '1' will prevent a pop
826                                                      event on a read operation, and will require a write to
827                                                      the FIFOPOP register to create a pop event.A value of '0'
828                                                      in this register will allow a pop event to occur on the
829                                                      read of the FIFOPOP register, and may cause inadvertent
830                                                      FIFO pops when used in a debugging mode.                                  */
831       __IOM uint32_t FIFORSTN   : 1;            /*!< [1..1] Active low manual reset of the FIFO. Write to 0 to reset
832                                                      FIFO, and then write to 1 to remove the reset.                            */
833             uint32_t            : 30;
834     } FIFOCTRL_b;
835   } ;
836 
837   union {
838     __IOM uint32_t FIFOLOC;                     /*!< (@ 0x00000114) Provides a read only value of the current read
839                                                                     and write pointers. This register is read
840                                                                     only and can be used along with the FIFO
841                                                                     direct access method to determine the next
842                                                                     data to be used for input and output functions.            */
843 
844     struct {
845       __IOM uint32_t FIFOWPTR   : 4;            /*!< [3..0] Current FIFO write pointer. Value is the index into the
846                                                      outgoing FIFO (FIFO0), which is used during write operations
847                                                      to external devices.                                                      */
848             uint32_t            : 4;
849       __IOM uint32_t FIFORPTR   : 4;            /*!< [11..8] Current FIFO read pointer. Used to index into the incoming
850                                                      FIFO (FIFO1), which is used to store read data returned
851                                                      from external devices during a read operation.                            */
852             uint32_t            : 20;
853     } FIFOLOC_b;
854   } ;
855   __IM  uint32_t  RESERVED1[58];
856 
857   union {
858     __IOM uint32_t CLKCFG;                      /*!< (@ 0x00000200) Provides clock related controls used internal
859                                                                     to the BLEIF module, and enablement of 32KHz
860                                                                     clock to the BLE Core module. The internal
861                                                                     clock sourced is selected via the FSEL and
862                                                                     can be further divided by 3 using the DIV3
863                                                                     control.This register is also used to enable
864                                                                     the clock, which must be done prior to performing
865                                                                     any IO transactions.                                       */
866 
867     struct {
868       __IOM uint32_t IOCLKEN    : 1;            /*!< [0..0] Enable for the interface clock. Must be enabled prior
869                                                      to executing any IO operations.                                           */
870             uint32_t            : 7;
871       __IOM uint32_t FSEL       : 3;            /*!< [10..8] Select the input clock frequency.                                 */
872       __IOM uint32_t CLK32KEN   : 1;            /*!< [11..11] Enable for the 32Khz clock to the BLE module                     */
873       __IOM uint32_t DIV3       : 1;            /*!< [12..12] Enable of the divide by 3 of the source IOCLK.                   */
874             uint32_t            : 19;
875     } CLKCFG_b;
876   } ;
877   __IM  uint32_t  RESERVED2[2];
878 
879   union {
880     __IOM uint32_t CMD;                         /*!< (@ 0x0000020C) Writes to this register will start an IO transaction,
881                                                                     as well as set various parameters for the
882                                                                     command itself. Reads will return the command
883                                                                     value written to the CMD register.To read
884                                                                     the number of bytes that have yet to be
885                                                                     transferred, refer to the CTSIZE field within
886                                                                     the CMDSTAT register.                                      */
887 
888     struct {
889       __IOM uint32_t CMD        : 5;            /*!< [4..0] Command for submodule.                                             */
890       __IOM uint32_t OFFSETCNT  : 2;            /*!< [6..5] Number of offset bytes to use for the command - 0, 1,
891                                                      2, 3 are valid selections. The second (byte 1) and third
892                                                      byte (byte 2) are read from the OFFSETHI register, and
893                                                      the low order byte is pulled from this register in the
894                                                      OFFSETLO field.Offset bytes are transmitted highest byte
895                                                      first. E.g., if OFFSETCNT == 3, OFFSETHI[15:8] will be
896                                                      transmitted first, then OFFSETHI[7:0] then OFFSETLO.If
897                                                      OFFSETCNT == 2, OFFSETHI[7:0] will be transmitted, then
898                                                      OFFSETLO.If OFFSETCNT == 1, only OFFSETLO will be transmitted             */
899       __IOM uint32_t CONT       : 1;            /*!< [7..7] Continue to hold the bus after the current transaction
900                                                      if set to a 1 with a new command issued.                                  */
901       __IOM uint32_t TSIZE      : 12;           /*!< [19..8] Defines the transaction size in bytes. The offset transfer
902                                                      is not included in this size.                                             */
903       __IOM uint32_t CMDSEL     : 2;            /*!< [21..20] Command Specific selection information                           */
904             uint32_t            : 2;
905       __IOM uint32_t OFFSETLO   : 8;            /*!< [31..24] This register holds the low order byte of offset to
906                                                      be used in the transaction. The number of offset bytes
907                                                      to use is set with bits 1:0 of the command. Offset bytes
908                                                      are transferred starting from the highest byte first.                     */
909     } CMD_b;
910   } ;
911 
912   union {
913     __IOM uint32_t CMDRPT;                      /*!< (@ 0x00000210) Will repeat the next command for CMDRPT number
914                                                                     of times. If CMDRPT is set to 1, the next
915                                                                     command will be done 2 times in series.
916                                                                     A repeat count of up to 31 is possible.
917                                                                     Each command will be done as a separate
918                                                                     command, but the data willbe treated as
919                                                                     packed, and aligned to byte boundaries.
920                                                                     This differs when executing separate commands
921                                                                     without the CMDRPT set, as the data for
922                                                                     each transaction is word aligned and any
923                                                                     unused byte locations will be filled with
924                                                                     0 for read operations, ordiscarded                         */
925 
926     struct {
927       __IOM uint32_t CMDRPT     : 5;            /*!< [4..0] Count of number of times to repeat the next command.               */
928             uint32_t            : 27;
929     } CMDRPT_b;
930   } ;
931 
932   union {
933     __IOM uint32_t OFFSETHI;                    /*!< (@ 0x00000214) Provides the high order bytes of 2 or 3 byte
934                                                                     offset transactions of the current command.
935                                                                     Usage of these bytes is dependent on the
936                                                                     OFFSETCNT field in the CMD register. If
937                                                                     the OFFSETCNT == 3, the data located at
938                                                                     OFFSETHI[15:0] will first be transmitted,followed
939                                                                     by OFFSETHI[7:0], followed by OFFSETLO (in
940                                                                     the CMD register) prior to sending or receiving
941                                                                     any transaction data (if programed via TSIZE
942                                                                     field in the CMD register).The offset bytes
943                                                                     are always transmitted MSB first for all
944                                                                     modules.                                                   */
945 
946     struct {
947       __IOM uint32_t OFFSETHI   : 16;           /*!< [15..0] Holds the high order bytes of the 2 or 3 byte offset
948                                                      phase of a transaction.                                                   */
949             uint32_t            : 16;
950     } OFFSETHI_b;
951   } ;
952 
953   union {
954     __IOM uint32_t CMDSTAT;                     /*!< (@ 0x00000218) Provides status on the execution of the command
955                                                                     currently in progress. The fields in this
956                                                                     register will reflect the real time status
957                                                                     of the internal state machines and data
958                                                                     transfers within the IOM.These are read
959                                                                     only fields and writes to the registers
960                                                                     are ignored.                                               */
961 
962     struct {
963       __IOM uint32_t CCMD       : 5;            /*!< [4..0] current command that is being executed                             */
964       __IOM uint32_t CMDSTAT    : 3;            /*!< [7..5] The current status of the command execution.                       */
965       __IOM uint32_t CTSIZE     : 12;           /*!< [19..8] The current number of bytes still to be transferred
966                                                      with this command. This field will count down to zero.                    */
967             uint32_t            : 12;
968     } CMDSTAT_b;
969   } ;
970   __IM  uint32_t  RESERVED3;
971 
972   union {
973     __IOM uint32_t INTEN;                       /*!< (@ 0x00000220) Set bits in this register to allow this module
974                                                                     to generate the corresponding interrupt.                   */
975 
976     struct {
977       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
978                                                      operation has completed. For repeated commands, this will
979                                                      only be asserted when the final repeated command is completed.            */
980       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
981                                                      when the number of free bytes in the write FIFO equals
982                                                      or exceeds the WTHR field.For read operations, asserted
983                                                      when the number of valid bytes in the read FIFO equals
984                                                      of exceeds the value set in the RTHR field.                               */
985       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
986                                                      is done to a empty read FIFO.                                             */
987       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
988                                                      tries to write to a full FIFO. The current operation does
989                                                      not stop.                                                                 */
990       __IOM uint32_t B2MST      : 1;            /*!< [4..4] B2M State change interrupt. Asserted on any change in
991                                                      the B2M_STATE signal from the BLE Core.                                   */
992       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
993                                                      a overflow or underflow event                                             */
994       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
995                                                      written when an active command is in progress.                            */
996       __IOM uint32_t BLECIRQ    : 1;            /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
997                                                      from the BLE Core is asserted, indicating the availability
998                                                      of read data from the BLE Core.                                           */
999       __IOM uint32_t BLECSSTAT  : 1;            /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
1000                                                      signal from the BLE Core is asserted, indicating that SPI
1001                                                      writes can be done to the BLE Core.Transfers to the BLE
1002                                                      Core should only be done when this signal is high.                        */
1003       __IOM uint32_t DCMP       : 1;            /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
1004                                                      and the DMA submodule is returned into the idle state                     */
1005       __IOM uint32_t DERR       : 1;            /*!< [10..10] DMA Error encountered during the processing of the
1006                                                      DMA command. The DMA error could occur when the memory
1007                                                      access specified in the DMA operation is not available
1008                                                      or incorrectly specified.                                                 */
1009       __IOM uint32_t CQPAUSED   : 1;            /*!< [11..11] Command queue is paused due to an active event enabled
1010                                                      in the PAUSEEN register. The interrupt is posted when the
1011                                                      event is enabled within the PAUSEEN register, the mask
1012                                                      is active in the CQIRQMASK field and the event occurs.                    */
1013       __IOM uint32_t CQUPD      : 1;            /*!< [12..12] Command queue write operation executed a register write
1014                                                      with the register address bit 0 set to 1. The low address
1015                                                      bits in the CQ address fields are unused and bit 0 can
1016                                                      be used to trigger an interrupt to indicate when this register
1017                                                      write is performed by the CQ operation.                                   */
1018       __IOM uint32_t CQERR      : 1;            /*!< [13..13] Command queue error during processing. When an error
1019                                                      occurs, the system will stop processing and halt operations
1020                                                      to allow software to take recovery actions                                */
1021       __IOM uint32_t B2MSLEEP   : 1;            /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
1022                                                      sleep state                                                               */
1023       __IOM uint32_t B2MACTIVE  : 1;            /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
1024                                                      into the active state Revision B: Falling BLE Core IRQ
1025                                                      signal. Asserted when the BLE_IRQ signal from the BLE Core
1026                                                      is deasserted (1 -> 0)                                                    */
1027       __IOM uint32_t B2MSHUTDN  : 1;            /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
1028                                                      into shutdown state Revision B: Falling BLE Core Status
1029                                                      signal. Asserted when the BLE_STATUS signal from the BLE
1030                                                      Core is deasserted (1 -> 0)                                               */
1031             uint32_t            : 15;
1032     } INTEN_b;
1033   } ;
1034 
1035   union {
1036     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000224) Read bits from this register to discover the
1037                                                                     cause of a recent interrupt.                               */
1038 
1039     struct {
1040       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
1041                                                      operation has completed. For repeated commands, this will
1042                                                      only be asserted when the final repeated command is completed.            */
1043       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
1044                                                      when the number of free bytes in the write FIFO equals
1045                                                      or exceeds the WTHR field.For read operations, asserted
1046                                                      when the number of valid bytes in the read FIFO equals
1047                                                      of exceeds the value set in the RTHR field.                               */
1048       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
1049                                                      is done to a empty read FIFO.                                             */
1050       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
1051                                                      tries to write to a full FIFO. The current operation does
1052                                                      not stop.                                                                 */
1053       __IOM uint32_t B2MST      : 1;            /*!< [4..4] B2M State change interrupt. Asserted on any change in
1054                                                      the B2M_STATE signal from the BLE Core.                                   */
1055       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
1056                                                      a overflow or underflow event                                             */
1057       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
1058                                                      written when an active command is in progress.                            */
1059       __IOM uint32_t BLECIRQ    : 1;            /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
1060                                                      from the BLE Core is asserted, indicating the availability
1061                                                      of read data from the BLE Core.                                           */
1062       __IOM uint32_t BLECSSTAT  : 1;            /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
1063                                                      signal from the BLE Core is asserted, indicating that SPI
1064                                                      writes can be done to the BLE Core.Transfers to the BLE
1065                                                      Core should only be done when this signal is high.                        */
1066       __IOM uint32_t DCMP       : 1;            /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
1067                                                      and the DMA submodule is returned into the idle state                     */
1068       __IOM uint32_t DERR       : 1;            /*!< [10..10] DMA Error encountered during the processing of the
1069                                                      DMA command. The DMA error could occur when the memory
1070                                                      access specified in the DMA operation is not available
1071                                                      or incorrectly specified.                                                 */
1072       __IOM uint32_t CQPAUSED   : 1;            /*!< [11..11] Command queue is paused due to an active event enabled
1073                                                      in the PAUSEEN register. The interrupt is posted when the
1074                                                      event is enabled within the PAUSEEN register, the mask
1075                                                      is active in the CQIRQMASK field and the event occurs.                    */
1076       __IOM uint32_t CQUPD      : 1;            /*!< [12..12] Command queue write operation executed a register write
1077                                                      with the register address bit 0 set to 1. The low address
1078                                                      bits in the CQ address fields are unused and bit 0 can
1079                                                      be used to trigger an interrupt to indicate when this register
1080                                                      write is performed by the CQ operation.                                   */
1081       __IOM uint32_t CQERR      : 1;            /*!< [13..13] Command queue error during processing. When an error
1082                                                      occurs, the system will stop processing and halt operations
1083                                                      to allow software to take recovery actions                                */
1084       __IOM uint32_t B2MSLEEP   : 1;            /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
1085                                                      sleep state                                                               */
1086       __IOM uint32_t B2MACTIVE  : 1;            /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
1087                                                      into the active state Revision B: Falling BLE Core IRQ
1088                                                      signal. Asserted when the BLE_IRQ signal from the BLE Core
1089                                                      is deasserted (1 -> 0)                                                    */
1090       __IOM uint32_t B2MSHUTDN  : 1;            /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
1091                                                      into shutdown state Revision B: Falling BLE Core Status
1092                                                      signal. Asserted when the BLE_STATUS signal from the BLE
1093                                                      Core is deasserted (1 -> 0)                                               */
1094             uint32_t            : 15;
1095     } INTSTAT_b;
1096   } ;
1097 
1098   union {
1099     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000228) Write a 1 to a bit in this register to clear
1100                                                                     the interrupt status associated with that
1101                                                                     bit.                                                       */
1102 
1103     struct {
1104       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
1105                                                      operation has completed. For repeated commands, this will
1106                                                      only be asserted when the final repeated command is completed.            */
1107       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
1108                                                      when the number of free bytes in the write FIFO equals
1109                                                      or exceeds the WTHR field.For read operations, asserted
1110                                                      when the number of valid bytes in the read FIFO equals
1111                                                      of exceeds the value set in the RTHR field.                               */
1112       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
1113                                                      is done to a empty read FIFO.                                             */
1114       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
1115                                                      tries to write to a full FIFO. The current operation does
1116                                                      not stop.                                                                 */
1117       __IOM uint32_t B2MST      : 1;            /*!< [4..4] B2M State change interrupt. Asserted on any change in
1118                                                      the B2M_STATE signal from the BLE Core.                                   */
1119       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
1120                                                      a overflow or underflow event                                             */
1121       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
1122                                                      written when an active command is in progress.                            */
1123       __IOM uint32_t BLECIRQ    : 1;            /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
1124                                                      from the BLE Core is asserted, indicating the availability
1125                                                      of read data from the BLE Core.                                           */
1126       __IOM uint32_t BLECSSTAT  : 1;            /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
1127                                                      signal from the BLE Core is asserted, indicating that SPI
1128                                                      writes can be done to the BLE Core.Transfers to the BLE
1129                                                      Core should only be done when this signal is high.                        */
1130       __IOM uint32_t DCMP       : 1;            /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
1131                                                      and the DMA submodule is returned into the idle state                     */
1132       __IOM uint32_t DERR       : 1;            /*!< [10..10] DMA Error encountered during the processing of the
1133                                                      DMA command. The DMA error could occur when the memory
1134                                                      access specified in the DMA operation is not available
1135                                                      or incorrectly specified.                                                 */
1136       __IOM uint32_t CQPAUSED   : 1;            /*!< [11..11] Command queue is paused due to an active event enabled
1137                                                      in the PAUSEEN register. The interrupt is posted when the
1138                                                      event is enabled within the PAUSEEN register, the mask
1139                                                      is active in the CQIRQMASK field and the event occurs.                    */
1140       __IOM uint32_t CQUPD      : 1;            /*!< [12..12] Command queue write operation executed a register write
1141                                                      with the register address bit 0 set to 1. The low address
1142                                                      bits in the CQ address fields are unused and bit 0 can
1143                                                      be used to trigger an interrupt to indicate when this register
1144                                                      write is performed by the CQ operation.                                   */
1145       __IOM uint32_t CQERR      : 1;            /*!< [13..13] Command queue error during processing. When an error
1146                                                      occurs, the system will stop processing and halt operations
1147                                                      to allow software to take recovery actions                                */
1148       __IOM uint32_t B2MSLEEP   : 1;            /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
1149                                                      sleep state                                                               */
1150       __IOM uint32_t B2MACTIVE  : 1;            /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
1151                                                      into the active state Revision B: Falling BLE Core IRQ
1152                                                      signal. Asserted when the BLE_IRQ signal from the BLE Core
1153                                                      is deasserted (1 -> 0)                                                    */
1154       __IOM uint32_t B2MSHUTDN  : 1;            /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
1155                                                      into shutdown state Revision B: Falling BLE Core Status
1156                                                      signal. Asserted when the BLE_STATUS signal from the BLE
1157                                                      Core is deasserted (1 -> 0)                                               */
1158             uint32_t            : 15;
1159     } INTCLR_b;
1160   } ;
1161 
1162   union {
1163     __IOM uint32_t INTSET;                      /*!< (@ 0x0000022C) Write a 1 to a bit in this register to instantly
1164                                                                     generate an interrupt from this module.
1165                                                                     (Generally used for testing purposes).                     */
1166 
1167     struct {
1168       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
1169                                                      operation has completed. For repeated commands, this will
1170                                                      only be asserted when the final repeated command is completed.            */
1171       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
1172                                                      when the number of free bytes in the write FIFO equals
1173                                                      or exceeds the WTHR field.For read operations, asserted
1174                                                      when the number of valid bytes in the read FIFO equals
1175                                                      of exceeds the value set in the RTHR field.                               */
1176       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
1177                                                      is done to a empty read FIFO.                                             */
1178       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
1179                                                      tries to write to a full FIFO. The current operation does
1180                                                      not stop.                                                                 */
1181       __IOM uint32_t B2MST      : 1;            /*!< [4..4] B2M State change interrupt. Asserted on any change in
1182                                                      the B2M_STATE signal from the BLE Core.                                   */
1183       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
1184                                                      a overflow or underflow event                                             */
1185       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
1186                                                      written when an active command is in progress.                            */
1187       __IOM uint32_t BLECIRQ    : 1;            /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
1188                                                      from the BLE Core is asserted, indicating the availability
1189                                                      of read data from the BLE Core.                                           */
1190       __IOM uint32_t BLECSSTAT  : 1;            /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
1191                                                      signal from the BLE Core is asserted, indicating that SPI
1192                                                      writes can be done to the BLE Core.Transfers to the BLE
1193                                                      Core should only be done when this signal is high.                        */
1194       __IOM uint32_t DCMP       : 1;            /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
1195                                                      and the DMA submodule is returned into the idle state                     */
1196       __IOM uint32_t DERR       : 1;            /*!< [10..10] DMA Error encountered during the processing of the
1197                                                      DMA command. The DMA error could occur when the memory
1198                                                      access specified in the DMA operation is not available
1199                                                      or incorrectly specified.                                                 */
1200       __IOM uint32_t CQPAUSED   : 1;            /*!< [11..11] Command queue is paused due to an active event enabled
1201                                                      in the PAUSEEN register. The interrupt is posted when the
1202                                                      event is enabled within the PAUSEEN register, the mask
1203                                                      is active in the CQIRQMASK field and the event occurs.                    */
1204       __IOM uint32_t CQUPD      : 1;            /*!< [12..12] Command queue write operation executed a register write
1205                                                      with the register address bit 0 set to 1. The low address
1206                                                      bits in the CQ address fields are unused and bit 0 can
1207                                                      be used to trigger an interrupt to indicate when this register
1208                                                      write is performed by the CQ operation.                                   */
1209       __IOM uint32_t CQERR      : 1;            /*!< [13..13] Command queue error during processing. When an error
1210                                                      occurs, the system will stop processing and halt operations
1211                                                      to allow software to take recovery actions                                */
1212       __IOM uint32_t B2MSLEEP   : 1;            /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
1213                                                      sleep state                                                               */
1214       __IOM uint32_t B2MACTIVE  : 1;            /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
1215                                                      into the active state Revision B: Falling BLE Core IRQ
1216                                                      signal. Asserted when the BLE_IRQ signal from the BLE Core
1217                                                      is deasserted (1 -> 0)                                                    */
1218       __IOM uint32_t B2MSHUTDN  : 1;            /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
1219                                                      into shutdown state Revision B: Falling BLE Core Status
1220                                                      signal. Asserted when the BLE_STATUS signal from the BLE
1221                                                      Core is deasserted (1 -> 0)                                               */
1222             uint32_t            : 15;
1223     } INTSET_b;
1224   } ;
1225 
1226   union {
1227     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000230) Provides control on which event will trigger
1228                                                                     the DMA transfer after the DMA operation
1229                                                                     is setup and enabled. The trigger event
1230                                                                     will cause a number of bytes (depending
1231                                                                     on trigger event) to betransferred via the
1232                                                                     DMA operation, and can be used to adjust
1233                                                                     the latency of data to/from the IOM module
1234                                                                     to/from the DMA target. DMA transfers are
1235                                                                     broken into smaller transfers internally
1236                                                                     of up to16 bytes each, and multiple trigger
1237                                                                     events can be used to complete the entire
1238                                                                     programmed DMA transfer.                                   */
1239 
1240     struct {
1241       __IOM uint32_t DCMDCMPEN  : 1;            /*!< [0..0] Trigger DMA upon command complete. Enables the trigger
1242                                                      of the DMA when a command is completed. When this event
1243                                                      is triggered, the number of words transferred will be the
1244                                                      lesser of the remaining TOTCOUNT bytes, or the number of
1245                                                      bytes in the FIFO when the command completed. If this is
1246                                                      disabled, and the number of bytes in the FIFO is equal
1247                                                      or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT
1248                                                      bytes will be done to ensure read data is stored when the
1249                                                      DMA is completed.                                                         */
1250       __IOM uint32_t DTHREN     : 1;            /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations
1251                                                      (IOM writes), the trigger will assert when the write FIFO
1252                                                      has (WTHR/4) number of words free in the write FIFO, and
1253                                                      will transfer (WTHR/4) number of wordsor, if the number
1254                                                      of words left to transfer is less than the WTHR value,
1255                                                      will transfer the remaining byte count.For P2M DMA operations,
1256                                                      the trigger will assert when the read FIFO has (RTHR/4)
1257                                                      words available in the read FIFO, and will transfer (RTHR/4)
1258                                                      words to SRAM. This trigger will NOT asser                                */
1259             uint32_t            : 30;
1260     } DMATRIGEN_b;
1261   } ;
1262 
1263   union {
1264     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000234) Provides the status of trigger events that have
1265                                                                     occurred for the transaction. Some of the
1266                                                                     bits are read only and some can be reset
1267                                                                     via a write of 0.                                          */
1268 
1269     struct {
1270       __IOM uint32_t DCMDCMP    : 1;            /*!< [0..0] Triggered DMA from Command complete event. Bit is read
1271                                                      only and can be cleared by disabling the DCMDCMP trigger
1272                                                      enable or by disabling DMA.                                               */
1273       __IOM uint32_t DTHR       : 1;            /*!< [1..1] Triggered DMA from THR event. Bit is read only and can
1274                                                      be cleared by disabling the DTHR trigger enable or by disabling
1275                                                      DMA.                                                                      */
1276       __IOM uint32_t DTOTCMP    : 1;            /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data
1277                                                      in the FIFO was enough to complete the DMA operation (greater
1278                                                      than or equal to current TOTCOUNT) when the command completed.
1279                                                      This trigger is default active when the DCMDCMP trigger
1280                                                      isdisabled and there is enough data in the FIFO to complete
1281                                                      the DMA operation.                                                        */
1282             uint32_t            : 29;
1283     } DMATRIGSTAT_b;
1284   } ;
1285 
1286   union {
1287     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000238) Configuration control of the DMA process, including
1288                                                                     the direction of DMA, and enablement of
1289                                                                     DMA                                                        */
1290 
1291     struct {
1292       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA
1293                                                      operation. This should be the last DMA related register
1294                                                      set prior to issuing the command                                          */
1295       __IOM uint32_t DMADIR     : 1;            /*!< [1..1] Direction                                                          */
1296             uint32_t            : 6;
1297       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
1298             uint32_t            : 23;
1299     } DMACFG_b;
1300   } ;
1301 
1302   union {
1303     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x0000023C) Contains the number of bytes to be transferred
1304                                                                     for this DMA transaction. This register
1305                                                                     is decremented as the data is transferred,
1306                                                                     and will be 0 at the completion of the DMA
1307                                                                     operation.                                                 */
1308 
1309     struct {
1310       __IOM uint32_t TOTCOUNT   : 12;           /*!< [11..0] Triggered DMA from Command complete event occurred.
1311                                                      Bit is read only and can be cleared by disabling the DTHR
1312                                                      trigger enable or by disabling DMA.                                       */
1313             uint32_t            : 20;
1314     } DMATOTCOUNT_b;
1315   } ;
1316 
1317   union {
1318     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000240) The source or destination address internal the
1319                                                                     SRAM for the DMA data. For write operations,
1320                                                                     this can only be SRAM data (ADDR bit 28
1321                                                                     = 1); For read operations, this can be either
1322                                                                     SRAM or FLASH (ADDR bit 28 = 0)                            */
1323 
1324     struct {
1325       __IOM uint32_t TARGADDR   : 21;           /*!< [20..0] Bits [19:0] of the target byte address for source of
1326                                                      DMA (either read or write). The address can be any byte
1327                                                      alignment, and does not have to be word aligned. In cases
1328                                                      of non-word aligned addresses, the DMA logic will take
1329                                                      care for ensuring only the target bytes are read/written.                 */
1330             uint32_t            : 7;
1331       __IOM uint32_t TARGADDR28 : 1;            /*!< [28..28] Bit 28 of the target byte address for source of DMA
1332                                                      (either read or write). In cases of non-word aligned addresses,
1333                                                      the DMA logic will take care for ensuring only the target
1334                                                      bytes are read/written.Setting to '1' will select the SRAM.
1335                                                      Setting to '0' will select the flash                                      */
1336             uint32_t            : 3;
1337     } DMATARGADDR_b;
1338   } ;
1339 
1340   union {
1341     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000244) Status of the DMA operation currently in progress.         */
1342 
1343     struct {
1344       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
1345                                                      a DMA transfer is active. The DMA transfer may be waiting
1346                                                      on data, transferring data, or waiting for priority.All
1347                                                      of these will be indicated with a 1. A 0 will indicate
1348                                                      that the DMA is fully complete and no further transactions
1349                                                      will be done. This bit is read only.                                      */
1350       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
1351                                                      operation. This bit can be cleared by writing to 0.                       */
1352       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals that an error
1353                                                      was encountered during the DMA operation.                                 */
1354             uint32_t            : 29;
1355     } DMASTAT_b;
1356   } ;
1357 
1358   union {
1359     __IOM uint32_t CQCFG;                       /*!< (@ 0x00000248) Controls parameters and options for execution
1360                                                                     of the command queue operation. To enable
1361                                                                     command queue, create this in memory, set
1362                                                                     the address, and enable it with a write
1363                                                                     to CQEN                                                    */
1364 
1365     struct {
1366       __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
1367                                                      of the command queue and fetches of address/data pairs
1368                                                      will proceed from the word address within the CQADDR register.
1369                                                      Can be disabledusing a CQ executed write to this bit as
1370                                                      well.                                                                     */
1371       __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue DMA request.                */
1372             uint32_t            : 30;
1373     } CQCFG_b;
1374   } ;
1375 
1376   union {
1377     __IOM uint32_t CQADDR;                      /*!< (@ 0x0000024C) The SRAM address which will be fetched next execution
1378                                                                     of the CQ operation. This register is updated
1379                                                                     as the CQ operation progresses, and is the
1380                                                                     live version of the register. The register
1381                                                                     can also bewritten by the Command Queue
1382                                                                     operation itself, allowing the relocation
1383                                                                     of successive CQ fetches. In this case,
1384                                                                     the new CQ address will be used for the
1385                                                                     next CQ address/data fetch                                 */
1386 
1387     struct {
1388             uint32_t            : 2;
1389       __IOM uint32_t CQADDR     : 19;           /*!< [20..2] Bits 19:2 of target byte address for source of CQ (read
1390                                                      only). The buffer must be aligned on a word boundary                      */
1391             uint32_t            : 7;
1392       __IOM uint32_t CQADDR28   : 1;            /*!< [28..28] Bit 28 of target byte address for source of CQ (read
1393                                                      only). Used to denote Flash (0) or SRAM (1) access                        */
1394             uint32_t            : 3;
1395     } CQADDR_b;
1396   } ;
1397 
1398   union {
1399     __IOM uint32_t CQSTAT;                      /*!< (@ 0x00000250) Provides the status of the command queue operation.
1400                                                                     If the command queue is disabled, these
1401                                                                     bits will be cleared. The bits are read
1402                                                                     only                                                       */
1403 
1404     struct {
1405       __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
1406                                                      indicate that a CQ transfer is active and this will remain
1407                                                      active even when paused waiting for external event.                       */
1408       __IOM uint32_t CQPAUSED   : 1;            /*!< [1..1] Command queue operation is currently paused.                       */
1409       __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing error. This active high bit
1410                                                      signals that an error was encountered during the CQ operation.            */
1411             uint32_t            : 29;
1412     } CQSTAT_b;
1413   } ;
1414 
1415   union {
1416     __IOM uint32_t CQFLAGS;                     /*!< (@ 0x00000254) Provides the current status of the SWFLAGS (bits
1417                                                                     7:0) and the hardware generated flags (15:8).
1418                                                                     A '1' will pause the CQ operation if it
1419                                                                     the same bit is enabled in the CQPAUSEEN
1420                                                                     register                                                   */
1421 
1422     struct {
1423       __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
1424                                                      controllable and bits [15:8] are hardware status.                         */
1425       __IOM uint32_t CQIRQMASK  : 16;           /*!< [31..16] Provides for a per-bit mask of the flags used to invoke
1426                                                      an interrupt. A '1' in the bit position will enable the
1427                                                      pause event to trigger the interrupt, if the CQWT_int interrupt
1428                                                      is enabled.Bits definitions are the same as CQPAUSE                       */
1429     } CQFLAGS_b;
1430   } ;
1431 
1432   union {
1433     __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x00000258) Set/Clear the command queue software pause flags
1434                                                                     on a per-bit basis. Contains 3 fields, allowing
1435                                                                     for setting, clearing or toggling the value
1436                                                                     in the software flags. Priority when the
1437                                                                     same bitis enabled in each field is toggle,
1438                                                                     then set, then clear.                                      */
1439 
1440     struct {
1441       __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any
1442                                                      SWFLAG with a '1' in the corresponding bit position of
1443                                                      this field                                                                */
1444       __IOM uint32_t CQFTGL     : 8;            /*!< [15..8] Toggle the indicated bit. Will toggle the value of any
1445                                                      SWFLAG with a '1' in the corresponding bit position of
1446                                                      this field                                                                */
1447       __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG
1448                                                      with a '1' in the corresponding bit position of this field                */
1449             uint32_t            : 8;
1450     } CQSETCLEAR_b;
1451   } ;
1452 
1453   union {
1454     __IOM uint32_t CQPAUSEEN;                   /*!< (@ 0x0000025C) Enables a flag to pause an active command queue
1455                                                                     operation. If a bit is '1' and the corresponding
1456                                                                     bit in the CQFLAG register is '1', CQ processing
1457                                                                     will halt until either value is changed
1458                                                                     to '0'.                                                    */
1459 
1460     struct {
1461       __IOM uint32_t CQPEN      : 16;           /*!< [15..0] Enables the specified event to pause command processing
1462                                                      when active                                                               */
1463             uint32_t            : 16;
1464     } CQPAUSEEN_b;
1465   } ;
1466 
1467   union {
1468     __IOM uint32_t CQCURIDX;                    /*!< (@ 0x00000260) Current index value, targeted to be written by
1469                                                                     register write operations within the command
1470                                                                     queue. This is compared to the CQENDIDX
1471                                                                     and will stop the CQ operation if bit 15
1472                                                                     of the CQPAUSEEN is '1' andthis current
1473                                                                     index equals the CQENDIDX register value.
1474                                                                     This will only pause when the values are
1475                                                                     equal.                                                     */
1476 
1477     struct {
1478       __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX
1479                                                      register field. If the values match, the IDXEQ pause event
1480                                                      will be activated, which will cause the pausing of command
1481                                                      queue operation if the IDXEQ bit is enabled in CQPAUSEEN.                 */
1482             uint32_t            : 24;
1483     } CQCURIDX_b;
1484   } ;
1485 
1486   union {
1487     __IOM uint32_t CQENDIDX;                    /*!< (@ 0x00000264) End index value, targeted to be written by software
1488                                                                     to indicate the last valid register pair
1489                                                                     contained within the command queue for register
1490                                                                     write operations within the command queue.This
1491                                                                     is compared to the CQCURIDX and will stop
1492                                                                     the CQ operation if bit 15 of the CQPAUSEEN
1493                                                                     is '1' andthis current index equals the
1494                                                                     CQCURIDX register value. This will only
1495                                                                     pause when the values are equal.                           */
1496 
1497     struct {
1498       __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX
1499                                                      register field. If the values match, the IDXEQ pause event
1500                                                      will be activated, which will cause the pausing of command
1501                                                      queue operation if the IDXEQ bit is enabled in CQPAUSEEN.                 */
1502             uint32_t            : 24;
1503     } CQENDIDX_b;
1504   } ;
1505 
1506   union {
1507     __IOM uint32_t STATUS;                      /*!< (@ 0x00000268) General status of the IOM module command execution.        */
1508 
1509     struct {
1510       __IOM uint32_t ERR        : 1;            /*!< [0..0] Bit has been deprecated. Please refer to the other error
1511                                                      indicators. This will always return 0.                                    */
1512       __IOM uint32_t CMDACT     : 1;            /*!< [1..1] Indicates if the active I/O Command is currently processing
1513                                                      a transaction, or command is complete, but the FIFO pointers
1514                                                      are still synchronizing internally. This bit will go high
1515                                                      atthe start of the transaction, and will go low when the
1516                                                      command is complete, and the data and pointers within the
1517                                                      FIFO have been synchronized.                                              */
1518       __IOM uint32_t IDLEST     : 1;            /*!< [2..2] indicates if the active I/O state machine is IDLE. Note
1519                                                      - The state machine could be in idle state due to hold-offs
1520                                                      from data availability, or as the command gets propagated
1521                                                      into the logic from the registers.                                        */
1522             uint32_t            : 29;
1523     } STATUS_b;
1524   } ;
1525   __IM  uint32_t  RESERVED4[37];
1526 
1527   union {
1528     __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000300) Controls the configuration of the SPI master
1529                                                                     module, including POL/PHA, LSB, flow control,
1530                                                                     and delays for MISO and MOSI                               */
1531 
1532     struct {
1533       __IOM uint32_t SPOL       : 1;            /*!< [0..0] This bit selects SPI polarity.                                     */
1534       __IOM uint32_t SPHA       : 1;            /*!< [1..1] Selects the SPI phase; When 1, will shift the sampling
1535                                                      edge by 1/2 clock.                                                        */
1536       __IOM uint32_t FULLDUP    : 1;            /*!< [2..2] Full Duplex mode. Capture read data during writes operations       */
1537             uint32_t            : 13;
1538       __IOM uint32_t WTFC       : 1;            /*!< [16..16] Enables flow control of new write transactions based
1539                                                      on the SPI_STATUS signal from the BLE Core.                               */
1540       __IOM uint32_t RDFC       : 1;            /*!< [17..17] Enables flow control of new read transactions based
1541                                                      on the SPI_STATUS signal from the BLE Core.                               */
1542             uint32_t            : 3;
1543       __IOM uint32_t WTFCPOL    : 1;            /*!< [21..21] Selects the write flow control signal polarity. The
1544                                                      transfers are halted when the selected flow control signal
1545                                                      is OPPOSITE polarity of this bit. (For example: WTFCPOL
1546                                                      = 0 will allow a SPI_STATUS=1 to pause transfers).                        */
1547       __IOM uint32_t RDFCPOL    : 1;            /*!< [22..22] Selects the read flow control signal polarity. When
1548                                                      set, the clock will be held low until the flow control
1549                                                      is deasserted.                                                            */
1550       __IOM uint32_t SPILSB     : 1;            /*!< [23..23] Selects data transfer as MSB first (0) or LSB first
1551                                                      (1) for the data portion of the SPI transaction. The offset
1552                                                      bytes are always transmitted MSB first.                                   */
1553       __IOM uint32_t DINDLY     : 3;            /*!< [26..24] Delay tap to use for the input signal (MISO). This
1554                                                      gives more hold time on the input data.                                   */
1555       __IOM uint32_t DOUTDLY    : 3;            /*!< [29..27] Delay tap to use for the output signal (MOSI). This
1556                                                      give more hold time on the output data.                                   */
1557       __IOM uint32_t MSPIRST    : 1;            /*!< [30..30] Bit is deprecated. setting it will have no effect.               */
1558             uint32_t            : 1;
1559     } MSPICFG_b;
1560   } ;
1561 
1562   union {
1563     __IOM uint32_t BLECFG;                      /*!< (@ 0x00000304) Provides control of isolation and IO signals
1564                                                                     between the interface module and the BLE
1565                                                                     Core.                                                      */
1566 
1567     struct {
1568       __IOM uint32_t PWRSMEN    : 1;            /*!< [0..0] Enable the power state machine for automatic sequencing
1569                                                      and control of power states of the BLE Core module.                       */
1570       __IOM uint32_t BLERSTN    : 1;            /*!< [1..1] Reset line to the BLE Core. This will reset the BLE core
1571                                                      when asserted ('0') and must be written to '1' prior to
1572                                                      performing any BTLE related operations to the core.                       */
1573       __IOM uint32_t WAKEUPCTL  : 2;            /*!< [3..2] WAKE signal override. Controls the source of the WAKE
1574                                                      signal to the BLE Core.                                                   */
1575       __IOM uint32_t DCDCFLGCTL : 2;            /*!< [5..4] DCDCFLG signal override. The value of this field will
1576                                                      be sent to the BLE Core when the PWRSM is off. Otherwise,
1577                                                      the value is supplied from internal logic.                                */
1578       __IOM uint32_t BLEHREQCTL : 2;            /*!< [7..6] BLEH power on request override. The value of this field
1579                                                      will be sent to the BLE Core when the PWRSM is off. Otherwise,
1580                                                      the value is supplied from internal logic.                                */
1581       __IOM uint32_t WT4ACTOFF  : 1;            /*!< [8..8] Debug control of BLEIF power state machine. Allows transition
1582                                                      into the active state in the BLEIF state without waiting
1583                                                      for DCDC request from BLE Core.                                           */
1584       __IOM uint32_t MCUFRCSLP  : 1;            /*!< [9..9] Force power state machine to go to the sleep state. Intended
1585                                                      for debug only. Has no effect on the actual BLE Core state,
1586                                                      only the state of the BLEIF interface state machine.                      */
1587       __IOM uint32_t FRCCLK     : 1;            /*!< [10..10] Force the clock in the BLEIF to be always running                */
1588       __IOM uint32_t STAYASLEEP : 1;            /*!< [11..11] Set to prevent the BLE power control module from waking
1589                                                      up the BLE Core after going into power down. To be used
1590                                                      for graceful shutdown, set by software prior to powering
1591                                                      off and will allow assertion of reset from sleep state.                   */
1592       __IOM uint32_t PWRISOCTL  : 2;            /*!< [13..12] Configuration of BLEH isolation control for power related
1593                                                      signals.                                                                  */
1594       __IOM uint32_t SPIISOCTL  : 2;            /*!< [15..14] Configuration of BLEH isolation controls for SPI related
1595                                                      signals.                                                                  */
1596             uint32_t            : 16;
1597     } BLECFG_b;
1598   } ;
1599 
1600   union {
1601     __IOM uint32_t PWRCMD;                      /*!< (@ 0x00000308) Sends power related commands to the power state
1602                                                                     machine in the BLE IF module.                              */
1603 
1604     struct {
1605       __IOM uint32_t WAKEREQ    : 1;            /*!< [0..0] Wake request from the MCU. When asserted (1), the BLE
1606                                                      Interface logic will assert the wakeup request signal to
1607                                                      the BLE Core. Only recognized when in the sleep state                     */
1608       __IOM uint32_t RESTART    : 1;            /*!< [1..1] Restart the BLE Core after going into the shutdown state.
1609                                                      Only valid when in the shutdown state.                                    */
1610             uint32_t            : 30;
1611     } PWRCMD_b;
1612   } ;
1613 
1614   union {
1615     __IOM uint32_t BSTATUS;                     /*!< (@ 0x0000030C) Status of the BLE Core interface signals                   */
1616 
1617     struct {
1618       __IOM uint32_t B2MSTATE   : 3;            /*!< [2..0] State of the BLE Core logic.                                       */
1619       __IOM uint32_t SPISTATUS  : 1;            /*!< [3..3] Value of the SPISTATUS signal from the BLE Core. The
1620                                                      signal is asserted when the BLE Core is able to accept
1621                                                      write data via the SPI interface. Data should be transmitted
1622                                                      to theBLE core only when this signal is 1. The hardware
1623                                                      will automatically wait for this signal prior to performing
1624                                                      a write operation if flow control is active.                              */
1625       __IOM uint32_t DCDCREQ    : 1;            /*!< [4..4] Value of the DCDCREQ signal from the BLE Core. The DCDCREQ
1626                                                      signal is sent from the core to the BLEIF module when the
1627                                                      BLE core requires BLEH power to be active. When activated,
1628                                                      this isindicated by DCDCFLAG going to 1.                                  */
1629       __IOM uint32_t DCDCFLAG   : 1;            /*!< [5..5] Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG
1630                                                      is a signal to the BLE Core indicating that the BLEH power
1631                                                      is active.                                                                */
1632       __IOM uint32_t WAKEUP     : 1;            /*!< [6..6] Value of the WAKEUP signal to the BLE Core . The WAKEUP
1633                                                      signals is sent from the BLEIF to the BLECORE to request
1634                                                      the BLE Core transition from sleep state to active state.                 */
1635       __IOM uint32_t BLEIRQ     : 1;            /*!< [7..7] Status of the BLEIRQ signal from the BLE Core. A value
1636                                                      of 1 indicates that read data is available in the core
1637                                                      and a read operation needs to be performed.                               */
1638       __IOM uint32_t PWRST      : 3;            /*!< [10..8] Current status of the power state machine                         */
1639       __IOM uint32_t BLEHACK    : 1;            /*!< [11..11] Value of the BLEHACK signal from the power control
1640                                                      unit. If the signal is '1', the BLEH power is active and
1641                                                      ready for use.                                                            */
1642       __IOM uint32_t BLEHREQ    : 1;            /*!< [12..12] Value of the BLEHREQ signal to the power control unit.
1643                                                      The BLEHREQ signal is sent from the BLEIF module to the
1644                                                      power control module to request the BLEH power up. When
1645                                                      the BLEHACK signal is asserted,BLEH power is stable and
1646                                                      ready for use.                                                            */
1647             uint32_t            : 19;
1648     } BSTATUS_b;
1649   } ;
1650   __IM  uint32_t  RESERVED5[64];
1651 
1652   union {
1653     __IOM uint32_t BLEDBG;                      /*!< (@ 0x00000410) Debug control                                              */
1654 
1655     struct {
1656       __IOM uint32_t DBGEN      : 1;            /*!< [0..0] Debug Enable. Setting this bit will enable the update
1657                                                      of data within this register, otherwise it is clock gated
1658                                                      for power savings                                                         */
1659       __IOM uint32_t IOCLKON    : 1;            /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active
1660                                                      when this bit is '1'. Otherwise, the clock is controlled
1661                                                      with gating from the logic as needed.                                     */
1662       __IOM uint32_t APBCLKON   : 1;            /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
1663                                                      when this bit is '1'. Otherwise, the clock is controlled
1664                                                      with gating from the logic as needed.                                     */
1665       __IOM uint32_t DBGDATA    : 29;           /*!< [31..3] Debug data                                                        */
1666     } BLEDBG_b;
1667   } ;
1668 } BLEIF_Type;                                   /*!< Size = 1044 (0x414)                                                       */
1669 
1670 
1671 
1672 /* =========================================================================================================================== */
1673 /* ================                                         CACHECTRL                                         ================ */
1674 /* =========================================================================================================================== */
1675 
1676 
1677 /**
1678   * @brief FLASH Cache Controller (CACHECTRL)
1679   */
1680 
1681 typedef struct {                                /*!< (@ 0x40018000) CACHECTRL Structure                                        */
1682 
1683   union {
1684     __IOM uint32_t CACHECFG;                    /*!< (@ 0x00000000) FLASH Cache Control                                        */
1685 
1686     struct {
1687       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] Enables the FLASH cache controller and enables power
1688                                                      to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE
1689                                                      should be set to enable caching for each type of access.                  */
1690       __IOM uint32_t LRU        : 1;            /*!< [1..1] Sets the cache replacement policy. 0=LRR (least recently
1691                                                      replaced), 1=LRU (least recently used). LRR minimizes writes
1692                                                      to the TAG SRAM.                                                          */
1693       __IOM uint32_t ENABLE_NC0 : 1;            /*!< [2..2] Enable Non-cacheable region 0. See NCR0 registers to
1694                                                      define the region.                                                        */
1695       __IOM uint32_t ENABLE_NC1 : 1;            /*!< [3..3] Enable Non-cacheable region 1. See NCR1 registers to
1696                                                      define the region.                                                        */
1697       __IOM uint32_t CONFIG     : 4;            /*!< [7..4] Sets the cache configuration                                       */
1698       __IOM uint32_t ICACHE_ENABLE : 1;         /*!< [8..8] Enable FLASH Instruction Caching                                   */
1699       __IOM uint32_t DCACHE_ENABLE : 1;         /*!< [9..9] Enable FLASH Data Caching                                          */
1700       __IOM uint32_t CACHE_CLKGATE : 1;         /*!< [10..10] Enable clock gating of cache TAG RAM. Software should
1701                                                      enable this bit for optimal power efficiency.                             */
1702       __IOM uint32_t CACHE_LS   : 1;            /*!< [11..11] Enable LS (light sleep) of cache RAMs. Software should
1703                                                      DISABLE this bit since cache activity is too high to benefit
1704                                                      from LS usage.                                                            */
1705             uint32_t            : 8;
1706       __IOM uint32_t DATA_CLKGATE : 1;          /*!< [20..20] Enable aggressive clock gating of entire data array.
1707                                                      This bit should be set to 1 for optimal power efficiency.                 */
1708             uint32_t            : 3;
1709       __IOM uint32_t ENABLE_MONITOR : 1;        /*!< [24..24] Enable Cache Monitoring Stats. Cache monitoring consumes
1710                                                      additional power and should only be enabled when profiling
1711                                                      code and counters will increment when this bit is set.
1712                                                      Counter values will be retained when this is set to 0,
1713                                                      allowing software to enable/disable counting for multiple
1714                                                      code segments.                                                            */
1715             uint32_t            : 7;
1716     } CACHECFG_b;
1717   } ;
1718   __IM  uint32_t  RESERVED;
1719 
1720   union {
1721     __IOM uint32_t CTRL;                        /*!< (@ 0x00000008) Cache Control                                              */
1722 
1723     struct {
1724       __IOM uint32_t INVALIDATE : 1;            /*!< [0..0] Writing a 1 to this bit field invalidates the FLASH cache
1725                                                      contents.                                                                 */
1726       __IOM uint32_t RESET_STAT : 1;            /*!< [1..1] Reset Cache Statistics. When written to a 1, the cache
1727                                                      monitor counters will be cleared. The monitor counters
1728                                                      can be reset only when the CACHECFG.ENABLE_MONITOR bit
1729                                                      is set.                                                                   */
1730       __IOM uint32_t CACHE_READY : 1;           /*!< [2..2] Cache Ready Status (enabled and not processing an invalidate
1731                                                      operation)                                                                */
1732             uint32_t            : 1;
1733       __IOM uint32_t FLASH0_SLM_STATUS : 1;     /*!< [4..4] FLASH Sleep Mode Status. 1 indicates that FLASH0 is in
1734                                                      sleep mode, 0 indicates FLASH0 is in normal mode.                         */
1735       __IOM uint32_t FLASH0_SLM_DISABLE : 1;    /*!< [5..5] Disable FLASH Sleep Mode. Write 1 to wake FLASH0 from
1736                                                      sleep mode (reading the array will also automatically wake
1737                                                      it).                                                                      */
1738       __IOM uint32_t FLASH0_SLM_ENABLE : 1;     /*!< [6..6] Enable FLASH Sleep Mode. Write to 1 to put FLASH0 into
1739                                                      sleep mode. NOTE: there is a 5 us latency after waking
1740                                                      FLASH until the first access will be returned.                            */
1741             uint32_t            : 1;
1742       __IOM uint32_t FLASH1_SLM_STATUS : 1;     /*!< [8..8] FLASH Sleep Mode Status. 1 indicates that FLASH1 is in
1743                                                      sleep mode, 0 indicates FLASH1 is in normal mode.                         */
1744       __IOM uint32_t FLASH1_SLM_DISABLE : 1;    /*!< [9..9] Disable FLASH Sleep Mode. Write 1 to wake FLASH1 from
1745                                                      sleep mode (reading the array will also automatically wake
1746                                                      it).                                                                      */
1747       __IOM uint32_t FLASH1_SLM_ENABLE : 1;     /*!< [10..10] Enable FLASH Sleep Mode. Write to 1 to put FLASH1 into
1748                                                      sleep mode. NOTE: there is a 5 us latency after waking
1749                                                      FLASH until the first access will be returned.                            */
1750             uint32_t            : 1;
1751       __IOM uint32_t FLASH2_SLM_STATUS : 1;     /*!< [12..12] FLASH Sleep Mode Status. 1 indicates that FLASH2 is
1752                                                      in sleep mode, 0 indicates FLASH2 is in normal mode.                      */
1753       __IOM uint32_t FLASH2_SLM_DISABLE : 1;    /*!< [13..13] Disable FLASH Sleep Mode. Write 1 to wake FLASH2 from
1754                                                      sleep mode (reading the array will also automatically wake
1755                                                      it).                                                                      */
1756       __IOM uint32_t FLASH2_SLM_ENABLE : 1;     /*!< [14..14] Enable FLASH Sleep Mode. Write to 1 to put FLASH1 into
1757                                                      sleep mode. NOTE: there is a 5 us latency after waking
1758                                                      FLASH until the first access will be returned.                            */
1759             uint32_t            : 1;
1760       __IOM uint32_t FLASH3_SLM_STATUS : 1;     /*!< [16..16] FLASH Sleep Mode Status. 1 indicates that FLASH1 is
1761                                                      in sleep mode, 0 indicates FLASH1 is in normal mode.                      */
1762       __IOM uint32_t FLASH3_SLM_DISABLE : 1;    /*!< [17..17] Disable FLASH Sleep Mode. Write 1 to wake FLASH1 from
1763                                                      sleep mode (reading the array will also automatically wake
1764                                                      it).                                                                      */
1765       __IOM uint32_t FLASH3_SLM_ENABLE : 1;     /*!< [18..18] Enable FLASH Sleep Mode. Write to 1 to put FLASH1 into
1766                                                      sleep mode. NOTE: there is a 5 us latency after waking
1767                                                      FLASH until the first access will be returned.                            */
1768             uint32_t            : 13;
1769     } CTRL_b;
1770   } ;
1771   __IM  uint32_t  RESERVED1;
1772 
1773   union {
1774     __IOM uint32_t NCR0START;                   /*!< (@ 0x00000010) FLASH Cache Noncacheable Region 0 Start                    */
1775 
1776     struct {
1777             uint32_t            : 4;
1778       __IOM uint32_t ADDR       : 23;           /*!< [26..4] Start address for non-cacheable region 0                          */
1779             uint32_t            : 5;
1780     } NCR0START_b;
1781   } ;
1782 
1783   union {
1784     __IOM uint32_t NCR0END;                     /*!< (@ 0x00000014) FLASH Cache Noncacheable Region 0 End                      */
1785 
1786     struct {
1787             uint32_t            : 4;
1788       __IOM uint32_t ADDR       : 23;           /*!< [26..4] End address for non-cacheable region 0                            */
1789             uint32_t            : 5;
1790     } NCR0END_b;
1791   } ;
1792 
1793   union {
1794     __IOM uint32_t NCR1START;                   /*!< (@ 0x00000018) FLASH Cache Noncacheable Region 1 Start                    */
1795 
1796     struct {
1797             uint32_t            : 4;
1798       __IOM uint32_t ADDR       : 23;           /*!< [26..4] Start address for non-cacheable region 1                          */
1799             uint32_t            : 5;
1800     } NCR1START_b;
1801   } ;
1802 
1803   union {
1804     __IOM uint32_t NCR1END;                     /*!< (@ 0x0000001C) FLASH Cache Noncacheable Region 1 End                      */
1805 
1806     struct {
1807             uint32_t            : 4;
1808       __IOM uint32_t ADDR       : 23;           /*!< [26..4] End address for non-cacheable region 1                            */
1809             uint32_t            : 5;
1810     } NCR1END_b;
1811   } ;
1812   __IM  uint32_t  RESERVED2[8];
1813 
1814   union {
1815     __IOM uint32_t DMON0;                       /*!< (@ 0x00000040) Data Cache Total Accesses                                  */
1816 
1817     struct {
1818       __IOM uint32_t DACCESS_COUNT : 32;        /*!< [31..0] Total accesses to data cache. All performance metrics
1819                                                      should be relative to the number of accesses performed.                   */
1820     } DMON0_b;
1821   } ;
1822 
1823   union {
1824     __IOM uint32_t DMON1;                       /*!< (@ 0x00000044) Data Cache Tag Lookups                                     */
1825 
1826     struct {
1827       __IOM uint32_t DLOOKUP_COUNT : 32;        /*!< [31..0] Total tag lookups from data cache.                                */
1828     } DMON1_b;
1829   } ;
1830 
1831   union {
1832     __IOM uint32_t DMON2;                       /*!< (@ 0x00000048) Data Cache Hits                                            */
1833 
1834     struct {
1835       __IOM uint32_t DHIT_COUNT : 32;           /*!< [31..0] Cache hits from lookup operations.                                */
1836     } DMON2_b;
1837   } ;
1838 
1839   union {
1840     __IOM uint32_t DMON3;                       /*!< (@ 0x0000004C) Data Cache Line Hits                                       */
1841 
1842     struct {
1843       __IOM uint32_t DLINE_COUNT : 32;          /*!< [31..0] Cache hits from line cache                                        */
1844     } DMON3_b;
1845   } ;
1846 
1847   union {
1848     __IOM uint32_t IMON0;                       /*!< (@ 0x00000050) Instruction Cache Total Accesses                           */
1849 
1850     struct {
1851       __IOM uint32_t IACCESS_COUNT : 32;        /*!< [31..0] Total accesses to Instruction cache                               */
1852     } IMON0_b;
1853   } ;
1854 
1855   union {
1856     __IOM uint32_t IMON1;                       /*!< (@ 0x00000054) Instruction Cache Tag Lookups                              */
1857 
1858     struct {
1859       __IOM uint32_t ILOOKUP_COUNT : 32;        /*!< [31..0] Total tag lookups from Instruction cache                          */
1860     } IMON1_b;
1861   } ;
1862 
1863   union {
1864     __IOM uint32_t IMON2;                       /*!< (@ 0x00000058) Instruction Cache Hits                                     */
1865 
1866     struct {
1867       __IOM uint32_t IHIT_COUNT : 32;           /*!< [31..0] Cache hits from lookup operations                                 */
1868     } IMON2_b;
1869   } ;
1870 
1871   union {
1872     __IOM uint32_t IMON3;                       /*!< (@ 0x0000005C) Instruction Cache Line Hits                                */
1873 
1874     struct {
1875       __IOM uint32_t ILINE_COUNT : 32;          /*!< [31..0] Cache hits from line cache                                        */
1876     } IMON3_b;
1877   } ;
1878   __IM  uint32_t  RESERVED3[40];
1879 
1880   union {
1881     __IOM uint32_t FLASH0CFG;                   /*!< (@ 0x00000100) FLASH 0 Control                                            */
1882 
1883     struct {
1884       __IOM uint32_t RDWAIT0    : 4;            /*!< [3..0] Sets read wait states for normal (fast) operation. A
1885                                                      value of 1 is recommended.                                                */
1886       __IOM uint32_t SEDELAY0   : 3;            /*!< [6..4] Sets SE delay (FLASH address setup). A value of 5 is
1887                                                      recommended.                                                              */
1888             uint32_t            : 1;
1889       __IOM uint32_t LPMRDWAIT0 : 4;            /*!< [11..8] Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in
1890                                                      LPM mode 2 only)                                                          */
1891       __IOM uint32_t LPMMODE0   : 2;            /*!< [13..12] Controls FLASH low power modes (control of LPM pin).             */
1892             uint32_t            : 18;
1893     } FLASH0CFG_b;
1894   } ;
1895 
1896   union {
1897     __IOM uint32_t FLASH1CFG;                   /*!< (@ 0x00000104) FLASH 1 Control                                            */
1898 
1899     struct {
1900       __IOM uint32_t RDWAIT1    : 4;            /*!< [3..0] Sets read wait states for normal (fast) operation. A
1901                                                      value of 1 is recommended.                                                */
1902       __IOM uint32_t SEDELAY1   : 3;            /*!< [6..4] Sets SE delay (FLASH address setup). A value of 5 is
1903                                                      recommended.                                                              */
1904             uint32_t            : 1;
1905       __IOM uint32_t LPMRDWAIT1 : 4;            /*!< [11..8] Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in
1906                                                      LPM mode 2 only)                                                          */
1907       __IOM uint32_t LPMMODE1   : 2;            /*!< [13..12] Controls FLASH low power modes (control of LPM pin).             */
1908             uint32_t            : 18;
1909     } FLASH1CFG_b;
1910   } ;
1911 
1912   union {
1913     __IOM uint32_t FLASH2CFG;                   /*!< (@ 0x00000108) FLASH 2 Control                                            */
1914 
1915     struct {
1916       __IOM uint32_t RDWAIT2    : 4;            /*!< [3..0] Sets read wait states for normal (fast) operation. A
1917                                                      value of 1 is recommended.                                                */
1918       __IOM uint32_t SEDELAY2   : 3;            /*!< [6..4] Sets SE delay (FLASH address setup). A value of 5 is
1919                                                      recommended.                                                              */
1920             uint32_t            : 1;
1921       __IOM uint32_t LPMRDWAIT2 : 4;            /*!< [11..8] Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in
1922                                                      LPM mode 2 only)                                                          */
1923       __IOM uint32_t LPMMODE2   : 2;            /*!< [13..12] Controls FLASH low power modes (control of LPM pin).             */
1924             uint32_t            : 18;
1925     } FLASH2CFG_b;
1926   } ;
1927 
1928   union {
1929     __IOM uint32_t FLASH3CFG;                   /*!< (@ 0x0000010C) FLASH 3 Control                                            */
1930 
1931     struct {
1932       __IOM uint32_t RDWAIT3    : 4;            /*!< [3..0] Sets read wait states for normal (fast) operation. A
1933                                                      value of 1 is recommended.                                                */
1934       __IOM uint32_t SEDELAY3   : 3;            /*!< [6..4] Sets SE delay (FLASH address setup). A value of 5 is
1935                                                      recommended.                                                              */
1936             uint32_t            : 1;
1937       __IOM uint32_t LPMRDWAIT3 : 4;            /*!< [11..8] Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in
1938                                                      LPM mode 2 only)                                                          */
1939       __IOM uint32_t LPMMODE3   : 2;            /*!< [13..12] Controls FLASH low power modes (control of LPM pin).             */
1940             uint32_t            : 18;
1941     } FLASH3CFG_b;
1942   } ;
1943 } CACHECTRL_Type;                               /*!< Size = 272 (0x110)                                                        */
1944 
1945 
1946 
1947 /* =========================================================================================================================== */
1948 /* ================                                          CLKGEN                                           ================ */
1949 /* =========================================================================================================================== */
1950 
1951 
1952 /**
1953   * @brief Clock Generator (CLKGEN)
1954   */
1955 
1956 typedef struct {                                /*!< (@ 0x40004000) CLKGEN Structure                                           */
1957 
1958   union {
1959     __IOM uint32_t CALXT;                       /*!< (@ 0x00000000) This is the XT Oscillator Calibration value.
1960                                                                     This value allows any derived XT clocks
1961                                                                     to be calibrated. This means that the original
1962                                                                     32KHz version of XT will not be changed,
1963                                                                     but a 16KHz version (divided down version)
1964                                                                     can be modified. This register value will
1965                                                                     add or subtract the number of cycles programmed
1966                                                                     in this register across a 32 seconds interval.
1967                                                                     For example, if a value of 100 is programmed
1968                                                                     in this register, then 100 additional clock
1969                                                                     cycles will be added into a 16KHz clock
1970                                                                     period across                                              */
1971 
1972     struct {
1973       __IOM uint32_t CALXT      : 11;           /*!< [10..0] XT Oscillator calibration value. This register will
1974                                                      enable the hardware to increase or decrease the number
1975                                                      of cycles in a 16KHz clock derived from the original 32KHz
1976                                                      version. The most significant bit is the sign. A '1' is
1977                                                      a reduction, and a '0' is an addition. This calibration
1978                                                      value will add or reduce the number of cycles programmed
1979                                                      here across a 32 second interval. The maximum value that
1980                                                      is effective is from -976 to 975.                                         */
1981             uint32_t            : 21;
1982     } CALXT_b;
1983   } ;
1984 
1985   union {
1986     __IOM uint32_t CALRC;                       /*!< (@ 0x00000004) This is the LFRC Calibration value. Similar to
1987                                                                     the XT calibration, it allows the derived
1988                                                                     LFRC clock to be calibrated. The original
1989                                                                     1024Hz clock source will not change, but
1990                                                                     a 512Hz version (divided down version) can
1991                                                                     be modified. This register will add or subtract
1992                                                                     the number of cycles programmed in this
1993                                                                     register across a 1024 seconds interval.
1994                                                                     For example, if a value of 200 is programmed
1995                                                                     in this register, then 200 additional clocks
1996                                                                     will be added into the 512Hz derived clock
1997                                                                     across a 1024 secon                                        */
1998 
1999     struct {
2000       __IOM uint32_t CALRC      : 18;           /*!< [17..0] LFRC Oscillator calibration value. This register will
2001                                                      enable the hardware to increase or decrease the number
2002                                                      of cycles in a 512 Hz clock derived from the original 1024
2003                                                      version. The most significant bit is the sign. A '1' is
2004                                                      a reduction, and a '0' is an addition. This calibration
2005                                                      value will add or reduce the number of cycles programmed
2006                                                      here across a 32 second interval. The range is from -131072
2007                                                      (decimal) to 131071 (decimal). This register is normally
2008                                                      used in conjunction with ACALCTR register. The CALRC regi                 */
2009             uint32_t            : 14;
2010     } CALRC_b;
2011   } ;
2012 
2013   union {
2014     __IOM uint32_t ACALCTR;                     /*!< (@ 0x00000008) This register can be used for 2 purposes. The
2015                                                                     first is to calibrate the LFRC clock using
2016                                                                     the XT clock source. The second is to measure
2017                                                                     an internal clock signal relative to the
2018                                                                     external clock. In that case, the ACALCTR
2019                                                                     will show the multiple of the external clock
2020                                                                     with respect to the internal clock signal.
2021                                                                     E.g. Fref = Fmeas x ACALCTR. Note that this
2022                                                                     register should not be confused with the
2023                                                                     HFRC Adjustment register, which is separately
2024                                                                     defined in CLKGEN_HFADJ register.                          */
2025 
2026     struct {
2027       __IOM uint32_t ACALCTR    : 24;           /*!< [23..0] Autocalibration Counter result. Bits 17 down to 0 of
2028                                                      this is feed directly to the CALRC register if ACAL register
2029                                                      in OCTRL register is set to 1024SEC or 512SEC.                            */
2030             uint32_t            : 8;
2031     } ACALCTR_b;
2032   } ;
2033 
2034   union {
2035     __IOM uint32_t OCTRL;                       /*!< (@ 0x0000000C) This register includes controls for autocalibration
2036                                                                     in addition to the RTC oscillator controls.                */
2037 
2038     struct {
2039       __IOM uint32_t STOPXT     : 1;            /*!< [0..0] Stop the XT Oscillator to the RTC                                  */
2040       __IOM uint32_t STOPRC     : 1;            /*!< [1..1] Stop the LFRC Oscillator to the RTC                                */
2041             uint32_t            : 4;
2042       __IOM uint32_t FOS        : 1;            /*!< [6..6] Oscillator switch on failure function. If this is set,
2043                                                      then LFRC clock source will switch from XT to RC.                         */
2044       __IOM uint32_t OSEL       : 1;            /*!< [7..7] Selects the RTC oscillator (1 => LFRC, 0 => XT)                    */
2045       __IOM uint32_t ACAL       : 3;            /*!< [10..8] Autocalibration control. This selects the source to
2046                                                      be used in the autocalibration flow. This flow can also
2047                                                      be used to measure an internal clock against an external
2048                                                      clock source, with the external clock normally used as
2049                                                      the reference.                                                            */
2050             uint32_t            : 21;
2051     } OCTRL_b;
2052   } ;
2053 
2054   union {
2055     __IOM uint32_t CLKOUT;                      /*!< (@ 0x00000010) This register enables the CLKOUT to the GPIOs,
2056                                                                     and selects the clock source to that.                      */
2057 
2058     struct {
2059       __IOM uint32_t CKSEL      : 6;            /*!< [5..0] CLKOUT signal select                                               */
2060             uint32_t            : 1;
2061       __IOM uint32_t CKEN       : 1;            /*!< [7..7] Enable the CLKOUT signal                                           */
2062             uint32_t            : 24;
2063     } CLKOUT_b;
2064   } ;
2065 
2066   union {
2067     __IOM uint32_t CLKKEY;                      /*!< (@ 0x00000014) This controls the write access to the CCTRL register.
2068                                                                     This prevents customers from accidentally
2069                                                                     setting the HFRC clocks to be half of what
2070                                                                     they are set to.                                           */
2071 
2072     struct {
2073       __IOM uint32_t CLKKEY     : 32;           /*!< [31..0] Key register value.                                               */
2074     } CLKKEY_b;
2075   } ;
2076 
2077   union {
2078     __IOM uint32_t CCTRL;                       /*!< (@ 0x00000018) This register controls the main divider for HFRC
2079                                                                     clock. If this is set, all internal HFRC
2080                                                                     clock sources are divided by 2.                            */
2081 
2082     struct {
2083       __IOM uint32_t CORESEL    : 1;            /*!< [0..0] Core Clock divisor                                                 */
2084             uint32_t            : 31;
2085     } CCTRL_b;
2086   } ;
2087 
2088   union {
2089     __IOM uint32_t STATUS;                      /*!< (@ 0x0000001C) This register provides status to the XT oscillator
2090                                                                     and the source of the RTC.                                 */
2091 
2092     struct {
2093       __IOM uint32_t OMODE      : 1;            /*!< [0..0] Current RTC oscillator (1 => LFRC, 0 => XT). After an
2094                                                      RTC oscillator change, it may take up to 2 seconds for
2095                                                      this field to reflect the new oscillator.                                 */
2096       __IOM uint32_t OSCF       : 1;            /*!< [1..1] XT Oscillator is enabled but not oscillating                       */
2097             uint32_t            : 30;
2098     } STATUS_b;
2099   } ;
2100 
2101   union {
2102     __IOM uint32_t HFADJ;                       /*!< (@ 0x00000020) This register controls the HFRC adjustment. The
2103                                                                     HFRC clock can change with temperature and
2104                                                                     process corners, and this register controls
2105                                                                     the HFRC adjustment logic which reduces
2106                                                                     the fluctuations to the clock.                             */
2107 
2108     struct {
2109       __IOM uint32_t HFADJEN    : 1;            /*!< [0..0] HFRC adjustment control                                            */
2110       __IOM uint32_t HFADJCK    : 3;            /*!< [3..1] Repeat period for HFRC adjustment                                  */
2111             uint32_t            : 4;
2112       __IOM uint32_t HFXTADJ    : 12;           /*!< [19..8] Target HFRC adjustment value.                                     */
2113       __IOM uint32_t HFWARMUP   : 1;            /*!< [20..20] XT warm-up period for HFRC adjustment                            */
2114       __IOM uint32_t HFADJGAIN  : 3;            /*!< [23..21] Gain control for HFRC adjustment                                 */
2115             uint32_t            : 8;
2116     } HFADJ_b;
2117   } ;
2118   __IM  uint32_t  RESERVED;
2119 
2120   union {
2121     __IOM uint32_t CLOCKENSTAT;                 /*!< (@ 0x00000028) This register provides the enable status to all
2122                                                                     the peripheral clocks.                                     */
2123 
2124     struct {
2125       __IOM uint32_t CLOCKENSTAT : 32;          /*!< [31..0] Clock enable status                                               */
2126     } CLOCKENSTAT_b;
2127   } ;
2128 
2129   union {
2130     __IOM uint32_t CLOCKEN2STAT;                /*!< (@ 0x0000002C) This is a continuation of the clock enable status.         */
2131 
2132     struct {
2133       __IOM uint32_t CLOCKEN2STAT : 32;         /*!< [31..0] Clock enable status 2                                             */
2134     } CLOCKEN2STAT_b;
2135   } ;
2136 
2137   union {
2138     __IOM uint32_t CLOCKEN3STAT;                /*!< (@ 0x00000030) This is a continuation of the clock enable status.         */
2139 
2140     struct {
2141       __IOM uint32_t CLOCKEN3STAT : 32;         /*!< [31..0] Clock enable status 3                                             */
2142     } CLOCKEN3STAT_b;
2143   } ;
2144 
2145   union {
2146     __IOM uint32_t FREQCTRL;                    /*!< (@ 0x00000034) This register provides the burst control and
2147                                                                     burst status.                                              */
2148 
2149     struct {
2150       __IOM uint32_t BURSTREQ   : 1;            /*!< [0..0] Frequency Burst Enable Request                                     */
2151       __IOM uint32_t BURSTACK   : 1;            /*!< [1..1] Frequency Burst Request Acknowledge. Frequency burst
2152                                                      requested is always acknowledged whether burst is granted
2153                                                      or not depending on feature enable.                                       */
2154       __IOM uint32_t BURSTSTATUS : 1;           /*!< [2..2] This represents frequency burst status.                            */
2155             uint32_t            : 29;
2156     } FREQCTRL_b;
2157   } ;
2158   __IM  uint32_t  RESERVED1;
2159 
2160   union {
2161     __IOM uint32_t BLEBUCKTONADJ;               /*!< (@ 0x0000003C) This is the register control for BLE ton adjustment
2162                                                                     logic.                                                     */
2163 
2164     struct {
2165       __IOM uint32_t TONLOWTHRESHOLD : 10;      /*!< [9..0] TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz)
2166                                                      #15(47KHz) #53(12Khz) #14D(3Khz)                                          */
2167       __IOM uint32_t TONHIGHTHRESHOLD : 10;     /*!< [19..10] TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz)
2168                                                      #2A(47Khz) #A6(12Khz) #29A(3Khz)                                          */
2169       __IOM uint32_t TONADJUSTPERIOD : 2;       /*!< [21..20] TON ADJUST PERIOD                                                */
2170       __IOM uint32_t TONADJUSTEN : 1;           /*!< [22..22] TON ADJUST ENABLE                                                */
2171       __IOM uint32_t ZEROLENDETECTTRIM : 4;     /*!< [26..23] BLEBUCK ZERO LENGTH DETECT TRIM                                  */
2172       __IOM uint32_t ZEROLENDETECTEN : 1;       /*!< [27..27] BLEBUCK ZERO LENGTH DETECT ENABLE                                */
2173             uint32_t            : 4;
2174     } BLEBUCKTONADJ_b;
2175   } ;
2176   __IM  uint32_t  RESERVED2[48];
2177 
2178   union {
2179     __IOM uint32_t INTRPTEN;                    /*!< (@ 0x00000100) Set bits in this register to allow this module
2180                                                                     to generate the corresponding interrupt.                   */
2181 
2182     struct {
2183       __IOM uint32_t ACF        : 1;            /*!< [0..0] Autocalibration Fail interrupt                                     */
2184       __IOM uint32_t ACC        : 1;            /*!< [1..1] Autocalibration Complete interrupt                                 */
2185       __IOM uint32_t OF         : 1;            /*!< [2..2] XT Oscillator Fail interrupt                                       */
2186             uint32_t            : 29;
2187     } INTRPTEN_b;
2188   } ;
2189 
2190   union {
2191     __IOM uint32_t INTRPTSTAT;                  /*!< (@ 0x00000104) Read bits from this register to discover the
2192                                                                     cause of a recent interrupt.                               */
2193 
2194     struct {
2195       __IOM uint32_t ACF        : 1;            /*!< [0..0] Autocalibration Fail interrupt                                     */
2196       __IOM uint32_t ACC        : 1;            /*!< [1..1] Autocalibration Complete interrupt                                 */
2197       __IOM uint32_t OF         : 1;            /*!< [2..2] XT Oscillator Fail interrupt                                       */
2198             uint32_t            : 29;
2199     } INTRPTSTAT_b;
2200   } ;
2201 
2202   union {
2203     __IOM uint32_t INTRPTCLR;                   /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
2204                                                                     the interrupt status associated with that
2205                                                                     bit.                                                       */
2206 
2207     struct {
2208       __IOM uint32_t ACF        : 1;            /*!< [0..0] Autocalibration Fail interrupt                                     */
2209       __IOM uint32_t ACC        : 1;            /*!< [1..1] Autocalibration Complete interrupt                                 */
2210       __IOM uint32_t OF         : 1;            /*!< [2..2] XT Oscillator Fail interrupt                                       */
2211             uint32_t            : 29;
2212     } INTRPTCLR_b;
2213   } ;
2214 
2215   union {
2216     __IOM uint32_t INTRPTSET;                   /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
2217                                                                     generate an interrupt from this module.
2218                                                                     (Generally used for testing purposes).                     */
2219 
2220     struct {
2221       __IOM uint32_t ACF        : 1;            /*!< [0..0] Autocalibration Fail interrupt                                     */
2222       __IOM uint32_t ACC        : 1;            /*!< [1..1] Autocalibration Complete interrupt                                 */
2223       __IOM uint32_t OF         : 1;            /*!< [2..2] XT Oscillator Fail interrupt                                       */
2224             uint32_t            : 29;
2225     } INTRPTSET_b;
2226   } ;
2227 } CLKGEN_Type;                                  /*!< Size = 272 (0x110)                                                        */
2228 
2229 
2230 
2231 /* =========================================================================================================================== */
2232 /* ================                                          CTIMER                                           ================ */
2233 /* =========================================================================================================================== */
2234 
2235 
2236 /**
2237   * @brief Counter/Timer (CTIMER)
2238   */
2239 
2240 typedef struct {                                /*!< (@ 0x40008000) CTIMER Structure                                           */
2241 
2242   union {
2243     __IOM uint32_t TMR0;                        /*!< (@ 0x00000000) This register holds the running time or event
2244                                                                     count for CTIMER 0. This is either for each
2245                                                                     16 bit half or for the whole 32 bit count
2246                                                                     when the pair is linked. If the pair is
2247                                                                     not linked, they can be running on separate
2248                                                                     clocks and are completely independent.                     */
2249 
2250     struct {
2251       __IOM uint32_t CTTMRA0    : 16;           /*!< [15..0] Counter/Timer A0.                                                 */
2252       __IOM uint32_t CTTMRB0    : 16;           /*!< [31..16] Counter/Timer B0.                                                */
2253     } TMR0_b;
2254   } ;
2255 
2256   union {
2257     __IOM uint32_t CMPRA0;                      /*!< (@ 0x00000004) This contains the Compare limits for timer 0
2258                                                                     half A.                                                    */
2259 
2260     struct {
2261       __IOM uint32_t CMPR0A0    : 16;           /*!< [15..0] Counter/Timer A0 Compare Register 0. Holds the lower
2262                                                      limit for timer half A.                                                   */
2263       __IOM uint32_t CMPR1A0    : 16;           /*!< [31..16] Counter/Timer A0 Compare Register 1. Holds the upper
2264                                                      limit for timer half A.                                                   */
2265     } CMPRA0_b;
2266   } ;
2267 
2268   union {
2269     __IOM uint32_t CMPRB0;                      /*!< (@ 0x00000008) This contains the Compare limits for timer 0
2270                                                                     B half.                                                    */
2271 
2272     struct {
2273       __IOM uint32_t CMPR0B0    : 16;           /*!< [15..0] Counter/Timer B0 Compare Register 0. Holds the lower
2274                                                      limit for timer half B.                                                   */
2275       __IOM uint32_t CMPR1B0    : 16;           /*!< [31..16] Counter/Timer B0 Compare Register 1. Holds the upper
2276                                                      limit for timer half B.                                                   */
2277     } CMPRB0_b;
2278   } ;
2279 
2280   union {
2281     __IOM uint32_t CTRL0;                       /*!< (@ 0x0000000C) This includes the Control bit fields for both
2282                                                                     halves of timer 0.                                         */
2283 
2284     struct {
2285       __IOM uint32_t TMRA0EN    : 1;            /*!< [0..0] Counter/Timer A0 Enable bit.                                       */
2286       __IOM uint32_t TMRA0CLK   : 5;            /*!< [5..1] Counter/Timer A0 Clock Select.                                     */
2287       __IOM uint32_t TMRA0FN    : 3;            /*!< [8..6] Counter/Timer A0 Function Select.                                  */
2288       __IOM uint32_t TMRA0IE0   : 1;            /*!< [9..9] Counter/Timer A0 Interrupt Enable bit based on COMPR0.             */
2289       __IOM uint32_t TMRA0IE1   : 1;            /*!< [10..10] Counter/Timer A0 Interrupt Enable bit based on COMPR1.           */
2290       __IOM uint32_t TMRA0CLR   : 1;            /*!< [11..11] Counter/Timer A0 Clear bit.                                      */
2291       __IOM uint32_t TMRA0POL   : 1;            /*!< [12..12] Counter/Timer A0 output polarity.                                */
2292             uint32_t            : 3;
2293       __IOM uint32_t TMRB0EN    : 1;            /*!< [16..16] Counter/Timer B0 Enable bit.                                     */
2294       __IOM uint32_t TMRB0CLK   : 5;            /*!< [21..17] Counter/Timer B0 Clock Select.                                   */
2295       __IOM uint32_t TMRB0FN    : 3;            /*!< [24..22] Counter/Timer B0 Function Select.                                */
2296       __IOM uint32_t TMRB0IE0   : 1;            /*!< [25..25] Counter/Timer B0 Interrupt Enable bit for COMPR0.                */
2297       __IOM uint32_t TMRB0IE1   : 1;            /*!< [26..26] Counter/Timer B0 Interrupt Enable bit for COMPR1.                */
2298       __IOM uint32_t TMRB0CLR   : 1;            /*!< [27..27] Counter/Timer B0 Clear bit.                                      */
2299       __IOM uint32_t TMRB0POL   : 1;            /*!< [28..28] Counter/Timer B0 output polarity.                                */
2300             uint32_t            : 2;
2301       __IOM uint32_t CTLINK0    : 1;            /*!< [31..31] Counter/Timer A0/B0 Link bit.                                    */
2302     } CTRL0_b;
2303   } ;
2304   __IM  uint32_t  RESERVED;
2305 
2306   union {
2307     __IOM uint32_t CMPRAUXA0;                   /*!< (@ 0x00000014) Enhanced compare limits for timer half A. This
2308                                                                     is valid if timer 0 is set to function 4
2309                                                                     and function 5.                                            */
2310 
2311     struct {
2312       __IOM uint32_t CMPR2A0    : 16;           /*!< [15..0] Counter/Timer A0 Compare Register 2. Holds the lower
2313                                                      limit for timer half A.                                                   */
2314       __IOM uint32_t CMPR3A0    : 16;           /*!< [31..16] Counter/Timer A0 Compare Register 3. Holds the upper
2315                                                      limit for timer half A.                                                   */
2316     } CMPRAUXA0_b;
2317   } ;
2318 
2319   union {
2320     __IOM uint32_t CMPRAUXB0;                   /*!< (@ 0x00000018) Enhanced compare limits for timer half B. This
2321                                                                     is valid if timer 0 is set to function 4
2322                                                                     and function 5.                                            */
2323 
2324     struct {
2325       __IOM uint32_t CMPR2B0    : 16;           /*!< [15..0] Counter/Timer B0 Compare Register 2. Holds the lower
2326                                                      limit for timer half B.                                                   */
2327       __IOM uint32_t CMPR3B0    : 16;           /*!< [31..16] Counter/Timer B0 Compare Register 3. Holds the upper
2328                                                      limit for timer half B.                                                   */
2329     } CMPRAUXB0_b;
2330   } ;
2331 
2332   union {
2333     __IOM uint32_t AUX0;                        /*!< (@ 0x0000001C) Control bit fields for both halves of timer 0.             */
2334 
2335     struct {
2336       __IOM uint32_t TMRA0LMT   : 7;            /*!< [6..0] Counter/Timer A0 Pattern Limit Count.                              */
2337       __IOM uint32_t TMRA0TRIG  : 4;            /*!< [10..7] Counter/Timer A0 Trigger Select.                                  */
2338       __IOM uint32_t TMRA0NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2339       __IOM uint32_t TMRA0TINV  : 1;            /*!< [12..12] Counter/Timer A0 Invert on trigger.                              */
2340       __IOM uint32_t TMRA0POL23 : 1;            /*!< [13..13] Counter/Timer A0 Upper output polarity                           */
2341       __IOM uint32_t TMRA0EN23  : 1;            /*!< [14..14] Counter/Timer A0 Upper compare enable.                           */
2342             uint32_t            : 1;
2343       __IOM uint32_t TMRB0LMT   : 6;            /*!< [21..16] Counter/Timer B0 Pattern Limit Count.                            */
2344             uint32_t            : 1;
2345       __IOM uint32_t TMRB0TRIG  : 4;            /*!< [26..23] Counter/Timer B0 Trigger Select.                                 */
2346       __IOM uint32_t TMRB0NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2347       __IOM uint32_t TMRB0TINV  : 1;            /*!< [28..28] Counter/Timer B0 Invert on trigger.                              */
2348       __IOM uint32_t TMRB0POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2349       __IOM uint32_t TMRB0EN23  : 1;            /*!< [30..30] Counter/Timer B0 Upper compare enable.                           */
2350             uint32_t            : 1;
2351     } AUX0_b;
2352   } ;
2353 
2354   union {
2355     __IOM uint32_t TMR1;                        /*!< (@ 0x00000020) This register holds the running time or event
2356                                                                     count for CTIMER 1. This is either for each
2357                                                                     16 bit half or for the whole 32 bit count
2358                                                                     when the pair is linked. If the pair is
2359                                                                     not linked, they can be running on separate
2360                                                                     clocks and are completely independent.                     */
2361 
2362     struct {
2363       __IOM uint32_t CTTMRA1    : 16;           /*!< [15..0] Counter/Timer A1.                                                 */
2364       __IOM uint32_t CTTMRB1    : 16;           /*!< [31..16] Counter/Timer B1.                                                */
2365     } TMR1_b;
2366   } ;
2367 
2368   union {
2369     __IOM uint32_t CMPRA1;                      /*!< (@ 0x00000024) This contains the Compare limits for timer 1
2370                                                                     A half.                                                    */
2371 
2372     struct {
2373       __IOM uint32_t CMPR0A1    : 16;           /*!< [15..0] Counter/Timer A1 Compare Register 0.                              */
2374       __IOM uint32_t CMPR1A1    : 16;           /*!< [31..16] Counter/Timer A1 Compare Register 1.                             */
2375     } CMPRA1_b;
2376   } ;
2377 
2378   union {
2379     __IOM uint32_t CMPRB1;                      /*!< (@ 0x00000028) This contains the Compare limits for timer 1
2380                                                                     B half.                                                    */
2381 
2382     struct {
2383       __IOM uint32_t CMPR0B1    : 16;           /*!< [15..0] Counter/Timer B1 Compare Register 0.                              */
2384       __IOM uint32_t CMPR1B1    : 16;           /*!< [31..16] Counter/Timer B1 Compare Register 1.                             */
2385     } CMPRB1_b;
2386   } ;
2387 
2388   union {
2389     __IOM uint32_t CTRL1;                       /*!< (@ 0x0000002C) This includes the Control bit fields for both
2390                                                                     halves of timer 1.                                         */
2391 
2392     struct {
2393       __IOM uint32_t TMRA1EN    : 1;            /*!< [0..0] Counter/Timer A1 Enable bit.                                       */
2394       __IOM uint32_t TMRA1CLK   : 5;            /*!< [5..1] Counter/Timer A1 Clock Select.                                     */
2395       __IOM uint32_t TMRA1FN    : 3;            /*!< [8..6] Counter/Timer A1 Function Select.                                  */
2396       __IOM uint32_t TMRA1IE0   : 1;            /*!< [9..9] Counter/Timer A1 Interrupt Enable bit based on COMPR0.             */
2397       __IOM uint32_t TMRA1IE1   : 1;            /*!< [10..10] Counter/Timer A1 Interrupt Enable bit based on COMPR1.           */
2398       __IOM uint32_t TMRA1CLR   : 1;            /*!< [11..11] Counter/Timer A1 Clear bit.                                      */
2399       __IOM uint32_t TMRA1POL   : 1;            /*!< [12..12] Counter/Timer A1 output polarity.                                */
2400             uint32_t            : 3;
2401       __IOM uint32_t TMRB1EN    : 1;            /*!< [16..16] Counter/Timer B1 Enable bit.                                     */
2402       __IOM uint32_t TMRB1CLK   : 5;            /*!< [21..17] Counter/Timer B1 Clock Select.                                   */
2403       __IOM uint32_t TMRB1FN    : 3;            /*!< [24..22] Counter/Timer B1 Function Select.                                */
2404       __IOM uint32_t TMRB1IE0   : 1;            /*!< [25..25] Counter/Timer B1 Interrupt Enable bit for COMPR0.                */
2405       __IOM uint32_t TMRB1IE1   : 1;            /*!< [26..26] Counter/Timer B1 Interrupt Enable bit for COMPR1.                */
2406       __IOM uint32_t TMRB1CLR   : 1;            /*!< [27..27] Counter/Timer B1 Clear bit.                                      */
2407       __IOM uint32_t TMRB1POL   : 1;            /*!< [28..28] Counter/Timer B1 output polarity.                                */
2408             uint32_t            : 2;
2409       __IOM uint32_t CTLINK1    : 1;            /*!< [31..31] Counter/Timer A1/B1 Link bit.                                    */
2410     } CTRL1_b;
2411   } ;
2412   __IM  uint32_t  RESERVED1;
2413 
2414   union {
2415     __IOM uint32_t CMPRAUXA1;                   /*!< (@ 0x00000034) Enhanced compare limits for timer half A. This
2416                                                                     is valid if timer 1 is set to function 4
2417                                                                     and function 5.                                            */
2418 
2419     struct {
2420       __IOM uint32_t CMPR2A1    : 16;           /*!< [15..0] Counter/Timer A1 Compare Register 2. Holds the lower
2421                                                      limit for timer half A.                                                   */
2422       __IOM uint32_t CMPR3A1    : 16;           /*!< [31..16] Counter/Timer A1 Compare Register 3. Holds the upper
2423                                                      limit for timer half A.                                                   */
2424     } CMPRAUXA1_b;
2425   } ;
2426 
2427   union {
2428     __IOM uint32_t CMPRAUXB1;                   /*!< (@ 0x00000038) Enhanced compare limits for timer half B. This
2429                                                                     is valid if timer 1 is set to function 4
2430                                                                     and function 5.                                            */
2431 
2432     struct {
2433       __IOM uint32_t CMPR2B1    : 16;           /*!< [15..0] Counter/Timer B1 Compare Register 2. Holds the lower
2434                                                      limit for timer half B.                                                   */
2435       __IOM uint32_t CMPR3B1    : 16;           /*!< [31..16] Counter/Timer B1 Compare Register 3. Holds the upper
2436                                                      limit for timer half B.                                                   */
2437     } CMPRAUXB1_b;
2438   } ;
2439 
2440   union {
2441     __IOM uint32_t AUX1;                        /*!< (@ 0x0000003C) Control bit fields for both halves of timer 0.             */
2442 
2443     struct {
2444       __IOM uint32_t TMRA1LMT   : 7;            /*!< [6..0] Counter/Timer A1 Pattern Limit Count.                              */
2445       __IOM uint32_t TMRA1TRIG  : 4;            /*!< [10..7] Counter/Timer A1 Trigger Select.                                  */
2446       __IOM uint32_t TMRA1NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2447       __IOM uint32_t TMRA1TINV  : 1;            /*!< [12..12] Counter/Timer A1 Invert on trigger.                              */
2448       __IOM uint32_t TMRA1POL23 : 1;            /*!< [13..13] Counter/Timer A1 Upper output polarity                           */
2449       __IOM uint32_t TMRA1EN23  : 1;            /*!< [14..14] Counter/Timer A1 Upper compare enable.                           */
2450             uint32_t            : 1;
2451       __IOM uint32_t TMRB1LMT   : 6;            /*!< [21..16] Counter/Timer B1 Pattern Limit Count.                            */
2452             uint32_t            : 1;
2453       __IOM uint32_t TMRB1TRIG  : 4;            /*!< [26..23] Counter/Timer B1 Trigger Select.                                 */
2454       __IOM uint32_t TMRB1NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2455       __IOM uint32_t TMRB1TINV  : 1;            /*!< [28..28] Counter/Timer B1 Invert on trigger.                              */
2456       __IOM uint32_t TMRB1POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2457       __IOM uint32_t TMRB1EN23  : 1;            /*!< [30..30] Counter/Timer B1 Upper compare enable.                           */
2458             uint32_t            : 1;
2459     } AUX1_b;
2460   } ;
2461 
2462   union {
2463     __IOM uint32_t TMR2;                        /*!< (@ 0x00000040) This register holds the running time or event
2464                                                                     count for CTIMER 2. This is either for each
2465                                                                     16 bit half or for the whole 32 bit count
2466                                                                     when the pair is linked. If the pair is
2467                                                                     not linked, they can be running on separate
2468                                                                     clocks and are completely independent.                     */
2469 
2470     struct {
2471       __IOM uint32_t CTTMRA2    : 16;           /*!< [15..0] Counter/Timer A2.                                                 */
2472       __IOM uint32_t CTTMRB2    : 16;           /*!< [31..16] Counter/Timer B2.                                                */
2473     } TMR2_b;
2474   } ;
2475 
2476   union {
2477     __IOM uint32_t CMPRA2;                      /*!< (@ 0x00000044) This register holds the compare limits for timer
2478                                                                     2 A half.                                                  */
2479 
2480     struct {
2481       __IOM uint32_t CMPR0A2    : 16;           /*!< [15..0] Counter/Timer A2 Compare Register 0.                              */
2482       __IOM uint32_t CMPR1A2    : 16;           /*!< [31..16] Counter/Timer A2 Compare Register 1.                             */
2483     } CMPRA2_b;
2484   } ;
2485 
2486   union {
2487     __IOM uint32_t CMPRB2;                      /*!< (@ 0x00000048) This register holds the compare limits for timer
2488                                                                     2 B half.                                                  */
2489 
2490     struct {
2491       __IOM uint32_t CMPR0B2    : 16;           /*!< [15..0] Counter/Timer B2 Compare Register 0.                              */
2492       __IOM uint32_t CMPR1B2    : 16;           /*!< [31..16] Counter/Timer B2 Compare Register 1.                             */
2493     } CMPRB2_b;
2494   } ;
2495 
2496   union {
2497     __IOM uint32_t CTRL2;                       /*!< (@ 0x0000004C) This register holds the control bit fields for
2498                                                                     both halves of timer 2.                                    */
2499 
2500     struct {
2501       __IOM uint32_t TMRA2EN    : 1;            /*!< [0..0] Counter/Timer A2 Enable bit.                                       */
2502       __IOM uint32_t TMRA2CLK   : 5;            /*!< [5..1] Counter/Timer A2 Clock Select.                                     */
2503       __IOM uint32_t TMRA2FN    : 3;            /*!< [8..6] Counter/Timer A2 Function Select.                                  */
2504       __IOM uint32_t TMRA2IE0   : 1;            /*!< [9..9] Counter/Timer A2 Interrupt Enable bit based on COMPR0.             */
2505       __IOM uint32_t TMRA2IE1   : 1;            /*!< [10..10] Counter/Timer A2 Interrupt Enable bit based on COMPR1.           */
2506       __IOM uint32_t TMRA2CLR   : 1;            /*!< [11..11] Counter/Timer A2 Clear bit.                                      */
2507       __IOM uint32_t TMRA2POL   : 1;            /*!< [12..12] Counter/Timer A2 output polarity.                                */
2508             uint32_t            : 3;
2509       __IOM uint32_t TMRB2EN    : 1;            /*!< [16..16] Counter/Timer B2 Enable bit.                                     */
2510       __IOM uint32_t TMRB2CLK   : 5;            /*!< [21..17] Counter/Timer B2 Clock Select.                                   */
2511       __IOM uint32_t TMRB2FN    : 3;            /*!< [24..22] Counter/Timer B2 Function Select.                                */
2512       __IOM uint32_t TMRB2IE0   : 1;            /*!< [25..25] Counter/Timer B2 Interrupt Enable bit for COMPR0.                */
2513       __IOM uint32_t TMRB2IE1   : 1;            /*!< [26..26] Counter/Timer B2 Interrupt Enable bit for COMPR1.                */
2514       __IOM uint32_t TMRB2CLR   : 1;            /*!< [27..27] Counter/Timer B2 Clear bit.                                      */
2515       __IOM uint32_t TMRB2POL   : 1;            /*!< [28..28] Counter/Timer B2 output polarity.                                */
2516             uint32_t            : 2;
2517       __IOM uint32_t CTLINK2    : 1;            /*!< [31..31] Counter/Timer A2/B2 Link bit.                                    */
2518     } CTRL2_b;
2519   } ;
2520   __IM  uint32_t  RESERVED2;
2521 
2522   union {
2523     __IOM uint32_t CMPRAUXA2;                   /*!< (@ 0x00000054) Enhanced compare limits for timer half A.                  */
2524 
2525     struct {
2526       __IOM uint32_t CMPR2A2    : 16;           /*!< [15..0] Counter/Timer A2 Compare Register 2. Holds the lower
2527                                                      limit for timer half A.                                                   */
2528       __IOM uint32_t CMPR3A2    : 16;           /*!< [31..16] Counter/Timer A2 Compare Register 3. Holds the upper
2529                                                      limit for timer half A.                                                   */
2530     } CMPRAUXA2_b;
2531   } ;
2532 
2533   union {
2534     __IOM uint32_t CMPRAUXB2;                   /*!< (@ 0x00000058) Enhanced compare limits for timer half B.                  */
2535 
2536     struct {
2537       __IOM uint32_t CMPR2B2    : 16;           /*!< [15..0] Counter/Timer B2 Compare Register 2. Holds the lower
2538                                                      limit for timer half B.                                                   */
2539       __IOM uint32_t CMPR3B2    : 16;           /*!< [31..16] Counter/Timer B2 Compare Register 3. Holds the upper
2540                                                      limit for timer half B.                                                   */
2541     } CMPRAUXB2_b;
2542   } ;
2543 
2544   union {
2545     __IOM uint32_t AUX2;                        /*!< (@ 0x0000005C) Control bit fields for both halves of timer 0.             */
2546 
2547     struct {
2548       __IOM uint32_t TMRA2LMT   : 7;            /*!< [6..0] Counter/Timer A2 Pattern Limit Count.                              */
2549       __IOM uint32_t TMRA2TRIG  : 4;            /*!< [10..7] Counter/Timer A2 Trigger Select.                                  */
2550       __IOM uint32_t TMRA2NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2551       __IOM uint32_t TMRA2TINV  : 1;            /*!< [12..12] Counter/Timer A2 Invert on trigger.                              */
2552       __IOM uint32_t TMRA2POL23 : 1;            /*!< [13..13] Counter/Timer A2 Upper output polarity                           */
2553       __IOM uint32_t TMRA2EN23  : 1;            /*!< [14..14] Counter/Timer A2 Upper compare enable.                           */
2554             uint32_t            : 1;
2555       __IOM uint32_t TMRB2LMT   : 6;            /*!< [21..16] Counter/Timer B2 Pattern Limit Count.                            */
2556             uint32_t            : 1;
2557       __IOM uint32_t TMRB2TRIG  : 4;            /*!< [26..23] Counter/Timer B2 Trigger Select.                                 */
2558       __IOM uint32_t TMRB2NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2559       __IOM uint32_t TMRB2TINV  : 1;            /*!< [28..28] Counter/Timer B2 Invert on trigger.                              */
2560       __IOM uint32_t TMRB2POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2561       __IOM uint32_t TMRB2EN23  : 1;            /*!< [30..30] Counter/Timer B2 Upper compare enable.                           */
2562             uint32_t            : 1;
2563     } AUX2_b;
2564   } ;
2565 
2566   union {
2567     __IOM uint32_t TMR3;                        /*!< (@ 0x00000060) Counter/Timer 3                                            */
2568 
2569     struct {
2570       __IOM uint32_t CTTMRA3    : 16;           /*!< [15..0] Counter/Timer A3.                                                 */
2571       __IOM uint32_t CTTMRB3    : 16;           /*!< [31..16] Counter/Timer B3.                                                */
2572     } TMR3_b;
2573   } ;
2574 
2575   union {
2576     __IOM uint32_t CMPRA3;                      /*!< (@ 0x00000064) This register holds the compare limits for timer
2577                                                                     half A.                                                    */
2578 
2579     struct {
2580       __IOM uint32_t CMPR0A3    : 16;           /*!< [15..0] Counter/Timer A3 Compare Register 0.                              */
2581       __IOM uint32_t CMPR1A3    : 16;           /*!< [31..16] Counter/Timer A3 Compare Register 1.                             */
2582     } CMPRA3_b;
2583   } ;
2584 
2585   union {
2586     __IOM uint32_t CMPRB3;                      /*!< (@ 0x00000068) This register holds the compare limits for timer
2587                                                                     half B.                                                    */
2588 
2589     struct {
2590       __IOM uint32_t CMPR0B3    : 16;           /*!< [15..0] Counter/Timer B3 Compare Register 0.                              */
2591       __IOM uint32_t CMPR1B3    : 16;           /*!< [31..16] Counter/Timer B3 Compare Register 1.                             */
2592     } CMPRB3_b;
2593   } ;
2594 
2595   union {
2596     __IOM uint32_t CTRL3;                       /*!< (@ 0x0000006C) This register holds the control bit fields for
2597                                                                     both halves of timer 3.                                    */
2598 
2599     struct {
2600       __IOM uint32_t TMRA3EN    : 1;            /*!< [0..0] Counter/Timer A3 Enable bit.                                       */
2601       __IOM uint32_t TMRA3CLK   : 5;            /*!< [5..1] Counter/Timer A3 Clock Select.                                     */
2602       __IOM uint32_t TMRA3FN    : 3;            /*!< [8..6] Counter/Timer A3 Function Select.                                  */
2603       __IOM uint32_t TMRA3IE0   : 1;            /*!< [9..9] Counter/Timer A3 Interrupt Enable bit based on COMPR0.             */
2604       __IOM uint32_t TMRA3IE1   : 1;            /*!< [10..10] Counter/Timer A3 Interrupt Enable bit based on COMPR1.           */
2605       __IOM uint32_t TMRA3CLR   : 1;            /*!< [11..11] Counter/Timer A3 Clear bit.                                      */
2606       __IOM uint32_t TMRA3POL   : 1;            /*!< [12..12] Counter/Timer A3 output polarity.                                */
2607             uint32_t            : 2;
2608       __IOM uint32_t ADCEN      : 1;            /*!< [15..15] Special Timer A3 enable for ADC function.                        */
2609       __IOM uint32_t TMRB3EN    : 1;            /*!< [16..16] Counter/Timer B3 Enable bit.                                     */
2610       __IOM uint32_t TMRB3CLK   : 5;            /*!< [21..17] Counter/Timer B3 Clock Select.                                   */
2611       __IOM uint32_t TMRB3FN    : 3;            /*!< [24..22] Counter/Timer B3 Function Select.                                */
2612       __IOM uint32_t TMRB3IE0   : 1;            /*!< [25..25] Counter/Timer B3 Interrupt Enable bit for COMPR0.                */
2613       __IOM uint32_t TMRB3IE1   : 1;            /*!< [26..26] Counter/Timer B3 Interrupt Enable bit for COMPR1.                */
2614       __IOM uint32_t TMRB3CLR   : 1;            /*!< [27..27] Counter/Timer B3 Clear bit.                                      */
2615       __IOM uint32_t TMRB3POL   : 1;            /*!< [28..28] Counter/Timer B3 output polarity.                                */
2616             uint32_t            : 2;
2617       __IOM uint32_t CTLINK3    : 1;            /*!< [31..31] Counter/Timer A3/B3 Link bit.                                    */
2618     } CTRL3_b;
2619   } ;
2620   __IM  uint32_t  RESERVED3;
2621 
2622   union {
2623     __IOM uint32_t CMPRAUXA3;                   /*!< (@ 0x00000074) Enhanced compare limits for timer half A.                  */
2624 
2625     struct {
2626       __IOM uint32_t CMPR2A3    : 16;           /*!< [15..0] Counter/Timer A3 Compare Register 2. Holds the lower
2627                                                      limit for timer half A.                                                   */
2628       __IOM uint32_t CMPR3A3    : 16;           /*!< [31..16] Counter/Timer A3 Compare Register 3. Holds the upper
2629                                                      limit for timer half A.                                                   */
2630     } CMPRAUXA3_b;
2631   } ;
2632 
2633   union {
2634     __IOM uint32_t CMPRAUXB3;                   /*!< (@ 0x00000078) Enhanced compare limits for timer half B.                  */
2635 
2636     struct {
2637       __IOM uint32_t CMPR2B3    : 16;           /*!< [15..0] Counter/Timer B3 Compare Register 2. Holds the lower
2638                                                      limit for timer half B.                                                   */
2639       __IOM uint32_t CMPR3B3    : 16;           /*!< [31..16] Counter/Timer B3 Compare Register 3. Holds the upper
2640                                                      limit for timer half B.                                                   */
2641     } CMPRAUXB3_b;
2642   } ;
2643 
2644   union {
2645     __IOM uint32_t AUX3;                        /*!< (@ 0x0000007C) Control bit fields for both halves of timer 0.             */
2646 
2647     struct {
2648       __IOM uint32_t TMRA3LMT   : 7;            /*!< [6..0] Counter/Timer A3 Pattern Limit Count.                              */
2649       __IOM uint32_t TMRA3TRIG  : 4;            /*!< [10..7] Counter/Timer A3 Trigger Select.                                  */
2650       __IOM uint32_t TMRA3NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2651       __IOM uint32_t TMRA3TINV  : 1;            /*!< [12..12] Counter/Timer A3 Invert on trigger.                              */
2652       __IOM uint32_t TMRA3POL23 : 1;            /*!< [13..13] Counter/Timer A3 Upper output polarity                           */
2653       __IOM uint32_t TMRA3EN23  : 1;            /*!< [14..14] Counter/Timer A3 Upper compare enable.                           */
2654             uint32_t            : 1;
2655       __IOM uint32_t TMRB3LMT   : 6;            /*!< [21..16] Counter/Timer B3 Pattern Limit Count.                            */
2656             uint32_t            : 1;
2657       __IOM uint32_t TMRB3TRIG  : 4;            /*!< [26..23] Counter/Timer B3 Trigger Select.                                 */
2658       __IOM uint32_t TMRB3NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2659       __IOM uint32_t TMRB3TINV  : 1;            /*!< [28..28] Counter/Timer B3 Invert on trigger.                              */
2660       __IOM uint32_t TMRB3POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2661       __IOM uint32_t TMRB3EN23  : 1;            /*!< [30..30] Counter/Timer B3 Upper compare enable.                           */
2662             uint32_t            : 1;
2663     } AUX3_b;
2664   } ;
2665 
2666   union {
2667     __IOM uint32_t TMR4;                        /*!< (@ 0x00000080) This register holds the running time or event
2668                                                                     count, either for each 16 bit half or for
2669                                                                     the whole 32 bit count when the pair is
2670                                                                     linked.                                                    */
2671 
2672     struct {
2673       __IOM uint32_t CTTMRA4    : 16;           /*!< [15..0] Counter/Timer A4.                                                 */
2674       __IOM uint32_t CTTMRB4    : 16;           /*!< [31..16] Counter/Timer B4.                                                */
2675     } TMR4_b;
2676   } ;
2677 
2678   union {
2679     __IOM uint32_t CMPRA4;                      /*!< (@ 0x00000084) Compare limits for timer half A.                           */
2680 
2681     struct {
2682       __IOM uint32_t CMPR0A4    : 16;           /*!< [15..0] Counter/Timer A4 Compare Register 0. Holds the lower
2683                                                      limit for timer half A.                                                   */
2684       __IOM uint32_t CMPR1A4    : 16;           /*!< [31..16] Counter/Timer A4 Compare Register 1. Holds the upper
2685                                                      limit for timer half A.                                                   */
2686     } CMPRA4_b;
2687   } ;
2688 
2689   union {
2690     __IOM uint32_t CMPRB4;                      /*!< (@ 0x00000088) Compare limits for timer half B.                           */
2691 
2692     struct {
2693       __IOM uint32_t CMPR0B4    : 16;           /*!< [15..0] Counter/Timer B4 Compare Register 0. Holds the lower
2694                                                      limit for timer half B.                                                   */
2695       __IOM uint32_t CMPR1B4    : 16;           /*!< [31..16] Counter/Timer B4 Compare Register 1. Holds the upper
2696                                                      limit for timer half B.                                                   */
2697     } CMPRB4_b;
2698   } ;
2699 
2700   union {
2701     __IOM uint32_t CTRL4;                       /*!< (@ 0x0000008C) Control bit fields for both halves of timer 4.             */
2702 
2703     struct {
2704       __IOM uint32_t TMRA4EN    : 1;            /*!< [0..0] Counter/Timer A4 Enable bit.                                       */
2705       __IOM uint32_t TMRA4CLK   : 5;            /*!< [5..1] Counter/Timer A4 Clock Select.                                     */
2706       __IOM uint32_t TMRA4FN    : 3;            /*!< [8..6] Counter/Timer A4 Function Select.                                  */
2707       __IOM uint32_t TMRA4IE0   : 1;            /*!< [9..9] Counter/Timer A4 Interrupt Enable bit based on COMPR0.             */
2708       __IOM uint32_t TMRA4IE1   : 1;            /*!< [10..10] Counter/Timer A4 Interrupt Enable bit based on COMPR1.           */
2709       __IOM uint32_t TMRA4CLR   : 1;            /*!< [11..11] Counter/Timer A4 Clear bit.                                      */
2710       __IOM uint32_t TMRA4POL   : 1;            /*!< [12..12] Counter/Timer A4 output polarity.                                */
2711             uint32_t            : 3;
2712       __IOM uint32_t TMRB4EN    : 1;            /*!< [16..16] Counter/Timer B4 Enable bit.                                     */
2713       __IOM uint32_t TMRB4CLK   : 5;            /*!< [21..17] Counter/Timer B4 Clock Select.                                   */
2714       __IOM uint32_t TMRB4FN    : 3;            /*!< [24..22] Counter/Timer B4 Function Select.                                */
2715       __IOM uint32_t TMRB4IE0   : 1;            /*!< [25..25] Counter/Timer B4 Interrupt Enable bit for COMPR0.                */
2716       __IOM uint32_t TMRB4IE1   : 1;            /*!< [26..26] Counter/Timer B4 Interrupt Enable bit for COMPR1.                */
2717       __IOM uint32_t TMRB4CLR   : 1;            /*!< [27..27] Counter/Timer B4 Clear bit.                                      */
2718       __IOM uint32_t TMRB4POL   : 1;            /*!< [28..28] Counter/Timer B4 output polarity.                                */
2719             uint32_t            : 2;
2720       __IOM uint32_t CTLINK4    : 1;            /*!< [31..31] Counter/Timer A4/B4 Link bit.                                    */
2721     } CTRL4_b;
2722   } ;
2723   __IM  uint32_t  RESERVED4;
2724 
2725   union {
2726     __IOM uint32_t CMPRAUXA4;                   /*!< (@ 0x00000094) Enhanced compare limits for timer half A.                  */
2727 
2728     struct {
2729       __IOM uint32_t CMPR2A4    : 16;           /*!< [15..0] Counter/Timer A4 Compare Register 2. Holds the lower
2730                                                      limit for timer half A.                                                   */
2731       __IOM uint32_t CMPR3A4    : 16;           /*!< [31..16] Counter/Timer A4 Compare Register 3. Holds the upper
2732                                                      limit for timer half A.                                                   */
2733     } CMPRAUXA4_b;
2734   } ;
2735 
2736   union {
2737     __IOM uint32_t CMPRAUXB4;                   /*!< (@ 0x00000098) Enhanced compare limits for timer half B.                  */
2738 
2739     struct {
2740       __IOM uint32_t CMPR2B4    : 16;           /*!< [15..0] Counter/Timer B4 Compare Register 2. Holds the lower
2741                                                      limit for timer half B.                                                   */
2742       __IOM uint32_t CMPR3B4    : 16;           /*!< [31..16] Counter/Timer B4 Compare Register 3. Holds the upper
2743                                                      limit for timer half B.                                                   */
2744     } CMPRAUXB4_b;
2745   } ;
2746 
2747   union {
2748     __IOM uint32_t AUX4;                        /*!< (@ 0x0000009C) Control bit fields for both halves of timer 4.             */
2749 
2750     struct {
2751       __IOM uint32_t TMRA4LMT   : 7;            /*!< [6..0] Counter/Timer A4 Pattern Limit Count.                              */
2752       __IOM uint32_t TMRA4TRIG  : 4;            /*!< [10..7] Counter/Timer A4 Trigger Select.                                  */
2753       __IOM uint32_t TMRA4NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2754       __IOM uint32_t TMRA4TINV  : 1;            /*!< [12..12] Counter/Timer A4 Invert on trigger.                              */
2755       __IOM uint32_t TMRA4POL23 : 1;            /*!< [13..13] Counter/Timer A4 Upper output polarity                           */
2756       __IOM uint32_t TMRA4EN23  : 1;            /*!< [14..14] Counter/Timer A4 Upper compare enable.                           */
2757             uint32_t            : 1;
2758       __IOM uint32_t TMRB4LMT   : 6;            /*!< [21..16] Counter/Timer B4 Pattern Limit Count.                            */
2759             uint32_t            : 1;
2760       __IOM uint32_t TMRB4TRIG  : 4;            /*!< [26..23] Counter/Timer B4 Trigger Select.                                 */
2761       __IOM uint32_t TMRB4NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2762       __IOM uint32_t TMRB4TINV  : 1;            /*!< [28..28] Counter/Timer B4 Invert on trigger.                              */
2763       __IOM uint32_t TMRB4POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2764       __IOM uint32_t TMRB4EN23  : 1;            /*!< [30..30] Counter/Timer B4 Upper compare enable.                           */
2765             uint32_t            : 1;
2766     } AUX4_b;
2767   } ;
2768 
2769   union {
2770     __IOM uint32_t TMR5;                        /*!< (@ 0x000000A0) This register holds the running time or event
2771                                                                     count, either for each 16 bit half or for
2772                                                                     the whole 32 bit count when the pair is
2773                                                                     linked.                                                    */
2774 
2775     struct {
2776       __IOM uint32_t CTTMRA5    : 16;           /*!< [15..0] Counter/Timer A5.                                                 */
2777       __IOM uint32_t CTTMRB5    : 16;           /*!< [31..16] Counter/Timer B5.                                                */
2778     } TMR5_b;
2779   } ;
2780 
2781   union {
2782     __IOM uint32_t CMPRA5;                      /*!< (@ 0x000000A4) This register holds the compare limits for timer
2783                                                                     half A.                                                    */
2784 
2785     struct {
2786       __IOM uint32_t CMPR0A5    : 16;           /*!< [15..0] Counter/Timer A5 Compare Register 0.                              */
2787       __IOM uint32_t CMPR1A5    : 16;           /*!< [31..16] Counter/Timer A5 Compare Register 1.                             */
2788     } CMPRA5_b;
2789   } ;
2790 
2791   union {
2792     __IOM uint32_t CMPRB5;                      /*!< (@ 0x000000A8) This register holds the compare limits for timer
2793                                                                     half B.                                                    */
2794 
2795     struct {
2796       __IOM uint32_t CMPR0B5    : 16;           /*!< [15..0] Counter/Timer B5 Compare Register 0.                              */
2797       __IOM uint32_t CMPR1B5    : 16;           /*!< [31..16] Counter/Timer B5 Compare Register 1.                             */
2798     } CMPRB5_b;
2799   } ;
2800 
2801   union {
2802     __IOM uint32_t CTRL5;                       /*!< (@ 0x000000AC) Control bit fields for both halves of timer 0.             */
2803 
2804     struct {
2805       __IOM uint32_t TMRA5EN    : 1;            /*!< [0..0] Counter/Timer A5 Enable bit.                                       */
2806       __IOM uint32_t TMRA5CLK   : 5;            /*!< [5..1] Counter/Timer A5 Clock Select.                                     */
2807       __IOM uint32_t TMRA5FN    : 3;            /*!< [8..6] Counter/Timer A5 Function Select.                                  */
2808       __IOM uint32_t TMRA5IE0   : 1;            /*!< [9..9] Counter/Timer A5 Interrupt Enable bit based on COMPR0.             */
2809       __IOM uint32_t TMRA5IE1   : 1;            /*!< [10..10] Counter/Timer A5 Interrupt Enable bit based on COMPR1.           */
2810       __IOM uint32_t TMRA5CLR   : 1;            /*!< [11..11] Counter/Timer A5 Clear bit.                                      */
2811       __IOM uint32_t TMRA5POL   : 1;            /*!< [12..12] Counter/Timer A5 output polarity.                                */
2812             uint32_t            : 3;
2813       __IOM uint32_t TMRB5EN    : 1;            /*!< [16..16] Counter/Timer B5 Enable bit.                                     */
2814       __IOM uint32_t TMRB5CLK   : 5;            /*!< [21..17] Counter/Timer B5 Clock Select.                                   */
2815       __IOM uint32_t TMRB5FN    : 3;            /*!< [24..22] Counter/Timer B5 Function Select.                                */
2816       __IOM uint32_t TMRB5IE0   : 1;            /*!< [25..25] Counter/Timer B5 Interrupt Enable bit for COMPR0.                */
2817       __IOM uint32_t TMRB5IE1   : 1;            /*!< [26..26] Counter/Timer B5 Interrupt Enable bit for COMPR1.                */
2818       __IOM uint32_t TMRB5CLR   : 1;            /*!< [27..27] Counter/Timer B5 Clear bit.                                      */
2819       __IOM uint32_t TMRB5POL   : 1;            /*!< [28..28] Counter/Timer B5 output polarity.                                */
2820             uint32_t            : 2;
2821       __IOM uint32_t CTLINK5    : 1;            /*!< [31..31] Counter/Timer A5/B5 Link bit.                                    */
2822     } CTRL5_b;
2823   } ;
2824   __IM  uint32_t  RESERVED5;
2825 
2826   union {
2827     __IOM uint32_t CMPRAUXA5;                   /*!< (@ 0x000000B4) Enhanced compare limits for timer half A.                  */
2828 
2829     struct {
2830       __IOM uint32_t CMPR2A5    : 16;           /*!< [15..0] Counter/Timer A5 Compare Register 2. Holds the lower
2831                                                      limit for timer half A.                                                   */
2832       __IOM uint32_t CMPR3A5    : 16;           /*!< [31..16] Counter/Timer A5 Compare Register 3. Holds the upper
2833                                                      limit for timer half A.                                                   */
2834     } CMPRAUXA5_b;
2835   } ;
2836 
2837   union {
2838     __IOM uint32_t CMPRAUXB5;                   /*!< (@ 0x000000B8) Enhanced compare limits for timer half B.                  */
2839 
2840     struct {
2841       __IOM uint32_t CMPR2B5    : 16;           /*!< [15..0] Counter/Timer B5 Compare Register 2. Holds the lower
2842                                                      limit for timer half B.                                                   */
2843       __IOM uint32_t CMPR3B5    : 16;           /*!< [31..16] Counter/Timer B5 Compare Register 3. Holds the upper
2844                                                      limit for timer half B.                                                   */
2845     } CMPRAUXB5_b;
2846   } ;
2847 
2848   union {
2849     __IOM uint32_t AUX5;                        /*!< (@ 0x000000BC) Control bit fields for both halves of timer 0.             */
2850 
2851     struct {
2852       __IOM uint32_t TMRA5LMT   : 7;            /*!< [6..0] Counter/Timer A5 Pattern Limit Count.                              */
2853       __IOM uint32_t TMRA5TRIG  : 4;            /*!< [10..7] Counter/Timer A5 Trigger Select.                                  */
2854       __IOM uint32_t TMRA5NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2855       __IOM uint32_t TMRA5TINV  : 1;            /*!< [12..12] Counter/Timer A5 Invert on trigger.                              */
2856       __IOM uint32_t TMRA5POL23 : 1;            /*!< [13..13] Counter/Timer A5 Upper output polarity                           */
2857       __IOM uint32_t TMRA5EN23  : 1;            /*!< [14..14] Counter/Timer A5 Upper compare enable.                           */
2858             uint32_t            : 1;
2859       __IOM uint32_t TMRB5LMT   : 6;            /*!< [21..16] Counter/Timer B5 Pattern Limit Count.                            */
2860             uint32_t            : 1;
2861       __IOM uint32_t TMRB5TRIG  : 4;            /*!< [26..23] Counter/Timer B5 Trigger Select.                                 */
2862       __IOM uint32_t TMRB5NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2863       __IOM uint32_t TMRB5TINV  : 1;            /*!< [28..28] Counter/Timer B5 Invert on trigger.                              */
2864       __IOM uint32_t TMRB5POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2865       __IOM uint32_t TMRB5EN23  : 1;            /*!< [30..30] Counter/Timer B5 Upper compare enable.                           */
2866             uint32_t            : 1;
2867     } AUX5_b;
2868   } ;
2869 
2870   union {
2871     __IOM uint32_t TMR6;                        /*!< (@ 0x000000C0) Counter/Timer 6                                            */
2872 
2873     struct {
2874       __IOM uint32_t CTTMRA6    : 16;           /*!< [15..0] Counter/Timer A6.                                                 */
2875       __IOM uint32_t CTTMRB6    : 16;           /*!< [31..16] Counter/Timer B6.                                                */
2876     } TMR6_b;
2877   } ;
2878 
2879   union {
2880     __IOM uint32_t CMPRA6;                      /*!< (@ 0x000000C4) This register holds the compare limits for timer
2881                                                                     half A.                                                    */
2882 
2883     struct {
2884       __IOM uint32_t CMPR0A6    : 16;           /*!< [15..0] Counter/Timer A6 Compare Register 0.                              */
2885       __IOM uint32_t CMPR1A6    : 16;           /*!< [31..16] Counter/Timer A6 Compare Register 1.                             */
2886     } CMPRA6_b;
2887   } ;
2888 
2889   union {
2890     __IOM uint32_t CMPRB6;                      /*!< (@ 0x000000C8) This register holds the compare limits for timer
2891                                                                     half B.                                                    */
2892 
2893     struct {
2894       __IOM uint32_t CMPR0B6    : 16;           /*!< [15..0] Counter/Timer B6 Compare Register 0.                              */
2895       __IOM uint32_t CMPR1B6    : 16;           /*!< [31..16] Counter/Timer B6 Compare Register 1.                             */
2896     } CMPRB6_b;
2897   } ;
2898 
2899   union {
2900     __IOM uint32_t CTRL6;                       /*!< (@ 0x000000CC) This register holds the control bit fields for
2901                                                                     both halves of timer 6.                                    */
2902 
2903     struct {
2904       __IOM uint32_t TMRA6EN    : 1;            /*!< [0..0] Counter/Timer A6 Enable bit.                                       */
2905       __IOM uint32_t TMRA6CLK   : 5;            /*!< [5..1] Counter/Timer A6 Clock Select.                                     */
2906       __IOM uint32_t TMRA6FN    : 3;            /*!< [8..6] Counter/Timer A6 Function Select.                                  */
2907       __IOM uint32_t TMRA6IE0   : 1;            /*!< [9..9] Counter/Timer A6 Interrupt Enable bit based on COMPR0.             */
2908       __IOM uint32_t TMRA6IE1   : 1;            /*!< [10..10] Counter/Timer A6 Interrupt Enable bit based on COMPR1.           */
2909       __IOM uint32_t TMRA6CLR   : 1;            /*!< [11..11] Counter/Timer A6 Clear bit.                                      */
2910       __IOM uint32_t TMRA6POL   : 1;            /*!< [12..12] Counter/Timer A6 output polarity.                                */
2911             uint32_t            : 3;
2912       __IOM uint32_t TMRB6EN    : 1;            /*!< [16..16] Counter/Timer B6 Enable bit.                                     */
2913       __IOM uint32_t TMRB6CLK   : 5;            /*!< [21..17] Counter/Timer B6 Clock Select.                                   */
2914       __IOM uint32_t TMRB6FN    : 3;            /*!< [24..22] Counter/Timer B6 Function Select.                                */
2915       __IOM uint32_t TMRB6IE0   : 1;            /*!< [25..25] Counter/Timer B6 Interrupt Enable bit for COMPR0.                */
2916       __IOM uint32_t TMRB6IE1   : 1;            /*!< [26..26] Counter/Timer B6 Interrupt Enable bit for COMPR1.                */
2917       __IOM uint32_t TMRB6CLR   : 1;            /*!< [27..27] Counter/Timer B6 Clear bit.                                      */
2918       __IOM uint32_t TMRB6POL   : 1;            /*!< [28..28] Counter/Timer B6 output polarity.                                */
2919             uint32_t            : 2;
2920       __IOM uint32_t CTLINK6    : 1;            /*!< [31..31] Counter/Timer A6/B6 Link bit.                                    */
2921     } CTRL6_b;
2922   } ;
2923   __IM  uint32_t  RESERVED6;
2924 
2925   union {
2926     __IOM uint32_t CMPRAUXA6;                   /*!< (@ 0x000000D4) Enhanced compare limits for timer half A.                  */
2927 
2928     struct {
2929       __IOM uint32_t CMPR2A6    : 16;           /*!< [15..0] Counter/Timer A6 Compare Register 2. Holds the lower
2930                                                      limit for timer half A.                                                   */
2931       __IOM uint32_t CMPR3A6    : 16;           /*!< [31..16] Counter/Timer A6 Compare Register 3. Holds the upper
2932                                                      limit for timer half A.                                                   */
2933     } CMPRAUXA6_b;
2934   } ;
2935 
2936   union {
2937     __IOM uint32_t CMPRAUXB6;                   /*!< (@ 0x000000D8) Enhanced compare limits for timer half B.                  */
2938 
2939     struct {
2940       __IOM uint32_t CMPR2B6    : 16;           /*!< [15..0] Counter/Timer B6 Compare Register 2. Holds the lower
2941                                                      limit for timer half B.                                                   */
2942       __IOM uint32_t CMPR3B6    : 16;           /*!< [31..16] Counter/Timer B6 Compare Register 3. Holds the upper
2943                                                      limit for timer half B.                                                   */
2944     } CMPRAUXB6_b;
2945   } ;
2946 
2947   union {
2948     __IOM uint32_t AUX6;                        /*!< (@ 0x000000DC) Control bit fields for both halves of timer 0.             */
2949 
2950     struct {
2951       __IOM uint32_t TMRA6LMT   : 7;            /*!< [6..0] Counter/Timer A6 Pattern Limit Count.                              */
2952       __IOM uint32_t TMRA6TRIG  : 4;            /*!< [10..7] Counter/Timer A6 Trigger Select.                                  */
2953       __IOM uint32_t TMRA6NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2954       __IOM uint32_t TMRA6TINV  : 1;            /*!< [12..12] Counter/Timer A6 Invert on trigger.                              */
2955       __IOM uint32_t TMRA6POL23 : 1;            /*!< [13..13] Counter/Timer A6 Upper output polarity                           */
2956       __IOM uint32_t TMRA6EN23  : 1;            /*!< [14..14] Counter/Timer A6 Upper compare enable.                           */
2957             uint32_t            : 1;
2958       __IOM uint32_t TMRB6LMT   : 6;            /*!< [21..16] Counter/Timer B6 Pattern Limit Count.                            */
2959             uint32_t            : 1;
2960       __IOM uint32_t TMRB6TRIG  : 4;            /*!< [26..23] Counter/Timer B6 Trigger Select.                                 */
2961       __IOM uint32_t TMRB6NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2962       __IOM uint32_t TMRB6TINV  : 1;            /*!< [28..28] Counter/Timer B6 Invert on trigger.                              */
2963       __IOM uint32_t TMRB6POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2964       __IOM uint32_t TMRB6EN23  : 1;            /*!< [30..30] Counter/Timer B6 Upper compare enable.                           */
2965             uint32_t            : 1;
2966     } AUX6_b;
2967   } ;
2968 
2969   union {
2970     __IOM uint32_t TMR7;                        /*!< (@ 0x000000E0) Counter/Timer 7                                            */
2971 
2972     struct {
2973       __IOM uint32_t CTTMRA7    : 16;           /*!< [15..0] Counter/Timer A7.                                                 */
2974       __IOM uint32_t CTTMRB7    : 16;           /*!< [31..16] Counter/Timer B7.                                                */
2975     } TMR7_b;
2976   } ;
2977 
2978   union {
2979     __IOM uint32_t CMPRA7;                      /*!< (@ 0x000000E4) This register holds the compare limits for timer
2980                                                                     half A.                                                    */
2981 
2982     struct {
2983       __IOM uint32_t CMPR0A7    : 16;           /*!< [15..0] Counter/Timer A7 Compare Register 0.                              */
2984       __IOM uint32_t CMPR1A7    : 16;           /*!< [31..16] Counter/Timer A7 Compare Register 1.                             */
2985     } CMPRA7_b;
2986   } ;
2987 
2988   union {
2989     __IOM uint32_t CMPRB7;                      /*!< (@ 0x000000E8) This register holds the compare limits for timer
2990                                                                     half B.                                                    */
2991 
2992     struct {
2993       __IOM uint32_t CMPR0B7    : 16;           /*!< [15..0] Counter/Timer B3 Compare Register 0.                              */
2994       __IOM uint32_t CMPR1B7    : 16;           /*!< [31..16] Counter/Timer B3 Compare Register 1.                             */
2995     } CMPRB7_b;
2996   } ;
2997 
2998   union {
2999     __IOM uint32_t CTRL7;                       /*!< (@ 0x000000EC) This register holds the control bit fields for
3000                                                                     both halves of timer 7.                                    */
3001 
3002     struct {
3003       __IOM uint32_t TMRA7EN    : 1;            /*!< [0..0] Counter/Timer A7 Enable bit.                                       */
3004       __IOM uint32_t TMRA7CLK   : 5;            /*!< [5..1] Counter/Timer A7 Clock Select.                                     */
3005       __IOM uint32_t TMRA7FN    : 3;            /*!< [8..6] Counter/Timer A7 Function Select.                                  */
3006       __IOM uint32_t TMRA7IE0   : 1;            /*!< [9..9] Counter/Timer A7 Interrupt Enable bit based on COMPR0.             */
3007       __IOM uint32_t TMRA7IE1   : 1;            /*!< [10..10] Counter/Timer A7 Interrupt Enable bit based on COMPR1.           */
3008       __IOM uint32_t TMRA7CLR   : 1;            /*!< [11..11] Counter/Timer A7 Clear bit.                                      */
3009       __IOM uint32_t TMRA7POL   : 1;            /*!< [12..12] Counter/Timer A7 output polarity.                                */
3010             uint32_t            : 3;
3011       __IOM uint32_t TMRB7EN    : 1;            /*!< [16..16] Counter/Timer B7 Enable bit.                                     */
3012       __IOM uint32_t TMRB7CLK   : 5;            /*!< [21..17] Counter/Timer B7 Clock Select.                                   */
3013       __IOM uint32_t TMRB7FN    : 3;            /*!< [24..22] Counter/Timer B7 Function Select.                                */
3014       __IOM uint32_t TMRB7IE0   : 1;            /*!< [25..25] Counter/Timer B7 Interrupt Enable bit for COMPR0.                */
3015       __IOM uint32_t TMRB7IE1   : 1;            /*!< [26..26] Counter/Timer B7 Interrupt Enable bit for COMPR1.                */
3016       __IOM uint32_t TMRB7CLR   : 1;            /*!< [27..27] Counter/Timer B7 Clear bit.                                      */
3017       __IOM uint32_t TMRB7POL   : 1;            /*!< [28..28] Counter/Timer B7 output polarity.                                */
3018             uint32_t            : 2;
3019       __IOM uint32_t CTLINK7    : 1;            /*!< [31..31] Counter/Timer A7/B7 Link bit.                                    */
3020     } CTRL7_b;
3021   } ;
3022   __IM  uint32_t  RESERVED7;
3023 
3024   union {
3025     __IOM uint32_t CMPRAUXA7;                   /*!< (@ 0x000000F4) Enhanced compare limits for timer half A.                  */
3026 
3027     struct {
3028       __IOM uint32_t CMPR2A7    : 16;           /*!< [15..0] Counter/Timer A7 Compare Register 2. Holds the lower
3029                                                      limit for timer half A.                                                   */
3030       __IOM uint32_t CMPR3A7    : 16;           /*!< [31..16] Counter/Timer A7 Compare Register 3. Holds the upper
3031                                                      limit for timer half A.                                                   */
3032     } CMPRAUXA7_b;
3033   } ;
3034 
3035   union {
3036     __IOM uint32_t CMPRAUXB7;                   /*!< (@ 0x000000F8) Enhanced compare limits for timer half B.                  */
3037 
3038     struct {
3039       __IOM uint32_t CMPR2B7    : 16;           /*!< [15..0] Counter/Timer B7 Compare Register 2. Holds the lower
3040                                                      limit for timer half B.                                                   */
3041       __IOM uint32_t CMPR3B7    : 16;           /*!< [31..16] Counter/Timer B7 Compare Register 3. Holds the upper
3042                                                      limit for timer half B.                                                   */
3043     } CMPRAUXB7_b;
3044   } ;
3045 
3046   union {
3047     __IOM uint32_t AUX7;                        /*!< (@ 0x000000FC) Control bit fields for both halves of timer 0.             */
3048 
3049     struct {
3050       __IOM uint32_t TMRA7LMT   : 7;            /*!< [6..0] Counter/Timer A7 Pattern Limit Count.                              */
3051       __IOM uint32_t TMRA7TRIG  : 4;            /*!< [10..7] Counter/Timer A7 Trigger Select.                                  */
3052       __IOM uint32_t TMRA7NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
3053       __IOM uint32_t TMRA7TINV  : 1;            /*!< [12..12] Counter/Timer A7 Invert on trigger.                              */
3054       __IOM uint32_t TMRA7POL23 : 1;            /*!< [13..13] Counter/Timer A7 Upper output polarity                           */
3055       __IOM uint32_t TMRA7EN23  : 1;            /*!< [14..14] Counter/Timer A7 Upper compare enable.                           */
3056             uint32_t            : 1;
3057       __IOM uint32_t TMRB7LMT   : 6;            /*!< [21..16] Counter/Timer B7 Pattern Limit Count.                            */
3058             uint32_t            : 1;
3059       __IOM uint32_t TMRB7TRIG  : 4;            /*!< [26..23] Counter/Timer B7 Trigger Select.                                 */
3060       __IOM uint32_t TMRB7NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
3061       __IOM uint32_t TMRB7TINV  : 1;            /*!< [28..28] Counter/Timer B7 Invert on trigger.                              */
3062       __IOM uint32_t TMRB7POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
3063       __IOM uint32_t TMRB7EN23  : 1;            /*!< [30..30] Counter/Timer B7 Upper compare enable.                           */
3064             uint32_t            : 1;
3065     } AUX7_b;
3066   } ;
3067 
3068   union {
3069     __IOM uint32_t GLOBEN;                      /*!< (@ 0x00000100) Alternate enables for all CTIMERs.                         */
3070 
3071     struct {
3072       __IOM uint32_t ENA0       : 1;            /*!< [0..0] Alternate enable for A0                                            */
3073       __IOM uint32_t ENB0       : 1;            /*!< [1..1] Alternate enable for B0                                            */
3074       __IOM uint32_t ENA1       : 1;            /*!< [2..2] Alternate enable for A1                                            */
3075       __IOM uint32_t ENB1       : 1;            /*!< [3..3] Alternate enable for B1                                            */
3076       __IOM uint32_t ENA2       : 1;            /*!< [4..4] Alternate enable for A2                                            */
3077       __IOM uint32_t ENB2       : 1;            /*!< [5..5] Alternate enable for B2                                            */
3078       __IOM uint32_t ENA3       : 1;            /*!< [6..6] Alternate enable for A3                                            */
3079       __IOM uint32_t ENB3       : 1;            /*!< [7..7] Alternate enable for B3.                                           */
3080       __IOM uint32_t ENA4       : 1;            /*!< [8..8] Alternate enable for A4                                            */
3081       __IOM uint32_t ENB4       : 1;            /*!< [9..9] Alternate enable for B4                                            */
3082       __IOM uint32_t ENA5       : 1;            /*!< [10..10] Alternate enable for A5                                          */
3083       __IOM uint32_t ENB5       : 1;            /*!< [11..11] Alternate enable for B5                                          */
3084       __IOM uint32_t ENA6       : 1;            /*!< [12..12] Alternate enable for A6                                          */
3085       __IOM uint32_t ENB6       : 1;            /*!< [13..13] Alternate enable for B6                                          */
3086       __IOM uint32_t ENA7       : 1;            /*!< [14..14] Alternate enable for A7                                          */
3087       __IOM uint32_t ENB7       : 1;            /*!< [15..15] Alternate enable for B7.                                         */
3088             uint32_t            : 16;
3089     } GLOBEN_b;
3090   } ;
3091 
3092   union {
3093     __IOM uint32_t OUTCFG0;                     /*!< (@ 0x00000104) Pad output configuration 0.                                */
3094 
3095     struct {
3096       __IOM uint32_t CFG0       : 3;            /*!< [2..0] Pad output 0 configuration                                         */
3097       __IOM uint32_t CFG1       : 3;            /*!< [5..3] Pad output 1 configuration                                         */
3098       __IOM uint32_t CFG2       : 3;            /*!< [8..6] Pad output 2 configuration                                         */
3099       __IOM uint32_t CFG3       : 3;            /*!< [11..9] Pad output 3 configuration                                        */
3100       __IOM uint32_t CFG4       : 3;            /*!< [14..12] Pad output 4 configuration                                       */
3101             uint32_t            : 1;
3102       __IOM uint32_t CFG5       : 3;            /*!< [18..16] Pad output 5 configuration                                       */
3103       __IOM uint32_t CFG6       : 3;            /*!< [21..19] Pad output 6 configuration                                       */
3104       __IOM uint32_t CFG7       : 3;            /*!< [24..22] Pad output 7 configuration                                       */
3105       __IOM uint32_t CFG8       : 3;            /*!< [27..25] Pad output 8 configuration                                       */
3106       __IOM uint32_t CFG9       : 3;            /*!< [30..28] Pad output 9 configuration                                       */
3107             uint32_t            : 1;
3108     } OUTCFG0_b;
3109   } ;
3110 
3111   union {
3112     __IOM uint32_t OUTCFG1;                     /*!< (@ 0x00000108) Pad output configuration 1.                                */
3113 
3114     struct {
3115       __IOM uint32_t CFG10      : 3;            /*!< [2..0] Pad output 10 configuration                                        */
3116       __IOM uint32_t CFG11      : 3;            /*!< [5..3] Pad output 11 configuration                                        */
3117       __IOM uint32_t CFG12      : 3;            /*!< [8..6] Pad output 12 configuration                                        */
3118       __IOM uint32_t CFG13      : 3;            /*!< [11..9] Pad output 13 configuration                                       */
3119       __IOM uint32_t CFG14      : 3;            /*!< [14..12] Pad output 14 configuration                                      */
3120             uint32_t            : 1;
3121       __IOM uint32_t CFG15      : 3;            /*!< [18..16] Pad output 15 configuration                                      */
3122       __IOM uint32_t CFG16      : 3;            /*!< [21..19] Pad output 16 configuration                                      */
3123       __IOM uint32_t CFG17      : 3;            /*!< [24..22] Pad output 17 configuration                                      */
3124       __IOM uint32_t CFG18      : 3;            /*!< [27..25] Pad output 18 configuration                                      */
3125       __IOM uint32_t CFG19      : 3;            /*!< [30..28] Pad output 19 configuration                                      */
3126             uint32_t            : 1;
3127     } OUTCFG1_b;
3128   } ;
3129 
3130   union {
3131     __IOM uint32_t OUTCFG2;                     /*!< (@ 0x0000010C) Pad output configuration 2.                                */
3132 
3133     struct {
3134       __IOM uint32_t CFG20      : 3;            /*!< [2..0] Pad output 20 configuration                                        */
3135       __IOM uint32_t CFG21      : 3;            /*!< [5..3] Pad output 21 configuration                                        */
3136       __IOM uint32_t CFG22      : 3;            /*!< [8..6] Pad output 22 configuration                                        */
3137       __IOM uint32_t CFG23      : 3;            /*!< [11..9] Pad output 23 configuration                                       */
3138       __IOM uint32_t CFG24      : 3;            /*!< [14..12] Pad output 24 configuration                                      */
3139             uint32_t            : 1;
3140       __IOM uint32_t CFG25      : 3;            /*!< [18..16] Pad output 25 configuration                                      */
3141       __IOM uint32_t CFG26      : 3;            /*!< [21..19] Pad output 26 configuration                                      */
3142       __IOM uint32_t CFG27      : 3;            /*!< [24..22] Pad output 27 configuration                                      */
3143       __IOM uint32_t CFG28      : 3;            /*!< [27..25] Pad output 28 configuration                                      */
3144       __IOM uint32_t CFG29      : 3;            /*!< [30..28] Pad output 29 configuration                                      */
3145             uint32_t            : 1;
3146     } OUTCFG2_b;
3147   } ;
3148   __IM  uint32_t  RESERVED8;
3149 
3150   union {
3151     __IOM uint32_t OUTCFG3;                     /*!< (@ 0x00000114) Pad output configuration 3.                                */
3152 
3153     struct {
3154       __IOM uint32_t CFG30      : 3;            /*!< [2..0] Pad output 30 configuration                                        */
3155       __IOM uint32_t CFG31      : 3;            /*!< [5..3] Pad output 31 configuration                                        */
3156             uint32_t            : 26;
3157     } OUTCFG3_b;
3158   } ;
3159 
3160   union {
3161     __IOM uint32_t INCFG;                       /*!< (@ 0x00000118) Pad input configuration.                                   */
3162 
3163     struct {
3164       __IOM uint32_t CFGA0      : 1;            /*!< [0..0] CTIMER A0 input configuration                                      */
3165       __IOM uint32_t CFGB0      : 1;            /*!< [1..1] CTIMER B0 input configuration                                      */
3166       __IOM uint32_t CFGA1      : 1;            /*!< [2..2] CTIMER A1 input configuration                                      */
3167       __IOM uint32_t CFGB1      : 1;            /*!< [3..3] CTIMER B1 input configuration                                      */
3168       __IOM uint32_t CFGA2      : 1;            /*!< [4..4] CTIMER A2 input configuration                                      */
3169       __IOM uint32_t CFGB2      : 1;            /*!< [5..5] CTIMER B2 input configuration                                      */
3170       __IOM uint32_t CFGA3      : 1;            /*!< [6..6] CTIMER A3 input configuration                                      */
3171       __IOM uint32_t CFGB3      : 1;            /*!< [7..7] CTIMER B3 input configuration                                      */
3172       __IOM uint32_t CFGA4      : 1;            /*!< [8..8] CTIMER A4 input configuration                                      */
3173       __IOM uint32_t CFGB4      : 1;            /*!< [9..9] CTIMER B4 input configuration                                      */
3174       __IOM uint32_t CFGA5      : 1;            /*!< [10..10] CTIMER A5 input configuration                                    */
3175       __IOM uint32_t CFGB5      : 1;            /*!< [11..11] CTIMER B5 input configuration                                    */
3176       __IOM uint32_t CFGA6      : 1;            /*!< [12..12] CTIMER A6 input configuration                                    */
3177       __IOM uint32_t CFGB6      : 1;            /*!< [13..13] CTIMER B6 input configuration                                    */
3178       __IOM uint32_t CFGA7      : 1;            /*!< [14..14] CTIMER A7 input configuration                                    */
3179       __IOM uint32_t CFGB7      : 1;            /*!< [15..15] CTIMER B7 input configuration                                    */
3180             uint32_t            : 16;
3181     } INCFG_b;
3182   } ;
3183   __IM  uint32_t  RESERVED9[9];
3184 
3185   union {
3186     __IOM uint32_t STCFG;                       /*!< (@ 0x00000140) The STIMER Configuration Register contains the
3187                                                                     software control for selecting the clock
3188                                                                     divider and source feeding the system timer.               */
3189 
3190     struct {
3191       __IOM uint32_t CLKSEL     : 4;            /*!< [3..0] Selects an appropriate clock source and divider to use
3192                                                      for the System Timer clock.                                               */
3193             uint32_t            : 4;
3194       __IOM uint32_t COMPARE_A_EN : 1;          /*!< [8..8] Selects whether compare is enabled for the corresponding
3195                                                      SCMPR register. If compare is enabled, the interrupt status
3196                                                      is set once the comparison is met.                                        */
3197       __IOM uint32_t COMPARE_B_EN : 1;          /*!< [9..9] Selects whether compare is enabled for the corresponding
3198                                                      SCMPR register. If compare is enabled, the interrupt status
3199                                                      is set once the comparison is met.                                        */
3200       __IOM uint32_t COMPARE_C_EN : 1;          /*!< [10..10] Selects whether compare is enabled for the corresponding
3201                                                      SCMPR register. If compare is enabled, the interrupt status
3202                                                      is set once the comparison is met.                                        */
3203       __IOM uint32_t COMPARE_D_EN : 1;          /*!< [11..11] Selects whether compare is enabled for the corresponding
3204                                                      SCMPR register. If compare is enabled, the interrupt status
3205                                                      is set once the comparison is met.                                        */
3206       __IOM uint32_t COMPARE_E_EN : 1;          /*!< [12..12] Selects whether compare is enabled for the corresponding
3207                                                      SCMPR register. If compare is enabled, the interrupt status
3208                                                      is set once the comparison is met.                                        */
3209       __IOM uint32_t COMPARE_F_EN : 1;          /*!< [13..13] Selects whether compare is enabled for the corresponding
3210                                                      SCMPR register. If compare is enabled, the interrupt status
3211                                                      is set once the comparison is met.                                        */
3212       __IOM uint32_t COMPARE_G_EN : 1;          /*!< [14..14] Selects whether compare is enabled for the corresponding
3213                                                      SCMPR register. If compare is enabled, the interrupt status
3214                                                      is set once the comparison is met.                                        */
3215       __IOM uint32_t COMPARE_H_EN : 1;          /*!< [15..15] Selects whether compare is enabled for the corresponding
3216                                                      SCMPR register. If compare is enabled, the interrupt status
3217                                                      is set once the comparison is met.                                        */
3218             uint32_t            : 14;
3219       __IOM uint32_t CLEAR      : 1;            /*!< [30..30] Set this bit to one to clear the System Timer register.
3220                                                      If this bit is set to '1', the system timer register will
3221                                                      stay cleared. It needs to be set to '0' for the system
3222                                                      timer to start running.                                                   */
3223       __IOM uint32_t FREEZE     : 1;            /*!< [31..31] Set this bit to one to freeze the clock input to the
3224                                                      COUNTER register. Once frozen, the value can be safely
3225                                                      written from the MCU. Unfreeze to resume.                                 */
3226     } STCFG_b;
3227   } ;
3228 
3229   union {
3230     __IOM uint32_t STTMR;                       /*!< (@ 0x00000144) The COUNTER Register contains the running count
3231                                                                     of time as maintained by incrementing for
3232                                                                     every rising clock edge of the clock source
3233                                                                     selected in the configuration register.
3234                                                                     It is this counter value that captured in
3235                                                                     the capture registers and it is this counter
3236                                                                     value that is compared against the various
3237                                                                     compare registers. This register cannot
3238                                                                     be written, but can be cleared to 0 for
3239                                                                     a deterministic value. Use the FREEZE bit
3240                                                                     will stop this counter from incrementing.                  */
3241 
3242     struct {
3243       __IOM uint32_t STTMR      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
3244     } STTMR_b;
3245   } ;
3246 
3247   union {
3248     __IOM uint32_t CAPTURECONTROL;              /*!< (@ 0x00000148) The STIMER Capture Control Register controls
3249                                                                     each of the 4 capture registers. It selects
3250                                                                     their GPIO pin number for a trigger source,
3251                                                                     enables a capture operation and sets the
3252                                                                     input polarity for the capture. NOTE: 8-bit
3253                                                                     writes can control individual capture registers
3254                                                                     atomically.                                                */
3255 
3256     struct {
3257       __IOM uint32_t CAPTURE0   : 1;            /*!< [0..0] Selects whether capture is enabled for the specified
3258                                                      capture register.                                                         */
3259       __IOM uint32_t CAPTURE1   : 1;            /*!< [1..1] Selects whether capture is enabled for the specified
3260                                                      capture register.                                                         */
3261       __IOM uint32_t CAPTURE2   : 1;            /*!< [2..2] Selects whether capture is enabled for the specified
3262                                                      capture register.                                                         */
3263       __IOM uint32_t CAPTURE3   : 1;            /*!< [3..3] Selects whether capture is enabled for the specified
3264                                                      capture register.                                                         */
3265             uint32_t            : 28;
3266     } CAPTURECONTROL_b;
3267   } ;
3268   __IM  uint32_t  RESERVED10;
3269 
3270   union {
3271     __IOM uint32_t SCMPR0;                      /*!< (@ 0x00000150) The VALUE in this bit field is used to compare
3272                                                                     against the VALUE in the COUNTER register.
3273                                                                     If the match criterion in the configuration
3274                                                                     register is met then a corresponding interrupt
3275                                                                     status bit is set. The match criterion is
3276                                                                     defined as COUNTER equal to COMPARE. To
3277                                                                     establish a desired value in this COMPARE
3278                                                                     register, write the number of ticks in the
3279                                                                     future to this register to indicate when
3280                                                                     to interrupt. The hardware does the addition
3281                                                                     to the COUNTER value in the STIMER clock
3282                                                                     domain so that the ma                                      */
3283 
3284     struct {
3285       __IOM uint32_t SCMPR0     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3286                                                      according to the match criterion, as selected in the COMPARE_A_EN
3287                                                      bit in the REG_CTIMER_STCGF register.                                     */
3288     } SCMPR0_b;
3289   } ;
3290 
3291   union {
3292     __IOM uint32_t SCMPR1;                      /*!< (@ 0x00000154) The VALUE in this bit field is used to compare
3293                                                                     against the VALUE in the COUNTER register.
3294                                                                     If the match criterion in the configuration
3295                                                                     register is met then a corresponding interrupt
3296                                                                     status bit is set. The match criterion is
3297                                                                     defined as COUNTER equal to COMPARE. To
3298                                                                     establish a desired value in this COMPARE
3299                                                                     register, write the number of ticks in the
3300                                                                     future to this register to indicate when
3301                                                                     to interrupt. The hardware does the addition
3302                                                                     to the COUNTER value in the STIMER clock
3303                                                                     domain so that the ma                                      */
3304 
3305     struct {
3306       __IOM uint32_t SCMPR1     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3307                                                      according to the match criterion, as selected in the COMPARE_B_EN
3308                                                      bit in the REG_CTIMER_STCGF register.                                     */
3309     } SCMPR1_b;
3310   } ;
3311 
3312   union {
3313     __IOM uint32_t SCMPR2;                      /*!< (@ 0x00000158) The VALUE in this bit field is used to compare
3314                                                                     against the VALUE in the COUNTER register.
3315                                                                     If the match criterion in the configuration
3316                                                                     register is met then a corresponding interrupt
3317                                                                     status bit is set. The match criterion is
3318                                                                     defined as COUNTER equal to COMPARE. To
3319                                                                     establish a desired value in this COMPARE
3320                                                                     register, write the number of ticks in the
3321                                                                     future to this register to indicate when
3322                                                                     to interrupt. The hardware does the addition
3323                                                                     to the COUNTER value in the STIMER clock
3324                                                                     domain so that the ma                                      */
3325 
3326     struct {
3327       __IOM uint32_t SCMPR2     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3328                                                      according to the match criterion, as selected in the COMPARE_C_EN
3329                                                      bit in the REG_CTIMER_STCGF register.                                     */
3330     } SCMPR2_b;
3331   } ;
3332 
3333   union {
3334     __IOM uint32_t SCMPR3;                      /*!< (@ 0x0000015C) The VALUE in this bit field is used to compare
3335                                                                     against the VALUE in the COUNTER register.
3336                                                                     If the match criterion in the configuration
3337                                                                     register is met then a corresponding interrupt
3338                                                                     status bit is set. The match criterion is
3339                                                                     defined as COUNTER equal to COMPARE. To
3340                                                                     establish a desired value in this COMPARE
3341                                                                     register, write the number of ticks in the
3342                                                                     future to this register to indicate when
3343                                                                     to interrupt. The hardware does the addition
3344                                                                     to the COUNTER value in the STIMER clock
3345                                                                     domain so that the ma                                      */
3346 
3347     struct {
3348       __IOM uint32_t SCMPR3     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3349                                                      according to the match criterion, as selected in the COMPARE_D_EN
3350                                                      bit in the REG_CTIMER_STCGF register.                                     */
3351     } SCMPR3_b;
3352   } ;
3353 
3354   union {
3355     __IOM uint32_t SCMPR4;                      /*!< (@ 0x00000160) The VALUE in this bit field is used to compare
3356                                                                     against the VALUE in the COUNTER register.
3357                                                                     If the match criterion in the configuration
3358                                                                     register is met then a corresponding interrupt
3359                                                                     status bit is set. The match criterion is
3360                                                                     defined as COUNTER equal to COMPARE. To
3361                                                                     establish a desired value in this COMPARE
3362                                                                     register, write the number of ticks in the
3363                                                                     future to this register to indicate when
3364                                                                     to interrupt. The hardware does the addition
3365                                                                     to the COUNTER value in the STIMER clock
3366                                                                     domain so that the ma                                      */
3367 
3368     struct {
3369       __IOM uint32_t SCMPR4     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3370                                                      according to the match criterion, as selected in the COMPARE_E_EN
3371                                                      bit in the REG_CTIMER_STCGF register.                                     */
3372     } SCMPR4_b;
3373   } ;
3374 
3375   union {
3376     __IOM uint32_t SCMPR5;                      /*!< (@ 0x00000164) The VALUE in this bit field is used to compare
3377                                                                     against the VALUE in the COUNTER register.
3378                                                                     If the match criterion in the configuration
3379                                                                     register is met then a corresponding interrupt
3380                                                                     status bit is set. The match criterion is
3381                                                                     defined as COUNTER equal to COMPARE. To
3382                                                                     establish a desired value in this COMPARE
3383                                                                     register, write the number of ticks in the
3384                                                                     future to this register to indicate when
3385                                                                     to interrupt. The hardware does the addition
3386                                                                     to the COUNTER value in the STIMER clock
3387                                                                     domain so that the ma                                      */
3388 
3389     struct {
3390       __IOM uint32_t SCMPR5     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3391                                                      according to the match criterion, as selected in the COMPARE_F_EN
3392                                                      bit in the REG_CTIMER_STCGF register.                                     */
3393     } SCMPR5_b;
3394   } ;
3395 
3396   union {
3397     __IOM uint32_t SCMPR6;                      /*!< (@ 0x00000168) The VALUE in this bit field is used to compare
3398                                                                     against the VALUE in the COUNTER register.
3399                                                                     If the match criterion in the configuration
3400                                                                     register is met then a corresponding interrupt
3401                                                                     status bit is set. The match criterion is
3402                                                                     defined as COUNTER equal to COMPARE. To
3403                                                                     establish a desired value in this COMPARE
3404                                                                     register, write the number of ticks in the
3405                                                                     future to this register to indicate when
3406                                                                     to interrupt. The hardware does the addition
3407                                                                     to the COUNTER value in the STIMER clock
3408                                                                     domain so that the ma                                      */
3409 
3410     struct {
3411       __IOM uint32_t SCMPR6     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3412                                                      according to the match criterion, as selected in the COMPARE_G_EN
3413                                                      bit in the REG_CTIMER_STCGF register.                                     */
3414     } SCMPR6_b;
3415   } ;
3416 
3417   union {
3418     __IOM uint32_t SCMPR7;                      /*!< (@ 0x0000016C) The VALUE in this bit field is used to compare
3419                                                                     against the VALUE in the COUNTER register.
3420                                                                     If the match criterion in the configuration
3421                                                                     register is met then a corresponding interrupt
3422                                                                     status bit is set. The match criterion is
3423                                                                     defined as COUNTER equal to COMPARE. To
3424                                                                     establish a desired value in this COMPARE
3425                                                                     register, write the number of ticks in the
3426                                                                     future to this register to indicate when
3427                                                                     to interrupt. The hardware does the addition
3428                                                                     to the COUNTER value in the STIMER clock
3429                                                                     domain so that the ma                                      */
3430 
3431     struct {
3432       __IOM uint32_t SCMPR7     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3433                                                      according to the match criterion, as selected in the COMPARE_H_EN
3434                                                      bit in the REG_CTIMER_STCGF register.                                     */
3435     } SCMPR7_b;
3436   } ;
3437   __IM  uint32_t  RESERVED11[28];
3438 
3439   union {
3440     __IOM uint32_t SCAPT0;                      /*!< (@ 0x000001E0) The STIMER Capture Register A grabs the VALUE
3441                                                                     in the COUNTER register whenever capture
3442                                                                     condition (event) A is asserted. This register
3443                                                                     holds a time stamp for the event.                          */
3444 
3445     struct {
3446       __IOM uint32_t SCAPT0     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
3447                                                      is copied into this register and the corresponding interrupt
3448                                                      status bit is set.                                                        */
3449     } SCAPT0_b;
3450   } ;
3451 
3452   union {
3453     __IOM uint32_t SCAPT1;                      /*!< (@ 0x000001E4) The STIMER Capture Register B grabs the VALUE
3454                                                                     in the COUNTER register whenever capture
3455                                                                     condition (event) B is asserted. This register
3456                                                                     holds a time stamp for the event.                          */
3457 
3458     struct {
3459       __IOM uint32_t SCAPT1     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
3460                                                      is copied into this register and the corresponding interrupt
3461                                                      status bit is set.                                                        */
3462     } SCAPT1_b;
3463   } ;
3464 
3465   union {
3466     __IOM uint32_t SCAPT2;                      /*!< (@ 0x000001E8) The STIMER Capture Register C grabs the VALUE
3467                                                                     in the COUNTER register whenever capture
3468                                                                     condition (event) C is asserted. This register
3469                                                                     holds a time stamp for the event.                          */
3470 
3471     struct {
3472       __IOM uint32_t SCAPT2     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
3473                                                      is copied into this register and the corresponding interrupt
3474                                                      status bit is set.                                                        */
3475     } SCAPT2_b;
3476   } ;
3477 
3478   union {
3479     __IOM uint32_t SCAPT3;                      /*!< (@ 0x000001EC) The STIMER Capture Register D grabs the VALUE
3480                                                                     in the COUNTER register whenever capture
3481                                                                     condition (event) D is asserted. This register
3482                                                                     holds a time stamp for the event.                          */
3483 
3484     struct {
3485       __IOM uint32_t SCAPT3     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
3486                                                      is copied into this register and the corresponding interrupt
3487                                                      status bit is set.                                                        */
3488     } SCAPT3_b;
3489   } ;
3490 
3491   union {
3492     __IOM uint32_t SNVR0;                       /*!< (@ 0x000001F0) The NVRAM_A Register contains a portion of the
3493                                                                     stored epoch offset associated with the
3494                                                                     time in the COUNTER register. This register
3495                                                                     is only reset by POI not by HRESETn. Its
3496                                                                     contents are intended to survive all reset
3497                                                                     level except POI and full power cycles.                    */
3498 
3499     struct {
3500       __IOM uint32_t SNVR0      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
3501     } SNVR0_b;
3502   } ;
3503 
3504   union {
3505     __IOM uint32_t SNVR1;                       /*!< (@ 0x000001F4) The NVRAM_B Register contains a portion of the
3506                                                                     stored epoch offset associated with the
3507                                                                     time in the COUNTER register. This register
3508                                                                     is only reset by POI not by HRESETn. Its
3509                                                                     contents are intended to survive all reset
3510                                                                     level except POI and full power cycles.                    */
3511 
3512     struct {
3513       __IOM uint32_t SNVR1      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
3514     } SNVR1_b;
3515   } ;
3516 
3517   union {
3518     __IOM uint32_t SNVR2;                       /*!< (@ 0x000001F8) The NVRAM_C Register contains a portion of the
3519                                                                     stored epoch offset associated with the
3520                                                                     time in the COUNTER register. This register
3521                                                                     is only reset by POI not by HRESETn. Its
3522                                                                     contents are intended to survive all reset
3523                                                                     level except POI and full power cycles.                    */
3524 
3525     struct {
3526       __IOM uint32_t SNVR2      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
3527     } SNVR2_b;
3528   } ;
3529 
3530   union {
3531     __IOM uint32_t SNVR3;                       /*!< (@ 0x000001FC) The NVRAM_D Register contains a portion of the
3532                                                                     stored epoch offset associated with the
3533                                                                     time in the COUNTER register. This register
3534                                                                     is only reset by POI not by HRESETn. Its
3535                                                                     contents are intended to survive all reset
3536                                                                     level except POI and full power cycles.                    */
3537 
3538     struct {
3539       __IOM uint32_t SNVR3      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
3540     } SNVR3_b;
3541   } ;
3542 
3543   union {
3544     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
3545                                                                     to generate the corresponding interrupt.                   */
3546 
3547     struct {
3548       __IOM uint32_t CTMRA0C0INT : 1;           /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0.                        */
3549       __IOM uint32_t CTMRB0C0INT : 1;           /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0.                        */
3550       __IOM uint32_t CTMRA1C0INT : 1;           /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0.                        */
3551       __IOM uint32_t CTMRB1C0INT : 1;           /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0.                        */
3552       __IOM uint32_t CTMRA2C0INT : 1;           /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0.                        */
3553       __IOM uint32_t CTMRB2C0INT : 1;           /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0.                        */
3554       __IOM uint32_t CTMRA3C0INT : 1;           /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0.                        */
3555       __IOM uint32_t CTMRB3C0INT : 1;           /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0.                        */
3556       __IOM uint32_t CTMRA4C0INT : 1;           /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0.                        */
3557       __IOM uint32_t CTMRB4C0INT : 1;           /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0.                        */
3558       __IOM uint32_t CTMRA5C0INT : 1;           /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0.                      */
3559       __IOM uint32_t CTMRB5C0INT : 1;           /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0.                      */
3560       __IOM uint32_t CTMRA6C0INT : 1;           /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0.                      */
3561       __IOM uint32_t CTMRB6C0INT : 1;           /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0.                      */
3562       __IOM uint32_t CTMRA7C0INT : 1;           /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0.                      */
3563       __IOM uint32_t CTMRB7C0INT : 1;           /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0.                      */
3564       __IOM uint32_t CTMRA0C1INT : 1;           /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1.                      */
3565       __IOM uint32_t CTMRB0C1INT : 1;           /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1.                      */
3566       __IOM uint32_t CTMRA1C1INT : 1;           /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1.                      */
3567       __IOM uint32_t CTMRB1C1INT : 1;           /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1.                      */
3568       __IOM uint32_t CTMRA2C1INT : 1;           /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1.                      */
3569       __IOM uint32_t CTMRB2C1INT : 1;           /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1.                      */
3570       __IOM uint32_t CTMRA3C1INT : 1;           /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1.                      */
3571       __IOM uint32_t CTMRB3C1INT : 1;           /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1.                      */
3572       __IOM uint32_t CTMRA4C1INT : 1;           /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1.                      */
3573       __IOM uint32_t CTMRB4C1INT : 1;           /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1.                      */
3574       __IOM uint32_t CTMRA5C1INT : 1;           /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1.                      */
3575       __IOM uint32_t CTMRB5C1INT : 1;           /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1.                      */
3576       __IOM uint32_t CTMRA6C1INT : 1;           /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1.                      */
3577       __IOM uint32_t CTMRB6C1INT : 1;           /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1.                      */
3578       __IOM uint32_t CTMRA7C1INT : 1;           /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1.                      */
3579       __IOM uint32_t CTMRB7C1INT : 1;           /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1.                      */
3580     } INTEN_b;
3581   } ;
3582 
3583   union {
3584     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
3585                                                                     cause of a recent interrupt.                               */
3586 
3587     struct {
3588       __IOM uint32_t CTMRA0C0INT : 1;           /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0.                        */
3589       __IOM uint32_t CTMRB0C0INT : 1;           /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0.                        */
3590       __IOM uint32_t CTMRA1C0INT : 1;           /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0.                        */
3591       __IOM uint32_t CTMRB1C0INT : 1;           /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0.                        */
3592       __IOM uint32_t CTMRA2C0INT : 1;           /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0.                        */
3593       __IOM uint32_t CTMRB2C0INT : 1;           /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0.                        */
3594       __IOM uint32_t CTMRA3C0INT : 1;           /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0.                        */
3595       __IOM uint32_t CTMRB3C0INT : 1;           /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0.                        */
3596       __IOM uint32_t CTMRA4C0INT : 1;           /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0.                        */
3597       __IOM uint32_t CTMRB4C0INT : 1;           /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0.                        */
3598       __IOM uint32_t CTMRA5C0INT : 1;           /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0.                      */
3599       __IOM uint32_t CTMRB5C0INT : 1;           /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0.                      */
3600       __IOM uint32_t CTMRA6C0INT : 1;           /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0.                      */
3601       __IOM uint32_t CTMRB6C0INT : 1;           /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0.                      */
3602       __IOM uint32_t CTMRA7C0INT : 1;           /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0.                      */
3603       __IOM uint32_t CTMRB7C0INT : 1;           /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0.                      */
3604       __IOM uint32_t CTMRA0C1INT : 1;           /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1.                      */
3605       __IOM uint32_t CTMRB0C1INT : 1;           /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1.                      */
3606       __IOM uint32_t CTMRA1C1INT : 1;           /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1.                      */
3607       __IOM uint32_t CTMRB1C1INT : 1;           /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1.                      */
3608       __IOM uint32_t CTMRA2C1INT : 1;           /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1.                      */
3609       __IOM uint32_t CTMRB2C1INT : 1;           /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1.                      */
3610       __IOM uint32_t CTMRA3C1INT : 1;           /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1.                      */
3611       __IOM uint32_t CTMRB3C1INT : 1;           /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1.                      */
3612       __IOM uint32_t CTMRA4C1INT : 1;           /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1.                      */
3613       __IOM uint32_t CTMRB4C1INT : 1;           /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1.                      */
3614       __IOM uint32_t CTMRA5C1INT : 1;           /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1.                      */
3615       __IOM uint32_t CTMRB5C1INT : 1;           /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1.                      */
3616       __IOM uint32_t CTMRA6C1INT : 1;           /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1.                      */
3617       __IOM uint32_t CTMRB6C1INT : 1;           /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1.                      */
3618       __IOM uint32_t CTMRA7C1INT : 1;           /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1.                      */
3619       __IOM uint32_t CTMRB7C1INT : 1;           /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1.                      */
3620     } INTSTAT_b;
3621   } ;
3622 
3623   union {
3624     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
3625                                                                     the interrupt status associated with that
3626                                                                     bit.                                                       */
3627 
3628     struct {
3629       __IOM uint32_t CTMRA0C0INT : 1;           /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0.                        */
3630       __IOM uint32_t CTMRB0C0INT : 1;           /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0.                        */
3631       __IOM uint32_t CTMRA1C0INT : 1;           /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0.                        */
3632       __IOM uint32_t CTMRB1C0INT : 1;           /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0.                        */
3633       __IOM uint32_t CTMRA2C0INT : 1;           /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0.                        */
3634       __IOM uint32_t CTMRB2C0INT : 1;           /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0.                        */
3635       __IOM uint32_t CTMRA3C0INT : 1;           /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0.                        */
3636       __IOM uint32_t CTMRB3C0INT : 1;           /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0.                        */
3637       __IOM uint32_t CTMRA4C0INT : 1;           /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0.                        */
3638       __IOM uint32_t CTMRB4C0INT : 1;           /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0.                        */
3639       __IOM uint32_t CTMRA5C0INT : 1;           /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0.                      */
3640       __IOM uint32_t CTMRB5C0INT : 1;           /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0.                      */
3641       __IOM uint32_t CTMRA6C0INT : 1;           /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0.                      */
3642       __IOM uint32_t CTMRB6C0INT : 1;           /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0.                      */
3643       __IOM uint32_t CTMRA7C0INT : 1;           /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0.                      */
3644       __IOM uint32_t CTMRB7C0INT : 1;           /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0.                      */
3645       __IOM uint32_t CTMRA0C1INT : 1;           /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1.                      */
3646       __IOM uint32_t CTMRB0C1INT : 1;           /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1.                      */
3647       __IOM uint32_t CTMRA1C1INT : 1;           /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1.                      */
3648       __IOM uint32_t CTMRB1C1INT : 1;           /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1.                      */
3649       __IOM uint32_t CTMRA2C1INT : 1;           /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1.                      */
3650       __IOM uint32_t CTMRB2C1INT : 1;           /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1.                      */
3651       __IOM uint32_t CTMRA3C1INT : 1;           /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1.                      */
3652       __IOM uint32_t CTMRB3C1INT : 1;           /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1.                      */
3653       __IOM uint32_t CTMRA4C1INT : 1;           /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1.                      */
3654       __IOM uint32_t CTMRB4C1INT : 1;           /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1.                      */
3655       __IOM uint32_t CTMRA5C1INT : 1;           /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1.                      */
3656       __IOM uint32_t CTMRB5C1INT : 1;           /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1.                      */
3657       __IOM uint32_t CTMRA6C1INT : 1;           /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1.                      */
3658       __IOM uint32_t CTMRB6C1INT : 1;           /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1.                      */
3659       __IOM uint32_t CTMRA7C1INT : 1;           /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1.                      */
3660       __IOM uint32_t CTMRB7C1INT : 1;           /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1.                      */
3661     } INTCLR_b;
3662   } ;
3663 
3664   union {
3665     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
3666                                                                     generate an interrupt from this module.
3667                                                                     (Generally used for testing purposes).                     */
3668 
3669     struct {
3670       __IOM uint32_t CTMRA0C0INT : 1;           /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0.                        */
3671       __IOM uint32_t CTMRB0C0INT : 1;           /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0.                        */
3672       __IOM uint32_t CTMRA1C0INT : 1;           /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0.                        */
3673       __IOM uint32_t CTMRB1C0INT : 1;           /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0.                        */
3674       __IOM uint32_t CTMRA2C0INT : 1;           /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0.                        */
3675       __IOM uint32_t CTMRB2C0INT : 1;           /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0.                        */
3676       __IOM uint32_t CTMRA3C0INT : 1;           /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0.                        */
3677       __IOM uint32_t CTMRB3C0INT : 1;           /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0.                        */
3678       __IOM uint32_t CTMRA4C0INT : 1;           /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0.                        */
3679       __IOM uint32_t CTMRB4C0INT : 1;           /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0.                        */
3680       __IOM uint32_t CTMRA5C0INT : 1;           /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0.                      */
3681       __IOM uint32_t CTMRB5C0INT : 1;           /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0.                      */
3682       __IOM uint32_t CTMRA6C0INT : 1;           /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0.                      */
3683       __IOM uint32_t CTMRB6C0INT : 1;           /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0.                      */
3684       __IOM uint32_t CTMRA7C0INT : 1;           /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0.                      */
3685       __IOM uint32_t CTMRB7C0INT : 1;           /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0.                      */
3686       __IOM uint32_t CTMRA0C1INT : 1;           /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1.                      */
3687       __IOM uint32_t CTMRB0C1INT : 1;           /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1.                      */
3688       __IOM uint32_t CTMRA1C1INT : 1;           /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1.                      */
3689       __IOM uint32_t CTMRB1C1INT : 1;           /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1.                      */
3690       __IOM uint32_t CTMRA2C1INT : 1;           /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1.                      */
3691       __IOM uint32_t CTMRB2C1INT : 1;           /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1.                      */
3692       __IOM uint32_t CTMRA3C1INT : 1;           /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1.                      */
3693       __IOM uint32_t CTMRB3C1INT : 1;           /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1.                      */
3694       __IOM uint32_t CTMRA4C1INT : 1;           /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1.                      */
3695       __IOM uint32_t CTMRB4C1INT : 1;           /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1.                      */
3696       __IOM uint32_t CTMRA5C1INT : 1;           /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1.                      */
3697       __IOM uint32_t CTMRB5C1INT : 1;           /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1.                      */
3698       __IOM uint32_t CTMRA6C1INT : 1;           /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1.                      */
3699       __IOM uint32_t CTMRB6C1INT : 1;           /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1.                      */
3700       __IOM uint32_t CTMRA7C1INT : 1;           /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1.                      */
3701       __IOM uint32_t CTMRB7C1INT : 1;           /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1.                      */
3702     } INTSET_b;
3703   } ;
3704   __IM  uint32_t  RESERVED12[60];
3705 
3706   union {
3707     __IOM uint32_t STMINTEN;                    /*!< (@ 0x00000300) Set bits in this register to allow this module
3708                                                                     to generate the corresponding interrupt.                   */
3709 
3710     struct {
3711       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
3712                                                      A.                                                                        */
3713       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
3714                                                      B.                                                                        */
3715       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
3716                                                      C.                                                                        */
3717       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
3718                                                      D.                                                                        */
3719       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
3720                                                      E.                                                                        */
3721       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
3722                                                      F.                                                                        */
3723       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
3724                                                      G.                                                                        */
3725       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
3726                                                      H.                                                                        */
3727       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
3728       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
3729       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
3730       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
3731       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
3732             uint32_t            : 19;
3733     } STMINTEN_b;
3734   } ;
3735 
3736   union {
3737     __IOM uint32_t STMINTSTAT;                  /*!< (@ 0x00000304) Read bits from this register to discover the
3738                                                                     cause of a recent interrupt.                               */
3739 
3740     struct {
3741       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
3742                                                      A.                                                                        */
3743       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
3744                                                      B.                                                                        */
3745       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
3746                                                      C.                                                                        */
3747       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
3748                                                      D.                                                                        */
3749       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
3750                                                      E.                                                                        */
3751       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
3752                                                      F.                                                                        */
3753       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
3754                                                      G.                                                                        */
3755       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
3756                                                      H.                                                                        */
3757       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
3758       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
3759       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
3760       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
3761       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
3762             uint32_t            : 19;
3763     } STMINTSTAT_b;
3764   } ;
3765 
3766   union {
3767     __IOM uint32_t STMINTCLR;                   /*!< (@ 0x00000308) Write a 1 to a bit in this register to clear
3768                                                                     the interrupt status associated with that
3769                                                                     bit.                                                       */
3770 
3771     struct {
3772       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
3773                                                      A.                                                                        */
3774       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
3775                                                      B.                                                                        */
3776       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
3777                                                      C.                                                                        */
3778       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
3779                                                      D.                                                                        */
3780       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
3781                                                      E.                                                                        */
3782       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
3783                                                      F.                                                                        */
3784       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
3785                                                      G.                                                                        */
3786       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
3787                                                      H.                                                                        */
3788       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
3789       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
3790       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
3791       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
3792       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
3793             uint32_t            : 19;
3794     } STMINTCLR_b;
3795   } ;
3796 
3797   union {
3798     __IOM uint32_t STMINTSET;                   /*!< (@ 0x0000030C) Write a 1 to a bit in this register to instantly
3799                                                                     generate an interrupt from this module.
3800                                                                     (Generally used for testing purposes).                     */
3801 
3802     struct {
3803       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
3804                                                      A.                                                                        */
3805       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
3806                                                      B.                                                                        */
3807       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
3808                                                      C.                                                                        */
3809       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
3810                                                      D.                                                                        */
3811       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
3812                                                      E.                                                                        */
3813       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
3814                                                      F.                                                                        */
3815       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
3816                                                      G.                                                                        */
3817       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
3818                                                      H.                                                                        */
3819       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
3820       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
3821       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
3822       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
3823       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
3824             uint32_t            : 19;
3825     } STMINTSET_b;
3826   } ;
3827 } CTIMER_Type;                                  /*!< Size = 784 (0x310)                                                        */
3828 
3829 
3830 
3831 /* =========================================================================================================================== */
3832 /* ================                                           GPIO                                            ================ */
3833 /* =========================================================================================================================== */
3834 
3835 
3836 /**
3837   * @brief General Purpose IO (GPIO)
3838   */
3839 
3840 typedef struct {                                /*!< (@ 0x40010000) GPIO Structure                                             */
3841 
3842   union {
3843     __IOM uint32_t PADREGA;                     /*!< (@ 0x00000000) This register controls the pad configuration
3844                                                                     controls for PAD3 through PAD0. Writes to
3845                                                                     this register must be unlocked by the PADKEY
3846                                                                     register.                                                  */
3847 
3848     struct {
3849       __IOM uint32_t PAD0PULL   : 1;            /*!< [0..0] Pad 0 pullup enable                                                */
3850       __IOM uint32_t PAD0INPEN  : 1;            /*!< [1..1] Pad 0 input enable                                                 */
3851       __IOM uint32_t PAD0STRNG  : 1;            /*!< [2..2] Pad 0 drive strength                                               */
3852       __IOM uint32_t PAD0FNCSEL : 3;            /*!< [5..3] Pad 0 function select                                              */
3853       __IOM uint32_t PAD0RSEL   : 2;            /*!< [7..6] Pad 0 pullup resistor selection.                                   */
3854       __IOM uint32_t PAD1PULL   : 1;            /*!< [8..8] Pad 1 pullup enable                                                */
3855       __IOM uint32_t PAD1INPEN  : 1;            /*!< [9..9] Pad 1 input enable                                                 */
3856       __IOM uint32_t PAD1STRNG  : 1;            /*!< [10..10] Pad 1 drive strength                                             */
3857       __IOM uint32_t PAD1FNCSEL : 3;            /*!< [13..11] Pad 1 function select                                            */
3858       __IOM uint32_t PAD1RSEL   : 2;            /*!< [15..14] Pad 1 pullup resistor selection.                                 */
3859       __IOM uint32_t PAD2PULL   : 1;            /*!< [16..16] Pad 2 pullup enable                                              */
3860       __IOM uint32_t PAD2INPEN  : 1;            /*!< [17..17] Pad 2 input enable                                               */
3861       __IOM uint32_t PAD2STRNG  : 1;            /*!< [18..18] Pad 2 drive strength                                             */
3862       __IOM uint32_t PAD2FNCSEL : 3;            /*!< [21..19] Pad 2 function select                                            */
3863             uint32_t            : 2;
3864       __IOM uint32_t PAD3PULL   : 1;            /*!< [24..24] Pad 3 pullup enable                                              */
3865       __IOM uint32_t PAD3INPEN  : 1;            /*!< [25..25] Pad 3 input enable.                                              */
3866       __IOM uint32_t PAD3STRNG  : 1;            /*!< [26..26] Pad 3 drive strength.                                            */
3867       __IOM uint32_t PAD3FNCSEL : 3;            /*!< [29..27] Pad 3 function select                                            */
3868       __IOM uint32_t PAD3PWRUP  : 1;            /*!< [30..30] Pad 3 VDD power switch enable                                    */
3869             uint32_t            : 1;
3870     } PADREGA_b;
3871   } ;
3872 
3873   union {
3874     __IOM uint32_t PADREGB;                     /*!< (@ 0x00000004) This register controls the pad configuration
3875                                                                     controls for PAD7 through PAD4. Writes to
3876                                                                     this register must be unlocked by the PADKEY
3877                                                                     register.                                                  */
3878 
3879     struct {
3880       __IOM uint32_t PAD4PULL   : 1;            /*!< [0..0] Pad 4 pullup enable                                                */
3881       __IOM uint32_t PAD4INPEN  : 1;            /*!< [1..1] Pad 4 input enable                                                 */
3882       __IOM uint32_t PAD4STRNG  : 1;            /*!< [2..2] Pad 4 drive strength                                               */
3883       __IOM uint32_t PAD4FNCSEL : 3;            /*!< [5..3] Pad 4 function select                                              */
3884             uint32_t            : 2;
3885       __IOM uint32_t PAD5PULL   : 1;            /*!< [8..8] Pad 5 pullup enable                                                */
3886       __IOM uint32_t PAD5INPEN  : 1;            /*!< [9..9] Pad 5 input enable                                                 */
3887       __IOM uint32_t PAD5STRNG  : 1;            /*!< [10..10] Pad 5 drive strength                                             */
3888       __IOM uint32_t PAD5FNCSEL : 3;            /*!< [13..11] Pad 5 function select                                            */
3889       __IOM uint32_t PAD5RSEL   : 2;            /*!< [15..14] Pad 5 pullup resistor selection.                                 */
3890       __IOM uint32_t PAD6PULL   : 1;            /*!< [16..16] Pad 6 pullup enable                                              */
3891       __IOM uint32_t PAD6INPEN  : 1;            /*!< [17..17] Pad 6 input enable                                               */
3892       __IOM uint32_t PAD6STRNG  : 1;            /*!< [18..18] Pad 6 drive strength                                             */
3893       __IOM uint32_t PAD6FNCSEL : 3;            /*!< [21..19] Pad 6 function select                                            */
3894       __IOM uint32_t PAD6RSEL   : 2;            /*!< [23..22] Pad 6 pullup resistor selection.                                 */
3895       __IOM uint32_t PAD7PULL   : 1;            /*!< [24..24] Pad 7 pullup enable                                              */
3896       __IOM uint32_t PAD7INPEN  : 1;            /*!< [25..25] Pad 7 input enable                                               */
3897       __IOM uint32_t PAD7STRNG  : 1;            /*!< [26..26] Pad 7 drive strength                                             */
3898       __IOM uint32_t PAD7FNCSEL : 3;            /*!< [29..27] Pad 7 function select                                            */
3899             uint32_t            : 2;
3900     } PADREGB_b;
3901   } ;
3902 
3903   union {
3904     __IOM uint32_t PADREGC;                     /*!< (@ 0x00000008) This register controls the pad configuration
3905                                                                     controls for PAD11 through PAD8. Writes
3906                                                                     to this register must be unlocked by the
3907                                                                     PADKEY register.                                           */
3908 
3909     struct {
3910       __IOM uint32_t PAD8PULL   : 1;            /*!< [0..0] Pad 8 pullup enable                                                */
3911       __IOM uint32_t PAD8INPEN  : 1;            /*!< [1..1] Pad 8 input enable                                                 */
3912       __IOM uint32_t PAD8STRNG  : 1;            /*!< [2..2] Pad 8 drive strength                                               */
3913       __IOM uint32_t PAD8FNCSEL : 3;            /*!< [5..3] Pad 8 function select                                              */
3914       __IOM uint32_t PAD8RSEL   : 2;            /*!< [7..6] Pad 8 pullup resistor selection.                                   */
3915       __IOM uint32_t PAD9PULL   : 1;            /*!< [8..8] Pad 9 pullup enable                                                */
3916       __IOM uint32_t PAD9INPEN  : 1;            /*!< [9..9] Pad 9 input enable                                                 */
3917       __IOM uint32_t PAD9STRNG  : 1;            /*!< [10..10] Pad 9 drive strength                                             */
3918       __IOM uint32_t PAD9FNCSEL : 3;            /*!< [13..11] Pad 9 function select                                            */
3919       __IOM uint32_t PAD9RSEL   : 2;            /*!< [15..14] Pad 9 pullup resistor selection                                  */
3920       __IOM uint32_t PAD10PULL  : 1;            /*!< [16..16] Pad 10 pullup enable                                             */
3921       __IOM uint32_t PAD10INPEN : 1;            /*!< [17..17] Pad 10 input enable                                              */
3922       __IOM uint32_t PAD10STRNG : 1;            /*!< [18..18] Pad 10 drive strength                                            */
3923       __IOM uint32_t PAD10FNCSEL : 3;           /*!< [21..19] Pad 10 function select                                           */
3924             uint32_t            : 2;
3925       __IOM uint32_t PAD11PULL  : 1;            /*!< [24..24] Pad 11 pullup enable                                             */
3926       __IOM uint32_t PAD11INPEN : 1;            /*!< [25..25] Pad 11 input enable                                              */
3927       __IOM uint32_t PAD11STRNG : 1;            /*!< [26..26] Pad 11 drive strength                                            */
3928       __IOM uint32_t PAD11FNCSEL : 3;           /*!< [29..27] Pad 11 function select                                           */
3929             uint32_t            : 2;
3930     } PADREGC_b;
3931   } ;
3932 
3933   union {
3934     __IOM uint32_t PADREGD;                     /*!< (@ 0x0000000C) This register controls the pad configuration
3935                                                                     controls for PAD15 through PAD12. Writes
3936                                                                     to this register must be unlocked by the
3937                                                                     PADKEY register.                                           */
3938 
3939     struct {
3940       __IOM uint32_t PAD12PULL  : 1;            /*!< [0..0] Pad 12 pullup enable                                               */
3941       __IOM uint32_t PAD12INPEN : 1;            /*!< [1..1] Pad 12 input enable                                                */
3942       __IOM uint32_t PAD12STRNG : 1;            /*!< [2..2] Pad 12 drive strength                                              */
3943       __IOM uint32_t PAD12FNCSEL : 3;           /*!< [5..3] Pad 12 function select                                             */
3944             uint32_t            : 2;
3945       __IOM uint32_t PAD13PULL  : 1;            /*!< [8..8] Pad 13 pullup enable                                               */
3946       __IOM uint32_t PAD13INPEN : 1;            /*!< [9..9] Pad 13 input enable                                                */
3947       __IOM uint32_t PAD13STRNG : 1;            /*!< [10..10] Pad 13 drive strength                                            */
3948       __IOM uint32_t PAD13FNCSEL : 3;           /*!< [13..11] Pad 13 function select                                           */
3949             uint32_t            : 2;
3950       __IOM uint32_t PAD14PULL  : 1;            /*!< [16..16] Pad 14 pullup enable                                             */
3951       __IOM uint32_t PAD14INPEN : 1;            /*!< [17..17] Pad 14 input enable                                              */
3952       __IOM uint32_t PAD14STRNG : 1;            /*!< [18..18] Pad 14 drive strength                                            */
3953       __IOM uint32_t PAD14FNCSEL : 3;           /*!< [21..19] Pad 14 function select                                           */
3954             uint32_t            : 2;
3955       __IOM uint32_t PAD15PULL  : 1;            /*!< [24..24] Pad 15 pullup enable                                             */
3956       __IOM uint32_t PAD15INPEN : 1;            /*!< [25..25] Pad 15 input enable                                              */
3957       __IOM uint32_t PAD15STRNG : 1;            /*!< [26..26] Pad 15 drive strength                                            */
3958       __IOM uint32_t PAD15FNCSEL : 3;           /*!< [29..27] Pad 15 function select                                           */
3959             uint32_t            : 2;
3960     } PADREGD_b;
3961   } ;
3962 
3963   union {
3964     __IOM uint32_t PADREGE;                     /*!< (@ 0x00000010) This register controls the pad configuration
3965                                                                     controls for PAD19 through PAD16. Writes
3966                                                                     to this register must be unlocked by the
3967                                                                     PADKEY register.                                           */
3968 
3969     struct {
3970       __IOM uint32_t PAD16PULL  : 1;            /*!< [0..0] Pad 16 pullup enable                                               */
3971       __IOM uint32_t PAD16INPEN : 1;            /*!< [1..1] Pad 16 input enable                                                */
3972       __IOM uint32_t PAD16STRNG : 1;            /*!< [2..2] Pad 16 drive strength                                              */
3973       __IOM uint32_t PAD16FNCSEL : 3;           /*!< [5..3] Pad 16 function select                                             */
3974             uint32_t            : 2;
3975       __IOM uint32_t PAD17PULL  : 1;            /*!< [8..8] Pad 17 pullup enable                                               */
3976       __IOM uint32_t PAD17INPEN : 1;            /*!< [9..9] Pad 17 input enable                                                */
3977       __IOM uint32_t PAD17STRNG : 1;            /*!< [10..10] Pad 17 drive strength                                            */
3978       __IOM uint32_t PAD17FNCSEL : 3;           /*!< [13..11] Pad 17 function select                                           */
3979             uint32_t            : 2;
3980       __IOM uint32_t PAD18PULL  : 1;            /*!< [16..16] Pad 18 pullup enable                                             */
3981       __IOM uint32_t PAD18INPEN : 1;            /*!< [17..17] Pad 18 input enable                                              */
3982       __IOM uint32_t PAD18STRNG : 1;            /*!< [18..18] Pad 18 drive strength                                            */
3983       __IOM uint32_t PAD18FNCSEL : 3;           /*!< [21..19] Pad 18 function select                                           */
3984             uint32_t            : 2;
3985       __IOM uint32_t PAD19PULL  : 1;            /*!< [24..24] Pad 19 pullup enable                                             */
3986       __IOM uint32_t PAD19INPEN : 1;            /*!< [25..25] Pad 19 input enable                                              */
3987       __IOM uint32_t PAD19STRNG : 1;            /*!< [26..26] Pad 19 drive strength                                            */
3988       __IOM uint32_t PAD19FNCSEL : 3;           /*!< [29..27] Pad 19 function select                                           */
3989             uint32_t            : 2;
3990     } PADREGE_b;
3991   } ;
3992 
3993   union {
3994     __IOM uint32_t PADREGF;                     /*!< (@ 0x00000014) This register controls the pad configuration
3995                                                                     controls for PAD23 through PAD20. Writes
3996                                                                     to this register must be unlocked by the
3997                                                                     PADKEY register.                                           */
3998 
3999     struct {
4000       __IOM uint32_t PAD20PULL  : 1;            /*!< [0..0] Pad 20 pulldown enable                                             */
4001       __IOM uint32_t PAD20INPEN : 1;            /*!< [1..1] Pad 20 input enable                                                */
4002       __IOM uint32_t PAD20STRNG : 1;            /*!< [2..2] Pad 20 drive strength                                              */
4003       __IOM uint32_t PAD20FNCSEL : 3;           /*!< [5..3] Pad 20 function select                                             */
4004             uint32_t            : 2;
4005       __IOM uint32_t PAD21PULL  : 1;            /*!< [8..8] Pad 21 pullup enable                                               */
4006       __IOM uint32_t PAD21INPEN : 1;            /*!< [9..9] Pad 21 input enable                                                */
4007       __IOM uint32_t PAD21STRNG : 1;            /*!< [10..10] Pad 21 drive strength                                            */
4008       __IOM uint32_t PAD21FNCSEL : 3;           /*!< [13..11] Pad 21 function select                                           */
4009             uint32_t            : 2;
4010       __IOM uint32_t PAD22PULL  : 1;            /*!< [16..16] Pad 22 pullup enable                                             */
4011       __IOM uint32_t PAD22INPEN : 1;            /*!< [17..17] Pad 22 input enable                                              */
4012       __IOM uint32_t PAD22STRNG : 1;            /*!< [18..18] Pad 22 drive strength                                            */
4013       __IOM uint32_t PAD22FNCSEL : 3;           /*!< [21..19] Pad 22 function select                                           */
4014             uint32_t            : 2;
4015       __IOM uint32_t PAD23PULL  : 1;            /*!< [24..24] Pad 23 pullup enable                                             */
4016       __IOM uint32_t PAD23INPEN : 1;            /*!< [25..25] Pad 23 input enable                                              */
4017       __IOM uint32_t PAD23STRNG : 1;            /*!< [26..26] Pad 23 drive strength                                            */
4018       __IOM uint32_t PAD23FNCSEL : 3;           /*!< [29..27] Pad 23 function select                                           */
4019             uint32_t            : 2;
4020     } PADREGF_b;
4021   } ;
4022 
4023   union {
4024     __IOM uint32_t PADREGG;                     /*!< (@ 0x00000018) This register controls the pad configuration
4025                                                                     controls for PAD27 through PAD24. Writes
4026                                                                     to this register must be unlocked by the
4027                                                                     PADKEY register.                                           */
4028 
4029     struct {
4030       __IOM uint32_t PAD24PULL  : 1;            /*!< [0..0] Pad 24 pullup enable                                               */
4031       __IOM uint32_t PAD24INPEN : 1;            /*!< [1..1] Pad 24 input enable                                                */
4032       __IOM uint32_t PAD24STRNG : 1;            /*!< [2..2] Pad 24 drive strength                                              */
4033       __IOM uint32_t PAD24FNCSEL : 3;           /*!< [5..3] Pad 24 function select                                             */
4034             uint32_t            : 2;
4035       __IOM uint32_t PAD25PULL  : 1;            /*!< [8..8] Pad 25 pullup enable                                               */
4036       __IOM uint32_t PAD25INPEN : 1;            /*!< [9..9] Pad 25 input enable                                                */
4037       __IOM uint32_t PAD25STRNG : 1;            /*!< [10..10] Pad 25 drive strength                                            */
4038       __IOM uint32_t PAD25FNCSEL : 3;           /*!< [13..11] Pad 25 function select                                           */
4039       __IOM uint32_t PAD25RSEL  : 2;            /*!< [15..14] Pad 25 pullup resistor selection.                                */
4040       __IOM uint32_t PAD26PULL  : 1;            /*!< [16..16] Pad 26 pullup enable                                             */
4041       __IOM uint32_t PAD26INPEN : 1;            /*!< [17..17] Pad 26 input enable                                              */
4042       __IOM uint32_t PAD26STRNG : 1;            /*!< [18..18] Pad 26 drive strength                                            */
4043       __IOM uint32_t PAD26FNCSEL : 3;           /*!< [21..19] Pad 26 function select                                           */
4044             uint32_t            : 2;
4045       __IOM uint32_t PAD27PULL  : 1;            /*!< [24..24] Pad 27 pullup enable                                             */
4046       __IOM uint32_t PAD27INPEN : 1;            /*!< [25..25] Pad 27 input enable                                              */
4047       __IOM uint32_t PAD27STRNG : 1;            /*!< [26..26] Pad 27 drive strength                                            */
4048       __IOM uint32_t PAD27FNCSEL : 3;           /*!< [29..27] Pad 27 function select                                           */
4049       __IOM uint32_t PAD27RSEL  : 2;            /*!< [31..30] Pad 27 pullup resistor selection.                                */
4050     } PADREGG_b;
4051   } ;
4052 
4053   union {
4054     __IOM uint32_t PADREGH;                     /*!< (@ 0x0000001C) This register controls the pad configuration
4055                                                                     controls for PAD31 through PAD28. Writes
4056                                                                     to this register must be unlocked by the
4057                                                                     PADKEY register.                                           */
4058 
4059     struct {
4060       __IOM uint32_t PAD28PULL  : 1;            /*!< [0..0] Pad 28 pullup enable                                               */
4061       __IOM uint32_t PAD28INPEN : 1;            /*!< [1..1] Pad 28 input enable                                                */
4062       __IOM uint32_t PAD28STRNG : 1;            /*!< [2..2] Pad 28 drive strength                                              */
4063       __IOM uint32_t PAD28FNCSEL : 3;           /*!< [5..3] Pad 28 function select                                             */
4064             uint32_t            : 2;
4065       __IOM uint32_t PAD29PULL  : 1;            /*!< [8..8] Pad 29 pullup enable                                               */
4066       __IOM uint32_t PAD29INPEN : 1;            /*!< [9..9] Pad 29 input enable                                                */
4067       __IOM uint32_t PAD29STRNG : 1;            /*!< [10..10] Pad 29 drive strength                                            */
4068       __IOM uint32_t PAD29FNCSEL : 3;           /*!< [13..11] Pad 29 function select                                           */
4069             uint32_t            : 2;
4070       __IOM uint32_t PAD30PULL  : 1;            /*!< [16..16] Pad 30 pullup enable                                             */
4071       __IOM uint32_t PAD30INPEN : 1;            /*!< [17..17] Pad 30 input enable                                              */
4072       __IOM uint32_t PAD30STRNG : 1;            /*!< [18..18] Pad 30 drive strength                                            */
4073       __IOM uint32_t PAD30FNCSEL : 3;           /*!< [21..19] Pad 30 function select                                           */
4074             uint32_t            : 2;
4075       __IOM uint32_t PAD31PULL  : 1;            /*!< [24..24] Pad 31 pullup enable                                             */
4076       __IOM uint32_t PAD31INPEN : 1;            /*!< [25..25] Pad 31 input enable                                              */
4077       __IOM uint32_t PAD31STRNG : 1;            /*!< [26..26] Pad 31 drive strength                                            */
4078       __IOM uint32_t PAD31FNCSEL : 3;           /*!< [29..27] Pad 31 function select                                           */
4079             uint32_t            : 2;
4080     } PADREGH_b;
4081   } ;
4082 
4083   union {
4084     __IOM uint32_t PADREGI;                     /*!< (@ 0x00000020) This register controls the pad configuration
4085                                                                     controls for PAD35 through PAD32. Writes
4086                                                                     to this register must be unlocked by the
4087                                                                     PADKEY register.                                           */
4088 
4089     struct {
4090       __IOM uint32_t PAD32PULL  : 1;            /*!< [0..0] Pad 32 pullup enable                                               */
4091       __IOM uint32_t PAD32INPEN : 1;            /*!< [1..1] Pad 32 input enable                                                */
4092       __IOM uint32_t PAD32STRNG : 1;            /*!< [2..2] Pad 32 drive strength                                              */
4093       __IOM uint32_t PAD32FNCSEL : 3;           /*!< [5..3] Pad 32 function select                                             */
4094             uint32_t            : 2;
4095       __IOM uint32_t PAD33PULL  : 1;            /*!< [8..8] Pad 33 pullup enable                                               */
4096       __IOM uint32_t PAD33INPEN : 1;            /*!< [9..9] Pad 33 input enable                                                */
4097       __IOM uint32_t PAD33STRNG : 1;            /*!< [10..10] Pad 33 drive strength                                            */
4098       __IOM uint32_t PAD33FNCSEL : 3;           /*!< [13..11] Pad 33 function select                                           */
4099             uint32_t            : 2;
4100       __IOM uint32_t PAD34PULL  : 1;            /*!< [16..16] Pad 34 pullup enable                                             */
4101       __IOM uint32_t PAD34INPEN : 1;            /*!< [17..17] Pad 34 input enable                                              */
4102       __IOM uint32_t PAD34STRNG : 1;            /*!< [18..18] Pad 34 drive strength                                            */
4103       __IOM uint32_t PAD34FNCSEL : 3;           /*!< [21..19] Pad 34 function select                                           */
4104             uint32_t            : 2;
4105       __IOM uint32_t PAD35PULL  : 1;            /*!< [24..24] Pad 35 pullup enable                                             */
4106       __IOM uint32_t PAD35INPEN : 1;            /*!< [25..25] Pad 35 input enable                                              */
4107       __IOM uint32_t PAD35STRNG : 1;            /*!< [26..26] Pad 35 drive strength                                            */
4108       __IOM uint32_t PAD35FNCSEL : 3;           /*!< [29..27] Pad 35 function select                                           */
4109             uint32_t            : 2;
4110     } PADREGI_b;
4111   } ;
4112 
4113   union {
4114     __IOM uint32_t PADREGJ;                     /*!< (@ 0x00000024) This register controls the pad configuration
4115                                                                     controls for PAD39 through PAD36. Writes
4116                                                                     to this register must be unlocked by the
4117                                                                     PADKEY register.                                           */
4118 
4119     struct {
4120       __IOM uint32_t PAD36PULL  : 1;            /*!< [0..0] Pad 36 pullup enable                                               */
4121       __IOM uint32_t PAD36INPEN : 1;            /*!< [1..1] Pad 36 input enable                                                */
4122       __IOM uint32_t PAD36STRNG : 1;            /*!< [2..2] Pad 36 drive strength                                              */
4123       __IOM uint32_t PAD36FNCSEL : 3;           /*!< [5..3] Pad 36 function select                                             */
4124             uint32_t            : 2;
4125       __IOM uint32_t PAD37PULL  : 1;            /*!< [8..8] Pad 37 pullup enable                                               */
4126       __IOM uint32_t PAD37INPEN : 1;            /*!< [9..9] Pad 37 input enable                                                */
4127       __IOM uint32_t PAD37STRNG : 1;            /*!< [10..10] Pad 37 drive strength                                            */
4128       __IOM uint32_t PAD37FNCSEL : 3;           /*!< [13..11] Pad 37 function select                                           */
4129             uint32_t            : 1;
4130       __IOM uint32_t PAD37PWRDN : 1;            /*!< [15..15] Pad 37 VSS power switch enable                                   */
4131       __IOM uint32_t PAD38PULL  : 1;            /*!< [16..16] Pad 38 pullup enable                                             */
4132       __IOM uint32_t PAD38INPEN : 1;            /*!< [17..17] Pad 38 input enable                                              */
4133       __IOM uint32_t PAD38STRNG : 1;            /*!< [18..18] Pad 38 drive strength                                            */
4134       __IOM uint32_t PAD38FNCSEL : 3;           /*!< [21..19] Pad 38 function select                                           */
4135             uint32_t            : 2;
4136       __IOM uint32_t PAD39PULL  : 1;            /*!< [24..24] Pad 39 pullup enable                                             */
4137       __IOM uint32_t PAD39INPEN : 1;            /*!< [25..25] Pad 39 input enable                                              */
4138       __IOM uint32_t PAD39STRNG : 1;            /*!< [26..26] Pad 39 drive strength                                            */
4139       __IOM uint32_t PAD39FNCSEL : 3;           /*!< [29..27] Pad 39 function select                                           */
4140       __IOM uint32_t PAD39RSEL  : 2;            /*!< [31..30] Pad 39 pullup resistor selection.                                */
4141     } PADREGJ_b;
4142   } ;
4143 
4144   union {
4145     __IOM uint32_t PADREGK;                     /*!< (@ 0x00000028) This register controls the pad configuration
4146                                                                     controls for PAD43 through PAD40. Writes
4147                                                                     to this register must be unlocked by the
4148                                                                     PADKEY register.                                           */
4149 
4150     struct {
4151       __IOM uint32_t PAD40PULL  : 1;            /*!< [0..0] Pad 40 pullup enable                                               */
4152       __IOM uint32_t PAD40INPEN : 1;            /*!< [1..1] Pad 40 input enable                                                */
4153       __IOM uint32_t PAD40STRNG : 1;            /*!< [2..2] Pad 40 drive strength                                              */
4154       __IOM uint32_t PAD40FNCSEL : 3;           /*!< [5..3] Pad 40 function select                                             */
4155       __IOM uint32_t PAD40RSEL  : 2;            /*!< [7..6] Pad 40 pullup resistor selection.                                  */
4156       __IOM uint32_t PAD41PULL  : 1;            /*!< [8..8] Pad 41 pullup enable                                               */
4157       __IOM uint32_t PAD41INPEN : 1;            /*!< [9..9] Pad 41 input enable                                                */
4158       __IOM uint32_t PAD41STRNG : 1;            /*!< [10..10] Pad 41 drive strength                                            */
4159       __IOM uint32_t PAD41FNCSEL : 3;           /*!< [13..11] Pad 41 function select                                           */
4160             uint32_t            : 1;
4161       __IOM uint32_t PAD41PWRDN : 1;            /*!< [15..15] Pad 41 power switch enable                                       */
4162       __IOM uint32_t PAD42PULL  : 1;            /*!< [16..16] Pad 42 pullup enable                                             */
4163       __IOM uint32_t PAD42INPEN : 1;            /*!< [17..17] Pad 42 input enable                                              */
4164       __IOM uint32_t PAD42STRNG : 1;            /*!< [18..18] Pad 42 drive strength                                            */
4165       __IOM uint32_t PAD42FNCSEL : 3;           /*!< [21..19] Pad 42 function select                                           */
4166       __IOM uint32_t PAD42RSEL  : 2;            /*!< [23..22] Pad 42 pullup resistor selection.                                */
4167       __IOM uint32_t PAD43PULL  : 1;            /*!< [24..24] Pad 43 pullup enable                                             */
4168       __IOM uint32_t PAD43INPEN : 1;            /*!< [25..25] Pad 43 input enable                                              */
4169       __IOM uint32_t PAD43STRNG : 1;            /*!< [26..26] Pad 43 drive strength                                            */
4170       __IOM uint32_t PAD43FNCSEL : 3;           /*!< [29..27] Pad 43 function select                                           */
4171       __IOM uint32_t PAD43RSEL  : 2;            /*!< [31..30] Pad 43 pullup resistor selection.                                */
4172     } PADREGK_b;
4173   } ;
4174 
4175   union {
4176     __IOM uint32_t PADREGL;                     /*!< (@ 0x0000002C) This register controls the pad configuration
4177                                                                     controls for PAD47 through PAD44. Writes
4178                                                                     to this register must be unlocked by the
4179                                                                     PADKEY register.                                           */
4180 
4181     struct {
4182       __IOM uint32_t PAD44PULL  : 1;            /*!< [0..0] Pad 44 pullup enable                                               */
4183       __IOM uint32_t PAD44INPEN : 1;            /*!< [1..1] Pad 44 input enable                                                */
4184       __IOM uint32_t PAD44STRNG : 1;            /*!< [2..2] Pad 44 drive strength                                              */
4185       __IOM uint32_t PAD44FNCSEL : 3;           /*!< [5..3] Pad 44 function select                                             */
4186             uint32_t            : 2;
4187       __IOM uint32_t PAD45PULL  : 1;            /*!< [8..8] Pad 45 pullup enable                                               */
4188       __IOM uint32_t PAD45INPEN : 1;            /*!< [9..9] Pad 45 input enable                                                */
4189       __IOM uint32_t PAD45STRNG : 1;            /*!< [10..10] Pad 45 drive strength                                            */
4190       __IOM uint32_t PAD45FNCSEL : 3;           /*!< [13..11] Pad 45 function select                                           */
4191             uint32_t            : 2;
4192       __IOM uint32_t PAD46PULL  : 1;            /*!< [16..16] Pad 46 pullup enable                                             */
4193       __IOM uint32_t PAD46INPEN : 1;            /*!< [17..17] Pad 46 input enable                                              */
4194       __IOM uint32_t PAD46STRNG : 1;            /*!< [18..18] Pad 46 drive strength                                            */
4195       __IOM uint32_t PAD46FNCSEL : 3;           /*!< [21..19] Pad 46 function select                                           */
4196             uint32_t            : 2;
4197       __IOM uint32_t PAD47PULL  : 1;            /*!< [24..24] Pad 47 pullup enable                                             */
4198       __IOM uint32_t PAD47INPEN : 1;            /*!< [25..25] Pad 47 input enable                                              */
4199       __IOM uint32_t PAD47STRNG : 1;            /*!< [26..26] Pad 47 drive strength                                            */
4200       __IOM uint32_t PAD47FNCSEL : 3;           /*!< [29..27] Pad 47 function select                                           */
4201             uint32_t            : 2;
4202     } PADREGL_b;
4203   } ;
4204 
4205   union {
4206     __IOM uint32_t PADREGM;                     /*!< (@ 0x00000030) This register controls the pad configuration
4207                                                                     controls for PAD48 through PAD51. Writes
4208                                                                     to this register must be unlocked by the
4209                                                                     PADKEY register.                                           */
4210 
4211     struct {
4212       __IOM uint32_t PAD48PULL  : 1;            /*!< [0..0] Pad 48 pullup enable                                               */
4213       __IOM uint32_t PAD48INPEN : 1;            /*!< [1..1] Pad 48 input enable                                                */
4214       __IOM uint32_t PAD48STRNG : 1;            /*!< [2..2] Pad 48 drive strength                                              */
4215       __IOM uint32_t PAD48FNCSEL : 3;           /*!< [5..3] Pad 48 function select                                             */
4216       __IOM uint32_t PAD48RSEL  : 2;            /*!< [7..6] Pad 48 pullup resistor selection.                                  */
4217       __IOM uint32_t PAD49PULL  : 1;            /*!< [8..8] Pad 49 pullup enable                                               */
4218       __IOM uint32_t PAD49INPEN : 1;            /*!< [9..9] Pad 49 input enable                                                */
4219       __IOM uint32_t PAD49STRNG : 1;            /*!< [10..10] Pad 49 drive strength                                            */
4220       __IOM uint32_t PAD49FNCSEL : 3;           /*!< [13..11] Pad 49 function select                                           */
4221       __IOM uint32_t PAD49RSEL  : 2;            /*!< [15..14] Pad 49 pullup resistor selection.                                */
4222       __IOM uint32_t PAD50PULL  : 1;            /*!< [16..16] Pad 50 pullup enable                                             */
4223       __IOM uint32_t PAD50INPEN : 1;            /*!< [17..17] Pad 50 input enable                                              */
4224       __IOM uint32_t PAD50STRNG : 1;            /*!< [18..18] Pad 50 drive strength                                            */
4225       __IOM uint32_t PAD50FNCSEL : 3;           /*!< [21..19] Pad 50 function select                                           */
4226             uint32_t            : 2;
4227       __IOM uint32_t PAD51PULL  : 1;            /*!< [24..24] Pad 51 pullup enable                                             */
4228       __IOM uint32_t PAD51INPEN : 1;            /*!< [25..25] Pad 51 input enable                                              */
4229       __IOM uint32_t PAD51STRNG : 1;            /*!< [26..26] Pad 51 drive strength                                            */
4230       __IOM uint32_t PAD51FNCSEL : 3;           /*!< [29..27] Pad 51 function select                                           */
4231             uint32_t            : 2;
4232     } PADREGM_b;
4233   } ;
4234 
4235   union {
4236     __IOM uint32_t PADREGN;                     /*!< (@ 0x00000034) This register controls the pad configuration
4237                                                                     controls for PAD52 through PAD55. Writes
4238                                                                     to this register must be unlocked by the
4239                                                                     PADKEY register.                                           */
4240 
4241     struct {
4242       __IOM uint32_t PAD52PULL  : 1;            /*!< [0..0] Pad 52 pullup enable                                               */
4243       __IOM uint32_t PAD52INPEN : 1;            /*!< [1..1] Pad 52 input enable                                                */
4244       __IOM uint32_t PAD52STRNG : 1;            /*!< [2..2] Pad 52 drive strength                                              */
4245       __IOM uint32_t PAD52FNCSEL : 3;           /*!< [5..3] Pad 52 function select                                             */
4246             uint32_t            : 2;
4247       __IOM uint32_t PAD53PULL  : 1;            /*!< [8..8] Pad 53 pullup enable                                               */
4248       __IOM uint32_t PAD53INPEN : 1;            /*!< [9..9] Pad 53 input enable                                                */
4249       __IOM uint32_t PAD53STRNG : 1;            /*!< [10..10] Pad 53 drive strength                                            */
4250       __IOM uint32_t PAD53FNCSEL : 3;           /*!< [13..11] Pad 53 function select                                           */
4251             uint32_t            : 2;
4252       __IOM uint32_t PAD54PULL  : 1;            /*!< [16..16] Pad 54 pullup enable                                             */
4253       __IOM uint32_t PAD54INPEN : 1;            /*!< [17..17] Pad 54 input enable                                              */
4254       __IOM uint32_t PAD54STRNG : 1;            /*!< [18..18] Pad 54 drive strength                                            */
4255       __IOM uint32_t PAD54FNCSEL : 3;           /*!< [21..19] Pad 54 function select                                           */
4256             uint32_t            : 2;
4257       __IOM uint32_t PAD55PULL  : 1;            /*!< [24..24] Pad 55 pullup enable                                             */
4258       __IOM uint32_t PAD55INPEN : 1;            /*!< [25..25] Pad 55 input enable                                              */
4259       __IOM uint32_t PAD55STRNG : 1;            /*!< [26..26] Pad 55 drive strength                                            */
4260       __IOM uint32_t PAD55FNCSEL : 3;           /*!< [29..27] Pad 55 function select                                           */
4261             uint32_t            : 2;
4262     } PADREGN_b;
4263   } ;
4264 
4265   union {
4266     __IOM uint32_t PADREGO;                     /*!< (@ 0x00000038) This register controls the pad configuration
4267                                                                     controls for PAD56 through PAD59. Writes
4268                                                                     to this register must be unlocked by the
4269                                                                     PADKEY register.                                           */
4270 
4271     struct {
4272       __IOM uint32_t PAD56PULL  : 1;            /*!< [0..0] Pad 56 pullup enable                                               */
4273       __IOM uint32_t PAD56INPEN : 1;            /*!< [1..1] Pad 56 input enable                                                */
4274       __IOM uint32_t PAD56STRNG : 1;            /*!< [2..2] Pad 56 drive strength                                              */
4275       __IOM uint32_t PAD56FNCSEL : 3;           /*!< [5..3] Pad 56 function select                                             */
4276             uint32_t            : 2;
4277       __IOM uint32_t PAD57PULL  : 1;            /*!< [8..8] Pad 57 pullup enable                                               */
4278       __IOM uint32_t PAD57INPEN : 1;            /*!< [9..9] Pad 57 input enable                                                */
4279       __IOM uint32_t PAD57STRNG : 1;            /*!< [10..10] Pad 57 drive strength                                            */
4280       __IOM uint32_t PAD57FNCSEL : 3;           /*!< [13..11] Pad 57 function select                                           */
4281             uint32_t            : 2;
4282       __IOM uint32_t PAD58PULL  : 1;            /*!< [16..16] Pad 58 pullup enable                                             */
4283       __IOM uint32_t PAD58INPEN : 1;            /*!< [17..17] Pad 58 input enable                                              */
4284       __IOM uint32_t PAD58STRNG : 1;            /*!< [18..18] Pad 58 drive strength                                            */
4285       __IOM uint32_t PAD58FNCSEL : 3;           /*!< [21..19] Pad 58 function select                                           */
4286             uint32_t            : 2;
4287       __IOM uint32_t PAD59PULL  : 1;            /*!< [24..24] Pad 59 pullup enable                                             */
4288       __IOM uint32_t PAD59INPEN : 1;            /*!< [25..25] Pad 59 input enable                                              */
4289       __IOM uint32_t PAD59STRNG : 1;            /*!< [26..26] Pad 59 drive strength                                            */
4290       __IOM uint32_t PAD59FNCSEL : 3;           /*!< [29..27] Pad 59 function select                                           */
4291             uint32_t            : 2;
4292     } PADREGO_b;
4293   } ;
4294 
4295   union {
4296     __IOM uint32_t PADREGP;                     /*!< (@ 0x0000003C) This register controls the pad configuration
4297                                                                     controls for PAD60 through PAD63. Writes
4298                                                                     to this register must be unlocked by the
4299                                                                     PADKEY register.                                           */
4300 
4301     struct {
4302       __IOM uint32_t PAD60PULL  : 1;            /*!< [0..0] Pad 60 pullup enable                                               */
4303       __IOM uint32_t PAD60INPEN : 1;            /*!< [1..1] Pad 60 input enable                                                */
4304       __IOM uint32_t PAD60STRNG : 1;            /*!< [2..2] Pad 60 drive strength                                              */
4305       __IOM uint32_t PAD60FNCSEL : 3;           /*!< [5..3] Pad 60 function select                                             */
4306             uint32_t            : 2;
4307       __IOM uint32_t PAD61PULL  : 1;            /*!< [8..8] Pad 61 pullup enable                                               */
4308       __IOM uint32_t PAD61INPEN : 1;            /*!< [9..9] Pad 61 input enable                                                */
4309       __IOM uint32_t PAD61STRNG : 1;            /*!< [10..10] Pad 61 drive strength                                            */
4310       __IOM uint32_t PAD61FNCSEL : 3;           /*!< [13..11] Pad 61 function select                                           */
4311             uint32_t            : 2;
4312       __IOM uint32_t PAD62PULL  : 1;            /*!< [16..16] Pad 62 pullup enable                                             */
4313       __IOM uint32_t PAD62INPEN : 1;            /*!< [17..17] Pad 62 input enable                                              */
4314       __IOM uint32_t PAD62STRNG : 1;            /*!< [18..18] Pad 62 drive strength                                            */
4315       __IOM uint32_t PAD62FNCSEL : 3;           /*!< [21..19] Pad 62 function select                                           */
4316             uint32_t            : 2;
4317       __IOM uint32_t PAD63PULL  : 1;            /*!< [24..24] Pad 63 pullup enable                                             */
4318       __IOM uint32_t PAD63INPEN : 1;            /*!< [25..25] Pad 63 input enable                                              */
4319       __IOM uint32_t PAD63STRNG : 1;            /*!< [26..26] Pad 63 drive strength                                            */
4320       __IOM uint32_t PAD63FNCSEL : 3;           /*!< [29..27] Pad 63 function select                                           */
4321             uint32_t            : 2;
4322     } PADREGP_b;
4323   } ;
4324 
4325   union {
4326     __IOM uint32_t PADREGQ;                     /*!< (@ 0x00000040) This register controls the pad configuration
4327                                                                     controls for PAD64 through PAD67. Writes
4328                                                                     to this register must be unlocked by the
4329                                                                     PADKEY register.                                           */
4330 
4331     struct {
4332       __IOM uint32_t PAD64PULL  : 1;            /*!< [0..0] Pad 64 pullup enable                                               */
4333       __IOM uint32_t PAD64INPEN : 1;            /*!< [1..1] Pad 64 input enable                                                */
4334       __IOM uint32_t PAD64STRNG : 1;            /*!< [2..2] Pad 64 drive strength                                              */
4335       __IOM uint32_t PAD64FNCSEL : 3;           /*!< [5..3] Pad 64 function select                                             */
4336             uint32_t            : 2;
4337       __IOM uint32_t PAD65PULL  : 1;            /*!< [8..8] Pad 65 pullup enable                                               */
4338       __IOM uint32_t PAD65INPEN : 1;            /*!< [9..9] Pad 65 input enable                                                */
4339       __IOM uint32_t PAD65STRNG : 1;            /*!< [10..10] Pad 65 drive strength                                            */
4340       __IOM uint32_t PAD65FNCSEL : 3;           /*!< [13..11] Pad 65 function select                                           */
4341             uint32_t            : 2;
4342       __IOM uint32_t PAD66PULL  : 1;            /*!< [16..16] Pad 66 pullup enable                                             */
4343       __IOM uint32_t PAD66INPEN : 1;            /*!< [17..17] Pad 66 input enable                                              */
4344       __IOM uint32_t PAD66STRNG : 1;            /*!< [18..18] Pad 66 drive strength                                            */
4345       __IOM uint32_t PAD66FNCSEL : 3;           /*!< [21..19] Pad 66 function select                                           */
4346             uint32_t            : 2;
4347       __IOM uint32_t PAD67PULL  : 1;            /*!< [24..24] Pad 67 pullup enable                                             */
4348       __IOM uint32_t PAD67INPEN : 1;            /*!< [25..25] Pad 67 input enable                                              */
4349       __IOM uint32_t PAD67STRNG : 1;            /*!< [26..26] Pad 67 drive strength                                            */
4350       __IOM uint32_t PAD67FNCSEL : 3;           /*!< [29..27] Pad 67 function select                                           */
4351             uint32_t            : 2;
4352     } PADREGQ_b;
4353   } ;
4354 
4355   union {
4356     __IOM uint32_t PADREGR;                     /*!< (@ 0x00000044) This register controls the pad configuration
4357                                                                     controls for PAD68 through PAD71. Writes
4358                                                                     to this register must be unlocked by the
4359                                                                     PADKEY register.                                           */
4360 
4361     struct {
4362       __IOM uint32_t PAD68PULL  : 1;            /*!< [0..0] Pad 68 pullup enable                                               */
4363       __IOM uint32_t PAD68INPEN : 1;            /*!< [1..1] Pad 68 input enable                                                */
4364       __IOM uint32_t PAD68STRNG : 1;            /*!< [2..2] Pad 68 drive strength                                              */
4365       __IOM uint32_t PAD68FNCSEL : 3;           /*!< [5..3] Pad 68 function select                                             */
4366             uint32_t            : 2;
4367       __IOM uint32_t PAD69PULL  : 1;            /*!< [8..8] Pad 69 pullup enable                                               */
4368       __IOM uint32_t PAD69INPEN : 1;            /*!< [9..9] Pad 69 input enable                                                */
4369       __IOM uint32_t PAD69STRNG : 1;            /*!< [10..10] Pad 69 drive strength                                            */
4370       __IOM uint32_t PAD69FNCSEL : 3;           /*!< [13..11] Pad 69 function select                                           */
4371             uint32_t            : 2;
4372       __IOM uint32_t PAD70PULL  : 1;            /*!< [16..16] Pad 70 pullup enable                                             */
4373       __IOM uint32_t PAD70INPEN : 1;            /*!< [17..17] Pad 70 input enable                                              */
4374       __IOM uint32_t PAD70STRNG : 1;            /*!< [18..18] Pad 70 drive strength                                            */
4375       __IOM uint32_t PAD70FNCSEL : 3;           /*!< [21..19] Pad 70 function select                                           */
4376             uint32_t            : 2;
4377       __IOM uint32_t PAD71PULL  : 1;            /*!< [24..24] Pad 71 pullup enable                                             */
4378       __IOM uint32_t PAD71INPEN : 1;            /*!< [25..25] Pad 71 input enable                                              */
4379       __IOM uint32_t PAD71STRNG : 1;            /*!< [26..26] Pad 71 drive strength                                            */
4380       __IOM uint32_t PAD71FNCSEL : 3;           /*!< [29..27] Pad 71 function select                                           */
4381             uint32_t            : 2;
4382     } PADREGR_b;
4383   } ;
4384 
4385   union {
4386     __IOM uint32_t PADREGS;                     /*!< (@ 0x00000048) This register controls the pad configuration
4387                                                                     controls for PAD72 through PAD73. Writes
4388                                                                     to this register must be unlocked by the
4389                                                                     PADKEY register.                                           */
4390 
4391     struct {
4392       __IOM uint32_t PAD72PULL  : 1;            /*!< [0..0] Pad 72 pullup enable                                               */
4393       __IOM uint32_t PAD72INPEN : 1;            /*!< [1..1] Pad 72 input enable                                                */
4394       __IOM uint32_t PAD72STRNG : 1;            /*!< [2..2] Pad 72 drive strength                                              */
4395       __IOM uint32_t PAD72FNCSEL : 3;           /*!< [5..3] Pad 72 function select                                             */
4396             uint32_t            : 2;
4397       __IOM uint32_t PAD73PULL  : 1;            /*!< [8..8] Pad 73 pullup enable                                               */
4398       __IOM uint32_t PAD73INPEN : 1;            /*!< [9..9] Pad 73 input enable                                                */
4399       __IOM uint32_t PAD73STRNG : 1;            /*!< [10..10] Pad 73 drive strength                                            */
4400       __IOM uint32_t PAD73FNCSEL : 3;           /*!< [13..11] Pad 73 function select                                           */
4401             uint32_t            : 18;
4402     } PADREGS_b;
4403   } ;
4404 
4405   union {
4406     __IOM uint32_t CFGA;                        /*!< (@ 0x0000004C) GPIO configuration controls for GPIO[7:0]. Writes
4407                                                                     to this register must be unlocked by the
4408                                                                     PADKEY register.                                           */
4409 
4410     struct {
4411       __IOM uint32_t GPIO0INCFG : 1;            /*!< [0..0] GPIO0 input enable.                                                */
4412       __IOM uint32_t GPIO0OUTCFG : 2;           /*!< [2..1] GPIO0 output configuration.                                        */
4413       __IOM uint32_t GPIO0INTD  : 1;            /*!< [3..3] GPIO0 interrupt direction, nCE polarity.                           */
4414       __IOM uint32_t GPIO1INCFG : 1;            /*!< [4..4] GPIO1 input enable.                                                */
4415       __IOM uint32_t GPIO1OUTCFG : 2;           /*!< [6..5] GPIO1 output configuration.                                        */
4416       __IOM uint32_t GPIO1INTD  : 1;            /*!< [7..7] GPIO1 interrupt direction, nCE polarity.                           */
4417       __IOM uint32_t GPIO2INCFG : 1;            /*!< [8..8] GPIO2 input enable.                                                */
4418       __IOM uint32_t GPIO2OUTCFG : 2;           /*!< [10..9] GPIO2 output configuration.                                       */
4419       __IOM uint32_t GPIO2INTD  : 1;            /*!< [11..11] GPIO2 interrupt direction, nCE polarity.                         */
4420       __IOM uint32_t GPIO3INCFG : 1;            /*!< [12..12] GPIO3 input enable.                                              */
4421       __IOM uint32_t GPIO3OUTCFG : 2;           /*!< [14..13] GPIO3 output configuration.                                      */
4422       __IOM uint32_t GPIO3INTD  : 1;            /*!< [15..15] GPIO3 interrupt direction, nCE polarity.                         */
4423       __IOM uint32_t GPIO4INCFG : 1;            /*!< [16..16] GPIO4 input enable.                                              */
4424       __IOM uint32_t GPIO4OUTCFG : 2;           /*!< [18..17] GPIO4 output configuration.                                      */
4425       __IOM uint32_t GPIO4INTD  : 1;            /*!< [19..19] GPIO4 interrupt direction, nCE polarity.                         */
4426       __IOM uint32_t GPIO5INCFG : 1;            /*!< [20..20] GPIO5 input enable.                                              */
4427       __IOM uint32_t GPIO5OUTCFG : 2;           /*!< [22..21] GPIO5 output configuration.                                      */
4428       __IOM uint32_t GPIO5INTD  : 1;            /*!< [23..23] GPIO5 interrupt direction, nCE polarity.                         */
4429       __IOM uint32_t GPIO6INCFG : 1;            /*!< [24..24] GPIO6 input enable.                                              */
4430       __IOM uint32_t GPIO6OUTCFG : 2;           /*!< [26..25] GPIO6 output configuration.                                      */
4431       __IOM uint32_t GPIO6INTD  : 1;            /*!< [27..27] GPIO6 interrupt direction, nCE polarity.                         */
4432       __IOM uint32_t GPIO7INCFG : 1;            /*!< [28..28] GPIO7 input enable.                                              */
4433       __IOM uint32_t GPIO7OUTCFG : 2;           /*!< [30..29] GPIO7 output configuration.                                      */
4434       __IOM uint32_t GPIO7INTD  : 1;            /*!< [31..31] GPIO7 interrupt direction, nCE polarity.                         */
4435     } CFGA_b;
4436   } ;
4437 
4438   union {
4439     __IOM uint32_t CFGB;                        /*!< (@ 0x00000050) GPIO configuration controls for GPIO[15:8]. Writes
4440                                                                     to this register must be unlocked by the
4441                                                                     PADKEY register.                                           */
4442 
4443     struct {
4444       __IOM uint32_t GPIO8INCFG : 1;            /*!< [0..0] GPIO8 input enable.                                                */
4445       __IOM uint32_t GPIO8OUTCFG : 2;           /*!< [2..1] GPIO8 output configuration.                                        */
4446       __IOM uint32_t GPIO8INTD  : 1;            /*!< [3..3] GPIO8 interrupt direction, nCE polarity.                           */
4447       __IOM uint32_t GPIO9INCFG : 1;            /*!< [4..4] GPIO9 input enable.                                                */
4448       __IOM uint32_t GPIO9OUTCFG : 2;           /*!< [6..5] GPIO9 output configuration.                                        */
4449       __IOM uint32_t GPIO9INTD  : 1;            /*!< [7..7] GPIO9 interrupt direction, nCE polarity.                           */
4450       __IOM uint32_t GPIO10INCFG : 1;           /*!< [8..8] GPIO10 input enable.                                               */
4451       __IOM uint32_t GPIO10OUTCFG : 2;          /*!< [10..9] GPIO10 output configuration.                                      */
4452       __IOM uint32_t GPIO10INTD : 1;            /*!< [11..11] GPIO10 interrupt direction, nCE polarity.                        */
4453       __IOM uint32_t GPIO11INCFG : 1;           /*!< [12..12] GPIO11 input enable.                                             */
4454       __IOM uint32_t GPIO11OUTCFG : 2;          /*!< [14..13] GPIO11 output configuration.                                     */
4455       __IOM uint32_t GPIO11INTD : 1;            /*!< [15..15] GPIO11 interrupt direction, nCE polarity.                        */
4456       __IOM uint32_t GPIO12INCFG : 1;           /*!< [16..16] GPIO12 input enable.                                             */
4457       __IOM uint32_t GPIO12OUTCFG : 2;          /*!< [18..17] GPIO12 output configuration.                                     */
4458       __IOM uint32_t GPIO12INTD : 1;            /*!< [19..19] GPIO12 interrupt direction, nCE polarity.                        */
4459       __IOM uint32_t GPIO13INCFG : 1;           /*!< [20..20] GPIO13 input enable.                                             */
4460       __IOM uint32_t GPIO13OUTCFG : 2;          /*!< [22..21] GPIO13 output configuration.                                     */
4461       __IOM uint32_t GPIO13INTD : 1;            /*!< [23..23] GPIO13 interrupt direction, nCE polarity.                        */
4462       __IOM uint32_t GPIO14INCFG : 1;           /*!< [24..24] GPIO14 input enable.                                             */
4463       __IOM uint32_t GPIO14OUTCFG : 2;          /*!< [26..25] GPIO14 output configuration.                                     */
4464       __IOM uint32_t GPIO14INTD : 1;            /*!< [27..27] GPIO14 interrupt direction, nCE polarity.                        */
4465       __IOM uint32_t GPIO15INCFG : 1;           /*!< [28..28] GPIO15 input enable.                                             */
4466       __IOM uint32_t GPIO15OUTCFG : 2;          /*!< [30..29] GPIO15 output configuration.                                     */
4467       __IOM uint32_t GPIO15INTD : 1;            /*!< [31..31] GPIO15 interrupt direction, nCE polarity.                        */
4468     } CFGB_b;
4469   } ;
4470 
4471   union {
4472     __IOM uint32_t CFGC;                        /*!< (@ 0x00000054) GPIO configuration controls for GPIO[23:16].
4473                                                                     Writes to this register must be unlocked
4474                                                                     by the PADKEY register.                                    */
4475 
4476     struct {
4477       __IOM uint32_t GPIO16INCFG : 1;           /*!< [0..0] GPIO16 input enable.                                               */
4478       __IOM uint32_t GPIO16OUTCFG : 2;          /*!< [2..1] GPIO16 output configuration.                                       */
4479       __IOM uint32_t GPIO16INTD : 1;            /*!< [3..3] GPIO16 interrupt direction, nCE polarity.                          */
4480       __IOM uint32_t GPIO17INCFG : 1;           /*!< [4..4] GPIO17 input enable.                                               */
4481       __IOM uint32_t GPIO17OUTCFG : 2;          /*!< [6..5] GPIO17 output configuration.                                       */
4482       __IOM uint32_t GPIO17INTD : 1;            /*!< [7..7] GPIO17 interrupt direction, nCE polarity.                          */
4483       __IOM uint32_t GPIO18INCFG : 1;           /*!< [8..8] GPIO18 input enable.                                               */
4484       __IOM uint32_t GPIO18OUTCFG : 2;          /*!< [10..9] GPIO18 output configuration.                                      */
4485       __IOM uint32_t GPIO18INTD : 1;            /*!< [11..11] GPIO18 interrupt direction, nCE polarity.                        */
4486       __IOM uint32_t GPIO19INCFG : 1;           /*!< [12..12] GPIO19 input enable.                                             */
4487       __IOM uint32_t GPIO19OUTCFG : 2;          /*!< [14..13] GPIO19 output configuration.                                     */
4488       __IOM uint32_t GPIO19INTD : 1;            /*!< [15..15] GPIO19 interrupt direction, nCE polarity.                        */
4489       __IOM uint32_t GPIO20INCFG : 1;           /*!< [16..16] GPIO20 input enable.                                             */
4490       __IOM uint32_t GPIO20OUTCFG : 2;          /*!< [18..17] GPIO20 output configuration.                                     */
4491       __IOM uint32_t GPIO20INTD : 1;            /*!< [19..19] GPIO20 interrupt direction, nCE polarity.                        */
4492       __IOM uint32_t GPIO21INCFG : 1;           /*!< [20..20] GPIO21 input enable.                                             */
4493       __IOM uint32_t GPIO21OUTCFG : 2;          /*!< [22..21] GPIO21 output configuration.                                     */
4494       __IOM uint32_t GPIO21INTD : 1;            /*!< [23..23] GPIO21 interrupt direction, nCE polarity.                        */
4495       __IOM uint32_t GPIO22INCFG : 1;           /*!< [24..24] GPIO22 input enable.                                             */
4496       __IOM uint32_t GPIO22OUTCFG : 2;          /*!< [26..25] GPIO22 output configuration.                                     */
4497       __IOM uint32_t GPIO22INTD : 1;            /*!< [27..27] GPIO22 interrupt direction, nCE polarity.                        */
4498       __IOM uint32_t GPIO23INCFG : 1;           /*!< [28..28] GPIO23 input enable.                                             */
4499       __IOM uint32_t GPIO23OUTCFG : 2;          /*!< [30..29] GPIO23 output configuration.                                     */
4500       __IOM uint32_t GPIO23INTD : 1;            /*!< [31..31] GPIO23 interrupt direction, nCE polarity.                        */
4501     } CFGC_b;
4502   } ;
4503 
4504   union {
4505     __IOM uint32_t CFGD;                        /*!< (@ 0x00000058) GPIO configuration controls for GPIO[31:24].
4506                                                                     Writes to this register must be unlocked
4507                                                                     by the PADKEY register.                                    */
4508 
4509     struct {
4510       __IOM uint32_t GPIO24INCFG : 1;           /*!< [0..0] GPIO24 input enable.                                               */
4511       __IOM uint32_t GPIO24OUTCFG : 2;          /*!< [2..1] GPIO24 output configuration.                                       */
4512       __IOM uint32_t GPIO24INTD : 1;            /*!< [3..3] GPIO24 interrupt direction, nCE polarity.                          */
4513       __IOM uint32_t GPIO25INCFG : 1;           /*!< [4..4] GPIO25 input enable.                                               */
4514       __IOM uint32_t GPIO25OUTCFG : 2;          /*!< [6..5] GPIO25 output configuration.                                       */
4515       __IOM uint32_t GPIO25INTD : 1;            /*!< [7..7] GPIO25 interrupt direction, nCE polarity.                          */
4516       __IOM uint32_t GPIO26INCFG : 1;           /*!< [8..8] GPIO26 input enable.                                               */
4517       __IOM uint32_t GPIO26OUTCFG : 2;          /*!< [10..9] GPIO26 output configuration.                                      */
4518       __IOM uint32_t GPIO26INTD : 1;            /*!< [11..11] GPIO26 interrupt direction, nCE polarity.                        */
4519       __IOM uint32_t GPIO27INCFG : 1;           /*!< [12..12] GPIO27 input enable.                                             */
4520       __IOM uint32_t GPIO27OUTCFG : 2;          /*!< [14..13] GPIO27 output configuration.                                     */
4521       __IOM uint32_t GPIO27INTD : 1;            /*!< [15..15] GPIO27 interrupt direction, nCE polarity.                        */
4522       __IOM uint32_t GPIO28INCFG : 1;           /*!< [16..16] GPIO28 input enable.                                             */
4523       __IOM uint32_t GPIO28OUTCFG : 2;          /*!< [18..17] GPIO28 output configuration.                                     */
4524       __IOM uint32_t GPIO28INTD : 1;            /*!< [19..19] GPIO28 interrupt direction, nCE polarity.                        */
4525       __IOM uint32_t GPIO29INCFG : 1;           /*!< [20..20] GPIO29 input enable.                                             */
4526       __IOM uint32_t GPIO29OUTCFG : 2;          /*!< [22..21] GPIO29 output configuration.                                     */
4527       __IOM uint32_t GPIO29INTD : 1;            /*!< [23..23] GPIO29 interrupt direction, nCE polarity.                        */
4528       __IOM uint32_t GPIO30INCFG : 1;           /*!< [24..24] GPIO30 input enable.                                             */
4529       __IOM uint32_t GPIO30OUTCFG : 2;          /*!< [26..25] GPIO30 output configuration.                                     */
4530       __IOM uint32_t GPIO30INTD : 1;            /*!< [27..27] GPIO30 interrupt direction, nCE polarity.                        */
4531       __IOM uint32_t GPIO31INCFG : 1;           /*!< [28..28] GPIO31 input enable.                                             */
4532       __IOM uint32_t GPIO31OUTCFG : 2;          /*!< [30..29] GPIO31 output configuration.                                     */
4533       __IOM uint32_t GPIO31INTD : 1;            /*!< [31..31] GPIO31 interrupt direction, nCE polarity.                        */
4534     } CFGD_b;
4535   } ;
4536 
4537   union {
4538     __IOM uint32_t CFGE;                        /*!< (@ 0x0000005C) GPIO configuration controls for GPIO[39:32].
4539                                                                     Writes to this register must be unlocked
4540                                                                     by the PADKEY register.                                    */
4541 
4542     struct {
4543       __IOM uint32_t GPIO32INCFG : 1;           /*!< [0..0] GPIO32 input enable.                                               */
4544       __IOM uint32_t GPIO32OUTCFG : 2;          /*!< [2..1] GPIO32 output configuration.                                       */
4545       __IOM uint32_t GPIO32INTD : 1;            /*!< [3..3] GPIO32 interrupt direction, nCE polarity.                          */
4546       __IOM uint32_t GPIO33INCFG : 1;           /*!< [4..4] GPIO33 input enable.                                               */
4547       __IOM uint32_t GPIO33OUTCFG : 2;          /*!< [6..5] GPIO33 output configuration.                                       */
4548       __IOM uint32_t GPIO33INTD : 1;            /*!< [7..7] GPIO33 interrupt direction, nCE polarity.                          */
4549       __IOM uint32_t GPIO34INCFG : 1;           /*!< [8..8] GPIO34 input enable.                                               */
4550       __IOM uint32_t GPIO34OUTCFG : 2;          /*!< [10..9] GPIO34 output configuration.                                      */
4551       __IOM uint32_t GPIO34INTD : 1;            /*!< [11..11] GPIO34 interrupt direction, nCE polarity.                        */
4552       __IOM uint32_t GPIO35INCFG : 1;           /*!< [12..12] GPIO35 input enable.                                             */
4553       __IOM uint32_t GPIO35OUTCFG : 2;          /*!< [14..13] GPIO35 output configuration.                                     */
4554       __IOM uint32_t GPIO35INTD : 1;            /*!< [15..15] GPIO35 interrupt direction, nCE polarity.                        */
4555       __IOM uint32_t GPIO36INCFG : 1;           /*!< [16..16] GPIO36 input enable.                                             */
4556       __IOM uint32_t GPIO36OUTCFG : 2;          /*!< [18..17] GPIO36 output configuration.                                     */
4557       __IOM uint32_t GPIO36INTD : 1;            /*!< [19..19] GPIO36 interrupt direction, nCE polarity.                        */
4558       __IOM uint32_t GPIO37INCFG : 1;           /*!< [20..20] GPIO37 input enable.                                             */
4559       __IOM uint32_t GPIO37OUTCFG : 2;          /*!< [22..21] GPIO37 output configuration.                                     */
4560       __IOM uint32_t GPIO37INTD : 1;            /*!< [23..23] GPIO37 interrupt direction, nCE polarity.                        */
4561       __IOM uint32_t GPIO38INCFG : 1;           /*!< [24..24] GPIO38 input enable.                                             */
4562       __IOM uint32_t GPIO38OUTCFG : 2;          /*!< [26..25] GPIO38 output configuration.                                     */
4563       __IOM uint32_t GPIO38INTD : 1;            /*!< [27..27] GPIO38 interrupt direction, nCE polarity.                        */
4564       __IOM uint32_t GPIO39INCFG : 1;           /*!< [28..28] GPIO39 input enable.                                             */
4565       __IOM uint32_t GPIO39OUTCFG : 2;          /*!< [30..29] GPIO39 output configuration.                                     */
4566       __IOM uint32_t GPIO39INTD : 1;            /*!< [31..31] GPIO39 interrupt direction, nCE polarity.                        */
4567     } CFGE_b;
4568   } ;
4569 
4570   union {
4571     __IOM uint32_t CFGF;                        /*!< (@ 0x00000060) GPIO configuration controls for GPIO[47:40].
4572                                                                     Writes to this register must be unlocked
4573                                                                     by the PADKEY register.                                    */
4574 
4575     struct {
4576       __IOM uint32_t GPIO40INCFG : 1;           /*!< [0..0] GPIO40 input enable.                                               */
4577       __IOM uint32_t GPIO40OUTCFG : 2;          /*!< [2..1] GPIO40 output configuration.                                       */
4578       __IOM uint32_t GPIO40INTD : 1;            /*!< [3..3] GPIO40 interrupt direction, nCE polarity.                          */
4579       __IOM uint32_t GPIO41INCFG : 1;           /*!< [4..4] GPIO41 input enable.                                               */
4580       __IOM uint32_t GPIO41OUTCFG : 2;          /*!< [6..5] GPIO41 output configuration.                                       */
4581       __IOM uint32_t GPIO41INTD : 1;            /*!< [7..7] GPIO41 interrupt direction, nCE polarity.                          */
4582       __IOM uint32_t GPIO42INCFG : 1;           /*!< [8..8] GPIO42 input enable.                                               */
4583       __IOM uint32_t GPIO42OUTCFG : 2;          /*!< [10..9] GPIO42 output configuration.                                      */
4584       __IOM uint32_t GPIO42INTD : 1;            /*!< [11..11] GPIO42 interrupt direction, nCE polarity.                        */
4585       __IOM uint32_t GPIO43INCFG : 1;           /*!< [12..12] GPIO43 input enable.                                             */
4586       __IOM uint32_t GPIO43OUTCFG : 2;          /*!< [14..13] GPIO43 output configuration.                                     */
4587       __IOM uint32_t GPIO43INTD : 1;            /*!< [15..15] GPIO43 interrupt direction, nCE polarity.                        */
4588       __IOM uint32_t GPIO44INCFG : 1;           /*!< [16..16] GPIO44 input enable.                                             */
4589       __IOM uint32_t GPIO44OUTCFG : 2;          /*!< [18..17] GPIO44 output configuration.                                     */
4590       __IOM uint32_t GPIO44INTD : 1;            /*!< [19..19] GPIO44 interrupt direction, nCE polarity.                        */
4591       __IOM uint32_t GPIO45INCFG : 1;           /*!< [20..20] GPIO45 input enable.                                             */
4592       __IOM uint32_t GPIO45OUTCFG : 2;          /*!< [22..21] GPIO45 output configuration.                                     */
4593       __IOM uint32_t GPIO45INTD : 1;            /*!< [23..23] GPIO45 interrupt direction, nCE polarity.                        */
4594       __IOM uint32_t GPIO46INCFG : 1;           /*!< [24..24] GPIO46 input enable.                                             */
4595       __IOM uint32_t GPIO46OUTCFG : 2;          /*!< [26..25] GPIO46 output configuration.                                     */
4596       __IOM uint32_t GPIO46INTD : 1;            /*!< [27..27] GPIO46 interrupt direction, nCE polarity.                        */
4597       __IOM uint32_t GPIO47INCFG : 1;           /*!< [28..28] GPIO47 input enable.                                             */
4598       __IOM uint32_t GPIO47OUTCFG : 2;          /*!< [30..29] GPIO47 output configuration.                                     */
4599       __IOM uint32_t GPIO47INTD : 1;            /*!< [31..31] GPIO47 interrupt direction, nCE polarity.                        */
4600     } CFGF_b;
4601   } ;
4602 
4603   union {
4604     __IOM uint32_t CFGG;                        /*!< (@ 0x00000064) GPIO configuration controls for GPIO[55:48].
4605                                                                     Writes to this register must be unlocked
4606                                                                     by the PADKEY register.                                    */
4607 
4608     struct {
4609       __IOM uint32_t GPIO48INCFG : 1;           /*!< [0..0] GPIO48 input enable.                                               */
4610       __IOM uint32_t GPIO48OUTCFG : 2;          /*!< [2..1] GPIO48 output configuration.                                       */
4611       __IOM uint32_t GPIO48INTD : 1;            /*!< [3..3] GPIO48 interrupt direction, nCE polarity.                          */
4612       __IOM uint32_t GPIO49INCFG : 1;           /*!< [4..4] GPIO49 input enable.                                               */
4613       __IOM uint32_t GPIO49OUTCFG : 2;          /*!< [6..5] GPIO49 output configuration.                                       */
4614       __IOM uint32_t GPIO49INTD : 1;            /*!< [7..7] GPIO49 interrupt direction, nCE polarity.                          */
4615       __IOM uint32_t GPIO50INCFG : 1;           /*!< [8..8] GPIO50 input enable.                                               */
4616       __IOM uint32_t GPIO50OUTCFG : 2;          /*!< [10..9] GPIO50 output configuration.                                      */
4617       __IOM uint32_t GPIO50INTD : 1;            /*!< [11..11] GPIO50 interrupt direction, nCE polarity.                        */
4618       __IOM uint32_t GPIO51INCFG : 1;           /*!< [12..12] GPIO51 input enable.                                             */
4619       __IOM uint32_t GPIO51OUTCFG : 2;          /*!< [14..13] GPIO51 output configuration.                                     */
4620       __IOM uint32_t GPIO51INTD : 1;            /*!< [15..15] GPIO51 interrupt direction, nCE polarity.                        */
4621       __IOM uint32_t GPIO52INCFG : 1;           /*!< [16..16] GPIO52 input enable.                                             */
4622       __IOM uint32_t GPIO52OUTCFG : 2;          /*!< [18..17] GPIO52 output configuration.                                     */
4623       __IOM uint32_t GPIO52INTD : 1;            /*!< [19..19] GPIO52 interrupt direction, nCE polarity.                        */
4624       __IOM uint32_t GPIO53INCFG : 1;           /*!< [20..20] GPIO53 input enable.                                             */
4625       __IOM uint32_t GPIO53OUTCFG : 2;          /*!< [22..21] GPIO53 output configuration.                                     */
4626       __IOM uint32_t GPIO53INTD : 1;            /*!< [23..23] GPIO53 interrupt direction, nCE polarity.                        */
4627       __IOM uint32_t GPIO54INCFG : 1;           /*!< [24..24] GPIO54 input enable.                                             */
4628       __IOM uint32_t GPIO54OUTCFG : 2;          /*!< [26..25] GPIO54 output configuration.                                     */
4629       __IOM uint32_t GPIO54INTD : 1;            /*!< [27..27] GPIO54 interrupt direction, nCE polarity.                        */
4630       __IOM uint32_t GPIO55INCFG : 1;           /*!< [28..28] GPIO55 input enable.                                             */
4631       __IOM uint32_t GPIO55OUTCFG : 2;          /*!< [30..29] GPIO55 output configuration.                                     */
4632       __IOM uint32_t GPIO55INTD : 1;            /*!< [31..31] GPIO55 interrupt direction, nCE polarity.                        */
4633     } CFGG_b;
4634   } ;
4635 
4636   union {
4637     __IOM uint32_t CFGH;                        /*!< (@ 0x00000068) GPIO configuration controls for GPIO[63:56].
4638                                                                     Writes to this register must be unlocked
4639                                                                     by the PADKEY register.                                    */
4640 
4641     struct {
4642       __IOM uint32_t GPIO56INCFG : 1;           /*!< [0..0] GPIO56 input enable.                                               */
4643       __IOM uint32_t GPIO56OUTCFG : 2;          /*!< [2..1] GPIO56 output configuration.                                       */
4644       __IOM uint32_t GPIO56INTD : 1;            /*!< [3..3] GPIO56 interrupt direction, nCE polarity.                          */
4645       __IOM uint32_t GPIO57INCFG : 1;           /*!< [4..4] GPIO57 input enable.                                               */
4646       __IOM uint32_t GPIO57OUTCFG : 2;          /*!< [6..5] GPIO57 output configuration.                                       */
4647       __IOM uint32_t GPIO57INTD : 1;            /*!< [7..7] GPIO57 interrupt direction, nCE polarity.                          */
4648       __IOM uint32_t GPIO58INCFG : 1;           /*!< [8..8] GPIO58 input enable.                                               */
4649       __IOM uint32_t GPIO58OUTCFG : 2;          /*!< [10..9] GPIO58 output configuration.                                      */
4650       __IOM uint32_t GPIO58INTD : 1;            /*!< [11..11] GPIO58 interrupt direction, nCE polarity.                        */
4651       __IOM uint32_t GPIO59INCFG : 1;           /*!< [12..12] GPIO59 input enable.                                             */
4652       __IOM uint32_t GPIO59OUTCFG : 2;          /*!< [14..13] GPIO59 output configuration.                                     */
4653       __IOM uint32_t GPIO59INTD : 1;            /*!< [15..15] GPIO59 interrupt direction, nCE polarity.                        */
4654       __IOM uint32_t GPIO60INCFG : 1;           /*!< [16..16] GPIO60 input enable.                                             */
4655       __IOM uint32_t GPIO60OUTCFG : 2;          /*!< [18..17] GPIO60 output configuration.                                     */
4656       __IOM uint32_t GPIO60INTD : 1;            /*!< [19..19] GPIO60 interrupt direction, nCE polarity.                        */
4657       __IOM uint32_t GPIO61INCFG : 1;           /*!< [20..20] GPIO61 input enable.                                             */
4658       __IOM uint32_t GPIO61OUTCFG : 2;          /*!< [22..21] GPIO61 output configuration.                                     */
4659       __IOM uint32_t GPIO61INTD : 1;            /*!< [23..23] GPIO61 interrupt direction, nCE polarity.                        */
4660       __IOM uint32_t GPIO62INCFG : 1;           /*!< [24..24] GPIO62 input enable.                                             */
4661       __IOM uint32_t GPIO62OUTCFG : 2;          /*!< [26..25] GPIO62 output configuration.                                     */
4662       __IOM uint32_t GPIO62INTD : 1;            /*!< [27..27] GPIO62 interrupt direction, nCE polarity.                        */
4663       __IOM uint32_t GPIO63INCFG : 1;           /*!< [28..28] GPIO63 input enable.                                             */
4664       __IOM uint32_t GPIO63OUTCFG : 2;          /*!< [30..29] GPIO63 output configuration.                                     */
4665       __IOM uint32_t GPIO63INTD : 1;            /*!< [31..31] GPIO63 interrupt direction, nCE polarity.                        */
4666     } CFGH_b;
4667   } ;
4668 
4669   union {
4670     __IOM uint32_t CFGI;                        /*!< (@ 0x0000006C) GPIO configuration controls for GPIO[71:64].
4671                                                                     Writes to this register must be unlocked
4672                                                                     by the PADKEY register.                                    */
4673 
4674     struct {
4675       __IOM uint32_t GPIO64INCFG : 1;           /*!< [0..0] GPIO64 input enable.                                               */
4676       __IOM uint32_t GPIO64OUTCFG : 2;          /*!< [2..1] GPIO64 output configuration.                                       */
4677       __IOM uint32_t GPIO64INTD : 1;            /*!< [3..3] GPIO64 interrupt direction, nCE polarity.                          */
4678       __IOM uint32_t GPIO65INCFG : 1;           /*!< [4..4] GPIO65 input enable.                                               */
4679       __IOM uint32_t GPIO65OUTCFG : 2;          /*!< [6..5] GPIO65 output configuration.                                       */
4680       __IOM uint32_t GPIO65INTD : 1;            /*!< [7..7] GPIO65 interrupt direction, nCE polarity.                          */
4681       __IOM uint32_t GPIO66INCFG : 1;           /*!< [8..8] GPIO66 input enable.                                               */
4682       __IOM uint32_t GPIO66OUTCFG : 2;          /*!< [10..9] GPIO66 output configuration.                                      */
4683       __IOM uint32_t GPIO66INTD : 1;            /*!< [11..11] GPIO66 interrupt direction, nCE polarity.                        */
4684       __IOM uint32_t GPIO67INCFG : 1;           /*!< [12..12] GPIO67 input enable.                                             */
4685       __IOM uint32_t GPIO67OUTCFG : 2;          /*!< [14..13] GPIO67 output configuration.                                     */
4686       __IOM uint32_t GPIO67INTD : 1;            /*!< [15..15] GPIO67 interrupt direction, nCE polarity.                        */
4687       __IOM uint32_t GPIO68INCFG : 1;           /*!< [16..16] GPIO68 input enable.                                             */
4688       __IOM uint32_t GPIO68OUTCFG : 2;          /*!< [18..17] GPIO68 output configuration.                                     */
4689       __IOM uint32_t GPIO68INTD : 1;            /*!< [19..19] GPIO68 interrupt direction, nCE polarity.                        */
4690       __IOM uint32_t GPIO69INCFG : 1;           /*!< [20..20] GPIO69 input enable.                                             */
4691       __IOM uint32_t GPIO69OUTCFG : 2;          /*!< [22..21] GPIO69 output configuration.                                     */
4692       __IOM uint32_t GPIO69INTD : 1;            /*!< [23..23] GPIO69 interrupt direction, nCE polarity.                        */
4693       __IOM uint32_t GPIO70INCFG : 1;           /*!< [24..24] GPIO70 input enable.                                             */
4694       __IOM uint32_t GPIO70OUTCFG : 2;          /*!< [26..25] GPIO70 output configuration.                                     */
4695       __IOM uint32_t GPIO70INTD : 1;            /*!< [27..27] GPIO70 interrupt direction, nCE polarity.                        */
4696       __IOM uint32_t GPIO71INCFG : 1;           /*!< [28..28] GPIO71 input enable.                                             */
4697       __IOM uint32_t GPIO71OUTCFG : 2;          /*!< [30..29] GPIO71 output configuration.                                     */
4698       __IOM uint32_t GPIO71INTD : 1;            /*!< [31..31] GPIO71 interrupt direction, nCE polarity.                        */
4699     } CFGI_b;
4700   } ;
4701 
4702   union {
4703     __IOM uint32_t CFGJ;                        /*!< (@ 0x00000070) GPIO configuration controls for GPIO[73:72].
4704                                                                     Writes to this register must be unlocked
4705                                                                     by the PADKEY register.                                    */
4706 
4707     struct {
4708       __IOM uint32_t GPIO72INCFG : 1;           /*!< [0..0] GPIO72 input enable.                                               */
4709       __IOM uint32_t GPIO72OUTCFG : 2;          /*!< [2..1] GPIO72 output configuration.                                       */
4710       __IOM uint32_t GPIO72INTD : 1;            /*!< [3..3] GPIO72 interrupt direction, nCE polarity.                          */
4711       __IOM uint32_t GPIO73INCFG : 1;           /*!< [4..4] GPIO73 input enable.                                               */
4712       __IOM uint32_t GPIO73OUTCFG : 2;          /*!< [6..5] GPIO73 output configuration.                                       */
4713       __IOM uint32_t GPIO73INTD : 1;            /*!< [7..7] GPIO73 interrupt direction, nCE polarity.                          */
4714             uint32_t            : 24;
4715     } CFGJ_b;
4716   } ;
4717 
4718   union {
4719     __IOM uint32_t PADKEY;                      /*!< (@ 0x00000074) Lock state of the PINCFG and GPIO configuration
4720                                                                     registers. Write a value of 0x73 to unlock
4721                                                                     write access to the PAD and GPIO configuration
4722                                                                     registers. Write any other value to lock
4723                                                                     access to PAD and GPIO registers. This register
4724                                                                     also indicates lock status when read. When
4725                                                                     in the unlocked state (i.e. 0x73 has been
4726                                                                     written), it reads as 1. When in the locked
4727                                                                     state, it reads as 0.                                      */
4728 
4729     struct {
4730       __IOM uint32_t PADKEY     : 32;           /*!< [31..0] Key register value.                                               */
4731     } PADKEY_b;
4732   } ;
4733   __IM  uint32_t  RESERVED[2];
4734 
4735   union {
4736     __IOM uint32_t RDA;                         /*!< (@ 0x00000080) GPIO Input A (31-0)                                        */
4737 
4738     struct {
4739       __IOM uint32_t RDA        : 32;           /*!< [31..0] GPIO31-0 read data.                                               */
4740     } RDA_b;
4741   } ;
4742 
4743   union {
4744     __IOM uint32_t RDB;                         /*!< (@ 0x00000084) GPIO Input B (63-32)                                       */
4745 
4746     struct {
4747       __IOM uint32_t RDB        : 32;           /*!< [31..0] GPIO63-32 read data.                                              */
4748     } RDB_b;
4749   } ;
4750 
4751   union {
4752     __IOM uint32_t RDC;                         /*!< (@ 0x00000088) GPIO Input C (73-64)                                       */
4753 
4754     struct {
4755       __IOM uint32_t RDC        : 10;           /*!< [9..0] GPIO73-64 read data.                                               */
4756             uint32_t            : 22;
4757     } RDC_b;
4758   } ;
4759 
4760   union {
4761     __IOM uint32_t WTA;                         /*!< (@ 0x0000008C) GPIO Output A (31-0)                                       */
4762 
4763     struct {
4764       __IOM uint32_t WTA        : 32;           /*!< [31..0] GPIO31-0 write data.                                              */
4765     } WTA_b;
4766   } ;
4767 
4768   union {
4769     __IOM uint32_t WTB;                         /*!< (@ 0x00000090) GPIO Output B (63-32)                                      */
4770 
4771     struct {
4772       __IOM uint32_t WTB        : 32;           /*!< [31..0] GPIO63-32 write data.                                             */
4773     } WTB_b;
4774   } ;
4775 
4776   union {
4777     __IOM uint32_t WTC;                         /*!< (@ 0x00000094) GPIO Output C (73-64)                                      */
4778 
4779     struct {
4780       __IOM uint32_t WTC        : 10;           /*!< [9..0] GPIO73-64 write data.                                              */
4781             uint32_t            : 22;
4782     } WTC_b;
4783   } ;
4784 
4785   union {
4786     __IOM uint32_t WTSA;                        /*!< (@ 0x00000098) GPIO Output A Set (31-0)                                   */
4787 
4788     struct {
4789       __IOM uint32_t WTSA       : 32;           /*!< [31..0] Set the GPIO31-0 write data.                                      */
4790     } WTSA_b;
4791   } ;
4792 
4793   union {
4794     __IOM uint32_t WTSB;                        /*!< (@ 0x0000009C) GPIO Output B Set (63-32)                                  */
4795 
4796     struct {
4797       __IOM uint32_t WTSB       : 32;           /*!< [31..0] Set the GPIO63-32 write data.                                     */
4798     } WTSB_b;
4799   } ;
4800 
4801   union {
4802     __IOM uint32_t WTSC;                        /*!< (@ 0x000000A0) GPIO Output C Set (73-64)                                  */
4803 
4804     struct {
4805       __IOM uint32_t WTSC       : 10;           /*!< [9..0] Set the GPIO73-64 write data.                                      */
4806             uint32_t            : 22;
4807     } WTSC_b;
4808   } ;
4809 
4810   union {
4811     __IOM uint32_t WTCA;                        /*!< (@ 0x000000A4) GPIO Output A Clear (31-0)                                 */
4812 
4813     struct {
4814       __IOM uint32_t WTCA       : 32;           /*!< [31..0] Clear the GPIO31-0 write data.                                    */
4815     } WTCA_b;
4816   } ;
4817 
4818   union {
4819     __IOM uint32_t WTCB;                        /*!< (@ 0x000000A8) GPIO Output B Clear (63-32)                                */
4820 
4821     struct {
4822       __IOM uint32_t WTCB       : 32;           /*!< [31..0] Clear the GPIO63-32 write data.                                   */
4823     } WTCB_b;
4824   } ;
4825 
4826   union {
4827     __IOM uint32_t WTCC;                        /*!< (@ 0x000000AC) GPIO Output C Clear (73-64)                                */
4828 
4829     struct {
4830       __IOM uint32_t WTCB       : 10;           /*!< [9..0] Clear the GPIO73-64 write data.                                    */
4831             uint32_t            : 22;
4832     } WTCC_b;
4833   } ;
4834 
4835   union {
4836     __IOM uint32_t ENA;                         /*!< (@ 0x000000B0) GPIO Enable A (31-0)                                       */
4837 
4838     struct {
4839       __IOM uint32_t ENA        : 32;           /*!< [31..0] GPIO31-0 output enables                                           */
4840     } ENA_b;
4841   } ;
4842 
4843   union {
4844     __IOM uint32_t ENB;                         /*!< (@ 0x000000B4) GPIO Enable B (63-32)                                      */
4845 
4846     struct {
4847       __IOM uint32_t ENB        : 32;           /*!< [31..0] GPIO63-32 output enables                                          */
4848     } ENB_b;
4849   } ;
4850 
4851   union {
4852     __IOM uint32_t ENC;                         /*!< (@ 0x000000B8) GPIO Enable C (73-64)                                      */
4853 
4854     struct {
4855       __IOM uint32_t ENC        : 10;           /*!< [9..0] GPIO73-64 output enables                                           */
4856             uint32_t            : 22;
4857     } ENC_b;
4858   } ;
4859 
4860   union {
4861     __IOM uint32_t ENSA;                        /*!< (@ 0x000000BC) GPIO Enable A Set (31-0)                                   */
4862 
4863     struct {
4864       __IOM uint32_t ENSA       : 32;           /*!< [31..0] Set the GPIO31-0 output enables                                   */
4865     } ENSA_b;
4866   } ;
4867 
4868   union {
4869     __IOM uint32_t ENSB;                        /*!< (@ 0x000000C0) GPIO Enable B Set (63-32)                                  */
4870 
4871     struct {
4872       __IOM uint32_t ENSB       : 32;           /*!< [31..0] Set the GPIO63-32 output enables                                  */
4873     } ENSB_b;
4874   } ;
4875 
4876   union {
4877     __IOM uint32_t ENSC;                        /*!< (@ 0x000000C4) GPIO Enable C Set (73-64)                                  */
4878 
4879     struct {
4880       __IOM uint32_t ENSC       : 10;           /*!< [9..0] Set the GPIO73-64 output enables                                   */
4881             uint32_t            : 22;
4882     } ENSC_b;
4883   } ;
4884 
4885   union {
4886     __IOM uint32_t ENCA;                        /*!< (@ 0x000000C8) GPIO Enable A Clear (31-0)                                 */
4887 
4888     struct {
4889       __IOM uint32_t ENCA       : 32;           /*!< [31..0] Clear the GPIO31-0 output enables                                 */
4890     } ENCA_b;
4891   } ;
4892 
4893   union {
4894     __IOM uint32_t ENCB;                        /*!< (@ 0x000000CC) GPIO Enable B Clear (63-32)                                */
4895 
4896     struct {
4897       __IOM uint32_t ENCB       : 32;           /*!< [31..0] Clear the GPIO49-32 output enables                                */
4898     } ENCB_b;
4899   } ;
4900 
4901   union {
4902     __IOM uint32_t ENCC;                        /*!< (@ 0x000000D0) GPIO Enable C Clear (73-64)                                */
4903 
4904     struct {
4905       __IOM uint32_t ENCC       : 10;           /*!< [9..0] Clear the GPIO73-64 output enables                                 */
4906             uint32_t            : 22;
4907     } ENCC_b;
4908   } ;
4909 
4910   union {
4911     __IOM uint32_t STMRCAP;                     /*!< (@ 0x000000D4) STIMER Capture trigger select and enable.                  */
4912 
4913     struct {
4914       __IOM uint32_t STSEL0     : 7;            /*!< [6..0] STIMER Capture 0 Select.                                           */
4915       __IOM uint32_t STPOL0     : 1;            /*!< [7..7] STIMER Capture 0 Polarity.                                         */
4916       __IOM uint32_t STSEL1     : 7;            /*!< [14..8] STIMER Capture 1 Select.                                          */
4917       __IOM uint32_t STPOL1     : 1;            /*!< [15..15] STIMER Capture 1 Polarity.                                       */
4918       __IOM uint32_t STSEL2     : 7;            /*!< [22..16] STIMER Capture 2 Select.                                         */
4919       __IOM uint32_t STPOL2     : 1;            /*!< [23..23] STIMER Capture 2 Polarity.                                       */
4920       __IOM uint32_t STSEL3     : 7;            /*!< [30..24] STIMER Capture 3 Select.                                         */
4921       __IOM uint32_t STPOL3     : 1;            /*!< [31..31] STIMER Capture 3 Polarity.                                       */
4922     } STMRCAP_b;
4923   } ;
4924 
4925   union {
4926     __IOM uint32_t IOM0IRQ;                     /*!< (@ 0x000000D8) IOMSTR0 IRQ select for flow control.                       */
4927 
4928     struct {
4929       __IOM uint32_t IOM0IRQ    : 7;            /*!< [6..0] IOMSTR0 IRQ pad select.                                            */
4930             uint32_t            : 25;
4931     } IOM0IRQ_b;
4932   } ;
4933 
4934   union {
4935     __IOM uint32_t IOM1IRQ;                     /*!< (@ 0x000000DC) IOMSTR1 IRQ select for flow control.                       */
4936 
4937     struct {
4938       __IOM uint32_t IOM1IRQ    : 7;            /*!< [6..0] IOMSTR1 IRQ pad select.                                            */
4939             uint32_t            : 25;
4940     } IOM1IRQ_b;
4941   } ;
4942 
4943   union {
4944     __IOM uint32_t IOM2IRQ;                     /*!< (@ 0x000000E0) IOMSTR2 IRQ select for flow control.                       */
4945 
4946     struct {
4947       __IOM uint32_t IOM2IRQ    : 7;            /*!< [6..0] IOMSTR2 IRQ pad select.                                            */
4948             uint32_t            : 25;
4949     } IOM2IRQ_b;
4950   } ;
4951 
4952   union {
4953     __IOM uint32_t IOM3IRQ;                     /*!< (@ 0x000000E4) IOMSTR3 IRQ select for flow control.                       */
4954 
4955     struct {
4956       __IOM uint32_t IOM3IRQ    : 7;            /*!< [6..0] IOMSTR3 IRQ pad select.                                            */
4957             uint32_t            : 25;
4958     } IOM3IRQ_b;
4959   } ;
4960 
4961   union {
4962     __IOM uint32_t IOM4IRQ;                     /*!< (@ 0x000000E8) IOMSTR4 IRQ select for flow control.                       */
4963 
4964     struct {
4965       __IOM uint32_t IOM4IRQ    : 7;            /*!< [6..0] IOMSTR4 IRQ pad select.                                            */
4966             uint32_t            : 25;
4967     } IOM4IRQ_b;
4968   } ;
4969 
4970   union {
4971     __IOM uint32_t IOM5IRQ;                     /*!< (@ 0x000000EC) IOMSTR5 IRQ select for flow control.                       */
4972 
4973     struct {
4974       __IOM uint32_t IOM5IRQ    : 7;            /*!< [6..0] IOMSTR5 IRQ pad select.                                            */
4975             uint32_t            : 25;
4976     } IOM5IRQ_b;
4977   } ;
4978 
4979   union {
4980     __IOM uint32_t BLEIFIRQ;                    /*!< (@ 0x000000F0) BLE IF IRQ select for flow control.                        */
4981 
4982     struct {
4983       __IOM uint32_t BLEIFIRQ   : 7;            /*!< [6..0] BLEIF IRQ pad select.                                              */
4984             uint32_t            : 25;
4985     } BLEIFIRQ_b;
4986   } ;
4987 
4988   union {
4989     __IOM uint32_t GPIOOBS;                     /*!< (@ 0x000000F4) GPIO Observation mode sample register                      */
4990 
4991     struct {
4992       __IOM uint32_t OBS_DATA   : 16;           /*!< [15..0] Sample of the data output on the GPIO observation port.
4993                                                      May have sampling non-synchronization issues, as the data
4994                                                      is not synchronized to the read operation. Intended for
4995                                                      debug purposes only                                                       */
4996             uint32_t            : 16;
4997     } GPIOOBS_b;
4998   } ;
4999 
5000   union {
5001     __IOM uint32_t ALTPADCFGA;                  /*!< (@ 0x000000F8) This register has additional configuration control
5002                                                                     for pads [3:0]                                             */
5003 
5004     struct {
5005       __IOM uint32_t PAD0_DS1   : 1;            /*!< [0..0] Pad 0 high order drive strength selection. Used in conjunction
5006                                                      with PAD0STRNG field to set the pad drive strength.                       */
5007             uint32_t            : 3;
5008       __IOM uint32_t PAD0_SR    : 1;            /*!< [4..4] Pad 3 slew rate selection.                                         */
5009             uint32_t            : 3;
5010       __IOM uint32_t PAD1_DS1   : 1;            /*!< [8..8] Pad 1 high order drive strength selection. Used in conjunction
5011                                                      with PAD1STRNG field to set the pad drive strength.                       */
5012             uint32_t            : 3;
5013       __IOM uint32_t PAD1_SR    : 1;            /*!< [12..12] Pad 3 slew rate selection.                                       */
5014             uint32_t            : 3;
5015       __IOM uint32_t PAD2_DS1   : 1;            /*!< [16..16] Pad 2 high order drive strength selection. Used in
5016                                                      conjunction with PAD2STRNG field to set the pad drive strength.           */
5017             uint32_t            : 3;
5018       __IOM uint32_t PAD2_SR    : 1;            /*!< [20..20] Pad 3 slew rate selection.                                       */
5019             uint32_t            : 3;
5020       __IOM uint32_t PAD3_DS1   : 1;            /*!< [24..24] Pad 3 high order drive strength selection. Used in
5021                                                      conjunction with PAD3STRNG field to set the pad drive strength.           */
5022             uint32_t            : 3;
5023       __IOM uint32_t PAD3_SR    : 1;            /*!< [28..28] Pad 3 slew rate selection.                                       */
5024             uint32_t            : 3;
5025     } ALTPADCFGA_b;
5026   } ;
5027 
5028   union {
5029     __IOM uint32_t ALTPADCFGB;                  /*!< (@ 0x000000FC) This register has additional configuration control
5030                                                                     for pads [7:4]                                             */
5031 
5032     struct {
5033       __IOM uint32_t PAD4_DS1   : 1;            /*!< [0..0] Pad 4 high order drive strength selection. Used in conjunction
5034                                                      with PAD4STRNG field to set the pad drive strength.                       */
5035             uint32_t            : 3;
5036       __IOM uint32_t PAD4_SR    : 1;            /*!< [4..4] Pad 7 slew rate selection.                                         */
5037             uint32_t            : 3;
5038       __IOM uint32_t PAD5_DS1   : 1;            /*!< [8..8] Pad 5 high order drive strength selection. Used in conjunction
5039                                                      with PAD5STRNG field to set the pad drive strength.                       */
5040             uint32_t            : 3;
5041       __IOM uint32_t PAD5_SR    : 1;            /*!< [12..12] Pad 7 slew rate selection.                                       */
5042             uint32_t            : 3;
5043       __IOM uint32_t PAD6_DS1   : 1;            /*!< [16..16] Pad 6 high order drive strength selection. Used in
5044                                                      conjunction with PAD6STRNG field to set the pad drive strength.           */
5045             uint32_t            : 3;
5046       __IOM uint32_t PAD6_SR    : 1;            /*!< [20..20] Pad 7 slew rate selection.                                       */
5047             uint32_t            : 3;
5048       __IOM uint32_t PAD7_DS1   : 1;            /*!< [24..24] Pad 7 high order drive strength selection. Used in
5049                                                      conjunction with PAD7STRNG field to set the pad drive strength.           */
5050             uint32_t            : 3;
5051       __IOM uint32_t PAD7_SR    : 1;            /*!< [28..28] Pad 7 slew rate selection.                                       */
5052             uint32_t            : 3;
5053     } ALTPADCFGB_b;
5054   } ;
5055 
5056   union {
5057     __IOM uint32_t ALTPADCFGC;                  /*!< (@ 0x00000100) This register has additional configuration control
5058                                                                     for pads [11:8]                                            */
5059 
5060     struct {
5061       __IOM uint32_t PAD8_DS1   : 1;            /*!< [0..0] Pad 8 high order drive strength selection. Used in conjunction
5062                                                      with PAD8STRNG field to set the pad drive strength.                       */
5063             uint32_t            : 3;
5064       __IOM uint32_t PAD8_SR    : 1;            /*!< [4..4] Pad 11 slew rate selection.                                        */
5065             uint32_t            : 3;
5066       __IOM uint32_t PAD9_DS1   : 1;            /*!< [8..8] Pad 9 high order drive strength selection. Used in conjunction
5067                                                      with PAD9STRNG field to set the pad drive strength.                       */
5068             uint32_t            : 3;
5069       __IOM uint32_t PAD9_SR    : 1;            /*!< [12..12] Pad 11 slew rate selection.                                      */
5070             uint32_t            : 3;
5071       __IOM uint32_t PAD10_DS1  : 1;            /*!< [16..16] Pad 10 high order drive strength selection. Used in
5072                                                      conjunction with PAD10STRNG field to set the pad drive
5073                                                      strength.                                                                 */
5074             uint32_t            : 3;
5075       __IOM uint32_t PAD10_SR   : 1;            /*!< [20..20] Pad 11 slew rate selection.                                      */
5076             uint32_t            : 3;
5077       __IOM uint32_t PAD11_DS1  : 1;            /*!< [24..24] Pad 11 high order drive strength selection. Used in
5078                                                      conjunction with PAD11STRNG field to set the pad drive
5079                                                      strength.                                                                 */
5080             uint32_t            : 3;
5081       __IOM uint32_t PAD11_SR   : 1;            /*!< [28..28] Pad 11 slew rate selection.                                      */
5082             uint32_t            : 3;
5083     } ALTPADCFGC_b;
5084   } ;
5085 
5086   union {
5087     __IOM uint32_t ALTPADCFGD;                  /*!< (@ 0x00000104) This register has additional configuration control
5088                                                                     for pads [15:12]                                           */
5089 
5090     struct {
5091       __IOM uint32_t PAD12_DS1  : 1;            /*!< [0..0] Pad 12 high order drive strength selection. Used in conjunction
5092                                                      with PAD12STRNG field to set the pad drive strength.                      */
5093             uint32_t            : 3;
5094       __IOM uint32_t PAD12_SR   : 1;            /*!< [4..4] Pad 15 slew rate selection.                                        */
5095             uint32_t            : 3;
5096       __IOM uint32_t PAD13_DS1  : 1;            /*!< [8..8] Pad 13 high order drive strength selection. Used in conjunction
5097                                                      with PAD13STRNG field to set the pad drive strength.                      */
5098             uint32_t            : 3;
5099       __IOM uint32_t PAD13_SR   : 1;            /*!< [12..12] Pad 15 slew rate selection.                                      */
5100             uint32_t            : 3;
5101       __IOM uint32_t PAD14_DS1  : 1;            /*!< [16..16] Pad 14 high order drive strength selection. Used in
5102                                                      conjunction with PAD14STRNG field to set the pad drive
5103                                                      strength.                                                                 */
5104             uint32_t            : 3;
5105       __IOM uint32_t PAD14_SR   : 1;            /*!< [20..20] Pad 15 slew rate selection.                                      */
5106             uint32_t            : 3;
5107       __IOM uint32_t PAD15_DS1  : 1;            /*!< [24..24] Pad 15 high order drive strength selection. Used in
5108                                                      conjunction with PAD15STRNG field to set the pad drive
5109                                                      strength.                                                                 */
5110             uint32_t            : 3;
5111       __IOM uint32_t PAD15_SR   : 1;            /*!< [28..28] Pad 15 slew rate selection.                                      */
5112             uint32_t            : 3;
5113     } ALTPADCFGD_b;
5114   } ;
5115 
5116   union {
5117     __IOM uint32_t ALTPADCFGE;                  /*!< (@ 0x00000108) This register has additional configuration control
5118                                                                     for pads [19:16]                                           */
5119 
5120     struct {
5121       __IOM uint32_t PAD16_DS1  : 1;            /*!< [0..0] Pad 16 high order drive strength selection. Used in conjunction
5122                                                      with PAD16STRNG field to set the pad drive strength.                      */
5123             uint32_t            : 3;
5124       __IOM uint32_t PAD16_SR   : 1;            /*!< [4..4] Pad 19 slew rate selection.                                        */
5125             uint32_t            : 3;
5126       __IOM uint32_t PAD17_DS1  : 1;            /*!< [8..8] Pad 17 high order drive strength selection. Used in conjunction
5127                                                      with PAD17STRNG field to set the pad drive strength.                      */
5128             uint32_t            : 3;
5129       __IOM uint32_t PAD17_SR   : 1;            /*!< [12..12] Pad 19 slew rate selection.                                      */
5130             uint32_t            : 3;
5131       __IOM uint32_t PAD18_DS1  : 1;            /*!< [16..16] Pad 18 high order drive strength selection. Used in
5132                                                      conjunction with PAD18STRNG field to set the pad drive
5133                                                      strength.                                                                 */
5134             uint32_t            : 3;
5135       __IOM uint32_t PAD18_SR   : 1;            /*!< [20..20] Pad 19 slew rate selection.                                      */
5136             uint32_t            : 3;
5137       __IOM uint32_t PAD19_DS1  : 1;            /*!< [24..24] Pad 19 high order drive strength selection. Used in
5138                                                      conjunction with PAD19STRNG field to set the pad drive
5139                                                      strength.                                                                 */
5140             uint32_t            : 3;
5141       __IOM uint32_t PAD19_SR   : 1;            /*!< [28..28] Pad 19 slew rate selection.                                      */
5142             uint32_t            : 3;
5143     } ALTPADCFGE_b;
5144   } ;
5145 
5146   union {
5147     __IOM uint32_t ALTPADCFGF;                  /*!< (@ 0x0000010C) This register has additional configuration control
5148                                                                     for pads [23:20]                                           */
5149 
5150     struct {
5151       __IOM uint32_t PAD20_DS1  : 1;            /*!< [0..0] Pad 20 high order drive strength selection. Used in conjunction
5152                                                      with PAD20STRNG field to set the pad drive strength.                      */
5153             uint32_t            : 3;
5154       __IOM uint32_t PAD20_SR   : 1;            /*!< [4..4] Pad 23 slew rate selection.                                        */
5155             uint32_t            : 3;
5156       __IOM uint32_t PAD21_DS1  : 1;            /*!< [8..8] Pad 21 high order drive strength selection. Used in conjunction
5157                                                      with PAD21STRNG field to set the pad drive strength.                      */
5158             uint32_t            : 3;
5159       __IOM uint32_t PAD21_SR   : 1;            /*!< [12..12] Pad 23 slew rate selection.                                      */
5160             uint32_t            : 3;
5161       __IOM uint32_t PAD22_DS1  : 1;            /*!< [16..16] Pad 22 high order drive strength selection. Used in
5162                                                      conjunction with PAD22STRNG field to set the pad drive
5163                                                      strength.                                                                 */
5164             uint32_t            : 3;
5165       __IOM uint32_t PAD22_SR   : 1;            /*!< [20..20] Pad 23 slew rate selection.                                      */
5166             uint32_t            : 3;
5167       __IOM uint32_t PAD23_DS1  : 1;            /*!< [24..24] Pad 23 high order drive strength selection. Used in
5168                                                      conjunction with PAD23STRNG field to set the pad drive
5169                                                      strength.                                                                 */
5170             uint32_t            : 3;
5171       __IOM uint32_t PAD23_SR   : 1;            /*!< [28..28] Pad 23 slew rate selection.                                      */
5172             uint32_t            : 3;
5173     } ALTPADCFGF_b;
5174   } ;
5175 
5176   union {
5177     __IOM uint32_t ALTPADCFGG;                  /*!< (@ 0x00000110) This register has additional configuration control
5178                                                                     for pads [27:24]                                           */
5179 
5180     struct {
5181       __IOM uint32_t PAD24_DS1  : 1;            /*!< [0..0] Pad 24 high order drive strength selection. Used in conjunction
5182                                                      with PAD24STRNG field to set the pad drive strength.                      */
5183             uint32_t            : 3;
5184       __IOM uint32_t PAD24_SR   : 1;            /*!< [4..4] Pad 27 slew rate selection.                                        */
5185             uint32_t            : 3;
5186       __IOM uint32_t PAD25_DS1  : 1;            /*!< [8..8] Pad 25 high order drive strength selection. Used in conjunction
5187                                                      with PAD25STRNG field to set the pad drive strength.                      */
5188             uint32_t            : 3;
5189       __IOM uint32_t PAD25_SR   : 1;            /*!< [12..12] Pad 27 slew rate selection.                                      */
5190             uint32_t            : 3;
5191       __IOM uint32_t PAD26_DS1  : 1;            /*!< [16..16] Pad 26 high order drive strength selection. Used in
5192                                                      conjunction with PAD26STRNG field to set the pad drive
5193                                                      strength.                                                                 */
5194             uint32_t            : 3;
5195       __IOM uint32_t PAD26_SR   : 1;            /*!< [20..20] Pad 27 slew rate selection.                                      */
5196             uint32_t            : 3;
5197       __IOM uint32_t PAD27_DS1  : 1;            /*!< [24..24] Pad 27 high order drive strength selection. Used in
5198                                                      conjunction with PAD27STRNG field to set the pad drive
5199                                                      strength.                                                                 */
5200             uint32_t            : 3;
5201       __IOM uint32_t PAD27_SR   : 1;            /*!< [28..28] Pad 27 slew rate selection.                                      */
5202             uint32_t            : 3;
5203     } ALTPADCFGG_b;
5204   } ;
5205 
5206   union {
5207     __IOM uint32_t ALTPADCFGH;                  /*!< (@ 0x00000114) This register has additional configuration control
5208                                                                     for pads [31:28]                                           */
5209 
5210     struct {
5211       __IOM uint32_t PAD28_DS1  : 1;            /*!< [0..0] Pad 28 high order drive strength selection. Used in conjunction
5212                                                      with PAD28STRNG field to set the pad drive strength.                      */
5213             uint32_t            : 3;
5214       __IOM uint32_t PAD28_SR   : 1;            /*!< [4..4] Pad 31 slew rate selection.                                        */
5215             uint32_t            : 3;
5216       __IOM uint32_t PAD29_DS1  : 1;            /*!< [8..8] Pad 29 high order drive strength selection. Used in conjunction
5217                                                      with PAD29STRNG field to set the pad drive strength.                      */
5218             uint32_t            : 3;
5219       __IOM uint32_t PAD29_SR   : 1;            /*!< [12..12] Pad 31 slew rate selection.                                      */
5220             uint32_t            : 3;
5221       __IOM uint32_t PAD30_DS1  : 1;            /*!< [16..16] Pad 30 high order drive strength selection. Used in
5222                                                      conjunction with PAD30STRNG field to set the pad drive
5223                                                      strength.                                                                 */
5224             uint32_t            : 3;
5225       __IOM uint32_t PAD30_SR   : 1;            /*!< [20..20] Pad 31 slew rate selection.                                      */
5226             uint32_t            : 3;
5227       __IOM uint32_t PAD31_DS1  : 1;            /*!< [24..24] Pad 31 high order drive strength selection. Used in
5228                                                      conjunction with PAD31STRNG field to set the pad drive
5229                                                      strength.                                                                 */
5230             uint32_t            : 3;
5231       __IOM uint32_t PAD31_SR   : 1;            /*!< [28..28] Pad 31 slew rate selection.                                      */
5232             uint32_t            : 3;
5233     } ALTPADCFGH_b;
5234   } ;
5235 
5236   union {
5237     __IOM uint32_t ALTPADCFGI;                  /*!< (@ 0x00000118) This register has additional configuration control
5238                                                                     for pads [35:32]                                           */
5239 
5240     struct {
5241       __IOM uint32_t PAD32_DS1  : 1;            /*!< [0..0] Pad 32 high order drive strength selection. Used in conjunction
5242                                                      with PAD32STRNG field to set the pad drive strength.                      */
5243             uint32_t            : 3;
5244       __IOM uint32_t PAD32_SR   : 1;            /*!< [4..4] Pad 35 slew rate selection.                                        */
5245             uint32_t            : 3;
5246       __IOM uint32_t PAD33_DS1  : 1;            /*!< [8..8] Pad 33 high order drive strength selection. Used in conjunction
5247                                                      with PAD33STRNG field to set the pad drive strength.                      */
5248             uint32_t            : 3;
5249       __IOM uint32_t PAD33_SR   : 1;            /*!< [12..12] Pad 35 slew rate selection.                                      */
5250             uint32_t            : 3;
5251       __IOM uint32_t PAD34_DS1  : 1;            /*!< [16..16] Pad 34 high order drive strength selection. Used in
5252                                                      conjunction with PAD34STRNG field to set the pad drive
5253                                                      strength.                                                                 */
5254             uint32_t            : 3;
5255       __IOM uint32_t PAD34_SR   : 1;            /*!< [20..20] Pad 35 slew rate selection.                                      */
5256             uint32_t            : 3;
5257       __IOM uint32_t PAD35_DS1  : 1;            /*!< [24..24] Pad 35 high order drive strength selection. Used in
5258                                                      conjunction with PAD35STRNG field to set the pad drive
5259                                                      strength.                                                                 */
5260             uint32_t            : 3;
5261       __IOM uint32_t PAD35_SR   : 1;            /*!< [28..28] Pad 35 slew rate selection.                                      */
5262             uint32_t            : 3;
5263     } ALTPADCFGI_b;
5264   } ;
5265 
5266   union {
5267     __IOM uint32_t ALTPADCFGJ;                  /*!< (@ 0x0000011C) This register has additional configuration control
5268                                                                     for pads [39:36]                                           */
5269 
5270     struct {
5271       __IOM uint32_t PAD36_DS1  : 1;            /*!< [0..0] Pad 36 high order drive strength selection. Used in conjunction
5272                                                      with PAD36STRNG field to set the pad drive strength.                      */
5273             uint32_t            : 3;
5274       __IOM uint32_t PAD36_SR   : 1;            /*!< [4..4] Pad 39 slew rate selection.                                        */
5275             uint32_t            : 3;
5276       __IOM uint32_t PAD37_DS1  : 1;            /*!< [8..8] Pad 37 high order drive strength selection. Used in conjunction
5277                                                      with PAD37STRNG field to set the pad drive strength.                      */
5278             uint32_t            : 3;
5279       __IOM uint32_t PAD37_SR   : 1;            /*!< [12..12] Pad 39 slew rate selection.                                      */
5280             uint32_t            : 3;
5281       __IOM uint32_t PAD38_DS1  : 1;            /*!< [16..16] Pad 38 high order drive strength selection. Used in
5282                                                      conjunction with PAD38STRNG field to set the pad drive
5283                                                      strength.                                                                 */
5284             uint32_t            : 3;
5285       __IOM uint32_t PAD38_SR   : 1;            /*!< [20..20] Pad 39 slew rate selection.                                      */
5286             uint32_t            : 3;
5287       __IOM uint32_t PAD39_DS1  : 1;            /*!< [24..24] Pad 39 high order drive strength selection. Used in
5288                                                      conjunction with PAD39STRNG field to set the pad drive
5289                                                      strength.                                                                 */
5290             uint32_t            : 3;
5291       __IOM uint32_t PAD39_SR   : 1;            /*!< [28..28] Pad 39 slew rate selection.                                      */
5292             uint32_t            : 3;
5293     } ALTPADCFGJ_b;
5294   } ;
5295 
5296   union {
5297     __IOM uint32_t ALTPADCFGK;                  /*!< (@ 0x00000120) This register has additional configuration control
5298                                                                     for pads [43:40]                                           */
5299 
5300     struct {
5301       __IOM uint32_t PAD40_DS1  : 1;            /*!< [0..0] Pad 40 high order drive strength selection. Used in conjunction
5302                                                      with PAD40STRNG field to set the pad drive strength.                      */
5303             uint32_t            : 3;
5304       __IOM uint32_t PAD40_SR   : 1;            /*!< [4..4] Pad 43 slew rate selection.                                        */
5305             uint32_t            : 3;
5306       __IOM uint32_t PAD41_DS1  : 1;            /*!< [8..8] Pad 41 high order drive strength selection. Used in conjunction
5307                                                      with PAD41STRNG field to set the pad drive strength.                      */
5308             uint32_t            : 3;
5309       __IOM uint32_t PAD41_SR   : 1;            /*!< [12..12] Pad 43 slew rate selection.                                      */
5310             uint32_t            : 3;
5311       __IOM uint32_t PAD42_DS1  : 1;            /*!< [16..16] Pad 42 high order drive strength selection. Used in
5312                                                      conjunction with PAD42STRNG field to set the pad drive
5313                                                      strength.                                                                 */
5314             uint32_t            : 3;
5315       __IOM uint32_t PAD42_SR   : 1;            /*!< [20..20] Pad 43 slew rate selection.                                      */
5316             uint32_t            : 3;
5317       __IOM uint32_t PAD43_DS1  : 1;            /*!< [24..24] Pad 43 high order drive strength selection. Used in
5318                                                      conjunction with PAD43STRNG field to set the pad drive
5319                                                      strength.                                                                 */
5320             uint32_t            : 3;
5321       __IOM uint32_t PAD43_SR   : 1;            /*!< [28..28] Pad 43 slew rate selection.                                      */
5322             uint32_t            : 3;
5323     } ALTPADCFGK_b;
5324   } ;
5325 
5326   union {
5327     __IOM uint32_t ALTPADCFGL;                  /*!< (@ 0x00000124) This register has additional configuration control
5328                                                                     for pads [47:44]                                           */
5329 
5330     struct {
5331       __IOM uint32_t PAD44_DS1  : 1;            /*!< [0..0] Pad 44 high order drive strength selection. Used in conjunction
5332                                                      with PAD44STRNG field to set the pad drive strength.                      */
5333             uint32_t            : 3;
5334       __IOM uint32_t PAD44_SR   : 1;            /*!< [4..4] Pad 47 slew rate selection.                                        */
5335             uint32_t            : 3;
5336       __IOM uint32_t PAD45_DS1  : 1;            /*!< [8..8] Pad 45 high order drive strength selection. Used in conjunction
5337                                                      with PAD45STRNG field to set the pad drive strength.                      */
5338             uint32_t            : 3;
5339       __IOM uint32_t PAD45_SR   : 1;            /*!< [12..12] Pad 47 slew rate selection.                                      */
5340             uint32_t            : 3;
5341       __IOM uint32_t PAD46_DS1  : 1;            /*!< [16..16] Pad 46 high order drive strength selection. Used in
5342                                                      conjunction with PAD46STRNG field to set the pad drive
5343                                                      strength.                                                                 */
5344             uint32_t            : 3;
5345       __IOM uint32_t PAD46_SR   : 1;            /*!< [20..20] Pad 47 slew rate selection.                                      */
5346             uint32_t            : 3;
5347       __IOM uint32_t PAD47_DS1  : 1;            /*!< [24..24] Pad 47 high order drive strength selection. Used in
5348                                                      conjunction with PAD47STRNG field to set the pad drive
5349                                                      strength.                                                                 */
5350             uint32_t            : 3;
5351       __IOM uint32_t PAD47_SR   : 1;            /*!< [28..28] Pad 47 slew rate selection.                                      */
5352             uint32_t            : 3;
5353     } ALTPADCFGL_b;
5354   } ;
5355 
5356   union {
5357     __IOM uint32_t ALTPADCFGM;                  /*!< (@ 0x00000128) This register has additional configuration control
5358                                                                     for pads [51:48]                                           */
5359 
5360     struct {
5361       __IOM uint32_t PAD48_DS1  : 1;            /*!< [0..0] Pad 48 high order drive strength selection. Used in conjunction
5362                                                      with PAD48STRNG field to set the pad drive strength.                      */
5363             uint32_t            : 3;
5364       __IOM uint32_t PAD48_SR   : 1;            /*!< [4..4] Pad 51 slew rate selection.                                        */
5365             uint32_t            : 3;
5366       __IOM uint32_t PAD49_DS1  : 1;            /*!< [8..8] Pad 49 high order drive strength selection. Used in conjunction
5367                                                      with PAD49STRNG field to set the pad drive strength.                      */
5368             uint32_t            : 3;
5369       __IOM uint32_t PAD49_SR   : 1;            /*!< [12..12] Pad 51 slew rate selection.                                      */
5370             uint32_t            : 3;
5371       __IOM uint32_t PAD50_DS1  : 1;            /*!< [16..16] Pad 50 high order drive strength selection. Used in
5372                                                      conjunction with PAD50STRNG field to set the pad drive
5373                                                      strength.                                                                 */
5374             uint32_t            : 3;
5375       __IOM uint32_t PAD50_SR   : 1;            /*!< [20..20] Pad 51 slew rate selection.                                      */
5376             uint32_t            : 3;
5377       __IOM uint32_t PAD51_DS1  : 1;            /*!< [24..24] Pad 51 high order drive strength selection. Used in
5378                                                      conjunction with PAD51STRNG field to set the pad drive
5379                                                      strength.                                                                 */
5380             uint32_t            : 3;
5381       __IOM uint32_t PAD51_SR   : 1;            /*!< [28..28] Pad 51 slew rate selection.                                      */
5382             uint32_t            : 3;
5383     } ALTPADCFGM_b;
5384   } ;
5385 
5386   union {
5387     __IOM uint32_t ALTPADCFGN;                  /*!< (@ 0x0000012C) This register has additional configuration control
5388                                                                     for pads [55:52]                                           */
5389 
5390     struct {
5391       __IOM uint32_t PAD52_DS1  : 1;            /*!< [0..0] Pad 52 high order drive strength selection. Used in conjunction
5392                                                      with PAD52STRNG field to set the pad drive strength.                      */
5393             uint32_t            : 3;
5394       __IOM uint32_t PAD52_SR   : 1;            /*!< [4..4] Pad 55 slew rate selection.                                        */
5395             uint32_t            : 3;
5396       __IOM uint32_t PAD53_DS1  : 1;            /*!< [8..8] Pad 53 high order drive strength selection. Used in conjunction
5397                                                      with PAD53STRNG field to set the pad drive strength.                      */
5398             uint32_t            : 3;
5399       __IOM uint32_t PAD53_SR   : 1;            /*!< [12..12] Pad 55 slew rate selection.                                      */
5400             uint32_t            : 3;
5401       __IOM uint32_t PAD54_DS1  : 1;            /*!< [16..16] Pad 54 high order drive strength selection. Used in
5402                                                      conjunction with PAD54STRNG field to set the pad drive
5403                                                      strength.                                                                 */
5404             uint32_t            : 3;
5405       __IOM uint32_t PAD54_SR   : 1;            /*!< [20..20] Pad 55 slew rate selection.                                      */
5406             uint32_t            : 3;
5407       __IOM uint32_t PAD55_DS1  : 1;            /*!< [24..24] Pad 55 high order drive strength selection. Used in
5408                                                      conjunction with PAD55STRNG field to set the pad drive
5409                                                      strength.                                                                 */
5410             uint32_t            : 3;
5411       __IOM uint32_t PAD55_SR   : 1;            /*!< [28..28] Pad 55 slew rate selection.                                      */
5412             uint32_t            : 3;
5413     } ALTPADCFGN_b;
5414   } ;
5415 
5416   union {
5417     __IOM uint32_t ALTPADCFGO;                  /*!< (@ 0x00000130) This register has additional configuration control
5418                                                                     for pads [59:56]                                           */
5419 
5420     struct {
5421       __IOM uint32_t PAD56_DS1  : 1;            /*!< [0..0] Pad 56 high order drive strength selection. Used in conjunction
5422                                                      with PAD56STRNG field to set the pad drive strength.                      */
5423             uint32_t            : 3;
5424       __IOM uint32_t PAD56_SR   : 1;            /*!< [4..4] Pad 59 slew rate selection.                                        */
5425             uint32_t            : 3;
5426       __IOM uint32_t PAD57_DS1  : 1;            /*!< [8..8] Pad 57 high order drive strength selection. Used in conjunction
5427                                                      with PAD57STRNG field to set the pad drive strength.                      */
5428             uint32_t            : 3;
5429       __IOM uint32_t PAD57_SR   : 1;            /*!< [12..12] Pad 59 slew rate selection.                                      */
5430             uint32_t            : 3;
5431       __IOM uint32_t PAD58_DS1  : 1;            /*!< [16..16] Pad 58 high order drive strength selection. Used in
5432                                                      conjunction with PAD58STRNG field to set the pad drive
5433                                                      strength.                                                                 */
5434             uint32_t            : 3;
5435       __IOM uint32_t PAD58_SR   : 1;            /*!< [20..20] Pad 59 slew rate selection.                                      */
5436             uint32_t            : 3;
5437       __IOM uint32_t PAD59_DS1  : 1;            /*!< [24..24] Pad 59 high order drive strength selection. Used in
5438                                                      conjunction with PAD59STRNG field to set the pad drive
5439                                                      strength.                                                                 */
5440             uint32_t            : 3;
5441       __IOM uint32_t PAD59_SR   : 1;            /*!< [28..28] Pad 59 slew rate selection.                                      */
5442             uint32_t            : 3;
5443     } ALTPADCFGO_b;
5444   } ;
5445 
5446   union {
5447     __IOM uint32_t ALTPADCFGP;                  /*!< (@ 0x00000134) This register has additional configuration control
5448                                                                     for pads [63:60]                                           */
5449 
5450     struct {
5451       __IOM uint32_t PAD60_DS1  : 1;            /*!< [0..0] Pad 60 high order drive strength selection. Used in conjunction
5452                                                      with PAD60STRNG field to set the pad drive strength.                      */
5453             uint32_t            : 3;
5454       __IOM uint32_t PAD60_SR   : 1;            /*!< [4..4] Pad 63 slew rate selection.                                        */
5455             uint32_t            : 3;
5456       __IOM uint32_t PAD61_DS1  : 1;            /*!< [8..8] Pad 61 high order drive strength selection. Used in conjunction
5457                                                      with PAD61STRNG field to set the pad drive strength.                      */
5458             uint32_t            : 3;
5459       __IOM uint32_t PAD61_SR   : 1;            /*!< [12..12] Pad 63 slew rate selection.                                      */
5460             uint32_t            : 3;
5461       __IOM uint32_t PAD62_DS1  : 1;            /*!< [16..16] Pad 62 high order drive strength selection. Used in
5462                                                      conjunction with PAD62STRNG field to set the pad drive
5463                                                      strength.                                                                 */
5464             uint32_t            : 3;
5465       __IOM uint32_t PAD62_SR   : 1;            /*!< [20..20] Pad 63 slew rate selection.                                      */
5466             uint32_t            : 3;
5467       __IOM uint32_t PAD63_DS1  : 1;            /*!< [24..24] Pad 63 high order drive strength selection. Used in
5468                                                      conjunction with PAD63STRNG field to set the pad drive
5469                                                      strength.                                                                 */
5470             uint32_t            : 3;
5471       __IOM uint32_t PAD63_SR   : 1;            /*!< [28..28] Pad 63 slew rate selection.                                      */
5472             uint32_t            : 3;
5473     } ALTPADCFGP_b;
5474   } ;
5475 
5476   union {
5477     __IOM uint32_t ALTPADCFGQ;                  /*!< (@ 0x00000138) This register has additional configuration control
5478                                                                     for pads [67:64]                                           */
5479 
5480     struct {
5481       __IOM uint32_t PAD64_DS1  : 1;            /*!< [0..0] Pad 64 high order drive strength selection. Used in conjunction
5482                                                      with PAD64STRNG field to set the pad drive strength.                      */
5483             uint32_t            : 3;
5484       __IOM uint32_t PAD64_SR   : 1;            /*!< [4..4] Pad 67 slew rate selection.                                        */
5485             uint32_t            : 3;
5486       __IOM uint32_t PAD65_DS1  : 1;            /*!< [8..8] Pad 65 high order drive strength selection. Used in conjunction
5487                                                      with PAD65STRNG field to set the pad drive strength.                      */
5488             uint32_t            : 3;
5489       __IOM uint32_t PAD65_SR   : 1;            /*!< [12..12] Pad 67 slew rate selection.                                      */
5490             uint32_t            : 3;
5491       __IOM uint32_t PAD66_DS1  : 1;            /*!< [16..16] Pad 66 high order drive strength selection. Used in
5492                                                      conjunction with PAD66STRNG field to set the pad drive
5493                                                      strength.                                                                 */
5494             uint32_t            : 3;
5495       __IOM uint32_t PAD66_SR   : 1;            /*!< [20..20] Pad 67 slew rate selection.                                      */
5496             uint32_t            : 3;
5497       __IOM uint32_t PAD67_DS1  : 1;            /*!< [24..24] Pad 67 high order drive strength selection. Used in
5498                                                      conjunction with PAD67STRNG field to set the pad drive
5499                                                      strength.                                                                 */
5500             uint32_t            : 3;
5501       __IOM uint32_t PAD67_SR   : 1;            /*!< [28..28] Pad 67 slew rate selection.                                      */
5502             uint32_t            : 3;
5503     } ALTPADCFGQ_b;
5504   } ;
5505 
5506   union {
5507     __IOM uint32_t ALTPADCFGR;                  /*!< (@ 0x0000013C) This register has additional configuration control
5508                                                                     for pads [71:68]                                           */
5509 
5510     struct {
5511       __IOM uint32_t PAD68_DS1  : 1;            /*!< [0..0] Pad 68 high order drive strength selection. Used in conjunction
5512                                                      with PAD68STRNG field to set the pad drive strength.                      */
5513             uint32_t            : 3;
5514       __IOM uint32_t PAD68_SR   : 1;            /*!< [4..4] Pad 71 slew rate selection.                                        */
5515             uint32_t            : 3;
5516       __IOM uint32_t PAD69_DS1  : 1;            /*!< [8..8] Pad 69 high order drive strength selection. Used in conjunction
5517                                                      with PAD69STRNG field to set the pad drive strength.                      */
5518             uint32_t            : 3;
5519       __IOM uint32_t PAD69_SR   : 1;            /*!< [12..12] Pad 71 slew rate selection.                                      */
5520             uint32_t            : 3;
5521       __IOM uint32_t PAD70_DS1  : 1;            /*!< [16..16] Pad 70 high order drive strength selection. Used in
5522                                                      conjunction with PAD70STRNG field to set the pad drive
5523                                                      strength.                                                                 */
5524             uint32_t            : 3;
5525       __IOM uint32_t PAD70_SR   : 1;            /*!< [20..20] Pad 71 slew rate selection.                                      */
5526             uint32_t            : 3;
5527       __IOM uint32_t PAD71_DS1  : 1;            /*!< [24..24] Pad 71 high order drive strength selection. Used in
5528                                                      conjunction with PAD71STRNG field to set the pad drive
5529                                                      strength.                                                                 */
5530             uint32_t            : 3;
5531       __IOM uint32_t PAD71_SR   : 1;            /*!< [28..28] Pad 71 slew rate selection.                                      */
5532             uint32_t            : 3;
5533     } ALTPADCFGR_b;
5534   } ;
5535 
5536   union {
5537     __IOM uint32_t ALTPADCFGS;                  /*!< (@ 0x00000140) This register has additional configuration control
5538                                                                     for pads [73:72]                                           */
5539 
5540     struct {
5541       __IOM uint32_t PAD72_DS1  : 1;            /*!< [0..0] Pad 72 high order drive strength selection. Used in conjunction
5542                                                      with PAD72STRNG field to set the pad drive strength.                      */
5543             uint32_t            : 3;
5544       __IOM uint32_t PAD72_SR   : 1;            /*!< [4..4] Pad 72 slew rate selection.                                        */
5545             uint32_t            : 3;
5546       __IOM uint32_t PAD73_DS1  : 1;            /*!< [8..8] Pad 73 high order drive strength selection. Used in conjunction
5547                                                      with PAD73STRNG field to set the pad drive strength.                      */
5548             uint32_t            : 3;
5549       __IOM uint32_t PAD73_SR   : 1;            /*!< [12..12] Pad 73 slew rate selection.                                      */
5550             uint32_t            : 19;
5551     } ALTPADCFGS_b;
5552   } ;
5553 
5554   union {
5555     __IOM uint32_t SCDET;                       /*!< (@ 0x00000144) SCARD card detect select.                                  */
5556 
5557     struct {
5558       __IOM uint32_t SCDET      : 7;            /*!< [6..0] SCARD card detect pad select.                                      */
5559             uint32_t            : 25;
5560     } SCDET_b;
5561   } ;
5562 
5563   union {
5564     __IOM uint32_t CTENCFG;                     /*!< (@ 0x00000148) Pad enable configuration.                                  */
5565 
5566     struct {
5567       __IOM uint32_t EN0        : 1;            /*!< [0..0] CT0 Enable                                                         */
5568       __IOM uint32_t EN1        : 1;            /*!< [1..1] CT1 Enable                                                         */
5569       __IOM uint32_t EN2        : 1;            /*!< [2..2] CT2 Enable                                                         */
5570       __IOM uint32_t EN3        : 1;            /*!< [3..3] CT3 Enable                                                         */
5571       __IOM uint32_t EN4        : 1;            /*!< [4..4] CT4 Enable                                                         */
5572       __IOM uint32_t EN5        : 1;            /*!< [5..5] CT5 Enable                                                         */
5573       __IOM uint32_t EN6        : 1;            /*!< [6..6] CT6 Enable                                                         */
5574       __IOM uint32_t EN7        : 1;            /*!< [7..7] CT7 Enable                                                         */
5575       __IOM uint32_t EN8        : 1;            /*!< [8..8] CT8 Enable                                                         */
5576       __IOM uint32_t EN9        : 1;            /*!< [9..9] CT9 Enable                                                         */
5577       __IOM uint32_t EN10       : 1;            /*!< [10..10] CT10 Enable                                                      */
5578       __IOM uint32_t EN11       : 1;            /*!< [11..11] CT11 Enable                                                      */
5579       __IOM uint32_t EN12       : 1;            /*!< [12..12] CT12 Enable                                                      */
5580       __IOM uint32_t EN13       : 1;            /*!< [13..13] CT13 Enable                                                      */
5581       __IOM uint32_t EN14       : 1;            /*!< [14..14] CT14 Enable                                                      */
5582       __IOM uint32_t EN15       : 1;            /*!< [15..15] CT15 Enable                                                      */
5583       __IOM uint32_t EN16       : 1;            /*!< [16..16] CT16 Enable                                                      */
5584       __IOM uint32_t EN17       : 1;            /*!< [17..17] CT17 Enable                                                      */
5585       __IOM uint32_t EN18       : 1;            /*!< [18..18] CT18 Enable                                                      */
5586       __IOM uint32_t EN19       : 1;            /*!< [19..19] CT19 Enable                                                      */
5587       __IOM uint32_t EN20       : 1;            /*!< [20..20] CT20 Enable                                                      */
5588       __IOM uint32_t EN21       : 1;            /*!< [21..21] CT21 Enable                                                      */
5589       __IOM uint32_t EN22       : 1;            /*!< [22..22] CT22 Enable                                                      */
5590       __IOM uint32_t EN23       : 1;            /*!< [23..23] CT23 Enable                                                      */
5591       __IOM uint32_t EN24       : 1;            /*!< [24..24] CT24 Enable                                                      */
5592       __IOM uint32_t EN25       : 1;            /*!< [25..25] CT25 Enable                                                      */
5593       __IOM uint32_t EN26       : 1;            /*!< [26..26] CT26 Enable                                                      */
5594       __IOM uint32_t EN27       : 1;            /*!< [27..27] CT27 Enable                                                      */
5595       __IOM uint32_t EN28       : 1;            /*!< [28..28] CT28 Enable                                                      */
5596       __IOM uint32_t EN29       : 1;            /*!< [29..29] CT29 Enable                                                      */
5597       __IOM uint32_t EN30       : 1;            /*!< [30..30] CT30 Enable                                                      */
5598       __IOM uint32_t EN31       : 1;            /*!< [31..31] CT31 Enable                                                      */
5599     } CTENCFG_b;
5600   } ;
5601   __IM  uint32_t  RESERVED1[45];
5602 
5603   union {
5604     __IOM uint32_t INT0EN;                      /*!< (@ 0x00000200) Set bits in this register to allow this module
5605                                                                     to generate the corresponding interrupt.                   */
5606 
5607     struct {
5608       __IOM uint32_t GPIO0      : 1;            /*!< [0..0] GPIO0 interrupt.                                                   */
5609       __IOM uint32_t GPIO1      : 1;            /*!< [1..1] GPIO1 interrupt.                                                   */
5610       __IOM uint32_t GPIO2      : 1;            /*!< [2..2] GPIO2 interrupt.                                                   */
5611       __IOM uint32_t GPIO3      : 1;            /*!< [3..3] GPIO3 interrupt.                                                   */
5612       __IOM uint32_t GPIO4      : 1;            /*!< [4..4] GPIO4 interrupt.                                                   */
5613       __IOM uint32_t GPIO5      : 1;            /*!< [5..5] GPIO5 interrupt.                                                   */
5614       __IOM uint32_t GPIO6      : 1;            /*!< [6..6] GPIO6 interrupt.                                                   */
5615       __IOM uint32_t GPIO7      : 1;            /*!< [7..7] GPIO7 interrupt.                                                   */
5616       __IOM uint32_t GPIO8      : 1;            /*!< [8..8] GPIO8 interrupt.                                                   */
5617       __IOM uint32_t GPIO9      : 1;            /*!< [9..9] GPIO9 interrupt.                                                   */
5618       __IOM uint32_t GPIO10     : 1;            /*!< [10..10] GPIO10 interrupt.                                                */
5619       __IOM uint32_t GPIO11     : 1;            /*!< [11..11] GPIO11 interrupt.                                                */
5620       __IOM uint32_t GPIO12     : 1;            /*!< [12..12] GPIO12 interrupt.                                                */
5621       __IOM uint32_t GPIO13     : 1;            /*!< [13..13] GPIO13 interrupt.                                                */
5622       __IOM uint32_t GPIO14     : 1;            /*!< [14..14] GPIO14 interrupt.                                                */
5623       __IOM uint32_t GPIO15     : 1;            /*!< [15..15] GPIO15 interrupt.                                                */
5624       __IOM uint32_t GPIO16     : 1;            /*!< [16..16] GPIO16 interrupt.                                                */
5625       __IOM uint32_t GPIO17     : 1;            /*!< [17..17] GPIO17 interrupt.                                                */
5626       __IOM uint32_t GPIO18     : 1;            /*!< [18..18] GPIO18interrupt.                                                 */
5627       __IOM uint32_t GPIO19     : 1;            /*!< [19..19] GPIO19 interrupt.                                                */
5628       __IOM uint32_t GPIO20     : 1;            /*!< [20..20] GPIO20 interrupt.                                                */
5629       __IOM uint32_t GPIO21     : 1;            /*!< [21..21] GPIO21 interrupt.                                                */
5630       __IOM uint32_t GPIO22     : 1;            /*!< [22..22] GPIO22 interrupt.                                                */
5631       __IOM uint32_t GPIO23     : 1;            /*!< [23..23] GPIO23 interrupt.                                                */
5632       __IOM uint32_t GPIO24     : 1;            /*!< [24..24] GPIO24 interrupt.                                                */
5633       __IOM uint32_t GPIO25     : 1;            /*!< [25..25] GPIO25 interrupt.                                                */
5634       __IOM uint32_t GPIO26     : 1;            /*!< [26..26] GPIO26 interrupt.                                                */
5635       __IOM uint32_t GPIO27     : 1;            /*!< [27..27] GPIO27 interrupt.                                                */
5636       __IOM uint32_t GPIO28     : 1;            /*!< [28..28] GPIO28 interrupt.                                                */
5637       __IOM uint32_t GPIO29     : 1;            /*!< [29..29] GPIO29 interrupt.                                                */
5638       __IOM uint32_t GPIO30     : 1;            /*!< [30..30] GPIO30 interrupt.                                                */
5639       __IOM uint32_t GPIO31     : 1;            /*!< [31..31] GPIO31 interrupt.                                                */
5640     } INT0EN_b;
5641   } ;
5642 
5643   union {
5644     __IOM uint32_t INT0STAT;                    /*!< (@ 0x00000204) Read bits from this register to discover the
5645                                                                     cause of a recent interrupt.                               */
5646 
5647     struct {
5648       __IOM uint32_t GPIO0      : 1;            /*!< [0..0] GPIO0 interrupt.                                                   */
5649       __IOM uint32_t GPIO1      : 1;            /*!< [1..1] GPIO1 interrupt.                                                   */
5650       __IOM uint32_t GPIO2      : 1;            /*!< [2..2] GPIO2 interrupt.                                                   */
5651       __IOM uint32_t GPIO3      : 1;            /*!< [3..3] GPIO3 interrupt.                                                   */
5652       __IOM uint32_t GPIO4      : 1;            /*!< [4..4] GPIO4 interrupt.                                                   */
5653       __IOM uint32_t GPIO5      : 1;            /*!< [5..5] GPIO5 interrupt.                                                   */
5654       __IOM uint32_t GPIO6      : 1;            /*!< [6..6] GPIO6 interrupt.                                                   */
5655       __IOM uint32_t GPIO7      : 1;            /*!< [7..7] GPIO7 interrupt.                                                   */
5656       __IOM uint32_t GPIO8      : 1;            /*!< [8..8] GPIO8 interrupt.                                                   */
5657       __IOM uint32_t GPIO9      : 1;            /*!< [9..9] GPIO9 interrupt.                                                   */
5658       __IOM uint32_t GPIO10     : 1;            /*!< [10..10] GPIO10 interrupt.                                                */
5659       __IOM uint32_t GPIO11     : 1;            /*!< [11..11] GPIO11 interrupt.                                                */
5660       __IOM uint32_t GPIO12     : 1;            /*!< [12..12] GPIO12 interrupt.                                                */
5661       __IOM uint32_t GPIO13     : 1;            /*!< [13..13] GPIO13 interrupt.                                                */
5662       __IOM uint32_t GPIO14     : 1;            /*!< [14..14] GPIO14 interrupt.                                                */
5663       __IOM uint32_t GPIO15     : 1;            /*!< [15..15] GPIO15 interrupt.                                                */
5664       __IOM uint32_t GPIO16     : 1;            /*!< [16..16] GPIO16 interrupt.                                                */
5665       __IOM uint32_t GPIO17     : 1;            /*!< [17..17] GPIO17 interrupt.                                                */
5666       __IOM uint32_t GPIO18     : 1;            /*!< [18..18] GPIO18interrupt.                                                 */
5667       __IOM uint32_t GPIO19     : 1;            /*!< [19..19] GPIO19 interrupt.                                                */
5668       __IOM uint32_t GPIO20     : 1;            /*!< [20..20] GPIO20 interrupt.                                                */
5669       __IOM uint32_t GPIO21     : 1;            /*!< [21..21] GPIO21 interrupt.                                                */
5670       __IOM uint32_t GPIO22     : 1;            /*!< [22..22] GPIO22 interrupt.                                                */
5671       __IOM uint32_t GPIO23     : 1;            /*!< [23..23] GPIO23 interrupt.                                                */
5672       __IOM uint32_t GPIO24     : 1;            /*!< [24..24] GPIO24 interrupt.                                                */
5673       __IOM uint32_t GPIO25     : 1;            /*!< [25..25] GPIO25 interrupt.                                                */
5674       __IOM uint32_t GPIO26     : 1;            /*!< [26..26] GPIO26 interrupt.                                                */
5675       __IOM uint32_t GPIO27     : 1;            /*!< [27..27] GPIO27 interrupt.                                                */
5676       __IOM uint32_t GPIO28     : 1;            /*!< [28..28] GPIO28 interrupt.                                                */
5677       __IOM uint32_t GPIO29     : 1;            /*!< [29..29] GPIO29 interrupt.                                                */
5678       __IOM uint32_t GPIO30     : 1;            /*!< [30..30] GPIO30 interrupt.                                                */
5679       __IOM uint32_t GPIO31     : 1;            /*!< [31..31] GPIO31 interrupt.                                                */
5680     } INT0STAT_b;
5681   } ;
5682 
5683   union {
5684     __IOM uint32_t INT0CLR;                     /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
5685                                                                     the interrupt status associated with that
5686                                                                     bit.                                                       */
5687 
5688     struct {
5689       __IOM uint32_t GPIO0      : 1;            /*!< [0..0] GPIO0 interrupt.                                                   */
5690       __IOM uint32_t GPIO1      : 1;            /*!< [1..1] GPIO1 interrupt.                                                   */
5691       __IOM uint32_t GPIO2      : 1;            /*!< [2..2] GPIO2 interrupt.                                                   */
5692       __IOM uint32_t GPIO3      : 1;            /*!< [3..3] GPIO3 interrupt.                                                   */
5693       __IOM uint32_t GPIO4      : 1;            /*!< [4..4] GPIO4 interrupt.                                                   */
5694       __IOM uint32_t GPIO5      : 1;            /*!< [5..5] GPIO5 interrupt.                                                   */
5695       __IOM uint32_t GPIO6      : 1;            /*!< [6..6] GPIO6 interrupt.                                                   */
5696       __IOM uint32_t GPIO7      : 1;            /*!< [7..7] GPIO7 interrupt.                                                   */
5697       __IOM uint32_t GPIO8      : 1;            /*!< [8..8] GPIO8 interrupt.                                                   */
5698       __IOM uint32_t GPIO9      : 1;            /*!< [9..9] GPIO9 interrupt.                                                   */
5699       __IOM uint32_t GPIO10     : 1;            /*!< [10..10] GPIO10 interrupt.                                                */
5700       __IOM uint32_t GPIO11     : 1;            /*!< [11..11] GPIO11 interrupt.                                                */
5701       __IOM uint32_t GPIO12     : 1;            /*!< [12..12] GPIO12 interrupt.                                                */
5702       __IOM uint32_t GPIO13     : 1;            /*!< [13..13] GPIO13 interrupt.                                                */
5703       __IOM uint32_t GPIO14     : 1;            /*!< [14..14] GPIO14 interrupt.                                                */
5704       __IOM uint32_t GPIO15     : 1;            /*!< [15..15] GPIO15 interrupt.                                                */
5705       __IOM uint32_t GPIO16     : 1;            /*!< [16..16] GPIO16 interrupt.                                                */
5706       __IOM uint32_t GPIO17     : 1;            /*!< [17..17] GPIO17 interrupt.                                                */
5707       __IOM uint32_t GPIO18     : 1;            /*!< [18..18] GPIO18interrupt.                                                 */
5708       __IOM uint32_t GPIO19     : 1;            /*!< [19..19] GPIO19 interrupt.                                                */
5709       __IOM uint32_t GPIO20     : 1;            /*!< [20..20] GPIO20 interrupt.                                                */
5710       __IOM uint32_t GPIO21     : 1;            /*!< [21..21] GPIO21 interrupt.                                                */
5711       __IOM uint32_t GPIO22     : 1;            /*!< [22..22] GPIO22 interrupt.                                                */
5712       __IOM uint32_t GPIO23     : 1;            /*!< [23..23] GPIO23 interrupt.                                                */
5713       __IOM uint32_t GPIO24     : 1;            /*!< [24..24] GPIO24 interrupt.                                                */
5714       __IOM uint32_t GPIO25     : 1;            /*!< [25..25] GPIO25 interrupt.                                                */
5715       __IOM uint32_t GPIO26     : 1;            /*!< [26..26] GPIO26 interrupt.                                                */
5716       __IOM uint32_t GPIO27     : 1;            /*!< [27..27] GPIO27 interrupt.                                                */
5717       __IOM uint32_t GPIO28     : 1;            /*!< [28..28] GPIO28 interrupt.                                                */
5718       __IOM uint32_t GPIO29     : 1;            /*!< [29..29] GPIO29 interrupt.                                                */
5719       __IOM uint32_t GPIO30     : 1;            /*!< [30..30] GPIO30 interrupt.                                                */
5720       __IOM uint32_t GPIO31     : 1;            /*!< [31..31] GPIO31 interrupt.                                                */
5721     } INT0CLR_b;
5722   } ;
5723 
5724   union {
5725     __IOM uint32_t INT0SET;                     /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
5726                                                                     generate an interrupt from this module.
5727                                                                     (Generally used for testing purposes).                     */
5728 
5729     struct {
5730       __IOM uint32_t GPIO0      : 1;            /*!< [0..0] GPIO0 interrupt.                                                   */
5731       __IOM uint32_t GPIO1      : 1;            /*!< [1..1] GPIO1 interrupt.                                                   */
5732       __IOM uint32_t GPIO2      : 1;            /*!< [2..2] GPIO2 interrupt.                                                   */
5733       __IOM uint32_t GPIO3      : 1;            /*!< [3..3] GPIO3 interrupt.                                                   */
5734       __IOM uint32_t GPIO4      : 1;            /*!< [4..4] GPIO4 interrupt.                                                   */
5735       __IOM uint32_t GPIO5      : 1;            /*!< [5..5] GPIO5 interrupt.                                                   */
5736       __IOM uint32_t GPIO6      : 1;            /*!< [6..6] GPIO6 interrupt.                                                   */
5737       __IOM uint32_t GPIO7      : 1;            /*!< [7..7] GPIO7 interrupt.                                                   */
5738       __IOM uint32_t GPIO8      : 1;            /*!< [8..8] GPIO8 interrupt.                                                   */
5739       __IOM uint32_t GPIO9      : 1;            /*!< [9..9] GPIO9 interrupt.                                                   */
5740       __IOM uint32_t GPIO10     : 1;            /*!< [10..10] GPIO10 interrupt.                                                */
5741       __IOM uint32_t GPIO11     : 1;            /*!< [11..11] GPIO11 interrupt.                                                */
5742       __IOM uint32_t GPIO12     : 1;            /*!< [12..12] GPIO12 interrupt.                                                */
5743       __IOM uint32_t GPIO13     : 1;            /*!< [13..13] GPIO13 interrupt.                                                */
5744       __IOM uint32_t GPIO14     : 1;            /*!< [14..14] GPIO14 interrupt.                                                */
5745       __IOM uint32_t GPIO15     : 1;            /*!< [15..15] GPIO15 interrupt.                                                */
5746       __IOM uint32_t GPIO16     : 1;            /*!< [16..16] GPIO16 interrupt.                                                */
5747       __IOM uint32_t GPIO17     : 1;            /*!< [17..17] GPIO17 interrupt.                                                */
5748       __IOM uint32_t GPIO18     : 1;            /*!< [18..18] GPIO18interrupt.                                                 */
5749       __IOM uint32_t GPIO19     : 1;            /*!< [19..19] GPIO19 interrupt.                                                */
5750       __IOM uint32_t GPIO20     : 1;            /*!< [20..20] GPIO20 interrupt.                                                */
5751       __IOM uint32_t GPIO21     : 1;            /*!< [21..21] GPIO21 interrupt.                                                */
5752       __IOM uint32_t GPIO22     : 1;            /*!< [22..22] GPIO22 interrupt.                                                */
5753       __IOM uint32_t GPIO23     : 1;            /*!< [23..23] GPIO23 interrupt.                                                */
5754       __IOM uint32_t GPIO24     : 1;            /*!< [24..24] GPIO24 interrupt.                                                */
5755       __IOM uint32_t GPIO25     : 1;            /*!< [25..25] GPIO25 interrupt.                                                */
5756       __IOM uint32_t GPIO26     : 1;            /*!< [26..26] GPIO26 interrupt.                                                */
5757       __IOM uint32_t GPIO27     : 1;            /*!< [27..27] GPIO27 interrupt.                                                */
5758       __IOM uint32_t GPIO28     : 1;            /*!< [28..28] GPIO28 interrupt.                                                */
5759       __IOM uint32_t GPIO29     : 1;            /*!< [29..29] GPIO29 interrupt.                                                */
5760       __IOM uint32_t GPIO30     : 1;            /*!< [30..30] GPIO30 interrupt.                                                */
5761       __IOM uint32_t GPIO31     : 1;            /*!< [31..31] GPIO31 interrupt.                                                */
5762     } INT0SET_b;
5763   } ;
5764   __IM  uint32_t  RESERVED2[4];
5765 
5766   union {
5767     __IOM uint32_t INT1EN;                      /*!< (@ 0x00000220) Set bits in this register to allow this module
5768                                                                     to generate the corresponding interrupt.                   */
5769 
5770     struct {
5771       __IOM uint32_t GPIO32     : 1;            /*!< [0..0] GPIO32 interrupt.                                                  */
5772       __IOM uint32_t GPIO33     : 1;            /*!< [1..1] GPIO33 interrupt.                                                  */
5773       __IOM uint32_t GPIO34     : 1;            /*!< [2..2] GPIO34 interrupt.                                                  */
5774       __IOM uint32_t GPIO35     : 1;            /*!< [3..3] GPIO35 interrupt.                                                  */
5775       __IOM uint32_t GPIO36     : 1;            /*!< [4..4] GPIO36 interrupt.                                                  */
5776       __IOM uint32_t GPIO37     : 1;            /*!< [5..5] GPIO37 interrupt.                                                  */
5777       __IOM uint32_t GPIO38     : 1;            /*!< [6..6] GPIO38 interrupt.                                                  */
5778       __IOM uint32_t GPIO39     : 1;            /*!< [7..7] GPIO39 interrupt.                                                  */
5779       __IOM uint32_t GPIO40     : 1;            /*!< [8..8] GPIO40 interrupt.                                                  */
5780       __IOM uint32_t GPIO41     : 1;            /*!< [9..9] GPIO41 interrupt.                                                  */
5781       __IOM uint32_t GPIO42     : 1;            /*!< [10..10] GPIO42 interrupt.                                                */
5782       __IOM uint32_t GPIO43     : 1;            /*!< [11..11] GPIO43 interrupt.                                                */
5783       __IOM uint32_t GPIO44     : 1;            /*!< [12..12] GPIO44 interrupt.                                                */
5784       __IOM uint32_t GPIO45     : 1;            /*!< [13..13] GPIO45 interrupt.                                                */
5785       __IOM uint32_t GPIO46     : 1;            /*!< [14..14] GPIO46 interrupt.                                                */
5786       __IOM uint32_t GPIO47     : 1;            /*!< [15..15] GPIO47 interrupt.                                                */
5787       __IOM uint32_t GPIO48     : 1;            /*!< [16..16] GPIO48 interrupt.                                                */
5788       __IOM uint32_t GPIO49     : 1;            /*!< [17..17] GPIO49 interrupt.                                                */
5789       __IOM uint32_t GPIO50     : 1;            /*!< [18..18] GPIO50 interrupt.                                                */
5790       __IOM uint32_t GPIO51     : 1;            /*!< [19..19] GPIO51 interrupt.                                                */
5791       __IOM uint32_t GPIO52     : 1;            /*!< [20..20] GPIO52 interrupt.                                                */
5792       __IOM uint32_t GPIO53     : 1;            /*!< [21..21] GPIO53 interrupt.                                                */
5793       __IOM uint32_t GPIO54     : 1;            /*!< [22..22] GPIO54 interrupt.                                                */
5794       __IOM uint32_t GPIO55     : 1;            /*!< [23..23] GPIO55 interrupt.                                                */
5795       __IOM uint32_t GPIO56     : 1;            /*!< [24..24] GPIO56 interrupt.                                                */
5796       __IOM uint32_t GPIO57     : 1;            /*!< [25..25] GPIO57 interrupt.                                                */
5797       __IOM uint32_t GPIO58     : 1;            /*!< [26..26] GPIO58 interrupt.                                                */
5798       __IOM uint32_t GPIO59     : 1;            /*!< [27..27] GPIO59 interrupt.                                                */
5799       __IOM uint32_t GPIO60     : 1;            /*!< [28..28] GPIO60 interrupt.                                                */
5800       __IOM uint32_t GPIO61     : 1;            /*!< [29..29] GPIO61 interrupt.                                                */
5801       __IOM uint32_t GPIO62     : 1;            /*!< [30..30] GPIO62 interrupt.                                                */
5802       __IOM uint32_t GPIO63     : 1;            /*!< [31..31] GPIO63 interrupt.                                                */
5803     } INT1EN_b;
5804   } ;
5805 
5806   union {
5807     __IOM uint32_t INT1STAT;                    /*!< (@ 0x00000224) Read bits from this register to discover the
5808                                                                     cause of a recent interrupt.                               */
5809 
5810     struct {
5811       __IOM uint32_t GPIO32     : 1;            /*!< [0..0] GPIO32 interrupt.                                                  */
5812       __IOM uint32_t GPIO33     : 1;            /*!< [1..1] GPIO33 interrupt.                                                  */
5813       __IOM uint32_t GPIO34     : 1;            /*!< [2..2] GPIO34 interrupt.                                                  */
5814       __IOM uint32_t GPIO35     : 1;            /*!< [3..3] GPIO35 interrupt.                                                  */
5815       __IOM uint32_t GPIO36     : 1;            /*!< [4..4] GPIO36 interrupt.                                                  */
5816       __IOM uint32_t GPIO37     : 1;            /*!< [5..5] GPIO37 interrupt.                                                  */
5817       __IOM uint32_t GPIO38     : 1;            /*!< [6..6] GPIO38 interrupt.                                                  */
5818       __IOM uint32_t GPIO39     : 1;            /*!< [7..7] GPIO39 interrupt.                                                  */
5819       __IOM uint32_t GPIO40     : 1;            /*!< [8..8] GPIO40 interrupt.                                                  */
5820       __IOM uint32_t GPIO41     : 1;            /*!< [9..9] GPIO41 interrupt.                                                  */
5821       __IOM uint32_t GPIO42     : 1;            /*!< [10..10] GPIO42 interrupt.                                                */
5822       __IOM uint32_t GPIO43     : 1;            /*!< [11..11] GPIO43 interrupt.                                                */
5823       __IOM uint32_t GPIO44     : 1;            /*!< [12..12] GPIO44 interrupt.                                                */
5824       __IOM uint32_t GPIO45     : 1;            /*!< [13..13] GPIO45 interrupt.                                                */
5825       __IOM uint32_t GPIO46     : 1;            /*!< [14..14] GPIO46 interrupt.                                                */
5826       __IOM uint32_t GPIO47     : 1;            /*!< [15..15] GPIO47 interrupt.                                                */
5827       __IOM uint32_t GPIO48     : 1;            /*!< [16..16] GPIO48 interrupt.                                                */
5828       __IOM uint32_t GPIO49     : 1;            /*!< [17..17] GPIO49 interrupt.                                                */
5829       __IOM uint32_t GPIO50     : 1;            /*!< [18..18] GPIO50 interrupt.                                                */
5830       __IOM uint32_t GPIO51     : 1;            /*!< [19..19] GPIO51 interrupt.                                                */
5831       __IOM uint32_t GPIO52     : 1;            /*!< [20..20] GPIO52 interrupt.                                                */
5832       __IOM uint32_t GPIO53     : 1;            /*!< [21..21] GPIO53 interrupt.                                                */
5833       __IOM uint32_t GPIO54     : 1;            /*!< [22..22] GPIO54 interrupt.                                                */
5834       __IOM uint32_t GPIO55     : 1;            /*!< [23..23] GPIO55 interrupt.                                                */
5835       __IOM uint32_t GPIO56     : 1;            /*!< [24..24] GPIO56 interrupt.                                                */
5836       __IOM uint32_t GPIO57     : 1;            /*!< [25..25] GPIO57 interrupt.                                                */
5837       __IOM uint32_t GPIO58     : 1;            /*!< [26..26] GPIO58 interrupt.                                                */
5838       __IOM uint32_t GPIO59     : 1;            /*!< [27..27] GPIO59 interrupt.                                                */
5839       __IOM uint32_t GPIO60     : 1;            /*!< [28..28] GPIO60 interrupt.                                                */
5840       __IOM uint32_t GPIO61     : 1;            /*!< [29..29] GPIO61 interrupt.                                                */
5841       __IOM uint32_t GPIO62     : 1;            /*!< [30..30] GPIO62 interrupt.                                                */
5842       __IOM uint32_t GPIO63     : 1;            /*!< [31..31] GPIO63 interrupt.                                                */
5843     } INT1STAT_b;
5844   } ;
5845 
5846   union {
5847     __IOM uint32_t INT1CLR;                     /*!< (@ 0x00000228) Write a 1 to a bit in this register to clear
5848                                                                     the interrupt status associated with that
5849                                                                     bit.                                                       */
5850 
5851     struct {
5852       __IOM uint32_t GPIO32     : 1;            /*!< [0..0] GPIO32 interrupt.                                                  */
5853       __IOM uint32_t GPIO33     : 1;            /*!< [1..1] GPIO33 interrupt.                                                  */
5854       __IOM uint32_t GPIO34     : 1;            /*!< [2..2] GPIO34 interrupt.                                                  */
5855       __IOM uint32_t GPIO35     : 1;            /*!< [3..3] GPIO35 interrupt.                                                  */
5856       __IOM uint32_t GPIO36     : 1;            /*!< [4..4] GPIO36 interrupt.                                                  */
5857       __IOM uint32_t GPIO37     : 1;            /*!< [5..5] GPIO37 interrupt.                                                  */
5858       __IOM uint32_t GPIO38     : 1;            /*!< [6..6] GPIO38 interrupt.                                                  */
5859       __IOM uint32_t GPIO39     : 1;            /*!< [7..7] GPIO39 interrupt.                                                  */
5860       __IOM uint32_t GPIO40     : 1;            /*!< [8..8] GPIO40 interrupt.                                                  */
5861       __IOM uint32_t GPIO41     : 1;            /*!< [9..9] GPIO41 interrupt.                                                  */
5862       __IOM uint32_t GPIO42     : 1;            /*!< [10..10] GPIO42 interrupt.                                                */
5863       __IOM uint32_t GPIO43     : 1;            /*!< [11..11] GPIO43 interrupt.                                                */
5864       __IOM uint32_t GPIO44     : 1;            /*!< [12..12] GPIO44 interrupt.                                                */
5865       __IOM uint32_t GPIO45     : 1;            /*!< [13..13] GPIO45 interrupt.                                                */
5866       __IOM uint32_t GPIO46     : 1;            /*!< [14..14] GPIO46 interrupt.                                                */
5867       __IOM uint32_t GPIO47     : 1;            /*!< [15..15] GPIO47 interrupt.                                                */
5868       __IOM uint32_t GPIO48     : 1;            /*!< [16..16] GPIO48 interrupt.                                                */
5869       __IOM uint32_t GPIO49     : 1;            /*!< [17..17] GPIO49 interrupt.                                                */
5870       __IOM uint32_t GPIO50     : 1;            /*!< [18..18] GPIO50 interrupt.                                                */
5871       __IOM uint32_t GPIO51     : 1;            /*!< [19..19] GPIO51 interrupt.                                                */
5872       __IOM uint32_t GPIO52     : 1;            /*!< [20..20] GPIO52 interrupt.                                                */
5873       __IOM uint32_t GPIO53     : 1;            /*!< [21..21] GPIO53 interrupt.                                                */
5874       __IOM uint32_t GPIO54     : 1;            /*!< [22..22] GPIO54 interrupt.                                                */
5875       __IOM uint32_t GPIO55     : 1;            /*!< [23..23] GPIO55 interrupt.                                                */
5876       __IOM uint32_t GPIO56     : 1;            /*!< [24..24] GPIO56 interrupt.                                                */
5877       __IOM uint32_t GPIO57     : 1;            /*!< [25..25] GPIO57 interrupt.                                                */
5878       __IOM uint32_t GPIO58     : 1;            /*!< [26..26] GPIO58 interrupt.                                                */
5879       __IOM uint32_t GPIO59     : 1;            /*!< [27..27] GPIO59 interrupt.                                                */
5880       __IOM uint32_t GPIO60     : 1;            /*!< [28..28] GPIO60 interrupt.                                                */
5881       __IOM uint32_t GPIO61     : 1;            /*!< [29..29] GPIO61 interrupt.                                                */
5882       __IOM uint32_t GPIO62     : 1;            /*!< [30..30] GPIO62 interrupt.                                                */
5883       __IOM uint32_t GPIO63     : 1;            /*!< [31..31] GPIO63 interrupt.                                                */
5884     } INT1CLR_b;
5885   } ;
5886 
5887   union {
5888     __IOM uint32_t INT1SET;                     /*!< (@ 0x0000022C) Write a 1 to a bit in this register to instantly
5889                                                                     generate an interrupt from this module.
5890                                                                     (Generally used for testing purposes).                     */
5891 
5892     struct {
5893       __IOM uint32_t GPIO32     : 1;            /*!< [0..0] GPIO32 interrupt.                                                  */
5894       __IOM uint32_t GPIO33     : 1;            /*!< [1..1] GPIO33 interrupt.                                                  */
5895       __IOM uint32_t GPIO34     : 1;            /*!< [2..2] GPIO34 interrupt.                                                  */
5896       __IOM uint32_t GPIO35     : 1;            /*!< [3..3] GPIO35 interrupt.                                                  */
5897       __IOM uint32_t GPIO36     : 1;            /*!< [4..4] GPIO36 interrupt.                                                  */
5898       __IOM uint32_t GPIO37     : 1;            /*!< [5..5] GPIO37 interrupt.                                                  */
5899       __IOM uint32_t GPIO38     : 1;            /*!< [6..6] GPIO38 interrupt.                                                  */
5900       __IOM uint32_t GPIO39     : 1;            /*!< [7..7] GPIO39 interrupt.                                                  */
5901       __IOM uint32_t GPIO40     : 1;            /*!< [8..8] GPIO40 interrupt.                                                  */
5902       __IOM uint32_t GPIO41     : 1;            /*!< [9..9] GPIO41 interrupt.                                                  */
5903       __IOM uint32_t GPIO42     : 1;            /*!< [10..10] GPIO42 interrupt.                                                */
5904       __IOM uint32_t GPIO43     : 1;            /*!< [11..11] GPIO43 interrupt.                                                */
5905       __IOM uint32_t GPIO44     : 1;            /*!< [12..12] GPIO44 interrupt.                                                */
5906       __IOM uint32_t GPIO45     : 1;            /*!< [13..13] GPIO45 interrupt.                                                */
5907       __IOM uint32_t GPIO46     : 1;            /*!< [14..14] GPIO46 interrupt.                                                */
5908       __IOM uint32_t GPIO47     : 1;            /*!< [15..15] GPIO47 interrupt.                                                */
5909       __IOM uint32_t GPIO48     : 1;            /*!< [16..16] GPIO48 interrupt.                                                */
5910       __IOM uint32_t GPIO49     : 1;            /*!< [17..17] GPIO49 interrupt.                                                */
5911       __IOM uint32_t GPIO50     : 1;            /*!< [18..18] GPIO50 interrupt.                                                */
5912       __IOM uint32_t GPIO51     : 1;            /*!< [19..19] GPIO51 interrupt.                                                */
5913       __IOM uint32_t GPIO52     : 1;            /*!< [20..20] GPIO52 interrupt.                                                */
5914       __IOM uint32_t GPIO53     : 1;            /*!< [21..21] GPIO53 interrupt.                                                */
5915       __IOM uint32_t GPIO54     : 1;            /*!< [22..22] GPIO54 interrupt.                                                */
5916       __IOM uint32_t GPIO55     : 1;            /*!< [23..23] GPIO55 interrupt.                                                */
5917       __IOM uint32_t GPIO56     : 1;            /*!< [24..24] GPIO56 interrupt.                                                */
5918       __IOM uint32_t GPIO57     : 1;            /*!< [25..25] GPIO57 interrupt.                                                */
5919       __IOM uint32_t GPIO58     : 1;            /*!< [26..26] GPIO58 interrupt.                                                */
5920       __IOM uint32_t GPIO59     : 1;            /*!< [27..27] GPIO59 interrupt.                                                */
5921       __IOM uint32_t GPIO60     : 1;            /*!< [28..28] GPIO60 interrupt.                                                */
5922       __IOM uint32_t GPIO61     : 1;            /*!< [29..29] GPIO61 interrupt.                                                */
5923       __IOM uint32_t GPIO62     : 1;            /*!< [30..30] GPIO62 interrupt.                                                */
5924       __IOM uint32_t GPIO63     : 1;            /*!< [31..31] GPIO63 interrupt.                                                */
5925     } INT1SET_b;
5926   } ;
5927   __IM  uint32_t  RESERVED3[4];
5928 
5929   union {
5930     __IOM uint32_t INT2EN;                      /*!< (@ 0x00000240) Set bits in this register to allow this module
5931                                                                     to generate the corresponding interrupt.                   */
5932 
5933     struct {
5934       __IOM uint32_t GPIO64     : 1;            /*!< [0..0] GPIO64 interrupt.                                                  */
5935       __IOM uint32_t GPIO65     : 1;            /*!< [1..1] GPIO65 interrupt.                                                  */
5936       __IOM uint32_t GPIO66     : 1;            /*!< [2..2] GPIO66 interrupt.                                                  */
5937       __IOM uint32_t GPIO67     : 1;            /*!< [3..3] GPIO67 interrupt.                                                  */
5938       __IOM uint32_t GPIO68     : 1;            /*!< [4..4] GPIO68 interrupt.                                                  */
5939       __IOM uint32_t GPIO69     : 1;            /*!< [5..5] GPIO69 interrupt.                                                  */
5940       __IOM uint32_t GPIO70     : 1;            /*!< [6..6] GPIO70 interrupt.                                                  */
5941       __IOM uint32_t GPIO71     : 1;            /*!< [7..7] GPIO71 interrupt.                                                  */
5942       __IOM uint32_t GPIO72     : 1;            /*!< [8..8] GPIO72 interrupt.                                                  */
5943       __IOM uint32_t GPIO73     : 1;            /*!< [9..9] GPIO73 interrupt.                                                  */
5944             uint32_t            : 22;
5945     } INT2EN_b;
5946   } ;
5947 
5948   union {
5949     __IOM uint32_t INT2STAT;                    /*!< (@ 0x00000244) Read bits from this register to discover the
5950                                                                     cause of a recent interrupt.                               */
5951 
5952     struct {
5953       __IOM uint32_t GPIO64     : 1;            /*!< [0..0] GPIO64 interrupt.                                                  */
5954       __IOM uint32_t GPIO65     : 1;            /*!< [1..1] GPIO65 interrupt.                                                  */
5955       __IOM uint32_t GPIO66     : 1;            /*!< [2..2] GPIO66 interrupt.                                                  */
5956       __IOM uint32_t GPIO67     : 1;            /*!< [3..3] GPIO67 interrupt.                                                  */
5957       __IOM uint32_t GPIO68     : 1;            /*!< [4..4] GPIO68 interrupt.                                                  */
5958       __IOM uint32_t GPIO69     : 1;            /*!< [5..5] GPIO69 interrupt.                                                  */
5959       __IOM uint32_t GPIO70     : 1;            /*!< [6..6] GPIO70 interrupt.                                                  */
5960       __IOM uint32_t GPIO71     : 1;            /*!< [7..7] GPIO71 interrupt.                                                  */
5961       __IOM uint32_t GPIO72     : 1;            /*!< [8..8] GPIO72 interrupt.                                                  */
5962       __IOM uint32_t GPIO73     : 1;            /*!< [9..9] GPIO73 interrupt.                                                  */
5963             uint32_t            : 22;
5964     } INT2STAT_b;
5965   } ;
5966 
5967   union {
5968     __IOM uint32_t INT2CLR;                     /*!< (@ 0x00000248) Write a 1 to a bit in this register to clear
5969                                                                     the interrupt status associated with that
5970                                                                     bit.                                                       */
5971 
5972     struct {
5973       __IOM uint32_t GPIO64     : 1;            /*!< [0..0] GPIO64 interrupt.                                                  */
5974       __IOM uint32_t GPIO65     : 1;            /*!< [1..1] GPIO65 interrupt.                                                  */
5975       __IOM uint32_t GPIO66     : 1;            /*!< [2..2] GPIO66 interrupt.                                                  */
5976       __IOM uint32_t GPIO67     : 1;            /*!< [3..3] GPIO67 interrupt.                                                  */
5977       __IOM uint32_t GPIO68     : 1;            /*!< [4..4] GPIO68 interrupt.                                                  */
5978       __IOM uint32_t GPIO69     : 1;            /*!< [5..5] GPIO69 interrupt.                                                  */
5979       __IOM uint32_t GPIO70     : 1;            /*!< [6..6] GPIO70 interrupt.                                                  */
5980       __IOM uint32_t GPIO71     : 1;            /*!< [7..7] GPIO71 interrupt.                                                  */
5981       __IOM uint32_t GPIO72     : 1;            /*!< [8..8] GPIO72 interrupt.                                                  */
5982       __IOM uint32_t GPIO73     : 1;            /*!< [9..9] GPIO73 interrupt.                                                  */
5983             uint32_t            : 22;
5984     } INT2CLR_b;
5985   } ;
5986 
5987   union {
5988     __IOM uint32_t INT2SET;                     /*!< (@ 0x0000024C) Write a 1 to a bit in this register to instantly
5989                                                                     generate an interrupt from this module.
5990                                                                     (Generally used for testing purposes).                     */
5991 
5992     struct {
5993       __IOM uint32_t GPIO64     : 1;            /*!< [0..0] GPIO64 interrupt.                                                  */
5994       __IOM uint32_t GPIO65     : 1;            /*!< [1..1] GPIO65 interrupt.                                                  */
5995       __IOM uint32_t GPIO66     : 1;            /*!< [2..2] GPIO66 interrupt.                                                  */
5996       __IOM uint32_t GPIO67     : 1;            /*!< [3..3] GPIO67 interrupt.                                                  */
5997       __IOM uint32_t GPIO68     : 1;            /*!< [4..4] GPIO68 interrupt.                                                  */
5998       __IOM uint32_t GPIO69     : 1;            /*!< [5..5] GPIO69 interrupt.                                                  */
5999       __IOM uint32_t GPIO70     : 1;            /*!< [6..6] GPIO70 interrupt.                                                  */
6000       __IOM uint32_t GPIO71     : 1;            /*!< [7..7] GPIO71 interrupt.                                                  */
6001       __IOM uint32_t GPIO72     : 1;            /*!< [8..8] GPIO72 interrupt.                                                  */
6002       __IOM uint32_t GPIO73     : 1;            /*!< [9..9] GPIO73 interrupt.                                                  */
6003             uint32_t            : 22;
6004     } INT2SET_b;
6005   } ;
6006 
6007   union {
6008     __IOM uint32_t DBGCTRL;                     /*!< (@ 0x00000250) Debug control for test purposes only                       */
6009 
6010     struct {
6011       __IOM uint32_t GCLK0      : 1;            /*!< [0..0] Gate IOM0 CLK in SPI mode, allowing external input clock           */
6012       __IOM uint32_t GCLK1      : 1;            /*!< [1..1] Gate IOM1 CLK in SPI mode, allowing external input clock           */
6013       __IOM uint32_t GCLK2      : 1;            /*!< [2..2] Gate IOM2 CLK in SPI mode, allowing external input clock           */
6014       __IOM uint32_t GCLK3      : 1;            /*!< [3..3] Gate IOM3 CLK in SPI mode, allowing external input clock           */
6015       __IOM uint32_t GCLK4      : 1;            /*!< [4..4] Gate IOM4 CLK in SPI mode, allowing external input clock           */
6016       __IOM uint32_t GCLK5      : 1;            /*!< [5..5] Gate IOM5 CLK in SPI mode, allowing external input clock           */
6017             uint32_t            : 26;
6018     } DBGCTRL_b;
6019   } ;
6020 } GPIO_Type;                                    /*!< Size = 596 (0x254)                                                        */
6021 
6022 
6023 
6024 /* =========================================================================================================================== */
6025 /* ================                                           IOM0                                            ================ */
6026 /* =========================================================================================================================== */
6027 
6028 
6029 /**
6030   * @brief IO Peripheral Master (IOM0)
6031   */
6032 
6033 typedef struct {                                /*!< (@ 0x50004000) IOM0 Structure                                             */
6034 
6035   union {
6036     __IOM uint32_t FIFO;                        /*!< (@ 0x00000000) Provides direct random access to both output
6037                                                                     and input FIFOs. The state of the FIFO is
6038                                                                     not disturbed by reading these locations
6039                                                                     (i.e., no POP will be done). FIFO0 is accessible
6040                                                                     from addresses 0x0 - 0x1C, and is used for
6041                                                                     data output from the IOM to external devices.
6042                                                                     These FIFO locations can be read and written
6043                                                                     directly.FIFO1 locations 0x20 - 0x3C provide
6044                                                                     read only access to the input FIFO. These
6045                                                                     FIFO locations cannot be directly written
6046                                                                     by the MCU and are updated only by the internal
6047                                                                     hardwa                                                     */
6048 
6049     struct {
6050       __IOM uint32_t FIFO       : 32;           /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return
6051                                                      valid information.                                                        */
6052     } FIFO_b;
6053   } ;
6054   __IM  uint32_t  RESERVED[63];
6055 
6056   union {
6057     __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Provides the current valid byte count of data
6058                                                                     within the FIFO as seen from the internal
6059                                                                     state machines. FIFO0 is dedicated to outgoing
6060                                                                     transactions and FIFO1 is dedicated to incoming
6061                                                                     transactions. All counts are specified in
6062                                                                     units of bytes.                                            */
6063 
6064     struct {
6065       __IOM uint32_t FIFO0SIZ   : 8;            /*!< [7..0] The number of valid data bytes currently in the FIFO
6066                                                      0 (written by MCU, read by interface)                                     */
6067       __IOM uint32_t FIFO0REM   : 8;            /*!< [15..8] The number of remaining data bytes slots currently in
6068                                                      FIFO 0 (written by MCU, read by interface)                                */
6069       __IOM uint32_t FIFO1SIZ   : 8;            /*!< [23..16] The number of valid data bytes currently in FIFO 1
6070                                                      (written by interface, read by MCU)                                       */
6071       __IOM uint32_t FIFO1REM   : 8;            /*!< [31..24] The number of remaining data bytes slots currently
6072                                                      in FIFO 1 (written by interface, read by MCU)                             */
6073     } FIFOPTR_b;
6074   } ;
6075 
6076   union {
6077     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000104) Sets the threshold values for incoming and outgoing
6078                                                                     transactions. The threshold values are used
6079                                                                     to assert the interrupt if enabled, and
6080                                                                     also used during DMA to set the transfer
6081                                                                     size as a result of DMATHR trigger.The WTHR
6082                                                                     is used to indicate when there are more
6083                                                                     than WTHR bytes of open FIFO locations available
6084                                                                     in the outgoing FIFO (FIFO0). The intended
6085                                                                     use to invoke an interrupt or DMA transfer
6086                                                                     that will refill the FIFO with a byte count
6087                                                                     up to this value.The RTHR is used to indicate
6088                                                                     when t                                                     */
6089 
6090     struct {
6091       __IOM uint32_t FIFORTHR   : 6;            /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable
6092                                                      the read FIFO level from activating the threshold interrupt.
6093                                                      If this field is non-zero, it will trigger a threshold
6094                                                      interrupt when the read FIFO contains FIFORTHR valid bytes
6095                                                      of data, as indicated by the FIFO1SIZ field. This is intended
6096                                                      to signal when a data transfer of FIFORTHR bytes can be
6097                                                      done from the IOM module to the host via the read FIFO
6098                                                      to support large IOM read operations.                                     */
6099             uint32_t            : 2;
6100       __IOM uint32_t FIFOWTHR   : 6;            /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable
6101                                                      the write FIFO level from activating the threshold interrupt.
6102                                                      If this field is non-zero, it will trigger a threshold
6103                                                      interrupt when the write FIFO contains FIFOWTHR free bytes,
6104                                                      as indicated by the FIFO0REM field. This is intended to
6105                                                      signal when a transfer of FIFOWTHR bytes can be done from
6106                                                      the host to the IOM write FIFO to support large IOM write
6107                                                      operations.                                                               */
6108             uint32_t            : 18;
6109     } FIFOTHR_b;
6110   } ;
6111 
6112   union {
6113     __IOM uint32_t FIFOPOP;                     /*!< (@ 0x00000108) Will advance the internal read pointer of the
6114                                                                     incoming FIFO (FIFO1) when read, if POPWR
6115                                                                     is not active. If POPWR is active, a write
6116                                                                     to this register is needed to advance the
6117                                                                     internal FIFO pointer.                                     */
6118 
6119     struct {
6120       __IOM uint32_t FIFODOUT   : 32;           /*!< [31..0] This register will return the read data indicated by
6121                                                      the current read pointer on reads. If the POPWR control
6122                                                      bit in the FIFOCTRL register is reset (0), the FIFO read
6123                                                      pointer will be advanced by one word as a result of the
6124                                                      read.If the POPWR bit is set (1), the FIFO read pointer
6125                                                      will only be advanced after a write operation to this register.
6126                                                      The write data is ignored for this register.If less than
6127                                                      a even word multiple is available, and the command is completed,
6128                                                      the module will return the word containing                                */
6129     } FIFOPOP_b;
6130   } ;
6131 
6132   union {
6133     __IOM uint32_t FIFOPUSH;                    /*!< (@ 0x0000010C) Will write new data into the outgoing FIFO and
6134                                                                     advance the internal write pointer.                        */
6135 
6136     struct {
6137       __IOM uint32_t FIFODIN    : 32;           /*!< [31..0] This register is used to write the FIFORAM in FIFO mode
6138                                                      and will cause a push event to occur to the next open slot
6139                                                      within the FIFORAM. Writing to this register will cause
6140                                                      the write point to increment by 1 word(4 bytes).                          */
6141     } FIFOPUSH_b;
6142   } ;
6143 
6144   union {
6145     __IOM uint32_t FIFOCTRL;                    /*!< (@ 0x00000110) Provides controls for the operation of the internal
6146                                                                     FIFOs. Contains fields used to control the
6147                                                                     operation of the POP register, and also
6148                                                                     controls to reset the internal pointers
6149                                                                     of the FIFOs.                                              */
6150 
6151     struct {
6152       __IOM uint32_t POPWR      : 1;            /*!< [0..0] Selects the mode in which 'pop' events are done for the
6153                                                      FIFO read operations. A value of '1' will prevent a pop
6154                                                      event on a read operation, and will require a write to
6155                                                      the FIFOPOP register to create a pop event.A value of '0'
6156                                                      in this register will allow a pop event to occur on the
6157                                                      read of the FIFOPOP register, and may cause inadvertent
6158                                                      FIFO pops when used in a debugging mode.                                  */
6159       __IOM uint32_t FIFORSTN   : 1;            /*!< [1..1] Active low manual reset of the FIFO. Write to 0 to reset
6160                                                      FIFO, and then write to 1 to remove the reset.                            */
6161             uint32_t            : 30;
6162     } FIFOCTRL_b;
6163   } ;
6164 
6165   union {
6166     __IOM uint32_t FIFOLOC;                     /*!< (@ 0x00000114) Provides a read only value of the current read
6167                                                                     and write pointers. This register is read
6168                                                                     only and can be used along with the FIFO
6169                                                                     direct access method to determine the next
6170                                                                     data to be used for input and output functions.            */
6171 
6172     struct {
6173       __IOM uint32_t FIFOWPTR   : 4;            /*!< [3..0] Current FIFO write pointer. Value is the index into the
6174                                                      outgoing FIFO (FIFO0), which is used during write operations
6175                                                      to external devices.                                                      */
6176             uint32_t            : 4;
6177       __IOM uint32_t FIFORPTR   : 4;            /*!< [11..8] Current FIFO read pointer. Used to index into the incoming
6178                                                      FIFO (FIFO1), which is used to store read data returned
6179                                                      from external devices during a read operation.                            */
6180             uint32_t            : 20;
6181     } FIFOLOC_b;
6182   } ;
6183   __IM  uint32_t  RESERVED1[58];
6184 
6185   union {
6186     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
6187                                                                     to generate the corresponding interrupt.                   */
6188 
6189     struct {
6190       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command complete interrupt                                         */
6191       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
6192                                                      when the number of free bytes in the write FIFO equals
6193                                                      or exceeds the WTHR field.For read operations, asserted
6194                                                      when the number of valid bytes in the read FIFO equals
6195                                                      of exceeds the value set in the RTHR field.                               */
6196       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
6197                                                      tries to pop from an empty FIFO.                                          */
6198       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
6199                                                      tries to write to a full FIFO. The current operation does
6200                                                      not stop.                                                                 */
6201       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
6202                                                      been received on the I2C bus.                                             */
6203       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
6204                                                      a overflow or underflow event                                             */
6205       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
6206                                                      written when an active command is in progress.                            */
6207       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
6208                                                      on the bus has signaled a START command.                                  */
6209       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
6210                                                      on the bus has signaled a STOP command.                                   */
6211       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
6212                                                      is enabled and has been lost to another master on the bus.                */
6213       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
6214                                                      and the DMA submodule is returned into the idle state                     */
6215       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
6216                                                      DMA command. The DMA error could occur when the memory
6217                                                      access specified in the DMA operation is not available
6218                                                      or incorrectly specified.                                                 */
6219       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
6220                                                      in the PAUSEEN register. The interrupt is posted when the
6221                                                      event is enabled within the PAUSEEN register, the mask
6222                                                      is active in the CQIRQMASK field and the event occurs.                    */
6223       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
6224                                                      the register address bit 0 set to 1. The low address bits
6225                                                      in the CQ address fields are unused and bit 0 can be used
6226                                                      to trigger an interrupt to indicate when this register
6227                                                      write is performed by the CQ operation.                                   */
6228       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
6229             uint32_t            : 17;
6230     } INTEN_b;
6231   } ;
6232 
6233   union {
6234     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
6235                                                                     cause of a recent interrupt.                               */
6236 
6237     struct {
6238       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command complete interrupt                                         */
6239       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
6240                                                      when the number of free bytes in the write FIFO equals
6241                                                      or exceeds the WTHR field.For read operations, asserted
6242                                                      when the number of valid bytes in the read FIFO equals
6243                                                      of exceeds the value set in the RTHR field.                               */
6244       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
6245                                                      tries to pop from an empty FIFO.                                          */
6246       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
6247                                                      tries to write to a full FIFO. The current operation does
6248                                                      not stop.                                                                 */
6249       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
6250                                                      been received on the I2C bus.                                             */
6251       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
6252                                                      a overflow or underflow event                                             */
6253       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
6254                                                      written when an active command is in progress.                            */
6255       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
6256                                                      on the bus has signaled a START command.                                  */
6257       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
6258                                                      on the bus has signaled a STOP command.                                   */
6259       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
6260                                                      is enabled and has been lost to another master on the bus.                */
6261       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
6262                                                      and the DMA submodule is returned into the idle state                     */
6263       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
6264                                                      DMA command. The DMA error could occur when the memory
6265                                                      access specified in the DMA operation is not available
6266                                                      or incorrectly specified.                                                 */
6267       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
6268                                                      in the PAUSEEN register. The interrupt is posted when the
6269                                                      event is enabled within the PAUSEEN register, the mask
6270                                                      is active in the CQIRQMASK field and the event occurs.                    */
6271       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
6272                                                      the register address bit 0 set to 1. The low address bits
6273                                                      in the CQ address fields are unused and bit 0 can be used
6274                                                      to trigger an interrupt to indicate when this register
6275                                                      write is performed by the CQ operation.                                   */
6276       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
6277             uint32_t            : 17;
6278     } INTSTAT_b;
6279   } ;
6280 
6281   union {
6282     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
6283                                                                     the interrupt status associated with that
6284                                                                     bit.                                                       */
6285 
6286     struct {
6287       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command complete interrupt                                         */
6288       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
6289                                                      when the number of free bytes in the write FIFO equals
6290                                                      or exceeds the WTHR field.For read operations, asserted
6291                                                      when the number of valid bytes in the read FIFO equals
6292                                                      of exceeds the value set in the RTHR field.                               */
6293       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
6294                                                      tries to pop from an empty FIFO.                                          */
6295       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
6296                                                      tries to write to a full FIFO. The current operation does
6297                                                      not stop.                                                                 */
6298       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
6299                                                      been received on the I2C bus.                                             */
6300       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
6301                                                      a overflow or underflow event                                             */
6302       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
6303                                                      written when an active command is in progress.                            */
6304       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
6305                                                      on the bus has signaled a START command.                                  */
6306       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
6307                                                      on the bus has signaled a STOP command.                                   */
6308       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
6309                                                      is enabled and has been lost to another master on the bus.                */
6310       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
6311                                                      and the DMA submodule is returned into the idle state                     */
6312       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
6313                                                      DMA command. The DMA error could occur when the memory
6314                                                      access specified in the DMA operation is not available
6315                                                      or incorrectly specified.                                                 */
6316       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
6317                                                      in the PAUSEEN register. The interrupt is posted when the
6318                                                      event is enabled within the PAUSEEN register, the mask
6319                                                      is active in the CQIRQMASK field and the event occurs.                    */
6320       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
6321                                                      the register address bit 0 set to 1. The low address bits
6322                                                      in the CQ address fields are unused and bit 0 can be used
6323                                                      to trigger an interrupt to indicate when this register
6324                                                      write is performed by the CQ operation.                                   */
6325       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
6326             uint32_t            : 17;
6327     } INTCLR_b;
6328   } ;
6329 
6330   union {
6331     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
6332                                                                     generate an interrupt from this module.
6333                                                                     (Generally used for testing purposes).                     */
6334 
6335     struct {
6336       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command complete interrupt                                         */
6337       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
6338                                                      when the number of free bytes in the write FIFO equals
6339                                                      or exceeds the WTHR field.For read operations, asserted
6340                                                      when the number of valid bytes in the read FIFO equals
6341                                                      of exceeds the value set in the RTHR field.                               */
6342       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
6343                                                      tries to pop from an empty FIFO.                                          */
6344       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
6345                                                      tries to write to a full FIFO. The current operation does
6346                                                      not stop.                                                                 */
6347       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
6348                                                      been received on the I2C bus.                                             */
6349       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
6350                                                      a overflow or underflow event                                             */
6351       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
6352                                                      written when an active command is in progress.                            */
6353       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
6354                                                      on the bus has signaled a START command.                                  */
6355       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
6356                                                      on the bus has signaled a STOP command.                                   */
6357       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
6358                                                      is enabled and has been lost to another master on the bus.                */
6359       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
6360                                                      and the DMA submodule is returned into the idle state                     */
6361       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
6362                                                      DMA command. The DMA error could occur when the memory
6363                                                      access specified in the DMA operation is not available
6364                                                      or incorrectly specified.                                                 */
6365       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
6366                                                      in the PAUSEEN register. The interrupt is posted when the
6367                                                      event is enabled within the PAUSEEN register, the mask
6368                                                      is active in the CQIRQMASK field and the event occurs.                    */
6369       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
6370                                                      the register address bit 0 set to 1. The low address bits
6371                                                      in the CQ address fields are unused and bit 0 can be used
6372                                                      to trigger an interrupt to indicate when this register
6373                                                      write is performed by the CQ operation.                                   */
6374       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
6375             uint32_t            : 17;
6376     } INTSET_b;
6377   } ;
6378 
6379   union {
6380     __IOM uint32_t CLKCFG;                      /*!< (@ 0x00000210) Provides clock related controls used internal
6381                                                                     to the BLEIF module, and enablement of 32KHz
6382                                                                     clock to the BLE Core module. The internal
6383                                                                     clock sourced is selected via the FSEL and
6384                                                                     can be further divided by 3 using the DIV3
6385                                                                     control.This register is also used to enable
6386                                                                     the clock, which must be done prior to performing
6387                                                                     any IO transactions.                                       */
6388 
6389     struct {
6390       __IOM uint32_t IOCLKEN    : 1;            /*!< [0..0] Enable for the interface clock. Must be enabled prior
6391                                                      to executing any IO operations.                                           */
6392             uint32_t            : 7;
6393       __IOM uint32_t FSEL       : 3;            /*!< [10..8] Select the input clock frequency.                                 */
6394       __IOM uint32_t DIV3       : 1;            /*!< [11..11] Enable divide by 3 of the source IOCLK. Division by
6395                                                      3 is done before the DIVEN programmable divider, and if
6396                                                      enabledwill provide the divided by 3 clock as the source
6397                                                      to the programmable divider.                                              */
6398       __IOM uint32_t DIVEN      : 1;            /*!< [12..12] Enable clock division by TOTPER and LOWPER                       */
6399             uint32_t            : 3;
6400       __IOM uint32_t LOWPER     : 8;            /*!< [23..16] Clock low clock count minus 1. This provides the number
6401                                                      of clocks the divided clock will be low when the DIVEN
6402                                                      = 1.Only applicable when DIVEN = 1.                                       */
6403       __IOM uint32_t TOTPER     : 8;            /*!< [31..24] Clock total clock count minus 1. This provides the
6404                                                      total period of the divided clock -1 when the DIVEN is
6405                                                      active. Thesource clock is selected by FSEL. Only applicable
6406                                                      when DIVEN = 1.                                                           */
6407     } CLKCFG_b;
6408   } ;
6409 
6410   union {
6411     __IOM uint32_t SUBMODCTRL;                  /*!< (@ 0x00000214) Provides enable for each submodule. Only a single
6412                                                                     submodule can be enabled at one time.                      */
6413 
6414     struct {
6415       __IOM uint32_t SMOD0EN    : 1;            /*!< [0..0] Submodule 0 enable (1) or disable (0)                              */
6416       __IOM uint32_t SMOD0TYPE  : 3;            /*!< [3..1] Submodule 0 module type. This is the SPI Master interface.         */
6417       __IOM uint32_t SMOD1EN    : 1;            /*!< [4..4] Submodule 1 enable (1) or disable (0)                              */
6418       __IOM uint32_t SMOD1TYPE  : 3;            /*!< [7..5] Submodule 0 module type. This is the I2C Master interface          */
6419             uint32_t            : 24;
6420     } SUBMODCTRL_b;
6421   } ;
6422 
6423   union {
6424     __IOM uint32_t CMD;                         /*!< (@ 0x00000218) Writes to this register will start an IO transaction,
6425                                                                     as well as set various parameters for the
6426                                                                     command itself. Reads will return the command
6427                                                                     value written to the CMD register.To read
6428                                                                     the number of bytes that have yet to be
6429                                                                     transferred, refer to the CTSIZE field within
6430                                                                     the CMDSTAT register.                                      */
6431 
6432     struct {
6433       __IOM uint32_t CMD        : 5;            /*!< [4..0] Command for submodule.                                             */
6434       __IOM uint32_t OFFSETCNT  : 2;            /*!< [6..5] Number of offset bytes to use for the command - 0, 1,
6435                                                      2, 3 are valid selections. The second (byte 1) and third
6436                                                      byte (byte 2) are read from the OFFSETHI register, and
6437                                                      the low order byte is pulled from this register in the
6438                                                      OFFSETLO field.Offset bytes are transmitted highest byte
6439                                                      first. EG if OFFSETCNT == 3, OFFSETHI[15:8] will be transmitted
6440                                                      first, then OFFSETHI[7:0] then OFFSETLO.If OFFSETCNT ==
6441                                                      2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.If
6442                                                      OFFSETCNT == 1, only OFFSETLO will be transmitted.                        */
6443       __IOM uint32_t CONT       : 1;            /*!< [7..7] Continue to hold the bus after the current transaction
6444                                                      if set to a 1 with a new command issued.                                  */
6445       __IOM uint32_t TSIZE      : 12;           /*!< [19..8] Defines the transaction size in bytes. The offset transfer
6446                                                      is not included in this size.                                             */
6447       __IOM uint32_t CMDSEL     : 2;            /*!< [21..20] Command Specific selection information. Not used in
6448                                                      Master I2C. Used as CEn select for Master SPI transactions                */
6449             uint32_t            : 2;
6450       __IOM uint32_t OFFSETLO   : 8;            /*!< [31..24] This register holds the low order byte of offset to
6451                                                      be used in the transaction. The number of offset bytes
6452                                                      to use is set with bits 1:0 of the command.                               */
6453     } CMD_b;
6454   } ;
6455 
6456   union {
6457     __IOM uint32_t DCX;                         /*!< (@ 0x0000021C) Enables use of CE signals to transmit DCX level
6458                                                                     for SPI transactions. Only used in Apollo3
6459                                                                     Revision B. For Revision A, this register
6460                                                                     MUST NOT be programmed!                                    */
6461 
6462     struct {
6463       __IOM uint32_t CE0OUT     : 1;            /*!< [0..0] Enable DCX output using CE0 output                                 */
6464       __IOM uint32_t CE1OUT     : 1;            /*!< [1..1] Enable DCX output using CE1 output                                 */
6465       __IOM uint32_t CE2OUT     : 1;            /*!< [2..2] Enable DCX output using CE2 output                                 */
6466       __IOM uint32_t CE3OUT     : 1;            /*!< [3..3] Enable DCX output using CE3 output                                 */
6467       __IOM uint32_t DCXEN      : 1;            /*!< [4..4] DCX Signaling Enable The selected DCX signal (unused
6468                                                      CE pin) will be driven low during write of offset byte,
6469                                                      and high during transmission of data bytes.                               */
6470             uint32_t            : 27;
6471     } DCX_b;
6472   } ;
6473 
6474   union {
6475     __IOM uint32_t OFFSETHI;                    /*!< (@ 0x00000220) High order 2 bytes of 3 byte offset for IO transaction     */
6476 
6477     struct {
6478       __IOM uint32_t OFFSETHI   : 16;           /*!< [15..0] Holds the high order 2 bytes of the 3 byte addressing/offset
6479                                                      field to use with IO commands. The number of offset bytes
6480                                                      to use is specified in the command register                               */
6481             uint32_t            : 16;
6482     } OFFSETHI_b;
6483   } ;
6484 
6485   union {
6486     __IOM uint32_t CMDSTAT;                     /*!< (@ 0x00000224) Provides status on the execution of the command
6487                                                                     currently in progress. The fields in this
6488                                                                     register will reflect the real time status
6489                                                                     of the internal state machines and data
6490                                                                     transfers within the IOM.These are read
6491                                                                     only fields and writes to the registers
6492                                                                     are ignored.                                               */
6493 
6494     struct {
6495       __IOM uint32_t CCMD       : 5;            /*!< [4..0] current command that is being executed                             */
6496       __IOM uint32_t CMDSTAT    : 3;            /*!< [7..5] The current status of the command execution.                       */
6497       __IOM uint32_t CTSIZE     : 12;           /*!< [19..8] The current number of bytes still to be transferred
6498                                                      with this command. This field will count down to zero.                    */
6499             uint32_t            : 12;
6500     } CMDSTAT_b;
6501   } ;
6502   __IM  uint32_t  RESERVED2[6];
6503 
6504   union {
6505     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000240) Provides control on which event will trigger
6506                                                                     the DMA transfer after the DMA operation
6507                                                                     is setup and enabled. The trigger event
6508                                                                     will cause a number of bytes (depending
6509                                                                     on trigger event) to betransferred via the
6510                                                                     DMA operation, and can be used to adjust
6511                                                                     the latency of data to/from the IOM module
6512                                                                     to/from the DMA target. DMA transfers are
6513                                                                     broken into smaller transfers internally
6514                                                                     of up to16 bytes each, and multiple trigger
6515                                                                     events can be used to complete the entire
6516                                                                     programmed DMA transfer.                                   */
6517 
6518     struct {
6519       __IOM uint32_t DCMDCMPEN  : 1;            /*!< [0..0] Trigger DMA upon command complete. Enables the trigger
6520                                                      of the DMA when a command is completed. When this event
6521                                                      is triggered, the number of words transferred will be the
6522                                                      lesser of the remaining TOTCOUNT bytes, or                                */
6523       __IOM uint32_t DTHREN     : 1;            /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations
6524                                                      (IOM writes), the trigger will assert when the write FIFO
6525                                                      has (WTHR/4) number of words free in the write FIFO, and
6526                                                      will transfer (WTHR/4) number of wordsor, if the number
6527                                                      of words left to transfer is less than the WTHR value,
6528                                                      will transfer the remaining byte count.For P2M DMA operations,
6529                                                      the trigger will assert when the read FIFO has (RTHR/4)
6530                                                      words available in the read FIFO, and will transfer (RTHR/4)
6531                                                      words to SRAM. This trigger will NOT asser                                */
6532             uint32_t            : 30;
6533     } DMATRIGEN_b;
6534   } ;
6535 
6536   union {
6537     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000244) Provides the status of trigger events that have
6538                                                                     occurred for the transaction. Some of the
6539                                                                     bits are read only and some can be reset
6540                                                                     via a write of 0.                                          */
6541 
6542     struct {
6543       __IOM uint32_t DCMDCMP    : 1;            /*!< [0..0] Triggered DMA from Command complete event. Bit is read
6544                                                      only and can be cleared by disabling the DCMDCMP trigger
6545                                                      enable or by disabling DMA.                                               */
6546       __IOM uint32_t DTHR       : 1;            /*!< [1..1] Triggered DMA from THR event. Bit is read only and can
6547                                                      be cleared by disabling the DTHR trigger enable or by disabling
6548                                                      DMA.                                                                      */
6549       __IOM uint32_t DTOTCMP    : 1;            /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data
6550                                                      in the FIFO was enough to complete the DMA operation (greater
6551                                                      than or equal to current TOTCOUNT) when the command completed.
6552                                                      This trigger is default active when the DCMDCMP trigger
6553                                                      isdisabled and there is enough data in the FIFO to complete
6554                                                      the DMA operation.                                                        */
6555             uint32_t            : 29;
6556     } DMATRIGSTAT_b;
6557   } ;
6558   __IM  uint32_t  RESERVED3[14];
6559 
6560   union {
6561     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000280) Configuration control of the DMA process, including
6562                                                                     the direction of DMA, and enablement of
6563                                                                     DMA                                                        */
6564 
6565     struct {
6566       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA
6567                                                      operation. This should be the last DMA related register
6568                                                      set prior to issuing the command                                          */
6569       __IOM uint32_t DMADIR     : 1;            /*!< [1..1] Direction                                                          */
6570             uint32_t            : 6;
6571       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
6572       __IOM uint32_t DPWROFF    : 1;            /*!< [9..9] Power off module after DMA is complete. If this bit is
6573                                                      active, the module will request to power off the supply
6574                                                      it is attached to. If there are other units still requiring
6575                                                      power from the same domain, power down will not be performed.             */
6576             uint32_t            : 22;
6577     } DMACFG_b;
6578   } ;
6579   __IM  uint32_t  RESERVED4;
6580 
6581   union {
6582     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000288) Contains the number of bytes to be transferred
6583                                                                     for this DMA transaction. This register
6584                                                                     is decremented as the data is transferred,
6585                                                                     and will be 0 at the completion of the DMA
6586                                                                     operation.                                                 */
6587 
6588     struct {
6589       __IOM uint32_t TOTCOUNT   : 12;           /*!< [11..0] Triggered DMA from Command complete event occurred.
6590                                                      Bit is read only and can be cleared by disabling the DTHR
6591                                                      trigger enable or by disabling DMA.                                       */
6592             uint32_t            : 20;
6593     } DMATOTCOUNT_b;
6594   } ;
6595 
6596   union {
6597     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x0000028C) The source or destination address internal the
6598                                                                     SRAM for the DMA data. For write operations,
6599                                                                     this can only be SRAM data (ADDR bit 28
6600                                                                     = 1); For read operations, this can be either
6601                                                                     SRAM or FLASH (ADDR bit 28 = 0)                            */
6602 
6603     struct {
6604       __IOM uint32_t TARGADDR   : 21;           /*!< [20..0] Bits [19:0] of the target byte address for source of
6605                                                      DMA (either read or write). The address can be any byte
6606                                                      alignment, and does not have to be word aligned. In cases
6607                                                      of non-word aligned addresses, the DMA logic will take
6608                                                      care for ensuring only the target bytes are read/written.                 */
6609             uint32_t            : 7;
6610       __IOM uint32_t TARGADDR28 : 1;            /*!< [28..28] Bit 28 of the target byte address for source of DMA
6611                                                      (either read or write). In cases of non-word aligned addresses,
6612                                                      the DMA logic will take care for ensuring only the target
6613                                                      bytes are read/written.Setting to '1' will select the SRAM.
6614                                                      Setting to '0' will select the flash                                      */
6615             uint32_t            : 3;
6616     } DMATARGADDR_b;
6617   } ;
6618 
6619   union {
6620     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000290) Status of the DMA operation currently in progress.         */
6621 
6622     struct {
6623       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
6624                                                      a DMA transfer is active. The DMA transfer may be waiting
6625                                                      on data, transferring data, or waiting for priority.All
6626                                                      of these will be indicated with a 1. A 0 will indicate
6627                                                      that the DMA is fully complete and no further transactions
6628                                                      will be done. This bit is read only.                                      */
6629       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
6630                                                      operation. This bit can be cleared by writing to 0, and
6631                                                      will also be cleared when a new DMA is started.                           */
6632       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals an error was
6633                                                      encountered during the DMA operation. The bit can be cleared
6634                                                      by writing to 0. Once set, this bit will remain set until
6635                                                      cleared by software.                                                      */
6636             uint32_t            : 29;
6637     } DMASTAT_b;
6638   } ;
6639 
6640   union {
6641     __IOM uint32_t CQCFG;                       /*!< (@ 0x00000294) Controls parameters and options for execution
6642                                                                     of the command queue operation. To enable
6643                                                                     command queue, create this in memory, set
6644                                                                     the address, and enable it with a write
6645                                                                     to CQEN                                                    */
6646 
6647     struct {
6648       __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
6649                                                      of the command queue and fetches of address/data pairs
6650                                                      will proceed from the word address within the CQADDR register.
6651                                                      Can be disabled using a CQ executed write to this bit as
6652                                                      well.                                                                     */
6653       __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue DMA request                 */
6654       __IOM uint32_t MSPIFLGSEL : 2;            /*!< [3..2] Selects the MPSI modules used for sourcing the CQFLAG
6655                                                      [11:8].                                                                   */
6656             uint32_t            : 28;
6657     } CQCFG_b;
6658   } ;
6659 
6660   union {
6661     __IOM uint32_t CQADDR;                      /*!< (@ 0x00000298) The SRAM address which will be fetched next execution
6662                                                                     of the CQ operation. This register is updated
6663                                                                     as the CQ operation progresses, and is the
6664                                                                     live version of the register. The register
6665                                                                     can also be written by the Command Queue
6666                                                                     operation itself, allowing the relocation
6667                                                                     of successive CQ fetches. In this case,
6668                                                                     the new CQ address will be used for the
6669                                                                     next CQ address/data fetch.                                */
6670 
6671     struct {
6672             uint32_t            : 2;
6673       __IOM uint32_t CQADDR     : 19;           /*!< [20..2] Bits 19:2 of target byte address for source of CQ. The
6674                                                      buffer must be aligned on a word boundary                                 */
6675             uint32_t            : 7;
6676       __IOM uint32_t CQADDR28   : 1;            /*!< [28..28] Bit 28 of target byte address for source of CQ. Used
6677                                                      to denote Flash (0) or SRAM (1) access                                    */
6678             uint32_t            : 3;
6679     } CQADDR_b;
6680   } ;
6681 
6682   union {
6683     __IOM uint32_t CQSTAT;                      /*!< (@ 0x0000029C) Provides the status of the command queue operation.
6684                                                                     If the command queue is disabled, these
6685                                                                     bits will be cleared. The bits are read
6686                                                                     only                                                       */
6687 
6688     struct {
6689       __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
6690                                                      indicate that a CQ transfer is active and this will remain
6691                                                      active even when paused waiting for external event.                       */
6692       __IOM uint32_t CQPAUSED   : 1;            /*!< [1..1] Command queue operation is currently paused.                       */
6693       __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing Error. This active high bit
6694                                                      signals that an error was encountered during the CQ operation.            */
6695             uint32_t            : 29;
6696     } CQSTAT_b;
6697   } ;
6698 
6699   union {
6700     __IOM uint32_t CQFLAGS;                     /*!< (@ 0x000002A0) Command Queue Flag                                         */
6701 
6702     struct {
6703       __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
6704                                                      controllable and bits [15:8] are hardware status.                         */
6705       __IOM uint32_t CQIRQMASK  : 16;           /*!< [31..16] Mask the bits used to generate the command queue interrupt.
6706                                                      A '1' in the bit position will enable the pause event to
6707                                                      trigger the interrupt, if the CQWT_int interrupt is enabled.
6708                                                      Bits definitions are the same as CQPAUSE                                  */
6709     } CQFLAGS_b;
6710   } ;
6711 
6712   union {
6713     __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x000002A4) Set/Clear the command queue software pause flags
6714                                                                     on a per-bit basis. Contains 3 fields, allowing
6715                                                                     for setting, clearing or toggling the value
6716                                                                     in the software flags. Priority when the
6717                                                                     same bitis enabled in each field is toggle,
6718                                                                     then set, then clear.                                      */
6719 
6720     struct {
6721       __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any
6722                                                      SWFLAG with a '1' in the corresponding bit position of
6723                                                      this field                                                                */
6724       __IOM uint32_t CQFTGL     : 8;            /*!< [15..8] Toggle the indicated bit. Will toggle the value of any
6725                                                      SWFLAG with a '1' in the corresponding bit position of
6726                                                      this field                                                                */
6727       __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG
6728                                                      with a '1' in the corresponding bit position of this field                */
6729             uint32_t            : 8;
6730     } CQSETCLEAR_b;
6731   } ;
6732 
6733   union {
6734     __IOM uint32_t CQPAUSEEN;                   /*!< (@ 0x000002A8) Enables a flag to pause an active command queue
6735                                                                     operation. If a bit is '1' and the corresponding
6736                                                                     bit in the CQFLAG register is '1', CQ processing
6737                                                                     will halt until either value is changed
6738                                                                     to '0'.                                                    */
6739 
6740     struct {
6741       __IOM uint32_t CQPEN      : 16;           /*!< [15..0] Enables the specified event to pause command processing
6742                                                      when active                                                               */
6743             uint32_t            : 16;
6744     } CQPAUSEEN_b;
6745   } ;
6746 
6747   union {
6748     __IOM uint32_t CQCURIDX;                    /*!< (@ 0x000002AC) Current index value, targeted to be written by
6749                                                                     register write operations within the command
6750                                                                     queue. This is compared to the CQENDIDX
6751                                                                     and will stop the CQ operation if bit 15
6752                                                                     of the CQPAUSEEN is '1' andthis current
6753                                                                     index equals the CQENDIDX register value.
6754                                                                     This will only pause when the values are
6755                                                                     equal.                                                     */
6756 
6757     struct {
6758       __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX
6759                                                      register field. If the values match, the IDXEQ pause event
6760                                                      will be activated, which will cause the pausing of command
6761                                                      queue operation if the IDXEQ bit is enabled in CQPAUSEEN.                 */
6762             uint32_t            : 24;
6763     } CQCURIDX_b;
6764   } ;
6765 
6766   union {
6767     __IOM uint32_t CQENDIDX;                    /*!< (@ 0x000002B0) End index value, targeted to be written by software
6768                                                                     to indicate the last valid register pair
6769                                                                     contained within the command queue for a
6770                                                                     register write operations within the command
6771                                                                     queue.This is compared to the CQCURIDX and
6772                                                                     will stop the CQ operation if bit 15 of
6773                                                                     the CQPAUSEEN is '1' andthis current index
6774                                                                     equals the CQCURIDX register value. This
6775                                                                     will only pause when the values are equal.                 */
6776 
6777     struct {
6778       __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX
6779                                                      register field. If the values match, the IDXEQ pause event
6780                                                      will be activated, which will cause the pausing of command
6781                                                      queue operation if the IDXEQ bit is enabled in CQPAUSEEN.                 */
6782             uint32_t            : 24;
6783     } CQENDIDX_b;
6784   } ;
6785 
6786   union {
6787     __IOM uint32_t STATUS;                      /*!< (@ 0x000002B4) IOM Module Status                                          */
6788 
6789     struct {
6790       __IOM uint32_t ERR        : 1;            /*!< [0..0] Bit has been deprecated. Please refer to the other error
6791                                                      indicators. This will always return 0.                                    */
6792       __IOM uint32_t CMDACT     : 1;            /*!< [1..1] Indicates if the active I/O Command is currently processing
6793                                                      a transaction, or command is complete, but the FIFO pointers
6794                                                      are still synchronizing internally. This bit will go high
6795                                                      atthe start of the transaction, and will go low when the
6796                                                      command is complete, and the data and pointers within the
6797                                                      FIFO have been synchronized.                                              */
6798       __IOM uint32_t IDLEST     : 1;            /*!< [2..2] indicates if the active I/O state machine is IDLE. Note
6799                                                      - The state machine could be in idle state due to hold-offs
6800                                                      from data availability, or as the command gets propagated
6801                                                      into the logic from the registers.                                        */
6802             uint32_t            : 29;
6803     } STATUS_b;
6804   } ;
6805   __IM  uint32_t  RESERVED5[18];
6806 
6807   union {
6808     __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000300) Controls the configuration of the SPI master
6809                                                                     module, including POL/PHA, LSB, flow control,
6810                                                                     and delays for MISO and MOSI                               */
6811 
6812     struct {
6813       __IOM uint32_t SPOL       : 1;            /*!< [0..0] selects SPI polarity.                                              */
6814       __IOM uint32_t SPHA       : 1;            /*!< [1..1] selects SPI phase.                                                 */
6815       __IOM uint32_t FULLDUP    : 1;            /*!< [2..2] Enables full duplex mode for Master SPI write operations.
6816                                                      Data will be captured simultaneously into the read FIFO                   */
6817             uint32_t            : 13;
6818       __IOM uint32_t WTFC       : 1;            /*!< [16..16] enables write mode flow control.                                 */
6819       __IOM uint32_t RDFC       : 1;            /*!< [17..17] enables read mode flow control.                                  */
6820       __IOM uint32_t MOSIINV    : 1;            /*!< [18..18] inverts MOSI when flow control is enabled.                       */
6821             uint32_t            : 1;
6822       __IOM uint32_t WTFCIRQ    : 1;            /*!< [20..20] selects the write mode flow control signal.                      */
6823       __IOM uint32_t WTFCPOL    : 1;            /*!< [21..21] selects the write flow control signal polarity. The
6824                                                      transfers are halted when the selected flow control signal
6825                                                      is OPPOSITE polarity of bit. (For example: WTFCPOL = 0
6826                                                      will allow a IRQ=1 to pause transfers).                                   */
6827       __IOM uint32_t RDFCPOL    : 1;            /*!< [22..22] selects the read flow control signal polarity.                   */
6828       __IOM uint32_t SPILSB     : 1;            /*!< [23..23] Selects data transfer as MSB first (0) or LSB first
6829                                                      (1) for the data portion of the SPI transaction. The offset
6830                                                      bytes are always transmitted MSB first.                                   */
6831       __IOM uint32_t DINDLY     : 3;            /*!< [26..24] Delay tap to use for the input signal (MISO). This
6832                                                      gives more hold time on the input data.                                   */
6833       __IOM uint32_t DOUTDLY    : 3;            /*!< [29..27] Delay tap to use for the output signal (MOSI). This
6834                                                      give more hold time on the output data                                    */
6835       __IOM uint32_t MSPIRST    : 1;            /*!< [30..30] Not used. To reset the module, toggle the SMOD_EN for
6836                                                      the module                                                                */
6837             uint32_t            : 1;
6838     } MSPICFG_b;
6839   } ;
6840   __IM  uint32_t  RESERVED6[63];
6841 
6842   union {
6843     __IOM uint32_t MI2CCFG;                     /*!< (@ 0x00000400) Controls the configuration of the I2C bus master.          */
6844 
6845     struct {
6846       __IOM uint32_t ADDRSZ     : 1;            /*!< [0..0] Sets the I2C master device address size to either 7 bits
6847                                                      (0) or 10 bits (1).                                                       */
6848       __IOM uint32_t I2CLSB     : 1;            /*!< [1..1] Direction of data transmit and receive, MSB(0) or LSB(1)
6849                                                      first. Default per I2C specification is MSB first. This
6850                                                      applies to both read and write data, and read data will
6851                                                      be bit                                                                    */
6852       __IOM uint32_t ARBEN      : 1;            /*!< [2..2] Enables multi-master arbitration for the I2C master.
6853                                                      If the bus is known to have only a single master, this
6854                                                      function can be disabled to save clock cycles on I2C transactions         */
6855             uint32_t            : 1;
6856       __IOM uint32_t SDADLY     : 2;            /*!< [5..4] Delay to enable on the SDA output. Values are 0x0-0x3.             */
6857       __IOM uint32_t MI2CRST    : 1;            /*!< [6..6] Not used. To reset the module, toggle the SMOD_EN for
6858                                                      the module                                                                */
6859             uint32_t            : 1;
6860       __IOM uint32_t SCLENDLY   : 4;            /*!< [11..8] Number of IOCLK cycles to delay the rising edge of the
6861                                                      SCL output en (clock will go low on this edge). Used to
6862                                                      allow clock shaping.                                                      */
6863       __IOM uint32_t SDAENDLY   : 4;            /*!< [15..12] Number of IOCLK cycles to delay the SDA output en (all
6864                                                      transitions affected). Used to delay data relative to clock               */
6865       __IOM uint32_t SMPCNT     : 8;            /*!< [23..16] Number of Base clock cycles to wait before sampling
6866                                                      the SCL clock to determine if a clock stretch event has
6867                                                      occurred                                                                  */
6868       __IOM uint32_t STRDIS     : 1;            /*!< [24..24] Disable detection of clock stretch events smaller than
6869                                                      1 cycle                                                                   */
6870             uint32_t            : 7;
6871     } MI2CCFG_b;
6872   } ;
6873 
6874   union {
6875     __IOM uint32_t DEVCFG;                      /*!< (@ 0x00000404) Contains the I2C device address.                           */
6876 
6877     struct {
6878       __IOM uint32_t DEVADDR    : 10;           /*!< [9..0] I2C address of the device that the Master will use to
6879                                                      target for read/write operations. This can be either a
6880                                                      7-bit or 10-bit address.                                                  */
6881             uint32_t            : 22;
6882     } DEVCFG_b;
6883   } ;
6884   __IM  uint32_t  RESERVED7[2];
6885 
6886   union {
6887     __IOM uint32_t IOMDBG;                      /*!< (@ 0x00000410) Debug control                                              */
6888 
6889     struct {
6890       __IOM uint32_t DBGEN      : 1;            /*!< [0..0] Debug Enable. Setting bit will enable the update of data
6891                                                      within this register, otherwise it is clock gated for power
6892                                                      savings                                                                   */
6893       __IOM uint32_t IOCLKON    : 1;            /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active
6894                                                      when this bit is '1'. Otherwise, the clock is controlled
6895                                                      with gating from the logic as needed.                                     */
6896       __IOM uint32_t APBCLKON   : 1;            /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
6897                                                      when this bit is '1'. Otherwise, the clock is controlled
6898                                                      with gating from the logic as needed.                                     */
6899       __IOM uint32_t DBGDATA    : 29;           /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used
6900                                                      to select between different debug data available in the
6901                                                      DBG0 and DBG1 registers.                                                  */
6902     } IOMDBG_b;
6903   } ;
6904 } IOM0_Type;                                    /*!< Size = 1044 (0x414)                                                       */
6905 
6906 
6907 
6908 /* =========================================================================================================================== */
6909 /* ================                                          IOSLAVE                                          ================ */
6910 /* =========================================================================================================================== */
6911 
6912 
6913 /**
6914   * @brief I2C/SPI Slave (IOSLAVE)
6915   */
6916 
6917 typedef struct {                                /*!< (@ 0x50000000) IOSLAVE Structure                                          */
6918   __IM  uint32_t  RESERVED[64];
6919 
6920   union {
6921     __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Current FIFO Pointer                                       */
6922 
6923     struct {
6924       __IOM uint32_t FIFOPTR    : 8;            /*!< [7..0] Current FIFO pointer.                                              */
6925       __IOM uint32_t FIFOSIZ    : 8;            /*!< [15..8] The number of bytes currently in the hardware FIFO.               */
6926             uint32_t            : 16;
6927     } FIFOPTR_b;
6928   } ;
6929 
6930   union {
6931     __IOM uint32_t FIFOCFG;                     /*!< (@ 0x00000104) FIFO Configuration                                         */
6932 
6933     struct {
6934       __IOM uint32_t FIFOBASE   : 5;            /*!< [4..0] These bits hold the base address of the I/O FIFO in 8
6935                                                      byte segments. The IO Slave FIFO is situated in LRAM at
6936                                                      (FIFOBASE*8) to (FIFOMAX*8-1).                                            */
6937             uint32_t            : 3;
6938       __IOM uint32_t FIFOMAX    : 6;            /*!< [13..8] These bits hold the maximum FIFO address in 8 byte segments.
6939                                                      It is also the beginning of the RAM area of the LRAM. Note
6940                                                      that no RAM area is configured if FIFOMAX is set to 0x1F.                 */
6941             uint32_t            : 10;
6942       __IOM uint32_t ROBASE     : 6;            /*!< [29..24] Defines the read-only area. The IO Slave read-only
6943                                                      area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1)                  */
6944             uint32_t            : 2;
6945     } FIFOCFG_b;
6946   } ;
6947 
6948   union {
6949     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000108) FIFO Threshold Configuration                               */
6950 
6951     struct {
6952       __IOM uint32_t FIFOTHR    : 8;            /*!< [7..0] FIFO size interrupt threshold.                                     */
6953             uint32_t            : 24;
6954     } FIFOTHR_b;
6955   } ;
6956 
6957   union {
6958     __IOM uint32_t FUPD;                        /*!< (@ 0x0000010C) FIFO Update Status                                         */
6959 
6960     struct {
6961       __IOM uint32_t FIFOUPD    : 1;            /*!< [0..0] This bit indicates that a FIFO update is underway.                 */
6962       __IOM uint32_t IOREAD     : 1;            /*!< [1..1] This bit field indicates an IO read is active.                     */
6963             uint32_t            : 30;
6964     } FUPD_b;
6965   } ;
6966 
6967   union {
6968     __IOM uint32_t FIFOCTR;                     /*!< (@ 0x00000110) Overall FIFO Counter                                       */
6969 
6970     struct {
6971       __IOM uint32_t FIFOCTR    : 10;           /*!< [9..0] Virtual FIFO byte count                                            */
6972             uint32_t            : 22;
6973     } FIFOCTR_b;
6974   } ;
6975 
6976   union {
6977     __IOM uint32_t FIFOINC;                     /*!< (@ 0x00000114) Overall FIFO Counter Increment                             */
6978 
6979     struct {
6980       __IOM uint32_t FIFOINC    : 10;           /*!< [9..0] Increment the Overall FIFO Counter by this value on a
6981                                                      write                                                                     */
6982             uint32_t            : 22;
6983     } FIFOINC_b;
6984   } ;
6985 
6986   union {
6987     __IOM uint32_t CFG;                         /*!< (@ 0x00000118) I/O Slave Configuration                                    */
6988 
6989     struct {
6990       __IOM uint32_t IFCSEL     : 1;            /*!< [0..0] This bit selects the I/O interface.                                */
6991       __IOM uint32_t SPOL       : 1;            /*!< [1..1] This bit selects SPI polarity.                                     */
6992       __IOM uint32_t LSB        : 1;            /*!< [2..2] This bit selects the transfer bit ordering.                        */
6993             uint32_t            : 1;
6994       __IOM uint32_t STARTRD    : 1;            /*!< [4..4] This bit holds the cycle to initiate an I/O RAM read.              */
6995             uint32_t            : 3;
6996       __IOM uint32_t I2CADDR    : 12;           /*!< [19..8] 7-bit or 10-bit I2C device address.                               */
6997             uint32_t            : 11;
6998       __IOM uint32_t IFCEN      : 1;            /*!< [31..31] IOSLAVE interface enable.                                        */
6999     } CFG_b;
7000   } ;
7001 
7002   union {
7003     __IOM uint32_t PRENC;                       /*!< (@ 0x0000011C) I/O Slave Interrupt Priority Encode                        */
7004 
7005     struct {
7006       __IOM uint32_t PRENC      : 5;            /*!< [4..0] These bits hold the priority encode of the REGACC interrupts.      */
7007             uint32_t            : 27;
7008     } PRENC_b;
7009   } ;
7010 
7011   union {
7012     __IOM uint32_t IOINTCTL;                    /*!< (@ 0x00000120) I/O Interrupt Control                                      */
7013 
7014     struct {
7015       __IOM uint32_t IOINTEN    : 8;            /*!< [7..0] These read-only bits indicate whether the IOINT interrupts
7016                                                      are enabled.                                                              */
7017       __IOM uint32_t IOINT      : 8;            /*!< [15..8] These bits read the IOINT interrupts.                             */
7018       __IOM uint32_t IOINTCLR   : 1;            /*!< [16..16] This bit clears all of the IOINT interrupts when written
7019                                                      with a 1.                                                                 */
7020             uint32_t            : 7;
7021       __IOM uint32_t IOINTSET   : 8;            /*!< [31..24] These bits set the IOINT interrupts when written with
7022                                                      a 1.                                                                      */
7023     } IOINTCTL_b;
7024   } ;
7025 
7026   union {
7027     __IOM uint32_t GENADD;                      /*!< (@ 0x00000124) General Address Data                                       */
7028 
7029     struct {
7030       __IOM uint32_t GADATA     : 8;            /*!< [7..0] The data supplied on the last General Address reference.           */
7031             uint32_t            : 24;
7032     } GENADD_b;
7033   } ;
7034   __IM  uint32_t  RESERVED1[54];
7035 
7036   union {
7037     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
7038                                                                     to generate the corresponding interrupt.                   */
7039 
7040     struct {
7041       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
7042       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
7043       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
7044       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
7045       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
7046       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
7047       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
7048       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
7049       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
7050       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
7051             uint32_t            : 22;
7052     } INTEN_b;
7053   } ;
7054 
7055   union {
7056     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
7057                                                                     cause of a recent interrupt.                               */
7058 
7059     struct {
7060       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
7061       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
7062       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
7063       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
7064       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
7065       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
7066       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
7067       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
7068       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
7069       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
7070             uint32_t            : 22;
7071     } INTSTAT_b;
7072   } ;
7073 
7074   union {
7075     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
7076                                                                     the interrupt status associated with that
7077                                                                     bit.                                                       */
7078 
7079     struct {
7080       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
7081       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
7082       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
7083       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
7084       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
7085       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
7086       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
7087       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
7088       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
7089       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
7090             uint32_t            : 22;
7091     } INTCLR_b;
7092   } ;
7093 
7094   union {
7095     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
7096                                                                     generate an interrupt from this module.
7097                                                                     (Generally used for testing purposes).                     */
7098 
7099     struct {
7100       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
7101       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
7102       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
7103       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
7104       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
7105       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
7106       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
7107       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
7108       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
7109       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
7110             uint32_t            : 22;
7111     } INTSET_b;
7112   } ;
7113 
7114   union {
7115     __IOM uint32_t REGACCINTEN;                 /*!< (@ 0x00000210) Set bits in this register to allow this module
7116                                                                     to generate the corresponding interrupt.                   */
7117 
7118     struct {
7119       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
7120     } REGACCINTEN_b;
7121   } ;
7122 
7123   union {
7124     __IOM uint32_t REGACCINTSTAT;               /*!< (@ 0x00000214) Read bits from this register to discover the
7125                                                                     cause of a recent interrupt.                               */
7126 
7127     struct {
7128       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
7129     } REGACCINTSTAT_b;
7130   } ;
7131 
7132   union {
7133     __IOM uint32_t REGACCINTCLR;                /*!< (@ 0x00000218) Write a 1 to a bit in this register to clear
7134                                                                     the interrupt status associated with that
7135                                                                     bit.                                                       */
7136 
7137     struct {
7138       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
7139     } REGACCINTCLR_b;
7140   } ;
7141 
7142   union {
7143     __IOM uint32_t REGACCINTSET;                /*!< (@ 0x0000021C) Write a 1 to a bit in this register to instantly
7144                                                                     generate an interrupt from this module.
7145                                                                     (Generally used for testing purposes).                     */
7146 
7147     struct {
7148       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
7149     } REGACCINTSET_b;
7150   } ;
7151 } IOSLAVE_Type;                                 /*!< Size = 544 (0x220)                                                        */
7152 
7153 
7154 
7155 /* =========================================================================================================================== */
7156 /* ================                                          MCUCTRL                                          ================ */
7157 /* =========================================================================================================================== */
7158 
7159 
7160 /**
7161   * @brief MCU Miscellaneous Control Logic (MCUCTRL)
7162   */
7163 
7164 typedef struct {                                /*!< (@ 0x40020000) MCUCTRL Structure                                          */
7165 
7166   union {
7167     __IOM uint32_t CHIPPN;                      /*!< (@ 0x00000000) Chip Information Register                                  */
7168 
7169     struct {
7170       __IOM uint32_t PARTNUM    : 32;           /*!< [31..0] BCD part number.                                                  */
7171     } CHIPPN_b;
7172   } ;
7173 
7174   union {
7175     __IOM uint32_t CHIPID0;                     /*!< (@ 0x00000004) Unique Chip ID 0                                           */
7176 
7177     struct {
7178       __IOM uint32_t CHIPID0    : 32;           /*!< [31..0] Unique chip ID 0.                                                 */
7179     } CHIPID0_b;
7180   } ;
7181 
7182   union {
7183     __IOM uint32_t CHIPID1;                     /*!< (@ 0x00000008) Unique Chip ID 1                                           */
7184 
7185     struct {
7186       __IOM uint32_t CHIPID1    : 32;           /*!< [31..0] Unique chip ID 1.                                                 */
7187     } CHIPID1_b;
7188   } ;
7189 
7190   union {
7191     __IOM uint32_t CHIPREV;                     /*!< (@ 0x0000000C) Chip Revision                                              */
7192 
7193     struct {
7194       __IOM uint32_t REVMIN     : 4;            /*!< [3..0] Minor Revision ID.                                                 */
7195       __IOM uint32_t REVMAJ     : 4;            /*!< [7..4] Major Revision ID.                                                 */
7196       __IOM uint32_t SIPART     : 12;           /*!< [19..8] Silicon Part ID                                                   */
7197             uint32_t            : 12;
7198     } CHIPREV_b;
7199   } ;
7200 
7201   union {
7202     __IOM uint32_t VENDORID;                    /*!< (@ 0x00000010) Unique Vendor ID                                           */
7203 
7204     struct {
7205       __IOM uint32_t VENDORID   : 32;           /*!< [31..0] Unique Vendor ID                                                  */
7206     } VENDORID_b;
7207   } ;
7208 
7209   union {
7210     __IOM uint32_t SKU;                         /*!< (@ 0x00000014) Unique Chip SKU                                            */
7211 
7212     struct {
7213       __IOM uint32_t ALLOWBURST : 1;            /*!< [0..0] Allow Burst feature                                                */
7214       __IOM uint32_t ALLOWBLE   : 1;            /*!< [1..1] Allow BLE feature                                                  */
7215       __IOM uint32_t SECBOOT    : 1;            /*!< [2..2] Secure boot feature allowed                                        */
7216             uint32_t            : 29;
7217     } SKU_b;
7218   } ;
7219 
7220   union {
7221     __IOM uint32_t FEATUREENABLE;               /*!< (@ 0x00000018) Feature Enable on Burst and BLE                            */
7222 
7223     struct {
7224       __IOM uint32_t BLEREQ     : 1;            /*!< [0..0] Controls the BLE functionality                                     */
7225       __IOM uint32_t BLEACK     : 1;            /*!< [1..1] ACK for BLEREQ                                                     */
7226       __IOM uint32_t BLEAVAIL   : 1;            /*!< [2..2] AVAILABILITY of the BLE functionality                              */
7227             uint32_t            : 1;
7228       __IOM uint32_t BURSTREQ   : 1;            /*!< [4..4] Controls the Burst functionality                                   */
7229       __IOM uint32_t BURSTACK   : 1;            /*!< [5..5] ACK for BURSTREQ                                                   */
7230       __IOM uint32_t BURSTAVAIL : 1;            /*!< [6..6] Availability of Burst functionality                                */
7231             uint32_t            : 25;
7232     } FEATUREENABLE_b;
7233   } ;
7234   __IM  uint32_t  RESERVED;
7235 
7236   union {
7237     __IOM uint32_t DEBUGGER;                    /*!< (@ 0x00000020) Debugger Control                                           */
7238 
7239     struct {
7240       __IOM uint32_t LOCKOUT    : 1;            /*!< [0..0] Lockout of debugger (SWD).                                         */
7241             uint32_t            : 31;
7242     } DEBUGGER_b;
7243   } ;
7244   __IM  uint32_t  RESERVED1[5];
7245 
7246   union {
7247     __IOM uint32_t DMASRAMWRITEPROTECT2;        /*!< (@ 0x00000038) These bits write-protect system SRAM from DMA
7248                                                                     operations in 8KB chunks.                                  */
7249 
7250     struct {
7251       __IOM uint32_t DMA_WPROT2 : 32;           /*!< [31..0] Write protect SRAM from DMA. Each bit provides write
7252                                                      protection for an 8KB region of memory. When set to 1,
7253                                                      the region will be protected from DMA writes, when set
7254                                                      to 0, DMA may write the region.                                           */
7255     } DMASRAMWRITEPROTECT2_b;
7256   } ;
7257   __IM  uint32_t  RESERVED2[9];
7258 
7259   union {
7260     __IOM uint32_t VRCTRL1;                     /*!< (@ 0x00000060) PRIMARY Voltage Regulator Control                          */
7261 
7262     struct {
7263             uint32_t            : 5;
7264       __IOM uint32_t BLEBUCKRSTB : 1;           /*!< [5..5] BLE BUCK RSTB control. Override for PWRCTRL going to
7265                                                      analog when BLEBUCKOVER = 1                                               */
7266       __IOM uint32_t BLEBUCKACTIVE : 1;         /*!< [6..6] BLE BUCK ACTIVE control. Override for PWRCTRL going to
7267                                                      analog when BLEBUCKOVER = 1                                               */
7268       __IOM uint32_t BLEBUCKPDNB : 1;           /*!< [7..7] BLE BUCK PDNB control. Override for PWRCTRL going to
7269                                                      analog when BLEBUCKOVER = 1                                               */
7270       __IOM uint32_t BLEBUCKOVER : 1;           /*!< [8..8] Override control for BLE BUCK signals                              */
7271             uint32_t            : 23;
7272     } VRCTRL1_b;
7273   } ;
7274 
7275   union {
7276     __IOM uint32_t VRCTRL2;                     /*!< (@ 0x00000064) SECONDARY Voltage Regulator Control                        */
7277 
7278     struct {
7279       __IOM uint32_t BURSTLDOCOLDSTARTEN : 1;   /*!< [0..0] BURST LDO COLDSTART EN control. Override for PWRCTRL
7280                                                      going to analog when BURSTLDOOVER = 1                                     */
7281       __IOM uint32_t BURSTLDOACTIVE : 1;        /*!< [1..1] BURST LDO ACTIVE control. Override for PWRCTRL going
7282                                                      to analog when BURSTLDOOVER = 1                                           */
7283       __IOM uint32_t BURSTLDOACTIVEEARLY : 1;   /*!< [2..2] BURST LDO EARLY ACTIVE control. Override for PWRCTRL
7284                                                      going to analog when BURSTLDOOVER = 1                                     */
7285       __IOM uint32_t BURSTLDOPDNB : 1;          /*!< [3..3] BURST LDO PDNB control. Override for PWRCTRL going to
7286                                                      analog when BURSTLDOOVER = 1                                              */
7287       __IOM uint32_t BURSTLDOOVER : 1;          /*!< [4..4] Override control for BURST LDO signals                             */
7288             uint32_t            : 27;
7289     } VRCTRL2_b;
7290   } ;
7291   __IM  uint32_t  RESERVED3[6];
7292 
7293   union {
7294     __IOM uint32_t LDOREG1;                     /*!< (@ 0x00000080) CORELDO trims Reg                                          */
7295 
7296     struct {
7297       __IOM uint32_t CORELDOACTIVETRIM : 10;    /*!< [9..0] CORE LDO active trim                                               */
7298       __IOM uint32_t CORELDOTEMPCOTRIM : 4;     /*!< [13..10] CORE LDO TEMPCO trim                                             */
7299       __IOM uint32_t CORELDOLPTRIM : 6;         /*!< [19..14] CORE LDO Low Power Trim                                          */
7300       __IOM uint32_t CORELDOIBIASTRIM : 1;      /*!< [20..20] CORE LDO Ibias Trim                                              */
7301       __IOM uint32_t CORELDOIBIASSEL : 1;       /*!< [21..21] Core LDO Ibias select. Note: the SWE mux select in
7302                                                      PWRSEQ2SWE must be set for this to take effect.                           */
7303             uint32_t            : 10;
7304     } LDOREG1_b;
7305   } ;
7306   __IM  uint32_t  RESERVED4;
7307 
7308   union {
7309     __IOM uint32_t LDOREG2;                     /*!< (@ 0x00000088) MEMLDO and MEMLPLDO Trims                                  */
7310 
7311     struct {
7312       __IOM uint32_t MEMLDOACTIVETRIM : 6;      /*!< [5..0] MEM LDO active trim                                                */
7313       __IOM uint32_t MEMLDOLPTRIM : 6;          /*!< [11..6] MEM LDO LP trim                                                   */
7314       __IOM uint32_t MEMLDOLPALTTRIM : 6;       /*!< [17..12] Mem LDO trim LP alternate set                                    */
7315       __IOM uint32_t MEMLPLDOTRIM : 6;          /*!< [23..18] Mem LPLDO trim                                                   */
7316       __IOM uint32_t MEMLPLDOIBIASTRIM : 1;     /*!< [24..24] Mem LPLDO Ibias trim                                             */
7317       __IOM uint32_t MEMLDOIBIASSEL : 1;        /*!< [25..25] Mem LDO Ibias select. Note: the SWE mux select in PWRSEQ2SWE
7318                                                      must be set for this to take effect.                                      */
7319       __IOM uint32_t TRIMANALDO : 4;            /*!< [29..26] Analog LDO Trim                                                  */
7320             uint32_t            : 2;
7321     } LDOREG2_b;
7322   } ;
7323   __IM  uint32_t  RESERVED5[30];
7324 
7325   union {
7326     __IOM uint32_t ADCPWRDLY;                   /*!< (@ 0x00000104) ADC Power Up Delay Control                                 */
7327 
7328     struct {
7329       __IOM uint32_t ADCPWR0    : 8;            /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK
7330                                                      increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments
7331                                                      for ADC_CLKSEL = 0x2.                                                     */
7332       __IOM uint32_t ADCPWR1    : 8;            /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments
7333                                                      for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL
7334                                                      = 0x2.                                                                    */
7335             uint32_t            : 16;
7336     } ADCPWRDLY_b;
7337   } ;
7338   __IM  uint32_t  RESERVED6;
7339 
7340   union {
7341     __IOM uint32_t ADCCAL;                      /*!< (@ 0x0000010C) ADC Calibration Control                                    */
7342 
7343     struct {
7344       __IOM uint32_t CALONPWRUP : 1;            /*!< [0..0] Run ADC Calibration on initial power up sequence                   */
7345       __IOM uint32_t ADCCALIBRATED : 1;         /*!< [1..1] Status for ADC Calibration                                         */
7346             uint32_t            : 30;
7347     } ADCCAL_b;
7348   } ;
7349 
7350   union {
7351     __IOM uint32_t ADCBATTLOAD;                 /*!< (@ 0x00000110) ADC Battery Load Enable                                    */
7352 
7353     struct {
7354       __IOM uint32_t BATTLOAD   : 1;            /*!< [0..0] Enable the ADC battery load resistor                               */
7355             uint32_t            : 31;
7356     } ADCBATTLOAD_b;
7357   } ;
7358   __IM  uint32_t  RESERVED7;
7359 
7360   union {
7361     __IOM uint32_t ADCTRIM;                     /*!< (@ 0x00000118) ADC Trims                                                  */
7362 
7363     struct {
7364       __IOM uint32_t ADCREFKEEPIBTRIM : 2;      /*!< [1..0] ADC Reference Ibias trim                                           */
7365             uint32_t            : 4;
7366       __IOM uint32_t ADCREFBUFTRIM : 5;         /*!< [10..6] ADC Reference buffer trim                                         */
7367       __IOM uint32_t ADCRFBUFIBTRIM : 2;        /*!< [12..11] ADC reference buffer input bias trim                             */
7368             uint32_t            : 19;
7369     } ADCTRIM_b;
7370   } ;
7371 
7372   union {
7373     __IOM uint32_t ADCREFCOMP;                  /*!< (@ 0x0000011C) ADC Reference Keeper and Comparator Control                */
7374 
7375     struct {
7376       __IOM uint32_t ADC_REFCOMP_OUT : 1;       /*!< [0..0] Output of the ADC reference comparator                             */
7377             uint32_t            : 7;
7378       __IOM uint32_t ADCREFKEEPTRIM : 5;        /*!< [12..8] ADC Reference Keeper Trim                                         */
7379             uint32_t            : 3;
7380       __IOM uint32_t ADCRFCMPEN : 1;            /*!< [16..16] ADC Reference comparator power down                              */
7381             uint32_t            : 15;
7382     } ADCREFCOMP_b;
7383   } ;
7384 
7385   union {
7386     __IOM uint32_t XTALCTRL;                    /*!< (@ 0x00000120) XTAL Oscillator Control                                    */
7387 
7388     struct {
7389       __IOM uint32_t XTALSWE    : 1;            /*!< [0..0] XTAL Software Override Enable.                                     */
7390       __IOM uint32_t FDBKDSBLXTAL : 1;          /*!< [1..1] XTAL Oscillator Disable Feedback.                                  */
7391       __IOM uint32_t BYPCMPRXTAL : 1;           /*!< [2..2] XTAL Oscillator Bypass Comparator.                                 */
7392       __IOM uint32_t PDNBCOREXTAL : 1;          /*!< [3..3] XTAL Oscillator Power Down Core.                                   */
7393       __IOM uint32_t PDNBCMPRXTAL : 1;          /*!< [4..4] XTAL Oscillator Power Down Comparator.                             */
7394       __IOM uint32_t PWDBODXTAL : 1;            /*!< [5..5] XTAL Power down on brown out.                                      */
7395       __IOM uint32_t XTALIBUFTRIM : 2;          /*!< [7..6] XTAL IBUFF trim                                                    */
7396       __IOM uint32_t XTALICOMPTRIM : 2;         /*!< [9..8] XTAL ICOMP trim                                                    */
7397             uint32_t            : 22;
7398     } XTALCTRL_b;
7399   } ;
7400 
7401   union {
7402     __IOM uint32_t XTALGENCTRL;                 /*!< (@ 0x00000124) XTAL Oscillator General Control                            */
7403 
7404     struct {
7405       __IOM uint32_t ACWARMUP   : 2;            /*!< [1..0] Auto-calibration delay control                                     */
7406       __IOM uint32_t XTALBIASTRIM : 6;          /*!< [7..2] XTAL BIAS trim                                                     */
7407       __IOM uint32_t XTALKSBIASTRIM : 6;        /*!< [13..8] XTAL IBIAS Kick start trim. This trim value is used
7408                                                      during the startup process to enable a faster lock.                       */
7409             uint32_t            : 18;
7410     } XTALGENCTRL_b;
7411   } ;
7412   __IM  uint32_t  RESERVED8[22];
7413 
7414   union {
7415     __IOM uint32_t MISCPWRCTRL;                 /*!< (@ 0x00000180) MISC power control override                                */
7416 
7417     struct {
7418             uint32_t            : 12;
7419       __IOM uint32_t PWRSWVDDLHBURSTEN : 1;     /*!< [12..12] override for pwrsw_vddlh_burst_en                                */
7420       __IOM uint32_t VDDLHBURSTOVER : 1;        /*!< [13..13] pwrsw_vddlh_burst_en override control                            */
7421       __IOM uint32_t PWRSWVDDRACTIVEEN : 1;     /*!< [14..14] override for pwrsw_vddr_active_en                                */
7422       __IOM uint32_t VDDRACTIVEOVER : 1;        /*!< [15..15] pwrsw_vddr_active_en override control                            */
7423       __IOM uint32_t PWRSWVDDRBURSTEN : 1;      /*!< [16..16] override for pwrsw_vddr_burst_en                                 */
7424       __IOM uint32_t VDDRBURSTOVER : 1;         /*!< [17..17] pwrsw_vddr_burst_en override control                             */
7425             uint32_t            : 14;
7426     } MISCPWRCTRL_b;
7427   } ;
7428   __IM  uint32_t  RESERVED9[5];
7429 
7430   union {
7431     __IOM uint32_t MISCCTRL;                    /*!< (@ 0x00000198) Miscellaneous control register.                            */
7432 
7433     struct {
7434             uint32_t            : 5;
7435       __IOM uint32_t BLE_RESETN : 1;            /*!< [5..5] BLE reset signal.                                                  */
7436             uint32_t            : 26;
7437     } MISCCTRL_b;
7438   } ;
7439   __IM  uint32_t  RESERVED10;
7440 
7441   union {
7442     __IOM uint32_t BOOTLOADER;                  /*!< (@ 0x000001A0) Bootloader and secure boot functions                       */
7443 
7444     struct {
7445       __IOM uint32_t BOOTLOADERLOW : 1;         /*!< [0..0] Determines whether the bootloader code is visible at
7446                                                      address 0x00000000 or not. Resets to 1, write 1 to clear.                 */
7447       __IOM uint32_t SBLOCK     : 1;            /*!< [1..1] Secure boot lock. Always resets to 1, write 1 to clear.
7448                                                      Enables system visibility to bootloader until set.                        */
7449       __IOM uint32_t PROTLOCK   : 1;            /*!< [2..2] Flash protection lock. Always resets to 1, write 1 to
7450                                                      clear. Enables writes to flash protection register set.                   */
7451             uint32_t            : 23;
7452       __IOM uint32_t SECBOOTFEATURE : 2;        /*!< [27..26] Indicates whether the secure boot feature is enabled.            */
7453       __IOM uint32_t SECBOOT    : 2;            /*!< [29..28] Indicates whether the secure boot on cold reset is
7454                                                      enabled                                                                   */
7455       __IOM uint32_t SECBOOTONRST : 2;          /*!< [31..30] Indicates whether the secure boot on warm reset is
7456                                                      enabled                                                                   */
7457     } BOOTLOADER_b;
7458   } ;
7459 
7460   union {
7461     __IOM uint32_t SHADOWVALID;                 /*!< (@ 0x000001A4) Register to indicate whether the shadow registers
7462                                                                     have been successfully loaded from the Flash
7463                                                                     Information Space.                                         */
7464 
7465     struct {
7466       __IOM uint32_t VALID      : 1;            /*!< [0..0] Indicates whether the shadow registers contain valid
7467                                                      data from the Flash Information Space.                                    */
7468       __IOM uint32_t BLDSLEEP   : 1;            /*!< [1..1] Indicates whether the bootloader should sleep or deep
7469                                                      sleep if no image loaded.                                                 */
7470       __IOM uint32_t INFO0_VALID : 1;           /*!< [2..2] Indicates whether INFO0 contains valid data                        */
7471             uint32_t            : 29;
7472     } SHADOWVALID_b;
7473   } ;
7474   __IM  uint32_t  RESERVED11[2];
7475 
7476   union {
7477     __IOM uint32_t SCRATCH0;                    /*!< (@ 0x000001B0) Scratch register that is not reset by any reset            */
7478 
7479     struct {
7480       __IOM uint32_t SCRATCH0   : 32;           /*!< [31..0] Scratch register 0.                                               */
7481     } SCRATCH0_b;
7482   } ;
7483 
7484   union {
7485     __IOM uint32_t SCRATCH1;                    /*!< (@ 0x000001B4) Scratch register that is not reset by any reset            */
7486 
7487     struct {
7488       __IOM uint32_t SCRATCH1   : 32;           /*!< [31..0] Scratch register 1.                                               */
7489     } SCRATCH1_b;
7490   } ;
7491   __IM  uint32_t  RESERVED12[2];
7492 
7493   union {
7494     __IOM uint32_t ICODEFAULTADDR;              /*!< (@ 0x000001C0) ICODE bus address which was present when a bus
7495                                                                     fault occurred.                                            */
7496 
7497     struct {
7498       __IOM uint32_t ICODEFAULTADDR : 32;       /*!< [31..0] The ICODE bus address observed when a Bus Fault occurred.
7499                                                      Once an address is captured in this field, it is held until
7500                                                      the corresponding Fault Observed bit is cleared in the
7501                                                      FAULTSTATUS register.                                                     */
7502     } ICODEFAULTADDR_b;
7503   } ;
7504 
7505   union {
7506     __IOM uint32_t DCODEFAULTADDR;              /*!< (@ 0x000001C4) DCODE bus address which was present when a bus
7507                                                                     fault occurred.                                            */
7508 
7509     struct {
7510       __IOM uint32_t DCODEFAULTADDR : 32;       /*!< [31..0] The DCODE bus address observed when a Bus Fault occurred.
7511                                                      Once an address is captured in this field, it is held until
7512                                                      the corresponding Fault Observed bit is cleared in the
7513                                                      FAULTSTATUS register.                                                     */
7514     } DCODEFAULTADDR_b;
7515   } ;
7516 
7517   union {
7518     __IOM uint32_t SYSFAULTADDR;                /*!< (@ 0x000001C8) System bus address which was present when a bus
7519                                                                     fault occurred.                                            */
7520 
7521     struct {
7522       __IOM uint32_t SYSFAULTADDR : 32;         /*!< [31..0] SYS bus address observed when a Bus Fault occurred.
7523                                                      Once an address is captured in this field, it is held until
7524                                                      the corresponding Fault Observed bit is cleared in the
7525                                                      FAULTSTATUS register.                                                     */
7526     } SYSFAULTADDR_b;
7527   } ;
7528 
7529   union {
7530     __IOM uint32_t FAULTSTATUS;                 /*!< (@ 0x000001CC) Reflects the status of the bus decoders' fault
7531                                                                     detection. Any write to this register will
7532                                                                     clear all of the status bits within the
7533                                                                     register.                                                  */
7534 
7535     struct {
7536       __IOM uint32_t ICODEFAULT : 1;            /*!< [0..0] The ICODE Bus Decoder Fault Detected bit. When set, a
7537                                                      fault has been detected, and the ICODEFAULTADDR register
7538                                                      will contain the bus address which generated the fault.                   */
7539       __IOM uint32_t DCODEFAULT : 1;            /*!< [1..1] DCODE Bus Decoder Fault Detected bit. When set, a fault
7540                                                      has been detected, and the DCODEFAULTADDR register will
7541                                                      contain the bus address which generated the fault.                        */
7542       __IOM uint32_t SYSFAULT   : 1;            /*!< [2..2] SYS Bus Decoder Fault Detected bit. When set, a fault
7543                                                      has been detected, and the SYSFAULTADDR register will contain
7544                                                      the bus address which generated the fault.                                */
7545             uint32_t            : 29;
7546     } FAULTSTATUS_b;
7547   } ;
7548 
7549   union {
7550     __IOM uint32_t FAULTCAPTUREEN;              /*!< (@ 0x000001D0) Enable the fault capture registers                         */
7551 
7552     struct {
7553       __IOM uint32_t FAULTCAPTUREEN : 1;        /*!< [0..0] Fault Capture Enable field. When set, the Fault Capture
7554                                                      monitors are enabled and addresses which generate a hard
7555                                                      fault are captured into the FAULTADDR registers.                          */
7556             uint32_t            : 31;
7557     } FAULTCAPTUREEN_b;
7558   } ;
7559   __IM  uint32_t  RESERVED13[11];
7560 
7561   union {
7562     __IOM uint32_t DBGR1;                       /*!< (@ 0x00000200) Read-only debug register 1                                 */
7563 
7564     struct {
7565       __IOM uint32_t ONETO8     : 32;           /*!< [31..0] Read-only register for communication validation                   */
7566     } DBGR1_b;
7567   } ;
7568 
7569   union {
7570     __IOM uint32_t DBGR2;                       /*!< (@ 0x00000204) Read-only debug register 2                                 */
7571 
7572     struct {
7573       __IOM uint32_t COOLCODE   : 32;           /*!< [31..0] Read-only register for communication validation                   */
7574     } DBGR2_b;
7575   } ;
7576   __IM  uint32_t  RESERVED14[6];
7577 
7578   union {
7579     __IOM uint32_t PMUENABLE;                   /*!< (@ 0x00000220) Control bit to enable/disable the PMU                      */
7580 
7581     struct {
7582       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] PMU Enable Control bit. When set, the MCU's PMU will
7583                                                      place the MCU into the lowest power consuming Deep Sleep
7584                                                      mode upon execution of a WFI instruction (dependent on
7585                                                      the setting of the SLEEPDEEP bit in the ARM SCR register).
7586                                                      When cleared, regardless of the requested sleep mode, the
7587                                                      PMU will not enter the lowest power Deep Sleep mode, instead
7588                                                      entering the Sleep mode.                                                  */
7589             uint32_t            : 31;
7590     } PMUENABLE_b;
7591   } ;
7592   __IM  uint32_t  RESERVED15[11];
7593 
7594   union {
7595     __IOM uint32_t TPIUCTRL;                    /*!< (@ 0x00000250) TPIU Control Register. Determines the clock enable
7596                                                                     and frequency for the M4's TPIU interface.                 */
7597 
7598     struct {
7599       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] TPIU Enable field. When set, the ARM M4 TPIU is enabled
7600                                                      and data can be streamed out of the MCU's SWO port using
7601                                                      the ARM ITM and TPIU modules.                                             */
7602             uint32_t            : 7;
7603       __IOM uint32_t CLKSEL     : 3;            /*!< [10..8] This field selects the frequency of the ARM M4 TPIU
7604                                                      port.                                                                     */
7605             uint32_t            : 21;
7606     } TPIUCTRL_b;
7607   } ;
7608   __IM  uint32_t  RESERVED16[4];
7609 
7610   union {
7611     __IOM uint32_t OTAPOINTER;                  /*!< (@ 0x00000264) OTA (Over the Air) Update Pointer/Status. Reset
7612                                                                     only by POA                                                */
7613 
7614     struct {
7615       __IOM uint32_t OTAVALID   : 1;            /*!< [0..0] Indicates that an OTA update is valid                              */
7616       __IOM uint32_t OTASBLUPDATE : 1;          /*!< [1..1] Indicates that the sbl_init has been updated                       */
7617       __IOM uint32_t OTAPOINTER : 30;           /*!< [31..2] Flash page pointer with updated OTA image                         */
7618     } OTAPOINTER_b;
7619   } ;
7620   __IM  uint32_t  RESERVED17[7];
7621 
7622   union {
7623     __IOM uint32_t SRAMMODE;                    /*!< (@ 0x00000284) SRAM Controller mode bits                                  */
7624 
7625     struct {
7626       __IOM uint32_t IPREFETCH  : 1;            /*!< [0..0] When set, instruction accesses to the SRAM banks will
7627                                                      be pre-fetched (normally 2 cycle read access). Generally,
7628                                                      this mode bit should be set for improved performance when
7629                                                      executing instructions from SRAM.                                         */
7630       __IOM uint32_t IPREFETCH_CACHE : 1;       /*!< [1..1] Secondary pre-fetch feature that will cache pre-fetched
7631                                                      data across bus wait states (requires IPREFETCH to be set).               */
7632             uint32_t            : 2;
7633       __IOM uint32_t DPREFETCH  : 1;            /*!< [4..4] When set, data bus accesses to the SRAM banks will be
7634                                                      pre-fetched (normally 2 cycle read access). Use of this
7635                                                      mode bit is only recommended if the work flow has a large
7636                                                      number of sequential accesses.                                            */
7637       __IOM uint32_t DPREFETCH_CACHE : 1;       /*!< [5..5] Secondary pre-fetch feature that will cache pre-fetched
7638                                                      data across bus wait states (requires DPREFETCH to be set).               */
7639             uint32_t            : 26;
7640     } SRAMMODE_b;
7641   } ;
7642   __IM  uint32_t  RESERVED18[48];
7643 
7644   union {
7645     __IOM uint32_t KEXTCLKSEL;                  /*!< (@ 0x00000348) Locks the state of the EXTCLKSEL register from
7646                                                                     writes. This is done to prevent errant writes
7647                                                                     to the register, as this could cause the
7648                                                                     chip to halt. Write a value of 0x53 to unlock
7649                                                                     write access to the EXTCLKSEL register.
7650                                                                     Once unlocked, the register will read back
7651                                                                     a 1 to indicate this is unlocked. Writing
7652                                                                     the register with any other value other
7653                                                                     than 0x53 will enable the lock.                            */
7654 
7655     struct {
7656       __IOM uint32_t KEXTCLKSEL : 32;           /*!< [31..0] Key register value.                                               */
7657     } KEXTCLKSEL_b;
7658   } ;
7659   __IM  uint32_t  RESERVED19;
7660 
7661   union {
7662     __IOM uint32_t SIMOBUCK1;                   /*!< (@ 0x00000350) SIMO Buck Control Reg 1                                    */
7663 
7664     struct {
7665       __IOM uint32_t COREACTIVETRIM : 10;       /*!< [9..0] simobuck_core_active_trim (VDDF)                                   */
7666       __IOM uint32_t SIMOBUCKCORELPTRIM : 6;    /*!< [15..10] simobuck_core_lp_trim                                            */
7667       __IOM uint32_t MEMACTIVETRIM : 6;         /*!< [21..16] simobuck_mem_active_trim (VDDC)                                  */
7668       __IOM uint32_t SIMOBUCKMEMLPTRIM : 6;     /*!< [27..22] simobuck_mem_lp_trim                                             */
7669       __IOM uint32_t CORETEMPCOTRIM : 4;        /*!< [31..28] simobuck_core_tempco_trim                                        */
7670     } SIMOBUCK1_b;
7671   } ;
7672 
7673   union {
7674     __IOM uint32_t SIMOBUCK2;                   /*!< (@ 0x00000354) SIMO Buck Control Reg 2                                    */
7675 
7676     struct {
7677       __IOM uint32_t SIMOBUCKTONGENTRIM : 5;    /*!< [4..0] simobuck_tongen_trim                                               */
7678             uint32_t            : 11;
7679       __IOM uint32_t SIMOBUCKCORELPHIGHTONTRIM : 4;/*!< [19..16] simobuck_core_lp_high_ton_trim                                */
7680       __IOM uint32_t SIMOBUCKCORELPLOWTONTRIM : 4;/*!< [23..20] simobuck_core_lp_low_ton_trim                                  */
7681             uint32_t            : 4;
7682       __IOM uint32_t SIMOBUCKCORELEAKAGETRIM : 2;/*!< [29..28] simobuck_core_leakage_trim                                      */
7683             uint32_t            : 2;
7684     } SIMOBUCK2_b;
7685   } ;
7686 
7687   union {
7688     __IOM uint32_t SIMOBUCK3;                   /*!< (@ 0x00000358) SIMO Buck Control Reg 3                                    */
7689 
7690     struct {
7691       __IOM uint32_t SIMOBUCKCORELPHIGHTOFFTRIM : 4;/*!< [3..0] simobuck_core_lp_high_toff_trim                                */
7692       __IOM uint32_t SIMOBUCKCORELPLOWTOFFTRIM : 4;/*!< [7..4] simobuck_core_lp_low_toff_trim                                  */
7693       __IOM uint32_t SIMOBUCKMEMLPHIGHTOFFTRIM : 4;/*!< [11..8] simobuck_mem_lp_high_toff_trim                                 */
7694       __IOM uint32_t SIMOBUCKMEMLPLOWTOFFTRIM : 4;/*!< [15..12] simobuck_mem_lp_low_toff_trim                                  */
7695             uint32_t            : 11;
7696       __IOM uint32_t SIMOBUCKMEMLPHIGHTONTRIM : 4;/*!< [30..27] simobuck_mem_lp_high_ton_trim                                  */
7697             uint32_t            : 1;
7698     } SIMOBUCK3_b;
7699   } ;
7700 
7701   union {
7702     __IOM uint32_t SIMOBUCK4;                   /*!< (@ 0x0000035C) SIMO Buck Control Reg 4                                    */
7703 
7704     struct {
7705       __IOM uint32_t SIMOBUCKMEMLPLOWTONTRIM : 4;/*!< [3..0] simobuck_mem_lp_low_ton_trim                                      */
7706             uint32_t            : 17;
7707       __IOM uint32_t SIMOBUCKCLKDIVSEL : 2;     /*!< [22..21] simobuck_clkdiv_sel                                              */
7708       __IOM uint32_t SIMOBUCKCOMP2LPEN : 1;     /*!< [23..23] simobuck_comp2_lp_en                                             */
7709       __IOM uint32_t SIMOBUCKCOMP2TIMEOUTEN : 1;/*!< [24..24] simobuck_comp2_timeout_en                                        */
7710             uint32_t            : 7;
7711     } SIMOBUCK4_b;
7712   } ;
7713   __IM  uint32_t  RESERVED20;
7714 
7715   union {
7716     __IOM uint32_t BLEBUCK1;                    /*!< (@ 0x00000364) BLEBUCK1 Control Reg                                       */
7717 
7718     struct {
7719             uint32_t            : 15;
7720       __IOM uint32_t BLEBUCKPULLUPTRIM : 4;     /*!< [18..15] blebuck_pullup_trim                                              */
7721             uint32_t            : 13;
7722     } BLEBUCK1_b;
7723   } ;
7724 
7725   union {
7726     __IOM uint32_t BLEBUCK2;                    /*!< (@ 0x00000368) BLEBUCK2 Control Reg                                       */
7727 
7728     struct {
7729       __IOM uint32_t BLEBUCKTONLOWTRIM : 6;     /*!< [5..0] blebuck_ton_low_trim                                               */
7730       __IOM uint32_t BLEBUCKTONHITRIM : 6;      /*!< [11..6] blebuck_ton_hi_trim                                               */
7731       __IOM uint32_t BLEBUCKTOND2ATRIM : 6;     /*!< [17..12] blebuck_ton_trim                                                 */
7732             uint32_t            : 14;
7733     } BLEBUCK2_b;
7734   } ;
7735   __IM  uint32_t  RESERVED21[13];
7736 
7737   union {
7738     __IOM uint32_t FLASHWPROT0;                 /*!< (@ 0x000003A0) These bits write-protect flash in 16KB chunks.             */
7739 
7740     struct {
7741       __IOM uint32_t FW0BITS    : 32;           /*!< [31..0] Write protect flash 0x00000000 - 0x0007FFFF. Each bit
7742                                                      provides write protection for 16KB chunks of flash data
7743                                                      space. Bits are cleared by writing a 1 to the bit. When
7744                                                      read, 0 indicates the region is protected. Bits are sticky
7745                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
7746     } FLASHWPROT0_b;
7747   } ;
7748 
7749   union {
7750     __IOM uint32_t FLASHWPROT1;                 /*!< (@ 0x000003A4) These bits write-protect flash in 16KB chunks.             */
7751 
7752     struct {
7753       __IOM uint32_t FW1BITS    : 32;           /*!< [31..0] Write protect flash 0x00080000 - 0x000FFFFF. Each bit
7754                                                      provides write protection for 16KB chunks of flash data
7755                                                      space. Bits are cleared by writing a 1 to the bit. When
7756                                                      read, 0 indicates the region is protected. Bits are sticky
7757                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
7758     } FLASHWPROT1_b;
7759   } ;
7760 
7761   union {
7762     __IOM uint32_t FLASHWPROT2;                 /*!< (@ 0x000003A8) These bits write-protect flash in 16KB chunks.             */
7763 
7764     struct {
7765       __IOM uint32_t FW2BITS    : 32;           /*!< [31..0] Write protect flash 0x00100000 - 0x0017FFFF. Each bit
7766                                                      provides write protection for 16KB chunks of flash data
7767                                                      space. Bits are cleared by writing a 1 to the bit. When
7768                                                      read, 0 indicates the region is protected. Bits are sticky
7769                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
7770     } FLASHWPROT2_b;
7771   } ;
7772 
7773   union {
7774     __IOM uint32_t FLASHWPROT3;                 /*!< (@ 0x000003AC) These bits write-protect flash in 16KB chunks.             */
7775 
7776     struct {
7777       __IOM uint32_t FW3BITS    : 32;           /*!< [31..0] Write protect flash 0x00180000 - 0x001FFFFF. Each bit
7778                                                      provides write protection for 16KB chunks of flash data
7779                                                      space. Bits are cleared by writing a 1 to the bit. When
7780                                                      read, 0 indicates the region is protected. Bits are sticky
7781                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
7782     } FLASHWPROT3_b;
7783   } ;
7784 
7785   union {
7786     __IOM uint32_t FLASHRPROT0;                 /*!< (@ 0x000003B0) These bits read-protect flash in 16KB chunks.              */
7787 
7788     struct {
7789       __IOM uint32_t FR0BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each
7790                                                      bit provides read protection for 16KB chunks of flash.
7791                                                      Bits are cleared by writing a 1 to the bit. When read,
7792                                                      0 indicates the region is protected. Bits are sticky (can
7793                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
7794     } FLASHRPROT0_b;
7795   } ;
7796 
7797   union {
7798     __IOM uint32_t FLASHRPROT1;                 /*!< (@ 0x000003B4) These bits read-protect flash in 16KB chunks.              */
7799 
7800     struct {
7801       __IOM uint32_t FR1BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each
7802                                                      bit provides read protection for 16KB chunks of flash.
7803                                                      Bits are cleared by writing a 1 to the bit. When read,
7804                                                      0 indicates the region is protected. Bits are sticky (can
7805                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
7806     } FLASHRPROT1_b;
7807   } ;
7808 
7809   union {
7810     __IOM uint32_t FLASHRPROT2;                 /*!< (@ 0x000003B8) These bits read-protect flash in 16KB chunks.              */
7811 
7812     struct {
7813       __IOM uint32_t FR2BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00100000 - 0x0017FFFF. Each
7814                                                      bit provides read protection for 16KB chunks of flash.
7815                                                      Bits are cleared by writing a 1 to the bit. When read,
7816                                                      0 indicates the region is protected. Bits are sticky (can
7817                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
7818     } FLASHRPROT2_b;
7819   } ;
7820 
7821   union {
7822     __IOM uint32_t FLASHRPROT3;                 /*!< (@ 0x000003BC) These bits read-protect flash in 16KB chunks.              */
7823 
7824     struct {
7825       __IOM uint32_t FR3BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00180000 - 0x001FFFFF. Each
7826                                                      bit provides read protection for 16KB chunks of flash.
7827                                                      Bits are cleared by writing a 1 to the bit. When read,
7828                                                      0 indicates the region is protected. Bits are sticky (can
7829                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
7830     } FLASHRPROT3_b;
7831   } ;
7832 
7833   union {
7834     __IOM uint32_t DMASRAMWRITEPROTECT0;        /*!< (@ 0x000003C0) These bits write-protect system SRAM from DMA
7835                                                                     operations in 8KB chunks.                                  */
7836 
7837     struct {
7838       __IOM uint32_t DMA_WPROT0 : 32;           /*!< [31..0] Write protect SRAM from DMA. Each bit provides write
7839                                                      protection for an 8KB region of memory. When set to 1,
7840                                                      the region will be protected from DMA writes, when set
7841                                                      to 0, DMA may write the region.                                           */
7842     } DMASRAMWRITEPROTECT0_b;
7843   } ;
7844 
7845   union {
7846     __IOM uint32_t DMASRAMWRITEPROTECT1;        /*!< (@ 0x000003C4) These bits write-protect system SRAM from DMA
7847                                                                     operations in 8KB chunks.                                  */
7848 
7849     struct {
7850       __IOM uint32_t DMA_WPROT1 : 32;           /*!< [31..0] Write protect SRAM from DMA. Each bit provides write
7851                                                      protection for an 8KB region of memory. When set to 1,
7852                                                      the region will be protected from DMA writes, when set
7853                                                      to 0, DMA may write the region.                                           */
7854     } DMASRAMWRITEPROTECT1_b;
7855   } ;
7856   __IM  uint32_t  RESERVED22[2];
7857 
7858   union {
7859     __IOM uint32_t DMASRAMREADPROTECT0;         /*!< (@ 0x000003D0) These bits read-protect system SRAM from DMA
7860                                                                     operations in 8KB chunks.                                  */
7861 
7862     struct {
7863       __IOM uint32_t DMA_RPROT0 : 32;           /*!< [31..0] Read protect SRAM from DMA. Each bit provides write
7864                                                      protection for an 8KB region of memory. When set to 1,
7865                                                      the region will be protected from DMA reads, when set to
7866                                                      0, DMA may read the region.                                               */
7867     } DMASRAMREADPROTECT0_b;
7868   } ;
7869 
7870   union {
7871     __IOM uint32_t DMASRAMREADPROTECT1;         /*!< (@ 0x000003D4) These bits read-protect system SRAM from DMA
7872                                                                     operations in 8KB chunks.                                  */
7873 
7874     struct {
7875       __IOM uint32_t DMA_RPROT1 : 32;           /*!< [31..0] Read protect SRAM from DMA. Each bit provides write
7876                                                      protection for an 8KB region of memory. When set to 1,
7877                                                      the region will be protected from DMA reads, when set to
7878                                                      0, DMA may read the region.                                               */
7879     } DMASRAMREADPROTECT1_b;
7880   } ;
7881 
7882   union {
7883     __IOM uint32_t DMASRAMREADPROTECT2;         /*!< (@ 0x000003D8) These bits read-protect system SRAM from DMA
7884                                                                     operations in 8KB chunks.                                  */
7885 
7886     struct {
7887       __IOM uint32_t DMA_RPROT2 : 32;           /*!< [31..0] Read protect SRAM from DMA. Each bit provides write
7888                                                      protection for an 8KB region of memory. When set to 1,
7889                                                      the region will be protected from DMA reads, when set to
7890                                                      0, DMA may read the region.                                               */
7891     } DMASRAMREADPROTECT2_b;
7892   } ;
7893 } MCUCTRL_Type;                                 /*!< Size = 988 (0x3dc)                                                        */
7894 
7895 
7896 
7897 /* =========================================================================================================================== */
7898 /* ================                                           MSPI0                                           ================ */
7899 /* =========================================================================================================================== */
7900 
7901 
7902 /**
7903   * @brief Multi-bit SPI Master (MSPI0)
7904   */
7905 
7906 typedef struct {                                /*!< (@ 0x50014000) MSPI0 Structure                                            */
7907 
7908   union {
7909     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) This register is used to enable individual PIO
7910                                                                     based transactions to a device on the bus.
7911                                                                     The CFG register must be programmed properly
7912                                                                     for the transfer, and the ADDR and INSTR
7913                                                                     registers should be programmed if the SENDI
7914                                                                     and SENDA fields are enabled.                              */
7915 
7916     struct {
7917       __IOM uint32_t START      : 1;            /*!< [0..0] Write to 1 to initiate a PIO transaction on the bus (typically
7918                                                      the entire register should be written at once with this
7919                                                      bit set).                                                                 */
7920       __IOM uint32_t STATUS     : 1;            /*!< [1..1] Command status: 1 indicates command has completed. Cleared
7921                                                      by writing 1 to this bit or starting a new transfer.                      */
7922       __IOM uint32_t BUSY       : 1;            /*!< [2..2] Command status: 1 indicates controller is busy (command
7923                                                      in progress)                                                              */
7924       __IOM uint32_t QUADCMD    : 1;            /*!< [3..3] Flag indicating that the operation is a command that
7925                                                      should be replicated to both devices in paired QUAD mode.
7926                                                      This is typically only used when reading/writing configuration
7927                                                      registers in paired flash devices (do not set for memory
7928                                                      transfers).                                                               */
7929       __IOM uint32_t ENWLAT     : 1;            /*!< [4..4] Enable Write Latency Counter (time between address and
7930                                                      first data byte). Counter value is WRITELATENCY.                          */
7931       __IOM uint32_t CONT       : 1;            /*!< [5..5] Continuation transfer. When 1, indicates that the MSPI
7932                                                      will hold CE low after the transaction completes. This
7933                                                      is included for compatibility with IOM module since the
7934                                                      MSPI transfer module can handle most cases in a single
7935                                                      transfer. NOTE: CONT functionality only works with CLKDIV=2
7936                                                      (24 MHz).                                                                 */
7937       __IOM uint32_t BIGENDIAN  : 1;            /*!< [6..6] 1 indicates data in FIFO is in big endian format (MSB
7938                                                      first); 0 indicates little endian data (default, LSB first).              */
7939       __IOM uint32_t ENTURN     : 1;            /*!< [7..7] Indicates whether TX->RX turnaround cycles should be
7940                                                      enabled for this operation (see TURNAROUND field in CFG
7941                                                      register).                                                                */
7942       __IOM uint32_t SENDA      : 1;            /*!< [8..8] Indicates whether an address phase should be sent (see
7943                                                      ADDR register and ASIZE field in CFG register)                            */
7944       __IOM uint32_t SENDI      : 1;            /*!< [9..9] Indicates whether an instruction phase should be sent
7945                                                      (see INSTR field and ISIZE field in CFG register)                         */
7946       __IOM uint32_t TXRX       : 1;            /*!< [10..10] 1 Indicates a TX operation, 0 indicates an RX operation
7947                                                      of XFERBYTES                                                              */
7948       __IOM uint32_t PIOSCRAMBLE : 1;           /*!< [11..11] Enables data scrambling for PIO operations. This should
7949                                                      only be used for data operations and never for commands
7950                                                      to a device.                                                              */
7951       __IOM uint32_t ENDCX      : 1;            /*!< [12..12] Enable DCX signal on data [1]                                    */
7952             uint32_t            : 3;
7953       __IOM uint32_t XFERBYTES  : 16;           /*!< [31..16] Number of bytes to transmit or receive (based on TXRX
7954                                                      bit)                                                                      */
7955     } CTRL_b;
7956   } ;
7957 
7958   union {
7959     __IOM uint32_t CFG;                         /*!< (@ 0x00000004) Command formatting for PIO based transactions
7960                                                                     (initiated by writes to CTRL register)                     */
7961 
7962     struct {
7963       __IOM uint32_t DEVCFG     : 4;            /*!< [3..0] Flash configuration for XIP and AUTO DMA operations.
7964                                                      Controls value for SER (Slave Enable) for XIP operations
7965                                                      and address generation for DMA/XIP modes. Also used to
7966                                                      configure SPIFRF (frame format).                                          */
7967       __IOM uint32_t ASIZE      : 2;            /*!< [5..4] Address Size. Address bytes to send from ADDR register             */
7968       __IOM uint32_t ISIZE      : 1;            /*!< [6..6] Instruction Sizeenum name = I8 value = 0x0 desc = Instruction
7969                                                      is 1 byteenum name = I16 value = 0x1 desc = Instruction
7970                                                      is 2 bytes                                                                */
7971       __IOM uint32_t SEPIO      : 1;            /*!< [7..7] Separate IO configuration. This bit should be set when
7972                                                      the target device has separate MOSI and MISO pins. Respective
7973                                                      IN/OUT bits below should be set to map pins.                              */
7974       __IOM uint32_t TURNAROUND : 6;            /*!< [13..8] Number of turnaround cycles (for TX->RX transitions).
7975                                                      Qualified by ENTURN or XIPENTURN bit field.                               */
7976             uint32_t            : 2;
7977       __IOM uint32_t CPHA       : 1;            /*!< [16..16] Serial clock phase.                                              */
7978       __IOM uint32_t CPOL       : 1;            /*!< [17..17] Serial clock polarity.                                           */
7979             uint32_t            : 2;
7980       __IOM uint32_t WRITELATENCY : 6;          /*!< [25..20] Number of cycles between addressn and TX data. Qualified
7981                                                      by ENLAT                                                                  */
7982             uint32_t            : 6;
7983     } CFG_b;
7984   } ;
7985 
7986   union {
7987     __IOM uint32_t ADDR;                        /*!< (@ 0x00000008) Optional Address field to send for PIO transfers           */
7988 
7989     struct {
7990       __IOM uint32_t ADDR       : 32;           /*!< [31..0] Optional Address field to send (after optional instruction
7991                                                      field) - qualified by ASIZE in CMD register. NOTE: This
7992                                                      register is aliased to DMADEVADDR.                                        */
7993     } ADDR_b;
7994   } ;
7995 
7996   union {
7997     __IOM uint32_t INSTR;                       /*!< (@ 0x0000000C) Optional Instruction field to send for PIO transfers       */
7998 
7999     struct {
8000       __IOM uint32_t INSTR      : 16;           /*!< [15..0] Optional Instruction field to send (1st byte) - qualified
8001                                                      by ISEND/ISIZE                                                            */
8002             uint32_t            : 16;
8003     } INSTR_b;
8004   } ;
8005 
8006   union {
8007     __IOM uint32_t TXFIFO;                      /*!< (@ 0x00000010) TX Data FIFO                                               */
8008 
8009     struct {
8010       __IOM uint32_t TXFIFO     : 32;           /*!< [31..0] Data to be transmitted. Data should normally be aligned
8011                                                      to the LSB (pad the upper bits with zeros) unless BIGENDIAN
8012                                                      is set.                                                                   */
8013     } TXFIFO_b;
8014   } ;
8015 
8016   union {
8017     __IOM uint32_t RXFIFO;                      /*!< (@ 0x00000014) RX Data FIFO                                               */
8018 
8019     struct {
8020       __IOM uint32_t RXFIFO     : 32;           /*!< [31..0] Receive data. Data is aligned to the LSB (padded zeros
8021                                                      on upper bits) unless BIGENDIAN is set.                                   */
8022     } RXFIFO_b;
8023   } ;
8024 
8025   union {
8026     __IOM uint32_t TXENTRIES;                   /*!< (@ 0x00000018) Number of words in TX FIFO                                 */
8027 
8028     struct {
8029       __IOM uint32_t TXENTRIES  : 6;            /*!< [5..0] Number of 32-bit words/entries in TX FIFO                          */
8030             uint32_t            : 26;
8031     } TXENTRIES_b;
8032   } ;
8033 
8034   union {
8035     __IOM uint32_t RXENTRIES;                   /*!< (@ 0x0000001C) Number of words in RX FIFO                                 */
8036 
8037     struct {
8038       __IOM uint32_t RXENTRIES  : 6;            /*!< [5..0] Number of 32-bit words/entries in RX FIFO                          */
8039             uint32_t            : 26;
8040     } RXENTRIES_b;
8041   } ;
8042 
8043   union {
8044     __IOM uint32_t THRESHOLD;                   /*!< (@ 0x00000020) Threshold levels that trigger RXFull and TXEmpty
8045                                                                     interrupts                                                 */
8046 
8047     struct {
8048       __IOM uint32_t TXTHRESH   : 6;            /*!< [5..0] Number of entries in TX FIFO that cause TXF interrupt              */
8049             uint32_t            : 2;
8050       __IOM uint32_t RXTHRESH   : 6;            /*!< [13..8] Number of entries in TX FIFO that cause RXE interrupt             */
8051             uint32_t            : 18;
8052     } THRESHOLD_b;
8053   } ;
8054   __IM  uint32_t  RESERVED[55];
8055 
8056   union {
8057     __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000100) Timing configuration bits for the MSPI module.
8058                                                                     PRSTN, IPRSTN, and FIFORESET can be used
8059                                                                     to reset portions of the MSPI interface
8060                                                                     in order to clear error conditions. The
8061                                                                     remaining bits control clock frequency and
8062                                                                     TX/RX capture timings.                                     */
8063 
8064     struct {
8065       __IOM uint32_t APBCLK     : 1;            /*!< [0..0] Enable continuous APB clock. For power-efficient operation,
8066                                                      APBCLK should be set to 0.                                                */
8067       __IOM uint32_t RXCAP      : 1;            /*!< [1..1] Controls RX data capture phase. A setting of 0 (NORMAL)
8068                                                      captures read data at the normal capture point relative
8069                                                      to the internal clock launch point. However, to accommodate
8070                                                      chip/pad/board delays, a setting of RXCAP of 1 is expected
8071                                                      to be used to align the capture point with the return data
8072                                                      window. This bit is used in conjunction with RXNEG to provide
8073                                                      4 unique capture points, all about 10 ns apart.                           */
8074       __IOM uint32_t RXNEG      : 1;            /*!< [2..2] Adjusts the RX capture phase to the negedge of the 48MHz
8075                                                      internal clock (~10 ns early). For normal operation, it
8076                                                      is expected that RXNEG will be set to 0.                                  */
8077       __IOM uint32_t TXNEG      : 1;            /*!< [3..3] Launches TX data a half clock cycle (~10 ns) early. This
8078                                                      should normally be programmed to zero (NORMAL).                           */
8079       __IOM uint32_t IOMSEL     : 4;            /*!< [7..4] Selects which IOM is selected for CQ handshake status.             */
8080       __IOM uint32_t CLKDIV     : 6;            /*!< [13..8] Clock Divider. Allows dividing 48 MHz base clock by
8081                                                      integer multiples. Enumerations are provided for common
8082                                                      frequency, but any integer divide from 48 MHz is allowed.
8083                                                      Odd divide ratios will result in a 33/66 percent duty cycle
8084                                                      with a long low clock pulse (to allow longer round-trip
8085                                                      for read data).                                                           */
8086             uint32_t            : 15;
8087       __IOM uint32_t FIFORESET  : 1;            /*!< [29..29] Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal
8088                                                      operation. May be used to manually flush the FIFO in error
8089                                                      handling.                                                                 */
8090       __IOM uint32_t IPRSTN     : 1;            /*!< [30..30] IP block reset. Write to 0 to put the transfer module
8091                                                      in reset or 1 for normal operation. This may be required
8092                                                      after error conditions to clear the transfer on the bus.                  */
8093       __IOM uint32_t PRSTN      : 1;            /*!< [31..31] Peripheral reset. Master reset to the entire MSPI module
8094                                                      (DMA, XIP, and transfer state machines). 1=normal operation,
8095                                                      0=in reset.                                                               */
8096     } MSPICFG_b;
8097   } ;
8098 
8099   union {
8100     __IOM uint32_t MSPIDDR;                     /*!< (@ 0x00000104) Timing configuration bits for DDR operation of
8101                                                                     the MSPI module.                                           */
8102 
8103     struct {
8104       __IOM uint32_t EMULATEDDR : 1;            /*!< [0..0] Drive external clock at 1/2 rate to emulate DDR mode               */
8105       __IOM uint32_t QUADDDR    : 1;            /*!< [1..1] Enables use of delay line to provide fine control over
8106                                                      traditional RX capture clock.                                             */
8107       __IOM uint32_t ENABLEDQS  : 1;            /*!< [2..2] In EMULATEDDR mode, enable DQS for read capture                    */
8108       __IOM uint32_t DQSSYNCNEG : 1;            /*!< [3..3] Use negative edge of clock for DDR data sync                       */
8109       __IOM uint32_t OVERRIDERXDQSDELAY : 1;    /*!< [4..4] Override DQS delay line with the value in DQSDELAY (for
8110                                                      RX capture in QUADDDR mode)                                               */
8111       __IOM uint32_t OVERRIDEDDRCLKOUTDELAY : 1;/*!< [5..5] Override TX delay line with the value in DQSDELAY (for
8112                                                      TX clock offset when in QUADDDR mode)                                     */
8113       __IOM uint32_t ENABLEFINEDELAY : 1;       /*!< [6..6] Enables use of delay line to provide fine control over
8114                                                      traditional RX capture clock.                                             */
8115             uint32_t            : 1;
8116       __IOM uint32_t RXDQSDELAY : 5;            /*!< [12..8] When OVERRIDEDQSDELAY is set this sets the DQS delay
8117                                                      line value. In ENABLEDQS mode, this acts as an offset to
8118                                                      the computed value (should be set to 0 by default)                        */
8119             uint32_t            : 3;
8120       __IOM uint32_t TXDQSDELAY : 5;            /*!< [20..16] When OVERRIDEDQSDELAY is set this sets the DQS delay
8121                                                      line value. In ENABLEDQS mode, this acts as an offset to
8122                                                      the computed value (should be set to 0 by default)                        */
8123             uint32_t            : 11;
8124     } MSPIDDR_b;
8125   } ;
8126   __IM  uint32_t  RESERVED1[2];
8127 
8128   union {
8129     __IOM uint32_t PADCFG;                      /*!< (@ 0x00000110) Configuration bits for the MSPI pads. Allows
8130                                                                     pads associated with the upper quad to be
8131                                                                     mapped to corresponding bits on the lower
8132                                                                     quad. Use of Quad0 pins is recommended for
8133                                                                     optimal timing.                                            */
8134 
8135     struct {
8136       __IOM uint32_t OUT3       : 1;            /*!< [0..0] Output pad 3 configuration. 0=data[3] 1=CLK                        */
8137       __IOM uint32_t OUT4       : 1;            /*!< [1..1] Output pad 4 configuration. 0=data[4] 1=data[0]                    */
8138       __IOM uint32_t OUT5       : 1;            /*!< [2..2] Output pad 5 configuration. 0=data[5] 1=data[1]                    */
8139       __IOM uint32_t OUT6       : 1;            /*!< [3..3] Output pad 6 configuration. 0=data[6] 1=data[2]                    */
8140       __IOM uint32_t OUT7       : 1;            /*!< [4..4] Output pad 7 configuration. 0=data[7] 1=data[3]                    */
8141             uint32_t            : 11;
8142       __IOM uint32_t IN0        : 2;            /*!< [17..16] Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1]
8143                                                      3=pad[5]                                                                  */
8144       __IOM uint32_t IN1        : 1;            /*!< [18..18] Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5]                   */
8145       __IOM uint32_t IN2        : 1;            /*!< [19..19] Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6]                   */
8146       __IOM uint32_t IN3        : 1;            /*!< [20..20] Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7]                   */
8147       __IOM uint32_t REVCS      : 1;            /*!< [21..21] Reverse CS connections. Allows CS1 to be associated
8148                                                      with lower data lanes and CS0 to be associated with upper
8149                                                      data lines                                                                */
8150             uint32_t            : 10;
8151     } PADCFG_b;
8152   } ;
8153 
8154   union {
8155     __IOM uint32_t PADOUTEN;                    /*!< (@ 0x00000114) Enable bits for the MSPI output pads. Each active
8156                                                                     MSPI line should be set to 1 in the OUTEN
8157                                                                     field below.                                               */
8158 
8159     struct {
8160       __IOM uint32_t OUTEN      : 10;           /*!< [9..0] Output pad enable configuration. Indicates which pads
8161                                                      should be driven. Bits [3:0] are Quad0 data, [7:4] are
8162                                                      Quad1 data, and [8] is clock.                                             */
8163             uint32_t            : 22;
8164     } PADOUTEN_b;
8165   } ;
8166 
8167   union {
8168     __IOM uint32_t PADOVEREN;                   /*!< (@ 0x00000118) Enables PIO-like pad override control                      */
8169 
8170     struct {
8171       __IOM uint32_t OVERRIDEEN : 10;           /*!< [9..0] Output pad override enable. Bit mask for pad outputs.
8172                                                      When set to 1, the values in the OVERRIDE field are driven
8173                                                      on the pad (output enable is implicitly set in this mode).
8174                                                      [7:0]=data [8]=clock [9]=DM                                               */
8175             uint32_t            : 22;
8176     } PADOVEREN_b;
8177   } ;
8178 
8179   union {
8180     __IOM uint32_t PADOVER;                     /*!< (@ 0x0000011C) Override data value                                        */
8181 
8182     struct {
8183       __IOM uint32_t OVERRIDE   : 10;           /*!< [9..0] Output pad override value. [7:0]=data [8]=clock [9]=DM             */
8184             uint32_t            : 22;
8185     } PADOVER_b;
8186   } ;
8187 
8188   union {
8189     __IOM uint32_t FLASH;                       /*!< (@ 0x00000120) When any SPI flash is configured, this register
8190                                                                     must be properly programmed before XIP or
8191                                                                     AUTO DMA operations commence.                              */
8192 
8193     struct {
8194       __IOM uint32_t XIPEN      : 1;            /*!< [0..0] Enable the XIP (eXecute In Place) function which effectively
8195                                                      enables the address decoding of the MSPI device in the
8196                                                      flash/cache address space at address 0x04000000-0x07FFFFFF.               */
8197       __IOM uint32_t XIPENDCX   : 1;            /*!< [1..1] Enable DCX signal on data [1] for XIP/DMA operations               */
8198       __IOM uint32_t XIPACK     : 2;            /*!< [3..2] Controls transmission of Micron XIP acknowledge cycles
8199                                                      (Micron Flash devices only)                                               */
8200       __IOM uint32_t XIPBIGENDIAN : 1;          /*!< [4..4] Indicates whether XIP/AUTO DMA data transfers are in
8201                                                      big or little endian format                                               */
8202       __IOM uint32_t XIPENTURN  : 1;            /*!< [5..5] Indicates whether XIP/AUTO DMA operations should enable
8203                                                      TX->RX turnaround cycles                                                  */
8204       __IOM uint32_t XIPSENDA   : 1;            /*!< [6..6] Indicates whether XIP/AUTO DMA operations should send
8205                                                      an an address phase (see DMADEVADDR register and ASIZE
8206                                                      field in CFG)                                                             */
8207       __IOM uint32_t XIPSENDI   : 1;            /*!< [7..7] Indicates whether XIP/AUTO DMA operations should send
8208                                                      an instruction (see READINSTR field and ISIZE field in
8209                                                      CFG)                                                                      */
8210       __IOM uint32_t XIPMIXED   : 3;            /*!< [10..8] Provides override controls for data operations where
8211                                                      instruction, address, and data may transfer in different
8212                                                      rates.                                                                    */
8213       __IOM uint32_t XIPENWLAT  : 1;            /*!< [11..11] Enable Write Latency counter for XIP write transactions          */
8214             uint32_t            : 20;
8215     } FLASH_b;
8216   } ;
8217 
8218   union {
8219     __IOM uint32_t XIPINSTR;                    /*!< (@ 0x00000124) When any SPI flash is configured, this register
8220                                                                     must be properly programmed before XIP or
8221                                                                     AUTO DMA operations commence.                              */
8222 
8223     struct {
8224       __IOM uint32_t WRITEINSTR : 16;           /*!< [15..0] Write command sent for DMA operations                             */
8225       __IOM uint32_t READINSTR  : 16;           /*!< [31..16] Read command sent to flash for DMA/XIP operations                */
8226     } XIPINSTR_b;
8227   } ;
8228 
8229   union {
8230     __IOM uint32_t SCRAMBLING;                  /*!< (@ 0x00000128) Enables data scrambling for the specified range
8231                                                                     external flash addresses. Scrambling does
8232                                                                     not impact flash access performance.                       */
8233 
8234     struct {
8235       __IOM uint32_t SCRSTART   : 10;           /*!< [9..0] Scrambling region start address [25:16] (64K block granularity).
8236                                                      The START block is the FIRST block included in the scrambled
8237                                                      address range.                                                            */
8238             uint32_t            : 6;
8239       __IOM uint32_t SCREND     : 10;           /*!< [25..16] Scrambling region end address [25:16] (64K block granularity).
8240                                                      The END block is the LAST block included in the scrambled
8241                                                      address range.                                                            */
8242             uint32_t            : 5;
8243       __IOM uint32_t SCRENABLE  : 1;            /*!< [31..31] Enables Data Scrambling Region. When 1 reads and writes
8244                                                      to the range will be scrambled. When 0, data will be read/written
8245                                                      unmodified. Address range is specified in 64K granularity
8246                                                      and the START/END ranges are included within the range.                   */
8247     } SCRAMBLING_b;
8248   } ;
8249   __IM  uint32_t  RESERVED2[53];
8250 
8251   union {
8252     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
8253                                                                     to generate the corresponding interrupt.                   */
8254 
8255     struct {
8256       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
8257                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
8258       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
8259       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
8260                                                      a full FIFO).                                                             */
8261       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
8262                                                      an empty FIFO)                                                            */
8263       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
8264                                                      MSPI bus pins will stall)                                                 */
8265       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
8266       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
8267       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
8268       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
8269       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
8270                                                      performs an operation where address bit[0] is set. Useful
8271                                                      for triggering CURIDX interrupts.                                         */
8272       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
8273       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
8274       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
8275                                                      be aligned to word (4-byte) start address.                                */
8276             uint32_t            : 19;
8277     } INTEN_b;
8278   } ;
8279 
8280   union {
8281     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
8282                                                                     cause of a recent interrupt.                               */
8283 
8284     struct {
8285       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
8286                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
8287       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
8288       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
8289                                                      a full FIFO).                                                             */
8290       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
8291                                                      an empty FIFO)                                                            */
8292       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
8293                                                      MSPI bus pins will stall)                                                 */
8294       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
8295       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
8296       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
8297       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
8298       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
8299                                                      performs an operation where address bit[0] is set. Useful
8300                                                      for triggering CURIDX interrupts.                                         */
8301       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
8302       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
8303       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
8304                                                      be aligned to word (4-byte) start address.                                */
8305             uint32_t            : 19;
8306     } INTSTAT_b;
8307   } ;
8308 
8309   union {
8310     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
8311                                                                     the interrupt status associated with that
8312                                                                     bit.                                                       */
8313 
8314     struct {
8315       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
8316                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
8317       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
8318       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
8319                                                      a full FIFO).                                                             */
8320       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
8321                                                      an empty FIFO)                                                            */
8322       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
8323                                                      MSPI bus pins will stall)                                                 */
8324       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
8325       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
8326       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
8327       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
8328       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
8329                                                      performs an operation where address bit[0] is set. Useful
8330                                                      for triggering CURIDX interrupts.                                         */
8331       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
8332       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
8333       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
8334                                                      be aligned to word (4-byte) start address.                                */
8335             uint32_t            : 19;
8336     } INTCLR_b;
8337   } ;
8338 
8339   union {
8340     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
8341                                                                     generate an interrupt from this module.
8342                                                                     (Generally used for testing purposes).                     */
8343 
8344     struct {
8345       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
8346                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
8347       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
8348       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
8349                                                      a full FIFO).                                                             */
8350       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
8351                                                      an empty FIFO)                                                            */
8352       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
8353                                                      MSPI bus pins will stall)                                                 */
8354       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
8355       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
8356       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
8357       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
8358       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
8359                                                      performs an operation where address bit[0] is set. Useful
8360                                                      for triggering CURIDX interrupts.                                         */
8361       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
8362       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
8363       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
8364                                                      be aligned to word (4-byte) start address.                                */
8365             uint32_t            : 19;
8366     } INTSET_b;
8367   } ;
8368   __IM  uint32_t  RESERVED3[16];
8369 
8370   union {
8371     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000250) DMA Configuration                                          */
8372 
8373     struct {
8374       __IOM uint32_t DMAEN      : 2;            /*!< [1..0] DMA Enable. Setting this bit to EN will start the DMA
8375                                                      operation                                                                 */
8376       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
8377       __IOM uint32_t DMAPRI     : 2;            /*!< [4..3] Sets the Priority of the DMA request                               */
8378             uint32_t            : 13;
8379       __IOM uint32_t DMAPWROFF  : 1;            /*!< [18..18] Power off MSPI domain upon completion of DMA operation.          */
8380             uint32_t            : 13;
8381     } DMACFG_b;
8382   } ;
8383 
8384   union {
8385     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000254) DMA Status                                                 */
8386 
8387     struct {
8388       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
8389                                                      a DMA transfer is active. The DMA transfer may be waiting
8390                                                      on data, transferring data, or waiting for priority. All
8391                                                      of these will be indicated with a 1. A 0 will indicate
8392                                                      that the DMA is fully complete and no further transactions
8393                                                      will be done.                                                             */
8394       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
8395                                                      operation.                                                                */
8396       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals that an error
8397                                                      was encountered during the DMA operation.                                 */
8398       __IOM uint32_t SCRERR     : 1;            /*!< [3..3] Scrambling Access Alignment Error. This active high bit
8399                                                      signals that a scrambling operation was specified for a
8400                                                      non-word aligned DEVADDR.                                                 */
8401             uint32_t            : 28;
8402     } DMASTAT_b;
8403   } ;
8404 
8405   union {
8406     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000258) DMA Target Address                                         */
8407 
8408     struct {
8409       __IOM uint32_t TARGADDR   : 32;           /*!< [31..0] Target byte address for source of DMA (either read or
8410                                                      write). In cases of non-word aligned addresses, the DMA
8411                                                      logic will take care for ensuring only the target bytes
8412                                                      are read/written.                                                         */
8413     } DMATARGADDR_b;
8414   } ;
8415 
8416   union {
8417     __IOM uint32_t DMADEVADDR;                  /*!< (@ 0x0000025C) DMA Device Address                                         */
8418 
8419     struct {
8420       __IOM uint32_t DEVADDR    : 32;           /*!< [31..0] SPI Device address for automated DMA transactions (both
8421                                                      read and write).                                                          */
8422     } DMADEVADDR_b;
8423   } ;
8424 
8425   union {
8426     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000260) DMA Total Transfer Count                                   */
8427 
8428     struct {
8429       __IOM uint32_t TOTCOUNT   : 24;           /*!< [23..0] Total Transfer Count in bytes.                                    */
8430             uint32_t            : 8;
8431     } DMATOTCOUNT_b;
8432   } ;
8433 
8434   union {
8435     __IOM uint32_t DMABCOUNT;                   /*!< (@ 0x00000264) DMA BYTE Transfer Count                                    */
8436 
8437     struct {
8438       __IOM uint32_t BCOUNT     : 8;            /*!< [7..0] Burst transfer size in bytes. This is the number of bytes
8439                                                      transferred when a FIFO trigger event occurs. Recommended
8440                                                      value is 32.                                                              */
8441             uint32_t            : 24;
8442     } DMABCOUNT_b;
8443   } ;
8444 
8445   union {
8446     __IOM uint32_t DMATHRESH;                   /*!< (@ 0x00000268) Indicates FIFO level at which a DMA should be
8447                                                                     triggered. For most configurations, a setting
8448                                                                     of 8 is recommended for both read and write
8449                                                                     operations.                                                */
8450 
8451     struct {
8452       __IOM uint32_t DMATXTHRESH : 5;           /*!< [4..0] DMA transfer FIFO level trigger. For read operations,
8453                                                      DMA is triggered when the FIFO level is greater than this
8454                                                      value. For write operations, DMA is triggered when the
8455                                                      FIFO level is less than this level. Each DMA operation
8456                                                      will consist of BCOUNT bytes.                                             */
8457             uint32_t            : 3;
8458       __IOM uint32_t DMARXTHRESH : 5;           /*!< [12..8] DMA transfer FIFO level trigger. For read operations,
8459                                                      DMA is triggered when the FIFO level is greater than this
8460                                                      value. For write operations, DMA is triggered when the
8461                                                      FIFO level is less than this level. Each DMA operation
8462                                                      will consist of BCOUNT bytes.                                             */
8463             uint32_t            : 19;
8464     } DMATHRESH_b;
8465   } ;
8466 
8467   union {
8468     __IOM uint32_t DMABOUNDARY;                 /*!< (@ 0x0000026C) Allows large transfers to be broken up into smaller
8469                                                                     ones in hardware to accommodate needs of
8470                                                                     external devices and allow XIP/XIPMM. Only
8471                                                                     applicable for memory-mapped devices (PSRAM,
8472                                                                     Flash, etc) where address can be retransmitted
8473                                                                     without side effects.                                      */
8474 
8475     struct {
8476       __IOM uint32_t DMATIMELIMIT : 12;         /*!< [11..0] DMA time limit. Can be used to limit the transaction
8477                                                      time on the MSPI bus. The count is in 100 ns increments.
8478                                                      A value of 0 disables the counter.                                        */
8479       __IOM uint32_t DMABOUND   : 4;            /*!< [15..12] DMA Address boundary                                             */
8480             uint32_t            : 16;
8481     } DMABOUNDARY_b;
8482   } ;
8483   __IM  uint32_t  RESERVED4[12];
8484 
8485   union {
8486     __IOM uint32_t CQCFG;                       /*!< (@ 0x000002A0) This register controls Command Queuing (CQ) operations
8487                                                                     in a manner similar to the DMACFG register.                */
8488 
8489     struct {
8490       __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
8491                                                      of the command queue                                                      */
8492       __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue DMA request                 */
8493       __IOM uint32_t CQPWROFF   : 1;            /*!< [2..2] Power off MSPI domain upon completion of DMA operation.            */
8494       __IOM uint32_t CQAUTOCLEARMASK : 1;       /*!< [3..3] Enable clear of CQMASK after each pause operation. This
8495                                                      may be useful when using software flags to pause CQ.                      */
8496             uint32_t            : 28;
8497     } CQCFG_b;
8498   } ;
8499   __IM  uint32_t  RESERVED5;
8500 
8501   union {
8502     __IOM uint32_t CQADDR;                      /*!< (@ 0x000002A8) Location of the command queue in SRAM or flash
8503                                                                     memory. This register will increment as
8504                                                                     CQ operations commence. Software should
8505                                                                     only write CQADDR when CQEN is disabled,
8506                                                                     however the command queue script itself
8507                                                                     may update CQADDR in order to perform queue
8508                                                                     management functions (like resetting the
8509                                                                     pointers)                                                  */
8510 
8511     struct {
8512       __IOM uint32_t CQADDR     : 29;           /*!< [28..0] Address of command queue buffer in SRAM or flash. The
8513                                                      buffer address must be aligned to a word boundary.                        */
8514             uint32_t            : 3;
8515     } CQADDR_b;
8516   } ;
8517 
8518   union {
8519     __IOM uint32_t CQSTAT;                      /*!< (@ 0x000002AC) Command Queue Status                                       */
8520 
8521     struct {
8522       __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
8523                                                      indicate that a CQ transfer is active and this will remain
8524                                                      active even when paused waiting for external event.                       */
8525       __IOM uint32_t CQCPL      : 1;            /*!< [1..1] Command queue operation Complete. This signals the end
8526                                                      of the command queue operation.                                           */
8527       __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing Error. This active high bit
8528                                                      signals that an error was encountered during the CQ operation.            */
8529       __IOM uint32_t CQPAUSED   : 1;            /*!< [3..3] Command queue is currently paused status.                          */
8530             uint32_t            : 28;
8531     } CQSTAT_b;
8532   } ;
8533 
8534   union {
8535     __IOM uint32_t CQFLAGS;                     /*!< (@ 0x000002B0) Command Queue Flags                                        */
8536 
8537     struct {
8538       __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
8539                                                      controllable and bits [15:8] are hardware status.                         */
8540             uint32_t            : 16;
8541     } CQFLAGS_b;
8542   } ;
8543 
8544   union {
8545     __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x000002B4) Command Queue Flag Set/Clear                               */
8546 
8547     struct {
8548       __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Set has priority over clear if
8549                                                      both are high.                                                            */
8550       __IOM uint32_t CQFTOGGLE  : 8;            /*!< [15..8] Toggle CQFlag status bits                                         */
8551       __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits.                                        */
8552             uint32_t            : 8;
8553     } CQSETCLEAR_b;
8554   } ;
8555 
8556   union {
8557     __IOM uint32_t CQPAUSE;                     /*!< (@ 0x000002B8) Command Queue Pause Mask                                   */
8558 
8559     struct {
8560       __IOM uint32_t CQMASK     : 16;           /*!< [15..0] CQ will pause processing when ALL specified events are
8561                                                      satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK.                      */
8562             uint32_t            : 16;
8563     } CQPAUSE_b;
8564   } ;
8565   __IM  uint32_t  RESERVED6;
8566 
8567   union {
8568     __IOM uint32_t CQCURIDX;                    /*!< (@ 0x000002C0) This register can be used in conjunction with
8569                                                                     the CQENDIDX register to manage the command
8570                                                                     queue. Typically software will initialize
8571                                                                     the CQCURIDX and CQENDIDX to the same value,
8572                                                                     which will cause the CQ to be paused when
8573                                                                     enabled. Software may then add entries to
8574                                                                     the command queue (in SRAM) and update CQENDIDX.
8575                                                                     The command queue operations will then increment
8576                                                                     CQCURIDX as it processes operations. Once
8577                                                                     CQCURIDX==CQENDIDX, the command queue hardware
8578                                                                     will automatically pause since no additional
8579                                                                     ope                                                        */
8580 
8581     struct {
8582       __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Can be used to indicate the current position of the command
8583                                                      queue by having CQ operations write this field. A CQ hardware
8584                                                      status flag indicates when CURIDX and ENDIDX are not equal,
8585                                                      allowing SW to pause the CQ processing until the end index
8586                                                      is updated.                                                               */
8587             uint32_t            : 24;
8588     } CQCURIDX_b;
8589   } ;
8590 
8591   union {
8592     __IOM uint32_t CQENDIDX;                    /*!< (@ 0x000002C4) Command Queue End Index                                    */
8593 
8594     struct {
8595       __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Can be used to indicate the end position of the command
8596                                                      queue. A CQ hardware status bit indices when CURIDX !=
8597                                                      ENDIDX so that the CQ can be paused when it reaches the
8598                                                      end pointer.                                                              */
8599             uint32_t            : 24;
8600     } CQENDIDX_b;
8601   } ;
8602 } MSPI0_Type;                                   /*!< Size = 712 (0x2c8)                                                        */
8603 
8604 
8605 
8606 /* =========================================================================================================================== */
8607 /* ================                                            PDM                                            ================ */
8608 /* =========================================================================================================================== */
8609 
8610 
8611 /**
8612   * @brief PDM Audio (PDM)
8613   */
8614 
8615 typedef struct {                                /*!< (@ 0x50011000) PDM Structure                                              */
8616 
8617   union {
8618     __IOM uint32_t PCFG;                        /*!< (@ 0x00000000) PDM Configuration                                          */
8619 
8620     struct {
8621       __IOM uint32_t PDMCOREEN  : 1;            /*!< [0..0] Data Streaming Control.                                            */
8622       __IOM uint32_t SOFTMUTE   : 1;            /*!< [1..1] Soft mute control.                                                 */
8623       __IOM uint32_t CYCLES     : 3;            /*!< [4..2] Number of clocks during gain-setting changes.                      */
8624       __IOM uint32_t HPCUTOFF   : 4;            /*!< [8..5] High pass filter coefficients.                                     */
8625       __IOM uint32_t ADCHPD     : 1;            /*!< [9..9] High pass filter control.                                          */
8626       __IOM uint32_t SINCRATE   : 7;            /*!< [16..10] SINC decimation rate.                                            */
8627       __IOM uint32_t MCLKDIV    : 2;            /*!< [18..17] PDM_CLK frequency divisor.                                       */
8628             uint32_t            : 2;
8629       __IOM uint32_t PGALEFT    : 5;            /*!< [25..21] Left channel PGA gain.                                           */
8630       __IOM uint32_t PGARIGHT   : 5;            /*!< [30..26] Right channel PGA gain.                                          */
8631       __IOM uint32_t LRSWAP     : 1;            /*!< [31..31] Left/right channel swap.                                         */
8632     } PCFG_b;
8633   } ;
8634 
8635   union {
8636     __IOM uint32_t VCFG;                        /*!< (@ 0x00000004) Voice Configuration                                        */
8637 
8638     struct {
8639             uint32_t            : 3;
8640       __IOM uint32_t CHSET      : 2;            /*!< [4..3] Set PCM channels.                                                  */
8641             uint32_t            : 3;
8642       __IOM uint32_t PCMPACK    : 1;            /*!< [8..8] PCM data packing enable.                                           */
8643             uint32_t            : 7;
8644       __IOM uint32_t SELAP      : 1;            /*!< [16..16] Select PDM input clock source.                                   */
8645       __IOM uint32_t DMICKDEL   : 1;            /*!< [17..17] PDM clock sampling delay.                                        */
8646             uint32_t            : 1;
8647       __IOM uint32_t BCLKINV    : 1;            /*!< [19..19] I2S BCLK input inversion.                                        */
8648       __IOM uint32_t I2SEN      : 1;            /*!< [20..20] I2S interface enable.                                            */
8649             uint32_t            : 5;
8650       __IOM uint32_t PDMCLKEN   : 1;            /*!< [26..26] Enable the serial clock.                                         */
8651       __IOM uint32_t PDMCLKSEL  : 3;            /*!< [29..27] Select the PDM input clock.                                      */
8652       __IOM uint32_t RSTB       : 1;            /*!< [30..30] Reset the IP core.                                               */
8653       __IOM uint32_t IOCLKEN    : 1;            /*!< [31..31] Enable the IO clock.                                             */
8654     } VCFG_b;
8655   } ;
8656 
8657   union {
8658     __IOM uint32_t VOICESTAT;                   /*!< (@ 0x00000008) Voice Status                                               */
8659 
8660     struct {
8661       __IOM uint32_t FIFOCNT    : 6;            /*!< [5..0] Valid 32-bit entries currently in the FIFO.                        */
8662             uint32_t            : 26;
8663     } VOICESTAT_b;
8664   } ;
8665 
8666   union {
8667     __IOM uint32_t FIFOREAD;                    /*!< (@ 0x0000000C) FIFO Read                                                  */
8668 
8669     struct {
8670       __IOM uint32_t FIFOREAD   : 32;           /*!< [31..0] FIFO read data.                                                   */
8671     } FIFOREAD_b;
8672   } ;
8673 
8674   union {
8675     __IOM uint32_t FIFOFLUSH;                   /*!< (@ 0x00000010) FIFO Flush                                                 */
8676 
8677     struct {
8678       __IOM uint32_t FIFOFLUSH  : 1;            /*!< [0..0] FIFO FLUSH.                                                        */
8679             uint32_t            : 31;
8680     } FIFOFLUSH_b;
8681   } ;
8682 
8683   union {
8684     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000014) FIFO Threshold                                             */
8685 
8686     struct {
8687       __IOM uint32_t FIFOTHR    : 5;            /*!< [4..0] FIFO Threshold value. When the FIFO count is equal to,
8688                                                      or larger than this value (in words), a THR interrupt is
8689                                                      generated (if enabled)                                                    */
8690             uint32_t            : 27;
8691     } FIFOTHR_b;
8692   } ;
8693   __IM  uint32_t  RESERVED[122];
8694 
8695   union {
8696     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
8697                                                                     to generate the corresponding interrupt.                   */
8698 
8699     struct {
8700       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
8701       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
8702       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
8703       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
8704       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error received                                                 */
8705             uint32_t            : 27;
8706     } INTEN_b;
8707   } ;
8708 
8709   union {
8710     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
8711                                                                     cause of a recent interrupt.                               */
8712 
8713     struct {
8714       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
8715       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
8716       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
8717       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
8718       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error received                                                 */
8719             uint32_t            : 27;
8720     } INTSTAT_b;
8721   } ;
8722 
8723   union {
8724     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
8725                                                                     the interrupt status associated with that
8726                                                                     bit.                                                       */
8727 
8728     struct {
8729       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
8730       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
8731       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
8732       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
8733       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error received                                                 */
8734             uint32_t            : 27;
8735     } INTCLR_b;
8736   } ;
8737 
8738   union {
8739     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
8740                                                                     generate an interrupt from this module.
8741                                                                     (Generally used for testing purposes).                     */
8742 
8743     struct {
8744       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
8745       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
8746       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
8747       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
8748       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error received                                                 */
8749             uint32_t            : 27;
8750     } INTSET_b;
8751   } ;
8752   __IM  uint32_t  RESERVED1[12];
8753 
8754   union {
8755     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000240) DMA Trigger Enable                                         */
8756 
8757     struct {
8758       __IOM uint32_t DTHR       : 1;            /*!< [0..0] Trigger DMA upon when FIFO is filled to level indicated
8759                                                      by the FIFO THRESHOLD,at granularity of 16 bytes only                     */
8760       __IOM uint32_t DTHR90     : 1;            /*!< [1..1] Trigger DMA at FIFO 90 percent full. This signal is also
8761                                                      used internally for AUTOHIP function                                      */
8762             uint32_t            : 30;
8763     } DMATRIGEN_b;
8764   } ;
8765 
8766   union {
8767     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000244) DMA Trigger Status                                         */
8768 
8769     struct {
8770       __IOM uint32_t DTHRSTAT   : 1;            /*!< [0..0] Triggered DMA from FIFO reaching threshold                         */
8771       __IOM uint32_t DTHR90STAT : 1;            /*!< [1..1] Triggered DMA from FIFO reaching 90 percent full                   */
8772             uint32_t            : 30;
8773     } DMATRIGSTAT_b;
8774   } ;
8775   __IM  uint32_t  RESERVED2[14];
8776 
8777   union {
8778     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000280) DMA Configuration                                          */
8779 
8780     struct {
8781       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
8782             uint32_t            : 1;
8783       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
8784             uint32_t            : 5;
8785       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
8786       __IOM uint32_t DAUTOHIP   : 1;            /*!< [9..9] Raise priority to high on FIFO full, and DMAPRI set to
8787                                                      low                                                                       */
8788       __IOM uint32_t DPWROFF    : 1;            /*!< [10..10] Power Off the ADC System upon DMACPL.                            */
8789             uint32_t            : 21;
8790     } DMACFG_b;
8791   } ;
8792   __IM  uint32_t  RESERVED3;
8793 
8794   union {
8795     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000288) DMA Total Transfer Count                                   */
8796 
8797     struct {
8798       __IOM uint32_t TOTCOUNT   : 20;           /*!< [19..0] Total Transfer Count. The transfer count must be a multiple
8799                                                      of the THR setting to avoid DMA overruns.                                 */
8800             uint32_t            : 12;
8801     } DMATOTCOUNT_b;
8802   } ;
8803 
8804   union {
8805     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x0000028C) DMA Target Address                                         */
8806 
8807     struct {
8808       __IOM uint32_t LTARGADDR  : 21;           /*!< [20..0] DMA Target Address. This register is not updated with
8809                                                      the current address of the DMA, but will remain static
8810                                                      with the original address during the DMA transfer.                        */
8811       __IOM uint32_t UTARGADDR  : 11;           /*!< [31..21] SRAM Target                                                      */
8812     } DMATARGADDR_b;
8813   } ;
8814 
8815   union {
8816     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000290) DMA Status                                                 */
8817 
8818     struct {
8819       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
8820       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
8821       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
8822             uint32_t            : 29;
8823     } DMASTAT_b;
8824   } ;
8825 } PDM_Type;                                     /*!< Size = 660 (0x294)                                                        */
8826 
8827 
8828 
8829 /* =========================================================================================================================== */
8830 /* ================                                          PWRCTRL                                          ================ */
8831 /* =========================================================================================================================== */
8832 
8833 
8834 /**
8835   * @brief PWR Controller Register Bank (PWRCTRL)
8836   */
8837 
8838 typedef struct {                                /*!< (@ 0x40021000) PWRCTRL Structure                                          */
8839 
8840   union {
8841     __IOM uint32_t SUPPLYSRC;                   /*!< (@ 0x00000000) This register controls the enable for BLE BUCK.            */
8842 
8843     struct {
8844       __IOM uint32_t BLEBUCKEN  : 1;            /*!< [0..0] Enables and Selects the BLE Buck as the supply for the
8845                                                      BLE power domain or for Burst LDO. It takes the initial
8846                                                      value from Customer INFO space. Buck will be powered up
8847                                                      only if there is an active request for BLEH domain or Burst
8848                                                      mode and appropriate feature is allowed.                                  */
8849             uint32_t            : 31;
8850     } SUPPLYSRC_b;
8851   } ;
8852 
8853   union {
8854     __IOM uint32_t SUPPLYSTATUS;                /*!< (@ 0x00000004) Provides an indicator for the BLE BUCK and SIMO
8855                                                                     BUCK status. Once the SIMO BUCK is powered
8856                                                                     up MEM and CORE LDOs are disabled.                         */
8857 
8858     struct {
8859       __IOM uint32_t SIMOBUCKON : 1;            /*!< [0..0] Indicates whether the Core/Mem low-voltage domains are
8860                                                      supplied from the LDO or the Buck.                                        */
8861       __IOM uint32_t BLEBUCKON  : 1;            /*!< [1..1] Indicates whether the BLE (if supported) domain and burst
8862                                                      (if supported) domain is supplied from the LDO or the Buck.
8863                                                      Buck will be powered up only if there is an active request
8864                                                      for BLEH domain or Burst mode and appropriate feature is
8865                                                      allowed.                                                                  */
8866             uint32_t            : 30;
8867     } SUPPLYSTATUS_b;
8868   } ;
8869 
8870   union {
8871     __IOM uint32_t DEVPWREN;                    /*!< (@ 0x00000008) This enables various peripherals power domains.            */
8872 
8873     struct {
8874       __IOM uint32_t PWRIOS     : 1;            /*!< [0..0] Power up IO Slave                                                  */
8875       __IOM uint32_t PWRIOM0    : 1;            /*!< [1..1] Power up IO Master 0                                               */
8876       __IOM uint32_t PWRIOM1    : 1;            /*!< [2..2] Power up IO Master 1                                               */
8877       __IOM uint32_t PWRIOM2    : 1;            /*!< [3..3] Power up IO Master 2                                               */
8878       __IOM uint32_t PWRIOM3    : 1;            /*!< [4..4] Power up IO Master 3                                               */
8879       __IOM uint32_t PWRIOM4    : 1;            /*!< [5..5] Power up IO Master 4                                               */
8880       __IOM uint32_t PWRIOM5    : 1;            /*!< [6..6] Power up IO Master 5                                               */
8881       __IOM uint32_t PWRUART0   : 1;            /*!< [7..7] Power up UART Controller 0                                         */
8882       __IOM uint32_t PWRUART1   : 1;            /*!< [8..8] Power up UART Controller 1                                         */
8883       __IOM uint32_t PWRADC     : 1;            /*!< [9..9] Power up ADC Digital Controller                                    */
8884       __IOM uint32_t PWRSCARD   : 1;            /*!< [10..10] Power up SCARD Controller                                        */
8885       __IOM uint32_t PWRMSPI0   : 1;            /*!< [11..11] Power up MSPI0 Controller                                        */
8886       __IOM uint32_t PWRMSPI1   : 1;            /*!< [12..12] Power up MSPI1 Controller                                        */
8887       __IOM uint32_t PWRMSPI2   : 1;            /*!< [13..13] Power up MSPI2 Controller                                        */
8888       __IOM uint32_t PWRPDM     : 1;            /*!< [14..14] Power up PDM block                                               */
8889       __IOM uint32_t PWRBLEL    : 1;            /*!< [15..15] Power up BLE controller                                          */
8890             uint32_t            : 16;
8891     } DEVPWREN_b;
8892   } ;
8893 
8894   union {
8895     __IOM uint32_t MEMPWDINSLEEP;               /*!< (@ 0x0000000C) This controls the power down of the SRAM banks
8896                                                                     in deep sleep mode. If this is set, then
8897                                                                     the power for that SRAM bank will be gated
8898                                                                     when the core goes into deep sleep. Upon
8899                                                                     wake, the data within the SRAMs will be
8900                                                                     erased. If this is not set, retention voltage
8901                                                                     will be applied to the SRAM bank when the
8902                                                                     core goes into deep sleep. Upon wake, the
8903                                                                     data within the SRAMs are retained. Do not
8904                                                                     set this if the SRAM bank is used as the
8905                                                                     target for DMA transfer while CPU in deep
8906                                                                     sleep.                                                     */
8907 
8908     struct {
8909       __IOM uint32_t DTCMPWDSLP : 3;            /*!< [2..0] power down DTCM in deep sleep                                      */
8910       __IOM uint32_t SRAMPWDSLP : 10;           /*!< [12..3] Selects which SRAM banks are powered down in deep sleep
8911                                                      mode, causing the contents of the bank to be lost.                        */
8912       __IOM uint32_t FLASH0PWDSLP : 1;          /*!< [13..13] Power-down FLASH0 in deep sleep                                  */
8913       __IOM uint32_t FLASH1PWDSLP : 1;          /*!< [14..14] Power-down FLASH1 in deep sleep                                  */
8914             uint32_t            : 16;
8915       __IOM uint32_t CACHEPWDSLP : 1;           /*!< [31..31] power down cache in deep sleep                                   */
8916     } MEMPWDINSLEEP_b;
8917   } ;
8918 
8919   union {
8920     __IOM uint32_t MEMPWREN;                    /*!< (@ 0x00000010) This register enables the individual banks for
8921                                                                     the memories. When set, power will be enabled
8922                                                                     to the banks. This register works in conjunction
8923                                                                     with the MEMPWDINSLEEP register. When this
8924                                                                     register is set, then the MEMPWRINSLEEP
8925                                                                     register will determine whether power is
8926                                                                     enabled to the SRAMs in deep sleep. If this
8927                                                                     register is not set, then power will always
8928                                                                     be disabled to the memory bank.                            */
8929 
8930     struct {
8931       __IOM uint32_t DTCM       : 3;            /*!< [2..0] Power up DTCM                                                      */
8932       __IOM uint32_t SRAM       : 10;           /*!< [12..3] Power up SRAM groups                                              */
8933       __IOM uint32_t FLASH0     : 1;            /*!< [13..13] Power up FLASH group 0 (0MB-1MB)                                 */
8934       __IOM uint32_t FLASH1     : 1;            /*!< [14..14] Power up FLASH group 1 (1MB-2MB)                                 */
8935             uint32_t            : 15;
8936       __IOM uint32_t CACHEB0    : 1;            /*!< [30..30] Power up Cache Bank 0. This works in conjunction with
8937                                                      Cache enable from flash_cache module. To power up cache
8938                                                      bank 0, cache has to be enabled and this bit has to be
8939                                                      set.                                                                      */
8940       __IOM uint32_t CACHEB2    : 1;            /*!< [31..31] Power up Cache Bank 2. This works in conjunction with
8941                                                      Cache enable from flash_cache module. To power up cache
8942                                                      bank 2, cache has to be enabled and this bit has to be
8943                                                      set.                                                                      */
8944     } MEMPWREN_b;
8945   } ;
8946 
8947   union {
8948     __IOM uint32_t MEMPWRSTATUS;                /*!< (@ 0x00000014) It provides the power status for all the memory
8949                                                                     banks including- caches, FLASH (0 and 1)
8950                                                                     and all the SRAM groups. The status here
8951                                                                     should reflect the enable provided by the
8952                                                                     MEMPWREN register. There may be a lag time
8953                                                                     between setting the bits in MEMPWREN register
8954                                                                     and MEMPWRSTATUS register, due to the need
8955                                                                     to cycle the power gate and isolation sequences
8956                                                                     to the memory banks.                                       */
8957 
8958     struct {
8959       __IOM uint32_t DTCM00     : 1;            /*!< [0..0] This bit is 1 if power is supplied to DTCM GROUP0_0                */
8960       __IOM uint32_t DTCM01     : 1;            /*!< [1..1] This bit is 1 if power is supplied to DTCM GROUP0_1                */
8961       __IOM uint32_t DTCM1      : 1;            /*!< [2..2] This bit is 1 if power is supplied to DTCM GROUP1                  */
8962       __IOM uint32_t SRAM0      : 1;            /*!< [3..3] This bit is 1 if power is supplied to SRAM GROUP0                  */
8963       __IOM uint32_t SRAM1      : 1;            /*!< [4..4] This bit is 1 if power is supplied to SRAM GROUP1                  */
8964       __IOM uint32_t SRAM2      : 1;            /*!< [5..5] This bit is 1 if power is supplied to SRAM GROUP2                  */
8965       __IOM uint32_t SRAM3      : 1;            /*!< [6..6] This bit is 1 if power is supplied to SRAM GROUP3                  */
8966       __IOM uint32_t SRAM4      : 1;            /*!< [7..7] This bit is 1 if power is supplied to SRAM GROUP4                  */
8967       __IOM uint32_t SRAM5      : 1;            /*!< [8..8] This bit is 1 if power is supplied to SRAM GROUP5                  */
8968       __IOM uint32_t SRAM6      : 1;            /*!< [9..9] This bit is 1 if power is supplied to SRAM GROUP6                  */
8969       __IOM uint32_t SRAM7      : 1;            /*!< [10..10] This bit is 1 if power is supplied to SRAM GROUP7                */
8970       __IOM uint32_t SRAM8      : 1;            /*!< [11..11] This bit is 1 if power is supplied to SRAM GROUP8                */
8971       __IOM uint32_t SRAM9      : 1;            /*!< [12..12] This bit is 1 if power is supplied to SRAM GROUP9                */
8972       __IOM uint32_t FLASH0     : 1;            /*!< [13..13] This bit is 1 if power is supplied to FLASH group 0              */
8973       __IOM uint32_t FLASH1     : 1;            /*!< [14..14] This bit is 1 if power is supplied to FLASH group 1              */
8974       __IOM uint32_t CACHEB0    : 1;            /*!< [15..15] This bit is 1 if power is supplied to Cache Bank 0               */
8975       __IOM uint32_t CACHEB2    : 1;            /*!< [16..16] This bit is 1 if power is supplied to Cache Bank 2               */
8976             uint32_t            : 15;
8977     } MEMPWRSTATUS_b;
8978   } ;
8979 
8980   union {
8981     __IOM uint32_t DEVPWRSTATUS;                /*!< (@ 0x00000018) This provides the power status for the peripheral
8982                                                                     devices- BLEL, PDM, PDM, MSPI2-0, SCARD,
8983                                                                     ADC, UART0 and 1, IOM5 to 0, IOSLAVE and
8984                                                                     MCUL (DMA and Fabrics) and MCUH (ARM core).
8985                                                                     The status here should reflect the enable
8986                                                                     provided by the DEVPWREN register. There
8987                                                                     may be a lag time between setting the bits
8988                                                                     in DEVPWREN register and DEVPWRSTATUS register,
8989                                                                     due to the need to cycle the power gate,
8990                                                                     isolation and reset sequences to the device
8991                                                                     power domains.                                             */
8992 
8993     struct {
8994       __IOM uint32_t MCUL       : 1;            /*!< [0..0] This bit is 1 if power is supplied to MCUL                         */
8995       __IOM uint32_t MCUH       : 1;            /*!< [1..1] This bit is 1 if power is supplied to MCUH                         */
8996       __IOM uint32_t HCPA       : 1;            /*!< [2..2] This bit is 1 if power is supplied to HCPA domain (IO
8997                                                      SLAVE, UART0, UART1, SCARD)                                               */
8998       __IOM uint32_t HCPB       : 1;            /*!< [3..3] This bit is 1 if power is supplied to HCPB domain (IO
8999                                                      MASTER 0, 1, 2)                                                           */
9000       __IOM uint32_t HCPC       : 1;            /*!< [4..4] This bit is 1 if power is supplied to HCPC domain (IO
9001                                                      MASTER4, 5, 6)                                                            */
9002       __IOM uint32_t PWRADC     : 1;            /*!< [5..5] This bit is 1 if power is supplied to ADC                          */
9003       __IOM uint32_t PWRMSPI    : 1;            /*!< [6..6] This bit is 1 if power is supplied to MSPI                         */
9004       __IOM uint32_t PWRPDM     : 1;            /*!< [7..7] This bit is 1 if power is supplied to PDM                          */
9005       __IOM uint32_t BLEL       : 1;            /*!< [8..8] This bit is 1 if power is supplied to BLEL                         */
9006       __IOM uint32_t BLEH       : 1;            /*!< [9..9] This bit is 1 if power is supplied to BLEH                         */
9007             uint32_t            : 22;
9008     } DEVPWRSTATUS_b;
9009   } ;
9010 
9011   union {
9012     __IOM uint32_t SRAMCTRL;                    /*!< (@ 0x0000001C) This register provides additional fine-tune power
9013                                                                     management controls for the SRAMs and the
9014                                                                     SRAM controller. This includes enabling
9015                                                                     light sleep for the SRAM and TCM banks,
9016                                                                     and clock gating for reduced dynamic power.                */
9017 
9018     struct {
9019             uint32_t            : 1;
9020       __IOM uint32_t SRAMCLKGATE : 1;           /*!< [1..1] This bit is 1 if clock gating is allowed for individual
9021                                                      system SRAMs                                                              */
9022       __IOM uint32_t SRAMMASTERCLKGATE : 1;     /*!< [2..2] This bit is 1 when the master clock gate is enabled (top-level
9023                                                      clock gate for entire SRAM block)                                         */
9024             uint32_t            : 5;
9025       __IOM uint32_t SRAMLIGHTSLEEP : 12;       /*!< [19..8] Light Sleep enable for each TCM/SRAM bank. When 1, corresponding
9026                                                      bank will be put into light sleep. For optimal power, banks
9027                                                      should be put into light sleep while the system is active
9028                                                      but the bank has minimal or no accesses.                                  */
9029             uint32_t            : 12;
9030     } SRAMCTRL_b;
9031   } ;
9032 
9033   union {
9034     __IOM uint32_t ADCSTATUS;                   /*!< (@ 0x00000020) This provides the power status for various blocks
9035                                                                     within the ADC. These status comes directly
9036                                                                     from the ADC module and is captured through
9037                                                                     this interface.                                            */
9038 
9039     struct {
9040       __IOM uint32_t ADCPWD     : 1;            /*!< [0..0] This bit indicates that the ADC is powered down                    */
9041       __IOM uint32_t BGTPWD     : 1;            /*!< [1..1] This bit indicates that the ADC Band Gap is powered down           */
9042       __IOM uint32_t VPTATPWD   : 1;            /*!< [2..2] This bit indicates that the ADC temperature sensor input
9043                                                      buffer is powered down                                                    */
9044       __IOM uint32_t VBATPWD    : 1;            /*!< [3..3] This bit indicates that the ADC VBAT resistor divider
9045                                                      is powered down                                                           */
9046       __IOM uint32_t REFKEEPPWD : 1;            /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down            */
9047       __IOM uint32_t REFBUFPWD  : 1;            /*!< [5..5] This bit indicates that the ADC REFBUF is powered down             */
9048             uint32_t            : 26;
9049     } ADCSTATUS_b;
9050   } ;
9051 
9052   union {
9053     __IOM uint32_t MISC;                        /*!< (@ 0x00000024) This register includes additional debug control
9054                                                                     bits. This is an internal Ambiq-only register.
9055                                                                     Customers should not attempt to change this
9056                                                                     or else functionality cannot be guaranteed.                */
9057 
9058     struct {
9059       __IOM uint32_t SIMOBUCKEN : 1;            /*!< [0..0] Enables and Selects the SIMO Buck as the supply for the
9060                                                      low-voltage power domain. It takes the initial value from
9061                                                      the bit set in Customer INFO space.                                       */
9062             uint32_t            : 2;
9063       __IOM uint32_t FORCEMEMVRLPTIMERS : 1;    /*!< [3..3] Control Bit to force Mem VR to LP mode in deep sleep
9064                                                      even when hfrc based ctimer or stimer is running.                         */
9065             uint32_t            : 2;
9066       __IOM uint32_t MEMVRLPBLE : 1;            /*!< [6..6] Control Bit to let Mem VR go to lp mode in deep sleep
9067                                                      even when BLEL or BLEH is powered on given none of the
9068                                                      other domains require it.                                                 */
9069       __IOM uint32_t FORCEBLEBUCKACT : 1;       /*!< [7..7] Control Bit to enable BLE Buck to be in active state
9070                                                      when BLE Buck is enabled. Default behavior is to be in
9071                                                      active only when Burst or BLEH power on are requested.                    */
9072             uint32_t            : 24;
9073     } MISC_b;
9074   } ;
9075 
9076   union {
9077     __IOM uint32_t DEVPWREVENTEN;               /*!< (@ 0x00000028) This register controls which feature trigger
9078                                                                     will result in an event to the CPU. It includes
9079                                                                     all the power on status for the core domains,
9080                                                                     as well as the Burst event. If any bits
9081                                                                     are set, then if the domain is turned on,
9082                                                                     it will result in an event to the ARM core.                */
9083 
9084     struct {
9085       __IOM uint32_t MCULEVEN   : 1;            /*!< [0..0] Control MCUL power-on status event                                 */
9086       __IOM uint32_t MCUHEVEN   : 1;            /*!< [1..1] Control MCUH power-on status event                                 */
9087       __IOM uint32_t HCPAEVEN   : 1;            /*!< [2..2] Control HCPA power-on status event                                 */
9088       __IOM uint32_t HCPBEVEN   : 1;            /*!< [3..3] Control HCPB power-on status event                                 */
9089       __IOM uint32_t HCPCEVEN   : 1;            /*!< [4..4] Control HCPC power-on status event                                 */
9090       __IOM uint32_t ADCEVEN    : 1;            /*!< [5..5] Control ADC power-on status event                                  */
9091       __IOM uint32_t MSPIEVEN   : 1;            /*!< [6..6] Control MSPI power-on status event                                 */
9092       __IOM uint32_t PDMEVEN    : 1;            /*!< [7..7] Control PDM power-on status event                                  */
9093       __IOM uint32_t BLELEVEN   : 1;            /*!< [8..8] Control BLE power-on status event                                  */
9094             uint32_t            : 20;
9095       __IOM uint32_t BLEFEATUREEVEN : 1;        /*!< [29..29] Control BLEFEATURE status event                                  */
9096       __IOM uint32_t BURSTFEATUREEVEN : 1;      /*!< [30..30] Control BURSTFEATURE status event                                */
9097       __IOM uint32_t BURSTEVEN  : 1;            /*!< [31..31] Control BURST status event                                       */
9098     } DEVPWREVENTEN_b;
9099   } ;
9100 
9101   union {
9102     __IOM uint32_t MEMPWREVENTEN;               /*!< (@ 0x0000002C) This register controls which power enable for
9103                                                                     the memories will result in an event to
9104                                                                     the CPU. It includes all the power on status
9105                                                                     for the memory domains. If any bits are
9106                                                                     set, then if the domain is turned on, it
9107                                                                     will result in an event to the ARM core.                   */
9108 
9109     struct {
9110       __IOM uint32_t DTCMEN     : 3;            /*!< [2..0] Enable DTCM power-on status event                                  */
9111       __IOM uint32_t SRAMEN     : 10;           /*!< [12..3] Control SRAM power-on status event                                */
9112       __IOM uint32_t FLASH0EN   : 1;            /*!< [13..13] Control FLASH power-on status event                              */
9113       __IOM uint32_t FLASH1EN   : 1;            /*!< [14..14] Control FLASH power-on status event                              */
9114             uint32_t            : 15;
9115       __IOM uint32_t CACHEB0EN  : 1;            /*!< [30..30] Control CACHE BANK 0 power-on status event                       */
9116       __IOM uint32_t CACHEB2EN  : 1;            /*!< [31..31] Control CACHEB2 power-on status event                            */
9117     } MEMPWREVENTEN_b;
9118   } ;
9119 } PWRCTRL_Type;                                 /*!< Size = 48 (0x30)                                                          */
9120 
9121 
9122 
9123 /* =========================================================================================================================== */
9124 /* ================                                          RSTGEN                                           ================ */
9125 /* =========================================================================================================================== */
9126 
9127 
9128 /**
9129   * @brief MCU Reset Generator (RSTGEN)
9130   */
9131 
9132 typedef struct {                                /*!< (@ 0x40000000) RSTGEN Structure                                           */
9133 
9134   union {
9135     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) Reset configuration register. This controls the
9136                                                                     reset enables for brownout condition, and
9137                                                                     for the expiration of the watch dog timer.                 */
9138 
9139     struct {
9140       __IOM uint32_t BODHREN    : 1;            /*!< [0..0] Brown out high (2.1 V) reset enable.                               */
9141       __IOM uint32_t WDREN      : 1;            /*!< [1..1] Watchdog Timer Reset Enable. NOTE: The WDT module must
9142                                                      also be configured for WDT reset. This includes enabling
9143                                                      the RESEN bit in WDTCFG register in Watch dog timer block.                */
9144             uint32_t            : 30;
9145     } CFG_b;
9146   } ;
9147 
9148   union {
9149     __IOM uint32_t SWPOI;                       /*!< (@ 0x00000004) This is the software POI reset. writing the key
9150                                                                     value to this register will trigger a POI
9151                                                                     to the system. This will cause a reset to
9152                                                                     all blocks except for registers in clock
9153                                                                     gen, RTC and the STIMER.                                   */
9154 
9155     struct {
9156       __IOM uint32_t SWPOIKEY   : 8;            /*!< [7..0] 0x1B generates a software POI reset. This is a write-only
9157                                                      register. Reading from this register will yield only all
9158                                                      0's.                                                                      */
9159             uint32_t            : 24;
9160     } SWPOI_b;
9161   } ;
9162 
9163   union {
9164     __IOM uint32_t SWPOR;                       /*!< (@ 0x00000008) This is the software POR reset. Writing the key
9165                                                                     value to this register will trigger a POR
9166                                                                     to the system. This will cause a reset to
9167                                                                     all blocks except for registers in clock
9168                                                                     gen, RTC, power management unit, the STIMER,
9169                                                                     and the power management unit.                             */
9170 
9171     struct {
9172       __IOM uint32_t SWPORKEY   : 8;            /*!< [7..0] 0xD4 generates a software POR reset.                               */
9173             uint32_t            : 24;
9174     } SWPOR_b;
9175   } ;
9176   __IM  uint32_t  RESERVED[2];
9177 
9178   union {
9179     __IOM uint32_t TPIURST;                     /*!< (@ 0x00000014) This will trigger a reset for the TPIU unit.               */
9180 
9181     struct {
9182       __IOM uint32_t TPIURST    : 1;            /*!< [0..0] Static reset for the TPIU. Write to '1' to assert reset
9183                                                      to TPIU. Write to '0' to clear the reset.                                 */
9184             uint32_t            : 31;
9185     } TPIURST_b;
9186   } ;
9187   __IM  uint32_t  RESERVED1[122];
9188 
9189   union {
9190     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
9191                                                                     to generate the corresponding interrupt.                   */
9192 
9193     struct {
9194       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
9195                                                      BODH level.                                                               */
9196             uint32_t            : 31;
9197     } INTEN_b;
9198   } ;
9199 
9200   union {
9201     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
9202                                                                     cause of a recent interrupt.                               */
9203 
9204     struct {
9205       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
9206                                                      BODH level.                                                               */
9207             uint32_t            : 31;
9208     } INTSTAT_b;
9209   } ;
9210 
9211   union {
9212     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
9213                                                                     the interrupt status associated with that
9214                                                                     bit.                                                       */
9215 
9216     struct {
9217       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
9218                                                      BODH level.                                                               */
9219             uint32_t            : 31;
9220     } INTCLR_b;
9221   } ;
9222 
9223   union {
9224     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
9225                                                                     generate an interrupt from this module.
9226                                                                     (Generally used for testing purposes).                     */
9227 
9228     struct {
9229       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
9230                                                      BODH level.                                                               */
9231             uint32_t            : 31;
9232     } INTSET_b;
9233   } ;
9234   __IM  uint32_t  RESERVED2[67107708];
9235 
9236   union {
9237     __IOM uint32_t STAT;                        /*!< (@ 0x0FFFF000) This register contains the status for brownout
9238                                                                     events and the causes for resets.
9239                                                                     NOTE 1: All bits in this register, including
9240                                                                     reserved bits, are writable. Therefore care
9241                                                                     should be taken not to write this register.
9242                                                                     NOTE 2: This register does not retain its
9243                                                                     value across a core deep sleep cycle. Therefore
9244                                                                     applications needing to use this value after
9245                                                                     deep sleep must copy and save this register
9246                                                                     to SRAM before initiating the first deep
9247                                                                     sleep cycle.                                               */
9248 
9249     struct {
9250       __IOM uint32_t EXRSTAT    : 1;            /*!< [0..0] Reset was initiated by an External Reset (SBL).                    */
9251       __IOM uint32_t PORSTAT    : 1;            /*!< [1..1] Reset was initiated by a Power-On Reset (SBL).                     */
9252       __IOM uint32_t BORSTAT    : 1;            /*!< [2..2] Reset was initiated by a Brown-Out Reset (SBL).                    */
9253       __IOM uint32_t SWRSTAT    : 1;            /*!< [3..3] Reset was a initiated by SW POR or AIRCR Reset (SBL).              */
9254       __IOM uint32_t POIRSTAT   : 1;            /*!< [4..4] Reset was a initiated by Software POI Reset (SBL).                 */
9255       __IOM uint32_t DBGRSTAT   : 1;            /*!< [5..5] Reset was a initiated by Debugger Reset (SBL).                     */
9256       __IOM uint32_t WDRSTAT    : 1;            /*!< [6..6] Reset was initiated by a Watchdog Timer Reset (SBL).               */
9257       __IOM uint32_t BOUSTAT    : 1;            /*!< [7..7] An Unregulated Supply Brownout Event occurred (SBL).               */
9258       __IOM uint32_t BOCSTAT    : 1;            /*!< [8..8] A Core Regulator Brownout Event occurred (SBL).                    */
9259       __IOM uint32_t BOFSTAT    : 1;            /*!< [9..9] A Memory Regulator Brownout Event occurred (SBL).                  */
9260       __IOM uint32_t BOBSTAT    : 1;            /*!< [10..10] A BLE/Burst Regulator Brownout Event occurred (SBL).             */
9261             uint32_t            : 19;
9262       __IOM uint32_t FBOOT      : 1;            /*!< [30..30] Set if current boot was initiated by soft reset and
9263                                                      resulted in Fast Boot (SBL).                                              */
9264       __IOM uint32_t SBOOT      : 1;            /*!< [31..31] Set when booting securely (SBL).                                 */
9265     } STAT_b;
9266   } ;
9267 } RSTGEN_Type;                                  /*!< Size = 268431364 (0xffff004)                                              */
9268 
9269 
9270 
9271 /* =========================================================================================================================== */
9272 /* ================                                            RTC                                            ================ */
9273 /* =========================================================================================================================== */
9274 
9275 
9276 /**
9277   * @brief Real Time Clock (RTC)
9278   */
9279 
9280 typedef struct {                                /*!< (@ 0x40004200) RTC Structure                                              */
9281   __IM  uint32_t  RESERVED[16];
9282 
9283   union {
9284     __IOM uint32_t CTRLOW;                      /*!< (@ 0x00000040) This counter contains the values for hour, minutes,
9285                                                                     seconds and 100ths of a second Counter.                    */
9286 
9287     struct {
9288       __IOM uint32_t CTR100     : 8;            /*!< [7..0] 100ths of a second Counter                                         */
9289       __IOM uint32_t CTRSEC     : 7;            /*!< [14..8] Seconds Counter                                                   */
9290             uint32_t            : 1;
9291       __IOM uint32_t CTRMIN     : 7;            /*!< [22..16] Minutes Counter                                                  */
9292             uint32_t            : 1;
9293       __IOM uint32_t CTRHR      : 6;            /*!< [29..24] Hours Counter                                                    */
9294             uint32_t            : 2;
9295     } CTRLOW_b;
9296   } ;
9297 
9298   union {
9299     __IOM uint32_t CTRUP;                       /*!< (@ 0x00000044) This register contains the day, month and year
9300                                                                     information. It contains which day in the
9301                                                                     week, and the century as well. The information
9302                                                                     of the century can also be derived from
9303                                                                     the year information. The 31st bit contains
9304                                                                     the error bit. See description in the register
9305                                                                     bit for condition when error is triggered.                 */
9306 
9307     struct {
9308       __IOM uint32_t CTRDATE    : 6;            /*!< [5..0] Date Counter                                                       */
9309             uint32_t            : 2;
9310       __IOM uint32_t CTRMO      : 5;            /*!< [12..8] Months Counter                                                    */
9311             uint32_t            : 3;
9312       __IOM uint32_t CTRYR      : 8;            /*!< [23..16] Years Counter                                                    */
9313       __IOM uint32_t CTRWKDY    : 3;            /*!< [26..24] Weekdays Counter                                                 */
9314       __IOM uint32_t CB         : 1;            /*!< [27..27] Century Bit. This bit will be toggled when the Years
9315                                                      register rolls over from 99 to 00 if the CEB bit is a 1.
9316                                                      CB=0 assumes the century it 19xx or 21xx, and CB=1 assumes
9317                                                      it is 20xx for leap year calculations.                                    */
9318       __IOM uint32_t CEB        : 1;            /*!< [28..28] Century Enable Bit.                                              */
9319             uint32_t            : 2;
9320       __IOM uint32_t CTERR      : 1;            /*!< [31..31] Counter read error status. Error is triggered when
9321                                                      software reads the lower word of the counters, and fails
9322                                                      to read the upper counter within 1/100 second. This is
9323                                                      because when the lower counter is read, the upper counter
9324                                                      is held off from incrementing until it is read so that
9325                                                      the full time stamp can be read.                                          */
9326     } CTRUP_b;
9327   } ;
9328 
9329   union {
9330     __IOM uint32_t ALMLOW;                      /*!< (@ 0x00000048) This register is the Alarm settings for hours,
9331                                                                     minutes, second and 1/100th seconds settings.              */
9332 
9333     struct {
9334       __IOM uint32_t ALM100     : 8;            /*!< [7..0] 100ths of a second Alarm                                           */
9335       __IOM uint32_t ALMSEC     : 7;            /*!< [14..8] Seconds Alarm                                                     */
9336             uint32_t            : 1;
9337       __IOM uint32_t ALMMIN     : 7;            /*!< [22..16] Minutes Alarm                                                    */
9338             uint32_t            : 1;
9339       __IOM uint32_t ALMHR      : 6;            /*!< [29..24] Hours Alarm                                                      */
9340             uint32_t            : 2;
9341     } ALMLOW_b;
9342   } ;
9343 
9344   union {
9345     __IOM uint32_t ALMUP;                       /*!< (@ 0x0000004C) This register is the alarm settings for week,
9346                                                                     month and day.                                             */
9347 
9348     struct {
9349       __IOM uint32_t ALMDATE    : 6;            /*!< [5..0] Date Alarm                                                         */
9350             uint32_t            : 2;
9351       __IOM uint32_t ALMMO      : 5;            /*!< [12..8] Months Alarm                                                      */
9352             uint32_t            : 3;
9353       __IOM uint32_t ALMWKDY    : 3;            /*!< [18..16] Weekdays Alarm                                                   */
9354             uint32_t            : 13;
9355     } ALMUP_b;
9356   } ;
9357 
9358   union {
9359     __IOM uint32_t RTCCTL;                      /*!< (@ 0x00000050) This is the register control for the RTC module.
9360                                                                     It sets the 12 or 24 hours mode, enables
9361                                                                     counter writes and sets the alarm repeat
9362                                                                     interval.                                                  */
9363 
9364     struct {
9365       __IOM uint32_t WRTC       : 1;            /*!< [0..0] Counter write control                                              */
9366       __IOM uint32_t RPT        : 3;            /*!< [3..1] Alarm repeat interval                                              */
9367       __IOM uint32_t RSTOP      : 1;            /*!< [4..4] RTC input clock control                                            */
9368       __IOM uint32_t HR1224     : 1;            /*!< [5..5] Hours Counter mode                                                 */
9369             uint32_t            : 26;
9370     } RTCCTL_b;
9371   } ;
9372   __IM  uint32_t  RESERVED1[43];
9373 
9374   union {
9375     __IOM uint32_t INTEN;                       /*!< (@ 0x00000100) Set bits in this register to allow this module
9376                                                                     to generate the corresponding interrupt.                   */
9377 
9378     struct {
9379       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
9380             uint32_t            : 31;
9381     } INTEN_b;
9382   } ;
9383 
9384   union {
9385     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000104) Read bits from this register to discover the
9386                                                                     cause of a recent interrupt.                               */
9387 
9388     struct {
9389       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
9390             uint32_t            : 31;
9391     } INTSTAT_b;
9392   } ;
9393 
9394   union {
9395     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
9396                                                                     the interrupt status associated with that
9397                                                                     bit.                                                       */
9398 
9399     struct {
9400       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
9401             uint32_t            : 31;
9402     } INTCLR_b;
9403   } ;
9404 
9405   union {
9406     __IOM uint32_t INTSET;                      /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
9407                                                                     generate an interrupt from this module.
9408                                                                     (Generally used for testing purposes).                     */
9409 
9410     struct {
9411       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
9412             uint32_t            : 31;
9413     } INTSET_b;
9414   } ;
9415 } RTC_Type;                                     /*!< Size = 272 (0x110)                                                        */
9416 
9417 
9418 
9419 /* =========================================================================================================================== */
9420 /* ================                                           SCARD                                           ================ */
9421 /* =========================================================================================================================== */
9422 
9423 
9424 /**
9425   * @brief Serial ISO7816 (SCARD)
9426   */
9427 
9428 typedef struct {                                /*!< (@ 0x40080000) SCARD Structure                                            */
9429 
9430   union {
9431     __IOM uint32_t SR;                          /*!< (@ 0x00000000) ISO7816 interrupt status                                   */
9432 
9433     struct {
9434       __IOM uint32_t FNE        : 1;            /*!< [0..0] RX FIFO not empty.                                                 */
9435       __IOM uint32_t TBERBF     : 1;            /*!< [1..1] FIFO empty (transmit) or full (receive).                           */
9436       __IOM uint32_t FER        : 1;            /*!< [2..2] Framing error.                                                     */
9437       __IOM uint32_t OVR        : 1;            /*!< [3..3] RX FIFO overflow.                                                  */
9438       __IOM uint32_t PE         : 1;            /*!< [4..4] Parity Error.                                                      */
9439       __IOM uint32_t FT2REND    : 1;            /*!< [5..5] TX to RX finished.                                                 */
9440       __IOM uint32_t FHF        : 1;            /*!< [6..6] FIFO Half Full.                                                    */
9441             uint32_t            : 25;
9442     } SR_b;
9443   } ;
9444 
9445   union {
9446     __IOM uint32_t IER;                         /*!< (@ 0x00000004) ISO7816 interrupt enable                                   */
9447 
9448     struct {
9449       __IOM uint32_t FNEEN      : 1;            /*!< [0..0] RX FIFO not empty interrupt enable.                                */
9450       __IOM uint32_t TBERBFEN   : 1;            /*!< [1..1] FIFO empty (transmit) or full (receive) interrupt enable.          */
9451       __IOM uint32_t FEREN      : 1;            /*!< [2..2] Framing error interrupt enable.                                    */
9452       __IOM uint32_t OVREN      : 1;            /*!< [3..3] RX FIFOI overflow interrupt enable.                                */
9453       __IOM uint32_t PEEN       : 1;            /*!< [4..4] Parity Error interrupt enable.                                     */
9454       __IOM uint32_t FT2RENDEN  : 1;            /*!< [5..5] TX to RX finished interrupt enable.                                */
9455       __IOM uint32_t FHFEN      : 1;            /*!< [6..6] FIFO Half Full interrupt enable.                                   */
9456             uint32_t            : 25;
9457     } IER_b;
9458   } ;
9459 
9460   union {
9461     __IOM uint32_t TCR;                         /*!< (@ 0x00000008) ISO7816 transmit control                                   */
9462 
9463     struct {
9464       __IOM uint32_t CONV       : 1;            /*!< [0..0] Conversion inversion control.                                      */
9465       __IOM uint32_t SS         : 1;            /*!< [1..1] Use first byte to configure conversion.                            */
9466       __IOM uint32_t LCT        : 1;            /*!< [2..2] Fast TX to RX.                                                     */
9467       __IOM uint32_t TR         : 1;            /*!< [3..3] Transmit/receive mode.                                             */
9468       __IOM uint32_t PROT       : 1;            /*!< [4..4] PROT control.                                                      */
9469       __IOM uint32_t AUTOCONV   : 1;            /*!< [5..5] Automatic conversion.                                              */
9470       __IOM uint32_t FIP        : 1;            /*!< [6..6] Parity select.                                                     */
9471       __IOM uint32_t DMAMD      : 1;            /*!< [7..7] DMA direction.                                                     */
9472             uint32_t            : 24;
9473     } TCR_b;
9474   } ;
9475 
9476   union {
9477     __IOM uint32_t UCR;                         /*!< (@ 0x0000000C) ISO7816 user control                                       */
9478 
9479     struct {
9480       __IOM uint32_t CST        : 1;            /*!< [0..0] Clock control.                                                     */
9481       __IOM uint32_t RIU        : 1;            /*!< [1..1] ISO7816 reset. This bit is write-only.                             */
9482       __IOM uint32_t RSTIN      : 1;            /*!< [2..2] Reset polarity.                                                    */
9483       __IOM uint32_t RETXEN     : 1;            /*!< [3..3] Enable TX/RX time configuration.                                   */
9484             uint32_t            : 28;
9485     } UCR_b;
9486   } ;
9487 
9488   union {
9489     __IOM uint32_t DR;                          /*!< (@ 0x00000010) ISO7816 data                                               */
9490 
9491     struct {
9492       __IOM uint32_t DR         : 8;            /*!< [7..0] Data register.                                                     */
9493             uint32_t            : 24;
9494     } DR_b;
9495   } ;
9496 
9497   union {
9498     __IOM uint32_t BPRL;                        /*!< (@ 0x00000014) ISO7816 baud rate low                                      */
9499 
9500     struct {
9501       __IOM uint32_t BPRL       : 8;            /*!< [7..0] Baud rate low                                                      */
9502             uint32_t            : 24;
9503     } BPRL_b;
9504   } ;
9505 
9506   union {
9507     __IOM uint32_t BPRH;                        /*!< (@ 0x00000018) ISO7816 baud rate high                                     */
9508 
9509     struct {
9510       __IOM uint32_t BPRH       : 4;            /*!< [3..0] Baud rate high                                                     */
9511             uint32_t            : 28;
9512     } BPRH_b;
9513   } ;
9514 
9515   union {
9516     __IOM uint32_t UCR1;                        /*!< (@ 0x0000001C) ISO7816 user control 1                                     */
9517 
9518     struct {
9519       __IOM uint32_t PR         : 1;            /*!< [0..0] Query Card Detect.                                                 */
9520             uint32_t            : 1;
9521       __IOM uint32_t STSP       : 1;            /*!< [2..2] ETU counter control. This bit is write-only.                       */
9522       __IOM uint32_t T1PAREN    : 1;            /*!< [3..3] Parity check control.                                              */
9523       __IOM uint32_t CLKIOV     : 1;            /*!< [4..4] Output clock level.                                                */
9524       __IOM uint32_t ENLASTB    : 1;            /*!< [5..5] Enable last byte function.                                         */
9525             uint32_t            : 26;
9526     } UCR1_b;
9527   } ;
9528 
9529   union {
9530     __IOM uint32_t SR1;                         /*!< (@ 0x00000020) ISO7816 interrupt status 1                                 */
9531 
9532     struct {
9533       __IOM uint32_t ECNTOVER   : 1;            /*!< [0..0] ETU counter overflow.                                              */
9534       __IOM uint32_t PRL        : 1;            /*!< [1..1] Card insert/remove.                                                */
9535       __IOM uint32_t SYNCEND    : 1;            /*!< [2..2] Write complete synchronization.                                    */
9536       __IOM uint32_t IDLE       : 1;            /*!< [3..3] ISO7816 idle.                                                      */
9537             uint32_t            : 28;
9538     } SR1_b;
9539   } ;
9540 
9541   union {
9542     __IOM uint32_t IER1;                        /*!< (@ 0x00000024) ISO7816 interrupt enable 1                                 */
9543 
9544     struct {
9545       __IOM uint32_t ECNTOVEREN : 1;            /*!< [0..0] ETU counter overflow interrupt enable.                             */
9546       __IOM uint32_t PRLEN      : 1;            /*!< [1..1] Card insert/remove interrupt enable.                               */
9547       __IOM uint32_t SYNCENDEN  : 1;            /*!< [2..2] Write complete synchronization interrupt enable.                   */
9548             uint32_t            : 29;
9549     } IER1_b;
9550   } ;
9551 
9552   union {
9553     __IOM uint32_t ECNTL;                       /*!< (@ 0x00000028) ETU counter low                                            */
9554 
9555     struct {
9556       __IOM uint32_t ECNTL      : 8;            /*!< [7..0] ETU counter low register.                                          */
9557             uint32_t            : 24;
9558     } ECNTL_b;
9559   } ;
9560 
9561   union {
9562     __IOM uint32_t ECNTH;                       /*!< (@ 0x0000002C) ETU counter high                                           */
9563 
9564     struct {
9565       __IOM uint32_t ECNTH      : 8;            /*!< [7..0] ETU counter high register.                                         */
9566             uint32_t            : 24;
9567     } ECNTH_b;
9568   } ;
9569 
9570   union {
9571     __IOM uint32_t GTR;                         /*!< (@ 0x00000030) ISO7816 guard time configuration                           */
9572 
9573     struct {
9574       __IOM uint32_t GTR        : 8;            /*!< [7..0] Guard time configuration register.                                 */
9575             uint32_t            : 24;
9576     } GTR_b;
9577   } ;
9578 
9579   union {
9580     __IOM uint32_t RETXCNT;                     /*!< (@ 0x00000034) ISO7816 resend count                                       */
9581 
9582     struct {
9583       __IOM uint32_t RETXCNT    : 4;            /*!< [3..0] Resend count register.                                             */
9584             uint32_t            : 28;
9585     } RETXCNT_b;
9586   } ;
9587 
9588   union {
9589     __IOM uint32_t RETXCNTRMI;                  /*!< (@ 0x00000038) ISO7816 resent count inquiry                               */
9590 
9591     struct {
9592       __IOM uint32_t RETXCNTRMI : 4;            /*!< [3..0] Resent count inquiry register.                                     */
9593             uint32_t            : 28;
9594     } RETXCNTRMI_b;
9595   } ;
9596   __IM  uint32_t  RESERVED[49];
9597 
9598   union {
9599     __IOM uint32_t CLKCTRL;                     /*!< (@ 0x00000100) SCARD external clock control                               */
9600 
9601     struct {
9602       __IOM uint32_t CLKEN      : 1;            /*!< [0..0] Enable the serial source clock for SCARD.                          */
9603       __IOM uint32_t APBCLKEN   : 1;            /*!< [1..1] Enable the SCARD APB clock to run continuously.                    */
9604             uint32_t            : 30;
9605     } CLKCTRL_b;
9606   } ;
9607 } SCARD_Type;                                   /*!< Size = 260 (0x104)                                                        */
9608 
9609 
9610 
9611 /* =========================================================================================================================== */
9612 /* ================                                         SECURITY                                          ================ */
9613 /* =========================================================================================================================== */
9614 
9615 
9616 /**
9617   * @brief Security Interfaces (SECURITY)
9618   */
9619 
9620 typedef struct {                                /*!< (@ 0x40030000) SECURITY Structure                                         */
9621 
9622   union {
9623     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) Control                                                    */
9624 
9625     struct {
9626       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] Function Enable. Software should set the ENABLE bit to
9627                                                      initiate a CRC operation. Hardware will clear the ENABLE
9628                                                      bit upon completion.                                                      */
9629             uint32_t            : 3;
9630       __IOM uint32_t FUNCTION   : 4;            /*!< [7..4] Function Select                                                    */
9631             uint32_t            : 23;
9632       __IOM uint32_t CRCERROR   : 1;            /*!< [31..31] CRC Error Status - Set to 1 if an error occurs during
9633                                                      a CRC operation. Cleared when CTRL register is written
9634                                                      (with any value). Usually indicates an invalid address
9635                                                      range.                                                                    */
9636     } CTRL_b;
9637   } ;
9638   __IM  uint32_t  RESERVED[3];
9639 
9640   union {
9641     __IOM uint32_t SRCADDR;                     /*!< (@ 0x00000010) Source Address                                             */
9642 
9643     struct {
9644       __IOM uint32_t ADDR       : 32;           /*!< [31..0] Source Buffer Address. Address may be byte aligned,
9645                                                      but the length must be a multiple of 4 bits.                              */
9646     } SRCADDR_b;
9647   } ;
9648   __IM  uint32_t  RESERVED1[3];
9649 
9650   union {
9651     __IOM uint32_t LEN;                         /*!< (@ 0x00000020) Length                                                     */
9652 
9653     struct {
9654             uint32_t            : 2;
9655       __IOM uint32_t LEN        : 22;           /*!< [23..2] Buffer size (bottom two bits assumed to be zero to ensure
9656                                                      a multiple of 4 bytes)                                                    */
9657             uint32_t            : 8;
9658     } LEN_b;
9659   } ;
9660   __IM  uint32_t  RESERVED2[3];
9661 
9662   union {
9663     __IOM uint32_t RESULT;                      /*!< (@ 0x00000030) CRC Seed/Result                                            */
9664 
9665     struct {
9666       __IOM uint32_t CRC        : 32;           /*!< [31..0] CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF
9667                                                      before starting a CRC operation (unless the CRC is continued
9668                                                      from a previous operation).                                               */
9669     } RESULT_b;
9670   } ;
9671   __IM  uint32_t  RESERVED3[17];
9672 
9673   union {
9674     __IOM uint32_t LOCKCTRL;                    /*!< (@ 0x00000078) LOCK Control                                               */
9675 
9676     struct {
9677       __IOM uint32_t SELECT     : 8;            /*!< [7..0] LOCK Function Select register.                                     */
9678             uint32_t            : 24;
9679     } LOCKCTRL_b;
9680   } ;
9681 
9682   union {
9683     __IOM uint32_t LOCKSTAT;                    /*!< (@ 0x0000007C) LOCK Status                                                */
9684 
9685     struct {
9686       __IOM uint32_t STATUS     : 32;           /*!< [31..0] LOCK Status register. This register is a bit mask for
9687                                                      which resources are currently unlocked. These bits are
9688                                                      one-hot per resource.                                                     */
9689     } LOCKSTAT_b;
9690   } ;
9691 
9692   union {
9693     __IOM uint32_t KEY0;                        /*!< (@ 0x00000080) Key0                                                       */
9694 
9695     struct {
9696       __IOM uint32_t KEY0       : 32;           /*!< [31..0] Bits [31:0] of the 128-bit key should be written to
9697                                                      this register. To protect key values, the register always
9698                                                      returns 0x00000000.                                                       */
9699     } KEY0_b;
9700   } ;
9701 
9702   union {
9703     __IOM uint32_t KEY1;                        /*!< (@ 0x00000084) Key1                                                       */
9704 
9705     struct {
9706       __IOM uint32_t KEY1       : 32;           /*!< [31..0] Bits [63:32] of the 128-bit key should be written to
9707                                                      this register. To protect key values, the register always
9708                                                      returns 0x00000000.                                                       */
9709     } KEY1_b;
9710   } ;
9711 
9712   union {
9713     __IOM uint32_t KEY2;                        /*!< (@ 0x00000088) Key2                                                       */
9714 
9715     struct {
9716       __IOM uint32_t KEY2       : 32;           /*!< [31..0] Bits [95:64] of the 128-bit key should be written to
9717                                                      this register. To protect key values, the register always
9718                                                      returns 0x00000000.                                                       */
9719     } KEY2_b;
9720   } ;
9721 
9722   union {
9723     __IOM uint32_t KEY3;                        /*!< (@ 0x0000008C) Key3                                                       */
9724 
9725     struct {
9726       __IOM uint32_t KEY3       : 32;           /*!< [31..0] Bits [127:96] of the 128-bit key should be written to
9727                                                      this register. To protect key values, the register always
9728                                                      returns 0x00000000.                                                       */
9729     } KEY3_b;
9730   } ;
9731 } SECURITY_Type;                                /*!< Size = 144 (0x90)                                                         */
9732 
9733 
9734 
9735 /* =========================================================================================================================== */
9736 /* ================                                           UART0                                           ================ */
9737 /* =========================================================================================================================== */
9738 
9739 
9740 /**
9741   * @brief Serial UART (UART0)
9742   */
9743 
9744 typedef struct {                                /*!< (@ 0x4001C000) UART0 Structure                                            */
9745 
9746   union {
9747     __IOM uint32_t DR;                          /*!< (@ 0x00000000) UART Data                                                  */
9748 
9749     struct {
9750       __IOM uint32_t DATA       : 8;            /*!< [7..0] This is the UART data port.                                        */
9751       __IOM uint32_t FEDATA     : 1;            /*!< [8..8] This is the framing error indicator.                               */
9752       __IOM uint32_t PEDATA     : 1;            /*!< [9..9] This is the parity error indicator.                                */
9753       __IOM uint32_t BEDATA     : 1;            /*!< [10..10] This is the break error indicator.                               */
9754       __IOM uint32_t OEDATA     : 1;            /*!< [11..11] This is the overrun error indicator.                             */
9755             uint32_t            : 20;
9756     } DR_b;
9757   } ;
9758 
9759   union {
9760     __IOM uint32_t RSR;                         /*!< (@ 0x00000004) UART Status                                                */
9761 
9762     struct {
9763       __IOM uint32_t FESTAT     : 1;            /*!< [0..0] This is the framing error indicator.                               */
9764       __IOM uint32_t PESTAT     : 1;            /*!< [1..1] This is the parity error indicator.                                */
9765       __IOM uint32_t BESTAT     : 1;            /*!< [2..2] This is the break error indicator.                                 */
9766       __IOM uint32_t OESTAT     : 1;            /*!< [3..3] This is the overrun error indicator.                               */
9767             uint32_t            : 28;
9768     } RSR_b;
9769   } ;
9770   __IM  uint32_t  RESERVED[4];
9771 
9772   union {
9773     __IOM uint32_t FR;                          /*!< (@ 0x00000018) Flag                                                       */
9774 
9775     struct {
9776       __IOM uint32_t CTS        : 1;            /*!< [0..0] This bit holds the clear to send indicator.                        */
9777       __IOM uint32_t DSR        : 1;            /*!< [1..1] This bit holds the data set ready indicator.                       */
9778       __IOM uint32_t DCD        : 1;            /*!< [2..2] This bit holds the data carrier detect indicator.                  */
9779       __IOM uint32_t BUSY       : 1;            /*!< [3..3] This bit holds the busy indicator.                                 */
9780       __IOM uint32_t RXFE       : 1;            /*!< [4..4] This bit holds the receive FIFO empty indicator.                   */
9781       __IOM uint32_t TXFF       : 1;            /*!< [5..5] This bit holds the transmit FIFO full indicator.                   */
9782       __IOM uint32_t RXFF       : 1;            /*!< [6..6] This bit holds the receive FIFO full indicator.                    */
9783       __IOM uint32_t TXFE       : 1;            /*!< [7..7] This bit holds the transmit FIFO empty indicator.                  */
9784       __IOM uint32_t TXBUSY     : 1;            /*!< [8..8] This bit holds the transmit BUSY indicator.                        */
9785             uint32_t            : 23;
9786     } FR_b;
9787   } ;
9788   __IM  uint32_t  RESERVED1;
9789 
9790   union {
9791     __IOM uint32_t ILPR;                        /*!< (@ 0x00000020) IrDA Counter                                               */
9792 
9793     struct {
9794       __IOM uint32_t ILPDVSR    : 8;            /*!< [7..0] These bits hold the IrDA counter divisor.                          */
9795             uint32_t            : 24;
9796     } ILPR_b;
9797   } ;
9798 
9799   union {
9800     __IOM uint32_t IBRD;                        /*!< (@ 0x00000024) Integer Baud Rate Divisor                                  */
9801 
9802     struct {
9803       __IOM uint32_t DIVINT     : 16;           /*!< [15..0] These bits hold the baud integer divisor.                         */
9804             uint32_t            : 16;
9805     } IBRD_b;
9806   } ;
9807 
9808   union {
9809     __IOM uint32_t FBRD;                        /*!< (@ 0x00000028) Fractional Baud Rate Divisor                               */
9810 
9811     struct {
9812       __IOM uint32_t DIVFRAC    : 6;            /*!< [5..0] These bits hold the baud fractional divisor.                       */
9813             uint32_t            : 26;
9814     } FBRD_b;
9815   } ;
9816 
9817   union {
9818     __IOM uint32_t LCRH;                        /*!< (@ 0x0000002C) Line Control High                                          */
9819 
9820     struct {
9821       __IOM uint32_t BRK        : 1;            /*!< [0..0] This bit holds the break set.                                      */
9822       __IOM uint32_t PEN        : 1;            /*!< [1..1] This bit holds the parity enable.                                  */
9823       __IOM uint32_t EPS        : 1;            /*!< [2..2] This bit holds the even parity select.                             */
9824       __IOM uint32_t STP2       : 1;            /*!< [3..3] This bit holds the two stop bits select.                           */
9825       __IOM uint32_t FEN        : 1;            /*!< [4..4] This bit holds the FIFO enable.                                    */
9826       __IOM uint32_t WLEN       : 2;            /*!< [6..5] These bits hold the write length.                                  */
9827       __IOM uint32_t SPS        : 1;            /*!< [7..7] This bit holds the stick parity select.                            */
9828             uint32_t            : 24;
9829     } LCRH_b;
9830   } ;
9831 
9832   union {
9833     __IOM uint32_t CR;                          /*!< (@ 0x00000030) Control                                                    */
9834 
9835     struct {
9836       __IOM uint32_t UARTEN     : 1;            /*!< [0..0] This bit is the UART enable.                                       */
9837       __IOM uint32_t SIREN      : 1;            /*!< [1..1] This bit is the SIR ENDEC enable.                                  */
9838       __IOM uint32_t SIRLP      : 1;            /*!< [2..2] This bit is the SIR low power select.                              */
9839       __IOM uint32_t CLKEN      : 1;            /*!< [3..3] This bit is the UART clock enable.                                 */
9840       __IOM uint32_t CLKSEL     : 3;            /*!< [6..4] This bit field is the UART clock select.                           */
9841       __IOM uint32_t LBE        : 1;            /*!< [7..7] This bit is the loopback enable.                                   */
9842       __IOM uint32_t TXE        : 1;            /*!< [8..8] This bit is the transmit enable.                                   */
9843       __IOM uint32_t RXE        : 1;            /*!< [9..9] This bit is the receive enable.                                    */
9844       __IOM uint32_t DTR        : 1;            /*!< [10..10] This bit enables data transmit ready.                            */
9845       __IOM uint32_t RTS        : 1;            /*!< [11..11] This bit enables request to send.                                */
9846       __IOM uint32_t OUT1       : 1;            /*!< [12..12] This bit holds modem Out1.                                       */
9847       __IOM uint32_t OUT2       : 1;            /*!< [13..13] This bit holds modem Out2.                                       */
9848       __IOM uint32_t RTSEN      : 1;            /*!< [14..14] This bit enables RTS hardware flow control.                      */
9849       __IOM uint32_t CTSEN      : 1;            /*!< [15..15] This bit enables CTS hardware flow control.                      */
9850             uint32_t            : 16;
9851     } CR_b;
9852   } ;
9853 
9854   union {
9855     __IOM uint32_t IFLS;                        /*!< (@ 0x00000034) FIFO Interrupt Level Select                                */
9856 
9857     struct {
9858       __IOM uint32_t TXIFLSEL   : 3;            /*!< [2..0] These bits hold the transmit FIFO interrupt level.                 */
9859       __IOM uint32_t RXIFLSEL   : 3;            /*!< [5..3] These bits hold the receive FIFO interrupt level.                  */
9860             uint32_t            : 26;
9861     } IFLS_b;
9862   } ;
9863 
9864   union {
9865     __IOM uint32_t IER;                         /*!< (@ 0x00000038) Interrupt Enable                                           */
9866 
9867     struct {
9868       __IOM uint32_t TXCMPMIM   : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt enable.                   */
9869       __IOM uint32_t CTSMIM     : 1;            /*!< [1..1] This bit holds the modem CTS interrupt enable.                     */
9870       __IOM uint32_t DCDMIM     : 1;            /*!< [2..2] This bit holds the modem DCD interrupt enable.                     */
9871       __IOM uint32_t DSRMIM     : 1;            /*!< [3..3] This bit holds the modem DSR interrupt enable.                     */
9872       __IOM uint32_t RXIM       : 1;            /*!< [4..4] This bit holds the receive interrupt enable.                       */
9873       __IOM uint32_t TXIM       : 1;            /*!< [5..5] This bit holds the transmit interrupt enable.                      */
9874       __IOM uint32_t RTIM       : 1;            /*!< [6..6] This bit holds the receive timeout interrupt enable.               */
9875       __IOM uint32_t FEIM       : 1;            /*!< [7..7] This bit holds the framing error interrupt enable.                 */
9876       __IOM uint32_t PEIM       : 1;            /*!< [8..8] This bit holds the parity error interrupt enable.                  */
9877       __IOM uint32_t BEIM       : 1;            /*!< [9..9] This bit holds the break error interrupt enable.                   */
9878       __IOM uint32_t OEIM       : 1;            /*!< [10..10] This bit holds the overflow interrupt enable.                    */
9879             uint32_t            : 21;
9880     } IER_b;
9881   } ;
9882 
9883   union {
9884     __IOM uint32_t IES;                         /*!< (@ 0x0000003C) Interrupt Status                                           */
9885 
9886     struct {
9887       __IOM uint32_t TXCMPMRIS  : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt status.                   */
9888       __IOM uint32_t CTSMRIS    : 1;            /*!< [1..1] This bit holds the modem CTS interrupt status.                     */
9889       __IOM uint32_t DCDMRIS    : 1;            /*!< [2..2] This bit holds the modem DCD interrupt status.                     */
9890       __IOM uint32_t DSRMRIS    : 1;            /*!< [3..3] This bit holds the modem DSR interrupt status.                     */
9891       __IOM uint32_t RXRIS      : 1;            /*!< [4..4] This bit holds the receive interrupt status.                       */
9892       __IOM uint32_t TXRIS      : 1;            /*!< [5..5] This bit holds the transmit interrupt status.                      */
9893       __IOM uint32_t RTRIS      : 1;            /*!< [6..6] This bit holds the receive timeout interrupt status.               */
9894       __IOM uint32_t FERIS      : 1;            /*!< [7..7] This bit holds the framing error interrupt status.                 */
9895       __IOM uint32_t PERIS      : 1;            /*!< [8..8] This bit holds the parity error interrupt status.                  */
9896       __IOM uint32_t BERIS      : 1;            /*!< [9..9] This bit holds the break error interrupt status.                   */
9897       __IOM uint32_t OERIS      : 1;            /*!< [10..10] This bit holds the overflow interrupt status.                    */
9898             uint32_t            : 21;
9899     } IES_b;
9900   } ;
9901 
9902   union {
9903     __IOM uint32_t MIS;                         /*!< (@ 0x00000040) Masked Interrupt Status                                    */
9904 
9905     struct {
9906       __IOM uint32_t TXCMPMMIS  : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt status masked.            */
9907       __IOM uint32_t CTSMMIS    : 1;            /*!< [1..1] This bit holds the modem CTS interrupt status masked.              */
9908       __IOM uint32_t DCDMMIS    : 1;            /*!< [2..2] This bit holds the modem DCD interrupt status masked.              */
9909       __IOM uint32_t DSRMMIS    : 1;            /*!< [3..3] This bit holds the modem DSR interrupt status masked.              */
9910       __IOM uint32_t RXMIS      : 1;            /*!< [4..4] This bit holds the receive interrupt status masked.                */
9911       __IOM uint32_t TXMIS      : 1;            /*!< [5..5] This bit holds the transmit interrupt status masked.               */
9912       __IOM uint32_t RTMIS      : 1;            /*!< [6..6] This bit holds the receive timeout interrupt status masked.        */
9913       __IOM uint32_t FEMIS      : 1;            /*!< [7..7] This bit holds the framing error interrupt status masked.          */
9914       __IOM uint32_t PEMIS      : 1;            /*!< [8..8] This bit holds the parity error interrupt status masked.           */
9915       __IOM uint32_t BEMIS      : 1;            /*!< [9..9] This bit holds the break error interrupt status masked.            */
9916       __IOM uint32_t OEMIS      : 1;            /*!< [10..10] This bit holds the overflow interrupt status masked.             */
9917             uint32_t            : 21;
9918     } MIS_b;
9919   } ;
9920 
9921   union {
9922     __IOM uint32_t IEC;                         /*!< (@ 0x00000044) Interrupt Clear                                            */
9923 
9924     struct {
9925       __IOM uint32_t TXCMPMIC   : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt clear.                    */
9926       __IOM uint32_t CTSMIC     : 1;            /*!< [1..1] This bit holds the modem CTS interrupt clear.                      */
9927       __IOM uint32_t DCDMIC     : 1;            /*!< [2..2] This bit holds the modem DCD interrupt clear.                      */
9928       __IOM uint32_t DSRMIC     : 1;            /*!< [3..3] This bit holds the modem DSR interrupt clear.                      */
9929       __IOM uint32_t RXIC       : 1;            /*!< [4..4] This bit holds the receive interrupt clear.                        */
9930       __IOM uint32_t TXIC       : 1;            /*!< [5..5] This bit holds the transmit interrupt clear.                       */
9931       __IOM uint32_t RTIC       : 1;            /*!< [6..6] This bit holds the receive timeout interrupt clear.                */
9932       __IOM uint32_t FEIC       : 1;            /*!< [7..7] This bit holds the framing error interrupt clear.                  */
9933       __IOM uint32_t PEIC       : 1;            /*!< [8..8] This bit holds the parity error interrupt clear.                   */
9934       __IOM uint32_t BEIC       : 1;            /*!< [9..9] This bit holds the break error interrupt clear.                    */
9935       __IOM uint32_t OEIC       : 1;            /*!< [10..10] This bit holds the overflow interrupt clear.                     */
9936             uint32_t            : 21;
9937     } IEC_b;
9938   } ;
9939 } UART0_Type;                                   /*!< Size = 72 (0x48)                                                          */
9940 
9941 
9942 
9943 /* =========================================================================================================================== */
9944 /* ================                                           VCOMP                                           ================ */
9945 /* =========================================================================================================================== */
9946 
9947 
9948 /**
9949   * @brief Voltage Comparator (VCOMP)
9950   */
9951 
9952 typedef struct {                                /*!< (@ 0x4000C000) VCOMP Structure                                            */
9953 
9954   union {
9955     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The Voltage Comparator Configuration Register
9956                                                                     contains the software control for selecting
9957                                                                     between the 4 options for the positive input
9958                                                                     as well as the multiple options for the
9959                                                                     reference input.                                           */
9960 
9961     struct {
9962       __IOM uint32_t PSEL       : 2;            /*!< [1..0] This bit field selects the positive input to the comparator.       */
9963             uint32_t            : 6;
9964       __IOM uint32_t NSEL       : 2;            /*!< [9..8] This bit field selects the negative input to the comparator.       */
9965             uint32_t            : 6;
9966       __IOM uint32_t LVLSEL     : 4;            /*!< [19..16] When the reference input NSEL is set to NSEL_DAC, this
9967                                                      bit field selects the voltage level for the negative input
9968                                                      to the comparator.                                                        */
9969             uint32_t            : 12;
9970     } CFG_b;
9971   } ;
9972 
9973   union {
9974     __IOM uint32_t STAT;                        /*!< (@ 0x00000004) Status                                                     */
9975 
9976     struct {
9977       __IOM uint32_t CMPOUT     : 1;            /*!< [0..0] This bit is 1 if the positive input of the comparator
9978                                                      is greater than the negative input.                                       */
9979       __IOM uint32_t PWDSTAT    : 1;            /*!< [1..1] This bit indicates the power down state of the voltage
9980                                                      comparator.                                                               */
9981             uint32_t            : 30;
9982     } STAT_b;
9983   } ;
9984 
9985   union {
9986     __IOM uint32_t PWDKEY;                      /*!< (@ 0x00000008) Write a value of 0x37 to unlock, write any other
9987                                                                     value to lock. This register also indicates
9988                                                                     lock status when read. When in the unlocked
9989                                                                     state (i.e. 0x37 has been written), it reads
9990                                                                     as 1. When in the locked state, it reads
9991                                                                     as 0.                                                      */
9992 
9993     struct {
9994       __IOM uint32_t PWDKEY     : 32;           /*!< [31..0] Key register value.                                               */
9995     } PWDKEY_b;
9996   } ;
9997   __IM  uint32_t  RESERVED[125];
9998 
9999   union {
10000     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
10001                                                                     to generate the corresponding interrupt.                   */
10002 
10003     struct {
10004       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
10005       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
10006             uint32_t            : 30;
10007     } INTEN_b;
10008   } ;
10009 
10010   union {
10011     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
10012                                                                     cause of a recent interrupt.                               */
10013 
10014     struct {
10015       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
10016       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
10017             uint32_t            : 30;
10018     } INTSTAT_b;
10019   } ;
10020 
10021   union {
10022     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
10023                                                                     the interrupt status associated with that
10024                                                                     bit.                                                       */
10025 
10026     struct {
10027       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
10028       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
10029             uint32_t            : 30;
10030     } INTCLR_b;
10031   } ;
10032 
10033   union {
10034     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
10035                                                                     generate an interrupt from this module.
10036                                                                     (Generally used for testing purposes).                     */
10037 
10038     struct {
10039       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
10040       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
10041             uint32_t            : 30;
10042     } INTSET_b;
10043   } ;
10044 } VCOMP_Type;                                   /*!< Size = 528 (0x210)                                                        */
10045 
10046 
10047 
10048 /* =========================================================================================================================== */
10049 /* ================                                            WDT                                            ================ */
10050 /* =========================================================================================================================== */
10051 
10052 
10053 /**
10054   * @brief Watchdog Timer (WDT)
10055   */
10056 
10057 typedef struct {                                /*!< (@ 0x40024000) WDT Structure                                              */
10058 
10059   union {
10060     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) This is the configuration register for the watch
10061                                                                     dog timer. It controls the enable, interrupt
10062                                                                     set, clocks for the timer, the compare values
10063                                                                     for the counters to trigger a reset or interrupt.
10064                                                                     This register can only be written to if
10065                                                                     the watch dog timer is unlocked (WDTLOCK
10066                                                                     is not set).                                               */
10067 
10068     struct {
10069       __IOM uint32_t WDTEN      : 1;            /*!< [0..0] This bit field enables the WDT.                                    */
10070       __IOM uint32_t INTEN      : 1;            /*!< [1..1] This bit field enables the WDT interrupt. Note : This
10071                                                      bit must be set before the interrupt status bit will reflect
10072                                                      a watchdog timer expiration. The IER interrupt register
10073                                                      must also be enabled for a WDT interrupt to be sent to
10074                                                      the NVIC.                                                                 */
10075       __IOM uint32_t RESEN      : 1;            /*!< [2..2] This bit field enables the WDT reset. This needs to be
10076                                                      set together with the WDREN bit in REG_RSTGEN_CFG register
10077                                                      (in reset gen) to trigger the reset.                                      */
10078             uint32_t            : 5;
10079       __IOM uint32_t RESVAL     : 8;            /*!< [15..8] This bit field is the compare value for counter bits
10080                                                      7:0 to generate a watchdog reset. This will cause a software
10081                                                      reset.                                                                    */
10082       __IOM uint32_t INTVAL     : 8;            /*!< [23..16] This bit field is the compare value for counter bits
10083                                                      7:0 to generate a watchdog interrupt.                                     */
10084       __IOM uint32_t CLKSEL     : 3;            /*!< [26..24] Select the frequency for the WDT. All values not enumerated
10085                                                      below are undefined.                                                      */
10086             uint32_t            : 5;
10087     } CFG_b;
10088   } ;
10089 
10090   union {
10091     __IOM uint32_t RSTRT;                       /*!< (@ 0x00000004) This register will Restart the watchdog timer.
10092                                                                     Writing a special key value into this register
10093                                                                     will result in the watch dog timer being
10094                                                                     reset, so that the count will start again.
10095                                                                     It is expected that the software will periodically
10096                                                                     write to this register to indicate that
10097                                                                     the system is functional. The watch dog
10098                                                                     timer can continue running when the system
10099                                                                     is in deep sleep, and the interrupt will
10100                                                                     trigger the wake. After the wake, the core
10101                                                                     can reset the watch dog timer.                             */
10102 
10103     struct {
10104       __IOM uint32_t RSTRT      : 8;            /*!< [7..0] Writing 0xB2 to WDTRSTRT restarts the watchdog timer.
10105                                                      This is a write only register. Reading this register will
10106                                                      only provide all 0.                                                       */
10107             uint32_t            : 24;
10108     } RSTRT_b;
10109   } ;
10110 
10111   union {
10112     __IOM uint32_t LOCK;                        /*!< (@ 0x00000008) This register locks the watch dog timer. Once
10113                                                                     it is locked, the configuration register
10114                                                                     (WDTCFG) for watch dog timer cannot be written
10115                                                                     to.                                                        */
10116 
10117     struct {
10118       __IOM uint32_t LOCK       : 8;            /*!< [7..0] Writing 0x3A locks the watchdog timer. Once locked, the
10119                                                      WDTCFG reg cannot be written and WDTEN is set.                            */
10120             uint32_t            : 24;
10121     } LOCK_b;
10122   } ;
10123 
10124   union {
10125     __IOM uint32_t COUNT;                       /*!< (@ 0x0000000C) This register holds the current count for the
10126                                                                     watch dog timer. This is a read only register.
10127                                                                     SW cannot set the value in the counter,
10128                                                                     but can reset it.                                          */
10129 
10130     struct {
10131       __IOM uint32_t COUNT      : 8;            /*!< [7..0] Read-Only current value of the WDT counter                         */
10132             uint32_t            : 24;
10133     } COUNT_b;
10134   } ;
10135   __IM  uint32_t  RESERVED[124];
10136 
10137   union {
10138     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
10139                                                                     to generate the corresponding interrupt.                   */
10140 
10141     struct {
10142       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
10143             uint32_t            : 31;
10144     } INTEN_b;
10145   } ;
10146 
10147   union {
10148     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
10149                                                                     cause of a recent interrupt.                               */
10150 
10151     struct {
10152       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
10153             uint32_t            : 31;
10154     } INTSTAT_b;
10155   } ;
10156 
10157   union {
10158     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
10159                                                                     the interrupt status associated with that
10160                                                                     bit.                                                       */
10161 
10162     struct {
10163       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
10164             uint32_t            : 31;
10165     } INTCLR_b;
10166   } ;
10167 
10168   union {
10169     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
10170                                                                     generate an interrupt from this module.
10171                                                                     (Generally used for testing purposes).                     */
10172 
10173     struct {
10174       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
10175             uint32_t            : 31;
10176     } INTSET_b;
10177   } ;
10178 } WDT_Type;                                     /*!< Size = 528 (0x210)                                                        */
10179 
10180 
10181 /** @} */ /* End of group Device_Peripheral_peripherals */
10182 
10183 
10184 /* =========================================================================================================================== */
10185 /* ================                          Device Specific Peripheral Address Map                           ================ */
10186 /* =========================================================================================================================== */
10187 
10188 
10189 /** @addtogroup Device_Peripheral_peripheralAddr
10190   * @{
10191   */
10192 
10193 #define ADC_BASE                    0x50010000UL
10194 #define APBDMA_BASE                 0x40011000UL
10195 #define BLEIF_BASE                  0x5000C000UL
10196 #define CACHECTRL_BASE              0x40018000UL
10197 #define CLKGEN_BASE                 0x40004000UL
10198 #define CTIMER_BASE                 0x40008000UL
10199 #define GPIO_BASE                   0x40010000UL
10200 #define IOM0_BASE                   0x50004000UL
10201 #define IOM1_BASE                   0x50005000UL
10202 #define IOM2_BASE                   0x50006000UL
10203 #define IOM3_BASE                   0x50007000UL
10204 #define IOM4_BASE                   0x50008000UL
10205 #define IOM5_BASE                   0x50009000UL
10206 #define IOSLAVE_BASE                0x50000000UL
10207 #define MCUCTRL_BASE                0x40020000UL
10208 #define MSPI0_BASE                  0x50014000UL
10209 #define MSPI1_BASE                  0x50015000UL
10210 #define MSPI2_BASE                  0x50016000UL
10211 #define PDM_BASE                    0x50011000UL
10212 #define PWRCTRL_BASE                0x40021000UL
10213 #define RSTGEN_BASE                 0x40000000UL
10214 #define RTC_BASE                    0x40004200UL
10215 #define SCARD_BASE                  0x40080000UL
10216 #define SECURITY_BASE               0x40030000UL
10217 #define UART0_BASE                  0x4001C000UL
10218 #define UART1_BASE                  0x4001D000UL
10219 #define VCOMP_BASE                  0x4000C000UL
10220 #define WDT_BASE                    0x40024000UL
10221 
10222 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
10223 
10224 
10225 /* =========================================================================================================================== */
10226 /* ================                                  Peripheral declaration                                   ================ */
10227 /* =========================================================================================================================== */
10228 
10229 
10230 /** @addtogroup Device_Peripheral_declaration
10231   * @{
10232   */
10233 
10234 #define ADC                         ((ADC_Type*)               ADC_BASE)
10235 #define APBDMA                      ((APBDMA_Type*)            APBDMA_BASE)
10236 #define BLEIF                       ((BLEIF_Type*)             BLEIF_BASE)
10237 #define CACHECTRL                   ((CACHECTRL_Type*)         CACHECTRL_BASE)
10238 #define CLKGEN                      ((CLKGEN_Type*)            CLKGEN_BASE)
10239 #define CTIMER                      ((CTIMER_Type*)            CTIMER_BASE)
10240 #define GPIO                        ((GPIO_Type*)              GPIO_BASE)
10241 #define IOM0                        ((IOM0_Type*)              IOM0_BASE)
10242 #define IOM1                        ((IOM0_Type*)              IOM1_BASE)
10243 #define IOM2                        ((IOM0_Type*)              IOM2_BASE)
10244 #define IOM3                        ((IOM0_Type*)              IOM3_BASE)
10245 #define IOM4                        ((IOM0_Type*)              IOM4_BASE)
10246 #define IOM5                        ((IOM0_Type*)              IOM5_BASE)
10247 #define IOSLAVE                     ((IOSLAVE_Type*)           IOSLAVE_BASE)
10248 #define MCUCTRL                     ((MCUCTRL_Type*)           MCUCTRL_BASE)
10249 #define MSPI0                       ((MSPI0_Type*)             MSPI0_BASE)
10250 #define MSPI1                       ((MSPI0_Type*)             MSPI1_BASE)
10251 #define MSPI2                       ((MSPI0_Type*)             MSPI2_BASE)
10252 #define PDM                         ((PDM_Type*)               PDM_BASE)
10253 #define PWRCTRL                     ((PWRCTRL_Type*)           PWRCTRL_BASE)
10254 #define RSTGEN                      ((RSTGEN_Type*)            RSTGEN_BASE)
10255 #define RTC                         ((RTC_Type*)               RTC_BASE)
10256 #define SCARD                       ((SCARD_Type*)             SCARD_BASE)
10257 #define SECURITY                    ((SECURITY_Type*)          SECURITY_BASE)
10258 #define UART0                       ((UART0_Type*)             UART0_BASE)
10259 #define UART1                       ((UART0_Type*)             UART1_BASE)
10260 #define VCOMP                       ((VCOMP_Type*)             VCOMP_BASE)
10261 #define WDT                         ((WDT_Type*)               WDT_BASE)
10262 
10263 /** @} */ /* End of group Device_Peripheral_declaration */
10264 
10265 
10266 /* =========================================  End of section using anonymous unions  ========================================= */
10267 #if defined (__CC_ARM)
10268   #pragma pop
10269 #elif defined (__ICCARM__)
10270   /* leave anonymous unions enabled */
10271 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
10272   #pragma clang diagnostic pop
10273 #elif defined (__GNUC__)
10274   /* anonymous unions are enabled by default */
10275 #elif defined (__TMS470__)
10276   /* anonymous unions are enabled by default */
10277 #elif defined (__TASKING__)
10278   #pragma warning restore
10279 #elif defined (__CSMC__)
10280   /* anonymous unions are enabled by default */
10281 #endif
10282 
10283 
10284 /* =========================================================================================================================== */
10285 /* ================                                Pos/Mask Peripheral Section                                ================ */
10286 /* =========================================================================================================================== */
10287 
10288 
10289 /** @addtogroup PosMask_peripherals
10290   * @{
10291   */
10292 
10293 
10294 
10295 /* =========================================================================================================================== */
10296 /* ================                                            ADC                                            ================ */
10297 /* =========================================================================================================================== */
10298 
10299 /* ==========================================================  CFG  ========================================================== */
10300 #define ADC_CFG_CLKSEL_Pos                (24UL)                    /*!< CLKSEL (Bit 24)                                       */
10301 #define ADC_CFG_CLKSEL_Msk                (0x3000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
10302 #define ADC_CFG_TRIGPOL_Pos               (19UL)                    /*!< TRIGPOL (Bit 19)                                      */
10303 #define ADC_CFG_TRIGPOL_Msk               (0x80000UL)               /*!< TRIGPOL (Bitfield-Mask: 0x01)                         */
10304 #define ADC_CFG_TRIGSEL_Pos               (16UL)                    /*!< TRIGSEL (Bit 16)                                      */
10305 #define ADC_CFG_TRIGSEL_Msk               (0x70000UL)               /*!< TRIGSEL (Bitfield-Mask: 0x07)                         */
10306 #define ADC_CFG_DFIFORDEN_Pos             (12UL)                    /*!< DFIFORDEN (Bit 12)                                    */
10307 #define ADC_CFG_DFIFORDEN_Msk             (0x1000UL)                /*!< DFIFORDEN (Bitfield-Mask: 0x01)                       */
10308 #define ADC_CFG_REFSEL_Pos                (8UL)                     /*!< REFSEL (Bit 8)                                        */
10309 #define ADC_CFG_REFSEL_Msk                (0x300UL)                 /*!< REFSEL (Bitfield-Mask: 0x03)                          */
10310 #define ADC_CFG_CKMODE_Pos                (4UL)                     /*!< CKMODE (Bit 4)                                        */
10311 #define ADC_CFG_CKMODE_Msk                (0x10UL)                  /*!< CKMODE (Bitfield-Mask: 0x01)                          */
10312 #define ADC_CFG_LPMODE_Pos                (3UL)                     /*!< LPMODE (Bit 3)                                        */
10313 #define ADC_CFG_LPMODE_Msk                (0x8UL)                   /*!< LPMODE (Bitfield-Mask: 0x01)                          */
10314 #define ADC_CFG_RPTEN_Pos                 (2UL)                     /*!< RPTEN (Bit 2)                                         */
10315 #define ADC_CFG_RPTEN_Msk                 (0x4UL)                   /*!< RPTEN (Bitfield-Mask: 0x01)                           */
10316 #define ADC_CFG_ADCEN_Pos                 (0UL)                     /*!< ADCEN (Bit 0)                                         */
10317 #define ADC_CFG_ADCEN_Msk                 (0x1UL)                   /*!< ADCEN (Bitfield-Mask: 0x01)                           */
10318 /* =========================================================  STAT  ========================================================== */
10319 #define ADC_STAT_PWDSTAT_Pos              (0UL)                     /*!< PWDSTAT (Bit 0)                                       */
10320 #define ADC_STAT_PWDSTAT_Msk              (0x1UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
10321 /* ==========================================================  SWT  ========================================================== */
10322 #define ADC_SWT_SWT_Pos                   (0UL)                     /*!< SWT (Bit 0)                                           */
10323 #define ADC_SWT_SWT_Msk                   (0xffUL)                  /*!< SWT (Bitfield-Mask: 0xff)                             */
10324 /* ========================================================  SL0CFG  ========================================================= */
10325 #define ADC_SL0CFG_ADSEL0_Pos             (24UL)                    /*!< ADSEL0 (Bit 24)                                       */
10326 #define ADC_SL0CFG_ADSEL0_Msk             (0x7000000UL)             /*!< ADSEL0 (Bitfield-Mask: 0x07)                          */
10327 #define ADC_SL0CFG_PRMODE0_Pos            (16UL)                    /*!< PRMODE0 (Bit 16)                                      */
10328 #define ADC_SL0CFG_PRMODE0_Msk            (0x30000UL)               /*!< PRMODE0 (Bitfield-Mask: 0x03)                         */
10329 #define ADC_SL0CFG_CHSEL0_Pos             (8UL)                     /*!< CHSEL0 (Bit 8)                                        */
10330 #define ADC_SL0CFG_CHSEL0_Msk             (0xf00UL)                 /*!< CHSEL0 (Bitfield-Mask: 0x0f)                          */
10331 #define ADC_SL0CFG_WCEN0_Pos              (1UL)                     /*!< WCEN0 (Bit 1)                                         */
10332 #define ADC_SL0CFG_WCEN0_Msk              (0x2UL)                   /*!< WCEN0 (Bitfield-Mask: 0x01)                           */
10333 #define ADC_SL0CFG_SLEN0_Pos              (0UL)                     /*!< SLEN0 (Bit 0)                                         */
10334 #define ADC_SL0CFG_SLEN0_Msk              (0x1UL)                   /*!< SLEN0 (Bitfield-Mask: 0x01)                           */
10335 /* ========================================================  SL1CFG  ========================================================= */
10336 #define ADC_SL1CFG_ADSEL1_Pos             (24UL)                    /*!< ADSEL1 (Bit 24)                                       */
10337 #define ADC_SL1CFG_ADSEL1_Msk             (0x7000000UL)             /*!< ADSEL1 (Bitfield-Mask: 0x07)                          */
10338 #define ADC_SL1CFG_PRMODE1_Pos            (16UL)                    /*!< PRMODE1 (Bit 16)                                      */
10339 #define ADC_SL1CFG_PRMODE1_Msk            (0x30000UL)               /*!< PRMODE1 (Bitfield-Mask: 0x03)                         */
10340 #define ADC_SL1CFG_CHSEL1_Pos             (8UL)                     /*!< CHSEL1 (Bit 8)                                        */
10341 #define ADC_SL1CFG_CHSEL1_Msk             (0xf00UL)                 /*!< CHSEL1 (Bitfield-Mask: 0x0f)                          */
10342 #define ADC_SL1CFG_WCEN1_Pos              (1UL)                     /*!< WCEN1 (Bit 1)                                         */
10343 #define ADC_SL1CFG_WCEN1_Msk              (0x2UL)                   /*!< WCEN1 (Bitfield-Mask: 0x01)                           */
10344 #define ADC_SL1CFG_SLEN1_Pos              (0UL)                     /*!< SLEN1 (Bit 0)                                         */
10345 #define ADC_SL1CFG_SLEN1_Msk              (0x1UL)                   /*!< SLEN1 (Bitfield-Mask: 0x01)                           */
10346 /* ========================================================  SL2CFG  ========================================================= */
10347 #define ADC_SL2CFG_ADSEL2_Pos             (24UL)                    /*!< ADSEL2 (Bit 24)                                       */
10348 #define ADC_SL2CFG_ADSEL2_Msk             (0x7000000UL)             /*!< ADSEL2 (Bitfield-Mask: 0x07)                          */
10349 #define ADC_SL2CFG_PRMODE2_Pos            (16UL)                    /*!< PRMODE2 (Bit 16)                                      */
10350 #define ADC_SL2CFG_PRMODE2_Msk            (0x30000UL)               /*!< PRMODE2 (Bitfield-Mask: 0x03)                         */
10351 #define ADC_SL2CFG_CHSEL2_Pos             (8UL)                     /*!< CHSEL2 (Bit 8)                                        */
10352 #define ADC_SL2CFG_CHSEL2_Msk             (0xf00UL)                 /*!< CHSEL2 (Bitfield-Mask: 0x0f)                          */
10353 #define ADC_SL2CFG_WCEN2_Pos              (1UL)                     /*!< WCEN2 (Bit 1)                                         */
10354 #define ADC_SL2CFG_WCEN2_Msk              (0x2UL)                   /*!< WCEN2 (Bitfield-Mask: 0x01)                           */
10355 #define ADC_SL2CFG_SLEN2_Pos              (0UL)                     /*!< SLEN2 (Bit 0)                                         */
10356 #define ADC_SL2CFG_SLEN2_Msk              (0x1UL)                   /*!< SLEN2 (Bitfield-Mask: 0x01)                           */
10357 /* ========================================================  SL3CFG  ========================================================= */
10358 #define ADC_SL3CFG_ADSEL3_Pos             (24UL)                    /*!< ADSEL3 (Bit 24)                                       */
10359 #define ADC_SL3CFG_ADSEL3_Msk             (0x7000000UL)             /*!< ADSEL3 (Bitfield-Mask: 0x07)                          */
10360 #define ADC_SL3CFG_PRMODE3_Pos            (16UL)                    /*!< PRMODE3 (Bit 16)                                      */
10361 #define ADC_SL3CFG_PRMODE3_Msk            (0x30000UL)               /*!< PRMODE3 (Bitfield-Mask: 0x03)                         */
10362 #define ADC_SL3CFG_CHSEL3_Pos             (8UL)                     /*!< CHSEL3 (Bit 8)                                        */
10363 #define ADC_SL3CFG_CHSEL3_Msk             (0xf00UL)                 /*!< CHSEL3 (Bitfield-Mask: 0x0f)                          */
10364 #define ADC_SL3CFG_WCEN3_Pos              (1UL)                     /*!< WCEN3 (Bit 1)                                         */
10365 #define ADC_SL3CFG_WCEN3_Msk              (0x2UL)                   /*!< WCEN3 (Bitfield-Mask: 0x01)                           */
10366 #define ADC_SL3CFG_SLEN3_Pos              (0UL)                     /*!< SLEN3 (Bit 0)                                         */
10367 #define ADC_SL3CFG_SLEN3_Msk              (0x1UL)                   /*!< SLEN3 (Bitfield-Mask: 0x01)                           */
10368 /* ========================================================  SL4CFG  ========================================================= */
10369 #define ADC_SL4CFG_ADSEL4_Pos             (24UL)                    /*!< ADSEL4 (Bit 24)                                       */
10370 #define ADC_SL4CFG_ADSEL4_Msk             (0x7000000UL)             /*!< ADSEL4 (Bitfield-Mask: 0x07)                          */
10371 #define ADC_SL4CFG_PRMODE4_Pos            (16UL)                    /*!< PRMODE4 (Bit 16)                                      */
10372 #define ADC_SL4CFG_PRMODE4_Msk            (0x30000UL)               /*!< PRMODE4 (Bitfield-Mask: 0x03)                         */
10373 #define ADC_SL4CFG_CHSEL4_Pos             (8UL)                     /*!< CHSEL4 (Bit 8)                                        */
10374 #define ADC_SL4CFG_CHSEL4_Msk             (0xf00UL)                 /*!< CHSEL4 (Bitfield-Mask: 0x0f)                          */
10375 #define ADC_SL4CFG_WCEN4_Pos              (1UL)                     /*!< WCEN4 (Bit 1)                                         */
10376 #define ADC_SL4CFG_WCEN4_Msk              (0x2UL)                   /*!< WCEN4 (Bitfield-Mask: 0x01)                           */
10377 #define ADC_SL4CFG_SLEN4_Pos              (0UL)                     /*!< SLEN4 (Bit 0)                                         */
10378 #define ADC_SL4CFG_SLEN4_Msk              (0x1UL)                   /*!< SLEN4 (Bitfield-Mask: 0x01)                           */
10379 /* ========================================================  SL5CFG  ========================================================= */
10380 #define ADC_SL5CFG_ADSEL5_Pos             (24UL)                    /*!< ADSEL5 (Bit 24)                                       */
10381 #define ADC_SL5CFG_ADSEL5_Msk             (0x7000000UL)             /*!< ADSEL5 (Bitfield-Mask: 0x07)                          */
10382 #define ADC_SL5CFG_PRMODE5_Pos            (16UL)                    /*!< PRMODE5 (Bit 16)                                      */
10383 #define ADC_SL5CFG_PRMODE5_Msk            (0x30000UL)               /*!< PRMODE5 (Bitfield-Mask: 0x03)                         */
10384 #define ADC_SL5CFG_CHSEL5_Pos             (8UL)                     /*!< CHSEL5 (Bit 8)                                        */
10385 #define ADC_SL5CFG_CHSEL5_Msk             (0xf00UL)                 /*!< CHSEL5 (Bitfield-Mask: 0x0f)                          */
10386 #define ADC_SL5CFG_WCEN5_Pos              (1UL)                     /*!< WCEN5 (Bit 1)                                         */
10387 #define ADC_SL5CFG_WCEN5_Msk              (0x2UL)                   /*!< WCEN5 (Bitfield-Mask: 0x01)                           */
10388 #define ADC_SL5CFG_SLEN5_Pos              (0UL)                     /*!< SLEN5 (Bit 0)                                         */
10389 #define ADC_SL5CFG_SLEN5_Msk              (0x1UL)                   /*!< SLEN5 (Bitfield-Mask: 0x01)                           */
10390 /* ========================================================  SL6CFG  ========================================================= */
10391 #define ADC_SL6CFG_ADSEL6_Pos             (24UL)                    /*!< ADSEL6 (Bit 24)                                       */
10392 #define ADC_SL6CFG_ADSEL6_Msk             (0x7000000UL)             /*!< ADSEL6 (Bitfield-Mask: 0x07)                          */
10393 #define ADC_SL6CFG_PRMODE6_Pos            (16UL)                    /*!< PRMODE6 (Bit 16)                                      */
10394 #define ADC_SL6CFG_PRMODE6_Msk            (0x30000UL)               /*!< PRMODE6 (Bitfield-Mask: 0x03)                         */
10395 #define ADC_SL6CFG_CHSEL6_Pos             (8UL)                     /*!< CHSEL6 (Bit 8)                                        */
10396 #define ADC_SL6CFG_CHSEL6_Msk             (0xf00UL)                 /*!< CHSEL6 (Bitfield-Mask: 0x0f)                          */
10397 #define ADC_SL6CFG_WCEN6_Pos              (1UL)                     /*!< WCEN6 (Bit 1)                                         */
10398 #define ADC_SL6CFG_WCEN6_Msk              (0x2UL)                   /*!< WCEN6 (Bitfield-Mask: 0x01)                           */
10399 #define ADC_SL6CFG_SLEN6_Pos              (0UL)                     /*!< SLEN6 (Bit 0)                                         */
10400 #define ADC_SL6CFG_SLEN6_Msk              (0x1UL)                   /*!< SLEN6 (Bitfield-Mask: 0x01)                           */
10401 /* ========================================================  SL7CFG  ========================================================= */
10402 #define ADC_SL7CFG_ADSEL7_Pos             (24UL)                    /*!< ADSEL7 (Bit 24)                                       */
10403 #define ADC_SL7CFG_ADSEL7_Msk             (0x7000000UL)             /*!< ADSEL7 (Bitfield-Mask: 0x07)                          */
10404 #define ADC_SL7CFG_PRMODE7_Pos            (16UL)                    /*!< PRMODE7 (Bit 16)                                      */
10405 #define ADC_SL7CFG_PRMODE7_Msk            (0x30000UL)               /*!< PRMODE7 (Bitfield-Mask: 0x03)                         */
10406 #define ADC_SL7CFG_CHSEL7_Pos             (8UL)                     /*!< CHSEL7 (Bit 8)                                        */
10407 #define ADC_SL7CFG_CHSEL7_Msk             (0xf00UL)                 /*!< CHSEL7 (Bitfield-Mask: 0x0f)                          */
10408 #define ADC_SL7CFG_WCEN7_Pos              (1UL)                     /*!< WCEN7 (Bit 1)                                         */
10409 #define ADC_SL7CFG_WCEN7_Msk              (0x2UL)                   /*!< WCEN7 (Bitfield-Mask: 0x01)                           */
10410 #define ADC_SL7CFG_SLEN7_Pos              (0UL)                     /*!< SLEN7 (Bit 0)                                         */
10411 #define ADC_SL7CFG_SLEN7_Msk              (0x1UL)                   /*!< SLEN7 (Bitfield-Mask: 0x01)                           */
10412 /* =========================================================  WULIM  ========================================================= */
10413 #define ADC_WULIM_ULIM_Pos                (0UL)                     /*!< ULIM (Bit 0)                                          */
10414 #define ADC_WULIM_ULIM_Msk                (0xfffffUL)               /*!< ULIM (Bitfield-Mask: 0xfffff)                         */
10415 /* =========================================================  WLLIM  ========================================================= */
10416 #define ADC_WLLIM_LLIM_Pos                (0UL)                     /*!< LLIM (Bit 0)                                          */
10417 #define ADC_WLLIM_LLIM_Msk                (0xfffffUL)               /*!< LLIM (Bitfield-Mask: 0xfffff)                         */
10418 /* ========================================================  SCWLIM  ========================================================= */
10419 #define ADC_SCWLIM_SCWLIMEN_Pos           (0UL)                     /*!< SCWLIMEN (Bit 0)                                      */
10420 #define ADC_SCWLIM_SCWLIMEN_Msk           (0x1UL)                   /*!< SCWLIMEN (Bitfield-Mask: 0x01)                        */
10421 /* =========================================================  FIFO  ========================================================== */
10422 #define ADC_FIFO_RSVD_Pos                 (31UL)                    /*!< RSVD (Bit 31)                                         */
10423 #define ADC_FIFO_RSVD_Msk                 (0x80000000UL)            /*!< RSVD (Bitfield-Mask: 0x01)                            */
10424 #define ADC_FIFO_SLOTNUM_Pos              (28UL)                    /*!< SLOTNUM (Bit 28)                                      */
10425 #define ADC_FIFO_SLOTNUM_Msk              (0x70000000UL)            /*!< SLOTNUM (Bitfield-Mask: 0x07)                         */
10426 #define ADC_FIFO_COUNT_Pos                (20UL)                    /*!< COUNT (Bit 20)                                        */
10427 #define ADC_FIFO_COUNT_Msk                (0xff00000UL)             /*!< COUNT (Bitfield-Mask: 0xff)                           */
10428 #define ADC_FIFO_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
10429 #define ADC_FIFO_DATA_Msk                 (0xfffffUL)               /*!< DATA (Bitfield-Mask: 0xfffff)                         */
10430 /* ========================================================  FIFOPR  ========================================================= */
10431 #define ADC_FIFOPR_RSVDPR_Pos             (31UL)                    /*!< RSVDPR (Bit 31)                                       */
10432 #define ADC_FIFOPR_RSVDPR_Msk             (0x80000000UL)            /*!< RSVDPR (Bitfield-Mask: 0x01)                          */
10433 #define ADC_FIFOPR_SLOTNUMPR_Pos          (28UL)                    /*!< SLOTNUMPR (Bit 28)                                    */
10434 #define ADC_FIFOPR_SLOTNUMPR_Msk          (0x70000000UL)            /*!< SLOTNUMPR (Bitfield-Mask: 0x07)                       */
10435 #define ADC_FIFOPR_COUNT_Pos              (20UL)                    /*!< COUNT (Bit 20)                                        */
10436 #define ADC_FIFOPR_COUNT_Msk              (0xff00000UL)             /*!< COUNT (Bitfield-Mask: 0xff)                           */
10437 #define ADC_FIFOPR_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
10438 #define ADC_FIFOPR_DATA_Msk               (0xfffffUL)               /*!< DATA (Bitfield-Mask: 0xfffff)                         */
10439 /* =========================================================  INTEN  ========================================================= */
10440 #define ADC_INTEN_DERR_Pos                (7UL)                     /*!< DERR (Bit 7)                                          */
10441 #define ADC_INTEN_DERR_Msk                (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
10442 #define ADC_INTEN_DCMP_Pos                (6UL)                     /*!< DCMP (Bit 6)                                          */
10443 #define ADC_INTEN_DCMP_Msk                (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
10444 #define ADC_INTEN_WCINC_Pos               (5UL)                     /*!< WCINC (Bit 5)                                         */
10445 #define ADC_INTEN_WCINC_Msk               (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
10446 #define ADC_INTEN_WCEXC_Pos               (4UL)                     /*!< WCEXC (Bit 4)                                         */
10447 #define ADC_INTEN_WCEXC_Msk               (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
10448 #define ADC_INTEN_FIFOOVR2_Pos            (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
10449 #define ADC_INTEN_FIFOOVR2_Msk            (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
10450 #define ADC_INTEN_FIFOOVR1_Pos            (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
10451 #define ADC_INTEN_FIFOOVR1_Msk            (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
10452 #define ADC_INTEN_SCNCMP_Pos              (1UL)                     /*!< SCNCMP (Bit 1)                                        */
10453 #define ADC_INTEN_SCNCMP_Msk              (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
10454 #define ADC_INTEN_CNVCMP_Pos              (0UL)                     /*!< CNVCMP (Bit 0)                                        */
10455 #define ADC_INTEN_CNVCMP_Msk              (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
10456 /* ========================================================  INTSTAT  ======================================================== */
10457 #define ADC_INTSTAT_DERR_Pos              (7UL)                     /*!< DERR (Bit 7)                                          */
10458 #define ADC_INTSTAT_DERR_Msk              (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
10459 #define ADC_INTSTAT_DCMP_Pos              (6UL)                     /*!< DCMP (Bit 6)                                          */
10460 #define ADC_INTSTAT_DCMP_Msk              (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
10461 #define ADC_INTSTAT_WCINC_Pos             (5UL)                     /*!< WCINC (Bit 5)                                         */
10462 #define ADC_INTSTAT_WCINC_Msk             (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
10463 #define ADC_INTSTAT_WCEXC_Pos             (4UL)                     /*!< WCEXC (Bit 4)                                         */
10464 #define ADC_INTSTAT_WCEXC_Msk             (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
10465 #define ADC_INTSTAT_FIFOOVR2_Pos          (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
10466 #define ADC_INTSTAT_FIFOOVR2_Msk          (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
10467 #define ADC_INTSTAT_FIFOOVR1_Pos          (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
10468 #define ADC_INTSTAT_FIFOOVR1_Msk          (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
10469 #define ADC_INTSTAT_SCNCMP_Pos            (1UL)                     /*!< SCNCMP (Bit 1)                                        */
10470 #define ADC_INTSTAT_SCNCMP_Msk            (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
10471 #define ADC_INTSTAT_CNVCMP_Pos            (0UL)                     /*!< CNVCMP (Bit 0)                                        */
10472 #define ADC_INTSTAT_CNVCMP_Msk            (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
10473 /* ========================================================  INTCLR  ========================================================= */
10474 #define ADC_INTCLR_DERR_Pos               (7UL)                     /*!< DERR (Bit 7)                                          */
10475 #define ADC_INTCLR_DERR_Msk               (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
10476 #define ADC_INTCLR_DCMP_Pos               (6UL)                     /*!< DCMP (Bit 6)                                          */
10477 #define ADC_INTCLR_DCMP_Msk               (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
10478 #define ADC_INTCLR_WCINC_Pos              (5UL)                     /*!< WCINC (Bit 5)                                         */
10479 #define ADC_INTCLR_WCINC_Msk              (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
10480 #define ADC_INTCLR_WCEXC_Pos              (4UL)                     /*!< WCEXC (Bit 4)                                         */
10481 #define ADC_INTCLR_WCEXC_Msk              (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
10482 #define ADC_INTCLR_FIFOOVR2_Pos           (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
10483 #define ADC_INTCLR_FIFOOVR2_Msk           (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
10484 #define ADC_INTCLR_FIFOOVR1_Pos           (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
10485 #define ADC_INTCLR_FIFOOVR1_Msk           (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
10486 #define ADC_INTCLR_SCNCMP_Pos             (1UL)                     /*!< SCNCMP (Bit 1)                                        */
10487 #define ADC_INTCLR_SCNCMP_Msk             (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
10488 #define ADC_INTCLR_CNVCMP_Pos             (0UL)                     /*!< CNVCMP (Bit 0)                                        */
10489 #define ADC_INTCLR_CNVCMP_Msk             (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
10490 /* ========================================================  INTSET  ========================================================= */
10491 #define ADC_INTSET_DERR_Pos               (7UL)                     /*!< DERR (Bit 7)                                          */
10492 #define ADC_INTSET_DERR_Msk               (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
10493 #define ADC_INTSET_DCMP_Pos               (6UL)                     /*!< DCMP (Bit 6)                                          */
10494 #define ADC_INTSET_DCMP_Msk               (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
10495 #define ADC_INTSET_WCINC_Pos              (5UL)                     /*!< WCINC (Bit 5)                                         */
10496 #define ADC_INTSET_WCINC_Msk              (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
10497 #define ADC_INTSET_WCEXC_Pos              (4UL)                     /*!< WCEXC (Bit 4)                                         */
10498 #define ADC_INTSET_WCEXC_Msk              (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
10499 #define ADC_INTSET_FIFOOVR2_Pos           (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
10500 #define ADC_INTSET_FIFOOVR2_Msk           (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
10501 #define ADC_INTSET_FIFOOVR1_Pos           (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
10502 #define ADC_INTSET_FIFOOVR1_Msk           (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
10503 #define ADC_INTSET_SCNCMP_Pos             (1UL)                     /*!< SCNCMP (Bit 1)                                        */
10504 #define ADC_INTSET_SCNCMP_Msk             (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
10505 #define ADC_INTSET_CNVCMP_Pos             (0UL)                     /*!< CNVCMP (Bit 0)                                        */
10506 #define ADC_INTSET_CNVCMP_Msk             (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
10507 /* =======================================================  DMATRIGEN  ======================================================= */
10508 #define ADC_DMATRIGEN_DFIFOFULL_Pos       (1UL)                     /*!< DFIFOFULL (Bit 1)                                     */
10509 #define ADC_DMATRIGEN_DFIFOFULL_Msk       (0x2UL)                   /*!< DFIFOFULL (Bitfield-Mask: 0x01)                       */
10510 #define ADC_DMATRIGEN_DFIFO75_Pos         (0UL)                     /*!< DFIFO75 (Bit 0)                                       */
10511 #define ADC_DMATRIGEN_DFIFO75_Msk         (0x1UL)                   /*!< DFIFO75 (Bitfield-Mask: 0x01)                         */
10512 /* ======================================================  DMATRIGSTAT  ====================================================== */
10513 #define ADC_DMATRIGSTAT_DFULLSTAT_Pos     (1UL)                     /*!< DFULLSTAT (Bit 1)                                     */
10514 #define ADC_DMATRIGSTAT_DFULLSTAT_Msk     (0x2UL)                   /*!< DFULLSTAT (Bitfield-Mask: 0x01)                       */
10515 #define ADC_DMATRIGSTAT_D75STAT_Pos       (0UL)                     /*!< D75STAT (Bit 0)                                       */
10516 #define ADC_DMATRIGSTAT_D75STAT_Msk       (0x1UL)                   /*!< D75STAT (Bitfield-Mask: 0x01)                         */
10517 /* ========================================================  DMACFG  ========================================================= */
10518 #define ADC_DMACFG_DPWROFF_Pos            (18UL)                    /*!< DPWROFF (Bit 18)                                      */
10519 #define ADC_DMACFG_DPWROFF_Msk            (0x40000UL)               /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
10520 #define ADC_DMACFG_DMAMSK_Pos             (17UL)                    /*!< DMAMSK (Bit 17)                                       */
10521 #define ADC_DMACFG_DMAMSK_Msk             (0x20000UL)               /*!< DMAMSK (Bitfield-Mask: 0x01)                          */
10522 #define ADC_DMACFG_DMAHONSTAT_Pos         (16UL)                    /*!< DMAHONSTAT (Bit 16)                                   */
10523 #define ADC_DMACFG_DMAHONSTAT_Msk         (0x10000UL)               /*!< DMAHONSTAT (Bitfield-Mask: 0x01)                      */
10524 #define ADC_DMACFG_DMADYNPRI_Pos          (9UL)                     /*!< DMADYNPRI (Bit 9)                                     */
10525 #define ADC_DMACFG_DMADYNPRI_Msk          (0x200UL)                 /*!< DMADYNPRI (Bitfield-Mask: 0x01)                       */
10526 #define ADC_DMACFG_DMAPRI_Pos             (8UL)                     /*!< DMAPRI (Bit 8)                                        */
10527 #define ADC_DMACFG_DMAPRI_Msk             (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
10528 #define ADC_DMACFG_DMADIR_Pos             (2UL)                     /*!< DMADIR (Bit 2)                                        */
10529 #define ADC_DMACFG_DMADIR_Msk             (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
10530 #define ADC_DMACFG_DMAEN_Pos              (0UL)                     /*!< DMAEN (Bit 0)                                         */
10531 #define ADC_DMACFG_DMAEN_Msk              (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
10532 /* ======================================================  DMATOTCOUNT  ====================================================== */
10533 #define ADC_DMATOTCOUNT_TOTCOUNT_Pos      (2UL)                     /*!< TOTCOUNT (Bit 2)                                      */
10534 #define ADC_DMATOTCOUNT_TOTCOUNT_Msk      (0x3fffcUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xffff)                      */
10535 /* ======================================================  DMATARGADDR  ====================================================== */
10536 #define ADC_DMATARGADDR_UTARGADDR_Pos     (20UL)                    /*!< UTARGADDR (Bit 20)                                    */
10537 #define ADC_DMATARGADDR_UTARGADDR_Msk     (0xfff00000UL)            /*!< UTARGADDR (Bitfield-Mask: 0xfff)                      */
10538 #define ADC_DMATARGADDR_LTARGADDR_Pos     (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
10539 #define ADC_DMATARGADDR_LTARGADDR_Msk     (0xfffffUL)               /*!< LTARGADDR (Bitfield-Mask: 0xfffff)                    */
10540 /* ========================================================  DMASTAT  ======================================================== */
10541 #define ADC_DMASTAT_DMAERR_Pos            (2UL)                     /*!< DMAERR (Bit 2)                                        */
10542 #define ADC_DMASTAT_DMAERR_Msk            (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
10543 #define ADC_DMASTAT_DMACPL_Pos            (1UL)                     /*!< DMACPL (Bit 1)                                        */
10544 #define ADC_DMASTAT_DMACPL_Msk            (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
10545 #define ADC_DMASTAT_DMATIP_Pos            (0UL)                     /*!< DMATIP (Bit 0)                                        */
10546 #define ADC_DMASTAT_DMATIP_Msk            (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
10547 
10548 
10549 /* =========================================================================================================================== */
10550 /* ================                                          APBDMA                                           ================ */
10551 /* =========================================================================================================================== */
10552 
10553 /* ========================================================  BBVALUE  ======================================================== */
10554 #define APBDMA_BBVALUE_PIN_Pos            (16UL)                    /*!< PIN (Bit 16)                                          */
10555 #define APBDMA_BBVALUE_PIN_Msk            (0xff0000UL)              /*!< PIN (Bitfield-Mask: 0xff)                             */
10556 #define APBDMA_BBVALUE_DATAOUT_Pos        (0UL)                     /*!< DATAOUT (Bit 0)                                       */
10557 #define APBDMA_BBVALUE_DATAOUT_Msk        (0xffUL)                  /*!< DATAOUT (Bitfield-Mask: 0xff)                         */
10558 /* ======================================================  BBSETCLEAR  ======================================================= */
10559 #define APBDMA_BBSETCLEAR_CLEAR_Pos       (16UL)                    /*!< CLEAR (Bit 16)                                        */
10560 #define APBDMA_BBSETCLEAR_CLEAR_Msk       (0xff0000UL)              /*!< CLEAR (Bitfield-Mask: 0xff)                           */
10561 #define APBDMA_BBSETCLEAR_SET_Pos         (0UL)                     /*!< SET (Bit 0)                                           */
10562 #define APBDMA_BBSETCLEAR_SET_Msk         (0xffUL)                  /*!< SET (Bitfield-Mask: 0xff)                             */
10563 /* ========================================================  BBINPUT  ======================================================== */
10564 #define APBDMA_BBINPUT_DATAIN_Pos         (0UL)                     /*!< DATAIN (Bit 0)                                        */
10565 #define APBDMA_BBINPUT_DATAIN_Msk         (0xffUL)                  /*!< DATAIN (Bitfield-Mask: 0xff)                          */
10566 /* =======================================================  DEBUGDATA  ======================================================= */
10567 #define APBDMA_DEBUGDATA_DEBUGDATA_Pos    (0UL)                     /*!< DEBUGDATA (Bit 0)                                     */
10568 #define APBDMA_DEBUGDATA_DEBUGDATA_Msk    (0xffffffffUL)            /*!< DEBUGDATA (Bitfield-Mask: 0xffffffff)                 */
10569 /* =========================================================  DEBUG  ========================================================= */
10570 #define APBDMA_DEBUG_DEBUGEN_Pos          (0UL)                     /*!< DEBUGEN (Bit 0)                                       */
10571 #define APBDMA_DEBUG_DEBUGEN_Msk          (0xfUL)                   /*!< DEBUGEN (Bitfield-Mask: 0x0f)                         */
10572 
10573 
10574 /* =========================================================================================================================== */
10575 /* ================                                           BLEIF                                           ================ */
10576 /* =========================================================================================================================== */
10577 
10578 /* =========================================================  FIFO  ========================================================== */
10579 #define BLEIF_FIFO_FIFO_Pos               (0UL)                     /*!< FIFO (Bit 0)                                          */
10580 #define BLEIF_FIFO_FIFO_Msk               (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
10581 /* ========================================================  FIFOPTR  ======================================================== */
10582 #define BLEIF_FIFOPTR_FIFO1REM_Pos        (24UL)                    /*!< FIFO1REM (Bit 24)                                     */
10583 #define BLEIF_FIFOPTR_FIFO1REM_Msk        (0xff000000UL)            /*!< FIFO1REM (Bitfield-Mask: 0xff)                        */
10584 #define BLEIF_FIFOPTR_FIFO1SIZ_Pos        (16UL)                    /*!< FIFO1SIZ (Bit 16)                                     */
10585 #define BLEIF_FIFOPTR_FIFO1SIZ_Msk        (0xff0000UL)              /*!< FIFO1SIZ (Bitfield-Mask: 0xff)                        */
10586 #define BLEIF_FIFOPTR_FIFO0REM_Pos        (8UL)                     /*!< FIFO0REM (Bit 8)                                      */
10587 #define BLEIF_FIFOPTR_FIFO0REM_Msk        (0xff00UL)                /*!< FIFO0REM (Bitfield-Mask: 0xff)                        */
10588 #define BLEIF_FIFOPTR_FIFO0SIZ_Pos        (0UL)                     /*!< FIFO0SIZ (Bit 0)                                      */
10589 #define BLEIF_FIFOPTR_FIFO0SIZ_Msk        (0xffUL)                  /*!< FIFO0SIZ (Bitfield-Mask: 0xff)                        */
10590 /* ========================================================  FIFOTHR  ======================================================== */
10591 #define BLEIF_FIFOTHR_FIFOWTHR_Pos        (8UL)                     /*!< FIFOWTHR (Bit 8)                                      */
10592 #define BLEIF_FIFOTHR_FIFOWTHR_Msk        (0x3f00UL)                /*!< FIFOWTHR (Bitfield-Mask: 0x3f)                        */
10593 #define BLEIF_FIFOTHR_FIFORTHR_Pos        (0UL)                     /*!< FIFORTHR (Bit 0)                                      */
10594 #define BLEIF_FIFOTHR_FIFORTHR_Msk        (0x3fUL)                  /*!< FIFORTHR (Bitfield-Mask: 0x3f)                        */
10595 /* ========================================================  FIFOPOP  ======================================================== */
10596 #define BLEIF_FIFOPOP_FIFODOUT_Pos        (0UL)                     /*!< FIFODOUT (Bit 0)                                      */
10597 #define BLEIF_FIFOPOP_FIFODOUT_Msk        (0xffffffffUL)            /*!< FIFODOUT (Bitfield-Mask: 0xffffffff)                  */
10598 /* =======================================================  FIFOPUSH  ======================================================== */
10599 #define BLEIF_FIFOPUSH_FIFODIN_Pos        (0UL)                     /*!< FIFODIN (Bit 0)                                       */
10600 #define BLEIF_FIFOPUSH_FIFODIN_Msk        (0xffffffffUL)            /*!< FIFODIN (Bitfield-Mask: 0xffffffff)                   */
10601 /* =======================================================  FIFOCTRL  ======================================================== */
10602 #define BLEIF_FIFOCTRL_FIFORSTN_Pos       (1UL)                     /*!< FIFORSTN (Bit 1)                                      */
10603 #define BLEIF_FIFOCTRL_FIFORSTN_Msk       (0x2UL)                   /*!< FIFORSTN (Bitfield-Mask: 0x01)                        */
10604 #define BLEIF_FIFOCTRL_POPWR_Pos          (0UL)                     /*!< POPWR (Bit 0)                                         */
10605 #define BLEIF_FIFOCTRL_POPWR_Msk          (0x1UL)                   /*!< POPWR (Bitfield-Mask: 0x01)                           */
10606 /* ========================================================  FIFOLOC  ======================================================== */
10607 #define BLEIF_FIFOLOC_FIFORPTR_Pos        (8UL)                     /*!< FIFORPTR (Bit 8)                                      */
10608 #define BLEIF_FIFOLOC_FIFORPTR_Msk        (0xf00UL)                 /*!< FIFORPTR (Bitfield-Mask: 0x0f)                        */
10609 #define BLEIF_FIFOLOC_FIFOWPTR_Pos        (0UL)                     /*!< FIFOWPTR (Bit 0)                                      */
10610 #define BLEIF_FIFOLOC_FIFOWPTR_Msk        (0xfUL)                   /*!< FIFOWPTR (Bitfield-Mask: 0x0f)                        */
10611 /* ========================================================  CLKCFG  ========================================================= */
10612 #define BLEIF_CLKCFG_DIV3_Pos             (12UL)                    /*!< DIV3 (Bit 12)                                         */
10613 #define BLEIF_CLKCFG_DIV3_Msk             (0x1000UL)                /*!< DIV3 (Bitfield-Mask: 0x01)                            */
10614 #define BLEIF_CLKCFG_CLK32KEN_Pos         (11UL)                    /*!< CLK32KEN (Bit 11)                                     */
10615 #define BLEIF_CLKCFG_CLK32KEN_Msk         (0x800UL)                 /*!< CLK32KEN (Bitfield-Mask: 0x01)                        */
10616 #define BLEIF_CLKCFG_FSEL_Pos             (8UL)                     /*!< FSEL (Bit 8)                                          */
10617 #define BLEIF_CLKCFG_FSEL_Msk             (0x700UL)                 /*!< FSEL (Bitfield-Mask: 0x07)                            */
10618 #define BLEIF_CLKCFG_IOCLKEN_Pos          (0UL)                     /*!< IOCLKEN (Bit 0)                                       */
10619 #define BLEIF_CLKCFG_IOCLKEN_Msk          (0x1UL)                   /*!< IOCLKEN (Bitfield-Mask: 0x01)                         */
10620 /* ==========================================================  CMD  ========================================================== */
10621 #define BLEIF_CMD_OFFSETLO_Pos            (24UL)                    /*!< OFFSETLO (Bit 24)                                     */
10622 #define BLEIF_CMD_OFFSETLO_Msk            (0xff000000UL)            /*!< OFFSETLO (Bitfield-Mask: 0xff)                        */
10623 #define BLEIF_CMD_CMDSEL_Pos              (20UL)                    /*!< CMDSEL (Bit 20)                                       */
10624 #define BLEIF_CMD_CMDSEL_Msk              (0x300000UL)              /*!< CMDSEL (Bitfield-Mask: 0x03)                          */
10625 #define BLEIF_CMD_TSIZE_Pos               (8UL)                     /*!< TSIZE (Bit 8)                                         */
10626 #define BLEIF_CMD_TSIZE_Msk               (0xfff00UL)               /*!< TSIZE (Bitfield-Mask: 0xfff)                          */
10627 #define BLEIF_CMD_CONT_Pos                (7UL)                     /*!< CONT (Bit 7)                                          */
10628 #define BLEIF_CMD_CONT_Msk                (0x80UL)                  /*!< CONT (Bitfield-Mask: 0x01)                            */
10629 #define BLEIF_CMD_OFFSETCNT_Pos           (5UL)                     /*!< OFFSETCNT (Bit 5)                                     */
10630 #define BLEIF_CMD_OFFSETCNT_Msk           (0x60UL)                  /*!< OFFSETCNT (Bitfield-Mask: 0x03)                       */
10631 #define BLEIF_CMD_CMD_Pos                 (0UL)                     /*!< CMD (Bit 0)                                           */
10632 #define BLEIF_CMD_CMD_Msk                 (0x1fUL)                  /*!< CMD (Bitfield-Mask: 0x1f)                             */
10633 /* ========================================================  CMDRPT  ========================================================= */
10634 #define BLEIF_CMDRPT_CMDRPT_Pos           (0UL)                     /*!< CMDRPT (Bit 0)                                        */
10635 #define BLEIF_CMDRPT_CMDRPT_Msk           (0x1fUL)                  /*!< CMDRPT (Bitfield-Mask: 0x1f)                          */
10636 /* =======================================================  OFFSETHI  ======================================================== */
10637 #define BLEIF_OFFSETHI_OFFSETHI_Pos       (0UL)                     /*!< OFFSETHI (Bit 0)                                      */
10638 #define BLEIF_OFFSETHI_OFFSETHI_Msk       (0xffffUL)                /*!< OFFSETHI (Bitfield-Mask: 0xffff)                      */
10639 /* ========================================================  CMDSTAT  ======================================================== */
10640 #define BLEIF_CMDSTAT_CTSIZE_Pos          (8UL)                     /*!< CTSIZE (Bit 8)                                        */
10641 #define BLEIF_CMDSTAT_CTSIZE_Msk          (0xfff00UL)               /*!< CTSIZE (Bitfield-Mask: 0xfff)                         */
10642 #define BLEIF_CMDSTAT_CMDSTAT_Pos         (5UL)                     /*!< CMDSTAT (Bit 5)                                       */
10643 #define BLEIF_CMDSTAT_CMDSTAT_Msk         (0xe0UL)                  /*!< CMDSTAT (Bitfield-Mask: 0x07)                         */
10644 #define BLEIF_CMDSTAT_CCMD_Pos            (0UL)                     /*!< CCMD (Bit 0)                                          */
10645 #define BLEIF_CMDSTAT_CCMD_Msk            (0x1fUL)                  /*!< CCMD (Bitfield-Mask: 0x1f)                            */
10646 /* =========================================================  INTEN  ========================================================= */
10647 #define BLEIF_INTEN_B2MSHUTDN_Pos         (16UL)                    /*!< B2MSHUTDN (Bit 16)                                    */
10648 #define BLEIF_INTEN_B2MSHUTDN_Msk         (0x10000UL)               /*!< B2MSHUTDN (Bitfield-Mask: 0x01)                       */
10649 #define BLEIF_INTEN_B2MACTIVE_Pos         (15UL)                    /*!< B2MACTIVE (Bit 15)                                    */
10650 #define BLEIF_INTEN_B2MACTIVE_Msk         (0x8000UL)                /*!< B2MACTIVE (Bitfield-Mask: 0x01)                       */
10651 #define BLEIF_INTEN_B2MSLEEP_Pos          (14UL)                    /*!< B2MSLEEP (Bit 14)                                     */
10652 #define BLEIF_INTEN_B2MSLEEP_Msk          (0x4000UL)                /*!< B2MSLEEP (Bitfield-Mask: 0x01)                        */
10653 #define BLEIF_INTEN_CQERR_Pos             (13UL)                    /*!< CQERR (Bit 13)                                        */
10654 #define BLEIF_INTEN_CQERR_Msk             (0x2000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
10655 #define BLEIF_INTEN_CQUPD_Pos             (12UL)                    /*!< CQUPD (Bit 12)                                        */
10656 #define BLEIF_INTEN_CQUPD_Msk             (0x1000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
10657 #define BLEIF_INTEN_CQPAUSED_Pos          (11UL)                    /*!< CQPAUSED (Bit 11)                                     */
10658 #define BLEIF_INTEN_CQPAUSED_Msk          (0x800UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
10659 #define BLEIF_INTEN_DERR_Pos              (10UL)                    /*!< DERR (Bit 10)                                         */
10660 #define BLEIF_INTEN_DERR_Msk              (0x400UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
10661 #define BLEIF_INTEN_DCMP_Pos              (9UL)                     /*!< DCMP (Bit 9)                                          */
10662 #define BLEIF_INTEN_DCMP_Msk              (0x200UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
10663 #define BLEIF_INTEN_BLECSSTAT_Pos         (8UL)                     /*!< BLECSSTAT (Bit 8)                                     */
10664 #define BLEIF_INTEN_BLECSSTAT_Msk         (0x100UL)                 /*!< BLECSSTAT (Bitfield-Mask: 0x01)                       */
10665 #define BLEIF_INTEN_BLECIRQ_Pos           (7UL)                     /*!< BLECIRQ (Bit 7)                                       */
10666 #define BLEIF_INTEN_BLECIRQ_Msk           (0x80UL)                  /*!< BLECIRQ (Bitfield-Mask: 0x01)                         */
10667 #define BLEIF_INTEN_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
10668 #define BLEIF_INTEN_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
10669 #define BLEIF_INTEN_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
10670 #define BLEIF_INTEN_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
10671 #define BLEIF_INTEN_B2MST_Pos             (4UL)                     /*!< B2MST (Bit 4)                                         */
10672 #define BLEIF_INTEN_B2MST_Msk             (0x10UL)                  /*!< B2MST (Bitfield-Mask: 0x01)                           */
10673 #define BLEIF_INTEN_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
10674 #define BLEIF_INTEN_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
10675 #define BLEIF_INTEN_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
10676 #define BLEIF_INTEN_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
10677 #define BLEIF_INTEN_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
10678 #define BLEIF_INTEN_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
10679 #define BLEIF_INTEN_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
10680 #define BLEIF_INTEN_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
10681 /* ========================================================  INTSTAT  ======================================================== */
10682 #define BLEIF_INTSTAT_B2MSHUTDN_Pos       (16UL)                    /*!< B2MSHUTDN (Bit 16)                                    */
10683 #define BLEIF_INTSTAT_B2MSHUTDN_Msk       (0x10000UL)               /*!< B2MSHUTDN (Bitfield-Mask: 0x01)                       */
10684 #define BLEIF_INTSTAT_B2MACTIVE_Pos       (15UL)                    /*!< B2MACTIVE (Bit 15)                                    */
10685 #define BLEIF_INTSTAT_B2MACTIVE_Msk       (0x8000UL)                /*!< B2MACTIVE (Bitfield-Mask: 0x01)                       */
10686 #define BLEIF_INTSTAT_B2MSLEEP_Pos        (14UL)                    /*!< B2MSLEEP (Bit 14)                                     */
10687 #define BLEIF_INTSTAT_B2MSLEEP_Msk        (0x4000UL)                /*!< B2MSLEEP (Bitfield-Mask: 0x01)                        */
10688 #define BLEIF_INTSTAT_CQERR_Pos           (13UL)                    /*!< CQERR (Bit 13)                                        */
10689 #define BLEIF_INTSTAT_CQERR_Msk           (0x2000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
10690 #define BLEIF_INTSTAT_CQUPD_Pos           (12UL)                    /*!< CQUPD (Bit 12)                                        */
10691 #define BLEIF_INTSTAT_CQUPD_Msk           (0x1000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
10692 #define BLEIF_INTSTAT_CQPAUSED_Pos        (11UL)                    /*!< CQPAUSED (Bit 11)                                     */
10693 #define BLEIF_INTSTAT_CQPAUSED_Msk        (0x800UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
10694 #define BLEIF_INTSTAT_DERR_Pos            (10UL)                    /*!< DERR (Bit 10)                                         */
10695 #define BLEIF_INTSTAT_DERR_Msk            (0x400UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
10696 #define BLEIF_INTSTAT_DCMP_Pos            (9UL)                     /*!< DCMP (Bit 9)                                          */
10697 #define BLEIF_INTSTAT_DCMP_Msk            (0x200UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
10698 #define BLEIF_INTSTAT_BLECSSTAT_Pos       (8UL)                     /*!< BLECSSTAT (Bit 8)                                     */
10699 #define BLEIF_INTSTAT_BLECSSTAT_Msk       (0x100UL)                 /*!< BLECSSTAT (Bitfield-Mask: 0x01)                       */
10700 #define BLEIF_INTSTAT_BLECIRQ_Pos         (7UL)                     /*!< BLECIRQ (Bit 7)                                       */
10701 #define BLEIF_INTSTAT_BLECIRQ_Msk         (0x80UL)                  /*!< BLECIRQ (Bitfield-Mask: 0x01)                         */
10702 #define BLEIF_INTSTAT_ICMD_Pos            (6UL)                     /*!< ICMD (Bit 6)                                          */
10703 #define BLEIF_INTSTAT_ICMD_Msk            (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
10704 #define BLEIF_INTSTAT_IACC_Pos            (5UL)                     /*!< IACC (Bit 5)                                          */
10705 #define BLEIF_INTSTAT_IACC_Msk            (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
10706 #define BLEIF_INTSTAT_B2MST_Pos           (4UL)                     /*!< B2MST (Bit 4)                                         */
10707 #define BLEIF_INTSTAT_B2MST_Msk           (0x10UL)                  /*!< B2MST (Bitfield-Mask: 0x01)                           */
10708 #define BLEIF_INTSTAT_FOVFL_Pos           (3UL)                     /*!< FOVFL (Bit 3)                                         */
10709 #define BLEIF_INTSTAT_FOVFL_Msk           (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
10710 #define BLEIF_INTSTAT_FUNDFL_Pos          (2UL)                     /*!< FUNDFL (Bit 2)                                        */
10711 #define BLEIF_INTSTAT_FUNDFL_Msk          (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
10712 #define BLEIF_INTSTAT_THR_Pos             (1UL)                     /*!< THR (Bit 1)                                           */
10713 #define BLEIF_INTSTAT_THR_Msk             (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
10714 #define BLEIF_INTSTAT_CMDCMP_Pos          (0UL)                     /*!< CMDCMP (Bit 0)                                        */
10715 #define BLEIF_INTSTAT_CMDCMP_Msk          (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
10716 /* ========================================================  INTCLR  ========================================================= */
10717 #define BLEIF_INTCLR_B2MSHUTDN_Pos        (16UL)                    /*!< B2MSHUTDN (Bit 16)                                    */
10718 #define BLEIF_INTCLR_B2MSHUTDN_Msk        (0x10000UL)               /*!< B2MSHUTDN (Bitfield-Mask: 0x01)                       */
10719 #define BLEIF_INTCLR_B2MACTIVE_Pos        (15UL)                    /*!< B2MACTIVE (Bit 15)                                    */
10720 #define BLEIF_INTCLR_B2MACTIVE_Msk        (0x8000UL)                /*!< B2MACTIVE (Bitfield-Mask: 0x01)                       */
10721 #define BLEIF_INTCLR_B2MSLEEP_Pos         (14UL)                    /*!< B2MSLEEP (Bit 14)                                     */
10722 #define BLEIF_INTCLR_B2MSLEEP_Msk         (0x4000UL)                /*!< B2MSLEEP (Bitfield-Mask: 0x01)                        */
10723 #define BLEIF_INTCLR_CQERR_Pos            (13UL)                    /*!< CQERR (Bit 13)                                        */
10724 #define BLEIF_INTCLR_CQERR_Msk            (0x2000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
10725 #define BLEIF_INTCLR_CQUPD_Pos            (12UL)                    /*!< CQUPD (Bit 12)                                        */
10726 #define BLEIF_INTCLR_CQUPD_Msk            (0x1000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
10727 #define BLEIF_INTCLR_CQPAUSED_Pos         (11UL)                    /*!< CQPAUSED (Bit 11)                                     */
10728 #define BLEIF_INTCLR_CQPAUSED_Msk         (0x800UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
10729 #define BLEIF_INTCLR_DERR_Pos             (10UL)                    /*!< DERR (Bit 10)                                         */
10730 #define BLEIF_INTCLR_DERR_Msk             (0x400UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
10731 #define BLEIF_INTCLR_DCMP_Pos             (9UL)                     /*!< DCMP (Bit 9)                                          */
10732 #define BLEIF_INTCLR_DCMP_Msk             (0x200UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
10733 #define BLEIF_INTCLR_BLECSSTAT_Pos        (8UL)                     /*!< BLECSSTAT (Bit 8)                                     */
10734 #define BLEIF_INTCLR_BLECSSTAT_Msk        (0x100UL)                 /*!< BLECSSTAT (Bitfield-Mask: 0x01)                       */
10735 #define BLEIF_INTCLR_BLECIRQ_Pos          (7UL)                     /*!< BLECIRQ (Bit 7)                                       */
10736 #define BLEIF_INTCLR_BLECIRQ_Msk          (0x80UL)                  /*!< BLECIRQ (Bitfield-Mask: 0x01)                         */
10737 #define BLEIF_INTCLR_ICMD_Pos             (6UL)                     /*!< ICMD (Bit 6)                                          */
10738 #define BLEIF_INTCLR_ICMD_Msk             (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
10739 #define BLEIF_INTCLR_IACC_Pos             (5UL)                     /*!< IACC (Bit 5)                                          */
10740 #define BLEIF_INTCLR_IACC_Msk             (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
10741 #define BLEIF_INTCLR_B2MST_Pos            (4UL)                     /*!< B2MST (Bit 4)                                         */
10742 #define BLEIF_INTCLR_B2MST_Msk            (0x10UL)                  /*!< B2MST (Bitfield-Mask: 0x01)                           */
10743 #define BLEIF_INTCLR_FOVFL_Pos            (3UL)                     /*!< FOVFL (Bit 3)                                         */
10744 #define BLEIF_INTCLR_FOVFL_Msk            (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
10745 #define BLEIF_INTCLR_FUNDFL_Pos           (2UL)                     /*!< FUNDFL (Bit 2)                                        */
10746 #define BLEIF_INTCLR_FUNDFL_Msk           (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
10747 #define BLEIF_INTCLR_THR_Pos              (1UL)                     /*!< THR (Bit 1)                                           */
10748 #define BLEIF_INTCLR_THR_Msk              (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
10749 #define BLEIF_INTCLR_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
10750 #define BLEIF_INTCLR_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
10751 /* ========================================================  INTSET  ========================================================= */
10752 #define BLEIF_INTSET_B2MSHUTDN_Pos        (16UL)                    /*!< B2MSHUTDN (Bit 16)                                    */
10753 #define BLEIF_INTSET_B2MSHUTDN_Msk        (0x10000UL)               /*!< B2MSHUTDN (Bitfield-Mask: 0x01)                       */
10754 #define BLEIF_INTSET_B2MACTIVE_Pos        (15UL)                    /*!< B2MACTIVE (Bit 15)                                    */
10755 #define BLEIF_INTSET_B2MACTIVE_Msk        (0x8000UL)                /*!< B2MACTIVE (Bitfield-Mask: 0x01)                       */
10756 #define BLEIF_INTSET_B2MSLEEP_Pos         (14UL)                    /*!< B2MSLEEP (Bit 14)                                     */
10757 #define BLEIF_INTSET_B2MSLEEP_Msk         (0x4000UL)                /*!< B2MSLEEP (Bitfield-Mask: 0x01)                        */
10758 #define BLEIF_INTSET_CQERR_Pos            (13UL)                    /*!< CQERR (Bit 13)                                        */
10759 #define BLEIF_INTSET_CQERR_Msk            (0x2000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
10760 #define BLEIF_INTSET_CQUPD_Pos            (12UL)                    /*!< CQUPD (Bit 12)                                        */
10761 #define BLEIF_INTSET_CQUPD_Msk            (0x1000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
10762 #define BLEIF_INTSET_CQPAUSED_Pos         (11UL)                    /*!< CQPAUSED (Bit 11)                                     */
10763 #define BLEIF_INTSET_CQPAUSED_Msk         (0x800UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
10764 #define BLEIF_INTSET_DERR_Pos             (10UL)                    /*!< DERR (Bit 10)                                         */
10765 #define BLEIF_INTSET_DERR_Msk             (0x400UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
10766 #define BLEIF_INTSET_DCMP_Pos             (9UL)                     /*!< DCMP (Bit 9)                                          */
10767 #define BLEIF_INTSET_DCMP_Msk             (0x200UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
10768 #define BLEIF_INTSET_BLECSSTAT_Pos        (8UL)                     /*!< BLECSSTAT (Bit 8)                                     */
10769 #define BLEIF_INTSET_BLECSSTAT_Msk        (0x100UL)                 /*!< BLECSSTAT (Bitfield-Mask: 0x01)                       */
10770 #define BLEIF_INTSET_BLECIRQ_Pos          (7UL)                     /*!< BLECIRQ (Bit 7)                                       */
10771 #define BLEIF_INTSET_BLECIRQ_Msk          (0x80UL)                  /*!< BLECIRQ (Bitfield-Mask: 0x01)                         */
10772 #define BLEIF_INTSET_ICMD_Pos             (6UL)                     /*!< ICMD (Bit 6)                                          */
10773 #define BLEIF_INTSET_ICMD_Msk             (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
10774 #define BLEIF_INTSET_IACC_Pos             (5UL)                     /*!< IACC (Bit 5)                                          */
10775 #define BLEIF_INTSET_IACC_Msk             (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
10776 #define BLEIF_INTSET_B2MST_Pos            (4UL)                     /*!< B2MST (Bit 4)                                         */
10777 #define BLEIF_INTSET_B2MST_Msk            (0x10UL)                  /*!< B2MST (Bitfield-Mask: 0x01)                           */
10778 #define BLEIF_INTSET_FOVFL_Pos            (3UL)                     /*!< FOVFL (Bit 3)                                         */
10779 #define BLEIF_INTSET_FOVFL_Msk            (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
10780 #define BLEIF_INTSET_FUNDFL_Pos           (2UL)                     /*!< FUNDFL (Bit 2)                                        */
10781 #define BLEIF_INTSET_FUNDFL_Msk           (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
10782 #define BLEIF_INTSET_THR_Pos              (1UL)                     /*!< THR (Bit 1)                                           */
10783 #define BLEIF_INTSET_THR_Msk              (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
10784 #define BLEIF_INTSET_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
10785 #define BLEIF_INTSET_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
10786 /* =======================================================  DMATRIGEN  ======================================================= */
10787 #define BLEIF_DMATRIGEN_DTHREN_Pos        (1UL)                     /*!< DTHREN (Bit 1)                                        */
10788 #define BLEIF_DMATRIGEN_DTHREN_Msk        (0x2UL)                   /*!< DTHREN (Bitfield-Mask: 0x01)                          */
10789 #define BLEIF_DMATRIGEN_DCMDCMPEN_Pos     (0UL)                     /*!< DCMDCMPEN (Bit 0)                                     */
10790 #define BLEIF_DMATRIGEN_DCMDCMPEN_Msk     (0x1UL)                   /*!< DCMDCMPEN (Bitfield-Mask: 0x01)                       */
10791 /* ======================================================  DMATRIGSTAT  ====================================================== */
10792 #define BLEIF_DMATRIGSTAT_DTOTCMP_Pos     (2UL)                     /*!< DTOTCMP (Bit 2)                                       */
10793 #define BLEIF_DMATRIGSTAT_DTOTCMP_Msk     (0x4UL)                   /*!< DTOTCMP (Bitfield-Mask: 0x01)                         */
10794 #define BLEIF_DMATRIGSTAT_DTHR_Pos        (1UL)                     /*!< DTHR (Bit 1)                                          */
10795 #define BLEIF_DMATRIGSTAT_DTHR_Msk        (0x2UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
10796 #define BLEIF_DMATRIGSTAT_DCMDCMP_Pos     (0UL)                     /*!< DCMDCMP (Bit 0)                                       */
10797 #define BLEIF_DMATRIGSTAT_DCMDCMP_Msk     (0x1UL)                   /*!< DCMDCMP (Bitfield-Mask: 0x01)                         */
10798 /* ========================================================  DMACFG  ========================================================= */
10799 #define BLEIF_DMACFG_DMAPRI_Pos           (8UL)                     /*!< DMAPRI (Bit 8)                                        */
10800 #define BLEIF_DMACFG_DMAPRI_Msk           (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
10801 #define BLEIF_DMACFG_DMADIR_Pos           (1UL)                     /*!< DMADIR (Bit 1)                                        */
10802 #define BLEIF_DMACFG_DMADIR_Msk           (0x2UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
10803 #define BLEIF_DMACFG_DMAEN_Pos            (0UL)                     /*!< DMAEN (Bit 0)                                         */
10804 #define BLEIF_DMACFG_DMAEN_Msk            (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
10805 /* ======================================================  DMATOTCOUNT  ====================================================== */
10806 #define BLEIF_DMATOTCOUNT_TOTCOUNT_Pos    (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
10807 #define BLEIF_DMATOTCOUNT_TOTCOUNT_Msk    (0xfffUL)                 /*!< TOTCOUNT (Bitfield-Mask: 0xfff)                       */
10808 /* ======================================================  DMATARGADDR  ====================================================== */
10809 #define BLEIF_DMATARGADDR_TARGADDR28_Pos  (28UL)                    /*!< TARGADDR28 (Bit 28)                                   */
10810 #define BLEIF_DMATARGADDR_TARGADDR28_Msk  (0x10000000UL)            /*!< TARGADDR28 (Bitfield-Mask: 0x01)                      */
10811 #define BLEIF_DMATARGADDR_TARGADDR_Pos    (0UL)                     /*!< TARGADDR (Bit 0)                                      */
10812 #define BLEIF_DMATARGADDR_TARGADDR_Msk    (0x1fffffUL)              /*!< TARGADDR (Bitfield-Mask: 0x1fffff)                    */
10813 /* ========================================================  DMASTAT  ======================================================== */
10814 #define BLEIF_DMASTAT_DMAERR_Pos          (2UL)                     /*!< DMAERR (Bit 2)                                        */
10815 #define BLEIF_DMASTAT_DMAERR_Msk          (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
10816 #define BLEIF_DMASTAT_DMACPL_Pos          (1UL)                     /*!< DMACPL (Bit 1)                                        */
10817 #define BLEIF_DMASTAT_DMACPL_Msk          (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
10818 #define BLEIF_DMASTAT_DMATIP_Pos          (0UL)                     /*!< DMATIP (Bit 0)                                        */
10819 #define BLEIF_DMASTAT_DMATIP_Msk          (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
10820 /* =========================================================  CQCFG  ========================================================= */
10821 #define BLEIF_CQCFG_CQPRI_Pos             (1UL)                     /*!< CQPRI (Bit 1)                                         */
10822 #define BLEIF_CQCFG_CQPRI_Msk             (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
10823 #define BLEIF_CQCFG_CQEN_Pos              (0UL)                     /*!< CQEN (Bit 0)                                          */
10824 #define BLEIF_CQCFG_CQEN_Msk              (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
10825 /* ========================================================  CQADDR  ========================================================= */
10826 #define BLEIF_CQADDR_CQADDR28_Pos         (28UL)                    /*!< CQADDR28 (Bit 28)                                     */
10827 #define BLEIF_CQADDR_CQADDR28_Msk         (0x10000000UL)            /*!< CQADDR28 (Bitfield-Mask: 0x01)                        */
10828 #define BLEIF_CQADDR_CQADDR_Pos           (2UL)                     /*!< CQADDR (Bit 2)                                        */
10829 #define BLEIF_CQADDR_CQADDR_Msk           (0x1ffffcUL)              /*!< CQADDR (Bitfield-Mask: 0x7ffff)                       */
10830 /* ========================================================  CQSTAT  ========================================================= */
10831 #define BLEIF_CQSTAT_CQERR_Pos            (2UL)                     /*!< CQERR (Bit 2)                                         */
10832 #define BLEIF_CQSTAT_CQERR_Msk            (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
10833 #define BLEIF_CQSTAT_CQPAUSED_Pos         (1UL)                     /*!< CQPAUSED (Bit 1)                                      */
10834 #define BLEIF_CQSTAT_CQPAUSED_Msk         (0x2UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
10835 #define BLEIF_CQSTAT_CQTIP_Pos            (0UL)                     /*!< CQTIP (Bit 0)                                         */
10836 #define BLEIF_CQSTAT_CQTIP_Msk            (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
10837 /* ========================================================  CQFLAGS  ======================================================== */
10838 #define BLEIF_CQFLAGS_CQIRQMASK_Pos       (16UL)                    /*!< CQIRQMASK (Bit 16)                                    */
10839 #define BLEIF_CQFLAGS_CQIRQMASK_Msk       (0xffff0000UL)            /*!< CQIRQMASK (Bitfield-Mask: 0xffff)                     */
10840 #define BLEIF_CQFLAGS_CQFLAGS_Pos         (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
10841 #define BLEIF_CQFLAGS_CQFLAGS_Msk         (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
10842 /* ======================================================  CQSETCLEAR  ======================================================= */
10843 #define BLEIF_CQSETCLEAR_CQFCLR_Pos       (16UL)                    /*!< CQFCLR (Bit 16)                                       */
10844 #define BLEIF_CQSETCLEAR_CQFCLR_Msk       (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
10845 #define BLEIF_CQSETCLEAR_CQFTGL_Pos       (8UL)                     /*!< CQFTGL (Bit 8)                                        */
10846 #define BLEIF_CQSETCLEAR_CQFTGL_Msk       (0xff00UL)                /*!< CQFTGL (Bitfield-Mask: 0xff)                          */
10847 #define BLEIF_CQSETCLEAR_CQFSET_Pos       (0UL)                     /*!< CQFSET (Bit 0)                                        */
10848 #define BLEIF_CQSETCLEAR_CQFSET_Msk       (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
10849 /* =======================================================  CQPAUSEEN  ======================================================= */
10850 #define BLEIF_CQPAUSEEN_CQPEN_Pos         (0UL)                     /*!< CQPEN (Bit 0)                                         */
10851 #define BLEIF_CQPAUSEEN_CQPEN_Msk         (0xffffUL)                /*!< CQPEN (Bitfield-Mask: 0xffff)                         */
10852 /* =======================================================  CQCURIDX  ======================================================== */
10853 #define BLEIF_CQCURIDX_CQCURIDX_Pos       (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
10854 #define BLEIF_CQCURIDX_CQCURIDX_Msk       (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
10855 /* =======================================================  CQENDIDX  ======================================================== */
10856 #define BLEIF_CQENDIDX_CQENDIDX_Pos       (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
10857 #define BLEIF_CQENDIDX_CQENDIDX_Msk       (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
10858 /* ========================================================  STATUS  ========================================================= */
10859 #define BLEIF_STATUS_IDLEST_Pos           (2UL)                     /*!< IDLEST (Bit 2)                                        */
10860 #define BLEIF_STATUS_IDLEST_Msk           (0x4UL)                   /*!< IDLEST (Bitfield-Mask: 0x01)                          */
10861 #define BLEIF_STATUS_CMDACT_Pos           (1UL)                     /*!< CMDACT (Bit 1)                                        */
10862 #define BLEIF_STATUS_CMDACT_Msk           (0x2UL)                   /*!< CMDACT (Bitfield-Mask: 0x01)                          */
10863 #define BLEIF_STATUS_ERR_Pos              (0UL)                     /*!< ERR (Bit 0)                                           */
10864 #define BLEIF_STATUS_ERR_Msk              (0x1UL)                   /*!< ERR (Bitfield-Mask: 0x01)                             */
10865 /* ========================================================  MSPICFG  ======================================================== */
10866 #define BLEIF_MSPICFG_MSPIRST_Pos         (30UL)                    /*!< MSPIRST (Bit 30)                                      */
10867 #define BLEIF_MSPICFG_MSPIRST_Msk         (0x40000000UL)            /*!< MSPIRST (Bitfield-Mask: 0x01)                         */
10868 #define BLEIF_MSPICFG_DOUTDLY_Pos         (27UL)                    /*!< DOUTDLY (Bit 27)                                      */
10869 #define BLEIF_MSPICFG_DOUTDLY_Msk         (0x38000000UL)            /*!< DOUTDLY (Bitfield-Mask: 0x07)                         */
10870 #define BLEIF_MSPICFG_DINDLY_Pos          (24UL)                    /*!< DINDLY (Bit 24)                                       */
10871 #define BLEIF_MSPICFG_DINDLY_Msk          (0x7000000UL)             /*!< DINDLY (Bitfield-Mask: 0x07)                          */
10872 #define BLEIF_MSPICFG_SPILSB_Pos          (23UL)                    /*!< SPILSB (Bit 23)                                       */
10873 #define BLEIF_MSPICFG_SPILSB_Msk          (0x800000UL)              /*!< SPILSB (Bitfield-Mask: 0x01)                          */
10874 #define BLEIF_MSPICFG_RDFCPOL_Pos         (22UL)                    /*!< RDFCPOL (Bit 22)                                      */
10875 #define BLEIF_MSPICFG_RDFCPOL_Msk         (0x400000UL)              /*!< RDFCPOL (Bitfield-Mask: 0x01)                         */
10876 #define BLEIF_MSPICFG_WTFCPOL_Pos         (21UL)                    /*!< WTFCPOL (Bit 21)                                      */
10877 #define BLEIF_MSPICFG_WTFCPOL_Msk         (0x200000UL)              /*!< WTFCPOL (Bitfield-Mask: 0x01)                         */
10878 #define BLEIF_MSPICFG_RDFC_Pos            (17UL)                    /*!< RDFC (Bit 17)                                         */
10879 #define BLEIF_MSPICFG_RDFC_Msk            (0x20000UL)               /*!< RDFC (Bitfield-Mask: 0x01)                            */
10880 #define BLEIF_MSPICFG_WTFC_Pos            (16UL)                    /*!< WTFC (Bit 16)                                         */
10881 #define BLEIF_MSPICFG_WTFC_Msk            (0x10000UL)               /*!< WTFC (Bitfield-Mask: 0x01)                            */
10882 #define BLEIF_MSPICFG_FULLDUP_Pos         (2UL)                     /*!< FULLDUP (Bit 2)                                       */
10883 #define BLEIF_MSPICFG_FULLDUP_Msk         (0x4UL)                   /*!< FULLDUP (Bitfield-Mask: 0x01)                         */
10884 #define BLEIF_MSPICFG_SPHA_Pos            (1UL)                     /*!< SPHA (Bit 1)                                          */
10885 #define BLEIF_MSPICFG_SPHA_Msk            (0x2UL)                   /*!< SPHA (Bitfield-Mask: 0x01)                            */
10886 #define BLEIF_MSPICFG_SPOL_Pos            (0UL)                     /*!< SPOL (Bit 0)                                          */
10887 #define BLEIF_MSPICFG_SPOL_Msk            (0x1UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
10888 /* ========================================================  BLECFG  ========================================================= */
10889 #define BLEIF_BLECFG_SPIISOCTL_Pos        (14UL)                    /*!< SPIISOCTL (Bit 14)                                    */
10890 #define BLEIF_BLECFG_SPIISOCTL_Msk        (0xc000UL)                /*!< SPIISOCTL (Bitfield-Mask: 0x03)                       */
10891 #define BLEIF_BLECFG_PWRISOCTL_Pos        (12UL)                    /*!< PWRISOCTL (Bit 12)                                    */
10892 #define BLEIF_BLECFG_PWRISOCTL_Msk        (0x3000UL)                /*!< PWRISOCTL (Bitfield-Mask: 0x03)                       */
10893 #define BLEIF_BLECFG_STAYASLEEP_Pos       (11UL)                    /*!< STAYASLEEP (Bit 11)                                   */
10894 #define BLEIF_BLECFG_STAYASLEEP_Msk       (0x800UL)                 /*!< STAYASLEEP (Bitfield-Mask: 0x01)                      */
10895 #define BLEIF_BLECFG_FRCCLK_Pos           (10UL)                    /*!< FRCCLK (Bit 10)                                       */
10896 #define BLEIF_BLECFG_FRCCLK_Msk           (0x400UL)                 /*!< FRCCLK (Bitfield-Mask: 0x01)                          */
10897 #define BLEIF_BLECFG_MCUFRCSLP_Pos        (9UL)                     /*!< MCUFRCSLP (Bit 9)                                     */
10898 #define BLEIF_BLECFG_MCUFRCSLP_Msk        (0x200UL)                 /*!< MCUFRCSLP (Bitfield-Mask: 0x01)                       */
10899 #define BLEIF_BLECFG_WT4ACTOFF_Pos        (8UL)                     /*!< WT4ACTOFF (Bit 8)                                     */
10900 #define BLEIF_BLECFG_WT4ACTOFF_Msk        (0x100UL)                 /*!< WT4ACTOFF (Bitfield-Mask: 0x01)                       */
10901 #define BLEIF_BLECFG_BLEHREQCTL_Pos       (6UL)                     /*!< BLEHREQCTL (Bit 6)                                    */
10902 #define BLEIF_BLECFG_BLEHREQCTL_Msk       (0xc0UL)                  /*!< BLEHREQCTL (Bitfield-Mask: 0x03)                      */
10903 #define BLEIF_BLECFG_DCDCFLGCTL_Pos       (4UL)                     /*!< DCDCFLGCTL (Bit 4)                                    */
10904 #define BLEIF_BLECFG_DCDCFLGCTL_Msk       (0x30UL)                  /*!< DCDCFLGCTL (Bitfield-Mask: 0x03)                      */
10905 #define BLEIF_BLECFG_WAKEUPCTL_Pos        (2UL)                     /*!< WAKEUPCTL (Bit 2)                                     */
10906 #define BLEIF_BLECFG_WAKEUPCTL_Msk        (0xcUL)                   /*!< WAKEUPCTL (Bitfield-Mask: 0x03)                       */
10907 #define BLEIF_BLECFG_BLERSTN_Pos          (1UL)                     /*!< BLERSTN (Bit 1)                                       */
10908 #define BLEIF_BLECFG_BLERSTN_Msk          (0x2UL)                   /*!< BLERSTN (Bitfield-Mask: 0x01)                         */
10909 #define BLEIF_BLECFG_PWRSMEN_Pos          (0UL)                     /*!< PWRSMEN (Bit 0)                                       */
10910 #define BLEIF_BLECFG_PWRSMEN_Msk          (0x1UL)                   /*!< PWRSMEN (Bitfield-Mask: 0x01)                         */
10911 /* ========================================================  PWRCMD  ========================================================= */
10912 #define BLEIF_PWRCMD_RESTART_Pos          (1UL)                     /*!< RESTART (Bit 1)                                       */
10913 #define BLEIF_PWRCMD_RESTART_Msk          (0x2UL)                   /*!< RESTART (Bitfield-Mask: 0x01)                         */
10914 #define BLEIF_PWRCMD_WAKEREQ_Pos          (0UL)                     /*!< WAKEREQ (Bit 0)                                       */
10915 #define BLEIF_PWRCMD_WAKEREQ_Msk          (0x1UL)                   /*!< WAKEREQ (Bitfield-Mask: 0x01)                         */
10916 /* ========================================================  BSTATUS  ======================================================== */
10917 #define BLEIF_BSTATUS_BLEHREQ_Pos         (12UL)                    /*!< BLEHREQ (Bit 12)                                      */
10918 #define BLEIF_BSTATUS_BLEHREQ_Msk         (0x1000UL)                /*!< BLEHREQ (Bitfield-Mask: 0x01)                         */
10919 #define BLEIF_BSTATUS_BLEHACK_Pos         (11UL)                    /*!< BLEHACK (Bit 11)                                      */
10920 #define BLEIF_BSTATUS_BLEHACK_Msk         (0x800UL)                 /*!< BLEHACK (Bitfield-Mask: 0x01)                         */
10921 #define BLEIF_BSTATUS_PWRST_Pos           (8UL)                     /*!< PWRST (Bit 8)                                         */
10922 #define BLEIF_BSTATUS_PWRST_Msk           (0x700UL)                 /*!< PWRST (Bitfield-Mask: 0x07)                           */
10923 #define BLEIF_BSTATUS_BLEIRQ_Pos          (7UL)                     /*!< BLEIRQ (Bit 7)                                        */
10924 #define BLEIF_BSTATUS_BLEIRQ_Msk          (0x80UL)                  /*!< BLEIRQ (Bitfield-Mask: 0x01)                          */
10925 #define BLEIF_BSTATUS_WAKEUP_Pos          (6UL)                     /*!< WAKEUP (Bit 6)                                        */
10926 #define BLEIF_BSTATUS_WAKEUP_Msk          (0x40UL)                  /*!< WAKEUP (Bitfield-Mask: 0x01)                          */
10927 #define BLEIF_BSTATUS_DCDCFLAG_Pos        (5UL)                     /*!< DCDCFLAG (Bit 5)                                      */
10928 #define BLEIF_BSTATUS_DCDCFLAG_Msk        (0x20UL)                  /*!< DCDCFLAG (Bitfield-Mask: 0x01)                        */
10929 #define BLEIF_BSTATUS_DCDCREQ_Pos         (4UL)                     /*!< DCDCREQ (Bit 4)                                       */
10930 #define BLEIF_BSTATUS_DCDCREQ_Msk         (0x10UL)                  /*!< DCDCREQ (Bitfield-Mask: 0x01)                         */
10931 #define BLEIF_BSTATUS_SPISTATUS_Pos       (3UL)                     /*!< SPISTATUS (Bit 3)                                     */
10932 #define BLEIF_BSTATUS_SPISTATUS_Msk       (0x8UL)                   /*!< SPISTATUS (Bitfield-Mask: 0x01)                       */
10933 #define BLEIF_BSTATUS_B2MSTATE_Pos        (0UL)                     /*!< B2MSTATE (Bit 0)                                      */
10934 #define BLEIF_BSTATUS_B2MSTATE_Msk        (0x7UL)                   /*!< B2MSTATE (Bitfield-Mask: 0x07)                        */
10935 /* ========================================================  BLEDBG  ========================================================= */
10936 #define BLEIF_BLEDBG_DBGDATA_Pos          (3UL)                     /*!< DBGDATA (Bit 3)                                       */
10937 #define BLEIF_BLEDBG_DBGDATA_Msk          (0xfffffff8UL)            /*!< DBGDATA (Bitfield-Mask: 0x1fffffff)                   */
10938 #define BLEIF_BLEDBG_APBCLKON_Pos         (2UL)                     /*!< APBCLKON (Bit 2)                                      */
10939 #define BLEIF_BLEDBG_APBCLKON_Msk         (0x4UL)                   /*!< APBCLKON (Bitfield-Mask: 0x01)                        */
10940 #define BLEIF_BLEDBG_IOCLKON_Pos          (1UL)                     /*!< IOCLKON (Bit 1)                                       */
10941 #define BLEIF_BLEDBG_IOCLKON_Msk          (0x2UL)                   /*!< IOCLKON (Bitfield-Mask: 0x01)                         */
10942 #define BLEIF_BLEDBG_DBGEN_Pos            (0UL)                     /*!< DBGEN (Bit 0)                                         */
10943 #define BLEIF_BLEDBG_DBGEN_Msk            (0x1UL)                   /*!< DBGEN (Bitfield-Mask: 0x01)                           */
10944 
10945 
10946 /* =========================================================================================================================== */
10947 /* ================                                         CACHECTRL                                         ================ */
10948 /* =========================================================================================================================== */
10949 
10950 /* =======================================================  CACHECFG  ======================================================== */
10951 #define CACHECTRL_CACHECFG_ENABLE_MONITOR_Pos (24UL)                /*!< ENABLE_MONITOR (Bit 24)                               */
10952 #define CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk (0x1000000UL)         /*!< ENABLE_MONITOR (Bitfield-Mask: 0x01)                  */
10953 #define CACHECTRL_CACHECFG_DATA_CLKGATE_Pos (20UL)                  /*!< DATA_CLKGATE (Bit 20)                                 */
10954 #define CACHECTRL_CACHECFG_DATA_CLKGATE_Msk (0x100000UL)            /*!< DATA_CLKGATE (Bitfield-Mask: 0x01)                    */
10955 #define CACHECTRL_CACHECFG_CACHE_LS_Pos   (11UL)                    /*!< CACHE_LS (Bit 11)                                     */
10956 #define CACHECTRL_CACHECFG_CACHE_LS_Msk   (0x800UL)                 /*!< CACHE_LS (Bitfield-Mask: 0x01)                        */
10957 #define CACHECTRL_CACHECFG_CACHE_CLKGATE_Pos (10UL)                 /*!< CACHE_CLKGATE (Bit 10)                                */
10958 #define CACHECTRL_CACHECFG_CACHE_CLKGATE_Msk (0x400UL)              /*!< CACHE_CLKGATE (Bitfield-Mask: 0x01)                   */
10959 #define CACHECTRL_CACHECFG_DCACHE_ENABLE_Pos (9UL)                  /*!< DCACHE_ENABLE (Bit 9)                                 */
10960 #define CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk (0x200UL)              /*!< DCACHE_ENABLE (Bitfield-Mask: 0x01)                   */
10961 #define CACHECTRL_CACHECFG_ICACHE_ENABLE_Pos (8UL)                  /*!< ICACHE_ENABLE (Bit 8)                                 */
10962 #define CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk (0x100UL)              /*!< ICACHE_ENABLE (Bitfield-Mask: 0x01)                   */
10963 #define CACHECTRL_CACHECFG_CONFIG_Pos     (4UL)                     /*!< CONFIG (Bit 4)                                        */
10964 #define CACHECTRL_CACHECFG_CONFIG_Msk     (0xf0UL)                  /*!< CONFIG (Bitfield-Mask: 0x0f)                          */
10965 #define CACHECTRL_CACHECFG_ENABLE_NC1_Pos (3UL)                     /*!< ENABLE_NC1 (Bit 3)                                    */
10966 #define CACHECTRL_CACHECFG_ENABLE_NC1_Msk (0x8UL)                   /*!< ENABLE_NC1 (Bitfield-Mask: 0x01)                      */
10967 #define CACHECTRL_CACHECFG_ENABLE_NC0_Pos (2UL)                     /*!< ENABLE_NC0 (Bit 2)                                    */
10968 #define CACHECTRL_CACHECFG_ENABLE_NC0_Msk (0x4UL)                   /*!< ENABLE_NC0 (Bitfield-Mask: 0x01)                      */
10969 #define CACHECTRL_CACHECFG_LRU_Pos        (1UL)                     /*!< LRU (Bit 1)                                           */
10970 #define CACHECTRL_CACHECFG_LRU_Msk        (0x2UL)                   /*!< LRU (Bitfield-Mask: 0x01)                             */
10971 #define CACHECTRL_CACHECFG_ENABLE_Pos     (0UL)                     /*!< ENABLE (Bit 0)                                        */
10972 #define CACHECTRL_CACHECFG_ENABLE_Msk     (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
10973 /* =========================================================  CTRL  ========================================================== */
10974 #define CACHECTRL_CTRL_FLASH3_SLM_ENABLE_Pos (18UL)                 /*!< FLASH3_SLM_ENABLE (Bit 18)                            */
10975 #define CACHECTRL_CTRL_FLASH3_SLM_ENABLE_Msk (0x40000UL)            /*!< FLASH3_SLM_ENABLE (Bitfield-Mask: 0x01)               */
10976 #define CACHECTRL_CTRL_FLASH3_SLM_DISABLE_Pos (17UL)                /*!< FLASH3_SLM_DISABLE (Bit 17)                           */
10977 #define CACHECTRL_CTRL_FLASH3_SLM_DISABLE_Msk (0x20000UL)           /*!< FLASH3_SLM_DISABLE (Bitfield-Mask: 0x01)              */
10978 #define CACHECTRL_CTRL_FLASH3_SLM_STATUS_Pos (16UL)                 /*!< FLASH3_SLM_STATUS (Bit 16)                            */
10979 #define CACHECTRL_CTRL_FLASH3_SLM_STATUS_Msk (0x10000UL)            /*!< FLASH3_SLM_STATUS (Bitfield-Mask: 0x01)               */
10980 #define CACHECTRL_CTRL_FLASH2_SLM_ENABLE_Pos (14UL)                 /*!< FLASH2_SLM_ENABLE (Bit 14)                            */
10981 #define CACHECTRL_CTRL_FLASH2_SLM_ENABLE_Msk (0x4000UL)             /*!< FLASH2_SLM_ENABLE (Bitfield-Mask: 0x01)               */
10982 #define CACHECTRL_CTRL_FLASH2_SLM_DISABLE_Pos (13UL)                /*!< FLASH2_SLM_DISABLE (Bit 13)                           */
10983 #define CACHECTRL_CTRL_FLASH2_SLM_DISABLE_Msk (0x2000UL)            /*!< FLASH2_SLM_DISABLE (Bitfield-Mask: 0x01)              */
10984 #define CACHECTRL_CTRL_FLASH2_SLM_STATUS_Pos (12UL)                 /*!< FLASH2_SLM_STATUS (Bit 12)                            */
10985 #define CACHECTRL_CTRL_FLASH2_SLM_STATUS_Msk (0x1000UL)             /*!< FLASH2_SLM_STATUS (Bitfield-Mask: 0x01)               */
10986 #define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Pos (10UL)                 /*!< FLASH1_SLM_ENABLE (Bit 10)                            */
10987 #define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk (0x400UL)              /*!< FLASH1_SLM_ENABLE (Bitfield-Mask: 0x01)               */
10988 #define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Pos (9UL)                 /*!< FLASH1_SLM_DISABLE (Bit 9)                            */
10989 #define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk (0x200UL)             /*!< FLASH1_SLM_DISABLE (Bitfield-Mask: 0x01)              */
10990 #define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Pos (8UL)                  /*!< FLASH1_SLM_STATUS (Bit 8)                             */
10991 #define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Msk (0x100UL)              /*!< FLASH1_SLM_STATUS (Bitfield-Mask: 0x01)               */
10992 #define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Pos (6UL)                  /*!< FLASH0_SLM_ENABLE (Bit 6)                             */
10993 #define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk (0x40UL)               /*!< FLASH0_SLM_ENABLE (Bitfield-Mask: 0x01)               */
10994 #define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Pos (5UL)                 /*!< FLASH0_SLM_DISABLE (Bit 5)                            */
10995 #define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk (0x20UL)              /*!< FLASH0_SLM_DISABLE (Bitfield-Mask: 0x01)              */
10996 #define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Pos (4UL)                  /*!< FLASH0_SLM_STATUS (Bit 4)                             */
10997 #define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Msk (0x10UL)               /*!< FLASH0_SLM_STATUS (Bitfield-Mask: 0x01)               */
10998 #define CACHECTRL_CTRL_CACHE_READY_Pos    (2UL)                     /*!< CACHE_READY (Bit 2)                                   */
10999 #define CACHECTRL_CTRL_CACHE_READY_Msk    (0x4UL)                   /*!< CACHE_READY (Bitfield-Mask: 0x01)                     */
11000 #define CACHECTRL_CTRL_RESET_STAT_Pos     (1UL)                     /*!< RESET_STAT (Bit 1)                                    */
11001 #define CACHECTRL_CTRL_RESET_STAT_Msk     (0x2UL)                   /*!< RESET_STAT (Bitfield-Mask: 0x01)                      */
11002 #define CACHECTRL_CTRL_INVALIDATE_Pos     (0UL)                     /*!< INVALIDATE (Bit 0)                                    */
11003 #define CACHECTRL_CTRL_INVALIDATE_Msk     (0x1UL)                   /*!< INVALIDATE (Bitfield-Mask: 0x01)                      */
11004 /* =======================================================  NCR0START  ======================================================= */
11005 #define CACHECTRL_NCR0START_ADDR_Pos      (4UL)                     /*!< ADDR (Bit 4)                                          */
11006 #define CACHECTRL_NCR0START_ADDR_Msk      (0x7fffff0UL)             /*!< ADDR (Bitfield-Mask: 0x7fffff)                        */
11007 /* ========================================================  NCR0END  ======================================================== */
11008 #define CACHECTRL_NCR0END_ADDR_Pos        (4UL)                     /*!< ADDR (Bit 4)                                          */
11009 #define CACHECTRL_NCR0END_ADDR_Msk        (0x7fffff0UL)             /*!< ADDR (Bitfield-Mask: 0x7fffff)                        */
11010 /* =======================================================  NCR1START  ======================================================= */
11011 #define CACHECTRL_NCR1START_ADDR_Pos      (4UL)                     /*!< ADDR (Bit 4)                                          */
11012 #define CACHECTRL_NCR1START_ADDR_Msk      (0x7fffff0UL)             /*!< ADDR (Bitfield-Mask: 0x7fffff)                        */
11013 /* ========================================================  NCR1END  ======================================================== */
11014 #define CACHECTRL_NCR1END_ADDR_Pos        (4UL)                     /*!< ADDR (Bit 4)                                          */
11015 #define CACHECTRL_NCR1END_ADDR_Msk        (0x7fffff0UL)             /*!< ADDR (Bitfield-Mask: 0x7fffff)                        */
11016 /* =========================================================  DMON0  ========================================================= */
11017 #define CACHECTRL_DMON0_DACCESS_COUNT_Pos (0UL)                     /*!< DACCESS_COUNT (Bit 0)                                 */
11018 #define CACHECTRL_DMON0_DACCESS_COUNT_Msk (0xffffffffUL)            /*!< DACCESS_COUNT (Bitfield-Mask: 0xffffffff)             */
11019 /* =========================================================  DMON1  ========================================================= */
11020 #define CACHECTRL_DMON1_DLOOKUP_COUNT_Pos (0UL)                     /*!< DLOOKUP_COUNT (Bit 0)                                 */
11021 #define CACHECTRL_DMON1_DLOOKUP_COUNT_Msk (0xffffffffUL)            /*!< DLOOKUP_COUNT (Bitfield-Mask: 0xffffffff)             */
11022 /* =========================================================  DMON2  ========================================================= */
11023 #define CACHECTRL_DMON2_DHIT_COUNT_Pos    (0UL)                     /*!< DHIT_COUNT (Bit 0)                                    */
11024 #define CACHECTRL_DMON2_DHIT_COUNT_Msk    (0xffffffffUL)            /*!< DHIT_COUNT (Bitfield-Mask: 0xffffffff)                */
11025 /* =========================================================  DMON3  ========================================================= */
11026 #define CACHECTRL_DMON3_DLINE_COUNT_Pos   (0UL)                     /*!< DLINE_COUNT (Bit 0)                                   */
11027 #define CACHECTRL_DMON3_DLINE_COUNT_Msk   (0xffffffffUL)            /*!< DLINE_COUNT (Bitfield-Mask: 0xffffffff)               */
11028 /* =========================================================  IMON0  ========================================================= */
11029 #define CACHECTRL_IMON0_IACCESS_COUNT_Pos (0UL)                     /*!< IACCESS_COUNT (Bit 0)                                 */
11030 #define CACHECTRL_IMON0_IACCESS_COUNT_Msk (0xffffffffUL)            /*!< IACCESS_COUNT (Bitfield-Mask: 0xffffffff)             */
11031 /* =========================================================  IMON1  ========================================================= */
11032 #define CACHECTRL_IMON1_ILOOKUP_COUNT_Pos (0UL)                     /*!< ILOOKUP_COUNT (Bit 0)                                 */
11033 #define CACHECTRL_IMON1_ILOOKUP_COUNT_Msk (0xffffffffUL)            /*!< ILOOKUP_COUNT (Bitfield-Mask: 0xffffffff)             */
11034 /* =========================================================  IMON2  ========================================================= */
11035 #define CACHECTRL_IMON2_IHIT_COUNT_Pos    (0UL)                     /*!< IHIT_COUNT (Bit 0)                                    */
11036 #define CACHECTRL_IMON2_IHIT_COUNT_Msk    (0xffffffffUL)            /*!< IHIT_COUNT (Bitfield-Mask: 0xffffffff)                */
11037 /* =========================================================  IMON3  ========================================================= */
11038 #define CACHECTRL_IMON3_ILINE_COUNT_Pos   (0UL)                     /*!< ILINE_COUNT (Bit 0)                                   */
11039 #define CACHECTRL_IMON3_ILINE_COUNT_Msk   (0xffffffffUL)            /*!< ILINE_COUNT (Bitfield-Mask: 0xffffffff)               */
11040 /* =======================================================  FLASH0CFG  ======================================================= */
11041 #define CACHECTRL_FLASH0CFG_LPMMODE0_Pos  (12UL)                    /*!< LPMMODE0 (Bit 12)                                     */
11042 #define CACHECTRL_FLASH0CFG_LPMMODE0_Msk  (0x3000UL)                /*!< LPMMODE0 (Bitfield-Mask: 0x03)                        */
11043 #define CACHECTRL_FLASH0CFG_LPMRDWAIT0_Pos (8UL)                    /*!< LPMRDWAIT0 (Bit 8)                                    */
11044 #define CACHECTRL_FLASH0CFG_LPMRDWAIT0_Msk (0xf00UL)                /*!< LPMRDWAIT0 (Bitfield-Mask: 0x0f)                      */
11045 #define CACHECTRL_FLASH0CFG_SEDELAY0_Pos  (4UL)                     /*!< SEDELAY0 (Bit 4)                                      */
11046 #define CACHECTRL_FLASH0CFG_SEDELAY0_Msk  (0x70UL)                  /*!< SEDELAY0 (Bitfield-Mask: 0x07)                        */
11047 #define CACHECTRL_FLASH0CFG_RDWAIT0_Pos   (0UL)                     /*!< RDWAIT0 (Bit 0)                                       */
11048 #define CACHECTRL_FLASH0CFG_RDWAIT0_Msk   (0xfUL)                   /*!< RDWAIT0 (Bitfield-Mask: 0x0f)                         */
11049 /* =======================================================  FLASH1CFG  ======================================================= */
11050 #define CACHECTRL_FLASH1CFG_LPMMODE1_Pos  (12UL)                    /*!< LPMMODE1 (Bit 12)                                     */
11051 #define CACHECTRL_FLASH1CFG_LPMMODE1_Msk  (0x3000UL)                /*!< LPMMODE1 (Bitfield-Mask: 0x03)                        */
11052 #define CACHECTRL_FLASH1CFG_LPMRDWAIT1_Pos (8UL)                    /*!< LPMRDWAIT1 (Bit 8)                                    */
11053 #define CACHECTRL_FLASH1CFG_LPMRDWAIT1_Msk (0xf00UL)                /*!< LPMRDWAIT1 (Bitfield-Mask: 0x0f)                      */
11054 #define CACHECTRL_FLASH1CFG_SEDELAY1_Pos  (4UL)                     /*!< SEDELAY1 (Bit 4)                                      */
11055 #define CACHECTRL_FLASH1CFG_SEDELAY1_Msk  (0x70UL)                  /*!< SEDELAY1 (Bitfield-Mask: 0x07)                        */
11056 #define CACHECTRL_FLASH1CFG_RDWAIT1_Pos   (0UL)                     /*!< RDWAIT1 (Bit 0)                                       */
11057 #define CACHECTRL_FLASH1CFG_RDWAIT1_Msk   (0xfUL)                   /*!< RDWAIT1 (Bitfield-Mask: 0x0f)                         */
11058 /* =======================================================  FLASH2CFG  ======================================================= */
11059 #define CACHECTRL_FLASH2CFG_LPMMODE2_Pos  (12UL)                    /*!< LPMMODE2 (Bit 12)                                     */
11060 #define CACHECTRL_FLASH2CFG_LPMMODE2_Msk  (0x3000UL)                /*!< LPMMODE2 (Bitfield-Mask: 0x03)                        */
11061 #define CACHECTRL_FLASH2CFG_LPMRDWAIT2_Pos (8UL)                    /*!< LPMRDWAIT2 (Bit 8)                                    */
11062 #define CACHECTRL_FLASH2CFG_LPMRDWAIT2_Msk (0xf00UL)                /*!< LPMRDWAIT2 (Bitfield-Mask: 0x0f)                      */
11063 #define CACHECTRL_FLASH2CFG_SEDELAY2_Pos  (4UL)                     /*!< SEDELAY2 (Bit 4)                                      */
11064 #define CACHECTRL_FLASH2CFG_SEDELAY2_Msk  (0x70UL)                  /*!< SEDELAY2 (Bitfield-Mask: 0x07)                        */
11065 #define CACHECTRL_FLASH2CFG_RDWAIT2_Pos   (0UL)                     /*!< RDWAIT2 (Bit 0)                                       */
11066 #define CACHECTRL_FLASH2CFG_RDWAIT2_Msk   (0xfUL)                   /*!< RDWAIT2 (Bitfield-Mask: 0x0f)                         */
11067 /* =======================================================  FLASH3CFG  ======================================================= */
11068 #define CACHECTRL_FLASH3CFG_LPMMODE3_Pos  (12UL)                    /*!< LPMMODE3 (Bit 12)                                     */
11069 #define CACHECTRL_FLASH3CFG_LPMMODE3_Msk  (0x3000UL)                /*!< LPMMODE3 (Bitfield-Mask: 0x03)                        */
11070 #define CACHECTRL_FLASH3CFG_LPMRDWAIT3_Pos (8UL)                    /*!< LPMRDWAIT3 (Bit 8)                                    */
11071 #define CACHECTRL_FLASH3CFG_LPMRDWAIT3_Msk (0xf00UL)                /*!< LPMRDWAIT3 (Bitfield-Mask: 0x0f)                      */
11072 #define CACHECTRL_FLASH3CFG_SEDELAY3_Pos  (4UL)                     /*!< SEDELAY3 (Bit 4)                                      */
11073 #define CACHECTRL_FLASH3CFG_SEDELAY3_Msk  (0x70UL)                  /*!< SEDELAY3 (Bitfield-Mask: 0x07)                        */
11074 #define CACHECTRL_FLASH3CFG_RDWAIT3_Pos   (0UL)                     /*!< RDWAIT3 (Bit 0)                                       */
11075 #define CACHECTRL_FLASH3CFG_RDWAIT3_Msk   (0xfUL)                   /*!< RDWAIT3 (Bitfield-Mask: 0x0f)                         */
11076 
11077 
11078 /* =========================================================================================================================== */
11079 /* ================                                          CLKGEN                                           ================ */
11080 /* =========================================================================================================================== */
11081 
11082 /* =========================================================  CALXT  ========================================================= */
11083 #define CLKGEN_CALXT_CALXT_Pos            (0UL)                     /*!< CALXT (Bit 0)                                         */
11084 #define CLKGEN_CALXT_CALXT_Msk            (0x7ffUL)                 /*!< CALXT (Bitfield-Mask: 0x7ff)                          */
11085 /* =========================================================  CALRC  ========================================================= */
11086 #define CLKGEN_CALRC_CALRC_Pos            (0UL)                     /*!< CALRC (Bit 0)                                         */
11087 #define CLKGEN_CALRC_CALRC_Msk            (0x3ffffUL)               /*!< CALRC (Bitfield-Mask: 0x3ffff)                        */
11088 /* ========================================================  ACALCTR  ======================================================== */
11089 #define CLKGEN_ACALCTR_ACALCTR_Pos        (0UL)                     /*!< ACALCTR (Bit 0)                                       */
11090 #define CLKGEN_ACALCTR_ACALCTR_Msk        (0xffffffUL)              /*!< ACALCTR (Bitfield-Mask: 0xffffff)                     */
11091 /* =========================================================  OCTRL  ========================================================= */
11092 #define CLKGEN_OCTRL_ACAL_Pos             (8UL)                     /*!< ACAL (Bit 8)                                          */
11093 #define CLKGEN_OCTRL_ACAL_Msk             (0x700UL)                 /*!< ACAL (Bitfield-Mask: 0x07)                            */
11094 #define CLKGEN_OCTRL_OSEL_Pos             (7UL)                     /*!< OSEL (Bit 7)                                          */
11095 #define CLKGEN_OCTRL_OSEL_Msk             (0x80UL)                  /*!< OSEL (Bitfield-Mask: 0x01)                            */
11096 #define CLKGEN_OCTRL_FOS_Pos              (6UL)                     /*!< FOS (Bit 6)                                           */
11097 #define CLKGEN_OCTRL_FOS_Msk              (0x40UL)                  /*!< FOS (Bitfield-Mask: 0x01)                             */
11098 #define CLKGEN_OCTRL_STOPRC_Pos           (1UL)                     /*!< STOPRC (Bit 1)                                        */
11099 #define CLKGEN_OCTRL_STOPRC_Msk           (0x2UL)                   /*!< STOPRC (Bitfield-Mask: 0x01)                          */
11100 #define CLKGEN_OCTRL_STOPXT_Pos           (0UL)                     /*!< STOPXT (Bit 0)                                        */
11101 #define CLKGEN_OCTRL_STOPXT_Msk           (0x1UL)                   /*!< STOPXT (Bitfield-Mask: 0x01)                          */
11102 /* ========================================================  CLKOUT  ========================================================= */
11103 #define CLKGEN_CLKOUT_CKEN_Pos            (7UL)                     /*!< CKEN (Bit 7)                                          */
11104 #define CLKGEN_CLKOUT_CKEN_Msk            (0x80UL)                  /*!< CKEN (Bitfield-Mask: 0x01)                            */
11105 #define CLKGEN_CLKOUT_CKSEL_Pos           (0UL)                     /*!< CKSEL (Bit 0)                                         */
11106 #define CLKGEN_CLKOUT_CKSEL_Msk           (0x3fUL)                  /*!< CKSEL (Bitfield-Mask: 0x3f)                           */
11107 /* ========================================================  CLKKEY  ========================================================= */
11108 #define CLKGEN_CLKKEY_CLKKEY_Pos          (0UL)                     /*!< CLKKEY (Bit 0)                                        */
11109 #define CLKGEN_CLKKEY_CLKKEY_Msk          (0xffffffffUL)            /*!< CLKKEY (Bitfield-Mask: 0xffffffff)                    */
11110 /* =========================================================  CCTRL  ========================================================= */
11111 #define CLKGEN_CCTRL_CORESEL_Pos          (0UL)                     /*!< CORESEL (Bit 0)                                       */
11112 #define CLKGEN_CCTRL_CORESEL_Msk          (0x1UL)                   /*!< CORESEL (Bitfield-Mask: 0x01)                         */
11113 /* ========================================================  STATUS  ========================================================= */
11114 #define CLKGEN_STATUS_OSCF_Pos            (1UL)                     /*!< OSCF (Bit 1)                                          */
11115 #define CLKGEN_STATUS_OSCF_Msk            (0x2UL)                   /*!< OSCF (Bitfield-Mask: 0x01)                            */
11116 #define CLKGEN_STATUS_OMODE_Pos           (0UL)                     /*!< OMODE (Bit 0)                                         */
11117 #define CLKGEN_STATUS_OMODE_Msk           (0x1UL)                   /*!< OMODE (Bitfield-Mask: 0x01)                           */
11118 /* =========================================================  HFADJ  ========================================================= */
11119 #define CLKGEN_HFADJ_HFADJGAIN_Pos        (21UL)                    /*!< HFADJGAIN (Bit 21)                                    */
11120 #define CLKGEN_HFADJ_HFADJGAIN_Msk        (0xe00000UL)              /*!< HFADJGAIN (Bitfield-Mask: 0x07)                       */
11121 #define CLKGEN_HFADJ_HFWARMUP_Pos         (20UL)                    /*!< HFWARMUP (Bit 20)                                     */
11122 #define CLKGEN_HFADJ_HFWARMUP_Msk         (0x100000UL)              /*!< HFWARMUP (Bitfield-Mask: 0x01)                        */
11123 #define CLKGEN_HFADJ_HFXTADJ_Pos          (8UL)                     /*!< HFXTADJ (Bit 8)                                       */
11124 #define CLKGEN_HFADJ_HFXTADJ_Msk          (0xfff00UL)               /*!< HFXTADJ (Bitfield-Mask: 0xfff)                        */
11125 #define CLKGEN_HFADJ_HFADJCK_Pos          (1UL)                     /*!< HFADJCK (Bit 1)                                       */
11126 #define CLKGEN_HFADJ_HFADJCK_Msk          (0xeUL)                   /*!< HFADJCK (Bitfield-Mask: 0x07)                         */
11127 #define CLKGEN_HFADJ_HFADJEN_Pos          (0UL)                     /*!< HFADJEN (Bit 0)                                       */
11128 #define CLKGEN_HFADJ_HFADJEN_Msk          (0x1UL)                   /*!< HFADJEN (Bitfield-Mask: 0x01)                         */
11129 /* ======================================================  CLOCKENSTAT  ====================================================== */
11130 #define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Pos (0UL)                    /*!< CLOCKENSTAT (Bit 0)                                   */
11131 #define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Msk (0xffffffffUL)           /*!< CLOCKENSTAT (Bitfield-Mask: 0xffffffff)               */
11132 /* =====================================================  CLOCKEN2STAT  ====================================================== */
11133 #define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Pos (0UL)                  /*!< CLOCKEN2STAT (Bit 0)                                  */
11134 #define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Msk (0xffffffffUL)         /*!< CLOCKEN2STAT (Bitfield-Mask: 0xffffffff)              */
11135 /* =====================================================  CLOCKEN3STAT  ====================================================== */
11136 #define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Pos (0UL)                  /*!< CLOCKEN3STAT (Bit 0)                                  */
11137 #define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Msk (0xffffffffUL)         /*!< CLOCKEN3STAT (Bitfield-Mask: 0xffffffff)              */
11138 /* =======================================================  FREQCTRL  ======================================================== */
11139 #define CLKGEN_FREQCTRL_BURSTSTATUS_Pos   (2UL)                     /*!< BURSTSTATUS (Bit 2)                                   */
11140 #define CLKGEN_FREQCTRL_BURSTSTATUS_Msk   (0x4UL)                   /*!< BURSTSTATUS (Bitfield-Mask: 0x01)                     */
11141 #define CLKGEN_FREQCTRL_BURSTACK_Pos      (1UL)                     /*!< BURSTACK (Bit 1)                                      */
11142 #define CLKGEN_FREQCTRL_BURSTACK_Msk      (0x2UL)                   /*!< BURSTACK (Bitfield-Mask: 0x01)                        */
11143 #define CLKGEN_FREQCTRL_BURSTREQ_Pos      (0UL)                     /*!< BURSTREQ (Bit 0)                                      */
11144 #define CLKGEN_FREQCTRL_BURSTREQ_Msk      (0x1UL)                   /*!< BURSTREQ (Bitfield-Mask: 0x01)                        */
11145 /* =====================================================  BLEBUCKTONADJ  ===================================================== */
11146 #define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Pos (27UL)             /*!< ZEROLENDETECTEN (Bit 27)                              */
11147 #define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Msk (0x8000000UL)      /*!< ZEROLENDETECTEN (Bitfield-Mask: 0x01)                 */
11148 #define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Pos (23UL)           /*!< ZEROLENDETECTTRIM (Bit 23)                            */
11149 #define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Msk (0x7800000UL)    /*!< ZEROLENDETECTTRIM (Bitfield-Mask: 0x0f)               */
11150 #define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Pos (22UL)                 /*!< TONADJUSTEN (Bit 22)                                  */
11151 #define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Msk (0x400000UL)           /*!< TONADJUSTEN (Bitfield-Mask: 0x01)                     */
11152 #define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Pos (20UL)             /*!< TONADJUSTPERIOD (Bit 20)                              */
11153 #define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Msk (0x300000UL)       /*!< TONADJUSTPERIOD (Bitfield-Mask: 0x03)                 */
11154 #define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Pos (10UL)            /*!< TONHIGHTHRESHOLD (Bit 10)                             */
11155 #define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Msk (0xffc00UL)       /*!< TONHIGHTHRESHOLD (Bitfield-Mask: 0x3ff)               */
11156 #define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Pos (0UL)              /*!< TONLOWTHRESHOLD (Bit 0)                               */
11157 #define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Msk (0x3ffUL)          /*!< TONLOWTHRESHOLD (Bitfield-Mask: 0x3ff)                */
11158 /* =======================================================  INTRPTEN  ======================================================== */
11159 #define CLKGEN_INTRPTEN_OF_Pos            (2UL)                     /*!< OF (Bit 2)                                            */
11160 #define CLKGEN_INTRPTEN_OF_Msk            (0x4UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
11161 #define CLKGEN_INTRPTEN_ACC_Pos           (1UL)                     /*!< ACC (Bit 1)                                           */
11162 #define CLKGEN_INTRPTEN_ACC_Msk           (0x2UL)                   /*!< ACC (Bitfield-Mask: 0x01)                             */
11163 #define CLKGEN_INTRPTEN_ACF_Pos           (0UL)                     /*!< ACF (Bit 0)                                           */
11164 #define CLKGEN_INTRPTEN_ACF_Msk           (0x1UL)                   /*!< ACF (Bitfield-Mask: 0x01)                             */
11165 /* ======================================================  INTRPTSTAT  ======================================================= */
11166 #define CLKGEN_INTRPTSTAT_OF_Pos          (2UL)                     /*!< OF (Bit 2)                                            */
11167 #define CLKGEN_INTRPTSTAT_OF_Msk          (0x4UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
11168 #define CLKGEN_INTRPTSTAT_ACC_Pos         (1UL)                     /*!< ACC (Bit 1)                                           */
11169 #define CLKGEN_INTRPTSTAT_ACC_Msk         (0x2UL)                   /*!< ACC (Bitfield-Mask: 0x01)                             */
11170 #define CLKGEN_INTRPTSTAT_ACF_Pos         (0UL)                     /*!< ACF (Bit 0)                                           */
11171 #define CLKGEN_INTRPTSTAT_ACF_Msk         (0x1UL)                   /*!< ACF (Bitfield-Mask: 0x01)                             */
11172 /* =======================================================  INTRPTCLR  ======================================================= */
11173 #define CLKGEN_INTRPTCLR_OF_Pos           (2UL)                     /*!< OF (Bit 2)                                            */
11174 #define CLKGEN_INTRPTCLR_OF_Msk           (0x4UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
11175 #define CLKGEN_INTRPTCLR_ACC_Pos          (1UL)                     /*!< ACC (Bit 1)                                           */
11176 #define CLKGEN_INTRPTCLR_ACC_Msk          (0x2UL)                   /*!< ACC (Bitfield-Mask: 0x01)                             */
11177 #define CLKGEN_INTRPTCLR_ACF_Pos          (0UL)                     /*!< ACF (Bit 0)                                           */
11178 #define CLKGEN_INTRPTCLR_ACF_Msk          (0x1UL)                   /*!< ACF (Bitfield-Mask: 0x01)                             */
11179 /* =======================================================  INTRPTSET  ======================================================= */
11180 #define CLKGEN_INTRPTSET_OF_Pos           (2UL)                     /*!< OF (Bit 2)                                            */
11181 #define CLKGEN_INTRPTSET_OF_Msk           (0x4UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
11182 #define CLKGEN_INTRPTSET_ACC_Pos          (1UL)                     /*!< ACC (Bit 1)                                           */
11183 #define CLKGEN_INTRPTSET_ACC_Msk          (0x2UL)                   /*!< ACC (Bitfield-Mask: 0x01)                             */
11184 #define CLKGEN_INTRPTSET_ACF_Pos          (0UL)                     /*!< ACF (Bit 0)                                           */
11185 #define CLKGEN_INTRPTSET_ACF_Msk          (0x1UL)                   /*!< ACF (Bitfield-Mask: 0x01)                             */
11186 
11187 
11188 /* =========================================================================================================================== */
11189 /* ================                                          CTIMER                                           ================ */
11190 /* =========================================================================================================================== */
11191 
11192 /* =========================================================  TMR0  ========================================================== */
11193 #define CTIMER_TMR0_CTTMRB0_Pos           (16UL)                    /*!< CTTMRB0 (Bit 16)                                      */
11194 #define CTIMER_TMR0_CTTMRB0_Msk           (0xffff0000UL)            /*!< CTTMRB0 (Bitfield-Mask: 0xffff)                       */
11195 #define CTIMER_TMR0_CTTMRA0_Pos           (0UL)                     /*!< CTTMRA0 (Bit 0)                                       */
11196 #define CTIMER_TMR0_CTTMRA0_Msk           (0xffffUL)                /*!< CTTMRA0 (Bitfield-Mask: 0xffff)                       */
11197 /* ========================================================  CMPRA0  ========================================================= */
11198 #define CTIMER_CMPRA0_CMPR1A0_Pos         (16UL)                    /*!< CMPR1A0 (Bit 16)                                      */
11199 #define CTIMER_CMPRA0_CMPR1A0_Msk         (0xffff0000UL)            /*!< CMPR1A0 (Bitfield-Mask: 0xffff)                       */
11200 #define CTIMER_CMPRA0_CMPR0A0_Pos         (0UL)                     /*!< CMPR0A0 (Bit 0)                                       */
11201 #define CTIMER_CMPRA0_CMPR0A0_Msk         (0xffffUL)                /*!< CMPR0A0 (Bitfield-Mask: 0xffff)                       */
11202 /* ========================================================  CMPRB0  ========================================================= */
11203 #define CTIMER_CMPRB0_CMPR1B0_Pos         (16UL)                    /*!< CMPR1B0 (Bit 16)                                      */
11204 #define CTIMER_CMPRB0_CMPR1B0_Msk         (0xffff0000UL)            /*!< CMPR1B0 (Bitfield-Mask: 0xffff)                       */
11205 #define CTIMER_CMPRB0_CMPR0B0_Pos         (0UL)                     /*!< CMPR0B0 (Bit 0)                                       */
11206 #define CTIMER_CMPRB0_CMPR0B0_Msk         (0xffffUL)                /*!< CMPR0B0 (Bitfield-Mask: 0xffff)                       */
11207 /* =========================================================  CTRL0  ========================================================= */
11208 #define CTIMER_CTRL0_CTLINK0_Pos          (31UL)                    /*!< CTLINK0 (Bit 31)                                      */
11209 #define CTIMER_CTRL0_CTLINK0_Msk          (0x80000000UL)            /*!< CTLINK0 (Bitfield-Mask: 0x01)                         */
11210 #define CTIMER_CTRL0_TMRB0POL_Pos         (28UL)                    /*!< TMRB0POL (Bit 28)                                     */
11211 #define CTIMER_CTRL0_TMRB0POL_Msk         (0x10000000UL)            /*!< TMRB0POL (Bitfield-Mask: 0x01)                        */
11212 #define CTIMER_CTRL0_TMRB0CLR_Pos         (27UL)                    /*!< TMRB0CLR (Bit 27)                                     */
11213 #define CTIMER_CTRL0_TMRB0CLR_Msk         (0x8000000UL)             /*!< TMRB0CLR (Bitfield-Mask: 0x01)                        */
11214 #define CTIMER_CTRL0_TMRB0IE1_Pos         (26UL)                    /*!< TMRB0IE1 (Bit 26)                                     */
11215 #define CTIMER_CTRL0_TMRB0IE1_Msk         (0x4000000UL)             /*!< TMRB0IE1 (Bitfield-Mask: 0x01)                        */
11216 #define CTIMER_CTRL0_TMRB0IE0_Pos         (25UL)                    /*!< TMRB0IE0 (Bit 25)                                     */
11217 #define CTIMER_CTRL0_TMRB0IE0_Msk         (0x2000000UL)             /*!< TMRB0IE0 (Bitfield-Mask: 0x01)                        */
11218 #define CTIMER_CTRL0_TMRB0FN_Pos          (22UL)                    /*!< TMRB0FN (Bit 22)                                      */
11219 #define CTIMER_CTRL0_TMRB0FN_Msk          (0x1c00000UL)             /*!< TMRB0FN (Bitfield-Mask: 0x07)                         */
11220 #define CTIMER_CTRL0_TMRB0CLK_Pos         (17UL)                    /*!< TMRB0CLK (Bit 17)                                     */
11221 #define CTIMER_CTRL0_TMRB0CLK_Msk         (0x3e0000UL)              /*!< TMRB0CLK (Bitfield-Mask: 0x1f)                        */
11222 #define CTIMER_CTRL0_TMRB0EN_Pos          (16UL)                    /*!< TMRB0EN (Bit 16)                                      */
11223 #define CTIMER_CTRL0_TMRB0EN_Msk          (0x10000UL)               /*!< TMRB0EN (Bitfield-Mask: 0x01)                         */
11224 #define CTIMER_CTRL0_TMRA0POL_Pos         (12UL)                    /*!< TMRA0POL (Bit 12)                                     */
11225 #define CTIMER_CTRL0_TMRA0POL_Msk         (0x1000UL)                /*!< TMRA0POL (Bitfield-Mask: 0x01)                        */
11226 #define CTIMER_CTRL0_TMRA0CLR_Pos         (11UL)                    /*!< TMRA0CLR (Bit 11)                                     */
11227 #define CTIMER_CTRL0_TMRA0CLR_Msk         (0x800UL)                 /*!< TMRA0CLR (Bitfield-Mask: 0x01)                        */
11228 #define CTIMER_CTRL0_TMRA0IE1_Pos         (10UL)                    /*!< TMRA0IE1 (Bit 10)                                     */
11229 #define CTIMER_CTRL0_TMRA0IE1_Msk         (0x400UL)                 /*!< TMRA0IE1 (Bitfield-Mask: 0x01)                        */
11230 #define CTIMER_CTRL0_TMRA0IE0_Pos         (9UL)                     /*!< TMRA0IE0 (Bit 9)                                      */
11231 #define CTIMER_CTRL0_TMRA0IE0_Msk         (0x200UL)                 /*!< TMRA0IE0 (Bitfield-Mask: 0x01)                        */
11232 #define CTIMER_CTRL0_TMRA0FN_Pos          (6UL)                     /*!< TMRA0FN (Bit 6)                                       */
11233 #define CTIMER_CTRL0_TMRA0FN_Msk          (0x1c0UL)                 /*!< TMRA0FN (Bitfield-Mask: 0x07)                         */
11234 #define CTIMER_CTRL0_TMRA0CLK_Pos         (1UL)                     /*!< TMRA0CLK (Bit 1)                                      */
11235 #define CTIMER_CTRL0_TMRA0CLK_Msk         (0x3eUL)                  /*!< TMRA0CLK (Bitfield-Mask: 0x1f)                        */
11236 #define CTIMER_CTRL0_TMRA0EN_Pos          (0UL)                     /*!< TMRA0EN (Bit 0)                                       */
11237 #define CTIMER_CTRL0_TMRA0EN_Msk          (0x1UL)                   /*!< TMRA0EN (Bitfield-Mask: 0x01)                         */
11238 /* =======================================================  CMPRAUXA0  ======================================================= */
11239 #define CTIMER_CMPRAUXA0_CMPR3A0_Pos      (16UL)                    /*!< CMPR3A0 (Bit 16)                                      */
11240 #define CTIMER_CMPRAUXA0_CMPR3A0_Msk      (0xffff0000UL)            /*!< CMPR3A0 (Bitfield-Mask: 0xffff)                       */
11241 #define CTIMER_CMPRAUXA0_CMPR2A0_Pos      (0UL)                     /*!< CMPR2A0 (Bit 0)                                       */
11242 #define CTIMER_CMPRAUXA0_CMPR2A0_Msk      (0xffffUL)                /*!< CMPR2A0 (Bitfield-Mask: 0xffff)                       */
11243 /* =======================================================  CMPRAUXB0  ======================================================= */
11244 #define CTIMER_CMPRAUXB0_CMPR3B0_Pos      (16UL)                    /*!< CMPR3B0 (Bit 16)                                      */
11245 #define CTIMER_CMPRAUXB0_CMPR3B0_Msk      (0xffff0000UL)            /*!< CMPR3B0 (Bitfield-Mask: 0xffff)                       */
11246 #define CTIMER_CMPRAUXB0_CMPR2B0_Pos      (0UL)                     /*!< CMPR2B0 (Bit 0)                                       */
11247 #define CTIMER_CMPRAUXB0_CMPR2B0_Msk      (0xffffUL)                /*!< CMPR2B0 (Bitfield-Mask: 0xffff)                       */
11248 /* =========================================================  AUX0  ========================================================== */
11249 #define CTIMER_AUX0_TMRB0EN23_Pos         (30UL)                    /*!< TMRB0EN23 (Bit 30)                                    */
11250 #define CTIMER_AUX0_TMRB0EN23_Msk         (0x40000000UL)            /*!< TMRB0EN23 (Bitfield-Mask: 0x01)                       */
11251 #define CTIMER_AUX0_TMRB0POL23_Pos        (29UL)                    /*!< TMRB0POL23 (Bit 29)                                   */
11252 #define CTIMER_AUX0_TMRB0POL23_Msk        (0x20000000UL)            /*!< TMRB0POL23 (Bitfield-Mask: 0x01)                      */
11253 #define CTIMER_AUX0_TMRB0TINV_Pos         (28UL)                    /*!< TMRB0TINV (Bit 28)                                    */
11254 #define CTIMER_AUX0_TMRB0TINV_Msk         (0x10000000UL)            /*!< TMRB0TINV (Bitfield-Mask: 0x01)                       */
11255 #define CTIMER_AUX0_TMRB0NOSYNC_Pos       (27UL)                    /*!< TMRB0NOSYNC (Bit 27)                                  */
11256 #define CTIMER_AUX0_TMRB0NOSYNC_Msk       (0x8000000UL)             /*!< TMRB0NOSYNC (Bitfield-Mask: 0x01)                     */
11257 #define CTIMER_AUX0_TMRB0TRIG_Pos         (23UL)                    /*!< TMRB0TRIG (Bit 23)                                    */
11258 #define CTIMER_AUX0_TMRB0TRIG_Msk         (0x7800000UL)             /*!< TMRB0TRIG (Bitfield-Mask: 0x0f)                       */
11259 #define CTIMER_AUX0_TMRB0LMT_Pos          (16UL)                    /*!< TMRB0LMT (Bit 16)                                     */
11260 #define CTIMER_AUX0_TMRB0LMT_Msk          (0x3f0000UL)              /*!< TMRB0LMT (Bitfield-Mask: 0x3f)                        */
11261 #define CTIMER_AUX0_TMRA0EN23_Pos         (14UL)                    /*!< TMRA0EN23 (Bit 14)                                    */
11262 #define CTIMER_AUX0_TMRA0EN23_Msk         (0x4000UL)                /*!< TMRA0EN23 (Bitfield-Mask: 0x01)                       */
11263 #define CTIMER_AUX0_TMRA0POL23_Pos        (13UL)                    /*!< TMRA0POL23 (Bit 13)                                   */
11264 #define CTIMER_AUX0_TMRA0POL23_Msk        (0x2000UL)                /*!< TMRA0POL23 (Bitfield-Mask: 0x01)                      */
11265 #define CTIMER_AUX0_TMRA0TINV_Pos         (12UL)                    /*!< TMRA0TINV (Bit 12)                                    */
11266 #define CTIMER_AUX0_TMRA0TINV_Msk         (0x1000UL)                /*!< TMRA0TINV (Bitfield-Mask: 0x01)                       */
11267 #define CTIMER_AUX0_TMRA0NOSYNC_Pos       (11UL)                    /*!< TMRA0NOSYNC (Bit 11)                                  */
11268 #define CTIMER_AUX0_TMRA0NOSYNC_Msk       (0x800UL)                 /*!< TMRA0NOSYNC (Bitfield-Mask: 0x01)                     */
11269 #define CTIMER_AUX0_TMRA0TRIG_Pos         (7UL)                     /*!< TMRA0TRIG (Bit 7)                                     */
11270 #define CTIMER_AUX0_TMRA0TRIG_Msk         (0x780UL)                 /*!< TMRA0TRIG (Bitfield-Mask: 0x0f)                       */
11271 #define CTIMER_AUX0_TMRA0LMT_Pos          (0UL)                     /*!< TMRA0LMT (Bit 0)                                      */
11272 #define CTIMER_AUX0_TMRA0LMT_Msk          (0x7fUL)                  /*!< TMRA0LMT (Bitfield-Mask: 0x7f)                        */
11273 /* =========================================================  TMR1  ========================================================== */
11274 #define CTIMER_TMR1_CTTMRB1_Pos           (16UL)                    /*!< CTTMRB1 (Bit 16)                                      */
11275 #define CTIMER_TMR1_CTTMRB1_Msk           (0xffff0000UL)            /*!< CTTMRB1 (Bitfield-Mask: 0xffff)                       */
11276 #define CTIMER_TMR1_CTTMRA1_Pos           (0UL)                     /*!< CTTMRA1 (Bit 0)                                       */
11277 #define CTIMER_TMR1_CTTMRA1_Msk           (0xffffUL)                /*!< CTTMRA1 (Bitfield-Mask: 0xffff)                       */
11278 /* ========================================================  CMPRA1  ========================================================= */
11279 #define CTIMER_CMPRA1_CMPR1A1_Pos         (16UL)                    /*!< CMPR1A1 (Bit 16)                                      */
11280 #define CTIMER_CMPRA1_CMPR1A1_Msk         (0xffff0000UL)            /*!< CMPR1A1 (Bitfield-Mask: 0xffff)                       */
11281 #define CTIMER_CMPRA1_CMPR0A1_Pos         (0UL)                     /*!< CMPR0A1 (Bit 0)                                       */
11282 #define CTIMER_CMPRA1_CMPR0A1_Msk         (0xffffUL)                /*!< CMPR0A1 (Bitfield-Mask: 0xffff)                       */
11283 /* ========================================================  CMPRB1  ========================================================= */
11284 #define CTIMER_CMPRB1_CMPR1B1_Pos         (16UL)                    /*!< CMPR1B1 (Bit 16)                                      */
11285 #define CTIMER_CMPRB1_CMPR1B1_Msk         (0xffff0000UL)            /*!< CMPR1B1 (Bitfield-Mask: 0xffff)                       */
11286 #define CTIMER_CMPRB1_CMPR0B1_Pos         (0UL)                     /*!< CMPR0B1 (Bit 0)                                       */
11287 #define CTIMER_CMPRB1_CMPR0B1_Msk         (0xffffUL)                /*!< CMPR0B1 (Bitfield-Mask: 0xffff)                       */
11288 /* =========================================================  CTRL1  ========================================================= */
11289 #define CTIMER_CTRL1_CTLINK1_Pos          (31UL)                    /*!< CTLINK1 (Bit 31)                                      */
11290 #define CTIMER_CTRL1_CTLINK1_Msk          (0x80000000UL)            /*!< CTLINK1 (Bitfield-Mask: 0x01)                         */
11291 #define CTIMER_CTRL1_TMRB1POL_Pos         (28UL)                    /*!< TMRB1POL (Bit 28)                                     */
11292 #define CTIMER_CTRL1_TMRB1POL_Msk         (0x10000000UL)            /*!< TMRB1POL (Bitfield-Mask: 0x01)                        */
11293 #define CTIMER_CTRL1_TMRB1CLR_Pos         (27UL)                    /*!< TMRB1CLR (Bit 27)                                     */
11294 #define CTIMER_CTRL1_TMRB1CLR_Msk         (0x8000000UL)             /*!< TMRB1CLR (Bitfield-Mask: 0x01)                        */
11295 #define CTIMER_CTRL1_TMRB1IE1_Pos         (26UL)                    /*!< TMRB1IE1 (Bit 26)                                     */
11296 #define CTIMER_CTRL1_TMRB1IE1_Msk         (0x4000000UL)             /*!< TMRB1IE1 (Bitfield-Mask: 0x01)                        */
11297 #define CTIMER_CTRL1_TMRB1IE0_Pos         (25UL)                    /*!< TMRB1IE0 (Bit 25)                                     */
11298 #define CTIMER_CTRL1_TMRB1IE0_Msk         (0x2000000UL)             /*!< TMRB1IE0 (Bitfield-Mask: 0x01)                        */
11299 #define CTIMER_CTRL1_TMRB1FN_Pos          (22UL)                    /*!< TMRB1FN (Bit 22)                                      */
11300 #define CTIMER_CTRL1_TMRB1FN_Msk          (0x1c00000UL)             /*!< TMRB1FN (Bitfield-Mask: 0x07)                         */
11301 #define CTIMER_CTRL1_TMRB1CLK_Pos         (17UL)                    /*!< TMRB1CLK (Bit 17)                                     */
11302 #define CTIMER_CTRL1_TMRB1CLK_Msk         (0x3e0000UL)              /*!< TMRB1CLK (Bitfield-Mask: 0x1f)                        */
11303 #define CTIMER_CTRL1_TMRB1EN_Pos          (16UL)                    /*!< TMRB1EN (Bit 16)                                      */
11304 #define CTIMER_CTRL1_TMRB1EN_Msk          (0x10000UL)               /*!< TMRB1EN (Bitfield-Mask: 0x01)                         */
11305 #define CTIMER_CTRL1_TMRA1POL_Pos         (12UL)                    /*!< TMRA1POL (Bit 12)                                     */
11306 #define CTIMER_CTRL1_TMRA1POL_Msk         (0x1000UL)                /*!< TMRA1POL (Bitfield-Mask: 0x01)                        */
11307 #define CTIMER_CTRL1_TMRA1CLR_Pos         (11UL)                    /*!< TMRA1CLR (Bit 11)                                     */
11308 #define CTIMER_CTRL1_TMRA1CLR_Msk         (0x800UL)                 /*!< TMRA1CLR (Bitfield-Mask: 0x01)                        */
11309 #define CTIMER_CTRL1_TMRA1IE1_Pos         (10UL)                    /*!< TMRA1IE1 (Bit 10)                                     */
11310 #define CTIMER_CTRL1_TMRA1IE1_Msk         (0x400UL)                 /*!< TMRA1IE1 (Bitfield-Mask: 0x01)                        */
11311 #define CTIMER_CTRL1_TMRA1IE0_Pos         (9UL)                     /*!< TMRA1IE0 (Bit 9)                                      */
11312 #define CTIMER_CTRL1_TMRA1IE0_Msk         (0x200UL)                 /*!< TMRA1IE0 (Bitfield-Mask: 0x01)                        */
11313 #define CTIMER_CTRL1_TMRA1FN_Pos          (6UL)                     /*!< TMRA1FN (Bit 6)                                       */
11314 #define CTIMER_CTRL1_TMRA1FN_Msk          (0x1c0UL)                 /*!< TMRA1FN (Bitfield-Mask: 0x07)                         */
11315 #define CTIMER_CTRL1_TMRA1CLK_Pos         (1UL)                     /*!< TMRA1CLK (Bit 1)                                      */
11316 #define CTIMER_CTRL1_TMRA1CLK_Msk         (0x3eUL)                  /*!< TMRA1CLK (Bitfield-Mask: 0x1f)                        */
11317 #define CTIMER_CTRL1_TMRA1EN_Pos          (0UL)                     /*!< TMRA1EN (Bit 0)                                       */
11318 #define CTIMER_CTRL1_TMRA1EN_Msk          (0x1UL)                   /*!< TMRA1EN (Bitfield-Mask: 0x01)                         */
11319 /* =======================================================  CMPRAUXA1  ======================================================= */
11320 #define CTIMER_CMPRAUXA1_CMPR3A1_Pos      (16UL)                    /*!< CMPR3A1 (Bit 16)                                      */
11321 #define CTIMER_CMPRAUXA1_CMPR3A1_Msk      (0xffff0000UL)            /*!< CMPR3A1 (Bitfield-Mask: 0xffff)                       */
11322 #define CTIMER_CMPRAUXA1_CMPR2A1_Pos      (0UL)                     /*!< CMPR2A1 (Bit 0)                                       */
11323 #define CTIMER_CMPRAUXA1_CMPR2A1_Msk      (0xffffUL)                /*!< CMPR2A1 (Bitfield-Mask: 0xffff)                       */
11324 /* =======================================================  CMPRAUXB1  ======================================================= */
11325 #define CTIMER_CMPRAUXB1_CMPR3B1_Pos      (16UL)                    /*!< CMPR3B1 (Bit 16)                                      */
11326 #define CTIMER_CMPRAUXB1_CMPR3B1_Msk      (0xffff0000UL)            /*!< CMPR3B1 (Bitfield-Mask: 0xffff)                       */
11327 #define CTIMER_CMPRAUXB1_CMPR2B1_Pos      (0UL)                     /*!< CMPR2B1 (Bit 0)                                       */
11328 #define CTIMER_CMPRAUXB1_CMPR2B1_Msk      (0xffffUL)                /*!< CMPR2B1 (Bitfield-Mask: 0xffff)                       */
11329 /* =========================================================  AUX1  ========================================================== */
11330 #define CTIMER_AUX1_TMRB1EN23_Pos         (30UL)                    /*!< TMRB1EN23 (Bit 30)                                    */
11331 #define CTIMER_AUX1_TMRB1EN23_Msk         (0x40000000UL)            /*!< TMRB1EN23 (Bitfield-Mask: 0x01)                       */
11332 #define CTIMER_AUX1_TMRB1POL23_Pos        (29UL)                    /*!< TMRB1POL23 (Bit 29)                                   */
11333 #define CTIMER_AUX1_TMRB1POL23_Msk        (0x20000000UL)            /*!< TMRB1POL23 (Bitfield-Mask: 0x01)                      */
11334 #define CTIMER_AUX1_TMRB1TINV_Pos         (28UL)                    /*!< TMRB1TINV (Bit 28)                                    */
11335 #define CTIMER_AUX1_TMRB1TINV_Msk         (0x10000000UL)            /*!< TMRB1TINV (Bitfield-Mask: 0x01)                       */
11336 #define CTIMER_AUX1_TMRB1NOSYNC_Pos       (27UL)                    /*!< TMRB1NOSYNC (Bit 27)                                  */
11337 #define CTIMER_AUX1_TMRB1NOSYNC_Msk       (0x8000000UL)             /*!< TMRB1NOSYNC (Bitfield-Mask: 0x01)                     */
11338 #define CTIMER_AUX1_TMRB1TRIG_Pos         (23UL)                    /*!< TMRB1TRIG (Bit 23)                                    */
11339 #define CTIMER_AUX1_TMRB1TRIG_Msk         (0x7800000UL)             /*!< TMRB1TRIG (Bitfield-Mask: 0x0f)                       */
11340 #define CTIMER_AUX1_TMRB1LMT_Pos          (16UL)                    /*!< TMRB1LMT (Bit 16)                                     */
11341 #define CTIMER_AUX1_TMRB1LMT_Msk          (0x3f0000UL)              /*!< TMRB1LMT (Bitfield-Mask: 0x3f)                        */
11342 #define CTIMER_AUX1_TMRA1EN23_Pos         (14UL)                    /*!< TMRA1EN23 (Bit 14)                                    */
11343 #define CTIMER_AUX1_TMRA1EN23_Msk         (0x4000UL)                /*!< TMRA1EN23 (Bitfield-Mask: 0x01)                       */
11344 #define CTIMER_AUX1_TMRA1POL23_Pos        (13UL)                    /*!< TMRA1POL23 (Bit 13)                                   */
11345 #define CTIMER_AUX1_TMRA1POL23_Msk        (0x2000UL)                /*!< TMRA1POL23 (Bitfield-Mask: 0x01)                      */
11346 #define CTIMER_AUX1_TMRA1TINV_Pos         (12UL)                    /*!< TMRA1TINV (Bit 12)                                    */
11347 #define CTIMER_AUX1_TMRA1TINV_Msk         (0x1000UL)                /*!< TMRA1TINV (Bitfield-Mask: 0x01)                       */
11348 #define CTIMER_AUX1_TMRA1NOSYNC_Pos       (11UL)                    /*!< TMRA1NOSYNC (Bit 11)                                  */
11349 #define CTIMER_AUX1_TMRA1NOSYNC_Msk       (0x800UL)                 /*!< TMRA1NOSYNC (Bitfield-Mask: 0x01)                     */
11350 #define CTIMER_AUX1_TMRA1TRIG_Pos         (7UL)                     /*!< TMRA1TRIG (Bit 7)                                     */
11351 #define CTIMER_AUX1_TMRA1TRIG_Msk         (0x780UL)                 /*!< TMRA1TRIG (Bitfield-Mask: 0x0f)                       */
11352 #define CTIMER_AUX1_TMRA1LMT_Pos          (0UL)                     /*!< TMRA1LMT (Bit 0)                                      */
11353 #define CTIMER_AUX1_TMRA1LMT_Msk          (0x7fUL)                  /*!< TMRA1LMT (Bitfield-Mask: 0x7f)                        */
11354 /* =========================================================  TMR2  ========================================================== */
11355 #define CTIMER_TMR2_CTTMRB2_Pos           (16UL)                    /*!< CTTMRB2 (Bit 16)                                      */
11356 #define CTIMER_TMR2_CTTMRB2_Msk           (0xffff0000UL)            /*!< CTTMRB2 (Bitfield-Mask: 0xffff)                       */
11357 #define CTIMER_TMR2_CTTMRA2_Pos           (0UL)                     /*!< CTTMRA2 (Bit 0)                                       */
11358 #define CTIMER_TMR2_CTTMRA2_Msk           (0xffffUL)                /*!< CTTMRA2 (Bitfield-Mask: 0xffff)                       */
11359 /* ========================================================  CMPRA2  ========================================================= */
11360 #define CTIMER_CMPRA2_CMPR1A2_Pos         (16UL)                    /*!< CMPR1A2 (Bit 16)                                      */
11361 #define CTIMER_CMPRA2_CMPR1A2_Msk         (0xffff0000UL)            /*!< CMPR1A2 (Bitfield-Mask: 0xffff)                       */
11362 #define CTIMER_CMPRA2_CMPR0A2_Pos         (0UL)                     /*!< CMPR0A2 (Bit 0)                                       */
11363 #define CTIMER_CMPRA2_CMPR0A2_Msk         (0xffffUL)                /*!< CMPR0A2 (Bitfield-Mask: 0xffff)                       */
11364 /* ========================================================  CMPRB2  ========================================================= */
11365 #define CTIMER_CMPRB2_CMPR1B2_Pos         (16UL)                    /*!< CMPR1B2 (Bit 16)                                      */
11366 #define CTIMER_CMPRB2_CMPR1B2_Msk         (0xffff0000UL)            /*!< CMPR1B2 (Bitfield-Mask: 0xffff)                       */
11367 #define CTIMER_CMPRB2_CMPR0B2_Pos         (0UL)                     /*!< CMPR0B2 (Bit 0)                                       */
11368 #define CTIMER_CMPRB2_CMPR0B2_Msk         (0xffffUL)                /*!< CMPR0B2 (Bitfield-Mask: 0xffff)                       */
11369 /* =========================================================  CTRL2  ========================================================= */
11370 #define CTIMER_CTRL2_CTLINK2_Pos          (31UL)                    /*!< CTLINK2 (Bit 31)                                      */
11371 #define CTIMER_CTRL2_CTLINK2_Msk          (0x80000000UL)            /*!< CTLINK2 (Bitfield-Mask: 0x01)                         */
11372 #define CTIMER_CTRL2_TMRB2POL_Pos         (28UL)                    /*!< TMRB2POL (Bit 28)                                     */
11373 #define CTIMER_CTRL2_TMRB2POL_Msk         (0x10000000UL)            /*!< TMRB2POL (Bitfield-Mask: 0x01)                        */
11374 #define CTIMER_CTRL2_TMRB2CLR_Pos         (27UL)                    /*!< TMRB2CLR (Bit 27)                                     */
11375 #define CTIMER_CTRL2_TMRB2CLR_Msk         (0x8000000UL)             /*!< TMRB2CLR (Bitfield-Mask: 0x01)                        */
11376 #define CTIMER_CTRL2_TMRB2IE1_Pos         (26UL)                    /*!< TMRB2IE1 (Bit 26)                                     */
11377 #define CTIMER_CTRL2_TMRB2IE1_Msk         (0x4000000UL)             /*!< TMRB2IE1 (Bitfield-Mask: 0x01)                        */
11378 #define CTIMER_CTRL2_TMRB2IE0_Pos         (25UL)                    /*!< TMRB2IE0 (Bit 25)                                     */
11379 #define CTIMER_CTRL2_TMRB2IE0_Msk         (0x2000000UL)             /*!< TMRB2IE0 (Bitfield-Mask: 0x01)                        */
11380 #define CTIMER_CTRL2_TMRB2FN_Pos          (22UL)                    /*!< TMRB2FN (Bit 22)                                      */
11381 #define CTIMER_CTRL2_TMRB2FN_Msk          (0x1c00000UL)             /*!< TMRB2FN (Bitfield-Mask: 0x07)                         */
11382 #define CTIMER_CTRL2_TMRB2CLK_Pos         (17UL)                    /*!< TMRB2CLK (Bit 17)                                     */
11383 #define CTIMER_CTRL2_TMRB2CLK_Msk         (0x3e0000UL)              /*!< TMRB2CLK (Bitfield-Mask: 0x1f)                        */
11384 #define CTIMER_CTRL2_TMRB2EN_Pos          (16UL)                    /*!< TMRB2EN (Bit 16)                                      */
11385 #define CTIMER_CTRL2_TMRB2EN_Msk          (0x10000UL)               /*!< TMRB2EN (Bitfield-Mask: 0x01)                         */
11386 #define CTIMER_CTRL2_TMRA2POL_Pos         (12UL)                    /*!< TMRA2POL (Bit 12)                                     */
11387 #define CTIMER_CTRL2_TMRA2POL_Msk         (0x1000UL)                /*!< TMRA2POL (Bitfield-Mask: 0x01)                        */
11388 #define CTIMER_CTRL2_TMRA2CLR_Pos         (11UL)                    /*!< TMRA2CLR (Bit 11)                                     */
11389 #define CTIMER_CTRL2_TMRA2CLR_Msk         (0x800UL)                 /*!< TMRA2CLR (Bitfield-Mask: 0x01)                        */
11390 #define CTIMER_CTRL2_TMRA2IE1_Pos         (10UL)                    /*!< TMRA2IE1 (Bit 10)                                     */
11391 #define CTIMER_CTRL2_TMRA2IE1_Msk         (0x400UL)                 /*!< TMRA2IE1 (Bitfield-Mask: 0x01)                        */
11392 #define CTIMER_CTRL2_TMRA2IE0_Pos         (9UL)                     /*!< TMRA2IE0 (Bit 9)                                      */
11393 #define CTIMER_CTRL2_TMRA2IE0_Msk         (0x200UL)                 /*!< TMRA2IE0 (Bitfield-Mask: 0x01)                        */
11394 #define CTIMER_CTRL2_TMRA2FN_Pos          (6UL)                     /*!< TMRA2FN (Bit 6)                                       */
11395 #define CTIMER_CTRL2_TMRA2FN_Msk          (0x1c0UL)                 /*!< TMRA2FN (Bitfield-Mask: 0x07)                         */
11396 #define CTIMER_CTRL2_TMRA2CLK_Pos         (1UL)                     /*!< TMRA2CLK (Bit 1)                                      */
11397 #define CTIMER_CTRL2_TMRA2CLK_Msk         (0x3eUL)                  /*!< TMRA2CLK (Bitfield-Mask: 0x1f)                        */
11398 #define CTIMER_CTRL2_TMRA2EN_Pos          (0UL)                     /*!< TMRA2EN (Bit 0)                                       */
11399 #define CTIMER_CTRL2_TMRA2EN_Msk          (0x1UL)                   /*!< TMRA2EN (Bitfield-Mask: 0x01)                         */
11400 /* =======================================================  CMPRAUXA2  ======================================================= */
11401 #define CTIMER_CMPRAUXA2_CMPR3A2_Pos      (16UL)                    /*!< CMPR3A2 (Bit 16)                                      */
11402 #define CTIMER_CMPRAUXA2_CMPR3A2_Msk      (0xffff0000UL)            /*!< CMPR3A2 (Bitfield-Mask: 0xffff)                       */
11403 #define CTIMER_CMPRAUXA2_CMPR2A2_Pos      (0UL)                     /*!< CMPR2A2 (Bit 0)                                       */
11404 #define CTIMER_CMPRAUXA2_CMPR2A2_Msk      (0xffffUL)                /*!< CMPR2A2 (Bitfield-Mask: 0xffff)                       */
11405 /* =======================================================  CMPRAUXB2  ======================================================= */
11406 #define CTIMER_CMPRAUXB2_CMPR3B2_Pos      (16UL)                    /*!< CMPR3B2 (Bit 16)                                      */
11407 #define CTIMER_CMPRAUXB2_CMPR3B2_Msk      (0xffff0000UL)            /*!< CMPR3B2 (Bitfield-Mask: 0xffff)                       */
11408 #define CTIMER_CMPRAUXB2_CMPR2B2_Pos      (0UL)                     /*!< CMPR2B2 (Bit 0)                                       */
11409 #define CTIMER_CMPRAUXB2_CMPR2B2_Msk      (0xffffUL)                /*!< CMPR2B2 (Bitfield-Mask: 0xffff)                       */
11410 /* =========================================================  AUX2  ========================================================== */
11411 #define CTIMER_AUX2_TMRB2EN23_Pos         (30UL)                    /*!< TMRB2EN23 (Bit 30)                                    */
11412 #define CTIMER_AUX2_TMRB2EN23_Msk         (0x40000000UL)            /*!< TMRB2EN23 (Bitfield-Mask: 0x01)                       */
11413 #define CTIMER_AUX2_TMRB2POL23_Pos        (29UL)                    /*!< TMRB2POL23 (Bit 29)                                   */
11414 #define CTIMER_AUX2_TMRB2POL23_Msk        (0x20000000UL)            /*!< TMRB2POL23 (Bitfield-Mask: 0x01)                      */
11415 #define CTIMER_AUX2_TMRB2TINV_Pos         (28UL)                    /*!< TMRB2TINV (Bit 28)                                    */
11416 #define CTIMER_AUX2_TMRB2TINV_Msk         (0x10000000UL)            /*!< TMRB2TINV (Bitfield-Mask: 0x01)                       */
11417 #define CTIMER_AUX2_TMRB2NOSYNC_Pos       (27UL)                    /*!< TMRB2NOSYNC (Bit 27)                                  */
11418 #define CTIMER_AUX2_TMRB2NOSYNC_Msk       (0x8000000UL)             /*!< TMRB2NOSYNC (Bitfield-Mask: 0x01)                     */
11419 #define CTIMER_AUX2_TMRB2TRIG_Pos         (23UL)                    /*!< TMRB2TRIG (Bit 23)                                    */
11420 #define CTIMER_AUX2_TMRB2TRIG_Msk         (0x7800000UL)             /*!< TMRB2TRIG (Bitfield-Mask: 0x0f)                       */
11421 #define CTIMER_AUX2_TMRB2LMT_Pos          (16UL)                    /*!< TMRB2LMT (Bit 16)                                     */
11422 #define CTIMER_AUX2_TMRB2LMT_Msk          (0x3f0000UL)              /*!< TMRB2LMT (Bitfield-Mask: 0x3f)                        */
11423 #define CTIMER_AUX2_TMRA2EN23_Pos         (14UL)                    /*!< TMRA2EN23 (Bit 14)                                    */
11424 #define CTIMER_AUX2_TMRA2EN23_Msk         (0x4000UL)                /*!< TMRA2EN23 (Bitfield-Mask: 0x01)                       */
11425 #define CTIMER_AUX2_TMRA2POL23_Pos        (13UL)                    /*!< TMRA2POL23 (Bit 13)                                   */
11426 #define CTIMER_AUX2_TMRA2POL23_Msk        (0x2000UL)                /*!< TMRA2POL23 (Bitfield-Mask: 0x01)                      */
11427 #define CTIMER_AUX2_TMRA2TINV_Pos         (12UL)                    /*!< TMRA2TINV (Bit 12)                                    */
11428 #define CTIMER_AUX2_TMRA2TINV_Msk         (0x1000UL)                /*!< TMRA2TINV (Bitfield-Mask: 0x01)                       */
11429 #define CTIMER_AUX2_TMRA2NOSYNC_Pos       (11UL)                    /*!< TMRA2NOSYNC (Bit 11)                                  */
11430 #define CTIMER_AUX2_TMRA2NOSYNC_Msk       (0x800UL)                 /*!< TMRA2NOSYNC (Bitfield-Mask: 0x01)                     */
11431 #define CTIMER_AUX2_TMRA2TRIG_Pos         (7UL)                     /*!< TMRA2TRIG (Bit 7)                                     */
11432 #define CTIMER_AUX2_TMRA2TRIG_Msk         (0x780UL)                 /*!< TMRA2TRIG (Bitfield-Mask: 0x0f)                       */
11433 #define CTIMER_AUX2_TMRA2LMT_Pos          (0UL)                     /*!< TMRA2LMT (Bit 0)                                      */
11434 #define CTIMER_AUX2_TMRA2LMT_Msk          (0x7fUL)                  /*!< TMRA2LMT (Bitfield-Mask: 0x7f)                        */
11435 /* =========================================================  TMR3  ========================================================== */
11436 #define CTIMER_TMR3_CTTMRB3_Pos           (16UL)                    /*!< CTTMRB3 (Bit 16)                                      */
11437 #define CTIMER_TMR3_CTTMRB3_Msk           (0xffff0000UL)            /*!< CTTMRB3 (Bitfield-Mask: 0xffff)                       */
11438 #define CTIMER_TMR3_CTTMRA3_Pos           (0UL)                     /*!< CTTMRA3 (Bit 0)                                       */
11439 #define CTIMER_TMR3_CTTMRA3_Msk           (0xffffUL)                /*!< CTTMRA3 (Bitfield-Mask: 0xffff)                       */
11440 /* ========================================================  CMPRA3  ========================================================= */
11441 #define CTIMER_CMPRA3_CMPR1A3_Pos         (16UL)                    /*!< CMPR1A3 (Bit 16)                                      */
11442 #define CTIMER_CMPRA3_CMPR1A3_Msk         (0xffff0000UL)            /*!< CMPR1A3 (Bitfield-Mask: 0xffff)                       */
11443 #define CTIMER_CMPRA3_CMPR0A3_Pos         (0UL)                     /*!< CMPR0A3 (Bit 0)                                       */
11444 #define CTIMER_CMPRA3_CMPR0A3_Msk         (0xffffUL)                /*!< CMPR0A3 (Bitfield-Mask: 0xffff)                       */
11445 /* ========================================================  CMPRB3  ========================================================= */
11446 #define CTIMER_CMPRB3_CMPR1B3_Pos         (16UL)                    /*!< CMPR1B3 (Bit 16)                                      */
11447 #define CTIMER_CMPRB3_CMPR1B3_Msk         (0xffff0000UL)            /*!< CMPR1B3 (Bitfield-Mask: 0xffff)                       */
11448 #define CTIMER_CMPRB3_CMPR0B3_Pos         (0UL)                     /*!< CMPR0B3 (Bit 0)                                       */
11449 #define CTIMER_CMPRB3_CMPR0B3_Msk         (0xffffUL)                /*!< CMPR0B3 (Bitfield-Mask: 0xffff)                       */
11450 /* =========================================================  CTRL3  ========================================================= */
11451 #define CTIMER_CTRL3_CTLINK3_Pos          (31UL)                    /*!< CTLINK3 (Bit 31)                                      */
11452 #define CTIMER_CTRL3_CTLINK3_Msk          (0x80000000UL)            /*!< CTLINK3 (Bitfield-Mask: 0x01)                         */
11453 #define CTIMER_CTRL3_TMRB3POL_Pos         (28UL)                    /*!< TMRB3POL (Bit 28)                                     */
11454 #define CTIMER_CTRL3_TMRB3POL_Msk         (0x10000000UL)            /*!< TMRB3POL (Bitfield-Mask: 0x01)                        */
11455 #define CTIMER_CTRL3_TMRB3CLR_Pos         (27UL)                    /*!< TMRB3CLR (Bit 27)                                     */
11456 #define CTIMER_CTRL3_TMRB3CLR_Msk         (0x8000000UL)             /*!< TMRB3CLR (Bitfield-Mask: 0x01)                        */
11457 #define CTIMER_CTRL3_TMRB3IE1_Pos         (26UL)                    /*!< TMRB3IE1 (Bit 26)                                     */
11458 #define CTIMER_CTRL3_TMRB3IE1_Msk         (0x4000000UL)             /*!< TMRB3IE1 (Bitfield-Mask: 0x01)                        */
11459 #define CTIMER_CTRL3_TMRB3IE0_Pos         (25UL)                    /*!< TMRB3IE0 (Bit 25)                                     */
11460 #define CTIMER_CTRL3_TMRB3IE0_Msk         (0x2000000UL)             /*!< TMRB3IE0 (Bitfield-Mask: 0x01)                        */
11461 #define CTIMER_CTRL3_TMRB3FN_Pos          (22UL)                    /*!< TMRB3FN (Bit 22)                                      */
11462 #define CTIMER_CTRL3_TMRB3FN_Msk          (0x1c00000UL)             /*!< TMRB3FN (Bitfield-Mask: 0x07)                         */
11463 #define CTIMER_CTRL3_TMRB3CLK_Pos         (17UL)                    /*!< TMRB3CLK (Bit 17)                                     */
11464 #define CTIMER_CTRL3_TMRB3CLK_Msk         (0x3e0000UL)              /*!< TMRB3CLK (Bitfield-Mask: 0x1f)                        */
11465 #define CTIMER_CTRL3_TMRB3EN_Pos          (16UL)                    /*!< TMRB3EN (Bit 16)                                      */
11466 #define CTIMER_CTRL3_TMRB3EN_Msk          (0x10000UL)               /*!< TMRB3EN (Bitfield-Mask: 0x01)                         */
11467 #define CTIMER_CTRL3_ADCEN_Pos            (15UL)                    /*!< ADCEN (Bit 15)                                        */
11468 #define CTIMER_CTRL3_ADCEN_Msk            (0x8000UL)                /*!< ADCEN (Bitfield-Mask: 0x01)                           */
11469 #define CTIMER_CTRL3_TMRA3POL_Pos         (12UL)                    /*!< TMRA3POL (Bit 12)                                     */
11470 #define CTIMER_CTRL3_TMRA3POL_Msk         (0x1000UL)                /*!< TMRA3POL (Bitfield-Mask: 0x01)                        */
11471 #define CTIMER_CTRL3_TMRA3CLR_Pos         (11UL)                    /*!< TMRA3CLR (Bit 11)                                     */
11472 #define CTIMER_CTRL3_TMRA3CLR_Msk         (0x800UL)                 /*!< TMRA3CLR (Bitfield-Mask: 0x01)                        */
11473 #define CTIMER_CTRL3_TMRA3IE1_Pos         (10UL)                    /*!< TMRA3IE1 (Bit 10)                                     */
11474 #define CTIMER_CTRL3_TMRA3IE1_Msk         (0x400UL)                 /*!< TMRA3IE1 (Bitfield-Mask: 0x01)                        */
11475 #define CTIMER_CTRL3_TMRA3IE0_Pos         (9UL)                     /*!< TMRA3IE0 (Bit 9)                                      */
11476 #define CTIMER_CTRL3_TMRA3IE0_Msk         (0x200UL)                 /*!< TMRA3IE0 (Bitfield-Mask: 0x01)                        */
11477 #define CTIMER_CTRL3_TMRA3FN_Pos          (6UL)                     /*!< TMRA3FN (Bit 6)                                       */
11478 #define CTIMER_CTRL3_TMRA3FN_Msk          (0x1c0UL)                 /*!< TMRA3FN (Bitfield-Mask: 0x07)                         */
11479 #define CTIMER_CTRL3_TMRA3CLK_Pos         (1UL)                     /*!< TMRA3CLK (Bit 1)                                      */
11480 #define CTIMER_CTRL3_TMRA3CLK_Msk         (0x3eUL)                  /*!< TMRA3CLK (Bitfield-Mask: 0x1f)                        */
11481 #define CTIMER_CTRL3_TMRA3EN_Pos          (0UL)                     /*!< TMRA3EN (Bit 0)                                       */
11482 #define CTIMER_CTRL3_TMRA3EN_Msk          (0x1UL)                   /*!< TMRA3EN (Bitfield-Mask: 0x01)                         */
11483 /* =======================================================  CMPRAUXA3  ======================================================= */
11484 #define CTIMER_CMPRAUXA3_CMPR3A3_Pos      (16UL)                    /*!< CMPR3A3 (Bit 16)                                      */
11485 #define CTIMER_CMPRAUXA3_CMPR3A3_Msk      (0xffff0000UL)            /*!< CMPR3A3 (Bitfield-Mask: 0xffff)                       */
11486 #define CTIMER_CMPRAUXA3_CMPR2A3_Pos      (0UL)                     /*!< CMPR2A3 (Bit 0)                                       */
11487 #define CTIMER_CMPRAUXA3_CMPR2A3_Msk      (0xffffUL)                /*!< CMPR2A3 (Bitfield-Mask: 0xffff)                       */
11488 /* =======================================================  CMPRAUXB3  ======================================================= */
11489 #define CTIMER_CMPRAUXB3_CMPR3B3_Pos      (16UL)                    /*!< CMPR3B3 (Bit 16)                                      */
11490 #define CTIMER_CMPRAUXB3_CMPR3B3_Msk      (0xffff0000UL)            /*!< CMPR3B3 (Bitfield-Mask: 0xffff)                       */
11491 #define CTIMER_CMPRAUXB3_CMPR2B3_Pos      (0UL)                     /*!< CMPR2B3 (Bit 0)                                       */
11492 #define CTIMER_CMPRAUXB3_CMPR2B3_Msk      (0xffffUL)                /*!< CMPR2B3 (Bitfield-Mask: 0xffff)                       */
11493 /* =========================================================  AUX3  ========================================================== */
11494 #define CTIMER_AUX3_TMRB3EN23_Pos         (30UL)                    /*!< TMRB3EN23 (Bit 30)                                    */
11495 #define CTIMER_AUX3_TMRB3EN23_Msk         (0x40000000UL)            /*!< TMRB3EN23 (Bitfield-Mask: 0x01)                       */
11496 #define CTIMER_AUX3_TMRB3POL23_Pos        (29UL)                    /*!< TMRB3POL23 (Bit 29)                                   */
11497 #define CTIMER_AUX3_TMRB3POL23_Msk        (0x20000000UL)            /*!< TMRB3POL23 (Bitfield-Mask: 0x01)                      */
11498 #define CTIMER_AUX3_TMRB3TINV_Pos         (28UL)                    /*!< TMRB3TINV (Bit 28)                                    */
11499 #define CTIMER_AUX3_TMRB3TINV_Msk         (0x10000000UL)            /*!< TMRB3TINV (Bitfield-Mask: 0x01)                       */
11500 #define CTIMER_AUX3_TMRB3NOSYNC_Pos       (27UL)                    /*!< TMRB3NOSYNC (Bit 27)                                  */
11501 #define CTIMER_AUX3_TMRB3NOSYNC_Msk       (0x8000000UL)             /*!< TMRB3NOSYNC (Bitfield-Mask: 0x01)                     */
11502 #define CTIMER_AUX3_TMRB3TRIG_Pos         (23UL)                    /*!< TMRB3TRIG (Bit 23)                                    */
11503 #define CTIMER_AUX3_TMRB3TRIG_Msk         (0x7800000UL)             /*!< TMRB3TRIG (Bitfield-Mask: 0x0f)                       */
11504 #define CTIMER_AUX3_TMRB3LMT_Pos          (16UL)                    /*!< TMRB3LMT (Bit 16)                                     */
11505 #define CTIMER_AUX3_TMRB3LMT_Msk          (0x3f0000UL)              /*!< TMRB3LMT (Bitfield-Mask: 0x3f)                        */
11506 #define CTIMER_AUX3_TMRA3EN23_Pos         (14UL)                    /*!< TMRA3EN23 (Bit 14)                                    */
11507 #define CTIMER_AUX3_TMRA3EN23_Msk         (0x4000UL)                /*!< TMRA3EN23 (Bitfield-Mask: 0x01)                       */
11508 #define CTIMER_AUX3_TMRA3POL23_Pos        (13UL)                    /*!< TMRA3POL23 (Bit 13)                                   */
11509 #define CTIMER_AUX3_TMRA3POL23_Msk        (0x2000UL)                /*!< TMRA3POL23 (Bitfield-Mask: 0x01)                      */
11510 #define CTIMER_AUX3_TMRA3TINV_Pos         (12UL)                    /*!< TMRA3TINV (Bit 12)                                    */
11511 #define CTIMER_AUX3_TMRA3TINV_Msk         (0x1000UL)                /*!< TMRA3TINV (Bitfield-Mask: 0x01)                       */
11512 #define CTIMER_AUX3_TMRA3NOSYNC_Pos       (11UL)                    /*!< TMRA3NOSYNC (Bit 11)                                  */
11513 #define CTIMER_AUX3_TMRA3NOSYNC_Msk       (0x800UL)                 /*!< TMRA3NOSYNC (Bitfield-Mask: 0x01)                     */
11514 #define CTIMER_AUX3_TMRA3TRIG_Pos         (7UL)                     /*!< TMRA3TRIG (Bit 7)                                     */
11515 #define CTIMER_AUX3_TMRA3TRIG_Msk         (0x780UL)                 /*!< TMRA3TRIG (Bitfield-Mask: 0x0f)                       */
11516 #define CTIMER_AUX3_TMRA3LMT_Pos          (0UL)                     /*!< TMRA3LMT (Bit 0)                                      */
11517 #define CTIMER_AUX3_TMRA3LMT_Msk          (0x7fUL)                  /*!< TMRA3LMT (Bitfield-Mask: 0x7f)                        */
11518 /* =========================================================  TMR4  ========================================================== */
11519 #define CTIMER_TMR4_CTTMRB4_Pos           (16UL)                    /*!< CTTMRB4 (Bit 16)                                      */
11520 #define CTIMER_TMR4_CTTMRB4_Msk           (0xffff0000UL)            /*!< CTTMRB4 (Bitfield-Mask: 0xffff)                       */
11521 #define CTIMER_TMR4_CTTMRA4_Pos           (0UL)                     /*!< CTTMRA4 (Bit 0)                                       */
11522 #define CTIMER_TMR4_CTTMRA4_Msk           (0xffffUL)                /*!< CTTMRA4 (Bitfield-Mask: 0xffff)                       */
11523 /* ========================================================  CMPRA4  ========================================================= */
11524 #define CTIMER_CMPRA4_CMPR1A4_Pos         (16UL)                    /*!< CMPR1A4 (Bit 16)                                      */
11525 #define CTIMER_CMPRA4_CMPR1A4_Msk         (0xffff0000UL)            /*!< CMPR1A4 (Bitfield-Mask: 0xffff)                       */
11526 #define CTIMER_CMPRA4_CMPR0A4_Pos         (0UL)                     /*!< CMPR0A4 (Bit 0)                                       */
11527 #define CTIMER_CMPRA4_CMPR0A4_Msk         (0xffffUL)                /*!< CMPR0A4 (Bitfield-Mask: 0xffff)                       */
11528 /* ========================================================  CMPRB4  ========================================================= */
11529 #define CTIMER_CMPRB4_CMPR1B4_Pos         (16UL)                    /*!< CMPR1B4 (Bit 16)                                      */
11530 #define CTIMER_CMPRB4_CMPR1B4_Msk         (0xffff0000UL)            /*!< CMPR1B4 (Bitfield-Mask: 0xffff)                       */
11531 #define CTIMER_CMPRB4_CMPR0B4_Pos         (0UL)                     /*!< CMPR0B4 (Bit 0)                                       */
11532 #define CTIMER_CMPRB4_CMPR0B4_Msk         (0xffffUL)                /*!< CMPR0B4 (Bitfield-Mask: 0xffff)                       */
11533 /* =========================================================  CTRL4  ========================================================= */
11534 #define CTIMER_CTRL4_CTLINK4_Pos          (31UL)                    /*!< CTLINK4 (Bit 31)                                      */
11535 #define CTIMER_CTRL4_CTLINK4_Msk          (0x80000000UL)            /*!< CTLINK4 (Bitfield-Mask: 0x01)                         */
11536 #define CTIMER_CTRL4_TMRB4POL_Pos         (28UL)                    /*!< TMRB4POL (Bit 28)                                     */
11537 #define CTIMER_CTRL4_TMRB4POL_Msk         (0x10000000UL)            /*!< TMRB4POL (Bitfield-Mask: 0x01)                        */
11538 #define CTIMER_CTRL4_TMRB4CLR_Pos         (27UL)                    /*!< TMRB4CLR (Bit 27)                                     */
11539 #define CTIMER_CTRL4_TMRB4CLR_Msk         (0x8000000UL)             /*!< TMRB4CLR (Bitfield-Mask: 0x01)                        */
11540 #define CTIMER_CTRL4_TMRB4IE1_Pos         (26UL)                    /*!< TMRB4IE1 (Bit 26)                                     */
11541 #define CTIMER_CTRL4_TMRB4IE1_Msk         (0x4000000UL)             /*!< TMRB4IE1 (Bitfield-Mask: 0x01)                        */
11542 #define CTIMER_CTRL4_TMRB4IE0_Pos         (25UL)                    /*!< TMRB4IE0 (Bit 25)                                     */
11543 #define CTIMER_CTRL4_TMRB4IE0_Msk         (0x2000000UL)             /*!< TMRB4IE0 (Bitfield-Mask: 0x01)                        */
11544 #define CTIMER_CTRL4_TMRB4FN_Pos          (22UL)                    /*!< TMRB4FN (Bit 22)                                      */
11545 #define CTIMER_CTRL4_TMRB4FN_Msk          (0x1c00000UL)             /*!< TMRB4FN (Bitfield-Mask: 0x07)                         */
11546 #define CTIMER_CTRL4_TMRB4CLK_Pos         (17UL)                    /*!< TMRB4CLK (Bit 17)                                     */
11547 #define CTIMER_CTRL4_TMRB4CLK_Msk         (0x3e0000UL)              /*!< TMRB4CLK (Bitfield-Mask: 0x1f)                        */
11548 #define CTIMER_CTRL4_TMRB4EN_Pos          (16UL)                    /*!< TMRB4EN (Bit 16)                                      */
11549 #define CTIMER_CTRL4_TMRB4EN_Msk          (0x10000UL)               /*!< TMRB4EN (Bitfield-Mask: 0x01)                         */
11550 #define CTIMER_CTRL4_TMRA4POL_Pos         (12UL)                    /*!< TMRA4POL (Bit 12)                                     */
11551 #define CTIMER_CTRL4_TMRA4POL_Msk         (0x1000UL)                /*!< TMRA4POL (Bitfield-Mask: 0x01)                        */
11552 #define CTIMER_CTRL4_TMRA4CLR_Pos         (11UL)                    /*!< TMRA4CLR (Bit 11)                                     */
11553 #define CTIMER_CTRL4_TMRA4CLR_Msk         (0x800UL)                 /*!< TMRA4CLR (Bitfield-Mask: 0x01)                        */
11554 #define CTIMER_CTRL4_TMRA4IE1_Pos         (10UL)                    /*!< TMRA4IE1 (Bit 10)                                     */
11555 #define CTIMER_CTRL4_TMRA4IE1_Msk         (0x400UL)                 /*!< TMRA4IE1 (Bitfield-Mask: 0x01)                        */
11556 #define CTIMER_CTRL4_TMRA4IE0_Pos         (9UL)                     /*!< TMRA4IE0 (Bit 9)                                      */
11557 #define CTIMER_CTRL4_TMRA4IE0_Msk         (0x200UL)                 /*!< TMRA4IE0 (Bitfield-Mask: 0x01)                        */
11558 #define CTIMER_CTRL4_TMRA4FN_Pos          (6UL)                     /*!< TMRA4FN (Bit 6)                                       */
11559 #define CTIMER_CTRL4_TMRA4FN_Msk          (0x1c0UL)                 /*!< TMRA4FN (Bitfield-Mask: 0x07)                         */
11560 #define CTIMER_CTRL4_TMRA4CLK_Pos         (1UL)                     /*!< TMRA4CLK (Bit 1)                                      */
11561 #define CTIMER_CTRL4_TMRA4CLK_Msk         (0x3eUL)                  /*!< TMRA4CLK (Bitfield-Mask: 0x1f)                        */
11562 #define CTIMER_CTRL4_TMRA4EN_Pos          (0UL)                     /*!< TMRA4EN (Bit 0)                                       */
11563 #define CTIMER_CTRL4_TMRA4EN_Msk          (0x1UL)                   /*!< TMRA4EN (Bitfield-Mask: 0x01)                         */
11564 /* =======================================================  CMPRAUXA4  ======================================================= */
11565 #define CTIMER_CMPRAUXA4_CMPR3A4_Pos      (16UL)                    /*!< CMPR3A4 (Bit 16)                                      */
11566 #define CTIMER_CMPRAUXA4_CMPR3A4_Msk      (0xffff0000UL)            /*!< CMPR3A4 (Bitfield-Mask: 0xffff)                       */
11567 #define CTIMER_CMPRAUXA4_CMPR2A4_Pos      (0UL)                     /*!< CMPR2A4 (Bit 0)                                       */
11568 #define CTIMER_CMPRAUXA4_CMPR2A4_Msk      (0xffffUL)                /*!< CMPR2A4 (Bitfield-Mask: 0xffff)                       */
11569 /* =======================================================  CMPRAUXB4  ======================================================= */
11570 #define CTIMER_CMPRAUXB4_CMPR3B4_Pos      (16UL)                    /*!< CMPR3B4 (Bit 16)                                      */
11571 #define CTIMER_CMPRAUXB4_CMPR3B4_Msk      (0xffff0000UL)            /*!< CMPR3B4 (Bitfield-Mask: 0xffff)                       */
11572 #define CTIMER_CMPRAUXB4_CMPR2B4_Pos      (0UL)                     /*!< CMPR2B4 (Bit 0)                                       */
11573 #define CTIMER_CMPRAUXB4_CMPR2B4_Msk      (0xffffUL)                /*!< CMPR2B4 (Bitfield-Mask: 0xffff)                       */
11574 /* =========================================================  AUX4  ========================================================== */
11575 #define CTIMER_AUX4_TMRB4EN23_Pos         (30UL)                    /*!< TMRB4EN23 (Bit 30)                                    */
11576 #define CTIMER_AUX4_TMRB4EN23_Msk         (0x40000000UL)            /*!< TMRB4EN23 (Bitfield-Mask: 0x01)                       */
11577 #define CTIMER_AUX4_TMRB4POL23_Pos        (29UL)                    /*!< TMRB4POL23 (Bit 29)                                   */
11578 #define CTIMER_AUX4_TMRB4POL23_Msk        (0x20000000UL)            /*!< TMRB4POL23 (Bitfield-Mask: 0x01)                      */
11579 #define CTIMER_AUX4_TMRB4TINV_Pos         (28UL)                    /*!< TMRB4TINV (Bit 28)                                    */
11580 #define CTIMER_AUX4_TMRB4TINV_Msk         (0x10000000UL)            /*!< TMRB4TINV (Bitfield-Mask: 0x01)                       */
11581 #define CTIMER_AUX4_TMRB4NOSYNC_Pos       (27UL)                    /*!< TMRB4NOSYNC (Bit 27)                                  */
11582 #define CTIMER_AUX4_TMRB4NOSYNC_Msk       (0x8000000UL)             /*!< TMRB4NOSYNC (Bitfield-Mask: 0x01)                     */
11583 #define CTIMER_AUX4_TMRB4TRIG_Pos         (23UL)                    /*!< TMRB4TRIG (Bit 23)                                    */
11584 #define CTIMER_AUX4_TMRB4TRIG_Msk         (0x7800000UL)             /*!< TMRB4TRIG (Bitfield-Mask: 0x0f)                       */
11585 #define CTIMER_AUX4_TMRB4LMT_Pos          (16UL)                    /*!< TMRB4LMT (Bit 16)                                     */
11586 #define CTIMER_AUX4_TMRB4LMT_Msk          (0x3f0000UL)              /*!< TMRB4LMT (Bitfield-Mask: 0x3f)                        */
11587 #define CTIMER_AUX4_TMRA4EN23_Pos         (14UL)                    /*!< TMRA4EN23 (Bit 14)                                    */
11588 #define CTIMER_AUX4_TMRA4EN23_Msk         (0x4000UL)                /*!< TMRA4EN23 (Bitfield-Mask: 0x01)                       */
11589 #define CTIMER_AUX4_TMRA4POL23_Pos        (13UL)                    /*!< TMRA4POL23 (Bit 13)                                   */
11590 #define CTIMER_AUX4_TMRA4POL23_Msk        (0x2000UL)                /*!< TMRA4POL23 (Bitfield-Mask: 0x01)                      */
11591 #define CTIMER_AUX4_TMRA4TINV_Pos         (12UL)                    /*!< TMRA4TINV (Bit 12)                                    */
11592 #define CTIMER_AUX4_TMRA4TINV_Msk         (0x1000UL)                /*!< TMRA4TINV (Bitfield-Mask: 0x01)                       */
11593 #define CTIMER_AUX4_TMRA4NOSYNC_Pos       (11UL)                    /*!< TMRA4NOSYNC (Bit 11)                                  */
11594 #define CTIMER_AUX4_TMRA4NOSYNC_Msk       (0x800UL)                 /*!< TMRA4NOSYNC (Bitfield-Mask: 0x01)                     */
11595 #define CTIMER_AUX4_TMRA4TRIG_Pos         (7UL)                     /*!< TMRA4TRIG (Bit 7)                                     */
11596 #define CTIMER_AUX4_TMRA4TRIG_Msk         (0x780UL)                 /*!< TMRA4TRIG (Bitfield-Mask: 0x0f)                       */
11597 #define CTIMER_AUX4_TMRA4LMT_Pos          (0UL)                     /*!< TMRA4LMT (Bit 0)                                      */
11598 #define CTIMER_AUX4_TMRA4LMT_Msk          (0x7fUL)                  /*!< TMRA4LMT (Bitfield-Mask: 0x7f)                        */
11599 /* =========================================================  TMR5  ========================================================== */
11600 #define CTIMER_TMR5_CTTMRB5_Pos           (16UL)                    /*!< CTTMRB5 (Bit 16)                                      */
11601 #define CTIMER_TMR5_CTTMRB5_Msk           (0xffff0000UL)            /*!< CTTMRB5 (Bitfield-Mask: 0xffff)                       */
11602 #define CTIMER_TMR5_CTTMRA5_Pos           (0UL)                     /*!< CTTMRA5 (Bit 0)                                       */
11603 #define CTIMER_TMR5_CTTMRA5_Msk           (0xffffUL)                /*!< CTTMRA5 (Bitfield-Mask: 0xffff)                       */
11604 /* ========================================================  CMPRA5  ========================================================= */
11605 #define CTIMER_CMPRA5_CMPR1A5_Pos         (16UL)                    /*!< CMPR1A5 (Bit 16)                                      */
11606 #define CTIMER_CMPRA5_CMPR1A5_Msk         (0xffff0000UL)            /*!< CMPR1A5 (Bitfield-Mask: 0xffff)                       */
11607 #define CTIMER_CMPRA5_CMPR0A5_Pos         (0UL)                     /*!< CMPR0A5 (Bit 0)                                       */
11608 #define CTIMER_CMPRA5_CMPR0A5_Msk         (0xffffUL)                /*!< CMPR0A5 (Bitfield-Mask: 0xffff)                       */
11609 /* ========================================================  CMPRB5  ========================================================= */
11610 #define CTIMER_CMPRB5_CMPR1B5_Pos         (16UL)                    /*!< CMPR1B5 (Bit 16)                                      */
11611 #define CTIMER_CMPRB5_CMPR1B5_Msk         (0xffff0000UL)            /*!< CMPR1B5 (Bitfield-Mask: 0xffff)                       */
11612 #define CTIMER_CMPRB5_CMPR0B5_Pos         (0UL)                     /*!< CMPR0B5 (Bit 0)                                       */
11613 #define CTIMER_CMPRB5_CMPR0B5_Msk         (0xffffUL)                /*!< CMPR0B5 (Bitfield-Mask: 0xffff)                       */
11614 /* =========================================================  CTRL5  ========================================================= */
11615 #define CTIMER_CTRL5_CTLINK5_Pos          (31UL)                    /*!< CTLINK5 (Bit 31)                                      */
11616 #define CTIMER_CTRL5_CTLINK5_Msk          (0x80000000UL)            /*!< CTLINK5 (Bitfield-Mask: 0x01)                         */
11617 #define CTIMER_CTRL5_TMRB5POL_Pos         (28UL)                    /*!< TMRB5POL (Bit 28)                                     */
11618 #define CTIMER_CTRL5_TMRB5POL_Msk         (0x10000000UL)            /*!< TMRB5POL (Bitfield-Mask: 0x01)                        */
11619 #define CTIMER_CTRL5_TMRB5CLR_Pos         (27UL)                    /*!< TMRB5CLR (Bit 27)                                     */
11620 #define CTIMER_CTRL5_TMRB5CLR_Msk         (0x8000000UL)             /*!< TMRB5CLR (Bitfield-Mask: 0x01)                        */
11621 #define CTIMER_CTRL5_TMRB5IE1_Pos         (26UL)                    /*!< TMRB5IE1 (Bit 26)                                     */
11622 #define CTIMER_CTRL5_TMRB5IE1_Msk         (0x4000000UL)             /*!< TMRB5IE1 (Bitfield-Mask: 0x01)                        */
11623 #define CTIMER_CTRL5_TMRB5IE0_Pos         (25UL)                    /*!< TMRB5IE0 (Bit 25)                                     */
11624 #define CTIMER_CTRL5_TMRB5IE0_Msk         (0x2000000UL)             /*!< TMRB5IE0 (Bitfield-Mask: 0x01)                        */
11625 #define CTIMER_CTRL5_TMRB5FN_Pos          (22UL)                    /*!< TMRB5FN (Bit 22)                                      */
11626 #define CTIMER_CTRL5_TMRB5FN_Msk          (0x1c00000UL)             /*!< TMRB5FN (Bitfield-Mask: 0x07)                         */
11627 #define CTIMER_CTRL5_TMRB5CLK_Pos         (17UL)                    /*!< TMRB5CLK (Bit 17)                                     */
11628 #define CTIMER_CTRL5_TMRB5CLK_Msk         (0x3e0000UL)              /*!< TMRB5CLK (Bitfield-Mask: 0x1f)                        */
11629 #define CTIMER_CTRL5_TMRB5EN_Pos          (16UL)                    /*!< TMRB5EN (Bit 16)                                      */
11630 #define CTIMER_CTRL5_TMRB5EN_Msk          (0x10000UL)               /*!< TMRB5EN (Bitfield-Mask: 0x01)                         */
11631 #define CTIMER_CTRL5_TMRA5POL_Pos         (12UL)                    /*!< TMRA5POL (Bit 12)                                     */
11632 #define CTIMER_CTRL5_TMRA5POL_Msk         (0x1000UL)                /*!< TMRA5POL (Bitfield-Mask: 0x01)                        */
11633 #define CTIMER_CTRL5_TMRA5CLR_Pos         (11UL)                    /*!< TMRA5CLR (Bit 11)                                     */
11634 #define CTIMER_CTRL5_TMRA5CLR_Msk         (0x800UL)                 /*!< TMRA5CLR (Bitfield-Mask: 0x01)                        */
11635 #define CTIMER_CTRL5_TMRA5IE1_Pos         (10UL)                    /*!< TMRA5IE1 (Bit 10)                                     */
11636 #define CTIMER_CTRL5_TMRA5IE1_Msk         (0x400UL)                 /*!< TMRA5IE1 (Bitfield-Mask: 0x01)                        */
11637 #define CTIMER_CTRL5_TMRA5IE0_Pos         (9UL)                     /*!< TMRA5IE0 (Bit 9)                                      */
11638 #define CTIMER_CTRL5_TMRA5IE0_Msk         (0x200UL)                 /*!< TMRA5IE0 (Bitfield-Mask: 0x01)                        */
11639 #define CTIMER_CTRL5_TMRA5FN_Pos          (6UL)                     /*!< TMRA5FN (Bit 6)                                       */
11640 #define CTIMER_CTRL5_TMRA5FN_Msk          (0x1c0UL)                 /*!< TMRA5FN (Bitfield-Mask: 0x07)                         */
11641 #define CTIMER_CTRL5_TMRA5CLK_Pos         (1UL)                     /*!< TMRA5CLK (Bit 1)                                      */
11642 #define CTIMER_CTRL5_TMRA5CLK_Msk         (0x3eUL)                  /*!< TMRA5CLK (Bitfield-Mask: 0x1f)                        */
11643 #define CTIMER_CTRL5_TMRA5EN_Pos          (0UL)                     /*!< TMRA5EN (Bit 0)                                       */
11644 #define CTIMER_CTRL5_TMRA5EN_Msk          (0x1UL)                   /*!< TMRA5EN (Bitfield-Mask: 0x01)                         */
11645 /* =======================================================  CMPRAUXA5  ======================================================= */
11646 #define CTIMER_CMPRAUXA5_CMPR3A5_Pos      (16UL)                    /*!< CMPR3A5 (Bit 16)                                      */
11647 #define CTIMER_CMPRAUXA5_CMPR3A5_Msk      (0xffff0000UL)            /*!< CMPR3A5 (Bitfield-Mask: 0xffff)                       */
11648 #define CTIMER_CMPRAUXA5_CMPR2A5_Pos      (0UL)                     /*!< CMPR2A5 (Bit 0)                                       */
11649 #define CTIMER_CMPRAUXA5_CMPR2A5_Msk      (0xffffUL)                /*!< CMPR2A5 (Bitfield-Mask: 0xffff)                       */
11650 /* =======================================================  CMPRAUXB5  ======================================================= */
11651 #define CTIMER_CMPRAUXB5_CMPR3B5_Pos      (16UL)                    /*!< CMPR3B5 (Bit 16)                                      */
11652 #define CTIMER_CMPRAUXB5_CMPR3B5_Msk      (0xffff0000UL)            /*!< CMPR3B5 (Bitfield-Mask: 0xffff)                       */
11653 #define CTIMER_CMPRAUXB5_CMPR2B5_Pos      (0UL)                     /*!< CMPR2B5 (Bit 0)                                       */
11654 #define CTIMER_CMPRAUXB5_CMPR2B5_Msk      (0xffffUL)                /*!< CMPR2B5 (Bitfield-Mask: 0xffff)                       */
11655 /* =========================================================  AUX5  ========================================================== */
11656 #define CTIMER_AUX5_TMRB5EN23_Pos         (30UL)                    /*!< TMRB5EN23 (Bit 30)                                    */
11657 #define CTIMER_AUX5_TMRB5EN23_Msk         (0x40000000UL)            /*!< TMRB5EN23 (Bitfield-Mask: 0x01)                       */
11658 #define CTIMER_AUX5_TMRB5POL23_Pos        (29UL)                    /*!< TMRB5POL23 (Bit 29)                                   */
11659 #define CTIMER_AUX5_TMRB5POL23_Msk        (0x20000000UL)            /*!< TMRB5POL23 (Bitfield-Mask: 0x01)                      */
11660 #define CTIMER_AUX5_TMRB5TINV_Pos         (28UL)                    /*!< TMRB5TINV (Bit 28)                                    */
11661 #define CTIMER_AUX5_TMRB5TINV_Msk         (0x10000000UL)            /*!< TMRB5TINV (Bitfield-Mask: 0x01)                       */
11662 #define CTIMER_AUX5_TMRB5NOSYNC_Pos       (27UL)                    /*!< TMRB5NOSYNC (Bit 27)                                  */
11663 #define CTIMER_AUX5_TMRB5NOSYNC_Msk       (0x8000000UL)             /*!< TMRB5NOSYNC (Bitfield-Mask: 0x01)                     */
11664 #define CTIMER_AUX5_TMRB5TRIG_Pos         (23UL)                    /*!< TMRB5TRIG (Bit 23)                                    */
11665 #define CTIMER_AUX5_TMRB5TRIG_Msk         (0x7800000UL)             /*!< TMRB5TRIG (Bitfield-Mask: 0x0f)                       */
11666 #define CTIMER_AUX5_TMRB5LMT_Pos          (16UL)                    /*!< TMRB5LMT (Bit 16)                                     */
11667 #define CTIMER_AUX5_TMRB5LMT_Msk          (0x3f0000UL)              /*!< TMRB5LMT (Bitfield-Mask: 0x3f)                        */
11668 #define CTIMER_AUX5_TMRA5EN23_Pos         (14UL)                    /*!< TMRA5EN23 (Bit 14)                                    */
11669 #define CTIMER_AUX5_TMRA5EN23_Msk         (0x4000UL)                /*!< TMRA5EN23 (Bitfield-Mask: 0x01)                       */
11670 #define CTIMER_AUX5_TMRA5POL23_Pos        (13UL)                    /*!< TMRA5POL23 (Bit 13)                                   */
11671 #define CTIMER_AUX5_TMRA5POL23_Msk        (0x2000UL)                /*!< TMRA5POL23 (Bitfield-Mask: 0x01)                      */
11672 #define CTIMER_AUX5_TMRA5TINV_Pos         (12UL)                    /*!< TMRA5TINV (Bit 12)                                    */
11673 #define CTIMER_AUX5_TMRA5TINV_Msk         (0x1000UL)                /*!< TMRA5TINV (Bitfield-Mask: 0x01)                       */
11674 #define CTIMER_AUX5_TMRA5NOSYNC_Pos       (11UL)                    /*!< TMRA5NOSYNC (Bit 11)                                  */
11675 #define CTIMER_AUX5_TMRA5NOSYNC_Msk       (0x800UL)                 /*!< TMRA5NOSYNC (Bitfield-Mask: 0x01)                     */
11676 #define CTIMER_AUX5_TMRA5TRIG_Pos         (7UL)                     /*!< TMRA5TRIG (Bit 7)                                     */
11677 #define CTIMER_AUX5_TMRA5TRIG_Msk         (0x780UL)                 /*!< TMRA5TRIG (Bitfield-Mask: 0x0f)                       */
11678 #define CTIMER_AUX5_TMRA5LMT_Pos          (0UL)                     /*!< TMRA5LMT (Bit 0)                                      */
11679 #define CTIMER_AUX5_TMRA5LMT_Msk          (0x7fUL)                  /*!< TMRA5LMT (Bitfield-Mask: 0x7f)                        */
11680 /* =========================================================  TMR6  ========================================================== */
11681 #define CTIMER_TMR6_CTTMRB6_Pos           (16UL)                    /*!< CTTMRB6 (Bit 16)                                      */
11682 #define CTIMER_TMR6_CTTMRB6_Msk           (0xffff0000UL)            /*!< CTTMRB6 (Bitfield-Mask: 0xffff)                       */
11683 #define CTIMER_TMR6_CTTMRA6_Pos           (0UL)                     /*!< CTTMRA6 (Bit 0)                                       */
11684 #define CTIMER_TMR6_CTTMRA6_Msk           (0xffffUL)                /*!< CTTMRA6 (Bitfield-Mask: 0xffff)                       */
11685 /* ========================================================  CMPRA6  ========================================================= */
11686 #define CTIMER_CMPRA6_CMPR1A6_Pos         (16UL)                    /*!< CMPR1A6 (Bit 16)                                      */
11687 #define CTIMER_CMPRA6_CMPR1A6_Msk         (0xffff0000UL)            /*!< CMPR1A6 (Bitfield-Mask: 0xffff)                       */
11688 #define CTIMER_CMPRA6_CMPR0A6_Pos         (0UL)                     /*!< CMPR0A6 (Bit 0)                                       */
11689 #define CTIMER_CMPRA6_CMPR0A6_Msk         (0xffffUL)                /*!< CMPR0A6 (Bitfield-Mask: 0xffff)                       */
11690 /* ========================================================  CMPRB6  ========================================================= */
11691 #define CTIMER_CMPRB6_CMPR1B6_Pos         (16UL)                    /*!< CMPR1B6 (Bit 16)                                      */
11692 #define CTIMER_CMPRB6_CMPR1B6_Msk         (0xffff0000UL)            /*!< CMPR1B6 (Bitfield-Mask: 0xffff)                       */
11693 #define CTIMER_CMPRB6_CMPR0B6_Pos         (0UL)                     /*!< CMPR0B6 (Bit 0)                                       */
11694 #define CTIMER_CMPRB6_CMPR0B6_Msk         (0xffffUL)                /*!< CMPR0B6 (Bitfield-Mask: 0xffff)                       */
11695 /* =========================================================  CTRL6  ========================================================= */
11696 #define CTIMER_CTRL6_CTLINK6_Pos          (31UL)                    /*!< CTLINK6 (Bit 31)                                      */
11697 #define CTIMER_CTRL6_CTLINK6_Msk          (0x80000000UL)            /*!< CTLINK6 (Bitfield-Mask: 0x01)                         */
11698 #define CTIMER_CTRL6_TMRB6POL_Pos         (28UL)                    /*!< TMRB6POL (Bit 28)                                     */
11699 #define CTIMER_CTRL6_TMRB6POL_Msk         (0x10000000UL)            /*!< TMRB6POL (Bitfield-Mask: 0x01)                        */
11700 #define CTIMER_CTRL6_TMRB6CLR_Pos         (27UL)                    /*!< TMRB6CLR (Bit 27)                                     */
11701 #define CTIMER_CTRL6_TMRB6CLR_Msk         (0x8000000UL)             /*!< TMRB6CLR (Bitfield-Mask: 0x01)                        */
11702 #define CTIMER_CTRL6_TMRB6IE1_Pos         (26UL)                    /*!< TMRB6IE1 (Bit 26)                                     */
11703 #define CTIMER_CTRL6_TMRB6IE1_Msk         (0x4000000UL)             /*!< TMRB6IE1 (Bitfield-Mask: 0x01)                        */
11704 #define CTIMER_CTRL6_TMRB6IE0_Pos         (25UL)                    /*!< TMRB6IE0 (Bit 25)                                     */
11705 #define CTIMER_CTRL6_TMRB6IE0_Msk         (0x2000000UL)             /*!< TMRB6IE0 (Bitfield-Mask: 0x01)                        */
11706 #define CTIMER_CTRL6_TMRB6FN_Pos          (22UL)                    /*!< TMRB6FN (Bit 22)                                      */
11707 #define CTIMER_CTRL6_TMRB6FN_Msk          (0x1c00000UL)             /*!< TMRB6FN (Bitfield-Mask: 0x07)                         */
11708 #define CTIMER_CTRL6_TMRB6CLK_Pos         (17UL)                    /*!< TMRB6CLK (Bit 17)                                     */
11709 #define CTIMER_CTRL6_TMRB6CLK_Msk         (0x3e0000UL)              /*!< TMRB6CLK (Bitfield-Mask: 0x1f)                        */
11710 #define CTIMER_CTRL6_TMRB6EN_Pos          (16UL)                    /*!< TMRB6EN (Bit 16)                                      */
11711 #define CTIMER_CTRL6_TMRB6EN_Msk          (0x10000UL)               /*!< TMRB6EN (Bitfield-Mask: 0x01)                         */
11712 #define CTIMER_CTRL6_TMRA6POL_Pos         (12UL)                    /*!< TMRA6POL (Bit 12)                                     */
11713 #define CTIMER_CTRL6_TMRA6POL_Msk         (0x1000UL)                /*!< TMRA6POL (Bitfield-Mask: 0x01)                        */
11714 #define CTIMER_CTRL6_TMRA6CLR_Pos         (11UL)                    /*!< TMRA6CLR (Bit 11)                                     */
11715 #define CTIMER_CTRL6_TMRA6CLR_Msk         (0x800UL)                 /*!< TMRA6CLR (Bitfield-Mask: 0x01)                        */
11716 #define CTIMER_CTRL6_TMRA6IE1_Pos         (10UL)                    /*!< TMRA6IE1 (Bit 10)                                     */
11717 #define CTIMER_CTRL6_TMRA6IE1_Msk         (0x400UL)                 /*!< TMRA6IE1 (Bitfield-Mask: 0x01)                        */
11718 #define CTIMER_CTRL6_TMRA6IE0_Pos         (9UL)                     /*!< TMRA6IE0 (Bit 9)                                      */
11719 #define CTIMER_CTRL6_TMRA6IE0_Msk         (0x200UL)                 /*!< TMRA6IE0 (Bitfield-Mask: 0x01)                        */
11720 #define CTIMER_CTRL6_TMRA6FN_Pos          (6UL)                     /*!< TMRA6FN (Bit 6)                                       */
11721 #define CTIMER_CTRL6_TMRA6FN_Msk          (0x1c0UL)                 /*!< TMRA6FN (Bitfield-Mask: 0x07)                         */
11722 #define CTIMER_CTRL6_TMRA6CLK_Pos         (1UL)                     /*!< TMRA6CLK (Bit 1)                                      */
11723 #define CTIMER_CTRL6_TMRA6CLK_Msk         (0x3eUL)                  /*!< TMRA6CLK (Bitfield-Mask: 0x1f)                        */
11724 #define CTIMER_CTRL6_TMRA6EN_Pos          (0UL)                     /*!< TMRA6EN (Bit 0)                                       */
11725 #define CTIMER_CTRL6_TMRA6EN_Msk          (0x1UL)                   /*!< TMRA6EN (Bitfield-Mask: 0x01)                         */
11726 /* =======================================================  CMPRAUXA6  ======================================================= */
11727 #define CTIMER_CMPRAUXA6_CMPR3A6_Pos      (16UL)                    /*!< CMPR3A6 (Bit 16)                                      */
11728 #define CTIMER_CMPRAUXA6_CMPR3A6_Msk      (0xffff0000UL)            /*!< CMPR3A6 (Bitfield-Mask: 0xffff)                       */
11729 #define CTIMER_CMPRAUXA6_CMPR2A6_Pos      (0UL)                     /*!< CMPR2A6 (Bit 0)                                       */
11730 #define CTIMER_CMPRAUXA6_CMPR2A6_Msk      (0xffffUL)                /*!< CMPR2A6 (Bitfield-Mask: 0xffff)                       */
11731 /* =======================================================  CMPRAUXB6  ======================================================= */
11732 #define CTIMER_CMPRAUXB6_CMPR3B6_Pos      (16UL)                    /*!< CMPR3B6 (Bit 16)                                      */
11733 #define CTIMER_CMPRAUXB6_CMPR3B6_Msk      (0xffff0000UL)            /*!< CMPR3B6 (Bitfield-Mask: 0xffff)                       */
11734 #define CTIMER_CMPRAUXB6_CMPR2B6_Pos      (0UL)                     /*!< CMPR2B6 (Bit 0)                                       */
11735 #define CTIMER_CMPRAUXB6_CMPR2B6_Msk      (0xffffUL)                /*!< CMPR2B6 (Bitfield-Mask: 0xffff)                       */
11736 /* =========================================================  AUX6  ========================================================== */
11737 #define CTIMER_AUX6_TMRB6EN23_Pos         (30UL)                    /*!< TMRB6EN23 (Bit 30)                                    */
11738 #define CTIMER_AUX6_TMRB6EN23_Msk         (0x40000000UL)            /*!< TMRB6EN23 (Bitfield-Mask: 0x01)                       */
11739 #define CTIMER_AUX6_TMRB6POL23_Pos        (29UL)                    /*!< TMRB6POL23 (Bit 29)                                   */
11740 #define CTIMER_AUX6_TMRB6POL23_Msk        (0x20000000UL)            /*!< TMRB6POL23 (Bitfield-Mask: 0x01)                      */
11741 #define CTIMER_AUX6_TMRB6TINV_Pos         (28UL)                    /*!< TMRB6TINV (Bit 28)                                    */
11742 #define CTIMER_AUX6_TMRB6TINV_Msk         (0x10000000UL)            /*!< TMRB6TINV (Bitfield-Mask: 0x01)                       */
11743 #define CTIMER_AUX6_TMRB6NOSYNC_Pos       (27UL)                    /*!< TMRB6NOSYNC (Bit 27)                                  */
11744 #define CTIMER_AUX6_TMRB6NOSYNC_Msk       (0x8000000UL)             /*!< TMRB6NOSYNC (Bitfield-Mask: 0x01)                     */
11745 #define CTIMER_AUX6_TMRB6TRIG_Pos         (23UL)                    /*!< TMRB6TRIG (Bit 23)                                    */
11746 #define CTIMER_AUX6_TMRB6TRIG_Msk         (0x7800000UL)             /*!< TMRB6TRIG (Bitfield-Mask: 0x0f)                       */
11747 #define CTIMER_AUX6_TMRB6LMT_Pos          (16UL)                    /*!< TMRB6LMT (Bit 16)                                     */
11748 #define CTIMER_AUX6_TMRB6LMT_Msk          (0x3f0000UL)              /*!< TMRB6LMT (Bitfield-Mask: 0x3f)                        */
11749 #define CTIMER_AUX6_TMRA6EN23_Pos         (14UL)                    /*!< TMRA6EN23 (Bit 14)                                    */
11750 #define CTIMER_AUX6_TMRA6EN23_Msk         (0x4000UL)                /*!< TMRA6EN23 (Bitfield-Mask: 0x01)                       */
11751 #define CTIMER_AUX6_TMRA6POL23_Pos        (13UL)                    /*!< TMRA6POL23 (Bit 13)                                   */
11752 #define CTIMER_AUX6_TMRA6POL23_Msk        (0x2000UL)                /*!< TMRA6POL23 (Bitfield-Mask: 0x01)                      */
11753 #define CTIMER_AUX6_TMRA6TINV_Pos         (12UL)                    /*!< TMRA6TINV (Bit 12)                                    */
11754 #define CTIMER_AUX6_TMRA6TINV_Msk         (0x1000UL)                /*!< TMRA6TINV (Bitfield-Mask: 0x01)                       */
11755 #define CTIMER_AUX6_TMRA6NOSYNC_Pos       (11UL)                    /*!< TMRA6NOSYNC (Bit 11)                                  */
11756 #define CTIMER_AUX6_TMRA6NOSYNC_Msk       (0x800UL)                 /*!< TMRA6NOSYNC (Bitfield-Mask: 0x01)                     */
11757 #define CTIMER_AUX6_TMRA6TRIG_Pos         (7UL)                     /*!< TMRA6TRIG (Bit 7)                                     */
11758 #define CTIMER_AUX6_TMRA6TRIG_Msk         (0x780UL)                 /*!< TMRA6TRIG (Bitfield-Mask: 0x0f)                       */
11759 #define CTIMER_AUX6_TMRA6LMT_Pos          (0UL)                     /*!< TMRA6LMT (Bit 0)                                      */
11760 #define CTIMER_AUX6_TMRA6LMT_Msk          (0x7fUL)                  /*!< TMRA6LMT (Bitfield-Mask: 0x7f)                        */
11761 /* =========================================================  TMR7  ========================================================== */
11762 #define CTIMER_TMR7_CTTMRB7_Pos           (16UL)                    /*!< CTTMRB7 (Bit 16)                                      */
11763 #define CTIMER_TMR7_CTTMRB7_Msk           (0xffff0000UL)            /*!< CTTMRB7 (Bitfield-Mask: 0xffff)                       */
11764 #define CTIMER_TMR7_CTTMRA7_Pos           (0UL)                     /*!< CTTMRA7 (Bit 0)                                       */
11765 #define CTIMER_TMR7_CTTMRA7_Msk           (0xffffUL)                /*!< CTTMRA7 (Bitfield-Mask: 0xffff)                       */
11766 /* ========================================================  CMPRA7  ========================================================= */
11767 #define CTIMER_CMPRA7_CMPR1A7_Pos         (16UL)                    /*!< CMPR1A7 (Bit 16)                                      */
11768 #define CTIMER_CMPRA7_CMPR1A7_Msk         (0xffff0000UL)            /*!< CMPR1A7 (Bitfield-Mask: 0xffff)                       */
11769 #define CTIMER_CMPRA7_CMPR0A7_Pos         (0UL)                     /*!< CMPR0A7 (Bit 0)                                       */
11770 #define CTIMER_CMPRA7_CMPR0A7_Msk         (0xffffUL)                /*!< CMPR0A7 (Bitfield-Mask: 0xffff)                       */
11771 /* ========================================================  CMPRB7  ========================================================= */
11772 #define CTIMER_CMPRB7_CMPR1B7_Pos         (16UL)                    /*!< CMPR1B7 (Bit 16)                                      */
11773 #define CTIMER_CMPRB7_CMPR1B7_Msk         (0xffff0000UL)            /*!< CMPR1B7 (Bitfield-Mask: 0xffff)                       */
11774 #define CTIMER_CMPRB7_CMPR0B7_Pos         (0UL)                     /*!< CMPR0B7 (Bit 0)                                       */
11775 #define CTIMER_CMPRB7_CMPR0B7_Msk         (0xffffUL)                /*!< CMPR0B7 (Bitfield-Mask: 0xffff)                       */
11776 /* =========================================================  CTRL7  ========================================================= */
11777 #define CTIMER_CTRL7_CTLINK7_Pos          (31UL)                    /*!< CTLINK7 (Bit 31)                                      */
11778 #define CTIMER_CTRL7_CTLINK7_Msk          (0x80000000UL)            /*!< CTLINK7 (Bitfield-Mask: 0x01)                         */
11779 #define CTIMER_CTRL7_TMRB7POL_Pos         (28UL)                    /*!< TMRB7POL (Bit 28)                                     */
11780 #define CTIMER_CTRL7_TMRB7POL_Msk         (0x10000000UL)            /*!< TMRB7POL (Bitfield-Mask: 0x01)                        */
11781 #define CTIMER_CTRL7_TMRB7CLR_Pos         (27UL)                    /*!< TMRB7CLR (Bit 27)                                     */
11782 #define CTIMER_CTRL7_TMRB7CLR_Msk         (0x8000000UL)             /*!< TMRB7CLR (Bitfield-Mask: 0x01)                        */
11783 #define CTIMER_CTRL7_TMRB7IE1_Pos         (26UL)                    /*!< TMRB7IE1 (Bit 26)                                     */
11784 #define CTIMER_CTRL7_TMRB7IE1_Msk         (0x4000000UL)             /*!< TMRB7IE1 (Bitfield-Mask: 0x01)                        */
11785 #define CTIMER_CTRL7_TMRB7IE0_Pos         (25UL)                    /*!< TMRB7IE0 (Bit 25)                                     */
11786 #define CTIMER_CTRL7_TMRB7IE0_Msk         (0x2000000UL)             /*!< TMRB7IE0 (Bitfield-Mask: 0x01)                        */
11787 #define CTIMER_CTRL7_TMRB7FN_Pos          (22UL)                    /*!< TMRB7FN (Bit 22)                                      */
11788 #define CTIMER_CTRL7_TMRB7FN_Msk          (0x1c00000UL)             /*!< TMRB7FN (Bitfield-Mask: 0x07)                         */
11789 #define CTIMER_CTRL7_TMRB7CLK_Pos         (17UL)                    /*!< TMRB7CLK (Bit 17)                                     */
11790 #define CTIMER_CTRL7_TMRB7CLK_Msk         (0x3e0000UL)              /*!< TMRB7CLK (Bitfield-Mask: 0x1f)                        */
11791 #define CTIMER_CTRL7_TMRB7EN_Pos          (16UL)                    /*!< TMRB7EN (Bit 16)                                      */
11792 #define CTIMER_CTRL7_TMRB7EN_Msk          (0x10000UL)               /*!< TMRB7EN (Bitfield-Mask: 0x01)                         */
11793 #define CTIMER_CTRL7_TMRA7POL_Pos         (12UL)                    /*!< TMRA7POL (Bit 12)                                     */
11794 #define CTIMER_CTRL7_TMRA7POL_Msk         (0x1000UL)                /*!< TMRA7POL (Bitfield-Mask: 0x01)                        */
11795 #define CTIMER_CTRL7_TMRA7CLR_Pos         (11UL)                    /*!< TMRA7CLR (Bit 11)                                     */
11796 #define CTIMER_CTRL7_TMRA7CLR_Msk         (0x800UL)                 /*!< TMRA7CLR (Bitfield-Mask: 0x01)                        */
11797 #define CTIMER_CTRL7_TMRA7IE1_Pos         (10UL)                    /*!< TMRA7IE1 (Bit 10)                                     */
11798 #define CTIMER_CTRL7_TMRA7IE1_Msk         (0x400UL)                 /*!< TMRA7IE1 (Bitfield-Mask: 0x01)                        */
11799 #define CTIMER_CTRL7_TMRA7IE0_Pos         (9UL)                     /*!< TMRA7IE0 (Bit 9)                                      */
11800 #define CTIMER_CTRL7_TMRA7IE0_Msk         (0x200UL)                 /*!< TMRA7IE0 (Bitfield-Mask: 0x01)                        */
11801 #define CTIMER_CTRL7_TMRA7FN_Pos          (6UL)                     /*!< TMRA7FN (Bit 6)                                       */
11802 #define CTIMER_CTRL7_TMRA7FN_Msk          (0x1c0UL)                 /*!< TMRA7FN (Bitfield-Mask: 0x07)                         */
11803 #define CTIMER_CTRL7_TMRA7CLK_Pos         (1UL)                     /*!< TMRA7CLK (Bit 1)                                      */
11804 #define CTIMER_CTRL7_TMRA7CLK_Msk         (0x3eUL)                  /*!< TMRA7CLK (Bitfield-Mask: 0x1f)                        */
11805 #define CTIMER_CTRL7_TMRA7EN_Pos          (0UL)                     /*!< TMRA7EN (Bit 0)                                       */
11806 #define CTIMER_CTRL7_TMRA7EN_Msk          (0x1UL)                   /*!< TMRA7EN (Bitfield-Mask: 0x01)                         */
11807 /* =======================================================  CMPRAUXA7  ======================================================= */
11808 #define CTIMER_CMPRAUXA7_CMPR3A7_Pos      (16UL)                    /*!< CMPR3A7 (Bit 16)                                      */
11809 #define CTIMER_CMPRAUXA7_CMPR3A7_Msk      (0xffff0000UL)            /*!< CMPR3A7 (Bitfield-Mask: 0xffff)                       */
11810 #define CTIMER_CMPRAUXA7_CMPR2A7_Pos      (0UL)                     /*!< CMPR2A7 (Bit 0)                                       */
11811 #define CTIMER_CMPRAUXA7_CMPR2A7_Msk      (0xffffUL)                /*!< CMPR2A7 (Bitfield-Mask: 0xffff)                       */
11812 /* =======================================================  CMPRAUXB7  ======================================================= */
11813 #define CTIMER_CMPRAUXB7_CMPR3B7_Pos      (16UL)                    /*!< CMPR3B7 (Bit 16)                                      */
11814 #define CTIMER_CMPRAUXB7_CMPR3B7_Msk      (0xffff0000UL)            /*!< CMPR3B7 (Bitfield-Mask: 0xffff)                       */
11815 #define CTIMER_CMPRAUXB7_CMPR2B7_Pos      (0UL)                     /*!< CMPR2B7 (Bit 0)                                       */
11816 #define CTIMER_CMPRAUXB7_CMPR2B7_Msk      (0xffffUL)                /*!< CMPR2B7 (Bitfield-Mask: 0xffff)                       */
11817 /* =========================================================  AUX7  ========================================================== */
11818 #define CTIMER_AUX7_TMRB7EN23_Pos         (30UL)                    /*!< TMRB7EN23 (Bit 30)                                    */
11819 #define CTIMER_AUX7_TMRB7EN23_Msk         (0x40000000UL)            /*!< TMRB7EN23 (Bitfield-Mask: 0x01)                       */
11820 #define CTIMER_AUX7_TMRB7POL23_Pos        (29UL)                    /*!< TMRB7POL23 (Bit 29)                                   */
11821 #define CTIMER_AUX7_TMRB7POL23_Msk        (0x20000000UL)            /*!< TMRB7POL23 (Bitfield-Mask: 0x01)                      */
11822 #define CTIMER_AUX7_TMRB7TINV_Pos         (28UL)                    /*!< TMRB7TINV (Bit 28)                                    */
11823 #define CTIMER_AUX7_TMRB7TINV_Msk         (0x10000000UL)            /*!< TMRB7TINV (Bitfield-Mask: 0x01)                       */
11824 #define CTIMER_AUX7_TMRB7NOSYNC_Pos       (27UL)                    /*!< TMRB7NOSYNC (Bit 27)                                  */
11825 #define CTIMER_AUX7_TMRB7NOSYNC_Msk       (0x8000000UL)             /*!< TMRB7NOSYNC (Bitfield-Mask: 0x01)                     */
11826 #define CTIMER_AUX7_TMRB7TRIG_Pos         (23UL)                    /*!< TMRB7TRIG (Bit 23)                                    */
11827 #define CTIMER_AUX7_TMRB7TRIG_Msk         (0x7800000UL)             /*!< TMRB7TRIG (Bitfield-Mask: 0x0f)                       */
11828 #define CTIMER_AUX7_TMRB7LMT_Pos          (16UL)                    /*!< TMRB7LMT (Bit 16)                                     */
11829 #define CTIMER_AUX7_TMRB7LMT_Msk          (0x3f0000UL)              /*!< TMRB7LMT (Bitfield-Mask: 0x3f)                        */
11830 #define CTIMER_AUX7_TMRA7EN23_Pos         (14UL)                    /*!< TMRA7EN23 (Bit 14)                                    */
11831 #define CTIMER_AUX7_TMRA7EN23_Msk         (0x4000UL)                /*!< TMRA7EN23 (Bitfield-Mask: 0x01)                       */
11832 #define CTIMER_AUX7_TMRA7POL23_Pos        (13UL)                    /*!< TMRA7POL23 (Bit 13)                                   */
11833 #define CTIMER_AUX7_TMRA7POL23_Msk        (0x2000UL)                /*!< TMRA7POL23 (Bitfield-Mask: 0x01)                      */
11834 #define CTIMER_AUX7_TMRA7TINV_Pos         (12UL)                    /*!< TMRA7TINV (Bit 12)                                    */
11835 #define CTIMER_AUX7_TMRA7TINV_Msk         (0x1000UL)                /*!< TMRA7TINV (Bitfield-Mask: 0x01)                       */
11836 #define CTIMER_AUX7_TMRA7NOSYNC_Pos       (11UL)                    /*!< TMRA7NOSYNC (Bit 11)                                  */
11837 #define CTIMER_AUX7_TMRA7NOSYNC_Msk       (0x800UL)                 /*!< TMRA7NOSYNC (Bitfield-Mask: 0x01)                     */
11838 #define CTIMER_AUX7_TMRA7TRIG_Pos         (7UL)                     /*!< TMRA7TRIG (Bit 7)                                     */
11839 #define CTIMER_AUX7_TMRA7TRIG_Msk         (0x780UL)                 /*!< TMRA7TRIG (Bitfield-Mask: 0x0f)                       */
11840 #define CTIMER_AUX7_TMRA7LMT_Pos          (0UL)                     /*!< TMRA7LMT (Bit 0)                                      */
11841 #define CTIMER_AUX7_TMRA7LMT_Msk          (0x7fUL)                  /*!< TMRA7LMT (Bitfield-Mask: 0x7f)                        */
11842 /* ========================================================  GLOBEN  ========================================================= */
11843 #define CTIMER_GLOBEN_ENB7_Pos            (15UL)                    /*!< ENB7 (Bit 15)                                         */
11844 #define CTIMER_GLOBEN_ENB7_Msk            (0x8000UL)                /*!< ENB7 (Bitfield-Mask: 0x01)                            */
11845 #define CTIMER_GLOBEN_ENA7_Pos            (14UL)                    /*!< ENA7 (Bit 14)                                         */
11846 #define CTIMER_GLOBEN_ENA7_Msk            (0x4000UL)                /*!< ENA7 (Bitfield-Mask: 0x01)                            */
11847 #define CTIMER_GLOBEN_ENB6_Pos            (13UL)                    /*!< ENB6 (Bit 13)                                         */
11848 #define CTIMER_GLOBEN_ENB6_Msk            (0x2000UL)                /*!< ENB6 (Bitfield-Mask: 0x01)                            */
11849 #define CTIMER_GLOBEN_ENA6_Pos            (12UL)                    /*!< ENA6 (Bit 12)                                         */
11850 #define CTIMER_GLOBEN_ENA6_Msk            (0x1000UL)                /*!< ENA6 (Bitfield-Mask: 0x01)                            */
11851 #define CTIMER_GLOBEN_ENB5_Pos            (11UL)                    /*!< ENB5 (Bit 11)                                         */
11852 #define CTIMER_GLOBEN_ENB5_Msk            (0x800UL)                 /*!< ENB5 (Bitfield-Mask: 0x01)                            */
11853 #define CTIMER_GLOBEN_ENA5_Pos            (10UL)                    /*!< ENA5 (Bit 10)                                         */
11854 #define CTIMER_GLOBEN_ENA5_Msk            (0x400UL)                 /*!< ENA5 (Bitfield-Mask: 0x01)                            */
11855 #define CTIMER_GLOBEN_ENB4_Pos            (9UL)                     /*!< ENB4 (Bit 9)                                          */
11856 #define CTIMER_GLOBEN_ENB4_Msk            (0x200UL)                 /*!< ENB4 (Bitfield-Mask: 0x01)                            */
11857 #define CTIMER_GLOBEN_ENA4_Pos            (8UL)                     /*!< ENA4 (Bit 8)                                          */
11858 #define CTIMER_GLOBEN_ENA4_Msk            (0x100UL)                 /*!< ENA4 (Bitfield-Mask: 0x01)                            */
11859 #define CTIMER_GLOBEN_ENB3_Pos            (7UL)                     /*!< ENB3 (Bit 7)                                          */
11860 #define CTIMER_GLOBEN_ENB3_Msk            (0x80UL)                  /*!< ENB3 (Bitfield-Mask: 0x01)                            */
11861 #define CTIMER_GLOBEN_ENA3_Pos            (6UL)                     /*!< ENA3 (Bit 6)                                          */
11862 #define CTIMER_GLOBEN_ENA3_Msk            (0x40UL)                  /*!< ENA3 (Bitfield-Mask: 0x01)                            */
11863 #define CTIMER_GLOBEN_ENB2_Pos            (5UL)                     /*!< ENB2 (Bit 5)                                          */
11864 #define CTIMER_GLOBEN_ENB2_Msk            (0x20UL)                  /*!< ENB2 (Bitfield-Mask: 0x01)                            */
11865 #define CTIMER_GLOBEN_ENA2_Pos            (4UL)                     /*!< ENA2 (Bit 4)                                          */
11866 #define CTIMER_GLOBEN_ENA2_Msk            (0x10UL)                  /*!< ENA2 (Bitfield-Mask: 0x01)                            */
11867 #define CTIMER_GLOBEN_ENB1_Pos            (3UL)                     /*!< ENB1 (Bit 3)                                          */
11868 #define CTIMER_GLOBEN_ENB1_Msk            (0x8UL)                   /*!< ENB1 (Bitfield-Mask: 0x01)                            */
11869 #define CTIMER_GLOBEN_ENA1_Pos            (2UL)                     /*!< ENA1 (Bit 2)                                          */
11870 #define CTIMER_GLOBEN_ENA1_Msk            (0x4UL)                   /*!< ENA1 (Bitfield-Mask: 0x01)                            */
11871 #define CTIMER_GLOBEN_ENB0_Pos            (1UL)                     /*!< ENB0 (Bit 1)                                          */
11872 #define CTIMER_GLOBEN_ENB0_Msk            (0x2UL)                   /*!< ENB0 (Bitfield-Mask: 0x01)                            */
11873 #define CTIMER_GLOBEN_ENA0_Pos            (0UL)                     /*!< ENA0 (Bit 0)                                          */
11874 #define CTIMER_GLOBEN_ENA0_Msk            (0x1UL)                   /*!< ENA0 (Bitfield-Mask: 0x01)                            */
11875 /* ========================================================  OUTCFG0  ======================================================== */
11876 #define CTIMER_OUTCFG0_CFG9_Pos           (28UL)                    /*!< CFG9 (Bit 28)                                         */
11877 #define CTIMER_OUTCFG0_CFG9_Msk           (0x70000000UL)            /*!< CFG9 (Bitfield-Mask: 0x07)                            */
11878 #define CTIMER_OUTCFG0_CFG8_Pos           (25UL)                    /*!< CFG8 (Bit 25)                                         */
11879 #define CTIMER_OUTCFG0_CFG8_Msk           (0xe000000UL)             /*!< CFG8 (Bitfield-Mask: 0x07)                            */
11880 #define CTIMER_OUTCFG0_CFG7_Pos           (22UL)                    /*!< CFG7 (Bit 22)                                         */
11881 #define CTIMER_OUTCFG0_CFG7_Msk           (0x1c00000UL)             /*!< CFG7 (Bitfield-Mask: 0x07)                            */
11882 #define CTIMER_OUTCFG0_CFG6_Pos           (19UL)                    /*!< CFG6 (Bit 19)                                         */
11883 #define CTIMER_OUTCFG0_CFG6_Msk           (0x380000UL)              /*!< CFG6 (Bitfield-Mask: 0x07)                            */
11884 #define CTIMER_OUTCFG0_CFG5_Pos           (16UL)                    /*!< CFG5 (Bit 16)                                         */
11885 #define CTIMER_OUTCFG0_CFG5_Msk           (0x70000UL)               /*!< CFG5 (Bitfield-Mask: 0x07)                            */
11886 #define CTIMER_OUTCFG0_CFG4_Pos           (12UL)                    /*!< CFG4 (Bit 12)                                         */
11887 #define CTIMER_OUTCFG0_CFG4_Msk           (0x7000UL)                /*!< CFG4 (Bitfield-Mask: 0x07)                            */
11888 #define CTIMER_OUTCFG0_CFG3_Pos           (9UL)                     /*!< CFG3 (Bit 9)                                          */
11889 #define CTIMER_OUTCFG0_CFG3_Msk           (0xe00UL)                 /*!< CFG3 (Bitfield-Mask: 0x07)                            */
11890 #define CTIMER_OUTCFG0_CFG2_Pos           (6UL)                     /*!< CFG2 (Bit 6)                                          */
11891 #define CTIMER_OUTCFG0_CFG2_Msk           (0x1c0UL)                 /*!< CFG2 (Bitfield-Mask: 0x07)                            */
11892 #define CTIMER_OUTCFG0_CFG1_Pos           (3UL)                     /*!< CFG1 (Bit 3)                                          */
11893 #define CTIMER_OUTCFG0_CFG1_Msk           (0x38UL)                  /*!< CFG1 (Bitfield-Mask: 0x07)                            */
11894 #define CTIMER_OUTCFG0_CFG0_Pos           (0UL)                     /*!< CFG0 (Bit 0)                                          */
11895 #define CTIMER_OUTCFG0_CFG0_Msk           (0x7UL)                   /*!< CFG0 (Bitfield-Mask: 0x07)                            */
11896 /* ========================================================  OUTCFG1  ======================================================== */
11897 #define CTIMER_OUTCFG1_CFG19_Pos          (28UL)                    /*!< CFG19 (Bit 28)                                        */
11898 #define CTIMER_OUTCFG1_CFG19_Msk          (0x70000000UL)            /*!< CFG19 (Bitfield-Mask: 0x07)                           */
11899 #define CTIMER_OUTCFG1_CFG18_Pos          (25UL)                    /*!< CFG18 (Bit 25)                                        */
11900 #define CTIMER_OUTCFG1_CFG18_Msk          (0xe000000UL)             /*!< CFG18 (Bitfield-Mask: 0x07)                           */
11901 #define CTIMER_OUTCFG1_CFG17_Pos          (22UL)                    /*!< CFG17 (Bit 22)                                        */
11902 #define CTIMER_OUTCFG1_CFG17_Msk          (0x1c00000UL)             /*!< CFG17 (Bitfield-Mask: 0x07)                           */
11903 #define CTIMER_OUTCFG1_CFG16_Pos          (19UL)                    /*!< CFG16 (Bit 19)                                        */
11904 #define CTIMER_OUTCFG1_CFG16_Msk          (0x380000UL)              /*!< CFG16 (Bitfield-Mask: 0x07)                           */
11905 #define CTIMER_OUTCFG1_CFG15_Pos          (16UL)                    /*!< CFG15 (Bit 16)                                        */
11906 #define CTIMER_OUTCFG1_CFG15_Msk          (0x70000UL)               /*!< CFG15 (Bitfield-Mask: 0x07)                           */
11907 #define CTIMER_OUTCFG1_CFG14_Pos          (12UL)                    /*!< CFG14 (Bit 12)                                        */
11908 #define CTIMER_OUTCFG1_CFG14_Msk          (0x7000UL)                /*!< CFG14 (Bitfield-Mask: 0x07)                           */
11909 #define CTIMER_OUTCFG1_CFG13_Pos          (9UL)                     /*!< CFG13 (Bit 9)                                         */
11910 #define CTIMER_OUTCFG1_CFG13_Msk          (0xe00UL)                 /*!< CFG13 (Bitfield-Mask: 0x07)                           */
11911 #define CTIMER_OUTCFG1_CFG12_Pos          (6UL)                     /*!< CFG12 (Bit 6)                                         */
11912 #define CTIMER_OUTCFG1_CFG12_Msk          (0x1c0UL)                 /*!< CFG12 (Bitfield-Mask: 0x07)                           */
11913 #define CTIMER_OUTCFG1_CFG11_Pos          (3UL)                     /*!< CFG11 (Bit 3)                                         */
11914 #define CTIMER_OUTCFG1_CFG11_Msk          (0x38UL)                  /*!< CFG11 (Bitfield-Mask: 0x07)                           */
11915 #define CTIMER_OUTCFG1_CFG10_Pos          (0UL)                     /*!< CFG10 (Bit 0)                                         */
11916 #define CTIMER_OUTCFG1_CFG10_Msk          (0x7UL)                   /*!< CFG10 (Bitfield-Mask: 0x07)                           */
11917 /* ========================================================  OUTCFG2  ======================================================== */
11918 #define CTIMER_OUTCFG2_CFG29_Pos          (28UL)                    /*!< CFG29 (Bit 28)                                        */
11919 #define CTIMER_OUTCFG2_CFG29_Msk          (0x70000000UL)            /*!< CFG29 (Bitfield-Mask: 0x07)                           */
11920 #define CTIMER_OUTCFG2_CFG28_Pos          (25UL)                    /*!< CFG28 (Bit 25)                                        */
11921 #define CTIMER_OUTCFG2_CFG28_Msk          (0xe000000UL)             /*!< CFG28 (Bitfield-Mask: 0x07)                           */
11922 #define CTIMER_OUTCFG2_CFG27_Pos          (22UL)                    /*!< CFG27 (Bit 22)                                        */
11923 #define CTIMER_OUTCFG2_CFG27_Msk          (0x1c00000UL)             /*!< CFG27 (Bitfield-Mask: 0x07)                           */
11924 #define CTIMER_OUTCFG2_CFG26_Pos          (19UL)                    /*!< CFG26 (Bit 19)                                        */
11925 #define CTIMER_OUTCFG2_CFG26_Msk          (0x380000UL)              /*!< CFG26 (Bitfield-Mask: 0x07)                           */
11926 #define CTIMER_OUTCFG2_CFG25_Pos          (16UL)                    /*!< CFG25 (Bit 16)                                        */
11927 #define CTIMER_OUTCFG2_CFG25_Msk          (0x70000UL)               /*!< CFG25 (Bitfield-Mask: 0x07)                           */
11928 #define CTIMER_OUTCFG2_CFG24_Pos          (12UL)                    /*!< CFG24 (Bit 12)                                        */
11929 #define CTIMER_OUTCFG2_CFG24_Msk          (0x7000UL)                /*!< CFG24 (Bitfield-Mask: 0x07)                           */
11930 #define CTIMER_OUTCFG2_CFG23_Pos          (9UL)                     /*!< CFG23 (Bit 9)                                         */
11931 #define CTIMER_OUTCFG2_CFG23_Msk          (0xe00UL)                 /*!< CFG23 (Bitfield-Mask: 0x07)                           */
11932 #define CTIMER_OUTCFG2_CFG22_Pos          (6UL)                     /*!< CFG22 (Bit 6)                                         */
11933 #define CTIMER_OUTCFG2_CFG22_Msk          (0x1c0UL)                 /*!< CFG22 (Bitfield-Mask: 0x07)                           */
11934 #define CTIMER_OUTCFG2_CFG21_Pos          (3UL)                     /*!< CFG21 (Bit 3)                                         */
11935 #define CTIMER_OUTCFG2_CFG21_Msk          (0x38UL)                  /*!< CFG21 (Bitfield-Mask: 0x07)                           */
11936 #define CTIMER_OUTCFG2_CFG20_Pos          (0UL)                     /*!< CFG20 (Bit 0)                                         */
11937 #define CTIMER_OUTCFG2_CFG20_Msk          (0x7UL)                   /*!< CFG20 (Bitfield-Mask: 0x07)                           */
11938 /* ========================================================  OUTCFG3  ======================================================== */
11939 #define CTIMER_OUTCFG3_CFG31_Pos          (3UL)                     /*!< CFG31 (Bit 3)                                         */
11940 #define CTIMER_OUTCFG3_CFG31_Msk          (0x38UL)                  /*!< CFG31 (Bitfield-Mask: 0x07)                           */
11941 #define CTIMER_OUTCFG3_CFG30_Pos          (0UL)                     /*!< CFG30 (Bit 0)                                         */
11942 #define CTIMER_OUTCFG3_CFG30_Msk          (0x7UL)                   /*!< CFG30 (Bitfield-Mask: 0x07)                           */
11943 /* =========================================================  INCFG  ========================================================= */
11944 #define CTIMER_INCFG_CFGB7_Pos            (15UL)                    /*!< CFGB7 (Bit 15)                                        */
11945 #define CTIMER_INCFG_CFGB7_Msk            (0x8000UL)                /*!< CFGB7 (Bitfield-Mask: 0x01)                           */
11946 #define CTIMER_INCFG_CFGA7_Pos            (14UL)                    /*!< CFGA7 (Bit 14)                                        */
11947 #define CTIMER_INCFG_CFGA7_Msk            (0x4000UL)                /*!< CFGA7 (Bitfield-Mask: 0x01)                           */
11948 #define CTIMER_INCFG_CFGB6_Pos            (13UL)                    /*!< CFGB6 (Bit 13)                                        */
11949 #define CTIMER_INCFG_CFGB6_Msk            (0x2000UL)                /*!< CFGB6 (Bitfield-Mask: 0x01)                           */
11950 #define CTIMER_INCFG_CFGA6_Pos            (12UL)                    /*!< CFGA6 (Bit 12)                                        */
11951 #define CTIMER_INCFG_CFGA6_Msk            (0x1000UL)                /*!< CFGA6 (Bitfield-Mask: 0x01)                           */
11952 #define CTIMER_INCFG_CFGB5_Pos            (11UL)                    /*!< CFGB5 (Bit 11)                                        */
11953 #define CTIMER_INCFG_CFGB5_Msk            (0x800UL)                 /*!< CFGB5 (Bitfield-Mask: 0x01)                           */
11954 #define CTIMER_INCFG_CFGA5_Pos            (10UL)                    /*!< CFGA5 (Bit 10)                                        */
11955 #define CTIMER_INCFG_CFGA5_Msk            (0x400UL)                 /*!< CFGA5 (Bitfield-Mask: 0x01)                           */
11956 #define CTIMER_INCFG_CFGB4_Pos            (9UL)                     /*!< CFGB4 (Bit 9)                                         */
11957 #define CTIMER_INCFG_CFGB4_Msk            (0x200UL)                 /*!< CFGB4 (Bitfield-Mask: 0x01)                           */
11958 #define CTIMER_INCFG_CFGA4_Pos            (8UL)                     /*!< CFGA4 (Bit 8)                                         */
11959 #define CTIMER_INCFG_CFGA4_Msk            (0x100UL)                 /*!< CFGA4 (Bitfield-Mask: 0x01)                           */
11960 #define CTIMER_INCFG_CFGB3_Pos            (7UL)                     /*!< CFGB3 (Bit 7)                                         */
11961 #define CTIMER_INCFG_CFGB3_Msk            (0x80UL)                  /*!< CFGB3 (Bitfield-Mask: 0x01)                           */
11962 #define CTIMER_INCFG_CFGA3_Pos            (6UL)                     /*!< CFGA3 (Bit 6)                                         */
11963 #define CTIMER_INCFG_CFGA3_Msk            (0x40UL)                  /*!< CFGA3 (Bitfield-Mask: 0x01)                           */
11964 #define CTIMER_INCFG_CFGB2_Pos            (5UL)                     /*!< CFGB2 (Bit 5)                                         */
11965 #define CTIMER_INCFG_CFGB2_Msk            (0x20UL)                  /*!< CFGB2 (Bitfield-Mask: 0x01)                           */
11966 #define CTIMER_INCFG_CFGA2_Pos            (4UL)                     /*!< CFGA2 (Bit 4)                                         */
11967 #define CTIMER_INCFG_CFGA2_Msk            (0x10UL)                  /*!< CFGA2 (Bitfield-Mask: 0x01)                           */
11968 #define CTIMER_INCFG_CFGB1_Pos            (3UL)                     /*!< CFGB1 (Bit 3)                                         */
11969 #define CTIMER_INCFG_CFGB1_Msk            (0x8UL)                   /*!< CFGB1 (Bitfield-Mask: 0x01)                           */
11970 #define CTIMER_INCFG_CFGA1_Pos            (2UL)                     /*!< CFGA1 (Bit 2)                                         */
11971 #define CTIMER_INCFG_CFGA1_Msk            (0x4UL)                   /*!< CFGA1 (Bitfield-Mask: 0x01)                           */
11972 #define CTIMER_INCFG_CFGB0_Pos            (1UL)                     /*!< CFGB0 (Bit 1)                                         */
11973 #define CTIMER_INCFG_CFGB0_Msk            (0x2UL)                   /*!< CFGB0 (Bitfield-Mask: 0x01)                           */
11974 #define CTIMER_INCFG_CFGA0_Pos            (0UL)                     /*!< CFGA0 (Bit 0)                                         */
11975 #define CTIMER_INCFG_CFGA0_Msk            (0x1UL)                   /*!< CFGA0 (Bitfield-Mask: 0x01)                           */
11976 /* =========================================================  STCFG  ========================================================= */
11977 #define CTIMER_STCFG_FREEZE_Pos           (31UL)                    /*!< FREEZE (Bit 31)                                       */
11978 #define CTIMER_STCFG_FREEZE_Msk           (0x80000000UL)            /*!< FREEZE (Bitfield-Mask: 0x01)                          */
11979 #define CTIMER_STCFG_CLEAR_Pos            (30UL)                    /*!< CLEAR (Bit 30)                                        */
11980 #define CTIMER_STCFG_CLEAR_Msk            (0x40000000UL)            /*!< CLEAR (Bitfield-Mask: 0x01)                           */
11981 #define CTIMER_STCFG_COMPARE_H_EN_Pos     (15UL)                    /*!< COMPARE_H_EN (Bit 15)                                 */
11982 #define CTIMER_STCFG_COMPARE_H_EN_Msk     (0x8000UL)                /*!< COMPARE_H_EN (Bitfield-Mask: 0x01)                    */
11983 #define CTIMER_STCFG_COMPARE_G_EN_Pos     (14UL)                    /*!< COMPARE_G_EN (Bit 14)                                 */
11984 #define CTIMER_STCFG_COMPARE_G_EN_Msk     (0x4000UL)                /*!< COMPARE_G_EN (Bitfield-Mask: 0x01)                    */
11985 #define CTIMER_STCFG_COMPARE_F_EN_Pos     (13UL)                    /*!< COMPARE_F_EN (Bit 13)                                 */
11986 #define CTIMER_STCFG_COMPARE_F_EN_Msk     (0x2000UL)                /*!< COMPARE_F_EN (Bitfield-Mask: 0x01)                    */
11987 #define CTIMER_STCFG_COMPARE_E_EN_Pos     (12UL)                    /*!< COMPARE_E_EN (Bit 12)                                 */
11988 #define CTIMER_STCFG_COMPARE_E_EN_Msk     (0x1000UL)                /*!< COMPARE_E_EN (Bitfield-Mask: 0x01)                    */
11989 #define CTIMER_STCFG_COMPARE_D_EN_Pos     (11UL)                    /*!< COMPARE_D_EN (Bit 11)                                 */
11990 #define CTIMER_STCFG_COMPARE_D_EN_Msk     (0x800UL)                 /*!< COMPARE_D_EN (Bitfield-Mask: 0x01)                    */
11991 #define CTIMER_STCFG_COMPARE_C_EN_Pos     (10UL)                    /*!< COMPARE_C_EN (Bit 10)                                 */
11992 #define CTIMER_STCFG_COMPARE_C_EN_Msk     (0x400UL)                 /*!< COMPARE_C_EN (Bitfield-Mask: 0x01)                    */
11993 #define CTIMER_STCFG_COMPARE_B_EN_Pos     (9UL)                     /*!< COMPARE_B_EN (Bit 9)                                  */
11994 #define CTIMER_STCFG_COMPARE_B_EN_Msk     (0x200UL)                 /*!< COMPARE_B_EN (Bitfield-Mask: 0x01)                    */
11995 #define CTIMER_STCFG_COMPARE_A_EN_Pos     (8UL)                     /*!< COMPARE_A_EN (Bit 8)                                  */
11996 #define CTIMER_STCFG_COMPARE_A_EN_Msk     (0x100UL)                 /*!< COMPARE_A_EN (Bitfield-Mask: 0x01)                    */
11997 #define CTIMER_STCFG_CLKSEL_Pos           (0UL)                     /*!< CLKSEL (Bit 0)                                        */
11998 #define CTIMER_STCFG_CLKSEL_Msk           (0xfUL)                   /*!< CLKSEL (Bitfield-Mask: 0x0f)                          */
11999 /* =========================================================  STTMR  ========================================================= */
12000 #define CTIMER_STTMR_STTMR_Pos            (0UL)                     /*!< STTMR (Bit 0)                                         */
12001 #define CTIMER_STTMR_STTMR_Msk            (0xffffffffUL)            /*!< STTMR (Bitfield-Mask: 0xffffffff)                     */
12002 /* ====================================================  CAPTURECONTROL  ===================================================== */
12003 #define CTIMER_CAPTURECONTROL_CAPTURE3_Pos (3UL)                    /*!< CAPTURE3 (Bit 3)                                      */
12004 #define CTIMER_CAPTURECONTROL_CAPTURE3_Msk (0x8UL)                  /*!< CAPTURE3 (Bitfield-Mask: 0x01)                        */
12005 #define CTIMER_CAPTURECONTROL_CAPTURE2_Pos (2UL)                    /*!< CAPTURE2 (Bit 2)                                      */
12006 #define CTIMER_CAPTURECONTROL_CAPTURE2_Msk (0x4UL)                  /*!< CAPTURE2 (Bitfield-Mask: 0x01)                        */
12007 #define CTIMER_CAPTURECONTROL_CAPTURE1_Pos (1UL)                    /*!< CAPTURE1 (Bit 1)                                      */
12008 #define CTIMER_CAPTURECONTROL_CAPTURE1_Msk (0x2UL)                  /*!< CAPTURE1 (Bitfield-Mask: 0x01)                        */
12009 #define CTIMER_CAPTURECONTROL_CAPTURE0_Pos (0UL)                    /*!< CAPTURE0 (Bit 0)                                      */
12010 #define CTIMER_CAPTURECONTROL_CAPTURE0_Msk (0x1UL)                  /*!< CAPTURE0 (Bitfield-Mask: 0x01)                        */
12011 /* ========================================================  SCMPR0  ========================================================= */
12012 #define CTIMER_SCMPR0_SCMPR0_Pos          (0UL)                     /*!< SCMPR0 (Bit 0)                                        */
12013 #define CTIMER_SCMPR0_SCMPR0_Msk          (0xffffffffUL)            /*!< SCMPR0 (Bitfield-Mask: 0xffffffff)                    */
12014 /* ========================================================  SCMPR1  ========================================================= */
12015 #define CTIMER_SCMPR1_SCMPR1_Pos          (0UL)                     /*!< SCMPR1 (Bit 0)                                        */
12016 #define CTIMER_SCMPR1_SCMPR1_Msk          (0xffffffffUL)            /*!< SCMPR1 (Bitfield-Mask: 0xffffffff)                    */
12017 /* ========================================================  SCMPR2  ========================================================= */
12018 #define CTIMER_SCMPR2_SCMPR2_Pos          (0UL)                     /*!< SCMPR2 (Bit 0)                                        */
12019 #define CTIMER_SCMPR2_SCMPR2_Msk          (0xffffffffUL)            /*!< SCMPR2 (Bitfield-Mask: 0xffffffff)                    */
12020 /* ========================================================  SCMPR3  ========================================================= */
12021 #define CTIMER_SCMPR3_SCMPR3_Pos          (0UL)                     /*!< SCMPR3 (Bit 0)                                        */
12022 #define CTIMER_SCMPR3_SCMPR3_Msk          (0xffffffffUL)            /*!< SCMPR3 (Bitfield-Mask: 0xffffffff)                    */
12023 /* ========================================================  SCMPR4  ========================================================= */
12024 #define CTIMER_SCMPR4_SCMPR4_Pos          (0UL)                     /*!< SCMPR4 (Bit 0)                                        */
12025 #define CTIMER_SCMPR4_SCMPR4_Msk          (0xffffffffUL)            /*!< SCMPR4 (Bitfield-Mask: 0xffffffff)                    */
12026 /* ========================================================  SCMPR5  ========================================================= */
12027 #define CTIMER_SCMPR5_SCMPR5_Pos          (0UL)                     /*!< SCMPR5 (Bit 0)                                        */
12028 #define CTIMER_SCMPR5_SCMPR5_Msk          (0xffffffffUL)            /*!< SCMPR5 (Bitfield-Mask: 0xffffffff)                    */
12029 /* ========================================================  SCMPR6  ========================================================= */
12030 #define CTIMER_SCMPR6_SCMPR6_Pos          (0UL)                     /*!< SCMPR6 (Bit 0)                                        */
12031 #define CTIMER_SCMPR6_SCMPR6_Msk          (0xffffffffUL)            /*!< SCMPR6 (Bitfield-Mask: 0xffffffff)                    */
12032 /* ========================================================  SCMPR7  ========================================================= */
12033 #define CTIMER_SCMPR7_SCMPR7_Pos          (0UL)                     /*!< SCMPR7 (Bit 0)                                        */
12034 #define CTIMER_SCMPR7_SCMPR7_Msk          (0xffffffffUL)            /*!< SCMPR7 (Bitfield-Mask: 0xffffffff)                    */
12035 /* ========================================================  SCAPT0  ========================================================= */
12036 #define CTIMER_SCAPT0_SCAPT0_Pos          (0UL)                     /*!< SCAPT0 (Bit 0)                                        */
12037 #define CTIMER_SCAPT0_SCAPT0_Msk          (0xffffffffUL)            /*!< SCAPT0 (Bitfield-Mask: 0xffffffff)                    */
12038 /* ========================================================  SCAPT1  ========================================================= */
12039 #define CTIMER_SCAPT1_SCAPT1_Pos          (0UL)                     /*!< SCAPT1 (Bit 0)                                        */
12040 #define CTIMER_SCAPT1_SCAPT1_Msk          (0xffffffffUL)            /*!< SCAPT1 (Bitfield-Mask: 0xffffffff)                    */
12041 /* ========================================================  SCAPT2  ========================================================= */
12042 #define CTIMER_SCAPT2_SCAPT2_Pos          (0UL)                     /*!< SCAPT2 (Bit 0)                                        */
12043 #define CTIMER_SCAPT2_SCAPT2_Msk          (0xffffffffUL)            /*!< SCAPT2 (Bitfield-Mask: 0xffffffff)                    */
12044 /* ========================================================  SCAPT3  ========================================================= */
12045 #define CTIMER_SCAPT3_SCAPT3_Pos          (0UL)                     /*!< SCAPT3 (Bit 0)                                        */
12046 #define CTIMER_SCAPT3_SCAPT3_Msk          (0xffffffffUL)            /*!< SCAPT3 (Bitfield-Mask: 0xffffffff)                    */
12047 /* =========================================================  SNVR0  ========================================================= */
12048 #define CTIMER_SNVR0_SNVR0_Pos            (0UL)                     /*!< SNVR0 (Bit 0)                                         */
12049 #define CTIMER_SNVR0_SNVR0_Msk            (0xffffffffUL)            /*!< SNVR0 (Bitfield-Mask: 0xffffffff)                     */
12050 /* =========================================================  SNVR1  ========================================================= */
12051 #define CTIMER_SNVR1_SNVR1_Pos            (0UL)                     /*!< SNVR1 (Bit 0)                                         */
12052 #define CTIMER_SNVR1_SNVR1_Msk            (0xffffffffUL)            /*!< SNVR1 (Bitfield-Mask: 0xffffffff)                     */
12053 /* =========================================================  SNVR2  ========================================================= */
12054 #define CTIMER_SNVR2_SNVR2_Pos            (0UL)                     /*!< SNVR2 (Bit 0)                                         */
12055 #define CTIMER_SNVR2_SNVR2_Msk            (0xffffffffUL)            /*!< SNVR2 (Bitfield-Mask: 0xffffffff)                     */
12056 /* =========================================================  SNVR3  ========================================================= */
12057 #define CTIMER_SNVR3_SNVR3_Pos            (0UL)                     /*!< SNVR3 (Bit 0)                                         */
12058 #define CTIMER_SNVR3_SNVR3_Msk            (0xffffffffUL)            /*!< SNVR3 (Bitfield-Mask: 0xffffffff)                     */
12059 /* =========================================================  INTEN  ========================================================= */
12060 #define CTIMER_INTEN_CTMRB7C1INT_Pos      (31UL)                    /*!< CTMRB7C1INT (Bit 31)                                  */
12061 #define CTIMER_INTEN_CTMRB7C1INT_Msk      (0x80000000UL)            /*!< CTMRB7C1INT (Bitfield-Mask: 0x01)                     */
12062 #define CTIMER_INTEN_CTMRA7C1INT_Pos      (30UL)                    /*!< CTMRA7C1INT (Bit 30)                                  */
12063 #define CTIMER_INTEN_CTMRA7C1INT_Msk      (0x40000000UL)            /*!< CTMRA7C1INT (Bitfield-Mask: 0x01)                     */
12064 #define CTIMER_INTEN_CTMRB6C1INT_Pos      (29UL)                    /*!< CTMRB6C1INT (Bit 29)                                  */
12065 #define CTIMER_INTEN_CTMRB6C1INT_Msk      (0x20000000UL)            /*!< CTMRB6C1INT (Bitfield-Mask: 0x01)                     */
12066 #define CTIMER_INTEN_CTMRA6C1INT_Pos      (28UL)                    /*!< CTMRA6C1INT (Bit 28)                                  */
12067 #define CTIMER_INTEN_CTMRA6C1INT_Msk      (0x10000000UL)            /*!< CTMRA6C1INT (Bitfield-Mask: 0x01)                     */
12068 #define CTIMER_INTEN_CTMRB5C1INT_Pos      (27UL)                    /*!< CTMRB5C1INT (Bit 27)                                  */
12069 #define CTIMER_INTEN_CTMRB5C1INT_Msk      (0x8000000UL)             /*!< CTMRB5C1INT (Bitfield-Mask: 0x01)                     */
12070 #define CTIMER_INTEN_CTMRA5C1INT_Pos      (26UL)                    /*!< CTMRA5C1INT (Bit 26)                                  */
12071 #define CTIMER_INTEN_CTMRA5C1INT_Msk      (0x4000000UL)             /*!< CTMRA5C1INT (Bitfield-Mask: 0x01)                     */
12072 #define CTIMER_INTEN_CTMRB4C1INT_Pos      (25UL)                    /*!< CTMRB4C1INT (Bit 25)                                  */
12073 #define CTIMER_INTEN_CTMRB4C1INT_Msk      (0x2000000UL)             /*!< CTMRB4C1INT (Bitfield-Mask: 0x01)                     */
12074 #define CTIMER_INTEN_CTMRA4C1INT_Pos      (24UL)                    /*!< CTMRA4C1INT (Bit 24)                                  */
12075 #define CTIMER_INTEN_CTMRA4C1INT_Msk      (0x1000000UL)             /*!< CTMRA4C1INT (Bitfield-Mask: 0x01)                     */
12076 #define CTIMER_INTEN_CTMRB3C1INT_Pos      (23UL)                    /*!< CTMRB3C1INT (Bit 23)                                  */
12077 #define CTIMER_INTEN_CTMRB3C1INT_Msk      (0x800000UL)              /*!< CTMRB3C1INT (Bitfield-Mask: 0x01)                     */
12078 #define CTIMER_INTEN_CTMRA3C1INT_Pos      (22UL)                    /*!< CTMRA3C1INT (Bit 22)                                  */
12079 #define CTIMER_INTEN_CTMRA3C1INT_Msk      (0x400000UL)              /*!< CTMRA3C1INT (Bitfield-Mask: 0x01)                     */
12080 #define CTIMER_INTEN_CTMRB2C1INT_Pos      (21UL)                    /*!< CTMRB2C1INT (Bit 21)                                  */
12081 #define CTIMER_INTEN_CTMRB2C1INT_Msk      (0x200000UL)              /*!< CTMRB2C1INT (Bitfield-Mask: 0x01)                     */
12082 #define CTIMER_INTEN_CTMRA2C1INT_Pos      (20UL)                    /*!< CTMRA2C1INT (Bit 20)                                  */
12083 #define CTIMER_INTEN_CTMRA2C1INT_Msk      (0x100000UL)              /*!< CTMRA2C1INT (Bitfield-Mask: 0x01)                     */
12084 #define CTIMER_INTEN_CTMRB1C1INT_Pos      (19UL)                    /*!< CTMRB1C1INT (Bit 19)                                  */
12085 #define CTIMER_INTEN_CTMRB1C1INT_Msk      (0x80000UL)               /*!< CTMRB1C1INT (Bitfield-Mask: 0x01)                     */
12086 #define CTIMER_INTEN_CTMRA1C1INT_Pos      (18UL)                    /*!< CTMRA1C1INT (Bit 18)                                  */
12087 #define CTIMER_INTEN_CTMRA1C1INT_Msk      (0x40000UL)               /*!< CTMRA1C1INT (Bitfield-Mask: 0x01)                     */
12088 #define CTIMER_INTEN_CTMRB0C1INT_Pos      (17UL)                    /*!< CTMRB0C1INT (Bit 17)                                  */
12089 #define CTIMER_INTEN_CTMRB0C1INT_Msk      (0x20000UL)               /*!< CTMRB0C1INT (Bitfield-Mask: 0x01)                     */
12090 #define CTIMER_INTEN_CTMRA0C1INT_Pos      (16UL)                    /*!< CTMRA0C1INT (Bit 16)                                  */
12091 #define CTIMER_INTEN_CTMRA0C1INT_Msk      (0x10000UL)               /*!< CTMRA0C1INT (Bitfield-Mask: 0x01)                     */
12092 #define CTIMER_INTEN_CTMRB7C0INT_Pos      (15UL)                    /*!< CTMRB7C0INT (Bit 15)                                  */
12093 #define CTIMER_INTEN_CTMRB7C0INT_Msk      (0x8000UL)                /*!< CTMRB7C0INT (Bitfield-Mask: 0x01)                     */
12094 #define CTIMER_INTEN_CTMRA7C0INT_Pos      (14UL)                    /*!< CTMRA7C0INT (Bit 14)                                  */
12095 #define CTIMER_INTEN_CTMRA7C0INT_Msk      (0x4000UL)                /*!< CTMRA7C0INT (Bitfield-Mask: 0x01)                     */
12096 #define CTIMER_INTEN_CTMRB6C0INT_Pos      (13UL)                    /*!< CTMRB6C0INT (Bit 13)                                  */
12097 #define CTIMER_INTEN_CTMRB6C0INT_Msk      (0x2000UL)                /*!< CTMRB6C0INT (Bitfield-Mask: 0x01)                     */
12098 #define CTIMER_INTEN_CTMRA6C0INT_Pos      (12UL)                    /*!< CTMRA6C0INT (Bit 12)                                  */
12099 #define CTIMER_INTEN_CTMRA6C0INT_Msk      (0x1000UL)                /*!< CTMRA6C0INT (Bitfield-Mask: 0x01)                     */
12100 #define CTIMER_INTEN_CTMRB5C0INT_Pos      (11UL)                    /*!< CTMRB5C0INT (Bit 11)                                  */
12101 #define CTIMER_INTEN_CTMRB5C0INT_Msk      (0x800UL)                 /*!< CTMRB5C0INT (Bitfield-Mask: 0x01)                     */
12102 #define CTIMER_INTEN_CTMRA5C0INT_Pos      (10UL)                    /*!< CTMRA5C0INT (Bit 10)                                  */
12103 #define CTIMER_INTEN_CTMRA5C0INT_Msk      (0x400UL)                 /*!< CTMRA5C0INT (Bitfield-Mask: 0x01)                     */
12104 #define CTIMER_INTEN_CTMRB4C0INT_Pos      (9UL)                     /*!< CTMRB4C0INT (Bit 9)                                   */
12105 #define CTIMER_INTEN_CTMRB4C0INT_Msk      (0x200UL)                 /*!< CTMRB4C0INT (Bitfield-Mask: 0x01)                     */
12106 #define CTIMER_INTEN_CTMRA4C0INT_Pos      (8UL)                     /*!< CTMRA4C0INT (Bit 8)                                   */
12107 #define CTIMER_INTEN_CTMRA4C0INT_Msk      (0x100UL)                 /*!< CTMRA4C0INT (Bitfield-Mask: 0x01)                     */
12108 #define CTIMER_INTEN_CTMRB3C0INT_Pos      (7UL)                     /*!< CTMRB3C0INT (Bit 7)                                   */
12109 #define CTIMER_INTEN_CTMRB3C0INT_Msk      (0x80UL)                  /*!< CTMRB3C0INT (Bitfield-Mask: 0x01)                     */
12110 #define CTIMER_INTEN_CTMRA3C0INT_Pos      (6UL)                     /*!< CTMRA3C0INT (Bit 6)                                   */
12111 #define CTIMER_INTEN_CTMRA3C0INT_Msk      (0x40UL)                  /*!< CTMRA3C0INT (Bitfield-Mask: 0x01)                     */
12112 #define CTIMER_INTEN_CTMRB2C0INT_Pos      (5UL)                     /*!< CTMRB2C0INT (Bit 5)                                   */
12113 #define CTIMER_INTEN_CTMRB2C0INT_Msk      (0x20UL)                  /*!< CTMRB2C0INT (Bitfield-Mask: 0x01)                     */
12114 #define CTIMER_INTEN_CTMRA2C0INT_Pos      (4UL)                     /*!< CTMRA2C0INT (Bit 4)                                   */
12115 #define CTIMER_INTEN_CTMRA2C0INT_Msk      (0x10UL)                  /*!< CTMRA2C0INT (Bitfield-Mask: 0x01)                     */
12116 #define CTIMER_INTEN_CTMRB1C0INT_Pos      (3UL)                     /*!< CTMRB1C0INT (Bit 3)                                   */
12117 #define CTIMER_INTEN_CTMRB1C0INT_Msk      (0x8UL)                   /*!< CTMRB1C0INT (Bitfield-Mask: 0x01)                     */
12118 #define CTIMER_INTEN_CTMRA1C0INT_Pos      (2UL)                     /*!< CTMRA1C0INT (Bit 2)                                   */
12119 #define CTIMER_INTEN_CTMRA1C0INT_Msk      (0x4UL)                   /*!< CTMRA1C0INT (Bitfield-Mask: 0x01)                     */
12120 #define CTIMER_INTEN_CTMRB0C0INT_Pos      (1UL)                     /*!< CTMRB0C0INT (Bit 1)                                   */
12121 #define CTIMER_INTEN_CTMRB0C0INT_Msk      (0x2UL)                   /*!< CTMRB0C0INT (Bitfield-Mask: 0x01)                     */
12122 #define CTIMER_INTEN_CTMRA0C0INT_Pos      (0UL)                     /*!< CTMRA0C0INT (Bit 0)                                   */
12123 #define CTIMER_INTEN_CTMRA0C0INT_Msk      (0x1UL)                   /*!< CTMRA0C0INT (Bitfield-Mask: 0x01)                     */
12124 /* ========================================================  INTSTAT  ======================================================== */
12125 #define CTIMER_INTSTAT_CTMRB7C1INT_Pos    (31UL)                    /*!< CTMRB7C1INT (Bit 31)                                  */
12126 #define CTIMER_INTSTAT_CTMRB7C1INT_Msk    (0x80000000UL)            /*!< CTMRB7C1INT (Bitfield-Mask: 0x01)                     */
12127 #define CTIMER_INTSTAT_CTMRA7C1INT_Pos    (30UL)                    /*!< CTMRA7C1INT (Bit 30)                                  */
12128 #define CTIMER_INTSTAT_CTMRA7C1INT_Msk    (0x40000000UL)            /*!< CTMRA7C1INT (Bitfield-Mask: 0x01)                     */
12129 #define CTIMER_INTSTAT_CTMRB6C1INT_Pos    (29UL)                    /*!< CTMRB6C1INT (Bit 29)                                  */
12130 #define CTIMER_INTSTAT_CTMRB6C1INT_Msk    (0x20000000UL)            /*!< CTMRB6C1INT (Bitfield-Mask: 0x01)                     */
12131 #define CTIMER_INTSTAT_CTMRA6C1INT_Pos    (28UL)                    /*!< CTMRA6C1INT (Bit 28)                                  */
12132 #define CTIMER_INTSTAT_CTMRA6C1INT_Msk    (0x10000000UL)            /*!< CTMRA6C1INT (Bitfield-Mask: 0x01)                     */
12133 #define CTIMER_INTSTAT_CTMRB5C1INT_Pos    (27UL)                    /*!< CTMRB5C1INT (Bit 27)                                  */
12134 #define CTIMER_INTSTAT_CTMRB5C1INT_Msk    (0x8000000UL)             /*!< CTMRB5C1INT (Bitfield-Mask: 0x01)                     */
12135 #define CTIMER_INTSTAT_CTMRA5C1INT_Pos    (26UL)                    /*!< CTMRA5C1INT (Bit 26)                                  */
12136 #define CTIMER_INTSTAT_CTMRA5C1INT_Msk    (0x4000000UL)             /*!< CTMRA5C1INT (Bitfield-Mask: 0x01)                     */
12137 #define CTIMER_INTSTAT_CTMRB4C1INT_Pos    (25UL)                    /*!< CTMRB4C1INT (Bit 25)                                  */
12138 #define CTIMER_INTSTAT_CTMRB4C1INT_Msk    (0x2000000UL)             /*!< CTMRB4C1INT (Bitfield-Mask: 0x01)                     */
12139 #define CTIMER_INTSTAT_CTMRA4C1INT_Pos    (24UL)                    /*!< CTMRA4C1INT (Bit 24)                                  */
12140 #define CTIMER_INTSTAT_CTMRA4C1INT_Msk    (0x1000000UL)             /*!< CTMRA4C1INT (Bitfield-Mask: 0x01)                     */
12141 #define CTIMER_INTSTAT_CTMRB3C1INT_Pos    (23UL)                    /*!< CTMRB3C1INT (Bit 23)                                  */
12142 #define CTIMER_INTSTAT_CTMRB3C1INT_Msk    (0x800000UL)              /*!< CTMRB3C1INT (Bitfield-Mask: 0x01)                     */
12143 #define CTIMER_INTSTAT_CTMRA3C1INT_Pos    (22UL)                    /*!< CTMRA3C1INT (Bit 22)                                  */
12144 #define CTIMER_INTSTAT_CTMRA3C1INT_Msk    (0x400000UL)              /*!< CTMRA3C1INT (Bitfield-Mask: 0x01)                     */
12145 #define CTIMER_INTSTAT_CTMRB2C1INT_Pos    (21UL)                    /*!< CTMRB2C1INT (Bit 21)                                  */
12146 #define CTIMER_INTSTAT_CTMRB2C1INT_Msk    (0x200000UL)              /*!< CTMRB2C1INT (Bitfield-Mask: 0x01)                     */
12147 #define CTIMER_INTSTAT_CTMRA2C1INT_Pos    (20UL)                    /*!< CTMRA2C1INT (Bit 20)                                  */
12148 #define CTIMER_INTSTAT_CTMRA2C1INT_Msk    (0x100000UL)              /*!< CTMRA2C1INT (Bitfield-Mask: 0x01)                     */
12149 #define CTIMER_INTSTAT_CTMRB1C1INT_Pos    (19UL)                    /*!< CTMRB1C1INT (Bit 19)                                  */
12150 #define CTIMER_INTSTAT_CTMRB1C1INT_Msk    (0x80000UL)               /*!< CTMRB1C1INT (Bitfield-Mask: 0x01)                     */
12151 #define CTIMER_INTSTAT_CTMRA1C1INT_Pos    (18UL)                    /*!< CTMRA1C1INT (Bit 18)                                  */
12152 #define CTIMER_INTSTAT_CTMRA1C1INT_Msk    (0x40000UL)               /*!< CTMRA1C1INT (Bitfield-Mask: 0x01)                     */
12153 #define CTIMER_INTSTAT_CTMRB0C1INT_Pos    (17UL)                    /*!< CTMRB0C1INT (Bit 17)                                  */
12154 #define CTIMER_INTSTAT_CTMRB0C1INT_Msk    (0x20000UL)               /*!< CTMRB0C1INT (Bitfield-Mask: 0x01)                     */
12155 #define CTIMER_INTSTAT_CTMRA0C1INT_Pos    (16UL)                    /*!< CTMRA0C1INT (Bit 16)                                  */
12156 #define CTIMER_INTSTAT_CTMRA0C1INT_Msk    (0x10000UL)               /*!< CTMRA0C1INT (Bitfield-Mask: 0x01)                     */
12157 #define CTIMER_INTSTAT_CTMRB7C0INT_Pos    (15UL)                    /*!< CTMRB7C0INT (Bit 15)                                  */
12158 #define CTIMER_INTSTAT_CTMRB7C0INT_Msk    (0x8000UL)                /*!< CTMRB7C0INT (Bitfield-Mask: 0x01)                     */
12159 #define CTIMER_INTSTAT_CTMRA7C0INT_Pos    (14UL)                    /*!< CTMRA7C0INT (Bit 14)                                  */
12160 #define CTIMER_INTSTAT_CTMRA7C0INT_Msk    (0x4000UL)                /*!< CTMRA7C0INT (Bitfield-Mask: 0x01)                     */
12161 #define CTIMER_INTSTAT_CTMRB6C0INT_Pos    (13UL)                    /*!< CTMRB6C0INT (Bit 13)                                  */
12162 #define CTIMER_INTSTAT_CTMRB6C0INT_Msk    (0x2000UL)                /*!< CTMRB6C0INT (Bitfield-Mask: 0x01)                     */
12163 #define CTIMER_INTSTAT_CTMRA6C0INT_Pos    (12UL)                    /*!< CTMRA6C0INT (Bit 12)                                  */
12164 #define CTIMER_INTSTAT_CTMRA6C0INT_Msk    (0x1000UL)                /*!< CTMRA6C0INT (Bitfield-Mask: 0x01)                     */
12165 #define CTIMER_INTSTAT_CTMRB5C0INT_Pos    (11UL)                    /*!< CTMRB5C0INT (Bit 11)                                  */
12166 #define CTIMER_INTSTAT_CTMRB5C0INT_Msk    (0x800UL)                 /*!< CTMRB5C0INT (Bitfield-Mask: 0x01)                     */
12167 #define CTIMER_INTSTAT_CTMRA5C0INT_Pos    (10UL)                    /*!< CTMRA5C0INT (Bit 10)                                  */
12168 #define CTIMER_INTSTAT_CTMRA5C0INT_Msk    (0x400UL)                 /*!< CTMRA5C0INT (Bitfield-Mask: 0x01)                     */
12169 #define CTIMER_INTSTAT_CTMRB4C0INT_Pos    (9UL)                     /*!< CTMRB4C0INT (Bit 9)                                   */
12170 #define CTIMER_INTSTAT_CTMRB4C0INT_Msk    (0x200UL)                 /*!< CTMRB4C0INT (Bitfield-Mask: 0x01)                     */
12171 #define CTIMER_INTSTAT_CTMRA4C0INT_Pos    (8UL)                     /*!< CTMRA4C0INT (Bit 8)                                   */
12172 #define CTIMER_INTSTAT_CTMRA4C0INT_Msk    (0x100UL)                 /*!< CTMRA4C0INT (Bitfield-Mask: 0x01)                     */
12173 #define CTIMER_INTSTAT_CTMRB3C0INT_Pos    (7UL)                     /*!< CTMRB3C0INT (Bit 7)                                   */
12174 #define CTIMER_INTSTAT_CTMRB3C0INT_Msk    (0x80UL)                  /*!< CTMRB3C0INT (Bitfield-Mask: 0x01)                     */
12175 #define CTIMER_INTSTAT_CTMRA3C0INT_Pos    (6UL)                     /*!< CTMRA3C0INT (Bit 6)                                   */
12176 #define CTIMER_INTSTAT_CTMRA3C0INT_Msk    (0x40UL)                  /*!< CTMRA3C0INT (Bitfield-Mask: 0x01)                     */
12177 #define CTIMER_INTSTAT_CTMRB2C0INT_Pos    (5UL)                     /*!< CTMRB2C0INT (Bit 5)                                   */
12178 #define CTIMER_INTSTAT_CTMRB2C0INT_Msk    (0x20UL)                  /*!< CTMRB2C0INT (Bitfield-Mask: 0x01)                     */
12179 #define CTIMER_INTSTAT_CTMRA2C0INT_Pos    (4UL)                     /*!< CTMRA2C0INT (Bit 4)                                   */
12180 #define CTIMER_INTSTAT_CTMRA2C0INT_Msk    (0x10UL)                  /*!< CTMRA2C0INT (Bitfield-Mask: 0x01)                     */
12181 #define CTIMER_INTSTAT_CTMRB1C0INT_Pos    (3UL)                     /*!< CTMRB1C0INT (Bit 3)                                   */
12182 #define CTIMER_INTSTAT_CTMRB1C0INT_Msk    (0x8UL)                   /*!< CTMRB1C0INT (Bitfield-Mask: 0x01)                     */
12183 #define CTIMER_INTSTAT_CTMRA1C0INT_Pos    (2UL)                     /*!< CTMRA1C0INT (Bit 2)                                   */
12184 #define CTIMER_INTSTAT_CTMRA1C0INT_Msk    (0x4UL)                   /*!< CTMRA1C0INT (Bitfield-Mask: 0x01)                     */
12185 #define CTIMER_INTSTAT_CTMRB0C0INT_Pos    (1UL)                     /*!< CTMRB0C0INT (Bit 1)                                   */
12186 #define CTIMER_INTSTAT_CTMRB0C0INT_Msk    (0x2UL)                   /*!< CTMRB0C0INT (Bitfield-Mask: 0x01)                     */
12187 #define CTIMER_INTSTAT_CTMRA0C0INT_Pos    (0UL)                     /*!< CTMRA0C0INT (Bit 0)                                   */
12188 #define CTIMER_INTSTAT_CTMRA0C0INT_Msk    (0x1UL)                   /*!< CTMRA0C0INT (Bitfield-Mask: 0x01)                     */
12189 /* ========================================================  INTCLR  ========================================================= */
12190 #define CTIMER_INTCLR_CTMRB7C1INT_Pos     (31UL)                    /*!< CTMRB7C1INT (Bit 31)                                  */
12191 #define CTIMER_INTCLR_CTMRB7C1INT_Msk     (0x80000000UL)            /*!< CTMRB7C1INT (Bitfield-Mask: 0x01)                     */
12192 #define CTIMER_INTCLR_CTMRA7C1INT_Pos     (30UL)                    /*!< CTMRA7C1INT (Bit 30)                                  */
12193 #define CTIMER_INTCLR_CTMRA7C1INT_Msk     (0x40000000UL)            /*!< CTMRA7C1INT (Bitfield-Mask: 0x01)                     */
12194 #define CTIMER_INTCLR_CTMRB6C1INT_Pos     (29UL)                    /*!< CTMRB6C1INT (Bit 29)                                  */
12195 #define CTIMER_INTCLR_CTMRB6C1INT_Msk     (0x20000000UL)            /*!< CTMRB6C1INT (Bitfield-Mask: 0x01)                     */
12196 #define CTIMER_INTCLR_CTMRA6C1INT_Pos     (28UL)                    /*!< CTMRA6C1INT (Bit 28)                                  */
12197 #define CTIMER_INTCLR_CTMRA6C1INT_Msk     (0x10000000UL)            /*!< CTMRA6C1INT (Bitfield-Mask: 0x01)                     */
12198 #define CTIMER_INTCLR_CTMRB5C1INT_Pos     (27UL)                    /*!< CTMRB5C1INT (Bit 27)                                  */
12199 #define CTIMER_INTCLR_CTMRB5C1INT_Msk     (0x8000000UL)             /*!< CTMRB5C1INT (Bitfield-Mask: 0x01)                     */
12200 #define CTIMER_INTCLR_CTMRA5C1INT_Pos     (26UL)                    /*!< CTMRA5C1INT (Bit 26)                                  */
12201 #define CTIMER_INTCLR_CTMRA5C1INT_Msk     (0x4000000UL)             /*!< CTMRA5C1INT (Bitfield-Mask: 0x01)                     */
12202 #define CTIMER_INTCLR_CTMRB4C1INT_Pos     (25UL)                    /*!< CTMRB4C1INT (Bit 25)                                  */
12203 #define CTIMER_INTCLR_CTMRB4C1INT_Msk     (0x2000000UL)             /*!< CTMRB4C1INT (Bitfield-Mask: 0x01)                     */
12204 #define CTIMER_INTCLR_CTMRA4C1INT_Pos     (24UL)                    /*!< CTMRA4C1INT (Bit 24)                                  */
12205 #define CTIMER_INTCLR_CTMRA4C1INT_Msk     (0x1000000UL)             /*!< CTMRA4C1INT (Bitfield-Mask: 0x01)                     */
12206 #define CTIMER_INTCLR_CTMRB3C1INT_Pos     (23UL)                    /*!< CTMRB3C1INT (Bit 23)                                  */
12207 #define CTIMER_INTCLR_CTMRB3C1INT_Msk     (0x800000UL)              /*!< CTMRB3C1INT (Bitfield-Mask: 0x01)                     */
12208 #define CTIMER_INTCLR_CTMRA3C1INT_Pos     (22UL)                    /*!< CTMRA3C1INT (Bit 22)                                  */
12209 #define CTIMER_INTCLR_CTMRA3C1INT_Msk     (0x400000UL)              /*!< CTMRA3C1INT (Bitfield-Mask: 0x01)                     */
12210 #define CTIMER_INTCLR_CTMRB2C1INT_Pos     (21UL)                    /*!< CTMRB2C1INT (Bit 21)                                  */
12211 #define CTIMER_INTCLR_CTMRB2C1INT_Msk     (0x200000UL)              /*!< CTMRB2C1INT (Bitfield-Mask: 0x01)                     */
12212 #define CTIMER_INTCLR_CTMRA2C1INT_Pos     (20UL)                    /*!< CTMRA2C1INT (Bit 20)                                  */
12213 #define CTIMER_INTCLR_CTMRA2C1INT_Msk     (0x100000UL)              /*!< CTMRA2C1INT (Bitfield-Mask: 0x01)                     */
12214 #define CTIMER_INTCLR_CTMRB1C1INT_Pos     (19UL)                    /*!< CTMRB1C1INT (Bit 19)                                  */
12215 #define CTIMER_INTCLR_CTMRB1C1INT_Msk     (0x80000UL)               /*!< CTMRB1C1INT (Bitfield-Mask: 0x01)                     */
12216 #define CTIMER_INTCLR_CTMRA1C1INT_Pos     (18UL)                    /*!< CTMRA1C1INT (Bit 18)                                  */
12217 #define CTIMER_INTCLR_CTMRA1C1INT_Msk     (0x40000UL)               /*!< CTMRA1C1INT (Bitfield-Mask: 0x01)                     */
12218 #define CTIMER_INTCLR_CTMRB0C1INT_Pos     (17UL)                    /*!< CTMRB0C1INT (Bit 17)                                  */
12219 #define CTIMER_INTCLR_CTMRB0C1INT_Msk     (0x20000UL)               /*!< CTMRB0C1INT (Bitfield-Mask: 0x01)                     */
12220 #define CTIMER_INTCLR_CTMRA0C1INT_Pos     (16UL)                    /*!< CTMRA0C1INT (Bit 16)                                  */
12221 #define CTIMER_INTCLR_CTMRA0C1INT_Msk     (0x10000UL)               /*!< CTMRA0C1INT (Bitfield-Mask: 0x01)                     */
12222 #define CTIMER_INTCLR_CTMRB7C0INT_Pos     (15UL)                    /*!< CTMRB7C0INT (Bit 15)                                  */
12223 #define CTIMER_INTCLR_CTMRB7C0INT_Msk     (0x8000UL)                /*!< CTMRB7C0INT (Bitfield-Mask: 0x01)                     */
12224 #define CTIMER_INTCLR_CTMRA7C0INT_Pos     (14UL)                    /*!< CTMRA7C0INT (Bit 14)                                  */
12225 #define CTIMER_INTCLR_CTMRA7C0INT_Msk     (0x4000UL)                /*!< CTMRA7C0INT (Bitfield-Mask: 0x01)                     */
12226 #define CTIMER_INTCLR_CTMRB6C0INT_Pos     (13UL)                    /*!< CTMRB6C0INT (Bit 13)                                  */
12227 #define CTIMER_INTCLR_CTMRB6C0INT_Msk     (0x2000UL)                /*!< CTMRB6C0INT (Bitfield-Mask: 0x01)                     */
12228 #define CTIMER_INTCLR_CTMRA6C0INT_Pos     (12UL)                    /*!< CTMRA6C0INT (Bit 12)                                  */
12229 #define CTIMER_INTCLR_CTMRA6C0INT_Msk     (0x1000UL)                /*!< CTMRA6C0INT (Bitfield-Mask: 0x01)                     */
12230 #define CTIMER_INTCLR_CTMRB5C0INT_Pos     (11UL)                    /*!< CTMRB5C0INT (Bit 11)                                  */
12231 #define CTIMER_INTCLR_CTMRB5C0INT_Msk     (0x800UL)                 /*!< CTMRB5C0INT (Bitfield-Mask: 0x01)                     */
12232 #define CTIMER_INTCLR_CTMRA5C0INT_Pos     (10UL)                    /*!< CTMRA5C0INT (Bit 10)                                  */
12233 #define CTIMER_INTCLR_CTMRA5C0INT_Msk     (0x400UL)                 /*!< CTMRA5C0INT (Bitfield-Mask: 0x01)                     */
12234 #define CTIMER_INTCLR_CTMRB4C0INT_Pos     (9UL)                     /*!< CTMRB4C0INT (Bit 9)                                   */
12235 #define CTIMER_INTCLR_CTMRB4C0INT_Msk     (0x200UL)                 /*!< CTMRB4C0INT (Bitfield-Mask: 0x01)                     */
12236 #define CTIMER_INTCLR_CTMRA4C0INT_Pos     (8UL)                     /*!< CTMRA4C0INT (Bit 8)                                   */
12237 #define CTIMER_INTCLR_CTMRA4C0INT_Msk     (0x100UL)                 /*!< CTMRA4C0INT (Bitfield-Mask: 0x01)                     */
12238 #define CTIMER_INTCLR_CTMRB3C0INT_Pos     (7UL)                     /*!< CTMRB3C0INT (Bit 7)                                   */
12239 #define CTIMER_INTCLR_CTMRB3C0INT_Msk     (0x80UL)                  /*!< CTMRB3C0INT (Bitfield-Mask: 0x01)                     */
12240 #define CTIMER_INTCLR_CTMRA3C0INT_Pos     (6UL)                     /*!< CTMRA3C0INT (Bit 6)                                   */
12241 #define CTIMER_INTCLR_CTMRA3C0INT_Msk     (0x40UL)                  /*!< CTMRA3C0INT (Bitfield-Mask: 0x01)                     */
12242 #define CTIMER_INTCLR_CTMRB2C0INT_Pos     (5UL)                     /*!< CTMRB2C0INT (Bit 5)                                   */
12243 #define CTIMER_INTCLR_CTMRB2C0INT_Msk     (0x20UL)                  /*!< CTMRB2C0INT (Bitfield-Mask: 0x01)                     */
12244 #define CTIMER_INTCLR_CTMRA2C0INT_Pos     (4UL)                     /*!< CTMRA2C0INT (Bit 4)                                   */
12245 #define CTIMER_INTCLR_CTMRA2C0INT_Msk     (0x10UL)                  /*!< CTMRA2C0INT (Bitfield-Mask: 0x01)                     */
12246 #define CTIMER_INTCLR_CTMRB1C0INT_Pos     (3UL)                     /*!< CTMRB1C0INT (Bit 3)                                   */
12247 #define CTIMER_INTCLR_CTMRB1C0INT_Msk     (0x8UL)                   /*!< CTMRB1C0INT (Bitfield-Mask: 0x01)                     */
12248 #define CTIMER_INTCLR_CTMRA1C0INT_Pos     (2UL)                     /*!< CTMRA1C0INT (Bit 2)                                   */
12249 #define CTIMER_INTCLR_CTMRA1C0INT_Msk     (0x4UL)                   /*!< CTMRA1C0INT (Bitfield-Mask: 0x01)                     */
12250 #define CTIMER_INTCLR_CTMRB0C0INT_Pos     (1UL)                     /*!< CTMRB0C0INT (Bit 1)                                   */
12251 #define CTIMER_INTCLR_CTMRB0C0INT_Msk     (0x2UL)                   /*!< CTMRB0C0INT (Bitfield-Mask: 0x01)                     */
12252 #define CTIMER_INTCLR_CTMRA0C0INT_Pos     (0UL)                     /*!< CTMRA0C0INT (Bit 0)                                   */
12253 #define CTIMER_INTCLR_CTMRA0C0INT_Msk     (0x1UL)                   /*!< CTMRA0C0INT (Bitfield-Mask: 0x01)                     */
12254 /* ========================================================  INTSET  ========================================================= */
12255 #define CTIMER_INTSET_CTMRB7C1INT_Pos     (31UL)                    /*!< CTMRB7C1INT (Bit 31)                                  */
12256 #define CTIMER_INTSET_CTMRB7C1INT_Msk     (0x80000000UL)            /*!< CTMRB7C1INT (Bitfield-Mask: 0x01)                     */
12257 #define CTIMER_INTSET_CTMRA7C1INT_Pos     (30UL)                    /*!< CTMRA7C1INT (Bit 30)                                  */
12258 #define CTIMER_INTSET_CTMRA7C1INT_Msk     (0x40000000UL)            /*!< CTMRA7C1INT (Bitfield-Mask: 0x01)                     */
12259 #define CTIMER_INTSET_CTMRB6C1INT_Pos     (29UL)                    /*!< CTMRB6C1INT (Bit 29)                                  */
12260 #define CTIMER_INTSET_CTMRB6C1INT_Msk     (0x20000000UL)            /*!< CTMRB6C1INT (Bitfield-Mask: 0x01)                     */
12261 #define CTIMER_INTSET_CTMRA6C1INT_Pos     (28UL)                    /*!< CTMRA6C1INT (Bit 28)                                  */
12262 #define CTIMER_INTSET_CTMRA6C1INT_Msk     (0x10000000UL)            /*!< CTMRA6C1INT (Bitfield-Mask: 0x01)                     */
12263 #define CTIMER_INTSET_CTMRB5C1INT_Pos     (27UL)                    /*!< CTMRB5C1INT (Bit 27)                                  */
12264 #define CTIMER_INTSET_CTMRB5C1INT_Msk     (0x8000000UL)             /*!< CTMRB5C1INT (Bitfield-Mask: 0x01)                     */
12265 #define CTIMER_INTSET_CTMRA5C1INT_Pos     (26UL)                    /*!< CTMRA5C1INT (Bit 26)                                  */
12266 #define CTIMER_INTSET_CTMRA5C1INT_Msk     (0x4000000UL)             /*!< CTMRA5C1INT (Bitfield-Mask: 0x01)                     */
12267 #define CTIMER_INTSET_CTMRB4C1INT_Pos     (25UL)                    /*!< CTMRB4C1INT (Bit 25)                                  */
12268 #define CTIMER_INTSET_CTMRB4C1INT_Msk     (0x2000000UL)             /*!< CTMRB4C1INT (Bitfield-Mask: 0x01)                     */
12269 #define CTIMER_INTSET_CTMRA4C1INT_Pos     (24UL)                    /*!< CTMRA4C1INT (Bit 24)                                  */
12270 #define CTIMER_INTSET_CTMRA4C1INT_Msk     (0x1000000UL)             /*!< CTMRA4C1INT (Bitfield-Mask: 0x01)                     */
12271 #define CTIMER_INTSET_CTMRB3C1INT_Pos     (23UL)                    /*!< CTMRB3C1INT (Bit 23)                                  */
12272 #define CTIMER_INTSET_CTMRB3C1INT_Msk     (0x800000UL)              /*!< CTMRB3C1INT (Bitfield-Mask: 0x01)                     */
12273 #define CTIMER_INTSET_CTMRA3C1INT_Pos     (22UL)                    /*!< CTMRA3C1INT (Bit 22)                                  */
12274 #define CTIMER_INTSET_CTMRA3C1INT_Msk     (0x400000UL)              /*!< CTMRA3C1INT (Bitfield-Mask: 0x01)                     */
12275 #define CTIMER_INTSET_CTMRB2C1INT_Pos     (21UL)                    /*!< CTMRB2C1INT (Bit 21)                                  */
12276 #define CTIMER_INTSET_CTMRB2C1INT_Msk     (0x200000UL)              /*!< CTMRB2C1INT (Bitfield-Mask: 0x01)                     */
12277 #define CTIMER_INTSET_CTMRA2C1INT_Pos     (20UL)                    /*!< CTMRA2C1INT (Bit 20)                                  */
12278 #define CTIMER_INTSET_CTMRA2C1INT_Msk     (0x100000UL)              /*!< CTMRA2C1INT (Bitfield-Mask: 0x01)                     */
12279 #define CTIMER_INTSET_CTMRB1C1INT_Pos     (19UL)                    /*!< CTMRB1C1INT (Bit 19)                                  */
12280 #define CTIMER_INTSET_CTMRB1C1INT_Msk     (0x80000UL)               /*!< CTMRB1C1INT (Bitfield-Mask: 0x01)                     */
12281 #define CTIMER_INTSET_CTMRA1C1INT_Pos     (18UL)                    /*!< CTMRA1C1INT (Bit 18)                                  */
12282 #define CTIMER_INTSET_CTMRA1C1INT_Msk     (0x40000UL)               /*!< CTMRA1C1INT (Bitfield-Mask: 0x01)                     */
12283 #define CTIMER_INTSET_CTMRB0C1INT_Pos     (17UL)                    /*!< CTMRB0C1INT (Bit 17)                                  */
12284 #define CTIMER_INTSET_CTMRB0C1INT_Msk     (0x20000UL)               /*!< CTMRB0C1INT (Bitfield-Mask: 0x01)                     */
12285 #define CTIMER_INTSET_CTMRA0C1INT_Pos     (16UL)                    /*!< CTMRA0C1INT (Bit 16)                                  */
12286 #define CTIMER_INTSET_CTMRA0C1INT_Msk     (0x10000UL)               /*!< CTMRA0C1INT (Bitfield-Mask: 0x01)                     */
12287 #define CTIMER_INTSET_CTMRB7C0INT_Pos     (15UL)                    /*!< CTMRB7C0INT (Bit 15)                                  */
12288 #define CTIMER_INTSET_CTMRB7C0INT_Msk     (0x8000UL)                /*!< CTMRB7C0INT (Bitfield-Mask: 0x01)                     */
12289 #define CTIMER_INTSET_CTMRA7C0INT_Pos     (14UL)                    /*!< CTMRA7C0INT (Bit 14)                                  */
12290 #define CTIMER_INTSET_CTMRA7C0INT_Msk     (0x4000UL)                /*!< CTMRA7C0INT (Bitfield-Mask: 0x01)                     */
12291 #define CTIMER_INTSET_CTMRB6C0INT_Pos     (13UL)                    /*!< CTMRB6C0INT (Bit 13)                                  */
12292 #define CTIMER_INTSET_CTMRB6C0INT_Msk     (0x2000UL)                /*!< CTMRB6C0INT (Bitfield-Mask: 0x01)                     */
12293 #define CTIMER_INTSET_CTMRA6C0INT_Pos     (12UL)                    /*!< CTMRA6C0INT (Bit 12)                                  */
12294 #define CTIMER_INTSET_CTMRA6C0INT_Msk     (0x1000UL)                /*!< CTMRA6C0INT (Bitfield-Mask: 0x01)                     */
12295 #define CTIMER_INTSET_CTMRB5C0INT_Pos     (11UL)                    /*!< CTMRB5C0INT (Bit 11)                                  */
12296 #define CTIMER_INTSET_CTMRB5C0INT_Msk     (0x800UL)                 /*!< CTMRB5C0INT (Bitfield-Mask: 0x01)                     */
12297 #define CTIMER_INTSET_CTMRA5C0INT_Pos     (10UL)                    /*!< CTMRA5C0INT (Bit 10)                                  */
12298 #define CTIMER_INTSET_CTMRA5C0INT_Msk     (0x400UL)                 /*!< CTMRA5C0INT (Bitfield-Mask: 0x01)                     */
12299 #define CTIMER_INTSET_CTMRB4C0INT_Pos     (9UL)                     /*!< CTMRB4C0INT (Bit 9)                                   */
12300 #define CTIMER_INTSET_CTMRB4C0INT_Msk     (0x200UL)                 /*!< CTMRB4C0INT (Bitfield-Mask: 0x01)                     */
12301 #define CTIMER_INTSET_CTMRA4C0INT_Pos     (8UL)                     /*!< CTMRA4C0INT (Bit 8)                                   */
12302 #define CTIMER_INTSET_CTMRA4C0INT_Msk     (0x100UL)                 /*!< CTMRA4C0INT (Bitfield-Mask: 0x01)                     */
12303 #define CTIMER_INTSET_CTMRB3C0INT_Pos     (7UL)                     /*!< CTMRB3C0INT (Bit 7)                                   */
12304 #define CTIMER_INTSET_CTMRB3C0INT_Msk     (0x80UL)                  /*!< CTMRB3C0INT (Bitfield-Mask: 0x01)                     */
12305 #define CTIMER_INTSET_CTMRA3C0INT_Pos     (6UL)                     /*!< CTMRA3C0INT (Bit 6)                                   */
12306 #define CTIMER_INTSET_CTMRA3C0INT_Msk     (0x40UL)                  /*!< CTMRA3C0INT (Bitfield-Mask: 0x01)                     */
12307 #define CTIMER_INTSET_CTMRB2C0INT_Pos     (5UL)                     /*!< CTMRB2C0INT (Bit 5)                                   */
12308 #define CTIMER_INTSET_CTMRB2C0INT_Msk     (0x20UL)                  /*!< CTMRB2C0INT (Bitfield-Mask: 0x01)                     */
12309 #define CTIMER_INTSET_CTMRA2C0INT_Pos     (4UL)                     /*!< CTMRA2C0INT (Bit 4)                                   */
12310 #define CTIMER_INTSET_CTMRA2C0INT_Msk     (0x10UL)                  /*!< CTMRA2C0INT (Bitfield-Mask: 0x01)                     */
12311 #define CTIMER_INTSET_CTMRB1C0INT_Pos     (3UL)                     /*!< CTMRB1C0INT (Bit 3)                                   */
12312 #define CTIMER_INTSET_CTMRB1C0INT_Msk     (0x8UL)                   /*!< CTMRB1C0INT (Bitfield-Mask: 0x01)                     */
12313 #define CTIMER_INTSET_CTMRA1C0INT_Pos     (2UL)                     /*!< CTMRA1C0INT (Bit 2)                                   */
12314 #define CTIMER_INTSET_CTMRA1C0INT_Msk     (0x4UL)                   /*!< CTMRA1C0INT (Bitfield-Mask: 0x01)                     */
12315 #define CTIMER_INTSET_CTMRB0C0INT_Pos     (1UL)                     /*!< CTMRB0C0INT (Bit 1)                                   */
12316 #define CTIMER_INTSET_CTMRB0C0INT_Msk     (0x2UL)                   /*!< CTMRB0C0INT (Bitfield-Mask: 0x01)                     */
12317 #define CTIMER_INTSET_CTMRA0C0INT_Pos     (0UL)                     /*!< CTMRA0C0INT (Bit 0)                                   */
12318 #define CTIMER_INTSET_CTMRA0C0INT_Msk     (0x1UL)                   /*!< CTMRA0C0INT (Bitfield-Mask: 0x01)                     */
12319 /* =======================================================  STMINTEN  ======================================================== */
12320 #define CTIMER_STMINTEN_CAPTURED_Pos      (12UL)                    /*!< CAPTURED (Bit 12)                                     */
12321 #define CTIMER_STMINTEN_CAPTURED_Msk      (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
12322 #define CTIMER_STMINTEN_CAPTUREC_Pos      (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
12323 #define CTIMER_STMINTEN_CAPTUREC_Msk      (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
12324 #define CTIMER_STMINTEN_CAPTUREB_Pos      (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
12325 #define CTIMER_STMINTEN_CAPTUREB_Msk      (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
12326 #define CTIMER_STMINTEN_CAPTUREA_Pos      (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
12327 #define CTIMER_STMINTEN_CAPTUREA_Msk      (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
12328 #define CTIMER_STMINTEN_OVERFLOW_Pos      (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
12329 #define CTIMER_STMINTEN_OVERFLOW_Msk      (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
12330 #define CTIMER_STMINTEN_COMPAREH_Pos      (7UL)                     /*!< COMPAREH (Bit 7)                                      */
12331 #define CTIMER_STMINTEN_COMPAREH_Msk      (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
12332 #define CTIMER_STMINTEN_COMPAREG_Pos      (6UL)                     /*!< COMPAREG (Bit 6)                                      */
12333 #define CTIMER_STMINTEN_COMPAREG_Msk      (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
12334 #define CTIMER_STMINTEN_COMPAREF_Pos      (5UL)                     /*!< COMPAREF (Bit 5)                                      */
12335 #define CTIMER_STMINTEN_COMPAREF_Msk      (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
12336 #define CTIMER_STMINTEN_COMPAREE_Pos      (4UL)                     /*!< COMPAREE (Bit 4)                                      */
12337 #define CTIMER_STMINTEN_COMPAREE_Msk      (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
12338 #define CTIMER_STMINTEN_COMPARED_Pos      (3UL)                     /*!< COMPARED (Bit 3)                                      */
12339 #define CTIMER_STMINTEN_COMPARED_Msk      (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
12340 #define CTIMER_STMINTEN_COMPAREC_Pos      (2UL)                     /*!< COMPAREC (Bit 2)                                      */
12341 #define CTIMER_STMINTEN_COMPAREC_Msk      (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
12342 #define CTIMER_STMINTEN_COMPAREB_Pos      (1UL)                     /*!< COMPAREB (Bit 1)                                      */
12343 #define CTIMER_STMINTEN_COMPAREB_Msk      (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
12344 #define CTIMER_STMINTEN_COMPAREA_Pos      (0UL)                     /*!< COMPAREA (Bit 0)                                      */
12345 #define CTIMER_STMINTEN_COMPAREA_Msk      (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
12346 /* ======================================================  STMINTSTAT  ======================================================= */
12347 #define CTIMER_STMINTSTAT_CAPTURED_Pos    (12UL)                    /*!< CAPTURED (Bit 12)                                     */
12348 #define CTIMER_STMINTSTAT_CAPTURED_Msk    (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
12349 #define CTIMER_STMINTSTAT_CAPTUREC_Pos    (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
12350 #define CTIMER_STMINTSTAT_CAPTUREC_Msk    (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
12351 #define CTIMER_STMINTSTAT_CAPTUREB_Pos    (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
12352 #define CTIMER_STMINTSTAT_CAPTUREB_Msk    (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
12353 #define CTIMER_STMINTSTAT_CAPTUREA_Pos    (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
12354 #define CTIMER_STMINTSTAT_CAPTUREA_Msk    (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
12355 #define CTIMER_STMINTSTAT_OVERFLOW_Pos    (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
12356 #define CTIMER_STMINTSTAT_OVERFLOW_Msk    (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
12357 #define CTIMER_STMINTSTAT_COMPAREH_Pos    (7UL)                     /*!< COMPAREH (Bit 7)                                      */
12358 #define CTIMER_STMINTSTAT_COMPAREH_Msk    (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
12359 #define CTIMER_STMINTSTAT_COMPAREG_Pos    (6UL)                     /*!< COMPAREG (Bit 6)                                      */
12360 #define CTIMER_STMINTSTAT_COMPAREG_Msk    (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
12361 #define CTIMER_STMINTSTAT_COMPAREF_Pos    (5UL)                     /*!< COMPAREF (Bit 5)                                      */
12362 #define CTIMER_STMINTSTAT_COMPAREF_Msk    (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
12363 #define CTIMER_STMINTSTAT_COMPAREE_Pos    (4UL)                     /*!< COMPAREE (Bit 4)                                      */
12364 #define CTIMER_STMINTSTAT_COMPAREE_Msk    (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
12365 #define CTIMER_STMINTSTAT_COMPARED_Pos    (3UL)                     /*!< COMPARED (Bit 3)                                      */
12366 #define CTIMER_STMINTSTAT_COMPARED_Msk    (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
12367 #define CTIMER_STMINTSTAT_COMPAREC_Pos    (2UL)                     /*!< COMPAREC (Bit 2)                                      */
12368 #define CTIMER_STMINTSTAT_COMPAREC_Msk    (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
12369 #define CTIMER_STMINTSTAT_COMPAREB_Pos    (1UL)                     /*!< COMPAREB (Bit 1)                                      */
12370 #define CTIMER_STMINTSTAT_COMPAREB_Msk    (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
12371 #define CTIMER_STMINTSTAT_COMPAREA_Pos    (0UL)                     /*!< COMPAREA (Bit 0)                                      */
12372 #define CTIMER_STMINTSTAT_COMPAREA_Msk    (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
12373 /* =======================================================  STMINTCLR  ======================================================= */
12374 #define CTIMER_STMINTCLR_CAPTURED_Pos     (12UL)                    /*!< CAPTURED (Bit 12)                                     */
12375 #define CTIMER_STMINTCLR_CAPTURED_Msk     (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
12376 #define CTIMER_STMINTCLR_CAPTUREC_Pos     (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
12377 #define CTIMER_STMINTCLR_CAPTUREC_Msk     (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
12378 #define CTIMER_STMINTCLR_CAPTUREB_Pos     (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
12379 #define CTIMER_STMINTCLR_CAPTUREB_Msk     (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
12380 #define CTIMER_STMINTCLR_CAPTUREA_Pos     (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
12381 #define CTIMER_STMINTCLR_CAPTUREA_Msk     (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
12382 #define CTIMER_STMINTCLR_OVERFLOW_Pos     (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
12383 #define CTIMER_STMINTCLR_OVERFLOW_Msk     (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
12384 #define CTIMER_STMINTCLR_COMPAREH_Pos     (7UL)                     /*!< COMPAREH (Bit 7)                                      */
12385 #define CTIMER_STMINTCLR_COMPAREH_Msk     (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
12386 #define CTIMER_STMINTCLR_COMPAREG_Pos     (6UL)                     /*!< COMPAREG (Bit 6)                                      */
12387 #define CTIMER_STMINTCLR_COMPAREG_Msk     (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
12388 #define CTIMER_STMINTCLR_COMPAREF_Pos     (5UL)                     /*!< COMPAREF (Bit 5)                                      */
12389 #define CTIMER_STMINTCLR_COMPAREF_Msk     (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
12390 #define CTIMER_STMINTCLR_COMPAREE_Pos     (4UL)                     /*!< COMPAREE (Bit 4)                                      */
12391 #define CTIMER_STMINTCLR_COMPAREE_Msk     (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
12392 #define CTIMER_STMINTCLR_COMPARED_Pos     (3UL)                     /*!< COMPARED (Bit 3)                                      */
12393 #define CTIMER_STMINTCLR_COMPARED_Msk     (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
12394 #define CTIMER_STMINTCLR_COMPAREC_Pos     (2UL)                     /*!< COMPAREC (Bit 2)                                      */
12395 #define CTIMER_STMINTCLR_COMPAREC_Msk     (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
12396 #define CTIMER_STMINTCLR_COMPAREB_Pos     (1UL)                     /*!< COMPAREB (Bit 1)                                      */
12397 #define CTIMER_STMINTCLR_COMPAREB_Msk     (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
12398 #define CTIMER_STMINTCLR_COMPAREA_Pos     (0UL)                     /*!< COMPAREA (Bit 0)                                      */
12399 #define CTIMER_STMINTCLR_COMPAREA_Msk     (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
12400 /* =======================================================  STMINTSET  ======================================================= */
12401 #define CTIMER_STMINTSET_CAPTURED_Pos     (12UL)                    /*!< CAPTURED (Bit 12)                                     */
12402 #define CTIMER_STMINTSET_CAPTURED_Msk     (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
12403 #define CTIMER_STMINTSET_CAPTUREC_Pos     (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
12404 #define CTIMER_STMINTSET_CAPTUREC_Msk     (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
12405 #define CTIMER_STMINTSET_CAPTUREB_Pos     (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
12406 #define CTIMER_STMINTSET_CAPTUREB_Msk     (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
12407 #define CTIMER_STMINTSET_CAPTUREA_Pos     (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
12408 #define CTIMER_STMINTSET_CAPTUREA_Msk     (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
12409 #define CTIMER_STMINTSET_OVERFLOW_Pos     (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
12410 #define CTIMER_STMINTSET_OVERFLOW_Msk     (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
12411 #define CTIMER_STMINTSET_COMPAREH_Pos     (7UL)                     /*!< COMPAREH (Bit 7)                                      */
12412 #define CTIMER_STMINTSET_COMPAREH_Msk     (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
12413 #define CTIMER_STMINTSET_COMPAREG_Pos     (6UL)                     /*!< COMPAREG (Bit 6)                                      */
12414 #define CTIMER_STMINTSET_COMPAREG_Msk     (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
12415 #define CTIMER_STMINTSET_COMPAREF_Pos     (5UL)                     /*!< COMPAREF (Bit 5)                                      */
12416 #define CTIMER_STMINTSET_COMPAREF_Msk     (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
12417 #define CTIMER_STMINTSET_COMPAREE_Pos     (4UL)                     /*!< COMPAREE (Bit 4)                                      */
12418 #define CTIMER_STMINTSET_COMPAREE_Msk     (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
12419 #define CTIMER_STMINTSET_COMPARED_Pos     (3UL)                     /*!< COMPARED (Bit 3)                                      */
12420 #define CTIMER_STMINTSET_COMPARED_Msk     (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
12421 #define CTIMER_STMINTSET_COMPAREC_Pos     (2UL)                     /*!< COMPAREC (Bit 2)                                      */
12422 #define CTIMER_STMINTSET_COMPAREC_Msk     (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
12423 #define CTIMER_STMINTSET_COMPAREB_Pos     (1UL)                     /*!< COMPAREB (Bit 1)                                      */
12424 #define CTIMER_STMINTSET_COMPAREB_Msk     (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
12425 #define CTIMER_STMINTSET_COMPAREA_Pos     (0UL)                     /*!< COMPAREA (Bit 0)                                      */
12426 #define CTIMER_STMINTSET_COMPAREA_Msk     (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
12427 
12428 
12429 /* =========================================================================================================================== */
12430 /* ================                                           GPIO                                            ================ */
12431 /* =========================================================================================================================== */
12432 
12433 /* ========================================================  PADREGA  ======================================================== */
12434 #define GPIO_PADREGA_PAD3PWRUP_Pos        (30UL)                    /*!< PAD3PWRUP (Bit 30)                                    */
12435 #define GPIO_PADREGA_PAD3PWRUP_Msk        (0x40000000UL)            /*!< PAD3PWRUP (Bitfield-Mask: 0x01)                       */
12436 #define GPIO_PADREGA_PAD3FNCSEL_Pos       (27UL)                    /*!< PAD3FNCSEL (Bit 27)                                   */
12437 #define GPIO_PADREGA_PAD3FNCSEL_Msk       (0x38000000UL)            /*!< PAD3FNCSEL (Bitfield-Mask: 0x07)                      */
12438 #define GPIO_PADREGA_PAD3STRNG_Pos        (26UL)                    /*!< PAD3STRNG (Bit 26)                                    */
12439 #define GPIO_PADREGA_PAD3STRNG_Msk        (0x4000000UL)             /*!< PAD3STRNG (Bitfield-Mask: 0x01)                       */
12440 #define GPIO_PADREGA_PAD3INPEN_Pos        (25UL)                    /*!< PAD3INPEN (Bit 25)                                    */
12441 #define GPIO_PADREGA_PAD3INPEN_Msk        (0x2000000UL)             /*!< PAD3INPEN (Bitfield-Mask: 0x01)                       */
12442 #define GPIO_PADREGA_PAD3PULL_Pos         (24UL)                    /*!< PAD3PULL (Bit 24)                                     */
12443 #define GPIO_PADREGA_PAD3PULL_Msk         (0x1000000UL)             /*!< PAD3PULL (Bitfield-Mask: 0x01)                        */
12444 #define GPIO_PADREGA_PAD2FNCSEL_Pos       (19UL)                    /*!< PAD2FNCSEL (Bit 19)                                   */
12445 #define GPIO_PADREGA_PAD2FNCSEL_Msk       (0x380000UL)              /*!< PAD2FNCSEL (Bitfield-Mask: 0x07)                      */
12446 #define GPIO_PADREGA_PAD2STRNG_Pos        (18UL)                    /*!< PAD2STRNG (Bit 18)                                    */
12447 #define GPIO_PADREGA_PAD2STRNG_Msk        (0x40000UL)               /*!< PAD2STRNG (Bitfield-Mask: 0x01)                       */
12448 #define GPIO_PADREGA_PAD2INPEN_Pos        (17UL)                    /*!< PAD2INPEN (Bit 17)                                    */
12449 #define GPIO_PADREGA_PAD2INPEN_Msk        (0x20000UL)               /*!< PAD2INPEN (Bitfield-Mask: 0x01)                       */
12450 #define GPIO_PADREGA_PAD2PULL_Pos         (16UL)                    /*!< PAD2PULL (Bit 16)                                     */
12451 #define GPIO_PADREGA_PAD2PULL_Msk         (0x10000UL)               /*!< PAD2PULL (Bitfield-Mask: 0x01)                        */
12452 #define GPIO_PADREGA_PAD1RSEL_Pos         (14UL)                    /*!< PAD1RSEL (Bit 14)                                     */
12453 #define GPIO_PADREGA_PAD1RSEL_Msk         (0xc000UL)                /*!< PAD1RSEL (Bitfield-Mask: 0x03)                        */
12454 #define GPIO_PADREGA_PAD1FNCSEL_Pos       (11UL)                    /*!< PAD1FNCSEL (Bit 11)                                   */
12455 #define GPIO_PADREGA_PAD1FNCSEL_Msk       (0x3800UL)                /*!< PAD1FNCSEL (Bitfield-Mask: 0x07)                      */
12456 #define GPIO_PADREGA_PAD1STRNG_Pos        (10UL)                    /*!< PAD1STRNG (Bit 10)                                    */
12457 #define GPIO_PADREGA_PAD1STRNG_Msk        (0x400UL)                 /*!< PAD1STRNG (Bitfield-Mask: 0x01)                       */
12458 #define GPIO_PADREGA_PAD1INPEN_Pos        (9UL)                     /*!< PAD1INPEN (Bit 9)                                     */
12459 #define GPIO_PADREGA_PAD1INPEN_Msk        (0x200UL)                 /*!< PAD1INPEN (Bitfield-Mask: 0x01)                       */
12460 #define GPIO_PADREGA_PAD1PULL_Pos         (8UL)                     /*!< PAD1PULL (Bit 8)                                      */
12461 #define GPIO_PADREGA_PAD1PULL_Msk         (0x100UL)                 /*!< PAD1PULL (Bitfield-Mask: 0x01)                        */
12462 #define GPIO_PADREGA_PAD0RSEL_Pos         (6UL)                     /*!< PAD0RSEL (Bit 6)                                      */
12463 #define GPIO_PADREGA_PAD0RSEL_Msk         (0xc0UL)                  /*!< PAD0RSEL (Bitfield-Mask: 0x03)                        */
12464 #define GPIO_PADREGA_PAD0FNCSEL_Pos       (3UL)                     /*!< PAD0FNCSEL (Bit 3)                                    */
12465 #define GPIO_PADREGA_PAD0FNCSEL_Msk       (0x38UL)                  /*!< PAD0FNCSEL (Bitfield-Mask: 0x07)                      */
12466 #define GPIO_PADREGA_PAD0STRNG_Pos        (2UL)                     /*!< PAD0STRNG (Bit 2)                                     */
12467 #define GPIO_PADREGA_PAD0STRNG_Msk        (0x4UL)                   /*!< PAD0STRNG (Bitfield-Mask: 0x01)                       */
12468 #define GPIO_PADREGA_PAD0INPEN_Pos        (1UL)                     /*!< PAD0INPEN (Bit 1)                                     */
12469 #define GPIO_PADREGA_PAD0INPEN_Msk        (0x2UL)                   /*!< PAD0INPEN (Bitfield-Mask: 0x01)                       */
12470 #define GPIO_PADREGA_PAD0PULL_Pos         (0UL)                     /*!< PAD0PULL (Bit 0)                                      */
12471 #define GPIO_PADREGA_PAD0PULL_Msk         (0x1UL)                   /*!< PAD0PULL (Bitfield-Mask: 0x01)                        */
12472 /* ========================================================  PADREGB  ======================================================== */
12473 #define GPIO_PADREGB_PAD7FNCSEL_Pos       (27UL)                    /*!< PAD7FNCSEL (Bit 27)                                   */
12474 #define GPIO_PADREGB_PAD7FNCSEL_Msk       (0x38000000UL)            /*!< PAD7FNCSEL (Bitfield-Mask: 0x07)                      */
12475 #define GPIO_PADREGB_PAD7STRNG_Pos        (26UL)                    /*!< PAD7STRNG (Bit 26)                                    */
12476 #define GPIO_PADREGB_PAD7STRNG_Msk        (0x4000000UL)             /*!< PAD7STRNG (Bitfield-Mask: 0x01)                       */
12477 #define GPIO_PADREGB_PAD7INPEN_Pos        (25UL)                    /*!< PAD7INPEN (Bit 25)                                    */
12478 #define GPIO_PADREGB_PAD7INPEN_Msk        (0x2000000UL)             /*!< PAD7INPEN (Bitfield-Mask: 0x01)                       */
12479 #define GPIO_PADREGB_PAD7PULL_Pos         (24UL)                    /*!< PAD7PULL (Bit 24)                                     */
12480 #define GPIO_PADREGB_PAD7PULL_Msk         (0x1000000UL)             /*!< PAD7PULL (Bitfield-Mask: 0x01)                        */
12481 #define GPIO_PADREGB_PAD6RSEL_Pos         (22UL)                    /*!< PAD6RSEL (Bit 22)                                     */
12482 #define GPIO_PADREGB_PAD6RSEL_Msk         (0xc00000UL)              /*!< PAD6RSEL (Bitfield-Mask: 0x03)                        */
12483 #define GPIO_PADREGB_PAD6FNCSEL_Pos       (19UL)                    /*!< PAD6FNCSEL (Bit 19)                                   */
12484 #define GPIO_PADREGB_PAD6FNCSEL_Msk       (0x380000UL)              /*!< PAD6FNCSEL (Bitfield-Mask: 0x07)                      */
12485 #define GPIO_PADREGB_PAD6STRNG_Pos        (18UL)                    /*!< PAD6STRNG (Bit 18)                                    */
12486 #define GPIO_PADREGB_PAD6STRNG_Msk        (0x40000UL)               /*!< PAD6STRNG (Bitfield-Mask: 0x01)                       */
12487 #define GPIO_PADREGB_PAD6INPEN_Pos        (17UL)                    /*!< PAD6INPEN (Bit 17)                                    */
12488 #define GPIO_PADREGB_PAD6INPEN_Msk        (0x20000UL)               /*!< PAD6INPEN (Bitfield-Mask: 0x01)                       */
12489 #define GPIO_PADREGB_PAD6PULL_Pos         (16UL)                    /*!< PAD6PULL (Bit 16)                                     */
12490 #define GPIO_PADREGB_PAD6PULL_Msk         (0x10000UL)               /*!< PAD6PULL (Bitfield-Mask: 0x01)                        */
12491 #define GPIO_PADREGB_PAD5RSEL_Pos         (14UL)                    /*!< PAD5RSEL (Bit 14)                                     */
12492 #define GPIO_PADREGB_PAD5RSEL_Msk         (0xc000UL)                /*!< PAD5RSEL (Bitfield-Mask: 0x03)                        */
12493 #define GPIO_PADREGB_PAD5FNCSEL_Pos       (11UL)                    /*!< PAD5FNCSEL (Bit 11)                                   */
12494 #define GPIO_PADREGB_PAD5FNCSEL_Msk       (0x3800UL)                /*!< PAD5FNCSEL (Bitfield-Mask: 0x07)                      */
12495 #define GPIO_PADREGB_PAD5STRNG_Pos        (10UL)                    /*!< PAD5STRNG (Bit 10)                                    */
12496 #define GPIO_PADREGB_PAD5STRNG_Msk        (0x400UL)                 /*!< PAD5STRNG (Bitfield-Mask: 0x01)                       */
12497 #define GPIO_PADREGB_PAD5INPEN_Pos        (9UL)                     /*!< PAD5INPEN (Bit 9)                                     */
12498 #define GPIO_PADREGB_PAD5INPEN_Msk        (0x200UL)                 /*!< PAD5INPEN (Bitfield-Mask: 0x01)                       */
12499 #define GPIO_PADREGB_PAD5PULL_Pos         (8UL)                     /*!< PAD5PULL (Bit 8)                                      */
12500 #define GPIO_PADREGB_PAD5PULL_Msk         (0x100UL)                 /*!< PAD5PULL (Bitfield-Mask: 0x01)                        */
12501 #define GPIO_PADREGB_PAD4FNCSEL_Pos       (3UL)                     /*!< PAD4FNCSEL (Bit 3)                                    */
12502 #define GPIO_PADREGB_PAD4FNCSEL_Msk       (0x38UL)                  /*!< PAD4FNCSEL (Bitfield-Mask: 0x07)                      */
12503 #define GPIO_PADREGB_PAD4STRNG_Pos        (2UL)                     /*!< PAD4STRNG (Bit 2)                                     */
12504 #define GPIO_PADREGB_PAD4STRNG_Msk        (0x4UL)                   /*!< PAD4STRNG (Bitfield-Mask: 0x01)                       */
12505 #define GPIO_PADREGB_PAD4INPEN_Pos        (1UL)                     /*!< PAD4INPEN (Bit 1)                                     */
12506 #define GPIO_PADREGB_PAD4INPEN_Msk        (0x2UL)                   /*!< PAD4INPEN (Bitfield-Mask: 0x01)                       */
12507 #define GPIO_PADREGB_PAD4PULL_Pos         (0UL)                     /*!< PAD4PULL (Bit 0)                                      */
12508 #define GPIO_PADREGB_PAD4PULL_Msk         (0x1UL)                   /*!< PAD4PULL (Bitfield-Mask: 0x01)                        */
12509 /* ========================================================  PADREGC  ======================================================== */
12510 #define GPIO_PADREGC_PAD11FNCSEL_Pos      (27UL)                    /*!< PAD11FNCSEL (Bit 27)                                  */
12511 #define GPIO_PADREGC_PAD11FNCSEL_Msk      (0x38000000UL)            /*!< PAD11FNCSEL (Bitfield-Mask: 0x07)                     */
12512 #define GPIO_PADREGC_PAD11STRNG_Pos       (26UL)                    /*!< PAD11STRNG (Bit 26)                                   */
12513 #define GPIO_PADREGC_PAD11STRNG_Msk       (0x4000000UL)             /*!< PAD11STRNG (Bitfield-Mask: 0x01)                      */
12514 #define GPIO_PADREGC_PAD11INPEN_Pos       (25UL)                    /*!< PAD11INPEN (Bit 25)                                   */
12515 #define GPIO_PADREGC_PAD11INPEN_Msk       (0x2000000UL)             /*!< PAD11INPEN (Bitfield-Mask: 0x01)                      */
12516 #define GPIO_PADREGC_PAD11PULL_Pos        (24UL)                    /*!< PAD11PULL (Bit 24)                                    */
12517 #define GPIO_PADREGC_PAD11PULL_Msk        (0x1000000UL)             /*!< PAD11PULL (Bitfield-Mask: 0x01)                       */
12518 #define GPIO_PADREGC_PAD10FNCSEL_Pos      (19UL)                    /*!< PAD10FNCSEL (Bit 19)                                  */
12519 #define GPIO_PADREGC_PAD10FNCSEL_Msk      (0x380000UL)              /*!< PAD10FNCSEL (Bitfield-Mask: 0x07)                     */
12520 #define GPIO_PADREGC_PAD10STRNG_Pos       (18UL)                    /*!< PAD10STRNG (Bit 18)                                   */
12521 #define GPIO_PADREGC_PAD10STRNG_Msk       (0x40000UL)               /*!< PAD10STRNG (Bitfield-Mask: 0x01)                      */
12522 #define GPIO_PADREGC_PAD10INPEN_Pos       (17UL)                    /*!< PAD10INPEN (Bit 17)                                   */
12523 #define GPIO_PADREGC_PAD10INPEN_Msk       (0x20000UL)               /*!< PAD10INPEN (Bitfield-Mask: 0x01)                      */
12524 #define GPIO_PADREGC_PAD10PULL_Pos        (16UL)                    /*!< PAD10PULL (Bit 16)                                    */
12525 #define GPIO_PADREGC_PAD10PULL_Msk        (0x10000UL)               /*!< PAD10PULL (Bitfield-Mask: 0x01)                       */
12526 #define GPIO_PADREGC_PAD9RSEL_Pos         (14UL)                    /*!< PAD9RSEL (Bit 14)                                     */
12527 #define GPIO_PADREGC_PAD9RSEL_Msk         (0xc000UL)                /*!< PAD9RSEL (Bitfield-Mask: 0x03)                        */
12528 #define GPIO_PADREGC_PAD9FNCSEL_Pos       (11UL)                    /*!< PAD9FNCSEL (Bit 11)                                   */
12529 #define GPIO_PADREGC_PAD9FNCSEL_Msk       (0x3800UL)                /*!< PAD9FNCSEL (Bitfield-Mask: 0x07)                      */
12530 #define GPIO_PADREGC_PAD9STRNG_Pos        (10UL)                    /*!< PAD9STRNG (Bit 10)                                    */
12531 #define GPIO_PADREGC_PAD9STRNG_Msk        (0x400UL)                 /*!< PAD9STRNG (Bitfield-Mask: 0x01)                       */
12532 #define GPIO_PADREGC_PAD9INPEN_Pos        (9UL)                     /*!< PAD9INPEN (Bit 9)                                     */
12533 #define GPIO_PADREGC_PAD9INPEN_Msk        (0x200UL)                 /*!< PAD9INPEN (Bitfield-Mask: 0x01)                       */
12534 #define GPIO_PADREGC_PAD9PULL_Pos         (8UL)                     /*!< PAD9PULL (Bit 8)                                      */
12535 #define GPIO_PADREGC_PAD9PULL_Msk         (0x100UL)                 /*!< PAD9PULL (Bitfield-Mask: 0x01)                        */
12536 #define GPIO_PADREGC_PAD8RSEL_Pos         (6UL)                     /*!< PAD8RSEL (Bit 6)                                      */
12537 #define GPIO_PADREGC_PAD8RSEL_Msk         (0xc0UL)                  /*!< PAD8RSEL (Bitfield-Mask: 0x03)                        */
12538 #define GPIO_PADREGC_PAD8FNCSEL_Pos       (3UL)                     /*!< PAD8FNCSEL (Bit 3)                                    */
12539 #define GPIO_PADREGC_PAD8FNCSEL_Msk       (0x38UL)                  /*!< PAD8FNCSEL (Bitfield-Mask: 0x07)                      */
12540 #define GPIO_PADREGC_PAD8STRNG_Pos        (2UL)                     /*!< PAD8STRNG (Bit 2)                                     */
12541 #define GPIO_PADREGC_PAD8STRNG_Msk        (0x4UL)                   /*!< PAD8STRNG (Bitfield-Mask: 0x01)                       */
12542 #define GPIO_PADREGC_PAD8INPEN_Pos        (1UL)                     /*!< PAD8INPEN (Bit 1)                                     */
12543 #define GPIO_PADREGC_PAD8INPEN_Msk        (0x2UL)                   /*!< PAD8INPEN (Bitfield-Mask: 0x01)                       */
12544 #define GPIO_PADREGC_PAD8PULL_Pos         (0UL)                     /*!< PAD8PULL (Bit 0)                                      */
12545 #define GPIO_PADREGC_PAD8PULL_Msk         (0x1UL)                   /*!< PAD8PULL (Bitfield-Mask: 0x01)                        */
12546 /* ========================================================  PADREGD  ======================================================== */
12547 #define GPIO_PADREGD_PAD15FNCSEL_Pos      (27UL)                    /*!< PAD15FNCSEL (Bit 27)                                  */
12548 #define GPIO_PADREGD_PAD15FNCSEL_Msk      (0x38000000UL)            /*!< PAD15FNCSEL (Bitfield-Mask: 0x07)                     */
12549 #define GPIO_PADREGD_PAD15STRNG_Pos       (26UL)                    /*!< PAD15STRNG (Bit 26)                                   */
12550 #define GPIO_PADREGD_PAD15STRNG_Msk       (0x4000000UL)             /*!< PAD15STRNG (Bitfield-Mask: 0x01)                      */
12551 #define GPIO_PADREGD_PAD15INPEN_Pos       (25UL)                    /*!< PAD15INPEN (Bit 25)                                   */
12552 #define GPIO_PADREGD_PAD15INPEN_Msk       (0x2000000UL)             /*!< PAD15INPEN (Bitfield-Mask: 0x01)                      */
12553 #define GPIO_PADREGD_PAD15PULL_Pos        (24UL)                    /*!< PAD15PULL (Bit 24)                                    */
12554 #define GPIO_PADREGD_PAD15PULL_Msk        (0x1000000UL)             /*!< PAD15PULL (Bitfield-Mask: 0x01)                       */
12555 #define GPIO_PADREGD_PAD14FNCSEL_Pos      (19UL)                    /*!< PAD14FNCSEL (Bit 19)                                  */
12556 #define GPIO_PADREGD_PAD14FNCSEL_Msk      (0x380000UL)              /*!< PAD14FNCSEL (Bitfield-Mask: 0x07)                     */
12557 #define GPIO_PADREGD_PAD14STRNG_Pos       (18UL)                    /*!< PAD14STRNG (Bit 18)                                   */
12558 #define GPIO_PADREGD_PAD14STRNG_Msk       (0x40000UL)               /*!< PAD14STRNG (Bitfield-Mask: 0x01)                      */
12559 #define GPIO_PADREGD_PAD14INPEN_Pos       (17UL)                    /*!< PAD14INPEN (Bit 17)                                   */
12560 #define GPIO_PADREGD_PAD14INPEN_Msk       (0x20000UL)               /*!< PAD14INPEN (Bitfield-Mask: 0x01)                      */
12561 #define GPIO_PADREGD_PAD14PULL_Pos        (16UL)                    /*!< PAD14PULL (Bit 16)                                    */
12562 #define GPIO_PADREGD_PAD14PULL_Msk        (0x10000UL)               /*!< PAD14PULL (Bitfield-Mask: 0x01)                       */
12563 #define GPIO_PADREGD_PAD13FNCSEL_Pos      (11UL)                    /*!< PAD13FNCSEL (Bit 11)                                  */
12564 #define GPIO_PADREGD_PAD13FNCSEL_Msk      (0x3800UL)                /*!< PAD13FNCSEL (Bitfield-Mask: 0x07)                     */
12565 #define GPIO_PADREGD_PAD13STRNG_Pos       (10UL)                    /*!< PAD13STRNG (Bit 10)                                   */
12566 #define GPIO_PADREGD_PAD13STRNG_Msk       (0x400UL)                 /*!< PAD13STRNG (Bitfield-Mask: 0x01)                      */
12567 #define GPIO_PADREGD_PAD13INPEN_Pos       (9UL)                     /*!< PAD13INPEN (Bit 9)                                    */
12568 #define GPIO_PADREGD_PAD13INPEN_Msk       (0x200UL)                 /*!< PAD13INPEN (Bitfield-Mask: 0x01)                      */
12569 #define GPIO_PADREGD_PAD13PULL_Pos        (8UL)                     /*!< PAD13PULL (Bit 8)                                     */
12570 #define GPIO_PADREGD_PAD13PULL_Msk        (0x100UL)                 /*!< PAD13PULL (Bitfield-Mask: 0x01)                       */
12571 #define GPIO_PADREGD_PAD12FNCSEL_Pos      (3UL)                     /*!< PAD12FNCSEL (Bit 3)                                   */
12572 #define GPIO_PADREGD_PAD12FNCSEL_Msk      (0x38UL)                  /*!< PAD12FNCSEL (Bitfield-Mask: 0x07)                     */
12573 #define GPIO_PADREGD_PAD12STRNG_Pos       (2UL)                     /*!< PAD12STRNG (Bit 2)                                    */
12574 #define GPIO_PADREGD_PAD12STRNG_Msk       (0x4UL)                   /*!< PAD12STRNG (Bitfield-Mask: 0x01)                      */
12575 #define GPIO_PADREGD_PAD12INPEN_Pos       (1UL)                     /*!< PAD12INPEN (Bit 1)                                    */
12576 #define GPIO_PADREGD_PAD12INPEN_Msk       (0x2UL)                   /*!< PAD12INPEN (Bitfield-Mask: 0x01)                      */
12577 #define GPIO_PADREGD_PAD12PULL_Pos        (0UL)                     /*!< PAD12PULL (Bit 0)                                     */
12578 #define GPIO_PADREGD_PAD12PULL_Msk        (0x1UL)                   /*!< PAD12PULL (Bitfield-Mask: 0x01)                       */
12579 /* ========================================================  PADREGE  ======================================================== */
12580 #define GPIO_PADREGE_PAD19FNCSEL_Pos      (27UL)                    /*!< PAD19FNCSEL (Bit 27)                                  */
12581 #define GPIO_PADREGE_PAD19FNCSEL_Msk      (0x38000000UL)            /*!< PAD19FNCSEL (Bitfield-Mask: 0x07)                     */
12582 #define GPIO_PADREGE_PAD19STRNG_Pos       (26UL)                    /*!< PAD19STRNG (Bit 26)                                   */
12583 #define GPIO_PADREGE_PAD19STRNG_Msk       (0x4000000UL)             /*!< PAD19STRNG (Bitfield-Mask: 0x01)                      */
12584 #define GPIO_PADREGE_PAD19INPEN_Pos       (25UL)                    /*!< PAD19INPEN (Bit 25)                                   */
12585 #define GPIO_PADREGE_PAD19INPEN_Msk       (0x2000000UL)             /*!< PAD19INPEN (Bitfield-Mask: 0x01)                      */
12586 #define GPIO_PADREGE_PAD19PULL_Pos        (24UL)                    /*!< PAD19PULL (Bit 24)                                    */
12587 #define GPIO_PADREGE_PAD19PULL_Msk        (0x1000000UL)             /*!< PAD19PULL (Bitfield-Mask: 0x01)                       */
12588 #define GPIO_PADREGE_PAD18FNCSEL_Pos      (19UL)                    /*!< PAD18FNCSEL (Bit 19)                                  */
12589 #define GPIO_PADREGE_PAD18FNCSEL_Msk      (0x380000UL)              /*!< PAD18FNCSEL (Bitfield-Mask: 0x07)                     */
12590 #define GPIO_PADREGE_PAD18STRNG_Pos       (18UL)                    /*!< PAD18STRNG (Bit 18)                                   */
12591 #define GPIO_PADREGE_PAD18STRNG_Msk       (0x40000UL)               /*!< PAD18STRNG (Bitfield-Mask: 0x01)                      */
12592 #define GPIO_PADREGE_PAD18INPEN_Pos       (17UL)                    /*!< PAD18INPEN (Bit 17)                                   */
12593 #define GPIO_PADREGE_PAD18INPEN_Msk       (0x20000UL)               /*!< PAD18INPEN (Bitfield-Mask: 0x01)                      */
12594 #define GPIO_PADREGE_PAD18PULL_Pos        (16UL)                    /*!< PAD18PULL (Bit 16)                                    */
12595 #define GPIO_PADREGE_PAD18PULL_Msk        (0x10000UL)               /*!< PAD18PULL (Bitfield-Mask: 0x01)                       */
12596 #define GPIO_PADREGE_PAD17FNCSEL_Pos      (11UL)                    /*!< PAD17FNCSEL (Bit 11)                                  */
12597 #define GPIO_PADREGE_PAD17FNCSEL_Msk      (0x3800UL)                /*!< PAD17FNCSEL (Bitfield-Mask: 0x07)                     */
12598 #define GPIO_PADREGE_PAD17STRNG_Pos       (10UL)                    /*!< PAD17STRNG (Bit 10)                                   */
12599 #define GPIO_PADREGE_PAD17STRNG_Msk       (0x400UL)                 /*!< PAD17STRNG (Bitfield-Mask: 0x01)                      */
12600 #define GPIO_PADREGE_PAD17INPEN_Pos       (9UL)                     /*!< PAD17INPEN (Bit 9)                                    */
12601 #define GPIO_PADREGE_PAD17INPEN_Msk       (0x200UL)                 /*!< PAD17INPEN (Bitfield-Mask: 0x01)                      */
12602 #define GPIO_PADREGE_PAD17PULL_Pos        (8UL)                     /*!< PAD17PULL (Bit 8)                                     */
12603 #define GPIO_PADREGE_PAD17PULL_Msk        (0x100UL)                 /*!< PAD17PULL (Bitfield-Mask: 0x01)                       */
12604 #define GPIO_PADREGE_PAD16FNCSEL_Pos      (3UL)                     /*!< PAD16FNCSEL (Bit 3)                                   */
12605 #define GPIO_PADREGE_PAD16FNCSEL_Msk      (0x38UL)                  /*!< PAD16FNCSEL (Bitfield-Mask: 0x07)                     */
12606 #define GPIO_PADREGE_PAD16STRNG_Pos       (2UL)                     /*!< PAD16STRNG (Bit 2)                                    */
12607 #define GPIO_PADREGE_PAD16STRNG_Msk       (0x4UL)                   /*!< PAD16STRNG (Bitfield-Mask: 0x01)                      */
12608 #define GPIO_PADREGE_PAD16INPEN_Pos       (1UL)                     /*!< PAD16INPEN (Bit 1)                                    */
12609 #define GPIO_PADREGE_PAD16INPEN_Msk       (0x2UL)                   /*!< PAD16INPEN (Bitfield-Mask: 0x01)                      */
12610 #define GPIO_PADREGE_PAD16PULL_Pos        (0UL)                     /*!< PAD16PULL (Bit 0)                                     */
12611 #define GPIO_PADREGE_PAD16PULL_Msk        (0x1UL)                   /*!< PAD16PULL (Bitfield-Mask: 0x01)                       */
12612 /* ========================================================  PADREGF  ======================================================== */
12613 #define GPIO_PADREGF_PAD23FNCSEL_Pos      (27UL)                    /*!< PAD23FNCSEL (Bit 27)                                  */
12614 #define GPIO_PADREGF_PAD23FNCSEL_Msk      (0x38000000UL)            /*!< PAD23FNCSEL (Bitfield-Mask: 0x07)                     */
12615 #define GPIO_PADREGF_PAD23STRNG_Pos       (26UL)                    /*!< PAD23STRNG (Bit 26)                                   */
12616 #define GPIO_PADREGF_PAD23STRNG_Msk       (0x4000000UL)             /*!< PAD23STRNG (Bitfield-Mask: 0x01)                      */
12617 #define GPIO_PADREGF_PAD23INPEN_Pos       (25UL)                    /*!< PAD23INPEN (Bit 25)                                   */
12618 #define GPIO_PADREGF_PAD23INPEN_Msk       (0x2000000UL)             /*!< PAD23INPEN (Bitfield-Mask: 0x01)                      */
12619 #define GPIO_PADREGF_PAD23PULL_Pos        (24UL)                    /*!< PAD23PULL (Bit 24)                                    */
12620 #define GPIO_PADREGF_PAD23PULL_Msk        (0x1000000UL)             /*!< PAD23PULL (Bitfield-Mask: 0x01)                       */
12621 #define GPIO_PADREGF_PAD22FNCSEL_Pos      (19UL)                    /*!< PAD22FNCSEL (Bit 19)                                  */
12622 #define GPIO_PADREGF_PAD22FNCSEL_Msk      (0x380000UL)              /*!< PAD22FNCSEL (Bitfield-Mask: 0x07)                     */
12623 #define GPIO_PADREGF_PAD22STRNG_Pos       (18UL)                    /*!< PAD22STRNG (Bit 18)                                   */
12624 #define GPIO_PADREGF_PAD22STRNG_Msk       (0x40000UL)               /*!< PAD22STRNG (Bitfield-Mask: 0x01)                      */
12625 #define GPIO_PADREGF_PAD22INPEN_Pos       (17UL)                    /*!< PAD22INPEN (Bit 17)                                   */
12626 #define GPIO_PADREGF_PAD22INPEN_Msk       (0x20000UL)               /*!< PAD22INPEN (Bitfield-Mask: 0x01)                      */
12627 #define GPIO_PADREGF_PAD22PULL_Pos        (16UL)                    /*!< PAD22PULL (Bit 16)                                    */
12628 #define GPIO_PADREGF_PAD22PULL_Msk        (0x10000UL)               /*!< PAD22PULL (Bitfield-Mask: 0x01)                       */
12629 #define GPIO_PADREGF_PAD21FNCSEL_Pos      (11UL)                    /*!< PAD21FNCSEL (Bit 11)                                  */
12630 #define GPIO_PADREGF_PAD21FNCSEL_Msk      (0x3800UL)                /*!< PAD21FNCSEL (Bitfield-Mask: 0x07)                     */
12631 #define GPIO_PADREGF_PAD21STRNG_Pos       (10UL)                    /*!< PAD21STRNG (Bit 10)                                   */
12632 #define GPIO_PADREGF_PAD21STRNG_Msk       (0x400UL)                 /*!< PAD21STRNG (Bitfield-Mask: 0x01)                      */
12633 #define GPIO_PADREGF_PAD21INPEN_Pos       (9UL)                     /*!< PAD21INPEN (Bit 9)                                    */
12634 #define GPIO_PADREGF_PAD21INPEN_Msk       (0x200UL)                 /*!< PAD21INPEN (Bitfield-Mask: 0x01)                      */
12635 #define GPIO_PADREGF_PAD21PULL_Pos        (8UL)                     /*!< PAD21PULL (Bit 8)                                     */
12636 #define GPIO_PADREGF_PAD21PULL_Msk        (0x100UL)                 /*!< PAD21PULL (Bitfield-Mask: 0x01)                       */
12637 #define GPIO_PADREGF_PAD20FNCSEL_Pos      (3UL)                     /*!< PAD20FNCSEL (Bit 3)                                   */
12638 #define GPIO_PADREGF_PAD20FNCSEL_Msk      (0x38UL)                  /*!< PAD20FNCSEL (Bitfield-Mask: 0x07)                     */
12639 #define GPIO_PADREGF_PAD20STRNG_Pos       (2UL)                     /*!< PAD20STRNG (Bit 2)                                    */
12640 #define GPIO_PADREGF_PAD20STRNG_Msk       (0x4UL)                   /*!< PAD20STRNG (Bitfield-Mask: 0x01)                      */
12641 #define GPIO_PADREGF_PAD20INPEN_Pos       (1UL)                     /*!< PAD20INPEN (Bit 1)                                    */
12642 #define GPIO_PADREGF_PAD20INPEN_Msk       (0x2UL)                   /*!< PAD20INPEN (Bitfield-Mask: 0x01)                      */
12643 #define GPIO_PADREGF_PAD20PULL_Pos        (0UL)                     /*!< PAD20PULL (Bit 0)                                     */
12644 #define GPIO_PADREGF_PAD20PULL_Msk        (0x1UL)                   /*!< PAD20PULL (Bitfield-Mask: 0x01)                       */
12645 /* ========================================================  PADREGG  ======================================================== */
12646 #define GPIO_PADREGG_PAD27RSEL_Pos        (30UL)                    /*!< PAD27RSEL (Bit 30)                                    */
12647 #define GPIO_PADREGG_PAD27RSEL_Msk        (0xc0000000UL)            /*!< PAD27RSEL (Bitfield-Mask: 0x03)                       */
12648 #define GPIO_PADREGG_PAD27FNCSEL_Pos      (27UL)                    /*!< PAD27FNCSEL (Bit 27)                                  */
12649 #define GPIO_PADREGG_PAD27FNCSEL_Msk      (0x38000000UL)            /*!< PAD27FNCSEL (Bitfield-Mask: 0x07)                     */
12650 #define GPIO_PADREGG_PAD27STRNG_Pos       (26UL)                    /*!< PAD27STRNG (Bit 26)                                   */
12651 #define GPIO_PADREGG_PAD27STRNG_Msk       (0x4000000UL)             /*!< PAD27STRNG (Bitfield-Mask: 0x01)                      */
12652 #define GPIO_PADREGG_PAD27INPEN_Pos       (25UL)                    /*!< PAD27INPEN (Bit 25)                                   */
12653 #define GPIO_PADREGG_PAD27INPEN_Msk       (0x2000000UL)             /*!< PAD27INPEN (Bitfield-Mask: 0x01)                      */
12654 #define GPIO_PADREGG_PAD27PULL_Pos        (24UL)                    /*!< PAD27PULL (Bit 24)                                    */
12655 #define GPIO_PADREGG_PAD27PULL_Msk        (0x1000000UL)             /*!< PAD27PULL (Bitfield-Mask: 0x01)                       */
12656 #define GPIO_PADREGG_PAD26FNCSEL_Pos      (19UL)                    /*!< PAD26FNCSEL (Bit 19)                                  */
12657 #define GPIO_PADREGG_PAD26FNCSEL_Msk      (0x380000UL)              /*!< PAD26FNCSEL (Bitfield-Mask: 0x07)                     */
12658 #define GPIO_PADREGG_PAD26STRNG_Pos       (18UL)                    /*!< PAD26STRNG (Bit 18)                                   */
12659 #define GPIO_PADREGG_PAD26STRNG_Msk       (0x40000UL)               /*!< PAD26STRNG (Bitfield-Mask: 0x01)                      */
12660 #define GPIO_PADREGG_PAD26INPEN_Pos       (17UL)                    /*!< PAD26INPEN (Bit 17)                                   */
12661 #define GPIO_PADREGG_PAD26INPEN_Msk       (0x20000UL)               /*!< PAD26INPEN (Bitfield-Mask: 0x01)                      */
12662 #define GPIO_PADREGG_PAD26PULL_Pos        (16UL)                    /*!< PAD26PULL (Bit 16)                                    */
12663 #define GPIO_PADREGG_PAD26PULL_Msk        (0x10000UL)               /*!< PAD26PULL (Bitfield-Mask: 0x01)                       */
12664 #define GPIO_PADREGG_PAD25RSEL_Pos        (14UL)                    /*!< PAD25RSEL (Bit 14)                                    */
12665 #define GPIO_PADREGG_PAD25RSEL_Msk        (0xc000UL)                /*!< PAD25RSEL (Bitfield-Mask: 0x03)                       */
12666 #define GPIO_PADREGG_PAD25FNCSEL_Pos      (11UL)                    /*!< PAD25FNCSEL (Bit 11)                                  */
12667 #define GPIO_PADREGG_PAD25FNCSEL_Msk      (0x3800UL)                /*!< PAD25FNCSEL (Bitfield-Mask: 0x07)                     */
12668 #define GPIO_PADREGG_PAD25STRNG_Pos       (10UL)                    /*!< PAD25STRNG (Bit 10)                                   */
12669 #define GPIO_PADREGG_PAD25STRNG_Msk       (0x400UL)                 /*!< PAD25STRNG (Bitfield-Mask: 0x01)                      */
12670 #define GPIO_PADREGG_PAD25INPEN_Pos       (9UL)                     /*!< PAD25INPEN (Bit 9)                                    */
12671 #define GPIO_PADREGG_PAD25INPEN_Msk       (0x200UL)                 /*!< PAD25INPEN (Bitfield-Mask: 0x01)                      */
12672 #define GPIO_PADREGG_PAD25PULL_Pos        (8UL)                     /*!< PAD25PULL (Bit 8)                                     */
12673 #define GPIO_PADREGG_PAD25PULL_Msk        (0x100UL)                 /*!< PAD25PULL (Bitfield-Mask: 0x01)                       */
12674 #define GPIO_PADREGG_PAD24FNCSEL_Pos      (3UL)                     /*!< PAD24FNCSEL (Bit 3)                                   */
12675 #define GPIO_PADREGG_PAD24FNCSEL_Msk      (0x38UL)                  /*!< PAD24FNCSEL (Bitfield-Mask: 0x07)                     */
12676 #define GPIO_PADREGG_PAD24STRNG_Pos       (2UL)                     /*!< PAD24STRNG (Bit 2)                                    */
12677 #define GPIO_PADREGG_PAD24STRNG_Msk       (0x4UL)                   /*!< PAD24STRNG (Bitfield-Mask: 0x01)                      */
12678 #define GPIO_PADREGG_PAD24INPEN_Pos       (1UL)                     /*!< PAD24INPEN (Bit 1)                                    */
12679 #define GPIO_PADREGG_PAD24INPEN_Msk       (0x2UL)                   /*!< PAD24INPEN (Bitfield-Mask: 0x01)                      */
12680 #define GPIO_PADREGG_PAD24PULL_Pos        (0UL)                     /*!< PAD24PULL (Bit 0)                                     */
12681 #define GPIO_PADREGG_PAD24PULL_Msk        (0x1UL)                   /*!< PAD24PULL (Bitfield-Mask: 0x01)                       */
12682 /* ========================================================  PADREGH  ======================================================== */
12683 #define GPIO_PADREGH_PAD31FNCSEL_Pos      (27UL)                    /*!< PAD31FNCSEL (Bit 27)                                  */
12684 #define GPIO_PADREGH_PAD31FNCSEL_Msk      (0x38000000UL)            /*!< PAD31FNCSEL (Bitfield-Mask: 0x07)                     */
12685 #define GPIO_PADREGH_PAD31STRNG_Pos       (26UL)                    /*!< PAD31STRNG (Bit 26)                                   */
12686 #define GPIO_PADREGH_PAD31STRNG_Msk       (0x4000000UL)             /*!< PAD31STRNG (Bitfield-Mask: 0x01)                      */
12687 #define GPIO_PADREGH_PAD31INPEN_Pos       (25UL)                    /*!< PAD31INPEN (Bit 25)                                   */
12688 #define GPIO_PADREGH_PAD31INPEN_Msk       (0x2000000UL)             /*!< PAD31INPEN (Bitfield-Mask: 0x01)                      */
12689 #define GPIO_PADREGH_PAD31PULL_Pos        (24UL)                    /*!< PAD31PULL (Bit 24)                                    */
12690 #define GPIO_PADREGH_PAD31PULL_Msk        (0x1000000UL)             /*!< PAD31PULL (Bitfield-Mask: 0x01)                       */
12691 #define GPIO_PADREGH_PAD30FNCSEL_Pos      (19UL)                    /*!< PAD30FNCSEL (Bit 19)                                  */
12692 #define GPIO_PADREGH_PAD30FNCSEL_Msk      (0x380000UL)              /*!< PAD30FNCSEL (Bitfield-Mask: 0x07)                     */
12693 #define GPIO_PADREGH_PAD30STRNG_Pos       (18UL)                    /*!< PAD30STRNG (Bit 18)                                   */
12694 #define GPIO_PADREGH_PAD30STRNG_Msk       (0x40000UL)               /*!< PAD30STRNG (Bitfield-Mask: 0x01)                      */
12695 #define GPIO_PADREGH_PAD30INPEN_Pos       (17UL)                    /*!< PAD30INPEN (Bit 17)                                   */
12696 #define GPIO_PADREGH_PAD30INPEN_Msk       (0x20000UL)               /*!< PAD30INPEN (Bitfield-Mask: 0x01)                      */
12697 #define GPIO_PADREGH_PAD30PULL_Pos        (16UL)                    /*!< PAD30PULL (Bit 16)                                    */
12698 #define GPIO_PADREGH_PAD30PULL_Msk        (0x10000UL)               /*!< PAD30PULL (Bitfield-Mask: 0x01)                       */
12699 #define GPIO_PADREGH_PAD29FNCSEL_Pos      (11UL)                    /*!< PAD29FNCSEL (Bit 11)                                  */
12700 #define GPIO_PADREGH_PAD29FNCSEL_Msk      (0x3800UL)                /*!< PAD29FNCSEL (Bitfield-Mask: 0x07)                     */
12701 #define GPIO_PADREGH_PAD29STRNG_Pos       (10UL)                    /*!< PAD29STRNG (Bit 10)                                   */
12702 #define GPIO_PADREGH_PAD29STRNG_Msk       (0x400UL)                 /*!< PAD29STRNG (Bitfield-Mask: 0x01)                      */
12703 #define GPIO_PADREGH_PAD29INPEN_Pos       (9UL)                     /*!< PAD29INPEN (Bit 9)                                    */
12704 #define GPIO_PADREGH_PAD29INPEN_Msk       (0x200UL)                 /*!< PAD29INPEN (Bitfield-Mask: 0x01)                      */
12705 #define GPIO_PADREGH_PAD29PULL_Pos        (8UL)                     /*!< PAD29PULL (Bit 8)                                     */
12706 #define GPIO_PADREGH_PAD29PULL_Msk        (0x100UL)                 /*!< PAD29PULL (Bitfield-Mask: 0x01)                       */
12707 #define GPIO_PADREGH_PAD28FNCSEL_Pos      (3UL)                     /*!< PAD28FNCSEL (Bit 3)                                   */
12708 #define GPIO_PADREGH_PAD28FNCSEL_Msk      (0x38UL)                  /*!< PAD28FNCSEL (Bitfield-Mask: 0x07)                     */
12709 #define GPIO_PADREGH_PAD28STRNG_Pos       (2UL)                     /*!< PAD28STRNG (Bit 2)                                    */
12710 #define GPIO_PADREGH_PAD28STRNG_Msk       (0x4UL)                   /*!< PAD28STRNG (Bitfield-Mask: 0x01)                      */
12711 #define GPIO_PADREGH_PAD28INPEN_Pos       (1UL)                     /*!< PAD28INPEN (Bit 1)                                    */
12712 #define GPIO_PADREGH_PAD28INPEN_Msk       (0x2UL)                   /*!< PAD28INPEN (Bitfield-Mask: 0x01)                      */
12713 #define GPIO_PADREGH_PAD28PULL_Pos        (0UL)                     /*!< PAD28PULL (Bit 0)                                     */
12714 #define GPIO_PADREGH_PAD28PULL_Msk        (0x1UL)                   /*!< PAD28PULL (Bitfield-Mask: 0x01)                       */
12715 /* ========================================================  PADREGI  ======================================================== */
12716 #define GPIO_PADREGI_PAD35FNCSEL_Pos      (27UL)                    /*!< PAD35FNCSEL (Bit 27)                                  */
12717 #define GPIO_PADREGI_PAD35FNCSEL_Msk      (0x38000000UL)            /*!< PAD35FNCSEL (Bitfield-Mask: 0x07)                     */
12718 #define GPIO_PADREGI_PAD35STRNG_Pos       (26UL)                    /*!< PAD35STRNG (Bit 26)                                   */
12719 #define GPIO_PADREGI_PAD35STRNG_Msk       (0x4000000UL)             /*!< PAD35STRNG (Bitfield-Mask: 0x01)                      */
12720 #define GPIO_PADREGI_PAD35INPEN_Pos       (25UL)                    /*!< PAD35INPEN (Bit 25)                                   */
12721 #define GPIO_PADREGI_PAD35INPEN_Msk       (0x2000000UL)             /*!< PAD35INPEN (Bitfield-Mask: 0x01)                      */
12722 #define GPIO_PADREGI_PAD35PULL_Pos        (24UL)                    /*!< PAD35PULL (Bit 24)                                    */
12723 #define GPIO_PADREGI_PAD35PULL_Msk        (0x1000000UL)             /*!< PAD35PULL (Bitfield-Mask: 0x01)                       */
12724 #define GPIO_PADREGI_PAD34FNCSEL_Pos      (19UL)                    /*!< PAD34FNCSEL (Bit 19)                                  */
12725 #define GPIO_PADREGI_PAD34FNCSEL_Msk      (0x380000UL)              /*!< PAD34FNCSEL (Bitfield-Mask: 0x07)                     */
12726 #define GPIO_PADREGI_PAD34STRNG_Pos       (18UL)                    /*!< PAD34STRNG (Bit 18)                                   */
12727 #define GPIO_PADREGI_PAD34STRNG_Msk       (0x40000UL)               /*!< PAD34STRNG (Bitfield-Mask: 0x01)                      */
12728 #define GPIO_PADREGI_PAD34INPEN_Pos       (17UL)                    /*!< PAD34INPEN (Bit 17)                                   */
12729 #define GPIO_PADREGI_PAD34INPEN_Msk       (0x20000UL)               /*!< PAD34INPEN (Bitfield-Mask: 0x01)                      */
12730 #define GPIO_PADREGI_PAD34PULL_Pos        (16UL)                    /*!< PAD34PULL (Bit 16)                                    */
12731 #define GPIO_PADREGI_PAD34PULL_Msk        (0x10000UL)               /*!< PAD34PULL (Bitfield-Mask: 0x01)                       */
12732 #define GPIO_PADREGI_PAD33FNCSEL_Pos      (11UL)                    /*!< PAD33FNCSEL (Bit 11)                                  */
12733 #define GPIO_PADREGI_PAD33FNCSEL_Msk      (0x3800UL)                /*!< PAD33FNCSEL (Bitfield-Mask: 0x07)                     */
12734 #define GPIO_PADREGI_PAD33STRNG_Pos       (10UL)                    /*!< PAD33STRNG (Bit 10)                                   */
12735 #define GPIO_PADREGI_PAD33STRNG_Msk       (0x400UL)                 /*!< PAD33STRNG (Bitfield-Mask: 0x01)                      */
12736 #define GPIO_PADREGI_PAD33INPEN_Pos       (9UL)                     /*!< PAD33INPEN (Bit 9)                                    */
12737 #define GPIO_PADREGI_PAD33INPEN_Msk       (0x200UL)                 /*!< PAD33INPEN (Bitfield-Mask: 0x01)                      */
12738 #define GPIO_PADREGI_PAD33PULL_Pos        (8UL)                     /*!< PAD33PULL (Bit 8)                                     */
12739 #define GPIO_PADREGI_PAD33PULL_Msk        (0x100UL)                 /*!< PAD33PULL (Bitfield-Mask: 0x01)                       */
12740 #define GPIO_PADREGI_PAD32FNCSEL_Pos      (3UL)                     /*!< PAD32FNCSEL (Bit 3)                                   */
12741 #define GPIO_PADREGI_PAD32FNCSEL_Msk      (0x38UL)                  /*!< PAD32FNCSEL (Bitfield-Mask: 0x07)                     */
12742 #define GPIO_PADREGI_PAD32STRNG_Pos       (2UL)                     /*!< PAD32STRNG (Bit 2)                                    */
12743 #define GPIO_PADREGI_PAD32STRNG_Msk       (0x4UL)                   /*!< PAD32STRNG (Bitfield-Mask: 0x01)                      */
12744 #define GPIO_PADREGI_PAD32INPEN_Pos       (1UL)                     /*!< PAD32INPEN (Bit 1)                                    */
12745 #define GPIO_PADREGI_PAD32INPEN_Msk       (0x2UL)                   /*!< PAD32INPEN (Bitfield-Mask: 0x01)                      */
12746 #define GPIO_PADREGI_PAD32PULL_Pos        (0UL)                     /*!< PAD32PULL (Bit 0)                                     */
12747 #define GPIO_PADREGI_PAD32PULL_Msk        (0x1UL)                   /*!< PAD32PULL (Bitfield-Mask: 0x01)                       */
12748 /* ========================================================  PADREGJ  ======================================================== */
12749 #define GPIO_PADREGJ_PAD39RSEL_Pos        (30UL)                    /*!< PAD39RSEL (Bit 30)                                    */
12750 #define GPIO_PADREGJ_PAD39RSEL_Msk        (0xc0000000UL)            /*!< PAD39RSEL (Bitfield-Mask: 0x03)                       */
12751 #define GPIO_PADREGJ_PAD39FNCSEL_Pos      (27UL)                    /*!< PAD39FNCSEL (Bit 27)                                  */
12752 #define GPIO_PADREGJ_PAD39FNCSEL_Msk      (0x38000000UL)            /*!< PAD39FNCSEL (Bitfield-Mask: 0x07)                     */
12753 #define GPIO_PADREGJ_PAD39STRNG_Pos       (26UL)                    /*!< PAD39STRNG (Bit 26)                                   */
12754 #define GPIO_PADREGJ_PAD39STRNG_Msk       (0x4000000UL)             /*!< PAD39STRNG (Bitfield-Mask: 0x01)                      */
12755 #define GPIO_PADREGJ_PAD39INPEN_Pos       (25UL)                    /*!< PAD39INPEN (Bit 25)                                   */
12756 #define GPIO_PADREGJ_PAD39INPEN_Msk       (0x2000000UL)             /*!< PAD39INPEN (Bitfield-Mask: 0x01)                      */
12757 #define GPIO_PADREGJ_PAD39PULL_Pos        (24UL)                    /*!< PAD39PULL (Bit 24)                                    */
12758 #define GPIO_PADREGJ_PAD39PULL_Msk        (0x1000000UL)             /*!< PAD39PULL (Bitfield-Mask: 0x01)                       */
12759 #define GPIO_PADREGJ_PAD38FNCSEL_Pos      (19UL)                    /*!< PAD38FNCSEL (Bit 19)                                  */
12760 #define GPIO_PADREGJ_PAD38FNCSEL_Msk      (0x380000UL)              /*!< PAD38FNCSEL (Bitfield-Mask: 0x07)                     */
12761 #define GPIO_PADREGJ_PAD38STRNG_Pos       (18UL)                    /*!< PAD38STRNG (Bit 18)                                   */
12762 #define GPIO_PADREGJ_PAD38STRNG_Msk       (0x40000UL)               /*!< PAD38STRNG (Bitfield-Mask: 0x01)                      */
12763 #define GPIO_PADREGJ_PAD38INPEN_Pos       (17UL)                    /*!< PAD38INPEN (Bit 17)                                   */
12764 #define GPIO_PADREGJ_PAD38INPEN_Msk       (0x20000UL)               /*!< PAD38INPEN (Bitfield-Mask: 0x01)                      */
12765 #define GPIO_PADREGJ_PAD38PULL_Pos        (16UL)                    /*!< PAD38PULL (Bit 16)                                    */
12766 #define GPIO_PADREGJ_PAD38PULL_Msk        (0x10000UL)               /*!< PAD38PULL (Bitfield-Mask: 0x01)                       */
12767 #define GPIO_PADREGJ_PAD37PWRDN_Pos       (15UL)                    /*!< PAD37PWRDN (Bit 15)                                   */
12768 #define GPIO_PADREGJ_PAD37PWRDN_Msk       (0x8000UL)                /*!< PAD37PWRDN (Bitfield-Mask: 0x01)                      */
12769 #define GPIO_PADREGJ_PAD37FNCSEL_Pos      (11UL)                    /*!< PAD37FNCSEL (Bit 11)                                  */
12770 #define GPIO_PADREGJ_PAD37FNCSEL_Msk      (0x3800UL)                /*!< PAD37FNCSEL (Bitfield-Mask: 0x07)                     */
12771 #define GPIO_PADREGJ_PAD37STRNG_Pos       (10UL)                    /*!< PAD37STRNG (Bit 10)                                   */
12772 #define GPIO_PADREGJ_PAD37STRNG_Msk       (0x400UL)                 /*!< PAD37STRNG (Bitfield-Mask: 0x01)                      */
12773 #define GPIO_PADREGJ_PAD37INPEN_Pos       (9UL)                     /*!< PAD37INPEN (Bit 9)                                    */
12774 #define GPIO_PADREGJ_PAD37INPEN_Msk       (0x200UL)                 /*!< PAD37INPEN (Bitfield-Mask: 0x01)                      */
12775 #define GPIO_PADREGJ_PAD37PULL_Pos        (8UL)                     /*!< PAD37PULL (Bit 8)                                     */
12776 #define GPIO_PADREGJ_PAD37PULL_Msk        (0x100UL)                 /*!< PAD37PULL (Bitfield-Mask: 0x01)                       */
12777 #define GPIO_PADREGJ_PAD36FNCSEL_Pos      (3UL)                     /*!< PAD36FNCSEL (Bit 3)                                   */
12778 #define GPIO_PADREGJ_PAD36FNCSEL_Msk      (0x38UL)                  /*!< PAD36FNCSEL (Bitfield-Mask: 0x07)                     */
12779 #define GPIO_PADREGJ_PAD36STRNG_Pos       (2UL)                     /*!< PAD36STRNG (Bit 2)                                    */
12780 #define GPIO_PADREGJ_PAD36STRNG_Msk       (0x4UL)                   /*!< PAD36STRNG (Bitfield-Mask: 0x01)                      */
12781 #define GPIO_PADREGJ_PAD36INPEN_Pos       (1UL)                     /*!< PAD36INPEN (Bit 1)                                    */
12782 #define GPIO_PADREGJ_PAD36INPEN_Msk       (0x2UL)                   /*!< PAD36INPEN (Bitfield-Mask: 0x01)                      */
12783 #define GPIO_PADREGJ_PAD36PULL_Pos        (0UL)                     /*!< PAD36PULL (Bit 0)                                     */
12784 #define GPIO_PADREGJ_PAD36PULL_Msk        (0x1UL)                   /*!< PAD36PULL (Bitfield-Mask: 0x01)                       */
12785 /* ========================================================  PADREGK  ======================================================== */
12786 #define GPIO_PADREGK_PAD43RSEL_Pos        (30UL)                    /*!< PAD43RSEL (Bit 30)                                    */
12787 #define GPIO_PADREGK_PAD43RSEL_Msk        (0xc0000000UL)            /*!< PAD43RSEL (Bitfield-Mask: 0x03)                       */
12788 #define GPIO_PADREGK_PAD43FNCSEL_Pos      (27UL)                    /*!< PAD43FNCSEL (Bit 27)                                  */
12789 #define GPIO_PADREGK_PAD43FNCSEL_Msk      (0x38000000UL)            /*!< PAD43FNCSEL (Bitfield-Mask: 0x07)                     */
12790 #define GPIO_PADREGK_PAD43STRNG_Pos       (26UL)                    /*!< PAD43STRNG (Bit 26)                                   */
12791 #define GPIO_PADREGK_PAD43STRNG_Msk       (0x4000000UL)             /*!< PAD43STRNG (Bitfield-Mask: 0x01)                      */
12792 #define GPIO_PADREGK_PAD43INPEN_Pos       (25UL)                    /*!< PAD43INPEN (Bit 25)                                   */
12793 #define GPIO_PADREGK_PAD43INPEN_Msk       (0x2000000UL)             /*!< PAD43INPEN (Bitfield-Mask: 0x01)                      */
12794 #define GPIO_PADREGK_PAD43PULL_Pos        (24UL)                    /*!< PAD43PULL (Bit 24)                                    */
12795 #define GPIO_PADREGK_PAD43PULL_Msk        (0x1000000UL)             /*!< PAD43PULL (Bitfield-Mask: 0x01)                       */
12796 #define GPIO_PADREGK_PAD42RSEL_Pos        (22UL)                    /*!< PAD42RSEL (Bit 22)                                    */
12797 #define GPIO_PADREGK_PAD42RSEL_Msk        (0xc00000UL)              /*!< PAD42RSEL (Bitfield-Mask: 0x03)                       */
12798 #define GPIO_PADREGK_PAD42FNCSEL_Pos      (19UL)                    /*!< PAD42FNCSEL (Bit 19)                                  */
12799 #define GPIO_PADREGK_PAD42FNCSEL_Msk      (0x380000UL)              /*!< PAD42FNCSEL (Bitfield-Mask: 0x07)                     */
12800 #define GPIO_PADREGK_PAD42STRNG_Pos       (18UL)                    /*!< PAD42STRNG (Bit 18)                                   */
12801 #define GPIO_PADREGK_PAD42STRNG_Msk       (0x40000UL)               /*!< PAD42STRNG (Bitfield-Mask: 0x01)                      */
12802 #define GPIO_PADREGK_PAD42INPEN_Pos       (17UL)                    /*!< PAD42INPEN (Bit 17)                                   */
12803 #define GPIO_PADREGK_PAD42INPEN_Msk       (0x20000UL)               /*!< PAD42INPEN (Bitfield-Mask: 0x01)                      */
12804 #define GPIO_PADREGK_PAD42PULL_Pos        (16UL)                    /*!< PAD42PULL (Bit 16)                                    */
12805 #define GPIO_PADREGK_PAD42PULL_Msk        (0x10000UL)               /*!< PAD42PULL (Bitfield-Mask: 0x01)                       */
12806 #define GPIO_PADREGK_PAD41PWRDN_Pos       (15UL)                    /*!< PAD41PWRDN (Bit 15)                                   */
12807 #define GPIO_PADREGK_PAD41PWRDN_Msk       (0x8000UL)                /*!< PAD41PWRDN (Bitfield-Mask: 0x01)                      */
12808 #define GPIO_PADREGK_PAD41FNCSEL_Pos      (11UL)                    /*!< PAD41FNCSEL (Bit 11)                                  */
12809 #define GPIO_PADREGK_PAD41FNCSEL_Msk      (0x3800UL)                /*!< PAD41FNCSEL (Bitfield-Mask: 0x07)                     */
12810 #define GPIO_PADREGK_PAD41STRNG_Pos       (10UL)                    /*!< PAD41STRNG (Bit 10)                                   */
12811 #define GPIO_PADREGK_PAD41STRNG_Msk       (0x400UL)                 /*!< PAD41STRNG (Bitfield-Mask: 0x01)                      */
12812 #define GPIO_PADREGK_PAD41INPEN_Pos       (9UL)                     /*!< PAD41INPEN (Bit 9)                                    */
12813 #define GPIO_PADREGK_PAD41INPEN_Msk       (0x200UL)                 /*!< PAD41INPEN (Bitfield-Mask: 0x01)                      */
12814 #define GPIO_PADREGK_PAD41PULL_Pos        (8UL)                     /*!< PAD41PULL (Bit 8)                                     */
12815 #define GPIO_PADREGK_PAD41PULL_Msk        (0x100UL)                 /*!< PAD41PULL (Bitfield-Mask: 0x01)                       */
12816 #define GPIO_PADREGK_PAD40RSEL_Pos        (6UL)                     /*!< PAD40RSEL (Bit 6)                                     */
12817 #define GPIO_PADREGK_PAD40RSEL_Msk        (0xc0UL)                  /*!< PAD40RSEL (Bitfield-Mask: 0x03)                       */
12818 #define GPIO_PADREGK_PAD40FNCSEL_Pos      (3UL)                     /*!< PAD40FNCSEL (Bit 3)                                   */
12819 #define GPIO_PADREGK_PAD40FNCSEL_Msk      (0x38UL)                  /*!< PAD40FNCSEL (Bitfield-Mask: 0x07)                     */
12820 #define GPIO_PADREGK_PAD40STRNG_Pos       (2UL)                     /*!< PAD40STRNG (Bit 2)                                    */
12821 #define GPIO_PADREGK_PAD40STRNG_Msk       (0x4UL)                   /*!< PAD40STRNG (Bitfield-Mask: 0x01)                      */
12822 #define GPIO_PADREGK_PAD40INPEN_Pos       (1UL)                     /*!< PAD40INPEN (Bit 1)                                    */
12823 #define GPIO_PADREGK_PAD40INPEN_Msk       (0x2UL)                   /*!< PAD40INPEN (Bitfield-Mask: 0x01)                      */
12824 #define GPIO_PADREGK_PAD40PULL_Pos        (0UL)                     /*!< PAD40PULL (Bit 0)                                     */
12825 #define GPIO_PADREGK_PAD40PULL_Msk        (0x1UL)                   /*!< PAD40PULL (Bitfield-Mask: 0x01)                       */
12826 /* ========================================================  PADREGL  ======================================================== */
12827 #define GPIO_PADREGL_PAD47FNCSEL_Pos      (27UL)                    /*!< PAD47FNCSEL (Bit 27)                                  */
12828 #define GPIO_PADREGL_PAD47FNCSEL_Msk      (0x38000000UL)            /*!< PAD47FNCSEL (Bitfield-Mask: 0x07)                     */
12829 #define GPIO_PADREGL_PAD47STRNG_Pos       (26UL)                    /*!< PAD47STRNG (Bit 26)                                   */
12830 #define GPIO_PADREGL_PAD47STRNG_Msk       (0x4000000UL)             /*!< PAD47STRNG (Bitfield-Mask: 0x01)                      */
12831 #define GPIO_PADREGL_PAD47INPEN_Pos       (25UL)                    /*!< PAD47INPEN (Bit 25)                                   */
12832 #define GPIO_PADREGL_PAD47INPEN_Msk       (0x2000000UL)             /*!< PAD47INPEN (Bitfield-Mask: 0x01)                      */
12833 #define GPIO_PADREGL_PAD47PULL_Pos        (24UL)                    /*!< PAD47PULL (Bit 24)                                    */
12834 #define GPIO_PADREGL_PAD47PULL_Msk        (0x1000000UL)             /*!< PAD47PULL (Bitfield-Mask: 0x01)                       */
12835 #define GPIO_PADREGL_PAD46FNCSEL_Pos      (19UL)                    /*!< PAD46FNCSEL (Bit 19)                                  */
12836 #define GPIO_PADREGL_PAD46FNCSEL_Msk      (0x380000UL)              /*!< PAD46FNCSEL (Bitfield-Mask: 0x07)                     */
12837 #define GPIO_PADREGL_PAD46STRNG_Pos       (18UL)                    /*!< PAD46STRNG (Bit 18)                                   */
12838 #define GPIO_PADREGL_PAD46STRNG_Msk       (0x40000UL)               /*!< PAD46STRNG (Bitfield-Mask: 0x01)                      */
12839 #define GPIO_PADREGL_PAD46INPEN_Pos       (17UL)                    /*!< PAD46INPEN (Bit 17)                                   */
12840 #define GPIO_PADREGL_PAD46INPEN_Msk       (0x20000UL)               /*!< PAD46INPEN (Bitfield-Mask: 0x01)                      */
12841 #define GPIO_PADREGL_PAD46PULL_Pos        (16UL)                    /*!< PAD46PULL (Bit 16)                                    */
12842 #define GPIO_PADREGL_PAD46PULL_Msk        (0x10000UL)               /*!< PAD46PULL (Bitfield-Mask: 0x01)                       */
12843 #define GPIO_PADREGL_PAD45FNCSEL_Pos      (11UL)                    /*!< PAD45FNCSEL (Bit 11)                                  */
12844 #define GPIO_PADREGL_PAD45FNCSEL_Msk      (0x3800UL)                /*!< PAD45FNCSEL (Bitfield-Mask: 0x07)                     */
12845 #define GPIO_PADREGL_PAD45STRNG_Pos       (10UL)                    /*!< PAD45STRNG (Bit 10)                                   */
12846 #define GPIO_PADREGL_PAD45STRNG_Msk       (0x400UL)                 /*!< PAD45STRNG (Bitfield-Mask: 0x01)                      */
12847 #define GPIO_PADREGL_PAD45INPEN_Pos       (9UL)                     /*!< PAD45INPEN (Bit 9)                                    */
12848 #define GPIO_PADREGL_PAD45INPEN_Msk       (0x200UL)                 /*!< PAD45INPEN (Bitfield-Mask: 0x01)                      */
12849 #define GPIO_PADREGL_PAD45PULL_Pos        (8UL)                     /*!< PAD45PULL (Bit 8)                                     */
12850 #define GPIO_PADREGL_PAD45PULL_Msk        (0x100UL)                 /*!< PAD45PULL (Bitfield-Mask: 0x01)                       */
12851 #define GPIO_PADREGL_PAD44FNCSEL_Pos      (3UL)                     /*!< PAD44FNCSEL (Bit 3)                                   */
12852 #define GPIO_PADREGL_PAD44FNCSEL_Msk      (0x38UL)                  /*!< PAD44FNCSEL (Bitfield-Mask: 0x07)                     */
12853 #define GPIO_PADREGL_PAD44STRNG_Pos       (2UL)                     /*!< PAD44STRNG (Bit 2)                                    */
12854 #define GPIO_PADREGL_PAD44STRNG_Msk       (0x4UL)                   /*!< PAD44STRNG (Bitfield-Mask: 0x01)                      */
12855 #define GPIO_PADREGL_PAD44INPEN_Pos       (1UL)                     /*!< PAD44INPEN (Bit 1)                                    */
12856 #define GPIO_PADREGL_PAD44INPEN_Msk       (0x2UL)                   /*!< PAD44INPEN (Bitfield-Mask: 0x01)                      */
12857 #define GPIO_PADREGL_PAD44PULL_Pos        (0UL)                     /*!< PAD44PULL (Bit 0)                                     */
12858 #define GPIO_PADREGL_PAD44PULL_Msk        (0x1UL)                   /*!< PAD44PULL (Bitfield-Mask: 0x01)                       */
12859 /* ========================================================  PADREGM  ======================================================== */
12860 #define GPIO_PADREGM_PAD51FNCSEL_Pos      (27UL)                    /*!< PAD51FNCSEL (Bit 27)                                  */
12861 #define GPIO_PADREGM_PAD51FNCSEL_Msk      (0x38000000UL)            /*!< PAD51FNCSEL (Bitfield-Mask: 0x07)                     */
12862 #define GPIO_PADREGM_PAD51STRNG_Pos       (26UL)                    /*!< PAD51STRNG (Bit 26)                                   */
12863 #define GPIO_PADREGM_PAD51STRNG_Msk       (0x4000000UL)             /*!< PAD51STRNG (Bitfield-Mask: 0x01)                      */
12864 #define GPIO_PADREGM_PAD51INPEN_Pos       (25UL)                    /*!< PAD51INPEN (Bit 25)                                   */
12865 #define GPIO_PADREGM_PAD51INPEN_Msk       (0x2000000UL)             /*!< PAD51INPEN (Bitfield-Mask: 0x01)                      */
12866 #define GPIO_PADREGM_PAD51PULL_Pos        (24UL)                    /*!< PAD51PULL (Bit 24)                                    */
12867 #define GPIO_PADREGM_PAD51PULL_Msk        (0x1000000UL)             /*!< PAD51PULL (Bitfield-Mask: 0x01)                       */
12868 #define GPIO_PADREGM_PAD50FNCSEL_Pos      (19UL)                    /*!< PAD50FNCSEL (Bit 19)                                  */
12869 #define GPIO_PADREGM_PAD50FNCSEL_Msk      (0x380000UL)              /*!< PAD50FNCSEL (Bitfield-Mask: 0x07)                     */
12870 #define GPIO_PADREGM_PAD50STRNG_Pos       (18UL)                    /*!< PAD50STRNG (Bit 18)                                   */
12871 #define GPIO_PADREGM_PAD50STRNG_Msk       (0x40000UL)               /*!< PAD50STRNG (Bitfield-Mask: 0x01)                      */
12872 #define GPIO_PADREGM_PAD50INPEN_Pos       (17UL)                    /*!< PAD50INPEN (Bit 17)                                   */
12873 #define GPIO_PADREGM_PAD50INPEN_Msk       (0x20000UL)               /*!< PAD50INPEN (Bitfield-Mask: 0x01)                      */
12874 #define GPIO_PADREGM_PAD50PULL_Pos        (16UL)                    /*!< PAD50PULL (Bit 16)                                    */
12875 #define GPIO_PADREGM_PAD50PULL_Msk        (0x10000UL)               /*!< PAD50PULL (Bitfield-Mask: 0x01)                       */
12876 #define GPIO_PADREGM_PAD49RSEL_Pos        (14UL)                    /*!< PAD49RSEL (Bit 14)                                    */
12877 #define GPIO_PADREGM_PAD49RSEL_Msk        (0xc000UL)                /*!< PAD49RSEL (Bitfield-Mask: 0x03)                       */
12878 #define GPIO_PADREGM_PAD49FNCSEL_Pos      (11UL)                    /*!< PAD49FNCSEL (Bit 11)                                  */
12879 #define GPIO_PADREGM_PAD49FNCSEL_Msk      (0x3800UL)                /*!< PAD49FNCSEL (Bitfield-Mask: 0x07)                     */
12880 #define GPIO_PADREGM_PAD49STRNG_Pos       (10UL)                    /*!< PAD49STRNG (Bit 10)                                   */
12881 #define GPIO_PADREGM_PAD49STRNG_Msk       (0x400UL)                 /*!< PAD49STRNG (Bitfield-Mask: 0x01)                      */
12882 #define GPIO_PADREGM_PAD49INPEN_Pos       (9UL)                     /*!< PAD49INPEN (Bit 9)                                    */
12883 #define GPIO_PADREGM_PAD49INPEN_Msk       (0x200UL)                 /*!< PAD49INPEN (Bitfield-Mask: 0x01)                      */
12884 #define GPIO_PADREGM_PAD49PULL_Pos        (8UL)                     /*!< PAD49PULL (Bit 8)                                     */
12885 #define GPIO_PADREGM_PAD49PULL_Msk        (0x100UL)                 /*!< PAD49PULL (Bitfield-Mask: 0x01)                       */
12886 #define GPIO_PADREGM_PAD48RSEL_Pos        (6UL)                     /*!< PAD48RSEL (Bit 6)                                     */
12887 #define GPIO_PADREGM_PAD48RSEL_Msk        (0xc0UL)                  /*!< PAD48RSEL (Bitfield-Mask: 0x03)                       */
12888 #define GPIO_PADREGM_PAD48FNCSEL_Pos      (3UL)                     /*!< PAD48FNCSEL (Bit 3)                                   */
12889 #define GPIO_PADREGM_PAD48FNCSEL_Msk      (0x38UL)                  /*!< PAD48FNCSEL (Bitfield-Mask: 0x07)                     */
12890 #define GPIO_PADREGM_PAD48STRNG_Pos       (2UL)                     /*!< PAD48STRNG (Bit 2)                                    */
12891 #define GPIO_PADREGM_PAD48STRNG_Msk       (0x4UL)                   /*!< PAD48STRNG (Bitfield-Mask: 0x01)                      */
12892 #define GPIO_PADREGM_PAD48INPEN_Pos       (1UL)                     /*!< PAD48INPEN (Bit 1)                                    */
12893 #define GPIO_PADREGM_PAD48INPEN_Msk       (0x2UL)                   /*!< PAD48INPEN (Bitfield-Mask: 0x01)                      */
12894 #define GPIO_PADREGM_PAD48PULL_Pos        (0UL)                     /*!< PAD48PULL (Bit 0)                                     */
12895 #define GPIO_PADREGM_PAD48PULL_Msk        (0x1UL)                   /*!< PAD48PULL (Bitfield-Mask: 0x01)                       */
12896 /* ========================================================  PADREGN  ======================================================== */
12897 #define GPIO_PADREGN_PAD55FNCSEL_Pos      (27UL)                    /*!< PAD55FNCSEL (Bit 27)                                  */
12898 #define GPIO_PADREGN_PAD55FNCSEL_Msk      (0x38000000UL)            /*!< PAD55FNCSEL (Bitfield-Mask: 0x07)                     */
12899 #define GPIO_PADREGN_PAD55STRNG_Pos       (26UL)                    /*!< PAD55STRNG (Bit 26)                                   */
12900 #define GPIO_PADREGN_PAD55STRNG_Msk       (0x4000000UL)             /*!< PAD55STRNG (Bitfield-Mask: 0x01)                      */
12901 #define GPIO_PADREGN_PAD55INPEN_Pos       (25UL)                    /*!< PAD55INPEN (Bit 25)                                   */
12902 #define GPIO_PADREGN_PAD55INPEN_Msk       (0x2000000UL)             /*!< PAD55INPEN (Bitfield-Mask: 0x01)                      */
12903 #define GPIO_PADREGN_PAD55PULL_Pos        (24UL)                    /*!< PAD55PULL (Bit 24)                                    */
12904 #define GPIO_PADREGN_PAD55PULL_Msk        (0x1000000UL)             /*!< PAD55PULL (Bitfield-Mask: 0x01)                       */
12905 #define GPIO_PADREGN_PAD54FNCSEL_Pos      (19UL)                    /*!< PAD54FNCSEL (Bit 19)                                  */
12906 #define GPIO_PADREGN_PAD54FNCSEL_Msk      (0x380000UL)              /*!< PAD54FNCSEL (Bitfield-Mask: 0x07)                     */
12907 #define GPIO_PADREGN_PAD54STRNG_Pos       (18UL)                    /*!< PAD54STRNG (Bit 18)                                   */
12908 #define GPIO_PADREGN_PAD54STRNG_Msk       (0x40000UL)               /*!< PAD54STRNG (Bitfield-Mask: 0x01)                      */
12909 #define GPIO_PADREGN_PAD54INPEN_Pos       (17UL)                    /*!< PAD54INPEN (Bit 17)                                   */
12910 #define GPIO_PADREGN_PAD54INPEN_Msk       (0x20000UL)               /*!< PAD54INPEN (Bitfield-Mask: 0x01)                      */
12911 #define GPIO_PADREGN_PAD54PULL_Pos        (16UL)                    /*!< PAD54PULL (Bit 16)                                    */
12912 #define GPIO_PADREGN_PAD54PULL_Msk        (0x10000UL)               /*!< PAD54PULL (Bitfield-Mask: 0x01)                       */
12913 #define GPIO_PADREGN_PAD53FNCSEL_Pos      (11UL)                    /*!< PAD53FNCSEL (Bit 11)                                  */
12914 #define GPIO_PADREGN_PAD53FNCSEL_Msk      (0x3800UL)                /*!< PAD53FNCSEL (Bitfield-Mask: 0x07)                     */
12915 #define GPIO_PADREGN_PAD53STRNG_Pos       (10UL)                    /*!< PAD53STRNG (Bit 10)                                   */
12916 #define GPIO_PADREGN_PAD53STRNG_Msk       (0x400UL)                 /*!< PAD53STRNG (Bitfield-Mask: 0x01)                      */
12917 #define GPIO_PADREGN_PAD53INPEN_Pos       (9UL)                     /*!< PAD53INPEN (Bit 9)                                    */
12918 #define GPIO_PADREGN_PAD53INPEN_Msk       (0x200UL)                 /*!< PAD53INPEN (Bitfield-Mask: 0x01)                      */
12919 #define GPIO_PADREGN_PAD53PULL_Pos        (8UL)                     /*!< PAD53PULL (Bit 8)                                     */
12920 #define GPIO_PADREGN_PAD53PULL_Msk        (0x100UL)                 /*!< PAD53PULL (Bitfield-Mask: 0x01)                       */
12921 #define GPIO_PADREGN_PAD52FNCSEL_Pos      (3UL)                     /*!< PAD52FNCSEL (Bit 3)                                   */
12922 #define GPIO_PADREGN_PAD52FNCSEL_Msk      (0x38UL)                  /*!< PAD52FNCSEL (Bitfield-Mask: 0x07)                     */
12923 #define GPIO_PADREGN_PAD52STRNG_Pos       (2UL)                     /*!< PAD52STRNG (Bit 2)                                    */
12924 #define GPIO_PADREGN_PAD52STRNG_Msk       (0x4UL)                   /*!< PAD52STRNG (Bitfield-Mask: 0x01)                      */
12925 #define GPIO_PADREGN_PAD52INPEN_Pos       (1UL)                     /*!< PAD52INPEN (Bit 1)                                    */
12926 #define GPIO_PADREGN_PAD52INPEN_Msk       (0x2UL)                   /*!< PAD52INPEN (Bitfield-Mask: 0x01)                      */
12927 #define GPIO_PADREGN_PAD52PULL_Pos        (0UL)                     /*!< PAD52PULL (Bit 0)                                     */
12928 #define GPIO_PADREGN_PAD52PULL_Msk        (0x1UL)                   /*!< PAD52PULL (Bitfield-Mask: 0x01)                       */
12929 /* ========================================================  PADREGO  ======================================================== */
12930 #define GPIO_PADREGO_PAD59FNCSEL_Pos      (27UL)                    /*!< PAD59FNCSEL (Bit 27)                                  */
12931 #define GPIO_PADREGO_PAD59FNCSEL_Msk      (0x38000000UL)            /*!< PAD59FNCSEL (Bitfield-Mask: 0x07)                     */
12932 #define GPIO_PADREGO_PAD59STRNG_Pos       (26UL)                    /*!< PAD59STRNG (Bit 26)                                   */
12933 #define GPIO_PADREGO_PAD59STRNG_Msk       (0x4000000UL)             /*!< PAD59STRNG (Bitfield-Mask: 0x01)                      */
12934 #define GPIO_PADREGO_PAD59INPEN_Pos       (25UL)                    /*!< PAD59INPEN (Bit 25)                                   */
12935 #define GPIO_PADREGO_PAD59INPEN_Msk       (0x2000000UL)             /*!< PAD59INPEN (Bitfield-Mask: 0x01)                      */
12936 #define GPIO_PADREGO_PAD59PULL_Pos        (24UL)                    /*!< PAD59PULL (Bit 24)                                    */
12937 #define GPIO_PADREGO_PAD59PULL_Msk        (0x1000000UL)             /*!< PAD59PULL (Bitfield-Mask: 0x01)                       */
12938 #define GPIO_PADREGO_PAD58FNCSEL_Pos      (19UL)                    /*!< PAD58FNCSEL (Bit 19)                                  */
12939 #define GPIO_PADREGO_PAD58FNCSEL_Msk      (0x380000UL)              /*!< PAD58FNCSEL (Bitfield-Mask: 0x07)                     */
12940 #define GPIO_PADREGO_PAD58STRNG_Pos       (18UL)                    /*!< PAD58STRNG (Bit 18)                                   */
12941 #define GPIO_PADREGO_PAD58STRNG_Msk       (0x40000UL)               /*!< PAD58STRNG (Bitfield-Mask: 0x01)                      */
12942 #define GPIO_PADREGO_PAD58INPEN_Pos       (17UL)                    /*!< PAD58INPEN (Bit 17)                                   */
12943 #define GPIO_PADREGO_PAD58INPEN_Msk       (0x20000UL)               /*!< PAD58INPEN (Bitfield-Mask: 0x01)                      */
12944 #define GPIO_PADREGO_PAD58PULL_Pos        (16UL)                    /*!< PAD58PULL (Bit 16)                                    */
12945 #define GPIO_PADREGO_PAD58PULL_Msk        (0x10000UL)               /*!< PAD58PULL (Bitfield-Mask: 0x01)                       */
12946 #define GPIO_PADREGO_PAD57FNCSEL_Pos      (11UL)                    /*!< PAD57FNCSEL (Bit 11)                                  */
12947 #define GPIO_PADREGO_PAD57FNCSEL_Msk      (0x3800UL)                /*!< PAD57FNCSEL (Bitfield-Mask: 0x07)                     */
12948 #define GPIO_PADREGO_PAD57STRNG_Pos       (10UL)                    /*!< PAD57STRNG (Bit 10)                                   */
12949 #define GPIO_PADREGO_PAD57STRNG_Msk       (0x400UL)                 /*!< PAD57STRNG (Bitfield-Mask: 0x01)                      */
12950 #define GPIO_PADREGO_PAD57INPEN_Pos       (9UL)                     /*!< PAD57INPEN (Bit 9)                                    */
12951 #define GPIO_PADREGO_PAD57INPEN_Msk       (0x200UL)                 /*!< PAD57INPEN (Bitfield-Mask: 0x01)                      */
12952 #define GPIO_PADREGO_PAD57PULL_Pos        (8UL)                     /*!< PAD57PULL (Bit 8)                                     */
12953 #define GPIO_PADREGO_PAD57PULL_Msk        (0x100UL)                 /*!< PAD57PULL (Bitfield-Mask: 0x01)                       */
12954 #define GPIO_PADREGO_PAD56FNCSEL_Pos      (3UL)                     /*!< PAD56FNCSEL (Bit 3)                                   */
12955 #define GPIO_PADREGO_PAD56FNCSEL_Msk      (0x38UL)                  /*!< PAD56FNCSEL (Bitfield-Mask: 0x07)                     */
12956 #define GPIO_PADREGO_PAD56STRNG_Pos       (2UL)                     /*!< PAD56STRNG (Bit 2)                                    */
12957 #define GPIO_PADREGO_PAD56STRNG_Msk       (0x4UL)                   /*!< PAD56STRNG (Bitfield-Mask: 0x01)                      */
12958 #define GPIO_PADREGO_PAD56INPEN_Pos       (1UL)                     /*!< PAD56INPEN (Bit 1)                                    */
12959 #define GPIO_PADREGO_PAD56INPEN_Msk       (0x2UL)                   /*!< PAD56INPEN (Bitfield-Mask: 0x01)                      */
12960 #define GPIO_PADREGO_PAD56PULL_Pos        (0UL)                     /*!< PAD56PULL (Bit 0)                                     */
12961 #define GPIO_PADREGO_PAD56PULL_Msk        (0x1UL)                   /*!< PAD56PULL (Bitfield-Mask: 0x01)                       */
12962 /* ========================================================  PADREGP  ======================================================== */
12963 #define GPIO_PADREGP_PAD63FNCSEL_Pos      (27UL)                    /*!< PAD63FNCSEL (Bit 27)                                  */
12964 #define GPIO_PADREGP_PAD63FNCSEL_Msk      (0x38000000UL)            /*!< PAD63FNCSEL (Bitfield-Mask: 0x07)                     */
12965 #define GPIO_PADREGP_PAD63STRNG_Pos       (26UL)                    /*!< PAD63STRNG (Bit 26)                                   */
12966 #define GPIO_PADREGP_PAD63STRNG_Msk       (0x4000000UL)             /*!< PAD63STRNG (Bitfield-Mask: 0x01)                      */
12967 #define GPIO_PADREGP_PAD63INPEN_Pos       (25UL)                    /*!< PAD63INPEN (Bit 25)                                   */
12968 #define GPIO_PADREGP_PAD63INPEN_Msk       (0x2000000UL)             /*!< PAD63INPEN (Bitfield-Mask: 0x01)                      */
12969 #define GPIO_PADREGP_PAD63PULL_Pos        (24UL)                    /*!< PAD63PULL (Bit 24)                                    */
12970 #define GPIO_PADREGP_PAD63PULL_Msk        (0x1000000UL)             /*!< PAD63PULL (Bitfield-Mask: 0x01)                       */
12971 #define GPIO_PADREGP_PAD62FNCSEL_Pos      (19UL)                    /*!< PAD62FNCSEL (Bit 19)                                  */
12972 #define GPIO_PADREGP_PAD62FNCSEL_Msk      (0x380000UL)              /*!< PAD62FNCSEL (Bitfield-Mask: 0x07)                     */
12973 #define GPIO_PADREGP_PAD62STRNG_Pos       (18UL)                    /*!< PAD62STRNG (Bit 18)                                   */
12974 #define GPIO_PADREGP_PAD62STRNG_Msk       (0x40000UL)               /*!< PAD62STRNG (Bitfield-Mask: 0x01)                      */
12975 #define GPIO_PADREGP_PAD62INPEN_Pos       (17UL)                    /*!< PAD62INPEN (Bit 17)                                   */
12976 #define GPIO_PADREGP_PAD62INPEN_Msk       (0x20000UL)               /*!< PAD62INPEN (Bitfield-Mask: 0x01)                      */
12977 #define GPIO_PADREGP_PAD62PULL_Pos        (16UL)                    /*!< PAD62PULL (Bit 16)                                    */
12978 #define GPIO_PADREGP_PAD62PULL_Msk        (0x10000UL)               /*!< PAD62PULL (Bitfield-Mask: 0x01)                       */
12979 #define GPIO_PADREGP_PAD61FNCSEL_Pos      (11UL)                    /*!< PAD61FNCSEL (Bit 11)                                  */
12980 #define GPIO_PADREGP_PAD61FNCSEL_Msk      (0x3800UL)                /*!< PAD61FNCSEL (Bitfield-Mask: 0x07)                     */
12981 #define GPIO_PADREGP_PAD61STRNG_Pos       (10UL)                    /*!< PAD61STRNG (Bit 10)                                   */
12982 #define GPIO_PADREGP_PAD61STRNG_Msk       (0x400UL)                 /*!< PAD61STRNG (Bitfield-Mask: 0x01)                      */
12983 #define GPIO_PADREGP_PAD61INPEN_Pos       (9UL)                     /*!< PAD61INPEN (Bit 9)                                    */
12984 #define GPIO_PADREGP_PAD61INPEN_Msk       (0x200UL)                 /*!< PAD61INPEN (Bitfield-Mask: 0x01)                      */
12985 #define GPIO_PADREGP_PAD61PULL_Pos        (8UL)                     /*!< PAD61PULL (Bit 8)                                     */
12986 #define GPIO_PADREGP_PAD61PULL_Msk        (0x100UL)                 /*!< PAD61PULL (Bitfield-Mask: 0x01)                       */
12987 #define GPIO_PADREGP_PAD60FNCSEL_Pos      (3UL)                     /*!< PAD60FNCSEL (Bit 3)                                   */
12988 #define GPIO_PADREGP_PAD60FNCSEL_Msk      (0x38UL)                  /*!< PAD60FNCSEL (Bitfield-Mask: 0x07)                     */
12989 #define GPIO_PADREGP_PAD60STRNG_Pos       (2UL)                     /*!< PAD60STRNG (Bit 2)                                    */
12990 #define GPIO_PADREGP_PAD60STRNG_Msk       (0x4UL)                   /*!< PAD60STRNG (Bitfield-Mask: 0x01)                      */
12991 #define GPIO_PADREGP_PAD60INPEN_Pos       (1UL)                     /*!< PAD60INPEN (Bit 1)                                    */
12992 #define GPIO_PADREGP_PAD60INPEN_Msk       (0x2UL)                   /*!< PAD60INPEN (Bitfield-Mask: 0x01)                      */
12993 #define GPIO_PADREGP_PAD60PULL_Pos        (0UL)                     /*!< PAD60PULL (Bit 0)                                     */
12994 #define GPIO_PADREGP_PAD60PULL_Msk        (0x1UL)                   /*!< PAD60PULL (Bitfield-Mask: 0x01)                       */
12995 /* ========================================================  PADREGQ  ======================================================== */
12996 #define GPIO_PADREGQ_PAD67FNCSEL_Pos      (27UL)                    /*!< PAD67FNCSEL (Bit 27)                                  */
12997 #define GPIO_PADREGQ_PAD67FNCSEL_Msk      (0x38000000UL)            /*!< PAD67FNCSEL (Bitfield-Mask: 0x07)                     */
12998 #define GPIO_PADREGQ_PAD67STRNG_Pos       (26UL)                    /*!< PAD67STRNG (Bit 26)                                   */
12999 #define GPIO_PADREGQ_PAD67STRNG_Msk       (0x4000000UL)             /*!< PAD67STRNG (Bitfield-Mask: 0x01)                      */
13000 #define GPIO_PADREGQ_PAD67INPEN_Pos       (25UL)                    /*!< PAD67INPEN (Bit 25)                                   */
13001 #define GPIO_PADREGQ_PAD67INPEN_Msk       (0x2000000UL)             /*!< PAD67INPEN (Bitfield-Mask: 0x01)                      */
13002 #define GPIO_PADREGQ_PAD67PULL_Pos        (24UL)                    /*!< PAD67PULL (Bit 24)                                    */
13003 #define GPIO_PADREGQ_PAD67PULL_Msk        (0x1000000UL)             /*!< PAD67PULL (Bitfield-Mask: 0x01)                       */
13004 #define GPIO_PADREGQ_PAD66FNCSEL_Pos      (19UL)                    /*!< PAD66FNCSEL (Bit 19)                                  */
13005 #define GPIO_PADREGQ_PAD66FNCSEL_Msk      (0x380000UL)              /*!< PAD66FNCSEL (Bitfield-Mask: 0x07)                     */
13006 #define GPIO_PADREGQ_PAD66STRNG_Pos       (18UL)                    /*!< PAD66STRNG (Bit 18)                                   */
13007 #define GPIO_PADREGQ_PAD66STRNG_Msk       (0x40000UL)               /*!< PAD66STRNG (Bitfield-Mask: 0x01)                      */
13008 #define GPIO_PADREGQ_PAD66INPEN_Pos       (17UL)                    /*!< PAD66INPEN (Bit 17)                                   */
13009 #define GPIO_PADREGQ_PAD66INPEN_Msk       (0x20000UL)               /*!< PAD66INPEN (Bitfield-Mask: 0x01)                      */
13010 #define GPIO_PADREGQ_PAD66PULL_Pos        (16UL)                    /*!< PAD66PULL (Bit 16)                                    */
13011 #define GPIO_PADREGQ_PAD66PULL_Msk        (0x10000UL)               /*!< PAD66PULL (Bitfield-Mask: 0x01)                       */
13012 #define GPIO_PADREGQ_PAD65FNCSEL_Pos      (11UL)                    /*!< PAD65FNCSEL (Bit 11)                                  */
13013 #define GPIO_PADREGQ_PAD65FNCSEL_Msk      (0x3800UL)                /*!< PAD65FNCSEL (Bitfield-Mask: 0x07)                     */
13014 #define GPIO_PADREGQ_PAD65STRNG_Pos       (10UL)                    /*!< PAD65STRNG (Bit 10)                                   */
13015 #define GPIO_PADREGQ_PAD65STRNG_Msk       (0x400UL)                 /*!< PAD65STRNG (Bitfield-Mask: 0x01)                      */
13016 #define GPIO_PADREGQ_PAD65INPEN_Pos       (9UL)                     /*!< PAD65INPEN (Bit 9)                                    */
13017 #define GPIO_PADREGQ_PAD65INPEN_Msk       (0x200UL)                 /*!< PAD65INPEN (Bitfield-Mask: 0x01)                      */
13018 #define GPIO_PADREGQ_PAD65PULL_Pos        (8UL)                     /*!< PAD65PULL (Bit 8)                                     */
13019 #define GPIO_PADREGQ_PAD65PULL_Msk        (0x100UL)                 /*!< PAD65PULL (Bitfield-Mask: 0x01)                       */
13020 #define GPIO_PADREGQ_PAD64FNCSEL_Pos      (3UL)                     /*!< PAD64FNCSEL (Bit 3)                                   */
13021 #define GPIO_PADREGQ_PAD64FNCSEL_Msk      (0x38UL)                  /*!< PAD64FNCSEL (Bitfield-Mask: 0x07)                     */
13022 #define GPIO_PADREGQ_PAD64STRNG_Pos       (2UL)                     /*!< PAD64STRNG (Bit 2)                                    */
13023 #define GPIO_PADREGQ_PAD64STRNG_Msk       (0x4UL)                   /*!< PAD64STRNG (Bitfield-Mask: 0x01)                      */
13024 #define GPIO_PADREGQ_PAD64INPEN_Pos       (1UL)                     /*!< PAD64INPEN (Bit 1)                                    */
13025 #define GPIO_PADREGQ_PAD64INPEN_Msk       (0x2UL)                   /*!< PAD64INPEN (Bitfield-Mask: 0x01)                      */
13026 #define GPIO_PADREGQ_PAD64PULL_Pos        (0UL)                     /*!< PAD64PULL (Bit 0)                                     */
13027 #define GPIO_PADREGQ_PAD64PULL_Msk        (0x1UL)                   /*!< PAD64PULL (Bitfield-Mask: 0x01)                       */
13028 /* ========================================================  PADREGR  ======================================================== */
13029 #define GPIO_PADREGR_PAD71FNCSEL_Pos      (27UL)                    /*!< PAD71FNCSEL (Bit 27)                                  */
13030 #define GPIO_PADREGR_PAD71FNCSEL_Msk      (0x38000000UL)            /*!< PAD71FNCSEL (Bitfield-Mask: 0x07)                     */
13031 #define GPIO_PADREGR_PAD71STRNG_Pos       (26UL)                    /*!< PAD71STRNG (Bit 26)                                   */
13032 #define GPIO_PADREGR_PAD71STRNG_Msk       (0x4000000UL)             /*!< PAD71STRNG (Bitfield-Mask: 0x01)                      */
13033 #define GPIO_PADREGR_PAD71INPEN_Pos       (25UL)                    /*!< PAD71INPEN (Bit 25)                                   */
13034 #define GPIO_PADREGR_PAD71INPEN_Msk       (0x2000000UL)             /*!< PAD71INPEN (Bitfield-Mask: 0x01)                      */
13035 #define GPIO_PADREGR_PAD71PULL_Pos        (24UL)                    /*!< PAD71PULL (Bit 24)                                    */
13036 #define GPIO_PADREGR_PAD71PULL_Msk        (0x1000000UL)             /*!< PAD71PULL (Bitfield-Mask: 0x01)                       */
13037 #define GPIO_PADREGR_PAD70FNCSEL_Pos      (19UL)                    /*!< PAD70FNCSEL (Bit 19)                                  */
13038 #define GPIO_PADREGR_PAD70FNCSEL_Msk      (0x380000UL)              /*!< PAD70FNCSEL (Bitfield-Mask: 0x07)                     */
13039 #define GPIO_PADREGR_PAD70STRNG_Pos       (18UL)                    /*!< PAD70STRNG (Bit 18)                                   */
13040 #define GPIO_PADREGR_PAD70STRNG_Msk       (0x40000UL)               /*!< PAD70STRNG (Bitfield-Mask: 0x01)                      */
13041 #define GPIO_PADREGR_PAD70INPEN_Pos       (17UL)                    /*!< PAD70INPEN (Bit 17)                                   */
13042 #define GPIO_PADREGR_PAD70INPEN_Msk       (0x20000UL)               /*!< PAD70INPEN (Bitfield-Mask: 0x01)                      */
13043 #define GPIO_PADREGR_PAD70PULL_Pos        (16UL)                    /*!< PAD70PULL (Bit 16)                                    */
13044 #define GPIO_PADREGR_PAD70PULL_Msk        (0x10000UL)               /*!< PAD70PULL (Bitfield-Mask: 0x01)                       */
13045 #define GPIO_PADREGR_PAD69FNCSEL_Pos      (11UL)                    /*!< PAD69FNCSEL (Bit 11)                                  */
13046 #define GPIO_PADREGR_PAD69FNCSEL_Msk      (0x3800UL)                /*!< PAD69FNCSEL (Bitfield-Mask: 0x07)                     */
13047 #define GPIO_PADREGR_PAD69STRNG_Pos       (10UL)                    /*!< PAD69STRNG (Bit 10)                                   */
13048 #define GPIO_PADREGR_PAD69STRNG_Msk       (0x400UL)                 /*!< PAD69STRNG (Bitfield-Mask: 0x01)                      */
13049 #define GPIO_PADREGR_PAD69INPEN_Pos       (9UL)                     /*!< PAD69INPEN (Bit 9)                                    */
13050 #define GPIO_PADREGR_PAD69INPEN_Msk       (0x200UL)                 /*!< PAD69INPEN (Bitfield-Mask: 0x01)                      */
13051 #define GPIO_PADREGR_PAD69PULL_Pos        (8UL)                     /*!< PAD69PULL (Bit 8)                                     */
13052 #define GPIO_PADREGR_PAD69PULL_Msk        (0x100UL)                 /*!< PAD69PULL (Bitfield-Mask: 0x01)                       */
13053 #define GPIO_PADREGR_PAD68FNCSEL_Pos      (3UL)                     /*!< PAD68FNCSEL (Bit 3)                                   */
13054 #define GPIO_PADREGR_PAD68FNCSEL_Msk      (0x38UL)                  /*!< PAD68FNCSEL (Bitfield-Mask: 0x07)                     */
13055 #define GPIO_PADREGR_PAD68STRNG_Pos       (2UL)                     /*!< PAD68STRNG (Bit 2)                                    */
13056 #define GPIO_PADREGR_PAD68STRNG_Msk       (0x4UL)                   /*!< PAD68STRNG (Bitfield-Mask: 0x01)                      */
13057 #define GPIO_PADREGR_PAD68INPEN_Pos       (1UL)                     /*!< PAD68INPEN (Bit 1)                                    */
13058 #define GPIO_PADREGR_PAD68INPEN_Msk       (0x2UL)                   /*!< PAD68INPEN (Bitfield-Mask: 0x01)                      */
13059 #define GPIO_PADREGR_PAD68PULL_Pos        (0UL)                     /*!< PAD68PULL (Bit 0)                                     */
13060 #define GPIO_PADREGR_PAD68PULL_Msk        (0x1UL)                   /*!< PAD68PULL (Bitfield-Mask: 0x01)                       */
13061 /* ========================================================  PADREGS  ======================================================== */
13062 #define GPIO_PADREGS_PAD73FNCSEL_Pos      (11UL)                    /*!< PAD73FNCSEL (Bit 11)                                  */
13063 #define GPIO_PADREGS_PAD73FNCSEL_Msk      (0x3800UL)                /*!< PAD73FNCSEL (Bitfield-Mask: 0x07)                     */
13064 #define GPIO_PADREGS_PAD73STRNG_Pos       (10UL)                    /*!< PAD73STRNG (Bit 10)                                   */
13065 #define GPIO_PADREGS_PAD73STRNG_Msk       (0x400UL)                 /*!< PAD73STRNG (Bitfield-Mask: 0x01)                      */
13066 #define GPIO_PADREGS_PAD73INPEN_Pos       (9UL)                     /*!< PAD73INPEN (Bit 9)                                    */
13067 #define GPIO_PADREGS_PAD73INPEN_Msk       (0x200UL)                 /*!< PAD73INPEN (Bitfield-Mask: 0x01)                      */
13068 #define GPIO_PADREGS_PAD73PULL_Pos        (8UL)                     /*!< PAD73PULL (Bit 8)                                     */
13069 #define GPIO_PADREGS_PAD73PULL_Msk        (0x100UL)                 /*!< PAD73PULL (Bitfield-Mask: 0x01)                       */
13070 #define GPIO_PADREGS_PAD72FNCSEL_Pos      (3UL)                     /*!< PAD72FNCSEL (Bit 3)                                   */
13071 #define GPIO_PADREGS_PAD72FNCSEL_Msk      (0x38UL)                  /*!< PAD72FNCSEL (Bitfield-Mask: 0x07)                     */
13072 #define GPIO_PADREGS_PAD72STRNG_Pos       (2UL)                     /*!< PAD72STRNG (Bit 2)                                    */
13073 #define GPIO_PADREGS_PAD72STRNG_Msk       (0x4UL)                   /*!< PAD72STRNG (Bitfield-Mask: 0x01)                      */
13074 #define GPIO_PADREGS_PAD72INPEN_Pos       (1UL)                     /*!< PAD72INPEN (Bit 1)                                    */
13075 #define GPIO_PADREGS_PAD72INPEN_Msk       (0x2UL)                   /*!< PAD72INPEN (Bitfield-Mask: 0x01)                      */
13076 #define GPIO_PADREGS_PAD72PULL_Pos        (0UL)                     /*!< PAD72PULL (Bit 0)                                     */
13077 #define GPIO_PADREGS_PAD72PULL_Msk        (0x1UL)                   /*!< PAD72PULL (Bitfield-Mask: 0x01)                       */
13078 /* =========================================================  CFGA  ========================================================== */
13079 #define GPIO_CFGA_GPIO7INTD_Pos           (31UL)                    /*!< GPIO7INTD (Bit 31)                                    */
13080 #define GPIO_CFGA_GPIO7INTD_Msk           (0x80000000UL)            /*!< GPIO7INTD (Bitfield-Mask: 0x01)                       */
13081 #define GPIO_CFGA_GPIO7OUTCFG_Pos         (29UL)                    /*!< GPIO7OUTCFG (Bit 29)                                  */
13082 #define GPIO_CFGA_GPIO7OUTCFG_Msk         (0x60000000UL)            /*!< GPIO7OUTCFG (Bitfield-Mask: 0x03)                     */
13083 #define GPIO_CFGA_GPIO7INCFG_Pos          (28UL)                    /*!< GPIO7INCFG (Bit 28)                                   */
13084 #define GPIO_CFGA_GPIO7INCFG_Msk          (0x10000000UL)            /*!< GPIO7INCFG (Bitfield-Mask: 0x01)                      */
13085 #define GPIO_CFGA_GPIO6INTD_Pos           (27UL)                    /*!< GPIO6INTD (Bit 27)                                    */
13086 #define GPIO_CFGA_GPIO6INTD_Msk           (0x8000000UL)             /*!< GPIO6INTD (Bitfield-Mask: 0x01)                       */
13087 #define GPIO_CFGA_GPIO6OUTCFG_Pos         (25UL)                    /*!< GPIO6OUTCFG (Bit 25)                                  */
13088 #define GPIO_CFGA_GPIO6OUTCFG_Msk         (0x6000000UL)             /*!< GPIO6OUTCFG (Bitfield-Mask: 0x03)                     */
13089 #define GPIO_CFGA_GPIO6INCFG_Pos          (24UL)                    /*!< GPIO6INCFG (Bit 24)                                   */
13090 #define GPIO_CFGA_GPIO6INCFG_Msk          (0x1000000UL)             /*!< GPIO6INCFG (Bitfield-Mask: 0x01)                      */
13091 #define GPIO_CFGA_GPIO5INTD_Pos           (23UL)                    /*!< GPIO5INTD (Bit 23)                                    */
13092 #define GPIO_CFGA_GPIO5INTD_Msk           (0x800000UL)              /*!< GPIO5INTD (Bitfield-Mask: 0x01)                       */
13093 #define GPIO_CFGA_GPIO5OUTCFG_Pos         (21UL)                    /*!< GPIO5OUTCFG (Bit 21)                                  */
13094 #define GPIO_CFGA_GPIO5OUTCFG_Msk         (0x600000UL)              /*!< GPIO5OUTCFG (Bitfield-Mask: 0x03)                     */
13095 #define GPIO_CFGA_GPIO5INCFG_Pos          (20UL)                    /*!< GPIO5INCFG (Bit 20)                                   */
13096 #define GPIO_CFGA_GPIO5INCFG_Msk          (0x100000UL)              /*!< GPIO5INCFG (Bitfield-Mask: 0x01)                      */
13097 #define GPIO_CFGA_GPIO4INTD_Pos           (19UL)                    /*!< GPIO4INTD (Bit 19)                                    */
13098 #define GPIO_CFGA_GPIO4INTD_Msk           (0x80000UL)               /*!< GPIO4INTD (Bitfield-Mask: 0x01)                       */
13099 #define GPIO_CFGA_GPIO4OUTCFG_Pos         (17UL)                    /*!< GPIO4OUTCFG (Bit 17)                                  */
13100 #define GPIO_CFGA_GPIO4OUTCFG_Msk         (0x60000UL)               /*!< GPIO4OUTCFG (Bitfield-Mask: 0x03)                     */
13101 #define GPIO_CFGA_GPIO4INCFG_Pos          (16UL)                    /*!< GPIO4INCFG (Bit 16)                                   */
13102 #define GPIO_CFGA_GPIO4INCFG_Msk          (0x10000UL)               /*!< GPIO4INCFG (Bitfield-Mask: 0x01)                      */
13103 #define GPIO_CFGA_GPIO3INTD_Pos           (15UL)                    /*!< GPIO3INTD (Bit 15)                                    */
13104 #define GPIO_CFGA_GPIO3INTD_Msk           (0x8000UL)                /*!< GPIO3INTD (Bitfield-Mask: 0x01)                       */
13105 #define GPIO_CFGA_GPIO3OUTCFG_Pos         (13UL)                    /*!< GPIO3OUTCFG (Bit 13)                                  */
13106 #define GPIO_CFGA_GPIO3OUTCFG_Msk         (0x6000UL)                /*!< GPIO3OUTCFG (Bitfield-Mask: 0x03)                     */
13107 #define GPIO_CFGA_GPIO3INCFG_Pos          (12UL)                    /*!< GPIO3INCFG (Bit 12)                                   */
13108 #define GPIO_CFGA_GPIO3INCFG_Msk          (0x1000UL)                /*!< GPIO3INCFG (Bitfield-Mask: 0x01)                      */
13109 #define GPIO_CFGA_GPIO2INTD_Pos           (11UL)                    /*!< GPIO2INTD (Bit 11)                                    */
13110 #define GPIO_CFGA_GPIO2INTD_Msk           (0x800UL)                 /*!< GPIO2INTD (Bitfield-Mask: 0x01)                       */
13111 #define GPIO_CFGA_GPIO2OUTCFG_Pos         (9UL)                     /*!< GPIO2OUTCFG (Bit 9)                                   */
13112 #define GPIO_CFGA_GPIO2OUTCFG_Msk         (0x600UL)                 /*!< GPIO2OUTCFG (Bitfield-Mask: 0x03)                     */
13113 #define GPIO_CFGA_GPIO2INCFG_Pos          (8UL)                     /*!< GPIO2INCFG (Bit 8)                                    */
13114 #define GPIO_CFGA_GPIO2INCFG_Msk          (0x100UL)                 /*!< GPIO2INCFG (Bitfield-Mask: 0x01)                      */
13115 #define GPIO_CFGA_GPIO1INTD_Pos           (7UL)                     /*!< GPIO1INTD (Bit 7)                                     */
13116 #define GPIO_CFGA_GPIO1INTD_Msk           (0x80UL)                  /*!< GPIO1INTD (Bitfield-Mask: 0x01)                       */
13117 #define GPIO_CFGA_GPIO1OUTCFG_Pos         (5UL)                     /*!< GPIO1OUTCFG (Bit 5)                                   */
13118 #define GPIO_CFGA_GPIO1OUTCFG_Msk         (0x60UL)                  /*!< GPIO1OUTCFG (Bitfield-Mask: 0x03)                     */
13119 #define GPIO_CFGA_GPIO1INCFG_Pos          (4UL)                     /*!< GPIO1INCFG (Bit 4)                                    */
13120 #define GPIO_CFGA_GPIO1INCFG_Msk          (0x10UL)                  /*!< GPIO1INCFG (Bitfield-Mask: 0x01)                      */
13121 #define GPIO_CFGA_GPIO0INTD_Pos           (3UL)                     /*!< GPIO0INTD (Bit 3)                                     */
13122 #define GPIO_CFGA_GPIO0INTD_Msk           (0x8UL)                   /*!< GPIO0INTD (Bitfield-Mask: 0x01)                       */
13123 #define GPIO_CFGA_GPIO0OUTCFG_Pos         (1UL)                     /*!< GPIO0OUTCFG (Bit 1)                                   */
13124 #define GPIO_CFGA_GPIO0OUTCFG_Msk         (0x6UL)                   /*!< GPIO0OUTCFG (Bitfield-Mask: 0x03)                     */
13125 #define GPIO_CFGA_GPIO0INCFG_Pos          (0UL)                     /*!< GPIO0INCFG (Bit 0)                                    */
13126 #define GPIO_CFGA_GPIO0INCFG_Msk          (0x1UL)                   /*!< GPIO0INCFG (Bitfield-Mask: 0x01)                      */
13127 /* =========================================================  CFGB  ========================================================== */
13128 #define GPIO_CFGB_GPIO15INTD_Pos          (31UL)                    /*!< GPIO15INTD (Bit 31)                                   */
13129 #define GPIO_CFGB_GPIO15INTD_Msk          (0x80000000UL)            /*!< GPIO15INTD (Bitfield-Mask: 0x01)                      */
13130 #define GPIO_CFGB_GPIO15OUTCFG_Pos        (29UL)                    /*!< GPIO15OUTCFG (Bit 29)                                 */
13131 #define GPIO_CFGB_GPIO15OUTCFG_Msk        (0x60000000UL)            /*!< GPIO15OUTCFG (Bitfield-Mask: 0x03)                    */
13132 #define GPIO_CFGB_GPIO15INCFG_Pos         (28UL)                    /*!< GPIO15INCFG (Bit 28)                                  */
13133 #define GPIO_CFGB_GPIO15INCFG_Msk         (0x10000000UL)            /*!< GPIO15INCFG (Bitfield-Mask: 0x01)                     */
13134 #define GPIO_CFGB_GPIO14INTD_Pos          (27UL)                    /*!< GPIO14INTD (Bit 27)                                   */
13135 #define GPIO_CFGB_GPIO14INTD_Msk          (0x8000000UL)             /*!< GPIO14INTD (Bitfield-Mask: 0x01)                      */
13136 #define GPIO_CFGB_GPIO14OUTCFG_Pos        (25UL)                    /*!< GPIO14OUTCFG (Bit 25)                                 */
13137 #define GPIO_CFGB_GPIO14OUTCFG_Msk        (0x6000000UL)             /*!< GPIO14OUTCFG (Bitfield-Mask: 0x03)                    */
13138 #define GPIO_CFGB_GPIO14INCFG_Pos         (24UL)                    /*!< GPIO14INCFG (Bit 24)                                  */
13139 #define GPIO_CFGB_GPIO14INCFG_Msk         (0x1000000UL)             /*!< GPIO14INCFG (Bitfield-Mask: 0x01)                     */
13140 #define GPIO_CFGB_GPIO13INTD_Pos          (23UL)                    /*!< GPIO13INTD (Bit 23)                                   */
13141 #define GPIO_CFGB_GPIO13INTD_Msk          (0x800000UL)              /*!< GPIO13INTD (Bitfield-Mask: 0x01)                      */
13142 #define GPIO_CFGB_GPIO13OUTCFG_Pos        (21UL)                    /*!< GPIO13OUTCFG (Bit 21)                                 */
13143 #define GPIO_CFGB_GPIO13OUTCFG_Msk        (0x600000UL)              /*!< GPIO13OUTCFG (Bitfield-Mask: 0x03)                    */
13144 #define GPIO_CFGB_GPIO13INCFG_Pos         (20UL)                    /*!< GPIO13INCFG (Bit 20)                                  */
13145 #define GPIO_CFGB_GPIO13INCFG_Msk         (0x100000UL)              /*!< GPIO13INCFG (Bitfield-Mask: 0x01)                     */
13146 #define GPIO_CFGB_GPIO12INTD_Pos          (19UL)                    /*!< GPIO12INTD (Bit 19)                                   */
13147 #define GPIO_CFGB_GPIO12INTD_Msk          (0x80000UL)               /*!< GPIO12INTD (Bitfield-Mask: 0x01)                      */
13148 #define GPIO_CFGB_GPIO12OUTCFG_Pos        (17UL)                    /*!< GPIO12OUTCFG (Bit 17)                                 */
13149 #define GPIO_CFGB_GPIO12OUTCFG_Msk        (0x60000UL)               /*!< GPIO12OUTCFG (Bitfield-Mask: 0x03)                    */
13150 #define GPIO_CFGB_GPIO12INCFG_Pos         (16UL)                    /*!< GPIO12INCFG (Bit 16)                                  */
13151 #define GPIO_CFGB_GPIO12INCFG_Msk         (0x10000UL)               /*!< GPIO12INCFG (Bitfield-Mask: 0x01)                     */
13152 #define GPIO_CFGB_GPIO11INTD_Pos          (15UL)                    /*!< GPIO11INTD (Bit 15)                                   */
13153 #define GPIO_CFGB_GPIO11INTD_Msk          (0x8000UL)                /*!< GPIO11INTD (Bitfield-Mask: 0x01)                      */
13154 #define GPIO_CFGB_GPIO11OUTCFG_Pos        (13UL)                    /*!< GPIO11OUTCFG (Bit 13)                                 */
13155 #define GPIO_CFGB_GPIO11OUTCFG_Msk        (0x6000UL)                /*!< GPIO11OUTCFG (Bitfield-Mask: 0x03)                    */
13156 #define GPIO_CFGB_GPIO11INCFG_Pos         (12UL)                    /*!< GPIO11INCFG (Bit 12)                                  */
13157 #define GPIO_CFGB_GPIO11INCFG_Msk         (0x1000UL)                /*!< GPIO11INCFG (Bitfield-Mask: 0x01)                     */
13158 #define GPIO_CFGB_GPIO10INTD_Pos          (11UL)                    /*!< GPIO10INTD (Bit 11)                                   */
13159 #define GPIO_CFGB_GPIO10INTD_Msk          (0x800UL)                 /*!< GPIO10INTD (Bitfield-Mask: 0x01)                      */
13160 #define GPIO_CFGB_GPIO10OUTCFG_Pos        (9UL)                     /*!< GPIO10OUTCFG (Bit 9)                                  */
13161 #define GPIO_CFGB_GPIO10OUTCFG_Msk        (0x600UL)                 /*!< GPIO10OUTCFG (Bitfield-Mask: 0x03)                    */
13162 #define GPIO_CFGB_GPIO10INCFG_Pos         (8UL)                     /*!< GPIO10INCFG (Bit 8)                                   */
13163 #define GPIO_CFGB_GPIO10INCFG_Msk         (0x100UL)                 /*!< GPIO10INCFG (Bitfield-Mask: 0x01)                     */
13164 #define GPIO_CFGB_GPIO9INTD_Pos           (7UL)                     /*!< GPIO9INTD (Bit 7)                                     */
13165 #define GPIO_CFGB_GPIO9INTD_Msk           (0x80UL)                  /*!< GPIO9INTD (Bitfield-Mask: 0x01)                       */
13166 #define GPIO_CFGB_GPIO9OUTCFG_Pos         (5UL)                     /*!< GPIO9OUTCFG (Bit 5)                                   */
13167 #define GPIO_CFGB_GPIO9OUTCFG_Msk         (0x60UL)                  /*!< GPIO9OUTCFG (Bitfield-Mask: 0x03)                     */
13168 #define GPIO_CFGB_GPIO9INCFG_Pos          (4UL)                     /*!< GPIO9INCFG (Bit 4)                                    */
13169 #define GPIO_CFGB_GPIO9INCFG_Msk          (0x10UL)                  /*!< GPIO9INCFG (Bitfield-Mask: 0x01)                      */
13170 #define GPIO_CFGB_GPIO8INTD_Pos           (3UL)                     /*!< GPIO8INTD (Bit 3)                                     */
13171 #define GPIO_CFGB_GPIO8INTD_Msk           (0x8UL)                   /*!< GPIO8INTD (Bitfield-Mask: 0x01)                       */
13172 #define GPIO_CFGB_GPIO8OUTCFG_Pos         (1UL)                     /*!< GPIO8OUTCFG (Bit 1)                                   */
13173 #define GPIO_CFGB_GPIO8OUTCFG_Msk         (0x6UL)                   /*!< GPIO8OUTCFG (Bitfield-Mask: 0x03)                     */
13174 #define GPIO_CFGB_GPIO8INCFG_Pos          (0UL)                     /*!< GPIO8INCFG (Bit 0)                                    */
13175 #define GPIO_CFGB_GPIO8INCFG_Msk          (0x1UL)                   /*!< GPIO8INCFG (Bitfield-Mask: 0x01)                      */
13176 /* =========================================================  CFGC  ========================================================== */
13177 #define GPIO_CFGC_GPIO23INTD_Pos          (31UL)                    /*!< GPIO23INTD (Bit 31)                                   */
13178 #define GPIO_CFGC_GPIO23INTD_Msk          (0x80000000UL)            /*!< GPIO23INTD (Bitfield-Mask: 0x01)                      */
13179 #define GPIO_CFGC_GPIO23OUTCFG_Pos        (29UL)                    /*!< GPIO23OUTCFG (Bit 29)                                 */
13180 #define GPIO_CFGC_GPIO23OUTCFG_Msk        (0x60000000UL)            /*!< GPIO23OUTCFG (Bitfield-Mask: 0x03)                    */
13181 #define GPIO_CFGC_GPIO23INCFG_Pos         (28UL)                    /*!< GPIO23INCFG (Bit 28)                                  */
13182 #define GPIO_CFGC_GPIO23INCFG_Msk         (0x10000000UL)            /*!< GPIO23INCFG (Bitfield-Mask: 0x01)                     */
13183 #define GPIO_CFGC_GPIO22INTD_Pos          (27UL)                    /*!< GPIO22INTD (Bit 27)                                   */
13184 #define GPIO_CFGC_GPIO22INTD_Msk          (0x8000000UL)             /*!< GPIO22INTD (Bitfield-Mask: 0x01)                      */
13185 #define GPIO_CFGC_GPIO22OUTCFG_Pos        (25UL)                    /*!< GPIO22OUTCFG (Bit 25)                                 */
13186 #define GPIO_CFGC_GPIO22OUTCFG_Msk        (0x6000000UL)             /*!< GPIO22OUTCFG (Bitfield-Mask: 0x03)                    */
13187 #define GPIO_CFGC_GPIO22INCFG_Pos         (24UL)                    /*!< GPIO22INCFG (Bit 24)                                  */
13188 #define GPIO_CFGC_GPIO22INCFG_Msk         (0x1000000UL)             /*!< GPIO22INCFG (Bitfield-Mask: 0x01)                     */
13189 #define GPIO_CFGC_GPIO21INTD_Pos          (23UL)                    /*!< GPIO21INTD (Bit 23)                                   */
13190 #define GPIO_CFGC_GPIO21INTD_Msk          (0x800000UL)              /*!< GPIO21INTD (Bitfield-Mask: 0x01)                      */
13191 #define GPIO_CFGC_GPIO21OUTCFG_Pos        (21UL)                    /*!< GPIO21OUTCFG (Bit 21)                                 */
13192 #define GPIO_CFGC_GPIO21OUTCFG_Msk        (0x600000UL)              /*!< GPIO21OUTCFG (Bitfield-Mask: 0x03)                    */
13193 #define GPIO_CFGC_GPIO21INCFG_Pos         (20UL)                    /*!< GPIO21INCFG (Bit 20)                                  */
13194 #define GPIO_CFGC_GPIO21INCFG_Msk         (0x100000UL)              /*!< GPIO21INCFG (Bitfield-Mask: 0x01)                     */
13195 #define GPIO_CFGC_GPIO20INTD_Pos          (19UL)                    /*!< GPIO20INTD (Bit 19)                                   */
13196 #define GPIO_CFGC_GPIO20INTD_Msk          (0x80000UL)               /*!< GPIO20INTD (Bitfield-Mask: 0x01)                      */
13197 #define GPIO_CFGC_GPIO20OUTCFG_Pos        (17UL)                    /*!< GPIO20OUTCFG (Bit 17)                                 */
13198 #define GPIO_CFGC_GPIO20OUTCFG_Msk        (0x60000UL)               /*!< GPIO20OUTCFG (Bitfield-Mask: 0x03)                    */
13199 #define GPIO_CFGC_GPIO20INCFG_Pos         (16UL)                    /*!< GPIO20INCFG (Bit 16)                                  */
13200 #define GPIO_CFGC_GPIO20INCFG_Msk         (0x10000UL)               /*!< GPIO20INCFG (Bitfield-Mask: 0x01)                     */
13201 #define GPIO_CFGC_GPIO19INTD_Pos          (15UL)                    /*!< GPIO19INTD (Bit 15)                                   */
13202 #define GPIO_CFGC_GPIO19INTD_Msk          (0x8000UL)                /*!< GPIO19INTD (Bitfield-Mask: 0x01)                      */
13203 #define GPIO_CFGC_GPIO19OUTCFG_Pos        (13UL)                    /*!< GPIO19OUTCFG (Bit 13)                                 */
13204 #define GPIO_CFGC_GPIO19OUTCFG_Msk        (0x6000UL)                /*!< GPIO19OUTCFG (Bitfield-Mask: 0x03)                    */
13205 #define GPIO_CFGC_GPIO19INCFG_Pos         (12UL)                    /*!< GPIO19INCFG (Bit 12)                                  */
13206 #define GPIO_CFGC_GPIO19INCFG_Msk         (0x1000UL)                /*!< GPIO19INCFG (Bitfield-Mask: 0x01)                     */
13207 #define GPIO_CFGC_GPIO18INTD_Pos          (11UL)                    /*!< GPIO18INTD (Bit 11)                                   */
13208 #define GPIO_CFGC_GPIO18INTD_Msk          (0x800UL)                 /*!< GPIO18INTD (Bitfield-Mask: 0x01)                      */
13209 #define GPIO_CFGC_GPIO18OUTCFG_Pos        (9UL)                     /*!< GPIO18OUTCFG (Bit 9)                                  */
13210 #define GPIO_CFGC_GPIO18OUTCFG_Msk        (0x600UL)                 /*!< GPIO18OUTCFG (Bitfield-Mask: 0x03)                    */
13211 #define GPIO_CFGC_GPIO18INCFG_Pos         (8UL)                     /*!< GPIO18INCFG (Bit 8)                                   */
13212 #define GPIO_CFGC_GPIO18INCFG_Msk         (0x100UL)                 /*!< GPIO18INCFG (Bitfield-Mask: 0x01)                     */
13213 #define GPIO_CFGC_GPIO17INTD_Pos          (7UL)                     /*!< GPIO17INTD (Bit 7)                                    */
13214 #define GPIO_CFGC_GPIO17INTD_Msk          (0x80UL)                  /*!< GPIO17INTD (Bitfield-Mask: 0x01)                      */
13215 #define GPIO_CFGC_GPIO17OUTCFG_Pos        (5UL)                     /*!< GPIO17OUTCFG (Bit 5)                                  */
13216 #define GPIO_CFGC_GPIO17OUTCFG_Msk        (0x60UL)                  /*!< GPIO17OUTCFG (Bitfield-Mask: 0x03)                    */
13217 #define GPIO_CFGC_GPIO17INCFG_Pos         (4UL)                     /*!< GPIO17INCFG (Bit 4)                                   */
13218 #define GPIO_CFGC_GPIO17INCFG_Msk         (0x10UL)                  /*!< GPIO17INCFG (Bitfield-Mask: 0x01)                     */
13219 #define GPIO_CFGC_GPIO16INTD_Pos          (3UL)                     /*!< GPIO16INTD (Bit 3)                                    */
13220 #define GPIO_CFGC_GPIO16INTD_Msk          (0x8UL)                   /*!< GPIO16INTD (Bitfield-Mask: 0x01)                      */
13221 #define GPIO_CFGC_GPIO16OUTCFG_Pos        (1UL)                     /*!< GPIO16OUTCFG (Bit 1)                                  */
13222 #define GPIO_CFGC_GPIO16OUTCFG_Msk        (0x6UL)                   /*!< GPIO16OUTCFG (Bitfield-Mask: 0x03)                    */
13223 #define GPIO_CFGC_GPIO16INCFG_Pos         (0UL)                     /*!< GPIO16INCFG (Bit 0)                                   */
13224 #define GPIO_CFGC_GPIO16INCFG_Msk         (0x1UL)                   /*!< GPIO16INCFG (Bitfield-Mask: 0x01)                     */
13225 /* =========================================================  CFGD  ========================================================== */
13226 #define GPIO_CFGD_GPIO31INTD_Pos          (31UL)                    /*!< GPIO31INTD (Bit 31)                                   */
13227 #define GPIO_CFGD_GPIO31INTD_Msk          (0x80000000UL)            /*!< GPIO31INTD (Bitfield-Mask: 0x01)                      */
13228 #define GPIO_CFGD_GPIO31OUTCFG_Pos        (29UL)                    /*!< GPIO31OUTCFG (Bit 29)                                 */
13229 #define GPIO_CFGD_GPIO31OUTCFG_Msk        (0x60000000UL)            /*!< GPIO31OUTCFG (Bitfield-Mask: 0x03)                    */
13230 #define GPIO_CFGD_GPIO31INCFG_Pos         (28UL)                    /*!< GPIO31INCFG (Bit 28)                                  */
13231 #define GPIO_CFGD_GPIO31INCFG_Msk         (0x10000000UL)            /*!< GPIO31INCFG (Bitfield-Mask: 0x01)                     */
13232 #define GPIO_CFGD_GPIO30INTD_Pos          (27UL)                    /*!< GPIO30INTD (Bit 27)                                   */
13233 #define GPIO_CFGD_GPIO30INTD_Msk          (0x8000000UL)             /*!< GPIO30INTD (Bitfield-Mask: 0x01)                      */
13234 #define GPIO_CFGD_GPIO30OUTCFG_Pos        (25UL)                    /*!< GPIO30OUTCFG (Bit 25)                                 */
13235 #define GPIO_CFGD_GPIO30OUTCFG_Msk        (0x6000000UL)             /*!< GPIO30OUTCFG (Bitfield-Mask: 0x03)                    */
13236 #define GPIO_CFGD_GPIO30INCFG_Pos         (24UL)                    /*!< GPIO30INCFG (Bit 24)                                  */
13237 #define GPIO_CFGD_GPIO30INCFG_Msk         (0x1000000UL)             /*!< GPIO30INCFG (Bitfield-Mask: 0x01)                     */
13238 #define GPIO_CFGD_GPIO29INTD_Pos          (23UL)                    /*!< GPIO29INTD (Bit 23)                                   */
13239 #define GPIO_CFGD_GPIO29INTD_Msk          (0x800000UL)              /*!< GPIO29INTD (Bitfield-Mask: 0x01)                      */
13240 #define GPIO_CFGD_GPIO29OUTCFG_Pos        (21UL)                    /*!< GPIO29OUTCFG (Bit 21)                                 */
13241 #define GPIO_CFGD_GPIO29OUTCFG_Msk        (0x600000UL)              /*!< GPIO29OUTCFG (Bitfield-Mask: 0x03)                    */
13242 #define GPIO_CFGD_GPIO29INCFG_Pos         (20UL)                    /*!< GPIO29INCFG (Bit 20)                                  */
13243 #define GPIO_CFGD_GPIO29INCFG_Msk         (0x100000UL)              /*!< GPIO29INCFG (Bitfield-Mask: 0x01)                     */
13244 #define GPIO_CFGD_GPIO28INTD_Pos          (19UL)                    /*!< GPIO28INTD (Bit 19)                                   */
13245 #define GPIO_CFGD_GPIO28INTD_Msk          (0x80000UL)               /*!< GPIO28INTD (Bitfield-Mask: 0x01)                      */
13246 #define GPIO_CFGD_GPIO28OUTCFG_Pos        (17UL)                    /*!< GPIO28OUTCFG (Bit 17)                                 */
13247 #define GPIO_CFGD_GPIO28OUTCFG_Msk        (0x60000UL)               /*!< GPIO28OUTCFG (Bitfield-Mask: 0x03)                    */
13248 #define GPIO_CFGD_GPIO28INCFG_Pos         (16UL)                    /*!< GPIO28INCFG (Bit 16)                                  */
13249 #define GPIO_CFGD_GPIO28INCFG_Msk         (0x10000UL)               /*!< GPIO28INCFG (Bitfield-Mask: 0x01)                     */
13250 #define GPIO_CFGD_GPIO27INTD_Pos          (15UL)                    /*!< GPIO27INTD (Bit 15)                                   */
13251 #define GPIO_CFGD_GPIO27INTD_Msk          (0x8000UL)                /*!< GPIO27INTD (Bitfield-Mask: 0x01)                      */
13252 #define GPIO_CFGD_GPIO27OUTCFG_Pos        (13UL)                    /*!< GPIO27OUTCFG (Bit 13)                                 */
13253 #define GPIO_CFGD_GPIO27OUTCFG_Msk        (0x6000UL)                /*!< GPIO27OUTCFG (Bitfield-Mask: 0x03)                    */
13254 #define GPIO_CFGD_GPIO27INCFG_Pos         (12UL)                    /*!< GPIO27INCFG (Bit 12)                                  */
13255 #define GPIO_CFGD_GPIO27INCFG_Msk         (0x1000UL)                /*!< GPIO27INCFG (Bitfield-Mask: 0x01)                     */
13256 #define GPIO_CFGD_GPIO26INTD_Pos          (11UL)                    /*!< GPIO26INTD (Bit 11)                                   */
13257 #define GPIO_CFGD_GPIO26INTD_Msk          (0x800UL)                 /*!< GPIO26INTD (Bitfield-Mask: 0x01)                      */
13258 #define GPIO_CFGD_GPIO26OUTCFG_Pos        (9UL)                     /*!< GPIO26OUTCFG (Bit 9)                                  */
13259 #define GPIO_CFGD_GPIO26OUTCFG_Msk        (0x600UL)                 /*!< GPIO26OUTCFG (Bitfield-Mask: 0x03)                    */
13260 #define GPIO_CFGD_GPIO26INCFG_Pos         (8UL)                     /*!< GPIO26INCFG (Bit 8)                                   */
13261 #define GPIO_CFGD_GPIO26INCFG_Msk         (0x100UL)                 /*!< GPIO26INCFG (Bitfield-Mask: 0x01)                     */
13262 #define GPIO_CFGD_GPIO25INTD_Pos          (7UL)                     /*!< GPIO25INTD (Bit 7)                                    */
13263 #define GPIO_CFGD_GPIO25INTD_Msk          (0x80UL)                  /*!< GPIO25INTD (Bitfield-Mask: 0x01)                      */
13264 #define GPIO_CFGD_GPIO25OUTCFG_Pos        (5UL)                     /*!< GPIO25OUTCFG (Bit 5)                                  */
13265 #define GPIO_CFGD_GPIO25OUTCFG_Msk        (0x60UL)                  /*!< GPIO25OUTCFG (Bitfield-Mask: 0x03)                    */
13266 #define GPIO_CFGD_GPIO25INCFG_Pos         (4UL)                     /*!< GPIO25INCFG (Bit 4)                                   */
13267 #define GPIO_CFGD_GPIO25INCFG_Msk         (0x10UL)                  /*!< GPIO25INCFG (Bitfield-Mask: 0x01)                     */
13268 #define GPIO_CFGD_GPIO24INTD_Pos          (3UL)                     /*!< GPIO24INTD (Bit 3)                                    */
13269 #define GPIO_CFGD_GPIO24INTD_Msk          (0x8UL)                   /*!< GPIO24INTD (Bitfield-Mask: 0x01)                      */
13270 #define GPIO_CFGD_GPIO24OUTCFG_Pos        (1UL)                     /*!< GPIO24OUTCFG (Bit 1)                                  */
13271 #define GPIO_CFGD_GPIO24OUTCFG_Msk        (0x6UL)                   /*!< GPIO24OUTCFG (Bitfield-Mask: 0x03)                    */
13272 #define GPIO_CFGD_GPIO24INCFG_Pos         (0UL)                     /*!< GPIO24INCFG (Bit 0)                                   */
13273 #define GPIO_CFGD_GPIO24INCFG_Msk         (0x1UL)                   /*!< GPIO24INCFG (Bitfield-Mask: 0x01)                     */
13274 /* =========================================================  CFGE  ========================================================== */
13275 #define GPIO_CFGE_GPIO39INTD_Pos          (31UL)                    /*!< GPIO39INTD (Bit 31)                                   */
13276 #define GPIO_CFGE_GPIO39INTD_Msk          (0x80000000UL)            /*!< GPIO39INTD (Bitfield-Mask: 0x01)                      */
13277 #define GPIO_CFGE_GPIO39OUTCFG_Pos        (29UL)                    /*!< GPIO39OUTCFG (Bit 29)                                 */
13278 #define GPIO_CFGE_GPIO39OUTCFG_Msk        (0x60000000UL)            /*!< GPIO39OUTCFG (Bitfield-Mask: 0x03)                    */
13279 #define GPIO_CFGE_GPIO39INCFG_Pos         (28UL)                    /*!< GPIO39INCFG (Bit 28)                                  */
13280 #define GPIO_CFGE_GPIO39INCFG_Msk         (0x10000000UL)            /*!< GPIO39INCFG (Bitfield-Mask: 0x01)                     */
13281 #define GPIO_CFGE_GPIO38INTD_Pos          (27UL)                    /*!< GPIO38INTD (Bit 27)                                   */
13282 #define GPIO_CFGE_GPIO38INTD_Msk          (0x8000000UL)             /*!< GPIO38INTD (Bitfield-Mask: 0x01)                      */
13283 #define GPIO_CFGE_GPIO38OUTCFG_Pos        (25UL)                    /*!< GPIO38OUTCFG (Bit 25)                                 */
13284 #define GPIO_CFGE_GPIO38OUTCFG_Msk        (0x6000000UL)             /*!< GPIO38OUTCFG (Bitfield-Mask: 0x03)                    */
13285 #define GPIO_CFGE_GPIO38INCFG_Pos         (24UL)                    /*!< GPIO38INCFG (Bit 24)                                  */
13286 #define GPIO_CFGE_GPIO38INCFG_Msk         (0x1000000UL)             /*!< GPIO38INCFG (Bitfield-Mask: 0x01)                     */
13287 #define GPIO_CFGE_GPIO37INTD_Pos          (23UL)                    /*!< GPIO37INTD (Bit 23)                                   */
13288 #define GPIO_CFGE_GPIO37INTD_Msk          (0x800000UL)              /*!< GPIO37INTD (Bitfield-Mask: 0x01)                      */
13289 #define GPIO_CFGE_GPIO37OUTCFG_Pos        (21UL)                    /*!< GPIO37OUTCFG (Bit 21)                                 */
13290 #define GPIO_CFGE_GPIO37OUTCFG_Msk        (0x600000UL)              /*!< GPIO37OUTCFG (Bitfield-Mask: 0x03)                    */
13291 #define GPIO_CFGE_GPIO37INCFG_Pos         (20UL)                    /*!< GPIO37INCFG (Bit 20)                                  */
13292 #define GPIO_CFGE_GPIO37INCFG_Msk         (0x100000UL)              /*!< GPIO37INCFG (Bitfield-Mask: 0x01)                     */
13293 #define GPIO_CFGE_GPIO36INTD_Pos          (19UL)                    /*!< GPIO36INTD (Bit 19)                                   */
13294 #define GPIO_CFGE_GPIO36INTD_Msk          (0x80000UL)               /*!< GPIO36INTD (Bitfield-Mask: 0x01)                      */
13295 #define GPIO_CFGE_GPIO36OUTCFG_Pos        (17UL)                    /*!< GPIO36OUTCFG (Bit 17)                                 */
13296 #define GPIO_CFGE_GPIO36OUTCFG_Msk        (0x60000UL)               /*!< GPIO36OUTCFG (Bitfield-Mask: 0x03)                    */
13297 #define GPIO_CFGE_GPIO36INCFG_Pos         (16UL)                    /*!< GPIO36INCFG (Bit 16)                                  */
13298 #define GPIO_CFGE_GPIO36INCFG_Msk         (0x10000UL)               /*!< GPIO36INCFG (Bitfield-Mask: 0x01)                     */
13299 #define GPIO_CFGE_GPIO35INTD_Pos          (15UL)                    /*!< GPIO35INTD (Bit 15)                                   */
13300 #define GPIO_CFGE_GPIO35INTD_Msk          (0x8000UL)                /*!< GPIO35INTD (Bitfield-Mask: 0x01)                      */
13301 #define GPIO_CFGE_GPIO35OUTCFG_Pos        (13UL)                    /*!< GPIO35OUTCFG (Bit 13)                                 */
13302 #define GPIO_CFGE_GPIO35OUTCFG_Msk        (0x6000UL)                /*!< GPIO35OUTCFG (Bitfield-Mask: 0x03)                    */
13303 #define GPIO_CFGE_GPIO35INCFG_Pos         (12UL)                    /*!< GPIO35INCFG (Bit 12)                                  */
13304 #define GPIO_CFGE_GPIO35INCFG_Msk         (0x1000UL)                /*!< GPIO35INCFG (Bitfield-Mask: 0x01)                     */
13305 #define GPIO_CFGE_GPIO34INTD_Pos          (11UL)                    /*!< GPIO34INTD (Bit 11)                                   */
13306 #define GPIO_CFGE_GPIO34INTD_Msk          (0x800UL)                 /*!< GPIO34INTD (Bitfield-Mask: 0x01)                      */
13307 #define GPIO_CFGE_GPIO34OUTCFG_Pos        (9UL)                     /*!< GPIO34OUTCFG (Bit 9)                                  */
13308 #define GPIO_CFGE_GPIO34OUTCFG_Msk        (0x600UL)                 /*!< GPIO34OUTCFG (Bitfield-Mask: 0x03)                    */
13309 #define GPIO_CFGE_GPIO34INCFG_Pos         (8UL)                     /*!< GPIO34INCFG (Bit 8)                                   */
13310 #define GPIO_CFGE_GPIO34INCFG_Msk         (0x100UL)                 /*!< GPIO34INCFG (Bitfield-Mask: 0x01)                     */
13311 #define GPIO_CFGE_GPIO33INTD_Pos          (7UL)                     /*!< GPIO33INTD (Bit 7)                                    */
13312 #define GPIO_CFGE_GPIO33INTD_Msk          (0x80UL)                  /*!< GPIO33INTD (Bitfield-Mask: 0x01)                      */
13313 #define GPIO_CFGE_GPIO33OUTCFG_Pos        (5UL)                     /*!< GPIO33OUTCFG (Bit 5)                                  */
13314 #define GPIO_CFGE_GPIO33OUTCFG_Msk        (0x60UL)                  /*!< GPIO33OUTCFG (Bitfield-Mask: 0x03)                    */
13315 #define GPIO_CFGE_GPIO33INCFG_Pos         (4UL)                     /*!< GPIO33INCFG (Bit 4)                                   */
13316 #define GPIO_CFGE_GPIO33INCFG_Msk         (0x10UL)                  /*!< GPIO33INCFG (Bitfield-Mask: 0x01)                     */
13317 #define GPIO_CFGE_GPIO32INTD_Pos          (3UL)                     /*!< GPIO32INTD (Bit 3)                                    */
13318 #define GPIO_CFGE_GPIO32INTD_Msk          (0x8UL)                   /*!< GPIO32INTD (Bitfield-Mask: 0x01)                      */
13319 #define GPIO_CFGE_GPIO32OUTCFG_Pos        (1UL)                     /*!< GPIO32OUTCFG (Bit 1)                                  */
13320 #define GPIO_CFGE_GPIO32OUTCFG_Msk        (0x6UL)                   /*!< GPIO32OUTCFG (Bitfield-Mask: 0x03)                    */
13321 #define GPIO_CFGE_GPIO32INCFG_Pos         (0UL)                     /*!< GPIO32INCFG (Bit 0)                                   */
13322 #define GPIO_CFGE_GPIO32INCFG_Msk         (0x1UL)                   /*!< GPIO32INCFG (Bitfield-Mask: 0x01)                     */
13323 /* =========================================================  CFGF  ========================================================== */
13324 #define GPIO_CFGF_GPIO47INTD_Pos          (31UL)                    /*!< GPIO47INTD (Bit 31)                                   */
13325 #define GPIO_CFGF_GPIO47INTD_Msk          (0x80000000UL)            /*!< GPIO47INTD (Bitfield-Mask: 0x01)                      */
13326 #define GPIO_CFGF_GPIO47OUTCFG_Pos        (29UL)                    /*!< GPIO47OUTCFG (Bit 29)                                 */
13327 #define GPIO_CFGF_GPIO47OUTCFG_Msk        (0x60000000UL)            /*!< GPIO47OUTCFG (Bitfield-Mask: 0x03)                    */
13328 #define GPIO_CFGF_GPIO47INCFG_Pos         (28UL)                    /*!< GPIO47INCFG (Bit 28)                                  */
13329 #define GPIO_CFGF_GPIO47INCFG_Msk         (0x10000000UL)            /*!< GPIO47INCFG (Bitfield-Mask: 0x01)                     */
13330 #define GPIO_CFGF_GPIO46INTD_Pos          (27UL)                    /*!< GPIO46INTD (Bit 27)                                   */
13331 #define GPIO_CFGF_GPIO46INTD_Msk          (0x8000000UL)             /*!< GPIO46INTD (Bitfield-Mask: 0x01)                      */
13332 #define GPIO_CFGF_GPIO46OUTCFG_Pos        (25UL)                    /*!< GPIO46OUTCFG (Bit 25)                                 */
13333 #define GPIO_CFGF_GPIO46OUTCFG_Msk        (0x6000000UL)             /*!< GPIO46OUTCFG (Bitfield-Mask: 0x03)                    */
13334 #define GPIO_CFGF_GPIO46INCFG_Pos         (24UL)                    /*!< GPIO46INCFG (Bit 24)                                  */
13335 #define GPIO_CFGF_GPIO46INCFG_Msk         (0x1000000UL)             /*!< GPIO46INCFG (Bitfield-Mask: 0x01)                     */
13336 #define GPIO_CFGF_GPIO45INTD_Pos          (23UL)                    /*!< GPIO45INTD (Bit 23)                                   */
13337 #define GPIO_CFGF_GPIO45INTD_Msk          (0x800000UL)              /*!< GPIO45INTD (Bitfield-Mask: 0x01)                      */
13338 #define GPIO_CFGF_GPIO45OUTCFG_Pos        (21UL)                    /*!< GPIO45OUTCFG (Bit 21)                                 */
13339 #define GPIO_CFGF_GPIO45OUTCFG_Msk        (0x600000UL)              /*!< GPIO45OUTCFG (Bitfield-Mask: 0x03)                    */
13340 #define GPIO_CFGF_GPIO45INCFG_Pos         (20UL)                    /*!< GPIO45INCFG (Bit 20)                                  */
13341 #define GPIO_CFGF_GPIO45INCFG_Msk         (0x100000UL)              /*!< GPIO45INCFG (Bitfield-Mask: 0x01)                     */
13342 #define GPIO_CFGF_GPIO44INTD_Pos          (19UL)                    /*!< GPIO44INTD (Bit 19)                                   */
13343 #define GPIO_CFGF_GPIO44INTD_Msk          (0x80000UL)               /*!< GPIO44INTD (Bitfield-Mask: 0x01)                      */
13344 #define GPIO_CFGF_GPIO44OUTCFG_Pos        (17UL)                    /*!< GPIO44OUTCFG (Bit 17)                                 */
13345 #define GPIO_CFGF_GPIO44OUTCFG_Msk        (0x60000UL)               /*!< GPIO44OUTCFG (Bitfield-Mask: 0x03)                    */
13346 #define GPIO_CFGF_GPIO44INCFG_Pos         (16UL)                    /*!< GPIO44INCFG (Bit 16)                                  */
13347 #define GPIO_CFGF_GPIO44INCFG_Msk         (0x10000UL)               /*!< GPIO44INCFG (Bitfield-Mask: 0x01)                     */
13348 #define GPIO_CFGF_GPIO43INTD_Pos          (15UL)                    /*!< GPIO43INTD (Bit 15)                                   */
13349 #define GPIO_CFGF_GPIO43INTD_Msk          (0x8000UL)                /*!< GPIO43INTD (Bitfield-Mask: 0x01)                      */
13350 #define GPIO_CFGF_GPIO43OUTCFG_Pos        (13UL)                    /*!< GPIO43OUTCFG (Bit 13)                                 */
13351 #define GPIO_CFGF_GPIO43OUTCFG_Msk        (0x6000UL)                /*!< GPIO43OUTCFG (Bitfield-Mask: 0x03)                    */
13352 #define GPIO_CFGF_GPIO43INCFG_Pos         (12UL)                    /*!< GPIO43INCFG (Bit 12)                                  */
13353 #define GPIO_CFGF_GPIO43INCFG_Msk         (0x1000UL)                /*!< GPIO43INCFG (Bitfield-Mask: 0x01)                     */
13354 #define GPIO_CFGF_GPIO42INTD_Pos          (11UL)                    /*!< GPIO42INTD (Bit 11)                                   */
13355 #define GPIO_CFGF_GPIO42INTD_Msk          (0x800UL)                 /*!< GPIO42INTD (Bitfield-Mask: 0x01)                      */
13356 #define GPIO_CFGF_GPIO42OUTCFG_Pos        (9UL)                     /*!< GPIO42OUTCFG (Bit 9)                                  */
13357 #define GPIO_CFGF_GPIO42OUTCFG_Msk        (0x600UL)                 /*!< GPIO42OUTCFG (Bitfield-Mask: 0x03)                    */
13358 #define GPIO_CFGF_GPIO42INCFG_Pos         (8UL)                     /*!< GPIO42INCFG (Bit 8)                                   */
13359 #define GPIO_CFGF_GPIO42INCFG_Msk         (0x100UL)                 /*!< GPIO42INCFG (Bitfield-Mask: 0x01)                     */
13360 #define GPIO_CFGF_GPIO41INTD_Pos          (7UL)                     /*!< GPIO41INTD (Bit 7)                                    */
13361 #define GPIO_CFGF_GPIO41INTD_Msk          (0x80UL)                  /*!< GPIO41INTD (Bitfield-Mask: 0x01)                      */
13362 #define GPIO_CFGF_GPIO41OUTCFG_Pos        (5UL)                     /*!< GPIO41OUTCFG (Bit 5)                                  */
13363 #define GPIO_CFGF_GPIO41OUTCFG_Msk        (0x60UL)                  /*!< GPIO41OUTCFG (Bitfield-Mask: 0x03)                    */
13364 #define GPIO_CFGF_GPIO41INCFG_Pos         (4UL)                     /*!< GPIO41INCFG (Bit 4)                                   */
13365 #define GPIO_CFGF_GPIO41INCFG_Msk         (0x10UL)                  /*!< GPIO41INCFG (Bitfield-Mask: 0x01)                     */
13366 #define GPIO_CFGF_GPIO40INTD_Pos          (3UL)                     /*!< GPIO40INTD (Bit 3)                                    */
13367 #define GPIO_CFGF_GPIO40INTD_Msk          (0x8UL)                   /*!< GPIO40INTD (Bitfield-Mask: 0x01)                      */
13368 #define GPIO_CFGF_GPIO40OUTCFG_Pos        (1UL)                     /*!< GPIO40OUTCFG (Bit 1)                                  */
13369 #define GPIO_CFGF_GPIO40OUTCFG_Msk        (0x6UL)                   /*!< GPIO40OUTCFG (Bitfield-Mask: 0x03)                    */
13370 #define GPIO_CFGF_GPIO40INCFG_Pos         (0UL)                     /*!< GPIO40INCFG (Bit 0)                                   */
13371 #define GPIO_CFGF_GPIO40INCFG_Msk         (0x1UL)                   /*!< GPIO40INCFG (Bitfield-Mask: 0x01)                     */
13372 /* =========================================================  CFGG  ========================================================== */
13373 #define GPIO_CFGG_GPIO55INTD_Pos          (31UL)                    /*!< GPIO55INTD (Bit 31)                                   */
13374 #define GPIO_CFGG_GPIO55INTD_Msk          (0x80000000UL)            /*!< GPIO55INTD (Bitfield-Mask: 0x01)                      */
13375 #define GPIO_CFGG_GPIO55OUTCFG_Pos        (29UL)                    /*!< GPIO55OUTCFG (Bit 29)                                 */
13376 #define GPIO_CFGG_GPIO55OUTCFG_Msk        (0x60000000UL)            /*!< GPIO55OUTCFG (Bitfield-Mask: 0x03)                    */
13377 #define GPIO_CFGG_GPIO55INCFG_Pos         (28UL)                    /*!< GPIO55INCFG (Bit 28)                                  */
13378 #define GPIO_CFGG_GPIO55INCFG_Msk         (0x10000000UL)            /*!< GPIO55INCFG (Bitfield-Mask: 0x01)                     */
13379 #define GPIO_CFGG_GPIO54INTD_Pos          (27UL)                    /*!< GPIO54INTD (Bit 27)                                   */
13380 #define GPIO_CFGG_GPIO54INTD_Msk          (0x8000000UL)             /*!< GPIO54INTD (Bitfield-Mask: 0x01)                      */
13381 #define GPIO_CFGG_GPIO54OUTCFG_Pos        (25UL)                    /*!< GPIO54OUTCFG (Bit 25)                                 */
13382 #define GPIO_CFGG_GPIO54OUTCFG_Msk        (0x6000000UL)             /*!< GPIO54OUTCFG (Bitfield-Mask: 0x03)                    */
13383 #define GPIO_CFGG_GPIO54INCFG_Pos         (24UL)                    /*!< GPIO54INCFG (Bit 24)                                  */
13384 #define GPIO_CFGG_GPIO54INCFG_Msk         (0x1000000UL)             /*!< GPIO54INCFG (Bitfield-Mask: 0x01)                     */
13385 #define GPIO_CFGG_GPIO53INTD_Pos          (23UL)                    /*!< GPIO53INTD (Bit 23)                                   */
13386 #define GPIO_CFGG_GPIO53INTD_Msk          (0x800000UL)              /*!< GPIO53INTD (Bitfield-Mask: 0x01)                      */
13387 #define GPIO_CFGG_GPIO53OUTCFG_Pos        (21UL)                    /*!< GPIO53OUTCFG (Bit 21)                                 */
13388 #define GPIO_CFGG_GPIO53OUTCFG_Msk        (0x600000UL)              /*!< GPIO53OUTCFG (Bitfield-Mask: 0x03)                    */
13389 #define GPIO_CFGG_GPIO53INCFG_Pos         (20UL)                    /*!< GPIO53INCFG (Bit 20)                                  */
13390 #define GPIO_CFGG_GPIO53INCFG_Msk         (0x100000UL)              /*!< GPIO53INCFG (Bitfield-Mask: 0x01)                     */
13391 #define GPIO_CFGG_GPIO52INTD_Pos          (19UL)                    /*!< GPIO52INTD (Bit 19)                                   */
13392 #define GPIO_CFGG_GPIO52INTD_Msk          (0x80000UL)               /*!< GPIO52INTD (Bitfield-Mask: 0x01)                      */
13393 #define GPIO_CFGG_GPIO52OUTCFG_Pos        (17UL)                    /*!< GPIO52OUTCFG (Bit 17)                                 */
13394 #define GPIO_CFGG_GPIO52OUTCFG_Msk        (0x60000UL)               /*!< GPIO52OUTCFG (Bitfield-Mask: 0x03)                    */
13395 #define GPIO_CFGG_GPIO52INCFG_Pos         (16UL)                    /*!< GPIO52INCFG (Bit 16)                                  */
13396 #define GPIO_CFGG_GPIO52INCFG_Msk         (0x10000UL)               /*!< GPIO52INCFG (Bitfield-Mask: 0x01)                     */
13397 #define GPIO_CFGG_GPIO51INTD_Pos          (15UL)                    /*!< GPIO51INTD (Bit 15)                                   */
13398 #define GPIO_CFGG_GPIO51INTD_Msk          (0x8000UL)                /*!< GPIO51INTD (Bitfield-Mask: 0x01)                      */
13399 #define GPIO_CFGG_GPIO51OUTCFG_Pos        (13UL)                    /*!< GPIO51OUTCFG (Bit 13)                                 */
13400 #define GPIO_CFGG_GPIO51OUTCFG_Msk        (0x6000UL)                /*!< GPIO51OUTCFG (Bitfield-Mask: 0x03)                    */
13401 #define GPIO_CFGG_GPIO51INCFG_Pos         (12UL)                    /*!< GPIO51INCFG (Bit 12)                                  */
13402 #define GPIO_CFGG_GPIO51INCFG_Msk         (0x1000UL)                /*!< GPIO51INCFG (Bitfield-Mask: 0x01)                     */
13403 #define GPIO_CFGG_GPIO50INTD_Pos          (11UL)                    /*!< GPIO50INTD (Bit 11)                                   */
13404 #define GPIO_CFGG_GPIO50INTD_Msk          (0x800UL)                 /*!< GPIO50INTD (Bitfield-Mask: 0x01)                      */
13405 #define GPIO_CFGG_GPIO50OUTCFG_Pos        (9UL)                     /*!< GPIO50OUTCFG (Bit 9)                                  */
13406 #define GPIO_CFGG_GPIO50OUTCFG_Msk        (0x600UL)                 /*!< GPIO50OUTCFG (Bitfield-Mask: 0x03)                    */
13407 #define GPIO_CFGG_GPIO50INCFG_Pos         (8UL)                     /*!< GPIO50INCFG (Bit 8)                                   */
13408 #define GPIO_CFGG_GPIO50INCFG_Msk         (0x100UL)                 /*!< GPIO50INCFG (Bitfield-Mask: 0x01)                     */
13409 #define GPIO_CFGG_GPIO49INTD_Pos          (7UL)                     /*!< GPIO49INTD (Bit 7)                                    */
13410 #define GPIO_CFGG_GPIO49INTD_Msk          (0x80UL)                  /*!< GPIO49INTD (Bitfield-Mask: 0x01)                      */
13411 #define GPIO_CFGG_GPIO49OUTCFG_Pos        (5UL)                     /*!< GPIO49OUTCFG (Bit 5)                                  */
13412 #define GPIO_CFGG_GPIO49OUTCFG_Msk        (0x60UL)                  /*!< GPIO49OUTCFG (Bitfield-Mask: 0x03)                    */
13413 #define GPIO_CFGG_GPIO49INCFG_Pos         (4UL)                     /*!< GPIO49INCFG (Bit 4)                                   */
13414 #define GPIO_CFGG_GPIO49INCFG_Msk         (0x10UL)                  /*!< GPIO49INCFG (Bitfield-Mask: 0x01)                     */
13415 #define GPIO_CFGG_GPIO48INTD_Pos          (3UL)                     /*!< GPIO48INTD (Bit 3)                                    */
13416 #define GPIO_CFGG_GPIO48INTD_Msk          (0x8UL)                   /*!< GPIO48INTD (Bitfield-Mask: 0x01)                      */
13417 #define GPIO_CFGG_GPIO48OUTCFG_Pos        (1UL)                     /*!< GPIO48OUTCFG (Bit 1)                                  */
13418 #define GPIO_CFGG_GPIO48OUTCFG_Msk        (0x6UL)                   /*!< GPIO48OUTCFG (Bitfield-Mask: 0x03)                    */
13419 #define GPIO_CFGG_GPIO48INCFG_Pos         (0UL)                     /*!< GPIO48INCFG (Bit 0)                                   */
13420 #define GPIO_CFGG_GPIO48INCFG_Msk         (0x1UL)                   /*!< GPIO48INCFG (Bitfield-Mask: 0x01)                     */
13421 /* =========================================================  CFGH  ========================================================== */
13422 #define GPIO_CFGH_GPIO63INTD_Pos          (31UL)                    /*!< GPIO63INTD (Bit 31)                                   */
13423 #define GPIO_CFGH_GPIO63INTD_Msk          (0x80000000UL)            /*!< GPIO63INTD (Bitfield-Mask: 0x01)                      */
13424 #define GPIO_CFGH_GPIO63OUTCFG_Pos        (29UL)                    /*!< GPIO63OUTCFG (Bit 29)                                 */
13425 #define GPIO_CFGH_GPIO63OUTCFG_Msk        (0x60000000UL)            /*!< GPIO63OUTCFG (Bitfield-Mask: 0x03)                    */
13426 #define GPIO_CFGH_GPIO63INCFG_Pos         (28UL)                    /*!< GPIO63INCFG (Bit 28)                                  */
13427 #define GPIO_CFGH_GPIO63INCFG_Msk         (0x10000000UL)            /*!< GPIO63INCFG (Bitfield-Mask: 0x01)                     */
13428 #define GPIO_CFGH_GPIO62INTD_Pos          (27UL)                    /*!< GPIO62INTD (Bit 27)                                   */
13429 #define GPIO_CFGH_GPIO62INTD_Msk          (0x8000000UL)             /*!< GPIO62INTD (Bitfield-Mask: 0x01)                      */
13430 #define GPIO_CFGH_GPIO62OUTCFG_Pos        (25UL)                    /*!< GPIO62OUTCFG (Bit 25)                                 */
13431 #define GPIO_CFGH_GPIO62OUTCFG_Msk        (0x6000000UL)             /*!< GPIO62OUTCFG (Bitfield-Mask: 0x03)                    */
13432 #define GPIO_CFGH_GPIO62INCFG_Pos         (24UL)                    /*!< GPIO62INCFG (Bit 24)                                  */
13433 #define GPIO_CFGH_GPIO62INCFG_Msk         (0x1000000UL)             /*!< GPIO62INCFG (Bitfield-Mask: 0x01)                     */
13434 #define GPIO_CFGH_GPIO61INTD_Pos          (23UL)                    /*!< GPIO61INTD (Bit 23)                                   */
13435 #define GPIO_CFGH_GPIO61INTD_Msk          (0x800000UL)              /*!< GPIO61INTD (Bitfield-Mask: 0x01)                      */
13436 #define GPIO_CFGH_GPIO61OUTCFG_Pos        (21UL)                    /*!< GPIO61OUTCFG (Bit 21)                                 */
13437 #define GPIO_CFGH_GPIO61OUTCFG_Msk        (0x600000UL)              /*!< GPIO61OUTCFG (Bitfield-Mask: 0x03)                    */
13438 #define GPIO_CFGH_GPIO61INCFG_Pos         (20UL)                    /*!< GPIO61INCFG (Bit 20)                                  */
13439 #define GPIO_CFGH_GPIO61INCFG_Msk         (0x100000UL)              /*!< GPIO61INCFG (Bitfield-Mask: 0x01)                     */
13440 #define GPIO_CFGH_GPIO60INTD_Pos          (19UL)                    /*!< GPIO60INTD (Bit 19)                                   */
13441 #define GPIO_CFGH_GPIO60INTD_Msk          (0x80000UL)               /*!< GPIO60INTD (Bitfield-Mask: 0x01)                      */
13442 #define GPIO_CFGH_GPIO60OUTCFG_Pos        (17UL)                    /*!< GPIO60OUTCFG (Bit 17)                                 */
13443 #define GPIO_CFGH_GPIO60OUTCFG_Msk        (0x60000UL)               /*!< GPIO60OUTCFG (Bitfield-Mask: 0x03)                    */
13444 #define GPIO_CFGH_GPIO60INCFG_Pos         (16UL)                    /*!< GPIO60INCFG (Bit 16)                                  */
13445 #define GPIO_CFGH_GPIO60INCFG_Msk         (0x10000UL)               /*!< GPIO60INCFG (Bitfield-Mask: 0x01)                     */
13446 #define GPIO_CFGH_GPIO59INTD_Pos          (15UL)                    /*!< GPIO59INTD (Bit 15)                                   */
13447 #define GPIO_CFGH_GPIO59INTD_Msk          (0x8000UL)                /*!< GPIO59INTD (Bitfield-Mask: 0x01)                      */
13448 #define GPIO_CFGH_GPIO59OUTCFG_Pos        (13UL)                    /*!< GPIO59OUTCFG (Bit 13)                                 */
13449 #define GPIO_CFGH_GPIO59OUTCFG_Msk        (0x6000UL)                /*!< GPIO59OUTCFG (Bitfield-Mask: 0x03)                    */
13450 #define GPIO_CFGH_GPIO59INCFG_Pos         (12UL)                    /*!< GPIO59INCFG (Bit 12)                                  */
13451 #define GPIO_CFGH_GPIO59INCFG_Msk         (0x1000UL)                /*!< GPIO59INCFG (Bitfield-Mask: 0x01)                     */
13452 #define GPIO_CFGH_GPIO58INTD_Pos          (11UL)                    /*!< GPIO58INTD (Bit 11)                                   */
13453 #define GPIO_CFGH_GPIO58INTD_Msk          (0x800UL)                 /*!< GPIO58INTD (Bitfield-Mask: 0x01)                      */
13454 #define GPIO_CFGH_GPIO58OUTCFG_Pos        (9UL)                     /*!< GPIO58OUTCFG (Bit 9)                                  */
13455 #define GPIO_CFGH_GPIO58OUTCFG_Msk        (0x600UL)                 /*!< GPIO58OUTCFG (Bitfield-Mask: 0x03)                    */
13456 #define GPIO_CFGH_GPIO58INCFG_Pos         (8UL)                     /*!< GPIO58INCFG (Bit 8)                                   */
13457 #define GPIO_CFGH_GPIO58INCFG_Msk         (0x100UL)                 /*!< GPIO58INCFG (Bitfield-Mask: 0x01)                     */
13458 #define GPIO_CFGH_GPIO57INTD_Pos          (7UL)                     /*!< GPIO57INTD (Bit 7)                                    */
13459 #define GPIO_CFGH_GPIO57INTD_Msk          (0x80UL)                  /*!< GPIO57INTD (Bitfield-Mask: 0x01)                      */
13460 #define GPIO_CFGH_GPIO57OUTCFG_Pos        (5UL)                     /*!< GPIO57OUTCFG (Bit 5)                                  */
13461 #define GPIO_CFGH_GPIO57OUTCFG_Msk        (0x60UL)                  /*!< GPIO57OUTCFG (Bitfield-Mask: 0x03)                    */
13462 #define GPIO_CFGH_GPIO57INCFG_Pos         (4UL)                     /*!< GPIO57INCFG (Bit 4)                                   */
13463 #define GPIO_CFGH_GPIO57INCFG_Msk         (0x10UL)                  /*!< GPIO57INCFG (Bitfield-Mask: 0x01)                     */
13464 #define GPIO_CFGH_GPIO56INTD_Pos          (3UL)                     /*!< GPIO56INTD (Bit 3)                                    */
13465 #define GPIO_CFGH_GPIO56INTD_Msk          (0x8UL)                   /*!< GPIO56INTD (Bitfield-Mask: 0x01)                      */
13466 #define GPIO_CFGH_GPIO56OUTCFG_Pos        (1UL)                     /*!< GPIO56OUTCFG (Bit 1)                                  */
13467 #define GPIO_CFGH_GPIO56OUTCFG_Msk        (0x6UL)                   /*!< GPIO56OUTCFG (Bitfield-Mask: 0x03)                    */
13468 #define GPIO_CFGH_GPIO56INCFG_Pos         (0UL)                     /*!< GPIO56INCFG (Bit 0)                                   */
13469 #define GPIO_CFGH_GPIO56INCFG_Msk         (0x1UL)                   /*!< GPIO56INCFG (Bitfield-Mask: 0x01)                     */
13470 /* =========================================================  CFGI  ========================================================== */
13471 #define GPIO_CFGI_GPIO71INTD_Pos          (31UL)                    /*!< GPIO71INTD (Bit 31)                                   */
13472 #define GPIO_CFGI_GPIO71INTD_Msk          (0x80000000UL)            /*!< GPIO71INTD (Bitfield-Mask: 0x01)                      */
13473 #define GPIO_CFGI_GPIO71OUTCFG_Pos        (29UL)                    /*!< GPIO71OUTCFG (Bit 29)                                 */
13474 #define GPIO_CFGI_GPIO71OUTCFG_Msk        (0x60000000UL)            /*!< GPIO71OUTCFG (Bitfield-Mask: 0x03)                    */
13475 #define GPIO_CFGI_GPIO71INCFG_Pos         (28UL)                    /*!< GPIO71INCFG (Bit 28)                                  */
13476 #define GPIO_CFGI_GPIO71INCFG_Msk         (0x10000000UL)            /*!< GPIO71INCFG (Bitfield-Mask: 0x01)                     */
13477 #define GPIO_CFGI_GPIO70INTD_Pos          (27UL)                    /*!< GPIO70INTD (Bit 27)                                   */
13478 #define GPIO_CFGI_GPIO70INTD_Msk          (0x8000000UL)             /*!< GPIO70INTD (Bitfield-Mask: 0x01)                      */
13479 #define GPIO_CFGI_GPIO70OUTCFG_Pos        (25UL)                    /*!< GPIO70OUTCFG (Bit 25)                                 */
13480 #define GPIO_CFGI_GPIO70OUTCFG_Msk        (0x6000000UL)             /*!< GPIO70OUTCFG (Bitfield-Mask: 0x03)                    */
13481 #define GPIO_CFGI_GPIO70INCFG_Pos         (24UL)                    /*!< GPIO70INCFG (Bit 24)                                  */
13482 #define GPIO_CFGI_GPIO70INCFG_Msk         (0x1000000UL)             /*!< GPIO70INCFG (Bitfield-Mask: 0x01)                     */
13483 #define GPIO_CFGI_GPIO69INTD_Pos          (23UL)                    /*!< GPIO69INTD (Bit 23)                                   */
13484 #define GPIO_CFGI_GPIO69INTD_Msk          (0x800000UL)              /*!< GPIO69INTD (Bitfield-Mask: 0x01)                      */
13485 #define GPIO_CFGI_GPIO69OUTCFG_Pos        (21UL)                    /*!< GPIO69OUTCFG (Bit 21)                                 */
13486 #define GPIO_CFGI_GPIO69OUTCFG_Msk        (0x600000UL)              /*!< GPIO69OUTCFG (Bitfield-Mask: 0x03)                    */
13487 #define GPIO_CFGI_GPIO69INCFG_Pos         (20UL)                    /*!< GPIO69INCFG (Bit 20)                                  */
13488 #define GPIO_CFGI_GPIO69INCFG_Msk         (0x100000UL)              /*!< GPIO69INCFG (Bitfield-Mask: 0x01)                     */
13489 #define GPIO_CFGI_GPIO68INTD_Pos          (19UL)                    /*!< GPIO68INTD (Bit 19)                                   */
13490 #define GPIO_CFGI_GPIO68INTD_Msk          (0x80000UL)               /*!< GPIO68INTD (Bitfield-Mask: 0x01)                      */
13491 #define GPIO_CFGI_GPIO68OUTCFG_Pos        (17UL)                    /*!< GPIO68OUTCFG (Bit 17)                                 */
13492 #define GPIO_CFGI_GPIO68OUTCFG_Msk        (0x60000UL)               /*!< GPIO68OUTCFG (Bitfield-Mask: 0x03)                    */
13493 #define GPIO_CFGI_GPIO68INCFG_Pos         (16UL)                    /*!< GPIO68INCFG (Bit 16)                                  */
13494 #define GPIO_CFGI_GPIO68INCFG_Msk         (0x10000UL)               /*!< GPIO68INCFG (Bitfield-Mask: 0x01)                     */
13495 #define GPIO_CFGI_GPIO67INTD_Pos          (15UL)                    /*!< GPIO67INTD (Bit 15)                                   */
13496 #define GPIO_CFGI_GPIO67INTD_Msk          (0x8000UL)                /*!< GPIO67INTD (Bitfield-Mask: 0x01)                      */
13497 #define GPIO_CFGI_GPIO67OUTCFG_Pos        (13UL)                    /*!< GPIO67OUTCFG (Bit 13)                                 */
13498 #define GPIO_CFGI_GPIO67OUTCFG_Msk        (0x6000UL)                /*!< GPIO67OUTCFG (Bitfield-Mask: 0x03)                    */
13499 #define GPIO_CFGI_GPIO67INCFG_Pos         (12UL)                    /*!< GPIO67INCFG (Bit 12)                                  */
13500 #define GPIO_CFGI_GPIO67INCFG_Msk         (0x1000UL)                /*!< GPIO67INCFG (Bitfield-Mask: 0x01)                     */
13501 #define GPIO_CFGI_GPIO66INTD_Pos          (11UL)                    /*!< GPIO66INTD (Bit 11)                                   */
13502 #define GPIO_CFGI_GPIO66INTD_Msk          (0x800UL)                 /*!< GPIO66INTD (Bitfield-Mask: 0x01)                      */
13503 #define GPIO_CFGI_GPIO66OUTCFG_Pos        (9UL)                     /*!< GPIO66OUTCFG (Bit 9)                                  */
13504 #define GPIO_CFGI_GPIO66OUTCFG_Msk        (0x600UL)                 /*!< GPIO66OUTCFG (Bitfield-Mask: 0x03)                    */
13505 #define GPIO_CFGI_GPIO66INCFG_Pos         (8UL)                     /*!< GPIO66INCFG (Bit 8)                                   */
13506 #define GPIO_CFGI_GPIO66INCFG_Msk         (0x100UL)                 /*!< GPIO66INCFG (Bitfield-Mask: 0x01)                     */
13507 #define GPIO_CFGI_GPIO65INTD_Pos          (7UL)                     /*!< GPIO65INTD (Bit 7)                                    */
13508 #define GPIO_CFGI_GPIO65INTD_Msk          (0x80UL)                  /*!< GPIO65INTD (Bitfield-Mask: 0x01)                      */
13509 #define GPIO_CFGI_GPIO65OUTCFG_Pos        (5UL)                     /*!< GPIO65OUTCFG (Bit 5)                                  */
13510 #define GPIO_CFGI_GPIO65OUTCFG_Msk        (0x60UL)                  /*!< GPIO65OUTCFG (Bitfield-Mask: 0x03)                    */
13511 #define GPIO_CFGI_GPIO65INCFG_Pos         (4UL)                     /*!< GPIO65INCFG (Bit 4)                                   */
13512 #define GPIO_CFGI_GPIO65INCFG_Msk         (0x10UL)                  /*!< GPIO65INCFG (Bitfield-Mask: 0x01)                     */
13513 #define GPIO_CFGI_GPIO64INTD_Pos          (3UL)                     /*!< GPIO64INTD (Bit 3)                                    */
13514 #define GPIO_CFGI_GPIO64INTD_Msk          (0x8UL)                   /*!< GPIO64INTD (Bitfield-Mask: 0x01)                      */
13515 #define GPIO_CFGI_GPIO64OUTCFG_Pos        (1UL)                     /*!< GPIO64OUTCFG (Bit 1)                                  */
13516 #define GPIO_CFGI_GPIO64OUTCFG_Msk        (0x6UL)                   /*!< GPIO64OUTCFG (Bitfield-Mask: 0x03)                    */
13517 #define GPIO_CFGI_GPIO64INCFG_Pos         (0UL)                     /*!< GPIO64INCFG (Bit 0)                                   */
13518 #define GPIO_CFGI_GPIO64INCFG_Msk         (0x1UL)                   /*!< GPIO64INCFG (Bitfield-Mask: 0x01)                     */
13519 /* =========================================================  CFGJ  ========================================================== */
13520 #define GPIO_CFGJ_GPIO73INTD_Pos          (7UL)                     /*!< GPIO73INTD (Bit 7)                                    */
13521 #define GPIO_CFGJ_GPIO73INTD_Msk          (0x80UL)                  /*!< GPIO73INTD (Bitfield-Mask: 0x01)                      */
13522 #define GPIO_CFGJ_GPIO73OUTCFG_Pos        (5UL)                     /*!< GPIO73OUTCFG (Bit 5)                                  */
13523 #define GPIO_CFGJ_GPIO73OUTCFG_Msk        (0x60UL)                  /*!< GPIO73OUTCFG (Bitfield-Mask: 0x03)                    */
13524 #define GPIO_CFGJ_GPIO73INCFG_Pos         (4UL)                     /*!< GPIO73INCFG (Bit 4)                                   */
13525 #define GPIO_CFGJ_GPIO73INCFG_Msk         (0x10UL)                  /*!< GPIO73INCFG (Bitfield-Mask: 0x01)                     */
13526 #define GPIO_CFGJ_GPIO72INTD_Pos          (3UL)                     /*!< GPIO72INTD (Bit 3)                                    */
13527 #define GPIO_CFGJ_GPIO72INTD_Msk          (0x8UL)                   /*!< GPIO72INTD (Bitfield-Mask: 0x01)                      */
13528 #define GPIO_CFGJ_GPIO72OUTCFG_Pos        (1UL)                     /*!< GPIO72OUTCFG (Bit 1)                                  */
13529 #define GPIO_CFGJ_GPIO72OUTCFG_Msk        (0x6UL)                   /*!< GPIO72OUTCFG (Bitfield-Mask: 0x03)                    */
13530 #define GPIO_CFGJ_GPIO72INCFG_Pos         (0UL)                     /*!< GPIO72INCFG (Bit 0)                                   */
13531 #define GPIO_CFGJ_GPIO72INCFG_Msk         (0x1UL)                   /*!< GPIO72INCFG (Bitfield-Mask: 0x01)                     */
13532 /* ========================================================  PADKEY  ========================================================= */
13533 #define GPIO_PADKEY_PADKEY_Pos            (0UL)                     /*!< PADKEY (Bit 0)                                        */
13534 #define GPIO_PADKEY_PADKEY_Msk            (0xffffffffUL)            /*!< PADKEY (Bitfield-Mask: 0xffffffff)                    */
13535 /* ==========================================================  RDA  ========================================================== */
13536 #define GPIO_RDA_RDA_Pos                  (0UL)                     /*!< RDA (Bit 0)                                           */
13537 #define GPIO_RDA_RDA_Msk                  (0xffffffffUL)            /*!< RDA (Bitfield-Mask: 0xffffffff)                       */
13538 /* ==========================================================  RDB  ========================================================== */
13539 #define GPIO_RDB_RDB_Pos                  (0UL)                     /*!< RDB (Bit 0)                                           */
13540 #define GPIO_RDB_RDB_Msk                  (0xffffffffUL)            /*!< RDB (Bitfield-Mask: 0xffffffff)                       */
13541 /* ==========================================================  RDC  ========================================================== */
13542 #define GPIO_RDC_RDC_Pos                  (0UL)                     /*!< RDC (Bit 0)                                           */
13543 #define GPIO_RDC_RDC_Msk                  (0x3ffUL)                 /*!< RDC (Bitfield-Mask: 0x3ff)                            */
13544 /* ==========================================================  WTA  ========================================================== */
13545 #define GPIO_WTA_WTA_Pos                  (0UL)                     /*!< WTA (Bit 0)                                           */
13546 #define GPIO_WTA_WTA_Msk                  (0xffffffffUL)            /*!< WTA (Bitfield-Mask: 0xffffffff)                       */
13547 /* ==========================================================  WTB  ========================================================== */
13548 #define GPIO_WTB_WTB_Pos                  (0UL)                     /*!< WTB (Bit 0)                                           */
13549 #define GPIO_WTB_WTB_Msk                  (0xffffffffUL)            /*!< WTB (Bitfield-Mask: 0xffffffff)                       */
13550 /* ==========================================================  WTC  ========================================================== */
13551 #define GPIO_WTC_WTC_Pos                  (0UL)                     /*!< WTC (Bit 0)                                           */
13552 #define GPIO_WTC_WTC_Msk                  (0x3ffUL)                 /*!< WTC (Bitfield-Mask: 0x3ff)                            */
13553 /* =========================================================  WTSA  ========================================================== */
13554 #define GPIO_WTSA_WTSA_Pos                (0UL)                     /*!< WTSA (Bit 0)                                          */
13555 #define GPIO_WTSA_WTSA_Msk                (0xffffffffUL)            /*!< WTSA (Bitfield-Mask: 0xffffffff)                      */
13556 /* =========================================================  WTSB  ========================================================== */
13557 #define GPIO_WTSB_WTSB_Pos                (0UL)                     /*!< WTSB (Bit 0)                                          */
13558 #define GPIO_WTSB_WTSB_Msk                (0xffffffffUL)            /*!< WTSB (Bitfield-Mask: 0xffffffff)                      */
13559 /* =========================================================  WTSC  ========================================================== */
13560 #define GPIO_WTSC_WTSC_Pos                (0UL)                     /*!< WTSC (Bit 0)                                          */
13561 #define GPIO_WTSC_WTSC_Msk                (0x3ffUL)                 /*!< WTSC (Bitfield-Mask: 0x3ff)                           */
13562 /* =========================================================  WTCA  ========================================================== */
13563 #define GPIO_WTCA_WTCA_Pos                (0UL)                     /*!< WTCA (Bit 0)                                          */
13564 #define GPIO_WTCA_WTCA_Msk                (0xffffffffUL)            /*!< WTCA (Bitfield-Mask: 0xffffffff)                      */
13565 /* =========================================================  WTCB  ========================================================== */
13566 #define GPIO_WTCB_WTCB_Pos                (0UL)                     /*!< WTCB (Bit 0)                                          */
13567 #define GPIO_WTCB_WTCB_Msk                (0xffffffffUL)            /*!< WTCB (Bitfield-Mask: 0xffffffff)                      */
13568 /* =========================================================  WTCC  ========================================================== */
13569 #define GPIO_WTCC_WTCB_Pos                (0UL)                     /*!< WTCB (Bit 0)                                          */
13570 #define GPIO_WTCC_WTCB_Msk                (0x3ffUL)                 /*!< WTCB (Bitfield-Mask: 0x3ff)                           */
13571 /* ==========================================================  ENA  ========================================================== */
13572 #define GPIO_ENA_ENA_Pos                  (0UL)                     /*!< ENA (Bit 0)                                           */
13573 #define GPIO_ENA_ENA_Msk                  (0xffffffffUL)            /*!< ENA (Bitfield-Mask: 0xffffffff)                       */
13574 /* ==========================================================  ENB  ========================================================== */
13575 #define GPIO_ENB_ENB_Pos                  (0UL)                     /*!< ENB (Bit 0)                                           */
13576 #define GPIO_ENB_ENB_Msk                  (0xffffffffUL)            /*!< ENB (Bitfield-Mask: 0xffffffff)                       */
13577 /* ==========================================================  ENC  ========================================================== */
13578 #define GPIO_ENC_ENC_Pos                  (0UL)                     /*!< ENC (Bit 0)                                           */
13579 #define GPIO_ENC_ENC_Msk                  (0x3ffUL)                 /*!< ENC (Bitfield-Mask: 0x3ff)                            */
13580 /* =========================================================  ENSA  ========================================================== */
13581 #define GPIO_ENSA_ENSA_Pos                (0UL)                     /*!< ENSA (Bit 0)                                          */
13582 #define GPIO_ENSA_ENSA_Msk                (0xffffffffUL)            /*!< ENSA (Bitfield-Mask: 0xffffffff)                      */
13583 /* =========================================================  ENSB  ========================================================== */
13584 #define GPIO_ENSB_ENSB_Pos                (0UL)                     /*!< ENSB (Bit 0)                                          */
13585 #define GPIO_ENSB_ENSB_Msk                (0xffffffffUL)            /*!< ENSB (Bitfield-Mask: 0xffffffff)                      */
13586 /* =========================================================  ENSC  ========================================================== */
13587 #define GPIO_ENSC_ENSC_Pos                (0UL)                     /*!< ENSC (Bit 0)                                          */
13588 #define GPIO_ENSC_ENSC_Msk                (0x3ffUL)                 /*!< ENSC (Bitfield-Mask: 0x3ff)                           */
13589 /* =========================================================  ENCA  ========================================================== */
13590 #define GPIO_ENCA_ENCA_Pos                (0UL)                     /*!< ENCA (Bit 0)                                          */
13591 #define GPIO_ENCA_ENCA_Msk                (0xffffffffUL)            /*!< ENCA (Bitfield-Mask: 0xffffffff)                      */
13592 /* =========================================================  ENCB  ========================================================== */
13593 #define GPIO_ENCB_ENCB_Pos                (0UL)                     /*!< ENCB (Bit 0)                                          */
13594 #define GPIO_ENCB_ENCB_Msk                (0xffffffffUL)            /*!< ENCB (Bitfield-Mask: 0xffffffff)                      */
13595 /* =========================================================  ENCC  ========================================================== */
13596 #define GPIO_ENCC_ENCC_Pos                (0UL)                     /*!< ENCC (Bit 0)                                          */
13597 #define GPIO_ENCC_ENCC_Msk                (0x3ffUL)                 /*!< ENCC (Bitfield-Mask: 0x3ff)                           */
13598 /* ========================================================  STMRCAP  ======================================================== */
13599 #define GPIO_STMRCAP_STPOL3_Pos           (31UL)                    /*!< STPOL3 (Bit 31)                                       */
13600 #define GPIO_STMRCAP_STPOL3_Msk           (0x80000000UL)            /*!< STPOL3 (Bitfield-Mask: 0x01)                          */
13601 #define GPIO_STMRCAP_STSEL3_Pos           (24UL)                    /*!< STSEL3 (Bit 24)                                       */
13602 #define GPIO_STMRCAP_STSEL3_Msk           (0x7f000000UL)            /*!< STSEL3 (Bitfield-Mask: 0x7f)                          */
13603 #define GPIO_STMRCAP_STPOL2_Pos           (23UL)                    /*!< STPOL2 (Bit 23)                                       */
13604 #define GPIO_STMRCAP_STPOL2_Msk           (0x800000UL)              /*!< STPOL2 (Bitfield-Mask: 0x01)                          */
13605 #define GPIO_STMRCAP_STSEL2_Pos           (16UL)                    /*!< STSEL2 (Bit 16)                                       */
13606 #define GPIO_STMRCAP_STSEL2_Msk           (0x7f0000UL)              /*!< STSEL2 (Bitfield-Mask: 0x7f)                          */
13607 #define GPIO_STMRCAP_STPOL1_Pos           (15UL)                    /*!< STPOL1 (Bit 15)                                       */
13608 #define GPIO_STMRCAP_STPOL1_Msk           (0x8000UL)                /*!< STPOL1 (Bitfield-Mask: 0x01)                          */
13609 #define GPIO_STMRCAP_STSEL1_Pos           (8UL)                     /*!< STSEL1 (Bit 8)                                        */
13610 #define GPIO_STMRCAP_STSEL1_Msk           (0x7f00UL)                /*!< STSEL1 (Bitfield-Mask: 0x7f)                          */
13611 #define GPIO_STMRCAP_STPOL0_Pos           (7UL)                     /*!< STPOL0 (Bit 7)                                        */
13612 #define GPIO_STMRCAP_STPOL0_Msk           (0x80UL)                  /*!< STPOL0 (Bitfield-Mask: 0x01)                          */
13613 #define GPIO_STMRCAP_STSEL0_Pos           (0UL)                     /*!< STSEL0 (Bit 0)                                        */
13614 #define GPIO_STMRCAP_STSEL0_Msk           (0x7fUL)                  /*!< STSEL0 (Bitfield-Mask: 0x7f)                          */
13615 /* ========================================================  IOM0IRQ  ======================================================== */
13616 #define GPIO_IOM0IRQ_IOM0IRQ_Pos          (0UL)                     /*!< IOM0IRQ (Bit 0)                                       */
13617 #define GPIO_IOM0IRQ_IOM0IRQ_Msk          (0x7fUL)                  /*!< IOM0IRQ (Bitfield-Mask: 0x7f)                         */
13618 /* ========================================================  IOM1IRQ  ======================================================== */
13619 #define GPIO_IOM1IRQ_IOM1IRQ_Pos          (0UL)                     /*!< IOM1IRQ (Bit 0)                                       */
13620 #define GPIO_IOM1IRQ_IOM1IRQ_Msk          (0x7fUL)                  /*!< IOM1IRQ (Bitfield-Mask: 0x7f)                         */
13621 /* ========================================================  IOM2IRQ  ======================================================== */
13622 #define GPIO_IOM2IRQ_IOM2IRQ_Pos          (0UL)                     /*!< IOM2IRQ (Bit 0)                                       */
13623 #define GPIO_IOM2IRQ_IOM2IRQ_Msk          (0x7fUL)                  /*!< IOM2IRQ (Bitfield-Mask: 0x7f)                         */
13624 /* ========================================================  IOM3IRQ  ======================================================== */
13625 #define GPIO_IOM3IRQ_IOM3IRQ_Pos          (0UL)                     /*!< IOM3IRQ (Bit 0)                                       */
13626 #define GPIO_IOM3IRQ_IOM3IRQ_Msk          (0x7fUL)                  /*!< IOM3IRQ (Bitfield-Mask: 0x7f)                         */
13627 /* ========================================================  IOM4IRQ  ======================================================== */
13628 #define GPIO_IOM4IRQ_IOM4IRQ_Pos          (0UL)                     /*!< IOM4IRQ (Bit 0)                                       */
13629 #define GPIO_IOM4IRQ_IOM4IRQ_Msk          (0x7fUL)                  /*!< IOM4IRQ (Bitfield-Mask: 0x7f)                         */
13630 /* ========================================================  IOM5IRQ  ======================================================== */
13631 #define GPIO_IOM5IRQ_IOM5IRQ_Pos          (0UL)                     /*!< IOM5IRQ (Bit 0)                                       */
13632 #define GPIO_IOM5IRQ_IOM5IRQ_Msk          (0x7fUL)                  /*!< IOM5IRQ (Bitfield-Mask: 0x7f)                         */
13633 /* =======================================================  BLEIFIRQ  ======================================================== */
13634 #define GPIO_BLEIFIRQ_BLEIFIRQ_Pos        (0UL)                     /*!< BLEIFIRQ (Bit 0)                                      */
13635 #define GPIO_BLEIFIRQ_BLEIFIRQ_Msk        (0x7fUL)                  /*!< BLEIFIRQ (Bitfield-Mask: 0x7f)                        */
13636 /* ========================================================  GPIOOBS  ======================================================== */
13637 #define GPIO_GPIOOBS_OBS_DATA_Pos         (0UL)                     /*!< OBS_DATA (Bit 0)                                      */
13638 #define GPIO_GPIOOBS_OBS_DATA_Msk         (0xffffUL)                /*!< OBS_DATA (Bitfield-Mask: 0xffff)                      */
13639 /* ======================================================  ALTPADCFGA  ======================================================= */
13640 #define GPIO_ALTPADCFGA_PAD3_SR_Pos       (28UL)                    /*!< PAD3_SR (Bit 28)                                      */
13641 #define GPIO_ALTPADCFGA_PAD3_SR_Msk       (0x10000000UL)            /*!< PAD3_SR (Bitfield-Mask: 0x01)                         */
13642 #define GPIO_ALTPADCFGA_PAD3_DS1_Pos      (24UL)                    /*!< PAD3_DS1 (Bit 24)                                     */
13643 #define GPIO_ALTPADCFGA_PAD3_DS1_Msk      (0x1000000UL)             /*!< PAD3_DS1 (Bitfield-Mask: 0x01)                        */
13644 #define GPIO_ALTPADCFGA_PAD2_SR_Pos       (20UL)                    /*!< PAD2_SR (Bit 20)                                      */
13645 #define GPIO_ALTPADCFGA_PAD2_SR_Msk       (0x100000UL)              /*!< PAD2_SR (Bitfield-Mask: 0x01)                         */
13646 #define GPIO_ALTPADCFGA_PAD2_DS1_Pos      (16UL)                    /*!< PAD2_DS1 (Bit 16)                                     */
13647 #define GPIO_ALTPADCFGA_PAD2_DS1_Msk      (0x10000UL)               /*!< PAD2_DS1 (Bitfield-Mask: 0x01)                        */
13648 #define GPIO_ALTPADCFGA_PAD1_SR_Pos       (12UL)                    /*!< PAD1_SR (Bit 12)                                      */
13649 #define GPIO_ALTPADCFGA_PAD1_SR_Msk       (0x1000UL)                /*!< PAD1_SR (Bitfield-Mask: 0x01)                         */
13650 #define GPIO_ALTPADCFGA_PAD1_DS1_Pos      (8UL)                     /*!< PAD1_DS1 (Bit 8)                                      */
13651 #define GPIO_ALTPADCFGA_PAD1_DS1_Msk      (0x100UL)                 /*!< PAD1_DS1 (Bitfield-Mask: 0x01)                        */
13652 #define GPIO_ALTPADCFGA_PAD0_SR_Pos       (4UL)                     /*!< PAD0_SR (Bit 4)                                       */
13653 #define GPIO_ALTPADCFGA_PAD0_SR_Msk       (0x10UL)                  /*!< PAD0_SR (Bitfield-Mask: 0x01)                         */
13654 #define GPIO_ALTPADCFGA_PAD0_DS1_Pos      (0UL)                     /*!< PAD0_DS1 (Bit 0)                                      */
13655 #define GPIO_ALTPADCFGA_PAD0_DS1_Msk      (0x1UL)                   /*!< PAD0_DS1 (Bitfield-Mask: 0x01)                        */
13656 /* ======================================================  ALTPADCFGB  ======================================================= */
13657 #define GPIO_ALTPADCFGB_PAD7_SR_Pos       (28UL)                    /*!< PAD7_SR (Bit 28)                                      */
13658 #define GPIO_ALTPADCFGB_PAD7_SR_Msk       (0x10000000UL)            /*!< PAD7_SR (Bitfield-Mask: 0x01)                         */
13659 #define GPIO_ALTPADCFGB_PAD7_DS1_Pos      (24UL)                    /*!< PAD7_DS1 (Bit 24)                                     */
13660 #define GPIO_ALTPADCFGB_PAD7_DS1_Msk      (0x1000000UL)             /*!< PAD7_DS1 (Bitfield-Mask: 0x01)                        */
13661 #define GPIO_ALTPADCFGB_PAD6_SR_Pos       (20UL)                    /*!< PAD6_SR (Bit 20)                                      */
13662 #define GPIO_ALTPADCFGB_PAD6_SR_Msk       (0x100000UL)              /*!< PAD6_SR (Bitfield-Mask: 0x01)                         */
13663 #define GPIO_ALTPADCFGB_PAD6_DS1_Pos      (16UL)                    /*!< PAD6_DS1 (Bit 16)                                     */
13664 #define GPIO_ALTPADCFGB_PAD6_DS1_Msk      (0x10000UL)               /*!< PAD6_DS1 (Bitfield-Mask: 0x01)                        */
13665 #define GPIO_ALTPADCFGB_PAD5_SR_Pos       (12UL)                    /*!< PAD5_SR (Bit 12)                                      */
13666 #define GPIO_ALTPADCFGB_PAD5_SR_Msk       (0x1000UL)                /*!< PAD5_SR (Bitfield-Mask: 0x01)                         */
13667 #define GPIO_ALTPADCFGB_PAD5_DS1_Pos      (8UL)                     /*!< PAD5_DS1 (Bit 8)                                      */
13668 #define GPIO_ALTPADCFGB_PAD5_DS1_Msk      (0x100UL)                 /*!< PAD5_DS1 (Bitfield-Mask: 0x01)                        */
13669 #define GPIO_ALTPADCFGB_PAD4_SR_Pos       (4UL)                     /*!< PAD4_SR (Bit 4)                                       */
13670 #define GPIO_ALTPADCFGB_PAD4_SR_Msk       (0x10UL)                  /*!< PAD4_SR (Bitfield-Mask: 0x01)                         */
13671 #define GPIO_ALTPADCFGB_PAD4_DS1_Pos      (0UL)                     /*!< PAD4_DS1 (Bit 0)                                      */
13672 #define GPIO_ALTPADCFGB_PAD4_DS1_Msk      (0x1UL)                   /*!< PAD4_DS1 (Bitfield-Mask: 0x01)                        */
13673 /* ======================================================  ALTPADCFGC  ======================================================= */
13674 #define GPIO_ALTPADCFGC_PAD11_SR_Pos      (28UL)                    /*!< PAD11_SR (Bit 28)                                     */
13675 #define GPIO_ALTPADCFGC_PAD11_SR_Msk      (0x10000000UL)            /*!< PAD11_SR (Bitfield-Mask: 0x01)                        */
13676 #define GPIO_ALTPADCFGC_PAD11_DS1_Pos     (24UL)                    /*!< PAD11_DS1 (Bit 24)                                    */
13677 #define GPIO_ALTPADCFGC_PAD11_DS1_Msk     (0x1000000UL)             /*!< PAD11_DS1 (Bitfield-Mask: 0x01)                       */
13678 #define GPIO_ALTPADCFGC_PAD10_SR_Pos      (20UL)                    /*!< PAD10_SR (Bit 20)                                     */
13679 #define GPIO_ALTPADCFGC_PAD10_SR_Msk      (0x100000UL)              /*!< PAD10_SR (Bitfield-Mask: 0x01)                        */
13680 #define GPIO_ALTPADCFGC_PAD10_DS1_Pos     (16UL)                    /*!< PAD10_DS1 (Bit 16)                                    */
13681 #define GPIO_ALTPADCFGC_PAD10_DS1_Msk     (0x10000UL)               /*!< PAD10_DS1 (Bitfield-Mask: 0x01)                       */
13682 #define GPIO_ALTPADCFGC_PAD9_SR_Pos       (12UL)                    /*!< PAD9_SR (Bit 12)                                      */
13683 #define GPIO_ALTPADCFGC_PAD9_SR_Msk       (0x1000UL)                /*!< PAD9_SR (Bitfield-Mask: 0x01)                         */
13684 #define GPIO_ALTPADCFGC_PAD9_DS1_Pos      (8UL)                     /*!< PAD9_DS1 (Bit 8)                                      */
13685 #define GPIO_ALTPADCFGC_PAD9_DS1_Msk      (0x100UL)                 /*!< PAD9_DS1 (Bitfield-Mask: 0x01)                        */
13686 #define GPIO_ALTPADCFGC_PAD8_SR_Pos       (4UL)                     /*!< PAD8_SR (Bit 4)                                       */
13687 #define GPIO_ALTPADCFGC_PAD8_SR_Msk       (0x10UL)                  /*!< PAD8_SR (Bitfield-Mask: 0x01)                         */
13688 #define GPIO_ALTPADCFGC_PAD8_DS1_Pos      (0UL)                     /*!< PAD8_DS1 (Bit 0)                                      */
13689 #define GPIO_ALTPADCFGC_PAD8_DS1_Msk      (0x1UL)                   /*!< PAD8_DS1 (Bitfield-Mask: 0x01)                        */
13690 /* ======================================================  ALTPADCFGD  ======================================================= */
13691 #define GPIO_ALTPADCFGD_PAD15_SR_Pos      (28UL)                    /*!< PAD15_SR (Bit 28)                                     */
13692 #define GPIO_ALTPADCFGD_PAD15_SR_Msk      (0x10000000UL)            /*!< PAD15_SR (Bitfield-Mask: 0x01)                        */
13693 #define GPIO_ALTPADCFGD_PAD15_DS1_Pos     (24UL)                    /*!< PAD15_DS1 (Bit 24)                                    */
13694 #define GPIO_ALTPADCFGD_PAD15_DS1_Msk     (0x1000000UL)             /*!< PAD15_DS1 (Bitfield-Mask: 0x01)                       */
13695 #define GPIO_ALTPADCFGD_PAD14_SR_Pos      (20UL)                    /*!< PAD14_SR (Bit 20)                                     */
13696 #define GPIO_ALTPADCFGD_PAD14_SR_Msk      (0x100000UL)              /*!< PAD14_SR (Bitfield-Mask: 0x01)                        */
13697 #define GPIO_ALTPADCFGD_PAD14_DS1_Pos     (16UL)                    /*!< PAD14_DS1 (Bit 16)                                    */
13698 #define GPIO_ALTPADCFGD_PAD14_DS1_Msk     (0x10000UL)               /*!< PAD14_DS1 (Bitfield-Mask: 0x01)                       */
13699 #define GPIO_ALTPADCFGD_PAD13_SR_Pos      (12UL)                    /*!< PAD13_SR (Bit 12)                                     */
13700 #define GPIO_ALTPADCFGD_PAD13_SR_Msk      (0x1000UL)                /*!< PAD13_SR (Bitfield-Mask: 0x01)                        */
13701 #define GPIO_ALTPADCFGD_PAD13_DS1_Pos     (8UL)                     /*!< PAD13_DS1 (Bit 8)                                     */
13702 #define GPIO_ALTPADCFGD_PAD13_DS1_Msk     (0x100UL)                 /*!< PAD13_DS1 (Bitfield-Mask: 0x01)                       */
13703 #define GPIO_ALTPADCFGD_PAD12_SR_Pos      (4UL)                     /*!< PAD12_SR (Bit 4)                                      */
13704 #define GPIO_ALTPADCFGD_PAD12_SR_Msk      (0x10UL)                  /*!< PAD12_SR (Bitfield-Mask: 0x01)                        */
13705 #define GPIO_ALTPADCFGD_PAD12_DS1_Pos     (0UL)                     /*!< PAD12_DS1 (Bit 0)                                     */
13706 #define GPIO_ALTPADCFGD_PAD12_DS1_Msk     (0x1UL)                   /*!< PAD12_DS1 (Bitfield-Mask: 0x01)                       */
13707 /* ======================================================  ALTPADCFGE  ======================================================= */
13708 #define GPIO_ALTPADCFGE_PAD19_SR_Pos      (28UL)                    /*!< PAD19_SR (Bit 28)                                     */
13709 #define GPIO_ALTPADCFGE_PAD19_SR_Msk      (0x10000000UL)            /*!< PAD19_SR (Bitfield-Mask: 0x01)                        */
13710 #define GPIO_ALTPADCFGE_PAD19_DS1_Pos     (24UL)                    /*!< PAD19_DS1 (Bit 24)                                    */
13711 #define GPIO_ALTPADCFGE_PAD19_DS1_Msk     (0x1000000UL)             /*!< PAD19_DS1 (Bitfield-Mask: 0x01)                       */
13712 #define GPIO_ALTPADCFGE_PAD18_SR_Pos      (20UL)                    /*!< PAD18_SR (Bit 20)                                     */
13713 #define GPIO_ALTPADCFGE_PAD18_SR_Msk      (0x100000UL)              /*!< PAD18_SR (Bitfield-Mask: 0x01)                        */
13714 #define GPIO_ALTPADCFGE_PAD18_DS1_Pos     (16UL)                    /*!< PAD18_DS1 (Bit 16)                                    */
13715 #define GPIO_ALTPADCFGE_PAD18_DS1_Msk     (0x10000UL)               /*!< PAD18_DS1 (Bitfield-Mask: 0x01)                       */
13716 #define GPIO_ALTPADCFGE_PAD17_SR_Pos      (12UL)                    /*!< PAD17_SR (Bit 12)                                     */
13717 #define GPIO_ALTPADCFGE_PAD17_SR_Msk      (0x1000UL)                /*!< PAD17_SR (Bitfield-Mask: 0x01)                        */
13718 #define GPIO_ALTPADCFGE_PAD17_DS1_Pos     (8UL)                     /*!< PAD17_DS1 (Bit 8)                                     */
13719 #define GPIO_ALTPADCFGE_PAD17_DS1_Msk     (0x100UL)                 /*!< PAD17_DS1 (Bitfield-Mask: 0x01)                       */
13720 #define GPIO_ALTPADCFGE_PAD16_SR_Pos      (4UL)                     /*!< PAD16_SR (Bit 4)                                      */
13721 #define GPIO_ALTPADCFGE_PAD16_SR_Msk      (0x10UL)                  /*!< PAD16_SR (Bitfield-Mask: 0x01)                        */
13722 #define GPIO_ALTPADCFGE_PAD16_DS1_Pos     (0UL)                     /*!< PAD16_DS1 (Bit 0)                                     */
13723 #define GPIO_ALTPADCFGE_PAD16_DS1_Msk     (0x1UL)                   /*!< PAD16_DS1 (Bitfield-Mask: 0x01)                       */
13724 /* ======================================================  ALTPADCFGF  ======================================================= */
13725 #define GPIO_ALTPADCFGF_PAD23_SR_Pos      (28UL)                    /*!< PAD23_SR (Bit 28)                                     */
13726 #define GPIO_ALTPADCFGF_PAD23_SR_Msk      (0x10000000UL)            /*!< PAD23_SR (Bitfield-Mask: 0x01)                        */
13727 #define GPIO_ALTPADCFGF_PAD23_DS1_Pos     (24UL)                    /*!< PAD23_DS1 (Bit 24)                                    */
13728 #define GPIO_ALTPADCFGF_PAD23_DS1_Msk     (0x1000000UL)             /*!< PAD23_DS1 (Bitfield-Mask: 0x01)                       */
13729 #define GPIO_ALTPADCFGF_PAD22_SR_Pos      (20UL)                    /*!< PAD22_SR (Bit 20)                                     */
13730 #define GPIO_ALTPADCFGF_PAD22_SR_Msk      (0x100000UL)              /*!< PAD22_SR (Bitfield-Mask: 0x01)                        */
13731 #define GPIO_ALTPADCFGF_PAD22_DS1_Pos     (16UL)                    /*!< PAD22_DS1 (Bit 16)                                    */
13732 #define GPIO_ALTPADCFGF_PAD22_DS1_Msk     (0x10000UL)               /*!< PAD22_DS1 (Bitfield-Mask: 0x01)                       */
13733 #define GPIO_ALTPADCFGF_PAD21_SR_Pos      (12UL)                    /*!< PAD21_SR (Bit 12)                                     */
13734 #define GPIO_ALTPADCFGF_PAD21_SR_Msk      (0x1000UL)                /*!< PAD21_SR (Bitfield-Mask: 0x01)                        */
13735 #define GPIO_ALTPADCFGF_PAD21_DS1_Pos     (8UL)                     /*!< PAD21_DS1 (Bit 8)                                     */
13736 #define GPIO_ALTPADCFGF_PAD21_DS1_Msk     (0x100UL)                 /*!< PAD21_DS1 (Bitfield-Mask: 0x01)                       */
13737 #define GPIO_ALTPADCFGF_PAD20_SR_Pos      (4UL)                     /*!< PAD20_SR (Bit 4)                                      */
13738 #define GPIO_ALTPADCFGF_PAD20_SR_Msk      (0x10UL)                  /*!< PAD20_SR (Bitfield-Mask: 0x01)                        */
13739 #define GPIO_ALTPADCFGF_PAD20_DS1_Pos     (0UL)                     /*!< PAD20_DS1 (Bit 0)                                     */
13740 #define GPIO_ALTPADCFGF_PAD20_DS1_Msk     (0x1UL)                   /*!< PAD20_DS1 (Bitfield-Mask: 0x01)                       */
13741 /* ======================================================  ALTPADCFGG  ======================================================= */
13742 #define GPIO_ALTPADCFGG_PAD27_SR_Pos      (28UL)                    /*!< PAD27_SR (Bit 28)                                     */
13743 #define GPIO_ALTPADCFGG_PAD27_SR_Msk      (0x10000000UL)            /*!< PAD27_SR (Bitfield-Mask: 0x01)                        */
13744 #define GPIO_ALTPADCFGG_PAD27_DS1_Pos     (24UL)                    /*!< PAD27_DS1 (Bit 24)                                    */
13745 #define GPIO_ALTPADCFGG_PAD27_DS1_Msk     (0x1000000UL)             /*!< PAD27_DS1 (Bitfield-Mask: 0x01)                       */
13746 #define GPIO_ALTPADCFGG_PAD26_SR_Pos      (20UL)                    /*!< PAD26_SR (Bit 20)                                     */
13747 #define GPIO_ALTPADCFGG_PAD26_SR_Msk      (0x100000UL)              /*!< PAD26_SR (Bitfield-Mask: 0x01)                        */
13748 #define GPIO_ALTPADCFGG_PAD26_DS1_Pos     (16UL)                    /*!< PAD26_DS1 (Bit 16)                                    */
13749 #define GPIO_ALTPADCFGG_PAD26_DS1_Msk     (0x10000UL)               /*!< PAD26_DS1 (Bitfield-Mask: 0x01)                       */
13750 #define GPIO_ALTPADCFGG_PAD25_SR_Pos      (12UL)                    /*!< PAD25_SR (Bit 12)                                     */
13751 #define GPIO_ALTPADCFGG_PAD25_SR_Msk      (0x1000UL)                /*!< PAD25_SR (Bitfield-Mask: 0x01)                        */
13752 #define GPIO_ALTPADCFGG_PAD25_DS1_Pos     (8UL)                     /*!< PAD25_DS1 (Bit 8)                                     */
13753 #define GPIO_ALTPADCFGG_PAD25_DS1_Msk     (0x100UL)                 /*!< PAD25_DS1 (Bitfield-Mask: 0x01)                       */
13754 #define GPIO_ALTPADCFGG_PAD24_SR_Pos      (4UL)                     /*!< PAD24_SR (Bit 4)                                      */
13755 #define GPIO_ALTPADCFGG_PAD24_SR_Msk      (0x10UL)                  /*!< PAD24_SR (Bitfield-Mask: 0x01)                        */
13756 #define GPIO_ALTPADCFGG_PAD24_DS1_Pos     (0UL)                     /*!< PAD24_DS1 (Bit 0)                                     */
13757 #define GPIO_ALTPADCFGG_PAD24_DS1_Msk     (0x1UL)                   /*!< PAD24_DS1 (Bitfield-Mask: 0x01)                       */
13758 /* ======================================================  ALTPADCFGH  ======================================================= */
13759 #define GPIO_ALTPADCFGH_PAD31_SR_Pos      (28UL)                    /*!< PAD31_SR (Bit 28)                                     */
13760 #define GPIO_ALTPADCFGH_PAD31_SR_Msk      (0x10000000UL)            /*!< PAD31_SR (Bitfield-Mask: 0x01)                        */
13761 #define GPIO_ALTPADCFGH_PAD31_DS1_Pos     (24UL)                    /*!< PAD31_DS1 (Bit 24)                                    */
13762 #define GPIO_ALTPADCFGH_PAD31_DS1_Msk     (0x1000000UL)             /*!< PAD31_DS1 (Bitfield-Mask: 0x01)                       */
13763 #define GPIO_ALTPADCFGH_PAD30_SR_Pos      (20UL)                    /*!< PAD30_SR (Bit 20)                                     */
13764 #define GPIO_ALTPADCFGH_PAD30_SR_Msk      (0x100000UL)              /*!< PAD30_SR (Bitfield-Mask: 0x01)                        */
13765 #define GPIO_ALTPADCFGH_PAD30_DS1_Pos     (16UL)                    /*!< PAD30_DS1 (Bit 16)                                    */
13766 #define GPIO_ALTPADCFGH_PAD30_DS1_Msk     (0x10000UL)               /*!< PAD30_DS1 (Bitfield-Mask: 0x01)                       */
13767 #define GPIO_ALTPADCFGH_PAD29_SR_Pos      (12UL)                    /*!< PAD29_SR (Bit 12)                                     */
13768 #define GPIO_ALTPADCFGH_PAD29_SR_Msk      (0x1000UL)                /*!< PAD29_SR (Bitfield-Mask: 0x01)                        */
13769 #define GPIO_ALTPADCFGH_PAD29_DS1_Pos     (8UL)                     /*!< PAD29_DS1 (Bit 8)                                     */
13770 #define GPIO_ALTPADCFGH_PAD29_DS1_Msk     (0x100UL)                 /*!< PAD29_DS1 (Bitfield-Mask: 0x01)                       */
13771 #define GPIO_ALTPADCFGH_PAD28_SR_Pos      (4UL)                     /*!< PAD28_SR (Bit 4)                                      */
13772 #define GPIO_ALTPADCFGH_PAD28_SR_Msk      (0x10UL)                  /*!< PAD28_SR (Bitfield-Mask: 0x01)                        */
13773 #define GPIO_ALTPADCFGH_PAD28_DS1_Pos     (0UL)                     /*!< PAD28_DS1 (Bit 0)                                     */
13774 #define GPIO_ALTPADCFGH_PAD28_DS1_Msk     (0x1UL)                   /*!< PAD28_DS1 (Bitfield-Mask: 0x01)                       */
13775 /* ======================================================  ALTPADCFGI  ======================================================= */
13776 #define GPIO_ALTPADCFGI_PAD35_SR_Pos      (28UL)                    /*!< PAD35_SR (Bit 28)                                     */
13777 #define GPIO_ALTPADCFGI_PAD35_SR_Msk      (0x10000000UL)            /*!< PAD35_SR (Bitfield-Mask: 0x01)                        */
13778 #define GPIO_ALTPADCFGI_PAD35_DS1_Pos     (24UL)                    /*!< PAD35_DS1 (Bit 24)                                    */
13779 #define GPIO_ALTPADCFGI_PAD35_DS1_Msk     (0x1000000UL)             /*!< PAD35_DS1 (Bitfield-Mask: 0x01)                       */
13780 #define GPIO_ALTPADCFGI_PAD34_SR_Pos      (20UL)                    /*!< PAD34_SR (Bit 20)                                     */
13781 #define GPIO_ALTPADCFGI_PAD34_SR_Msk      (0x100000UL)              /*!< PAD34_SR (Bitfield-Mask: 0x01)                        */
13782 #define GPIO_ALTPADCFGI_PAD34_DS1_Pos     (16UL)                    /*!< PAD34_DS1 (Bit 16)                                    */
13783 #define GPIO_ALTPADCFGI_PAD34_DS1_Msk     (0x10000UL)               /*!< PAD34_DS1 (Bitfield-Mask: 0x01)                       */
13784 #define GPIO_ALTPADCFGI_PAD33_SR_Pos      (12UL)                    /*!< PAD33_SR (Bit 12)                                     */
13785 #define GPIO_ALTPADCFGI_PAD33_SR_Msk      (0x1000UL)                /*!< PAD33_SR (Bitfield-Mask: 0x01)                        */
13786 #define GPIO_ALTPADCFGI_PAD33_DS1_Pos     (8UL)                     /*!< PAD33_DS1 (Bit 8)                                     */
13787 #define GPIO_ALTPADCFGI_PAD33_DS1_Msk     (0x100UL)                 /*!< PAD33_DS1 (Bitfield-Mask: 0x01)                       */
13788 #define GPIO_ALTPADCFGI_PAD32_SR_Pos      (4UL)                     /*!< PAD32_SR (Bit 4)                                      */
13789 #define GPIO_ALTPADCFGI_PAD32_SR_Msk      (0x10UL)                  /*!< PAD32_SR (Bitfield-Mask: 0x01)                        */
13790 #define GPIO_ALTPADCFGI_PAD32_DS1_Pos     (0UL)                     /*!< PAD32_DS1 (Bit 0)                                     */
13791 #define GPIO_ALTPADCFGI_PAD32_DS1_Msk     (0x1UL)                   /*!< PAD32_DS1 (Bitfield-Mask: 0x01)                       */
13792 /* ======================================================  ALTPADCFGJ  ======================================================= */
13793 #define GPIO_ALTPADCFGJ_PAD39_SR_Pos      (28UL)                    /*!< PAD39_SR (Bit 28)                                     */
13794 #define GPIO_ALTPADCFGJ_PAD39_SR_Msk      (0x10000000UL)            /*!< PAD39_SR (Bitfield-Mask: 0x01)                        */
13795 #define GPIO_ALTPADCFGJ_PAD39_DS1_Pos     (24UL)                    /*!< PAD39_DS1 (Bit 24)                                    */
13796 #define GPIO_ALTPADCFGJ_PAD39_DS1_Msk     (0x1000000UL)             /*!< PAD39_DS1 (Bitfield-Mask: 0x01)                       */
13797 #define GPIO_ALTPADCFGJ_PAD38_SR_Pos      (20UL)                    /*!< PAD38_SR (Bit 20)                                     */
13798 #define GPIO_ALTPADCFGJ_PAD38_SR_Msk      (0x100000UL)              /*!< PAD38_SR (Bitfield-Mask: 0x01)                        */
13799 #define GPIO_ALTPADCFGJ_PAD38_DS1_Pos     (16UL)                    /*!< PAD38_DS1 (Bit 16)                                    */
13800 #define GPIO_ALTPADCFGJ_PAD38_DS1_Msk     (0x10000UL)               /*!< PAD38_DS1 (Bitfield-Mask: 0x01)                       */
13801 #define GPIO_ALTPADCFGJ_PAD37_SR_Pos      (12UL)                    /*!< PAD37_SR (Bit 12)                                     */
13802 #define GPIO_ALTPADCFGJ_PAD37_SR_Msk      (0x1000UL)                /*!< PAD37_SR (Bitfield-Mask: 0x01)                        */
13803 #define GPIO_ALTPADCFGJ_PAD37_DS1_Pos     (8UL)                     /*!< PAD37_DS1 (Bit 8)                                     */
13804 #define GPIO_ALTPADCFGJ_PAD37_DS1_Msk     (0x100UL)                 /*!< PAD37_DS1 (Bitfield-Mask: 0x01)                       */
13805 #define GPIO_ALTPADCFGJ_PAD36_SR_Pos      (4UL)                     /*!< PAD36_SR (Bit 4)                                      */
13806 #define GPIO_ALTPADCFGJ_PAD36_SR_Msk      (0x10UL)                  /*!< PAD36_SR (Bitfield-Mask: 0x01)                        */
13807 #define GPIO_ALTPADCFGJ_PAD36_DS1_Pos     (0UL)                     /*!< PAD36_DS1 (Bit 0)                                     */
13808 #define GPIO_ALTPADCFGJ_PAD36_DS1_Msk     (0x1UL)                   /*!< PAD36_DS1 (Bitfield-Mask: 0x01)                       */
13809 /* ======================================================  ALTPADCFGK  ======================================================= */
13810 #define GPIO_ALTPADCFGK_PAD43_SR_Pos      (28UL)                    /*!< PAD43_SR (Bit 28)                                     */
13811 #define GPIO_ALTPADCFGK_PAD43_SR_Msk      (0x10000000UL)            /*!< PAD43_SR (Bitfield-Mask: 0x01)                        */
13812 #define GPIO_ALTPADCFGK_PAD43_DS1_Pos     (24UL)                    /*!< PAD43_DS1 (Bit 24)                                    */
13813 #define GPIO_ALTPADCFGK_PAD43_DS1_Msk     (0x1000000UL)             /*!< PAD43_DS1 (Bitfield-Mask: 0x01)                       */
13814 #define GPIO_ALTPADCFGK_PAD42_SR_Pos      (20UL)                    /*!< PAD42_SR (Bit 20)                                     */
13815 #define GPIO_ALTPADCFGK_PAD42_SR_Msk      (0x100000UL)              /*!< PAD42_SR (Bitfield-Mask: 0x01)                        */
13816 #define GPIO_ALTPADCFGK_PAD42_DS1_Pos     (16UL)                    /*!< PAD42_DS1 (Bit 16)                                    */
13817 #define GPIO_ALTPADCFGK_PAD42_DS1_Msk     (0x10000UL)               /*!< PAD42_DS1 (Bitfield-Mask: 0x01)                       */
13818 #define GPIO_ALTPADCFGK_PAD41_SR_Pos      (12UL)                    /*!< PAD41_SR (Bit 12)                                     */
13819 #define GPIO_ALTPADCFGK_PAD41_SR_Msk      (0x1000UL)                /*!< PAD41_SR (Bitfield-Mask: 0x01)                        */
13820 #define GPIO_ALTPADCFGK_PAD41_DS1_Pos     (8UL)                     /*!< PAD41_DS1 (Bit 8)                                     */
13821 #define GPIO_ALTPADCFGK_PAD41_DS1_Msk     (0x100UL)                 /*!< PAD41_DS1 (Bitfield-Mask: 0x01)                       */
13822 #define GPIO_ALTPADCFGK_PAD40_SR_Pos      (4UL)                     /*!< PAD40_SR (Bit 4)                                      */
13823 #define GPIO_ALTPADCFGK_PAD40_SR_Msk      (0x10UL)                  /*!< PAD40_SR (Bitfield-Mask: 0x01)                        */
13824 #define GPIO_ALTPADCFGK_PAD40_DS1_Pos     (0UL)                     /*!< PAD40_DS1 (Bit 0)                                     */
13825 #define GPIO_ALTPADCFGK_PAD40_DS1_Msk     (0x1UL)                   /*!< PAD40_DS1 (Bitfield-Mask: 0x01)                       */
13826 /* ======================================================  ALTPADCFGL  ======================================================= */
13827 #define GPIO_ALTPADCFGL_PAD47_SR_Pos      (28UL)                    /*!< PAD47_SR (Bit 28)                                     */
13828 #define GPIO_ALTPADCFGL_PAD47_SR_Msk      (0x10000000UL)            /*!< PAD47_SR (Bitfield-Mask: 0x01)                        */
13829 #define GPIO_ALTPADCFGL_PAD47_DS1_Pos     (24UL)                    /*!< PAD47_DS1 (Bit 24)                                    */
13830 #define GPIO_ALTPADCFGL_PAD47_DS1_Msk     (0x1000000UL)             /*!< PAD47_DS1 (Bitfield-Mask: 0x01)                       */
13831 #define GPIO_ALTPADCFGL_PAD46_SR_Pos      (20UL)                    /*!< PAD46_SR (Bit 20)                                     */
13832 #define GPIO_ALTPADCFGL_PAD46_SR_Msk      (0x100000UL)              /*!< PAD46_SR (Bitfield-Mask: 0x01)                        */
13833 #define GPIO_ALTPADCFGL_PAD46_DS1_Pos     (16UL)                    /*!< PAD46_DS1 (Bit 16)                                    */
13834 #define GPIO_ALTPADCFGL_PAD46_DS1_Msk     (0x10000UL)               /*!< PAD46_DS1 (Bitfield-Mask: 0x01)                       */
13835 #define GPIO_ALTPADCFGL_PAD45_SR_Pos      (12UL)                    /*!< PAD45_SR (Bit 12)                                     */
13836 #define GPIO_ALTPADCFGL_PAD45_SR_Msk      (0x1000UL)                /*!< PAD45_SR (Bitfield-Mask: 0x01)                        */
13837 #define GPIO_ALTPADCFGL_PAD45_DS1_Pos     (8UL)                     /*!< PAD45_DS1 (Bit 8)                                     */
13838 #define GPIO_ALTPADCFGL_PAD45_DS1_Msk     (0x100UL)                 /*!< PAD45_DS1 (Bitfield-Mask: 0x01)                       */
13839 #define GPIO_ALTPADCFGL_PAD44_SR_Pos      (4UL)                     /*!< PAD44_SR (Bit 4)                                      */
13840 #define GPIO_ALTPADCFGL_PAD44_SR_Msk      (0x10UL)                  /*!< PAD44_SR (Bitfield-Mask: 0x01)                        */
13841 #define GPIO_ALTPADCFGL_PAD44_DS1_Pos     (0UL)                     /*!< PAD44_DS1 (Bit 0)                                     */
13842 #define GPIO_ALTPADCFGL_PAD44_DS1_Msk     (0x1UL)                   /*!< PAD44_DS1 (Bitfield-Mask: 0x01)                       */
13843 /* ======================================================  ALTPADCFGM  ======================================================= */
13844 #define GPIO_ALTPADCFGM_PAD51_SR_Pos      (28UL)                    /*!< PAD51_SR (Bit 28)                                     */
13845 #define GPIO_ALTPADCFGM_PAD51_SR_Msk      (0x10000000UL)            /*!< PAD51_SR (Bitfield-Mask: 0x01)                        */
13846 #define GPIO_ALTPADCFGM_PAD51_DS1_Pos     (24UL)                    /*!< PAD51_DS1 (Bit 24)                                    */
13847 #define GPIO_ALTPADCFGM_PAD51_DS1_Msk     (0x1000000UL)             /*!< PAD51_DS1 (Bitfield-Mask: 0x01)                       */
13848 #define GPIO_ALTPADCFGM_PAD50_SR_Pos      (20UL)                    /*!< PAD50_SR (Bit 20)                                     */
13849 #define GPIO_ALTPADCFGM_PAD50_SR_Msk      (0x100000UL)              /*!< PAD50_SR (Bitfield-Mask: 0x01)                        */
13850 #define GPIO_ALTPADCFGM_PAD50_DS1_Pos     (16UL)                    /*!< PAD50_DS1 (Bit 16)                                    */
13851 #define GPIO_ALTPADCFGM_PAD50_DS1_Msk     (0x10000UL)               /*!< PAD50_DS1 (Bitfield-Mask: 0x01)                       */
13852 #define GPIO_ALTPADCFGM_PAD49_SR_Pos      (12UL)                    /*!< PAD49_SR (Bit 12)                                     */
13853 #define GPIO_ALTPADCFGM_PAD49_SR_Msk      (0x1000UL)                /*!< PAD49_SR (Bitfield-Mask: 0x01)                        */
13854 #define GPIO_ALTPADCFGM_PAD49_DS1_Pos     (8UL)                     /*!< PAD49_DS1 (Bit 8)                                     */
13855 #define GPIO_ALTPADCFGM_PAD49_DS1_Msk     (0x100UL)                 /*!< PAD49_DS1 (Bitfield-Mask: 0x01)                       */
13856 #define GPIO_ALTPADCFGM_PAD48_SR_Pos      (4UL)                     /*!< PAD48_SR (Bit 4)                                      */
13857 #define GPIO_ALTPADCFGM_PAD48_SR_Msk      (0x10UL)                  /*!< PAD48_SR (Bitfield-Mask: 0x01)                        */
13858 #define GPIO_ALTPADCFGM_PAD48_DS1_Pos     (0UL)                     /*!< PAD48_DS1 (Bit 0)                                     */
13859 #define GPIO_ALTPADCFGM_PAD48_DS1_Msk     (0x1UL)                   /*!< PAD48_DS1 (Bitfield-Mask: 0x01)                       */
13860 /* ======================================================  ALTPADCFGN  ======================================================= */
13861 #define GPIO_ALTPADCFGN_PAD55_SR_Pos      (28UL)                    /*!< PAD55_SR (Bit 28)                                     */
13862 #define GPIO_ALTPADCFGN_PAD55_SR_Msk      (0x10000000UL)            /*!< PAD55_SR (Bitfield-Mask: 0x01)                        */
13863 #define GPIO_ALTPADCFGN_PAD55_DS1_Pos     (24UL)                    /*!< PAD55_DS1 (Bit 24)                                    */
13864 #define GPIO_ALTPADCFGN_PAD55_DS1_Msk     (0x1000000UL)             /*!< PAD55_DS1 (Bitfield-Mask: 0x01)                       */
13865 #define GPIO_ALTPADCFGN_PAD54_SR_Pos      (20UL)                    /*!< PAD54_SR (Bit 20)                                     */
13866 #define GPIO_ALTPADCFGN_PAD54_SR_Msk      (0x100000UL)              /*!< PAD54_SR (Bitfield-Mask: 0x01)                        */
13867 #define GPIO_ALTPADCFGN_PAD54_DS1_Pos     (16UL)                    /*!< PAD54_DS1 (Bit 16)                                    */
13868 #define GPIO_ALTPADCFGN_PAD54_DS1_Msk     (0x10000UL)               /*!< PAD54_DS1 (Bitfield-Mask: 0x01)                       */
13869 #define GPIO_ALTPADCFGN_PAD53_SR_Pos      (12UL)                    /*!< PAD53_SR (Bit 12)                                     */
13870 #define GPIO_ALTPADCFGN_PAD53_SR_Msk      (0x1000UL)                /*!< PAD53_SR (Bitfield-Mask: 0x01)                        */
13871 #define GPIO_ALTPADCFGN_PAD53_DS1_Pos     (8UL)                     /*!< PAD53_DS1 (Bit 8)                                     */
13872 #define GPIO_ALTPADCFGN_PAD53_DS1_Msk     (0x100UL)                 /*!< PAD53_DS1 (Bitfield-Mask: 0x01)                       */
13873 #define GPIO_ALTPADCFGN_PAD52_SR_Pos      (4UL)                     /*!< PAD52_SR (Bit 4)                                      */
13874 #define GPIO_ALTPADCFGN_PAD52_SR_Msk      (0x10UL)                  /*!< PAD52_SR (Bitfield-Mask: 0x01)                        */
13875 #define GPIO_ALTPADCFGN_PAD52_DS1_Pos     (0UL)                     /*!< PAD52_DS1 (Bit 0)                                     */
13876 #define GPIO_ALTPADCFGN_PAD52_DS1_Msk     (0x1UL)                   /*!< PAD52_DS1 (Bitfield-Mask: 0x01)                       */
13877 /* ======================================================  ALTPADCFGO  ======================================================= */
13878 #define GPIO_ALTPADCFGO_PAD59_SR_Pos      (28UL)                    /*!< PAD59_SR (Bit 28)                                     */
13879 #define GPIO_ALTPADCFGO_PAD59_SR_Msk      (0x10000000UL)            /*!< PAD59_SR (Bitfield-Mask: 0x01)                        */
13880 #define GPIO_ALTPADCFGO_PAD59_DS1_Pos     (24UL)                    /*!< PAD59_DS1 (Bit 24)                                    */
13881 #define GPIO_ALTPADCFGO_PAD59_DS1_Msk     (0x1000000UL)             /*!< PAD59_DS1 (Bitfield-Mask: 0x01)                       */
13882 #define GPIO_ALTPADCFGO_PAD58_SR_Pos      (20UL)                    /*!< PAD58_SR (Bit 20)                                     */
13883 #define GPIO_ALTPADCFGO_PAD58_SR_Msk      (0x100000UL)              /*!< PAD58_SR (Bitfield-Mask: 0x01)                        */
13884 #define GPIO_ALTPADCFGO_PAD58_DS1_Pos     (16UL)                    /*!< PAD58_DS1 (Bit 16)                                    */
13885 #define GPIO_ALTPADCFGO_PAD58_DS1_Msk     (0x10000UL)               /*!< PAD58_DS1 (Bitfield-Mask: 0x01)                       */
13886 #define GPIO_ALTPADCFGO_PAD57_SR_Pos      (12UL)                    /*!< PAD57_SR (Bit 12)                                     */
13887 #define GPIO_ALTPADCFGO_PAD57_SR_Msk      (0x1000UL)                /*!< PAD57_SR (Bitfield-Mask: 0x01)                        */
13888 #define GPIO_ALTPADCFGO_PAD57_DS1_Pos     (8UL)                     /*!< PAD57_DS1 (Bit 8)                                     */
13889 #define GPIO_ALTPADCFGO_PAD57_DS1_Msk     (0x100UL)                 /*!< PAD57_DS1 (Bitfield-Mask: 0x01)                       */
13890 #define GPIO_ALTPADCFGO_PAD56_SR_Pos      (4UL)                     /*!< PAD56_SR (Bit 4)                                      */
13891 #define GPIO_ALTPADCFGO_PAD56_SR_Msk      (0x10UL)                  /*!< PAD56_SR (Bitfield-Mask: 0x01)                        */
13892 #define GPIO_ALTPADCFGO_PAD56_DS1_Pos     (0UL)                     /*!< PAD56_DS1 (Bit 0)                                     */
13893 #define GPIO_ALTPADCFGO_PAD56_DS1_Msk     (0x1UL)                   /*!< PAD56_DS1 (Bitfield-Mask: 0x01)                       */
13894 /* ======================================================  ALTPADCFGP  ======================================================= */
13895 #define GPIO_ALTPADCFGP_PAD63_SR_Pos      (28UL)                    /*!< PAD63_SR (Bit 28)                                     */
13896 #define GPIO_ALTPADCFGP_PAD63_SR_Msk      (0x10000000UL)            /*!< PAD63_SR (Bitfield-Mask: 0x01)                        */
13897 #define GPIO_ALTPADCFGP_PAD63_DS1_Pos     (24UL)                    /*!< PAD63_DS1 (Bit 24)                                    */
13898 #define GPIO_ALTPADCFGP_PAD63_DS1_Msk     (0x1000000UL)             /*!< PAD63_DS1 (Bitfield-Mask: 0x01)                       */
13899 #define GPIO_ALTPADCFGP_PAD62_SR_Pos      (20UL)                    /*!< PAD62_SR (Bit 20)                                     */
13900 #define GPIO_ALTPADCFGP_PAD62_SR_Msk      (0x100000UL)              /*!< PAD62_SR (Bitfield-Mask: 0x01)                        */
13901 #define GPIO_ALTPADCFGP_PAD62_DS1_Pos     (16UL)                    /*!< PAD62_DS1 (Bit 16)                                    */
13902 #define GPIO_ALTPADCFGP_PAD62_DS1_Msk     (0x10000UL)               /*!< PAD62_DS1 (Bitfield-Mask: 0x01)                       */
13903 #define GPIO_ALTPADCFGP_PAD61_SR_Pos      (12UL)                    /*!< PAD61_SR (Bit 12)                                     */
13904 #define GPIO_ALTPADCFGP_PAD61_SR_Msk      (0x1000UL)                /*!< PAD61_SR (Bitfield-Mask: 0x01)                        */
13905 #define GPIO_ALTPADCFGP_PAD61_DS1_Pos     (8UL)                     /*!< PAD61_DS1 (Bit 8)                                     */
13906 #define GPIO_ALTPADCFGP_PAD61_DS1_Msk     (0x100UL)                 /*!< PAD61_DS1 (Bitfield-Mask: 0x01)                       */
13907 #define GPIO_ALTPADCFGP_PAD60_SR_Pos      (4UL)                     /*!< PAD60_SR (Bit 4)                                      */
13908 #define GPIO_ALTPADCFGP_PAD60_SR_Msk      (0x10UL)                  /*!< PAD60_SR (Bitfield-Mask: 0x01)                        */
13909 #define GPIO_ALTPADCFGP_PAD60_DS1_Pos     (0UL)                     /*!< PAD60_DS1 (Bit 0)                                     */
13910 #define GPIO_ALTPADCFGP_PAD60_DS1_Msk     (0x1UL)                   /*!< PAD60_DS1 (Bitfield-Mask: 0x01)                       */
13911 /* ======================================================  ALTPADCFGQ  ======================================================= */
13912 #define GPIO_ALTPADCFGQ_PAD67_SR_Pos      (28UL)                    /*!< PAD67_SR (Bit 28)                                     */
13913 #define GPIO_ALTPADCFGQ_PAD67_SR_Msk      (0x10000000UL)            /*!< PAD67_SR (Bitfield-Mask: 0x01)                        */
13914 #define GPIO_ALTPADCFGQ_PAD67_DS1_Pos     (24UL)                    /*!< PAD67_DS1 (Bit 24)                                    */
13915 #define GPIO_ALTPADCFGQ_PAD67_DS1_Msk     (0x1000000UL)             /*!< PAD67_DS1 (Bitfield-Mask: 0x01)                       */
13916 #define GPIO_ALTPADCFGQ_PAD66_SR_Pos      (20UL)                    /*!< PAD66_SR (Bit 20)                                     */
13917 #define GPIO_ALTPADCFGQ_PAD66_SR_Msk      (0x100000UL)              /*!< PAD66_SR (Bitfield-Mask: 0x01)                        */
13918 #define GPIO_ALTPADCFGQ_PAD66_DS1_Pos     (16UL)                    /*!< PAD66_DS1 (Bit 16)                                    */
13919 #define GPIO_ALTPADCFGQ_PAD66_DS1_Msk     (0x10000UL)               /*!< PAD66_DS1 (Bitfield-Mask: 0x01)                       */
13920 #define GPIO_ALTPADCFGQ_PAD65_SR_Pos      (12UL)                    /*!< PAD65_SR (Bit 12)                                     */
13921 #define GPIO_ALTPADCFGQ_PAD65_SR_Msk      (0x1000UL)                /*!< PAD65_SR (Bitfield-Mask: 0x01)                        */
13922 #define GPIO_ALTPADCFGQ_PAD65_DS1_Pos     (8UL)                     /*!< PAD65_DS1 (Bit 8)                                     */
13923 #define GPIO_ALTPADCFGQ_PAD65_DS1_Msk     (0x100UL)                 /*!< PAD65_DS1 (Bitfield-Mask: 0x01)                       */
13924 #define GPIO_ALTPADCFGQ_PAD64_SR_Pos      (4UL)                     /*!< PAD64_SR (Bit 4)                                      */
13925 #define GPIO_ALTPADCFGQ_PAD64_SR_Msk      (0x10UL)                  /*!< PAD64_SR (Bitfield-Mask: 0x01)                        */
13926 #define GPIO_ALTPADCFGQ_PAD64_DS1_Pos     (0UL)                     /*!< PAD64_DS1 (Bit 0)                                     */
13927 #define GPIO_ALTPADCFGQ_PAD64_DS1_Msk     (0x1UL)                   /*!< PAD64_DS1 (Bitfield-Mask: 0x01)                       */
13928 /* ======================================================  ALTPADCFGR  ======================================================= */
13929 #define GPIO_ALTPADCFGR_PAD71_SR_Pos      (28UL)                    /*!< PAD71_SR (Bit 28)                                     */
13930 #define GPIO_ALTPADCFGR_PAD71_SR_Msk      (0x10000000UL)            /*!< PAD71_SR (Bitfield-Mask: 0x01)                        */
13931 #define GPIO_ALTPADCFGR_PAD71_DS1_Pos     (24UL)                    /*!< PAD71_DS1 (Bit 24)                                    */
13932 #define GPIO_ALTPADCFGR_PAD71_DS1_Msk     (0x1000000UL)             /*!< PAD71_DS1 (Bitfield-Mask: 0x01)                       */
13933 #define GPIO_ALTPADCFGR_PAD70_SR_Pos      (20UL)                    /*!< PAD70_SR (Bit 20)                                     */
13934 #define GPIO_ALTPADCFGR_PAD70_SR_Msk      (0x100000UL)              /*!< PAD70_SR (Bitfield-Mask: 0x01)                        */
13935 #define GPIO_ALTPADCFGR_PAD70_DS1_Pos     (16UL)                    /*!< PAD70_DS1 (Bit 16)                                    */
13936 #define GPIO_ALTPADCFGR_PAD70_DS1_Msk     (0x10000UL)               /*!< PAD70_DS1 (Bitfield-Mask: 0x01)                       */
13937 #define GPIO_ALTPADCFGR_PAD69_SR_Pos      (12UL)                    /*!< PAD69_SR (Bit 12)                                     */
13938 #define GPIO_ALTPADCFGR_PAD69_SR_Msk      (0x1000UL)                /*!< PAD69_SR (Bitfield-Mask: 0x01)                        */
13939 #define GPIO_ALTPADCFGR_PAD69_DS1_Pos     (8UL)                     /*!< PAD69_DS1 (Bit 8)                                     */
13940 #define GPIO_ALTPADCFGR_PAD69_DS1_Msk     (0x100UL)                 /*!< PAD69_DS1 (Bitfield-Mask: 0x01)                       */
13941 #define GPIO_ALTPADCFGR_PAD68_SR_Pos      (4UL)                     /*!< PAD68_SR (Bit 4)                                      */
13942 #define GPIO_ALTPADCFGR_PAD68_SR_Msk      (0x10UL)                  /*!< PAD68_SR (Bitfield-Mask: 0x01)                        */
13943 #define GPIO_ALTPADCFGR_PAD68_DS1_Pos     (0UL)                     /*!< PAD68_DS1 (Bit 0)                                     */
13944 #define GPIO_ALTPADCFGR_PAD68_DS1_Msk     (0x1UL)                   /*!< PAD68_DS1 (Bitfield-Mask: 0x01)                       */
13945 /* ======================================================  ALTPADCFGS  ======================================================= */
13946 #define GPIO_ALTPADCFGS_PAD73_SR_Pos      (12UL)                    /*!< PAD73_SR (Bit 12)                                     */
13947 #define GPIO_ALTPADCFGS_PAD73_SR_Msk      (0x1000UL)                /*!< PAD73_SR (Bitfield-Mask: 0x01)                        */
13948 #define GPIO_ALTPADCFGS_PAD73_DS1_Pos     (8UL)                     /*!< PAD73_DS1 (Bit 8)                                     */
13949 #define GPIO_ALTPADCFGS_PAD73_DS1_Msk     (0x100UL)                 /*!< PAD73_DS1 (Bitfield-Mask: 0x01)                       */
13950 #define GPIO_ALTPADCFGS_PAD72_SR_Pos      (4UL)                     /*!< PAD72_SR (Bit 4)                                      */
13951 #define GPIO_ALTPADCFGS_PAD72_SR_Msk      (0x10UL)                  /*!< PAD72_SR (Bitfield-Mask: 0x01)                        */
13952 #define GPIO_ALTPADCFGS_PAD72_DS1_Pos     (0UL)                     /*!< PAD72_DS1 (Bit 0)                                     */
13953 #define GPIO_ALTPADCFGS_PAD72_DS1_Msk     (0x1UL)                   /*!< PAD72_DS1 (Bitfield-Mask: 0x01)                       */
13954 /* =========================================================  SCDET  ========================================================= */
13955 #define GPIO_SCDET_SCDET_Pos              (0UL)                     /*!< SCDET (Bit 0)                                         */
13956 #define GPIO_SCDET_SCDET_Msk              (0x7fUL)                  /*!< SCDET (Bitfield-Mask: 0x7f)                           */
13957 /* ========================================================  CTENCFG  ======================================================== */
13958 #define GPIO_CTENCFG_EN31_Pos             (31UL)                    /*!< EN31 (Bit 31)                                         */
13959 #define GPIO_CTENCFG_EN31_Msk             (0x80000000UL)            /*!< EN31 (Bitfield-Mask: 0x01)                            */
13960 #define GPIO_CTENCFG_EN30_Pos             (30UL)                    /*!< EN30 (Bit 30)                                         */
13961 #define GPIO_CTENCFG_EN30_Msk             (0x40000000UL)            /*!< EN30 (Bitfield-Mask: 0x01)                            */
13962 #define GPIO_CTENCFG_EN29_Pos             (29UL)                    /*!< EN29 (Bit 29)                                         */
13963 #define GPIO_CTENCFG_EN29_Msk             (0x20000000UL)            /*!< EN29 (Bitfield-Mask: 0x01)                            */
13964 #define GPIO_CTENCFG_EN28_Pos             (28UL)                    /*!< EN28 (Bit 28)                                         */
13965 #define GPIO_CTENCFG_EN28_Msk             (0x10000000UL)            /*!< EN28 (Bitfield-Mask: 0x01)                            */
13966 #define GPIO_CTENCFG_EN27_Pos             (27UL)                    /*!< EN27 (Bit 27)                                         */
13967 #define GPIO_CTENCFG_EN27_Msk             (0x8000000UL)             /*!< EN27 (Bitfield-Mask: 0x01)                            */
13968 #define GPIO_CTENCFG_EN26_Pos             (26UL)                    /*!< EN26 (Bit 26)                                         */
13969 #define GPIO_CTENCFG_EN26_Msk             (0x4000000UL)             /*!< EN26 (Bitfield-Mask: 0x01)                            */
13970 #define GPIO_CTENCFG_EN25_Pos             (25UL)                    /*!< EN25 (Bit 25)                                         */
13971 #define GPIO_CTENCFG_EN25_Msk             (0x2000000UL)             /*!< EN25 (Bitfield-Mask: 0x01)                            */
13972 #define GPIO_CTENCFG_EN24_Pos             (24UL)                    /*!< EN24 (Bit 24)                                         */
13973 #define GPIO_CTENCFG_EN24_Msk             (0x1000000UL)             /*!< EN24 (Bitfield-Mask: 0x01)                            */
13974 #define GPIO_CTENCFG_EN23_Pos             (23UL)                    /*!< EN23 (Bit 23)                                         */
13975 #define GPIO_CTENCFG_EN23_Msk             (0x800000UL)              /*!< EN23 (Bitfield-Mask: 0x01)                            */
13976 #define GPIO_CTENCFG_EN22_Pos             (22UL)                    /*!< EN22 (Bit 22)                                         */
13977 #define GPIO_CTENCFG_EN22_Msk             (0x400000UL)              /*!< EN22 (Bitfield-Mask: 0x01)                            */
13978 #define GPIO_CTENCFG_EN21_Pos             (21UL)                    /*!< EN21 (Bit 21)                                         */
13979 #define GPIO_CTENCFG_EN21_Msk             (0x200000UL)              /*!< EN21 (Bitfield-Mask: 0x01)                            */
13980 #define GPIO_CTENCFG_EN20_Pos             (20UL)                    /*!< EN20 (Bit 20)                                         */
13981 #define GPIO_CTENCFG_EN20_Msk             (0x100000UL)              /*!< EN20 (Bitfield-Mask: 0x01)                            */
13982 #define GPIO_CTENCFG_EN19_Pos             (19UL)                    /*!< EN19 (Bit 19)                                         */
13983 #define GPIO_CTENCFG_EN19_Msk             (0x80000UL)               /*!< EN19 (Bitfield-Mask: 0x01)                            */
13984 #define GPIO_CTENCFG_EN18_Pos             (18UL)                    /*!< EN18 (Bit 18)                                         */
13985 #define GPIO_CTENCFG_EN18_Msk             (0x40000UL)               /*!< EN18 (Bitfield-Mask: 0x01)                            */
13986 #define GPIO_CTENCFG_EN17_Pos             (17UL)                    /*!< EN17 (Bit 17)                                         */
13987 #define GPIO_CTENCFG_EN17_Msk             (0x20000UL)               /*!< EN17 (Bitfield-Mask: 0x01)                            */
13988 #define GPIO_CTENCFG_EN16_Pos             (16UL)                    /*!< EN16 (Bit 16)                                         */
13989 #define GPIO_CTENCFG_EN16_Msk             (0x10000UL)               /*!< EN16 (Bitfield-Mask: 0x01)                            */
13990 #define GPIO_CTENCFG_EN15_Pos             (15UL)                    /*!< EN15 (Bit 15)                                         */
13991 #define GPIO_CTENCFG_EN15_Msk             (0x8000UL)                /*!< EN15 (Bitfield-Mask: 0x01)                            */
13992 #define GPIO_CTENCFG_EN14_Pos             (14UL)                    /*!< EN14 (Bit 14)                                         */
13993 #define GPIO_CTENCFG_EN14_Msk             (0x4000UL)                /*!< EN14 (Bitfield-Mask: 0x01)                            */
13994 #define GPIO_CTENCFG_EN13_Pos             (13UL)                    /*!< EN13 (Bit 13)                                         */
13995 #define GPIO_CTENCFG_EN13_Msk             (0x2000UL)                /*!< EN13 (Bitfield-Mask: 0x01)                            */
13996 #define GPIO_CTENCFG_EN12_Pos             (12UL)                    /*!< EN12 (Bit 12)                                         */
13997 #define GPIO_CTENCFG_EN12_Msk             (0x1000UL)                /*!< EN12 (Bitfield-Mask: 0x01)                            */
13998 #define GPIO_CTENCFG_EN11_Pos             (11UL)                    /*!< EN11 (Bit 11)                                         */
13999 #define GPIO_CTENCFG_EN11_Msk             (0x800UL)                 /*!< EN11 (Bitfield-Mask: 0x01)                            */
14000 #define GPIO_CTENCFG_EN10_Pos             (10UL)                    /*!< EN10 (Bit 10)                                         */
14001 #define GPIO_CTENCFG_EN10_Msk             (0x400UL)                 /*!< EN10 (Bitfield-Mask: 0x01)                            */
14002 #define GPIO_CTENCFG_EN9_Pos              (9UL)                     /*!< EN9 (Bit 9)                                           */
14003 #define GPIO_CTENCFG_EN9_Msk              (0x200UL)                 /*!< EN9 (Bitfield-Mask: 0x01)                             */
14004 #define GPIO_CTENCFG_EN8_Pos              (8UL)                     /*!< EN8 (Bit 8)                                           */
14005 #define GPIO_CTENCFG_EN8_Msk              (0x100UL)                 /*!< EN8 (Bitfield-Mask: 0x01)                             */
14006 #define GPIO_CTENCFG_EN7_Pos              (7UL)                     /*!< EN7 (Bit 7)                                           */
14007 #define GPIO_CTENCFG_EN7_Msk              (0x80UL)                  /*!< EN7 (Bitfield-Mask: 0x01)                             */
14008 #define GPIO_CTENCFG_EN6_Pos              (6UL)                     /*!< EN6 (Bit 6)                                           */
14009 #define GPIO_CTENCFG_EN6_Msk              (0x40UL)                  /*!< EN6 (Bitfield-Mask: 0x01)                             */
14010 #define GPIO_CTENCFG_EN5_Pos              (5UL)                     /*!< EN5 (Bit 5)                                           */
14011 #define GPIO_CTENCFG_EN5_Msk              (0x20UL)                  /*!< EN5 (Bitfield-Mask: 0x01)                             */
14012 #define GPIO_CTENCFG_EN4_Pos              (4UL)                     /*!< EN4 (Bit 4)                                           */
14013 #define GPIO_CTENCFG_EN4_Msk              (0x10UL)                  /*!< EN4 (Bitfield-Mask: 0x01)                             */
14014 #define GPIO_CTENCFG_EN3_Pos              (3UL)                     /*!< EN3 (Bit 3)                                           */
14015 #define GPIO_CTENCFG_EN3_Msk              (0x8UL)                   /*!< EN3 (Bitfield-Mask: 0x01)                             */
14016 #define GPIO_CTENCFG_EN2_Pos              (2UL)                     /*!< EN2 (Bit 2)                                           */
14017 #define GPIO_CTENCFG_EN2_Msk              (0x4UL)                   /*!< EN2 (Bitfield-Mask: 0x01)                             */
14018 #define GPIO_CTENCFG_EN1_Pos              (1UL)                     /*!< EN1 (Bit 1)                                           */
14019 #define GPIO_CTENCFG_EN1_Msk              (0x2UL)                   /*!< EN1 (Bitfield-Mask: 0x01)                             */
14020 #define GPIO_CTENCFG_EN0_Pos              (0UL)                     /*!< EN0 (Bit 0)                                           */
14021 #define GPIO_CTENCFG_EN0_Msk              (0x1UL)                   /*!< EN0 (Bitfield-Mask: 0x01)                             */
14022 /* ========================================================  INT0EN  ========================================================= */
14023 #define GPIO_INT0EN_GPIO31_Pos            (31UL)                    /*!< GPIO31 (Bit 31)                                       */
14024 #define GPIO_INT0EN_GPIO31_Msk            (0x80000000UL)            /*!< GPIO31 (Bitfield-Mask: 0x01)                          */
14025 #define GPIO_INT0EN_GPIO30_Pos            (30UL)                    /*!< GPIO30 (Bit 30)                                       */
14026 #define GPIO_INT0EN_GPIO30_Msk            (0x40000000UL)            /*!< GPIO30 (Bitfield-Mask: 0x01)                          */
14027 #define GPIO_INT0EN_GPIO29_Pos            (29UL)                    /*!< GPIO29 (Bit 29)                                       */
14028 #define GPIO_INT0EN_GPIO29_Msk            (0x20000000UL)            /*!< GPIO29 (Bitfield-Mask: 0x01)                          */
14029 #define GPIO_INT0EN_GPIO28_Pos            (28UL)                    /*!< GPIO28 (Bit 28)                                       */
14030 #define GPIO_INT0EN_GPIO28_Msk            (0x10000000UL)            /*!< GPIO28 (Bitfield-Mask: 0x01)                          */
14031 #define GPIO_INT0EN_GPIO27_Pos            (27UL)                    /*!< GPIO27 (Bit 27)                                       */
14032 #define GPIO_INT0EN_GPIO27_Msk            (0x8000000UL)             /*!< GPIO27 (Bitfield-Mask: 0x01)                          */
14033 #define GPIO_INT0EN_GPIO26_Pos            (26UL)                    /*!< GPIO26 (Bit 26)                                       */
14034 #define GPIO_INT0EN_GPIO26_Msk            (0x4000000UL)             /*!< GPIO26 (Bitfield-Mask: 0x01)                          */
14035 #define GPIO_INT0EN_GPIO25_Pos            (25UL)                    /*!< GPIO25 (Bit 25)                                       */
14036 #define GPIO_INT0EN_GPIO25_Msk            (0x2000000UL)             /*!< GPIO25 (Bitfield-Mask: 0x01)                          */
14037 #define GPIO_INT0EN_GPIO24_Pos            (24UL)                    /*!< GPIO24 (Bit 24)                                       */
14038 #define GPIO_INT0EN_GPIO24_Msk            (0x1000000UL)             /*!< GPIO24 (Bitfield-Mask: 0x01)                          */
14039 #define GPIO_INT0EN_GPIO23_Pos            (23UL)                    /*!< GPIO23 (Bit 23)                                       */
14040 #define GPIO_INT0EN_GPIO23_Msk            (0x800000UL)              /*!< GPIO23 (Bitfield-Mask: 0x01)                          */
14041 #define GPIO_INT0EN_GPIO22_Pos            (22UL)                    /*!< GPIO22 (Bit 22)                                       */
14042 #define GPIO_INT0EN_GPIO22_Msk            (0x400000UL)              /*!< GPIO22 (Bitfield-Mask: 0x01)                          */
14043 #define GPIO_INT0EN_GPIO21_Pos            (21UL)                    /*!< GPIO21 (Bit 21)                                       */
14044 #define GPIO_INT0EN_GPIO21_Msk            (0x200000UL)              /*!< GPIO21 (Bitfield-Mask: 0x01)                          */
14045 #define GPIO_INT0EN_GPIO20_Pos            (20UL)                    /*!< GPIO20 (Bit 20)                                       */
14046 #define GPIO_INT0EN_GPIO20_Msk            (0x100000UL)              /*!< GPIO20 (Bitfield-Mask: 0x01)                          */
14047 #define GPIO_INT0EN_GPIO19_Pos            (19UL)                    /*!< GPIO19 (Bit 19)                                       */
14048 #define GPIO_INT0EN_GPIO19_Msk            (0x80000UL)               /*!< GPIO19 (Bitfield-Mask: 0x01)                          */
14049 #define GPIO_INT0EN_GPIO18_Pos            (18UL)                    /*!< GPIO18 (Bit 18)                                       */
14050 #define GPIO_INT0EN_GPIO18_Msk            (0x40000UL)               /*!< GPIO18 (Bitfield-Mask: 0x01)                          */
14051 #define GPIO_INT0EN_GPIO17_Pos            (17UL)                    /*!< GPIO17 (Bit 17)                                       */
14052 #define GPIO_INT0EN_GPIO17_Msk            (0x20000UL)               /*!< GPIO17 (Bitfield-Mask: 0x01)                          */
14053 #define GPIO_INT0EN_GPIO16_Pos            (16UL)                    /*!< GPIO16 (Bit 16)                                       */
14054 #define GPIO_INT0EN_GPIO16_Msk            (0x10000UL)               /*!< GPIO16 (Bitfield-Mask: 0x01)                          */
14055 #define GPIO_INT0EN_GPIO15_Pos            (15UL)                    /*!< GPIO15 (Bit 15)                                       */
14056 #define GPIO_INT0EN_GPIO15_Msk            (0x8000UL)                /*!< GPIO15 (Bitfield-Mask: 0x01)                          */
14057 #define GPIO_INT0EN_GPIO14_Pos            (14UL)                    /*!< GPIO14 (Bit 14)                                       */
14058 #define GPIO_INT0EN_GPIO14_Msk            (0x4000UL)                /*!< GPIO14 (Bitfield-Mask: 0x01)                          */
14059 #define GPIO_INT0EN_GPIO13_Pos            (13UL)                    /*!< GPIO13 (Bit 13)                                       */
14060 #define GPIO_INT0EN_GPIO13_Msk            (0x2000UL)                /*!< GPIO13 (Bitfield-Mask: 0x01)                          */
14061 #define GPIO_INT0EN_GPIO12_Pos            (12UL)                    /*!< GPIO12 (Bit 12)                                       */
14062 #define GPIO_INT0EN_GPIO12_Msk            (0x1000UL)                /*!< GPIO12 (Bitfield-Mask: 0x01)                          */
14063 #define GPIO_INT0EN_GPIO11_Pos            (11UL)                    /*!< GPIO11 (Bit 11)                                       */
14064 #define GPIO_INT0EN_GPIO11_Msk            (0x800UL)                 /*!< GPIO11 (Bitfield-Mask: 0x01)                          */
14065 #define GPIO_INT0EN_GPIO10_Pos            (10UL)                    /*!< GPIO10 (Bit 10)                                       */
14066 #define GPIO_INT0EN_GPIO10_Msk            (0x400UL)                 /*!< GPIO10 (Bitfield-Mask: 0x01)                          */
14067 #define GPIO_INT0EN_GPIO9_Pos             (9UL)                     /*!< GPIO9 (Bit 9)                                         */
14068 #define GPIO_INT0EN_GPIO9_Msk             (0x200UL)                 /*!< GPIO9 (Bitfield-Mask: 0x01)                           */
14069 #define GPIO_INT0EN_GPIO8_Pos             (8UL)                     /*!< GPIO8 (Bit 8)                                         */
14070 #define GPIO_INT0EN_GPIO8_Msk             (0x100UL)                 /*!< GPIO8 (Bitfield-Mask: 0x01)                           */
14071 #define GPIO_INT0EN_GPIO7_Pos             (7UL)                     /*!< GPIO7 (Bit 7)                                         */
14072 #define GPIO_INT0EN_GPIO7_Msk             (0x80UL)                  /*!< GPIO7 (Bitfield-Mask: 0x01)                           */
14073 #define GPIO_INT0EN_GPIO6_Pos             (6UL)                     /*!< GPIO6 (Bit 6)                                         */
14074 #define GPIO_INT0EN_GPIO6_Msk             (0x40UL)                  /*!< GPIO6 (Bitfield-Mask: 0x01)                           */
14075 #define GPIO_INT0EN_GPIO5_Pos             (5UL)                     /*!< GPIO5 (Bit 5)                                         */
14076 #define GPIO_INT0EN_GPIO5_Msk             (0x20UL)                  /*!< GPIO5 (Bitfield-Mask: 0x01)                           */
14077 #define GPIO_INT0EN_GPIO4_Pos             (4UL)                     /*!< GPIO4 (Bit 4)                                         */
14078 #define GPIO_INT0EN_GPIO4_Msk             (0x10UL)                  /*!< GPIO4 (Bitfield-Mask: 0x01)                           */
14079 #define GPIO_INT0EN_GPIO3_Pos             (3UL)                     /*!< GPIO3 (Bit 3)                                         */
14080 #define GPIO_INT0EN_GPIO3_Msk             (0x8UL)                   /*!< GPIO3 (Bitfield-Mask: 0x01)                           */
14081 #define GPIO_INT0EN_GPIO2_Pos             (2UL)                     /*!< GPIO2 (Bit 2)                                         */
14082 #define GPIO_INT0EN_GPIO2_Msk             (0x4UL)                   /*!< GPIO2 (Bitfield-Mask: 0x01)                           */
14083 #define GPIO_INT0EN_GPIO1_Pos             (1UL)                     /*!< GPIO1 (Bit 1)                                         */
14084 #define GPIO_INT0EN_GPIO1_Msk             (0x2UL)                   /*!< GPIO1 (Bitfield-Mask: 0x01)                           */
14085 #define GPIO_INT0EN_GPIO0_Pos             (0UL)                     /*!< GPIO0 (Bit 0)                                         */
14086 #define GPIO_INT0EN_GPIO0_Msk             (0x1UL)                   /*!< GPIO0 (Bitfield-Mask: 0x01)                           */
14087 /* =======================================================  INT0STAT  ======================================================== */
14088 #define GPIO_INT0STAT_GPIO31_Pos          (31UL)                    /*!< GPIO31 (Bit 31)                                       */
14089 #define GPIO_INT0STAT_GPIO31_Msk          (0x80000000UL)            /*!< GPIO31 (Bitfield-Mask: 0x01)                          */
14090 #define GPIO_INT0STAT_GPIO30_Pos          (30UL)                    /*!< GPIO30 (Bit 30)                                       */
14091 #define GPIO_INT0STAT_GPIO30_Msk          (0x40000000UL)            /*!< GPIO30 (Bitfield-Mask: 0x01)                          */
14092 #define GPIO_INT0STAT_GPIO29_Pos          (29UL)                    /*!< GPIO29 (Bit 29)                                       */
14093 #define GPIO_INT0STAT_GPIO29_Msk          (0x20000000UL)            /*!< GPIO29 (Bitfield-Mask: 0x01)                          */
14094 #define GPIO_INT0STAT_GPIO28_Pos          (28UL)                    /*!< GPIO28 (Bit 28)                                       */
14095 #define GPIO_INT0STAT_GPIO28_Msk          (0x10000000UL)            /*!< GPIO28 (Bitfield-Mask: 0x01)                          */
14096 #define GPIO_INT0STAT_GPIO27_Pos          (27UL)                    /*!< GPIO27 (Bit 27)                                       */
14097 #define GPIO_INT0STAT_GPIO27_Msk          (0x8000000UL)             /*!< GPIO27 (Bitfield-Mask: 0x01)                          */
14098 #define GPIO_INT0STAT_GPIO26_Pos          (26UL)                    /*!< GPIO26 (Bit 26)                                       */
14099 #define GPIO_INT0STAT_GPIO26_Msk          (0x4000000UL)             /*!< GPIO26 (Bitfield-Mask: 0x01)                          */
14100 #define GPIO_INT0STAT_GPIO25_Pos          (25UL)                    /*!< GPIO25 (Bit 25)                                       */
14101 #define GPIO_INT0STAT_GPIO25_Msk          (0x2000000UL)             /*!< GPIO25 (Bitfield-Mask: 0x01)                          */
14102 #define GPIO_INT0STAT_GPIO24_Pos          (24UL)                    /*!< GPIO24 (Bit 24)                                       */
14103 #define GPIO_INT0STAT_GPIO24_Msk          (0x1000000UL)             /*!< GPIO24 (Bitfield-Mask: 0x01)                          */
14104 #define GPIO_INT0STAT_GPIO23_Pos          (23UL)                    /*!< GPIO23 (Bit 23)                                       */
14105 #define GPIO_INT0STAT_GPIO23_Msk          (0x800000UL)              /*!< GPIO23 (Bitfield-Mask: 0x01)                          */
14106 #define GPIO_INT0STAT_GPIO22_Pos          (22UL)                    /*!< GPIO22 (Bit 22)                                       */
14107 #define GPIO_INT0STAT_GPIO22_Msk          (0x400000UL)              /*!< GPIO22 (Bitfield-Mask: 0x01)                          */
14108 #define GPIO_INT0STAT_GPIO21_Pos          (21UL)                    /*!< GPIO21 (Bit 21)                                       */
14109 #define GPIO_INT0STAT_GPIO21_Msk          (0x200000UL)              /*!< GPIO21 (Bitfield-Mask: 0x01)                          */
14110 #define GPIO_INT0STAT_GPIO20_Pos          (20UL)                    /*!< GPIO20 (Bit 20)                                       */
14111 #define GPIO_INT0STAT_GPIO20_Msk          (0x100000UL)              /*!< GPIO20 (Bitfield-Mask: 0x01)                          */
14112 #define GPIO_INT0STAT_GPIO19_Pos          (19UL)                    /*!< GPIO19 (Bit 19)                                       */
14113 #define GPIO_INT0STAT_GPIO19_Msk          (0x80000UL)               /*!< GPIO19 (Bitfield-Mask: 0x01)                          */
14114 #define GPIO_INT0STAT_GPIO18_Pos          (18UL)                    /*!< GPIO18 (Bit 18)                                       */
14115 #define GPIO_INT0STAT_GPIO18_Msk          (0x40000UL)               /*!< GPIO18 (Bitfield-Mask: 0x01)                          */
14116 #define GPIO_INT0STAT_GPIO17_Pos          (17UL)                    /*!< GPIO17 (Bit 17)                                       */
14117 #define GPIO_INT0STAT_GPIO17_Msk          (0x20000UL)               /*!< GPIO17 (Bitfield-Mask: 0x01)                          */
14118 #define GPIO_INT0STAT_GPIO16_Pos          (16UL)                    /*!< GPIO16 (Bit 16)                                       */
14119 #define GPIO_INT0STAT_GPIO16_Msk          (0x10000UL)               /*!< GPIO16 (Bitfield-Mask: 0x01)                          */
14120 #define GPIO_INT0STAT_GPIO15_Pos          (15UL)                    /*!< GPIO15 (Bit 15)                                       */
14121 #define GPIO_INT0STAT_GPIO15_Msk          (0x8000UL)                /*!< GPIO15 (Bitfield-Mask: 0x01)                          */
14122 #define GPIO_INT0STAT_GPIO14_Pos          (14UL)                    /*!< GPIO14 (Bit 14)                                       */
14123 #define GPIO_INT0STAT_GPIO14_Msk          (0x4000UL)                /*!< GPIO14 (Bitfield-Mask: 0x01)                          */
14124 #define GPIO_INT0STAT_GPIO13_Pos          (13UL)                    /*!< GPIO13 (Bit 13)                                       */
14125 #define GPIO_INT0STAT_GPIO13_Msk          (0x2000UL)                /*!< GPIO13 (Bitfield-Mask: 0x01)                          */
14126 #define GPIO_INT0STAT_GPIO12_Pos          (12UL)                    /*!< GPIO12 (Bit 12)                                       */
14127 #define GPIO_INT0STAT_GPIO12_Msk          (0x1000UL)                /*!< GPIO12 (Bitfield-Mask: 0x01)                          */
14128 #define GPIO_INT0STAT_GPIO11_Pos          (11UL)                    /*!< GPIO11 (Bit 11)                                       */
14129 #define GPIO_INT0STAT_GPIO11_Msk          (0x800UL)                 /*!< GPIO11 (Bitfield-Mask: 0x01)                          */
14130 #define GPIO_INT0STAT_GPIO10_Pos          (10UL)                    /*!< GPIO10 (Bit 10)                                       */
14131 #define GPIO_INT0STAT_GPIO10_Msk          (0x400UL)                 /*!< GPIO10 (Bitfield-Mask: 0x01)                          */
14132 #define GPIO_INT0STAT_GPIO9_Pos           (9UL)                     /*!< GPIO9 (Bit 9)                                         */
14133 #define GPIO_INT0STAT_GPIO9_Msk           (0x200UL)                 /*!< GPIO9 (Bitfield-Mask: 0x01)                           */
14134 #define GPIO_INT0STAT_GPIO8_Pos           (8UL)                     /*!< GPIO8 (Bit 8)                                         */
14135 #define GPIO_INT0STAT_GPIO8_Msk           (0x100UL)                 /*!< GPIO8 (Bitfield-Mask: 0x01)                           */
14136 #define GPIO_INT0STAT_GPIO7_Pos           (7UL)                     /*!< GPIO7 (Bit 7)                                         */
14137 #define GPIO_INT0STAT_GPIO7_Msk           (0x80UL)                  /*!< GPIO7 (Bitfield-Mask: 0x01)                           */
14138 #define GPIO_INT0STAT_GPIO6_Pos           (6UL)                     /*!< GPIO6 (Bit 6)                                         */
14139 #define GPIO_INT0STAT_GPIO6_Msk           (0x40UL)                  /*!< GPIO6 (Bitfield-Mask: 0x01)                           */
14140 #define GPIO_INT0STAT_GPIO5_Pos           (5UL)                     /*!< GPIO5 (Bit 5)                                         */
14141 #define GPIO_INT0STAT_GPIO5_Msk           (0x20UL)                  /*!< GPIO5 (Bitfield-Mask: 0x01)                           */
14142 #define GPIO_INT0STAT_GPIO4_Pos           (4UL)                     /*!< GPIO4 (Bit 4)                                         */
14143 #define GPIO_INT0STAT_GPIO4_Msk           (0x10UL)                  /*!< GPIO4 (Bitfield-Mask: 0x01)                           */
14144 #define GPIO_INT0STAT_GPIO3_Pos           (3UL)                     /*!< GPIO3 (Bit 3)                                         */
14145 #define GPIO_INT0STAT_GPIO3_Msk           (0x8UL)                   /*!< GPIO3 (Bitfield-Mask: 0x01)                           */
14146 #define GPIO_INT0STAT_GPIO2_Pos           (2UL)                     /*!< GPIO2 (Bit 2)                                         */
14147 #define GPIO_INT0STAT_GPIO2_Msk           (0x4UL)                   /*!< GPIO2 (Bitfield-Mask: 0x01)                           */
14148 #define GPIO_INT0STAT_GPIO1_Pos           (1UL)                     /*!< GPIO1 (Bit 1)                                         */
14149 #define GPIO_INT0STAT_GPIO1_Msk           (0x2UL)                   /*!< GPIO1 (Bitfield-Mask: 0x01)                           */
14150 #define GPIO_INT0STAT_GPIO0_Pos           (0UL)                     /*!< GPIO0 (Bit 0)                                         */
14151 #define GPIO_INT0STAT_GPIO0_Msk           (0x1UL)                   /*!< GPIO0 (Bitfield-Mask: 0x01)                           */
14152 /* ========================================================  INT0CLR  ======================================================== */
14153 #define GPIO_INT0CLR_GPIO31_Pos           (31UL)                    /*!< GPIO31 (Bit 31)                                       */
14154 #define GPIO_INT0CLR_GPIO31_Msk           (0x80000000UL)            /*!< GPIO31 (Bitfield-Mask: 0x01)                          */
14155 #define GPIO_INT0CLR_GPIO30_Pos           (30UL)                    /*!< GPIO30 (Bit 30)                                       */
14156 #define GPIO_INT0CLR_GPIO30_Msk           (0x40000000UL)            /*!< GPIO30 (Bitfield-Mask: 0x01)                          */
14157 #define GPIO_INT0CLR_GPIO29_Pos           (29UL)                    /*!< GPIO29 (Bit 29)                                       */
14158 #define GPIO_INT0CLR_GPIO29_Msk           (0x20000000UL)            /*!< GPIO29 (Bitfield-Mask: 0x01)                          */
14159 #define GPIO_INT0CLR_GPIO28_Pos           (28UL)                    /*!< GPIO28 (Bit 28)                                       */
14160 #define GPIO_INT0CLR_GPIO28_Msk           (0x10000000UL)            /*!< GPIO28 (Bitfield-Mask: 0x01)                          */
14161 #define GPIO_INT0CLR_GPIO27_Pos           (27UL)                    /*!< GPIO27 (Bit 27)                                       */
14162 #define GPIO_INT0CLR_GPIO27_Msk           (0x8000000UL)             /*!< GPIO27 (Bitfield-Mask: 0x01)                          */
14163 #define GPIO_INT0CLR_GPIO26_Pos           (26UL)                    /*!< GPIO26 (Bit 26)                                       */
14164 #define GPIO_INT0CLR_GPIO26_Msk           (0x4000000UL)             /*!< GPIO26 (Bitfield-Mask: 0x01)                          */
14165 #define GPIO_INT0CLR_GPIO25_Pos           (25UL)                    /*!< GPIO25 (Bit 25)                                       */
14166 #define GPIO_INT0CLR_GPIO25_Msk           (0x2000000UL)             /*!< GPIO25 (Bitfield-Mask: 0x01)                          */
14167 #define GPIO_INT0CLR_GPIO24_Pos           (24UL)                    /*!< GPIO24 (Bit 24)                                       */
14168 #define GPIO_INT0CLR_GPIO24_Msk           (0x1000000UL)             /*!< GPIO24 (Bitfield-Mask: 0x01)                          */
14169 #define GPIO_INT0CLR_GPIO23_Pos           (23UL)                    /*!< GPIO23 (Bit 23)                                       */
14170 #define GPIO_INT0CLR_GPIO23_Msk           (0x800000UL)              /*!< GPIO23 (Bitfield-Mask: 0x01)                          */
14171 #define GPIO_INT0CLR_GPIO22_Pos           (22UL)                    /*!< GPIO22 (Bit 22)                                       */
14172 #define GPIO_INT0CLR_GPIO22_Msk           (0x400000UL)              /*!< GPIO22 (Bitfield-Mask: 0x01)                          */
14173 #define GPIO_INT0CLR_GPIO21_Pos           (21UL)                    /*!< GPIO21 (Bit 21)                                       */
14174 #define GPIO_INT0CLR_GPIO21_Msk           (0x200000UL)              /*!< GPIO21 (Bitfield-Mask: 0x01)                          */
14175 #define GPIO_INT0CLR_GPIO20_Pos           (20UL)                    /*!< GPIO20 (Bit 20)                                       */
14176 #define GPIO_INT0CLR_GPIO20_Msk           (0x100000UL)              /*!< GPIO20 (Bitfield-Mask: 0x01)                          */
14177 #define GPIO_INT0CLR_GPIO19_Pos           (19UL)                    /*!< GPIO19 (Bit 19)                                       */
14178 #define GPIO_INT0CLR_GPIO19_Msk           (0x80000UL)               /*!< GPIO19 (Bitfield-Mask: 0x01)                          */
14179 #define GPIO_INT0CLR_GPIO18_Pos           (18UL)                    /*!< GPIO18 (Bit 18)                                       */
14180 #define GPIO_INT0CLR_GPIO18_Msk           (0x40000UL)               /*!< GPIO18 (Bitfield-Mask: 0x01)                          */
14181 #define GPIO_INT0CLR_GPIO17_Pos           (17UL)                    /*!< GPIO17 (Bit 17)                                       */
14182 #define GPIO_INT0CLR_GPIO17_Msk           (0x20000UL)               /*!< GPIO17 (Bitfield-Mask: 0x01)                          */
14183 #define GPIO_INT0CLR_GPIO16_Pos           (16UL)                    /*!< GPIO16 (Bit 16)                                       */
14184 #define GPIO_INT0CLR_GPIO16_Msk           (0x10000UL)               /*!< GPIO16 (Bitfield-Mask: 0x01)                          */
14185 #define GPIO_INT0CLR_GPIO15_Pos           (15UL)                    /*!< GPIO15 (Bit 15)                                       */
14186 #define GPIO_INT0CLR_GPIO15_Msk           (0x8000UL)                /*!< GPIO15 (Bitfield-Mask: 0x01)                          */
14187 #define GPIO_INT0CLR_GPIO14_Pos           (14UL)                    /*!< GPIO14 (Bit 14)                                       */
14188 #define GPIO_INT0CLR_GPIO14_Msk           (0x4000UL)                /*!< GPIO14 (Bitfield-Mask: 0x01)                          */
14189 #define GPIO_INT0CLR_GPIO13_Pos           (13UL)                    /*!< GPIO13 (Bit 13)                                       */
14190 #define GPIO_INT0CLR_GPIO13_Msk           (0x2000UL)                /*!< GPIO13 (Bitfield-Mask: 0x01)                          */
14191 #define GPIO_INT0CLR_GPIO12_Pos           (12UL)                    /*!< GPIO12 (Bit 12)                                       */
14192 #define GPIO_INT0CLR_GPIO12_Msk           (0x1000UL)                /*!< GPIO12 (Bitfield-Mask: 0x01)                          */
14193 #define GPIO_INT0CLR_GPIO11_Pos           (11UL)                    /*!< GPIO11 (Bit 11)                                       */
14194 #define GPIO_INT0CLR_GPIO11_Msk           (0x800UL)                 /*!< GPIO11 (Bitfield-Mask: 0x01)                          */
14195 #define GPIO_INT0CLR_GPIO10_Pos           (10UL)                    /*!< GPIO10 (Bit 10)                                       */
14196 #define GPIO_INT0CLR_GPIO10_Msk           (0x400UL)                 /*!< GPIO10 (Bitfield-Mask: 0x01)                          */
14197 #define GPIO_INT0CLR_GPIO9_Pos            (9UL)                     /*!< GPIO9 (Bit 9)                                         */
14198 #define GPIO_INT0CLR_GPIO9_Msk            (0x200UL)                 /*!< GPIO9 (Bitfield-Mask: 0x01)                           */
14199 #define GPIO_INT0CLR_GPIO8_Pos            (8UL)                     /*!< GPIO8 (Bit 8)                                         */
14200 #define GPIO_INT0CLR_GPIO8_Msk            (0x100UL)                 /*!< GPIO8 (Bitfield-Mask: 0x01)                           */
14201 #define GPIO_INT0CLR_GPIO7_Pos            (7UL)                     /*!< GPIO7 (Bit 7)                                         */
14202 #define GPIO_INT0CLR_GPIO7_Msk            (0x80UL)                  /*!< GPIO7 (Bitfield-Mask: 0x01)                           */
14203 #define GPIO_INT0CLR_GPIO6_Pos            (6UL)                     /*!< GPIO6 (Bit 6)                                         */
14204 #define GPIO_INT0CLR_GPIO6_Msk            (0x40UL)                  /*!< GPIO6 (Bitfield-Mask: 0x01)                           */
14205 #define GPIO_INT0CLR_GPIO5_Pos            (5UL)                     /*!< GPIO5 (Bit 5)                                         */
14206 #define GPIO_INT0CLR_GPIO5_Msk            (0x20UL)                  /*!< GPIO5 (Bitfield-Mask: 0x01)                           */
14207 #define GPIO_INT0CLR_GPIO4_Pos            (4UL)                     /*!< GPIO4 (Bit 4)                                         */
14208 #define GPIO_INT0CLR_GPIO4_Msk            (0x10UL)                  /*!< GPIO4 (Bitfield-Mask: 0x01)                           */
14209 #define GPIO_INT0CLR_GPIO3_Pos            (3UL)                     /*!< GPIO3 (Bit 3)                                         */
14210 #define GPIO_INT0CLR_GPIO3_Msk            (0x8UL)                   /*!< GPIO3 (Bitfield-Mask: 0x01)                           */
14211 #define GPIO_INT0CLR_GPIO2_Pos            (2UL)                     /*!< GPIO2 (Bit 2)                                         */
14212 #define GPIO_INT0CLR_GPIO2_Msk            (0x4UL)                   /*!< GPIO2 (Bitfield-Mask: 0x01)                           */
14213 #define GPIO_INT0CLR_GPIO1_Pos            (1UL)                     /*!< GPIO1 (Bit 1)                                         */
14214 #define GPIO_INT0CLR_GPIO1_Msk            (0x2UL)                   /*!< GPIO1 (Bitfield-Mask: 0x01)                           */
14215 #define GPIO_INT0CLR_GPIO0_Pos            (0UL)                     /*!< GPIO0 (Bit 0)                                         */
14216 #define GPIO_INT0CLR_GPIO0_Msk            (0x1UL)                   /*!< GPIO0 (Bitfield-Mask: 0x01)                           */
14217 /* ========================================================  INT0SET  ======================================================== */
14218 #define GPIO_INT0SET_GPIO31_Pos           (31UL)                    /*!< GPIO31 (Bit 31)                                       */
14219 #define GPIO_INT0SET_GPIO31_Msk           (0x80000000UL)            /*!< GPIO31 (Bitfield-Mask: 0x01)                          */
14220 #define GPIO_INT0SET_GPIO30_Pos           (30UL)                    /*!< GPIO30 (Bit 30)                                       */
14221 #define GPIO_INT0SET_GPIO30_Msk           (0x40000000UL)            /*!< GPIO30 (Bitfield-Mask: 0x01)                          */
14222 #define GPIO_INT0SET_GPIO29_Pos           (29UL)                    /*!< GPIO29 (Bit 29)                                       */
14223 #define GPIO_INT0SET_GPIO29_Msk           (0x20000000UL)            /*!< GPIO29 (Bitfield-Mask: 0x01)                          */
14224 #define GPIO_INT0SET_GPIO28_Pos           (28UL)                    /*!< GPIO28 (Bit 28)                                       */
14225 #define GPIO_INT0SET_GPIO28_Msk           (0x10000000UL)            /*!< GPIO28 (Bitfield-Mask: 0x01)                          */
14226 #define GPIO_INT0SET_GPIO27_Pos           (27UL)                    /*!< GPIO27 (Bit 27)                                       */
14227 #define GPIO_INT0SET_GPIO27_Msk           (0x8000000UL)             /*!< GPIO27 (Bitfield-Mask: 0x01)                          */
14228 #define GPIO_INT0SET_GPIO26_Pos           (26UL)                    /*!< GPIO26 (Bit 26)                                       */
14229 #define GPIO_INT0SET_GPIO26_Msk           (0x4000000UL)             /*!< GPIO26 (Bitfield-Mask: 0x01)                          */
14230 #define GPIO_INT0SET_GPIO25_Pos           (25UL)                    /*!< GPIO25 (Bit 25)                                       */
14231 #define GPIO_INT0SET_GPIO25_Msk           (0x2000000UL)             /*!< GPIO25 (Bitfield-Mask: 0x01)                          */
14232 #define GPIO_INT0SET_GPIO24_Pos           (24UL)                    /*!< GPIO24 (Bit 24)                                       */
14233 #define GPIO_INT0SET_GPIO24_Msk           (0x1000000UL)             /*!< GPIO24 (Bitfield-Mask: 0x01)                          */
14234 #define GPIO_INT0SET_GPIO23_Pos           (23UL)                    /*!< GPIO23 (Bit 23)                                       */
14235 #define GPIO_INT0SET_GPIO23_Msk           (0x800000UL)              /*!< GPIO23 (Bitfield-Mask: 0x01)                          */
14236 #define GPIO_INT0SET_GPIO22_Pos           (22UL)                    /*!< GPIO22 (Bit 22)                                       */
14237 #define GPIO_INT0SET_GPIO22_Msk           (0x400000UL)              /*!< GPIO22 (Bitfield-Mask: 0x01)                          */
14238 #define GPIO_INT0SET_GPIO21_Pos           (21UL)                    /*!< GPIO21 (Bit 21)                                       */
14239 #define GPIO_INT0SET_GPIO21_Msk           (0x200000UL)              /*!< GPIO21 (Bitfield-Mask: 0x01)                          */
14240 #define GPIO_INT0SET_GPIO20_Pos           (20UL)                    /*!< GPIO20 (Bit 20)                                       */
14241 #define GPIO_INT0SET_GPIO20_Msk           (0x100000UL)              /*!< GPIO20 (Bitfield-Mask: 0x01)                          */
14242 #define GPIO_INT0SET_GPIO19_Pos           (19UL)                    /*!< GPIO19 (Bit 19)                                       */
14243 #define GPIO_INT0SET_GPIO19_Msk           (0x80000UL)               /*!< GPIO19 (Bitfield-Mask: 0x01)                          */
14244 #define GPIO_INT0SET_GPIO18_Pos           (18UL)                    /*!< GPIO18 (Bit 18)                                       */
14245 #define GPIO_INT0SET_GPIO18_Msk           (0x40000UL)               /*!< GPIO18 (Bitfield-Mask: 0x01)                          */
14246 #define GPIO_INT0SET_GPIO17_Pos           (17UL)                    /*!< GPIO17 (Bit 17)                                       */
14247 #define GPIO_INT0SET_GPIO17_Msk           (0x20000UL)               /*!< GPIO17 (Bitfield-Mask: 0x01)                          */
14248 #define GPIO_INT0SET_GPIO16_Pos           (16UL)                    /*!< GPIO16 (Bit 16)                                       */
14249 #define GPIO_INT0SET_GPIO16_Msk           (0x10000UL)               /*!< GPIO16 (Bitfield-Mask: 0x01)                          */
14250 #define GPIO_INT0SET_GPIO15_Pos           (15UL)                    /*!< GPIO15 (Bit 15)                                       */
14251 #define GPIO_INT0SET_GPIO15_Msk           (0x8000UL)                /*!< GPIO15 (Bitfield-Mask: 0x01)                          */
14252 #define GPIO_INT0SET_GPIO14_Pos           (14UL)                    /*!< GPIO14 (Bit 14)                                       */
14253 #define GPIO_INT0SET_GPIO14_Msk           (0x4000UL)                /*!< GPIO14 (Bitfield-Mask: 0x01)                          */
14254 #define GPIO_INT0SET_GPIO13_Pos           (13UL)                    /*!< GPIO13 (Bit 13)                                       */
14255 #define GPIO_INT0SET_GPIO13_Msk           (0x2000UL)                /*!< GPIO13 (Bitfield-Mask: 0x01)                          */
14256 #define GPIO_INT0SET_GPIO12_Pos           (12UL)                    /*!< GPIO12 (Bit 12)                                       */
14257 #define GPIO_INT0SET_GPIO12_Msk           (0x1000UL)                /*!< GPIO12 (Bitfield-Mask: 0x01)                          */
14258 #define GPIO_INT0SET_GPIO11_Pos           (11UL)                    /*!< GPIO11 (Bit 11)                                       */
14259 #define GPIO_INT0SET_GPIO11_Msk           (0x800UL)                 /*!< GPIO11 (Bitfield-Mask: 0x01)                          */
14260 #define GPIO_INT0SET_GPIO10_Pos           (10UL)                    /*!< GPIO10 (Bit 10)                                       */
14261 #define GPIO_INT0SET_GPIO10_Msk           (0x400UL)                 /*!< GPIO10 (Bitfield-Mask: 0x01)                          */
14262 #define GPIO_INT0SET_GPIO9_Pos            (9UL)                     /*!< GPIO9 (Bit 9)                                         */
14263 #define GPIO_INT0SET_GPIO9_Msk            (0x200UL)                 /*!< GPIO9 (Bitfield-Mask: 0x01)                           */
14264 #define GPIO_INT0SET_GPIO8_Pos            (8UL)                     /*!< GPIO8 (Bit 8)                                         */
14265 #define GPIO_INT0SET_GPIO8_Msk            (0x100UL)                 /*!< GPIO8 (Bitfield-Mask: 0x01)                           */
14266 #define GPIO_INT0SET_GPIO7_Pos            (7UL)                     /*!< GPIO7 (Bit 7)                                         */
14267 #define GPIO_INT0SET_GPIO7_Msk            (0x80UL)                  /*!< GPIO7 (Bitfield-Mask: 0x01)                           */
14268 #define GPIO_INT0SET_GPIO6_Pos            (6UL)                     /*!< GPIO6 (Bit 6)                                         */
14269 #define GPIO_INT0SET_GPIO6_Msk            (0x40UL)                  /*!< GPIO6 (Bitfield-Mask: 0x01)                           */
14270 #define GPIO_INT0SET_GPIO5_Pos            (5UL)                     /*!< GPIO5 (Bit 5)                                         */
14271 #define GPIO_INT0SET_GPIO5_Msk            (0x20UL)                  /*!< GPIO5 (Bitfield-Mask: 0x01)                           */
14272 #define GPIO_INT0SET_GPIO4_Pos            (4UL)                     /*!< GPIO4 (Bit 4)                                         */
14273 #define GPIO_INT0SET_GPIO4_Msk            (0x10UL)                  /*!< GPIO4 (Bitfield-Mask: 0x01)                           */
14274 #define GPIO_INT0SET_GPIO3_Pos            (3UL)                     /*!< GPIO3 (Bit 3)                                         */
14275 #define GPIO_INT0SET_GPIO3_Msk            (0x8UL)                   /*!< GPIO3 (Bitfield-Mask: 0x01)                           */
14276 #define GPIO_INT0SET_GPIO2_Pos            (2UL)                     /*!< GPIO2 (Bit 2)                                         */
14277 #define GPIO_INT0SET_GPIO2_Msk            (0x4UL)                   /*!< GPIO2 (Bitfield-Mask: 0x01)                           */
14278 #define GPIO_INT0SET_GPIO1_Pos            (1UL)                     /*!< GPIO1 (Bit 1)                                         */
14279 #define GPIO_INT0SET_GPIO1_Msk            (0x2UL)                   /*!< GPIO1 (Bitfield-Mask: 0x01)                           */
14280 #define GPIO_INT0SET_GPIO0_Pos            (0UL)                     /*!< GPIO0 (Bit 0)                                         */
14281 #define GPIO_INT0SET_GPIO0_Msk            (0x1UL)                   /*!< GPIO0 (Bitfield-Mask: 0x01)                           */
14282 /* ========================================================  INT1EN  ========================================================= */
14283 #define GPIO_INT1EN_GPIO63_Pos            (31UL)                    /*!< GPIO63 (Bit 31)                                       */
14284 #define GPIO_INT1EN_GPIO63_Msk            (0x80000000UL)            /*!< GPIO63 (Bitfield-Mask: 0x01)                          */
14285 #define GPIO_INT1EN_GPIO62_Pos            (30UL)                    /*!< GPIO62 (Bit 30)                                       */
14286 #define GPIO_INT1EN_GPIO62_Msk            (0x40000000UL)            /*!< GPIO62 (Bitfield-Mask: 0x01)                          */
14287 #define GPIO_INT1EN_GPIO61_Pos            (29UL)                    /*!< GPIO61 (Bit 29)                                       */
14288 #define GPIO_INT1EN_GPIO61_Msk            (0x20000000UL)            /*!< GPIO61 (Bitfield-Mask: 0x01)                          */
14289 #define GPIO_INT1EN_GPIO60_Pos            (28UL)                    /*!< GPIO60 (Bit 28)                                       */
14290 #define GPIO_INT1EN_GPIO60_Msk            (0x10000000UL)            /*!< GPIO60 (Bitfield-Mask: 0x01)                          */
14291 #define GPIO_INT1EN_GPIO59_Pos            (27UL)                    /*!< GPIO59 (Bit 27)                                       */
14292 #define GPIO_INT1EN_GPIO59_Msk            (0x8000000UL)             /*!< GPIO59 (Bitfield-Mask: 0x01)                          */
14293 #define GPIO_INT1EN_GPIO58_Pos            (26UL)                    /*!< GPIO58 (Bit 26)                                       */
14294 #define GPIO_INT1EN_GPIO58_Msk            (0x4000000UL)             /*!< GPIO58 (Bitfield-Mask: 0x01)                          */
14295 #define GPIO_INT1EN_GPIO57_Pos            (25UL)                    /*!< GPIO57 (Bit 25)                                       */
14296 #define GPIO_INT1EN_GPIO57_Msk            (0x2000000UL)             /*!< GPIO57 (Bitfield-Mask: 0x01)                          */
14297 #define GPIO_INT1EN_GPIO56_Pos            (24UL)                    /*!< GPIO56 (Bit 24)                                       */
14298 #define GPIO_INT1EN_GPIO56_Msk            (0x1000000UL)             /*!< GPIO56 (Bitfield-Mask: 0x01)                          */
14299 #define GPIO_INT1EN_GPIO55_Pos            (23UL)                    /*!< GPIO55 (Bit 23)                                       */
14300 #define GPIO_INT1EN_GPIO55_Msk            (0x800000UL)              /*!< GPIO55 (Bitfield-Mask: 0x01)                          */
14301 #define GPIO_INT1EN_GPIO54_Pos            (22UL)                    /*!< GPIO54 (Bit 22)                                       */
14302 #define GPIO_INT1EN_GPIO54_Msk            (0x400000UL)              /*!< GPIO54 (Bitfield-Mask: 0x01)                          */
14303 #define GPIO_INT1EN_GPIO53_Pos            (21UL)                    /*!< GPIO53 (Bit 21)                                       */
14304 #define GPIO_INT1EN_GPIO53_Msk            (0x200000UL)              /*!< GPIO53 (Bitfield-Mask: 0x01)                          */
14305 #define GPIO_INT1EN_GPIO52_Pos            (20UL)                    /*!< GPIO52 (Bit 20)                                       */
14306 #define GPIO_INT1EN_GPIO52_Msk            (0x100000UL)              /*!< GPIO52 (Bitfield-Mask: 0x01)                          */
14307 #define GPIO_INT1EN_GPIO51_Pos            (19UL)                    /*!< GPIO51 (Bit 19)                                       */
14308 #define GPIO_INT1EN_GPIO51_Msk            (0x80000UL)               /*!< GPIO51 (Bitfield-Mask: 0x01)                          */
14309 #define GPIO_INT1EN_GPIO50_Pos            (18UL)                    /*!< GPIO50 (Bit 18)                                       */
14310 #define GPIO_INT1EN_GPIO50_Msk            (0x40000UL)               /*!< GPIO50 (Bitfield-Mask: 0x01)                          */
14311 #define GPIO_INT1EN_GPIO49_Pos            (17UL)                    /*!< GPIO49 (Bit 17)                                       */
14312 #define GPIO_INT1EN_GPIO49_Msk            (0x20000UL)               /*!< GPIO49 (Bitfield-Mask: 0x01)                          */
14313 #define GPIO_INT1EN_GPIO48_Pos            (16UL)                    /*!< GPIO48 (Bit 16)                                       */
14314 #define GPIO_INT1EN_GPIO48_Msk            (0x10000UL)               /*!< GPIO48 (Bitfield-Mask: 0x01)                          */
14315 #define GPIO_INT1EN_GPIO47_Pos            (15UL)                    /*!< GPIO47 (Bit 15)                                       */
14316 #define GPIO_INT1EN_GPIO47_Msk            (0x8000UL)                /*!< GPIO47 (Bitfield-Mask: 0x01)                          */
14317 #define GPIO_INT1EN_GPIO46_Pos            (14UL)                    /*!< GPIO46 (Bit 14)                                       */
14318 #define GPIO_INT1EN_GPIO46_Msk            (0x4000UL)                /*!< GPIO46 (Bitfield-Mask: 0x01)                          */
14319 #define GPIO_INT1EN_GPIO45_Pos            (13UL)                    /*!< GPIO45 (Bit 13)                                       */
14320 #define GPIO_INT1EN_GPIO45_Msk            (0x2000UL)                /*!< GPIO45 (Bitfield-Mask: 0x01)                          */
14321 #define GPIO_INT1EN_GPIO44_Pos            (12UL)                    /*!< GPIO44 (Bit 12)                                       */
14322 #define GPIO_INT1EN_GPIO44_Msk            (0x1000UL)                /*!< GPIO44 (Bitfield-Mask: 0x01)                          */
14323 #define GPIO_INT1EN_GPIO43_Pos            (11UL)                    /*!< GPIO43 (Bit 11)                                       */
14324 #define GPIO_INT1EN_GPIO43_Msk            (0x800UL)                 /*!< GPIO43 (Bitfield-Mask: 0x01)                          */
14325 #define GPIO_INT1EN_GPIO42_Pos            (10UL)                    /*!< GPIO42 (Bit 10)                                       */
14326 #define GPIO_INT1EN_GPIO42_Msk            (0x400UL)                 /*!< GPIO42 (Bitfield-Mask: 0x01)                          */
14327 #define GPIO_INT1EN_GPIO41_Pos            (9UL)                     /*!< GPIO41 (Bit 9)                                        */
14328 #define GPIO_INT1EN_GPIO41_Msk            (0x200UL)                 /*!< GPIO41 (Bitfield-Mask: 0x01)                          */
14329 #define GPIO_INT1EN_GPIO40_Pos            (8UL)                     /*!< GPIO40 (Bit 8)                                        */
14330 #define GPIO_INT1EN_GPIO40_Msk            (0x100UL)                 /*!< GPIO40 (Bitfield-Mask: 0x01)                          */
14331 #define GPIO_INT1EN_GPIO39_Pos            (7UL)                     /*!< GPIO39 (Bit 7)                                        */
14332 #define GPIO_INT1EN_GPIO39_Msk            (0x80UL)                  /*!< GPIO39 (Bitfield-Mask: 0x01)                          */
14333 #define GPIO_INT1EN_GPIO38_Pos            (6UL)                     /*!< GPIO38 (Bit 6)                                        */
14334 #define GPIO_INT1EN_GPIO38_Msk            (0x40UL)                  /*!< GPIO38 (Bitfield-Mask: 0x01)                          */
14335 #define GPIO_INT1EN_GPIO37_Pos            (5UL)                     /*!< GPIO37 (Bit 5)                                        */
14336 #define GPIO_INT1EN_GPIO37_Msk            (0x20UL)                  /*!< GPIO37 (Bitfield-Mask: 0x01)                          */
14337 #define GPIO_INT1EN_GPIO36_Pos            (4UL)                     /*!< GPIO36 (Bit 4)                                        */
14338 #define GPIO_INT1EN_GPIO36_Msk            (0x10UL)                  /*!< GPIO36 (Bitfield-Mask: 0x01)                          */
14339 #define GPIO_INT1EN_GPIO35_Pos            (3UL)                     /*!< GPIO35 (Bit 3)                                        */
14340 #define GPIO_INT1EN_GPIO35_Msk            (0x8UL)                   /*!< GPIO35 (Bitfield-Mask: 0x01)                          */
14341 #define GPIO_INT1EN_GPIO34_Pos            (2UL)                     /*!< GPIO34 (Bit 2)                                        */
14342 #define GPIO_INT1EN_GPIO34_Msk            (0x4UL)                   /*!< GPIO34 (Bitfield-Mask: 0x01)                          */
14343 #define GPIO_INT1EN_GPIO33_Pos            (1UL)                     /*!< GPIO33 (Bit 1)                                        */
14344 #define GPIO_INT1EN_GPIO33_Msk            (0x2UL)                   /*!< GPIO33 (Bitfield-Mask: 0x01)                          */
14345 #define GPIO_INT1EN_GPIO32_Pos            (0UL)                     /*!< GPIO32 (Bit 0)                                        */
14346 #define GPIO_INT1EN_GPIO32_Msk            (0x1UL)                   /*!< GPIO32 (Bitfield-Mask: 0x01)                          */
14347 /* =======================================================  INT1STAT  ======================================================== */
14348 #define GPIO_INT1STAT_GPIO63_Pos          (31UL)                    /*!< GPIO63 (Bit 31)                                       */
14349 #define GPIO_INT1STAT_GPIO63_Msk          (0x80000000UL)            /*!< GPIO63 (Bitfield-Mask: 0x01)                          */
14350 #define GPIO_INT1STAT_GPIO62_Pos          (30UL)                    /*!< GPIO62 (Bit 30)                                       */
14351 #define GPIO_INT1STAT_GPIO62_Msk          (0x40000000UL)            /*!< GPIO62 (Bitfield-Mask: 0x01)                          */
14352 #define GPIO_INT1STAT_GPIO61_Pos          (29UL)                    /*!< GPIO61 (Bit 29)                                       */
14353 #define GPIO_INT1STAT_GPIO61_Msk          (0x20000000UL)            /*!< GPIO61 (Bitfield-Mask: 0x01)                          */
14354 #define GPIO_INT1STAT_GPIO60_Pos          (28UL)                    /*!< GPIO60 (Bit 28)                                       */
14355 #define GPIO_INT1STAT_GPIO60_Msk          (0x10000000UL)            /*!< GPIO60 (Bitfield-Mask: 0x01)                          */
14356 #define GPIO_INT1STAT_GPIO59_Pos          (27UL)                    /*!< GPIO59 (Bit 27)                                       */
14357 #define GPIO_INT1STAT_GPIO59_Msk          (0x8000000UL)             /*!< GPIO59 (Bitfield-Mask: 0x01)                          */
14358 #define GPIO_INT1STAT_GPIO58_Pos          (26UL)                    /*!< GPIO58 (Bit 26)                                       */
14359 #define GPIO_INT1STAT_GPIO58_Msk          (0x4000000UL)             /*!< GPIO58 (Bitfield-Mask: 0x01)                          */
14360 #define GPIO_INT1STAT_GPIO57_Pos          (25UL)                    /*!< GPIO57 (Bit 25)                                       */
14361 #define GPIO_INT1STAT_GPIO57_Msk          (0x2000000UL)             /*!< GPIO57 (Bitfield-Mask: 0x01)                          */
14362 #define GPIO_INT1STAT_GPIO56_Pos          (24UL)                    /*!< GPIO56 (Bit 24)                                       */
14363 #define GPIO_INT1STAT_GPIO56_Msk          (0x1000000UL)             /*!< GPIO56 (Bitfield-Mask: 0x01)                          */
14364 #define GPIO_INT1STAT_GPIO55_Pos          (23UL)                    /*!< GPIO55 (Bit 23)                                       */
14365 #define GPIO_INT1STAT_GPIO55_Msk          (0x800000UL)              /*!< GPIO55 (Bitfield-Mask: 0x01)                          */
14366 #define GPIO_INT1STAT_GPIO54_Pos          (22UL)                    /*!< GPIO54 (Bit 22)                                       */
14367 #define GPIO_INT1STAT_GPIO54_Msk          (0x400000UL)              /*!< GPIO54 (Bitfield-Mask: 0x01)                          */
14368 #define GPIO_INT1STAT_GPIO53_Pos          (21UL)                    /*!< GPIO53 (Bit 21)                                       */
14369 #define GPIO_INT1STAT_GPIO53_Msk          (0x200000UL)              /*!< GPIO53 (Bitfield-Mask: 0x01)                          */
14370 #define GPIO_INT1STAT_GPIO52_Pos          (20UL)                    /*!< GPIO52 (Bit 20)                                       */
14371 #define GPIO_INT1STAT_GPIO52_Msk          (0x100000UL)              /*!< GPIO52 (Bitfield-Mask: 0x01)                          */
14372 #define GPIO_INT1STAT_GPIO51_Pos          (19UL)                    /*!< GPIO51 (Bit 19)                                       */
14373 #define GPIO_INT1STAT_GPIO51_Msk          (0x80000UL)               /*!< GPIO51 (Bitfield-Mask: 0x01)                          */
14374 #define GPIO_INT1STAT_GPIO50_Pos          (18UL)                    /*!< GPIO50 (Bit 18)                                       */
14375 #define GPIO_INT1STAT_GPIO50_Msk          (0x40000UL)               /*!< GPIO50 (Bitfield-Mask: 0x01)                          */
14376 #define GPIO_INT1STAT_GPIO49_Pos          (17UL)                    /*!< GPIO49 (Bit 17)                                       */
14377 #define GPIO_INT1STAT_GPIO49_Msk          (0x20000UL)               /*!< GPIO49 (Bitfield-Mask: 0x01)                          */
14378 #define GPIO_INT1STAT_GPIO48_Pos          (16UL)                    /*!< GPIO48 (Bit 16)                                       */
14379 #define GPIO_INT1STAT_GPIO48_Msk          (0x10000UL)               /*!< GPIO48 (Bitfield-Mask: 0x01)                          */
14380 #define GPIO_INT1STAT_GPIO47_Pos          (15UL)                    /*!< GPIO47 (Bit 15)                                       */
14381 #define GPIO_INT1STAT_GPIO47_Msk          (0x8000UL)                /*!< GPIO47 (Bitfield-Mask: 0x01)                          */
14382 #define GPIO_INT1STAT_GPIO46_Pos          (14UL)                    /*!< GPIO46 (Bit 14)                                       */
14383 #define GPIO_INT1STAT_GPIO46_Msk          (0x4000UL)                /*!< GPIO46 (Bitfield-Mask: 0x01)                          */
14384 #define GPIO_INT1STAT_GPIO45_Pos          (13UL)                    /*!< GPIO45 (Bit 13)                                       */
14385 #define GPIO_INT1STAT_GPIO45_Msk          (0x2000UL)                /*!< GPIO45 (Bitfield-Mask: 0x01)                          */
14386 #define GPIO_INT1STAT_GPIO44_Pos          (12UL)                    /*!< GPIO44 (Bit 12)                                       */
14387 #define GPIO_INT1STAT_GPIO44_Msk          (0x1000UL)                /*!< GPIO44 (Bitfield-Mask: 0x01)                          */
14388 #define GPIO_INT1STAT_GPIO43_Pos          (11UL)                    /*!< GPIO43 (Bit 11)                                       */
14389 #define GPIO_INT1STAT_GPIO43_Msk          (0x800UL)                 /*!< GPIO43 (Bitfield-Mask: 0x01)                          */
14390 #define GPIO_INT1STAT_GPIO42_Pos          (10UL)                    /*!< GPIO42 (Bit 10)                                       */
14391 #define GPIO_INT1STAT_GPIO42_Msk          (0x400UL)                 /*!< GPIO42 (Bitfield-Mask: 0x01)                          */
14392 #define GPIO_INT1STAT_GPIO41_Pos          (9UL)                     /*!< GPIO41 (Bit 9)                                        */
14393 #define GPIO_INT1STAT_GPIO41_Msk          (0x200UL)                 /*!< GPIO41 (Bitfield-Mask: 0x01)                          */
14394 #define GPIO_INT1STAT_GPIO40_Pos          (8UL)                     /*!< GPIO40 (Bit 8)                                        */
14395 #define GPIO_INT1STAT_GPIO40_Msk          (0x100UL)                 /*!< GPIO40 (Bitfield-Mask: 0x01)                          */
14396 #define GPIO_INT1STAT_GPIO39_Pos          (7UL)                     /*!< GPIO39 (Bit 7)                                        */
14397 #define GPIO_INT1STAT_GPIO39_Msk          (0x80UL)                  /*!< GPIO39 (Bitfield-Mask: 0x01)                          */
14398 #define GPIO_INT1STAT_GPIO38_Pos          (6UL)                     /*!< GPIO38 (Bit 6)                                        */
14399 #define GPIO_INT1STAT_GPIO38_Msk          (0x40UL)                  /*!< GPIO38 (Bitfield-Mask: 0x01)                          */
14400 #define GPIO_INT1STAT_GPIO37_Pos          (5UL)                     /*!< GPIO37 (Bit 5)                                        */
14401 #define GPIO_INT1STAT_GPIO37_Msk          (0x20UL)                  /*!< GPIO37 (Bitfield-Mask: 0x01)                          */
14402 #define GPIO_INT1STAT_GPIO36_Pos          (4UL)                     /*!< GPIO36 (Bit 4)                                        */
14403 #define GPIO_INT1STAT_GPIO36_Msk          (0x10UL)                  /*!< GPIO36 (Bitfield-Mask: 0x01)                          */
14404 #define GPIO_INT1STAT_GPIO35_Pos          (3UL)                     /*!< GPIO35 (Bit 3)                                        */
14405 #define GPIO_INT1STAT_GPIO35_Msk          (0x8UL)                   /*!< GPIO35 (Bitfield-Mask: 0x01)                          */
14406 #define GPIO_INT1STAT_GPIO34_Pos          (2UL)                     /*!< GPIO34 (Bit 2)                                        */
14407 #define GPIO_INT1STAT_GPIO34_Msk          (0x4UL)                   /*!< GPIO34 (Bitfield-Mask: 0x01)                          */
14408 #define GPIO_INT1STAT_GPIO33_Pos          (1UL)                     /*!< GPIO33 (Bit 1)                                        */
14409 #define GPIO_INT1STAT_GPIO33_Msk          (0x2UL)                   /*!< GPIO33 (Bitfield-Mask: 0x01)                          */
14410 #define GPIO_INT1STAT_GPIO32_Pos          (0UL)                     /*!< GPIO32 (Bit 0)                                        */
14411 #define GPIO_INT1STAT_GPIO32_Msk          (0x1UL)                   /*!< GPIO32 (Bitfield-Mask: 0x01)                          */
14412 /* ========================================================  INT1CLR  ======================================================== */
14413 #define GPIO_INT1CLR_GPIO63_Pos           (31UL)                    /*!< GPIO63 (Bit 31)                                       */
14414 #define GPIO_INT1CLR_GPIO63_Msk           (0x80000000UL)            /*!< GPIO63 (Bitfield-Mask: 0x01)                          */
14415 #define GPIO_INT1CLR_GPIO62_Pos           (30UL)                    /*!< GPIO62 (Bit 30)                                       */
14416 #define GPIO_INT1CLR_GPIO62_Msk           (0x40000000UL)            /*!< GPIO62 (Bitfield-Mask: 0x01)                          */
14417 #define GPIO_INT1CLR_GPIO61_Pos           (29UL)                    /*!< GPIO61 (Bit 29)                                       */
14418 #define GPIO_INT1CLR_GPIO61_Msk           (0x20000000UL)            /*!< GPIO61 (Bitfield-Mask: 0x01)                          */
14419 #define GPIO_INT1CLR_GPIO60_Pos           (28UL)                    /*!< GPIO60 (Bit 28)                                       */
14420 #define GPIO_INT1CLR_GPIO60_Msk           (0x10000000UL)            /*!< GPIO60 (Bitfield-Mask: 0x01)                          */
14421 #define GPIO_INT1CLR_GPIO59_Pos           (27UL)                    /*!< GPIO59 (Bit 27)                                       */
14422 #define GPIO_INT1CLR_GPIO59_Msk           (0x8000000UL)             /*!< GPIO59 (Bitfield-Mask: 0x01)                          */
14423 #define GPIO_INT1CLR_GPIO58_Pos           (26UL)                    /*!< GPIO58 (Bit 26)                                       */
14424 #define GPIO_INT1CLR_GPIO58_Msk           (0x4000000UL)             /*!< GPIO58 (Bitfield-Mask: 0x01)                          */
14425 #define GPIO_INT1CLR_GPIO57_Pos           (25UL)                    /*!< GPIO57 (Bit 25)                                       */
14426 #define GPIO_INT1CLR_GPIO57_Msk           (0x2000000UL)             /*!< GPIO57 (Bitfield-Mask: 0x01)                          */
14427 #define GPIO_INT1CLR_GPIO56_Pos           (24UL)                    /*!< GPIO56 (Bit 24)                                       */
14428 #define GPIO_INT1CLR_GPIO56_Msk           (0x1000000UL)             /*!< GPIO56 (Bitfield-Mask: 0x01)                          */
14429 #define GPIO_INT1CLR_GPIO55_Pos           (23UL)                    /*!< GPIO55 (Bit 23)                                       */
14430 #define GPIO_INT1CLR_GPIO55_Msk           (0x800000UL)              /*!< GPIO55 (Bitfield-Mask: 0x01)                          */
14431 #define GPIO_INT1CLR_GPIO54_Pos           (22UL)                    /*!< GPIO54 (Bit 22)                                       */
14432 #define GPIO_INT1CLR_GPIO54_Msk           (0x400000UL)              /*!< GPIO54 (Bitfield-Mask: 0x01)                          */
14433 #define GPIO_INT1CLR_GPIO53_Pos           (21UL)                    /*!< GPIO53 (Bit 21)                                       */
14434 #define GPIO_INT1CLR_GPIO53_Msk           (0x200000UL)              /*!< GPIO53 (Bitfield-Mask: 0x01)                          */
14435 #define GPIO_INT1CLR_GPIO52_Pos           (20UL)                    /*!< GPIO52 (Bit 20)                                       */
14436 #define GPIO_INT1CLR_GPIO52_Msk           (0x100000UL)              /*!< GPIO52 (Bitfield-Mask: 0x01)                          */
14437 #define GPIO_INT1CLR_GPIO51_Pos           (19UL)                    /*!< GPIO51 (Bit 19)                                       */
14438 #define GPIO_INT1CLR_GPIO51_Msk           (0x80000UL)               /*!< GPIO51 (Bitfield-Mask: 0x01)                          */
14439 #define GPIO_INT1CLR_GPIO50_Pos           (18UL)                    /*!< GPIO50 (Bit 18)                                       */
14440 #define GPIO_INT1CLR_GPIO50_Msk           (0x40000UL)               /*!< GPIO50 (Bitfield-Mask: 0x01)                          */
14441 #define GPIO_INT1CLR_GPIO49_Pos           (17UL)                    /*!< GPIO49 (Bit 17)                                       */
14442 #define GPIO_INT1CLR_GPIO49_Msk           (0x20000UL)               /*!< GPIO49 (Bitfield-Mask: 0x01)                          */
14443 #define GPIO_INT1CLR_GPIO48_Pos           (16UL)                    /*!< GPIO48 (Bit 16)                                       */
14444 #define GPIO_INT1CLR_GPIO48_Msk           (0x10000UL)               /*!< GPIO48 (Bitfield-Mask: 0x01)                          */
14445 #define GPIO_INT1CLR_GPIO47_Pos           (15UL)                    /*!< GPIO47 (Bit 15)                                       */
14446 #define GPIO_INT1CLR_GPIO47_Msk           (0x8000UL)                /*!< GPIO47 (Bitfield-Mask: 0x01)                          */
14447 #define GPIO_INT1CLR_GPIO46_Pos           (14UL)                    /*!< GPIO46 (Bit 14)                                       */
14448 #define GPIO_INT1CLR_GPIO46_Msk           (0x4000UL)                /*!< GPIO46 (Bitfield-Mask: 0x01)                          */
14449 #define GPIO_INT1CLR_GPIO45_Pos           (13UL)                    /*!< GPIO45 (Bit 13)                                       */
14450 #define GPIO_INT1CLR_GPIO45_Msk           (0x2000UL)                /*!< GPIO45 (Bitfield-Mask: 0x01)                          */
14451 #define GPIO_INT1CLR_GPIO44_Pos           (12UL)                    /*!< GPIO44 (Bit 12)                                       */
14452 #define GPIO_INT1CLR_GPIO44_Msk           (0x1000UL)                /*!< GPIO44 (Bitfield-Mask: 0x01)                          */
14453 #define GPIO_INT1CLR_GPIO43_Pos           (11UL)                    /*!< GPIO43 (Bit 11)                                       */
14454 #define GPIO_INT1CLR_GPIO43_Msk           (0x800UL)                 /*!< GPIO43 (Bitfield-Mask: 0x01)                          */
14455 #define GPIO_INT1CLR_GPIO42_Pos           (10UL)                    /*!< GPIO42 (Bit 10)                                       */
14456 #define GPIO_INT1CLR_GPIO42_Msk           (0x400UL)                 /*!< GPIO42 (Bitfield-Mask: 0x01)                          */
14457 #define GPIO_INT1CLR_GPIO41_Pos           (9UL)                     /*!< GPIO41 (Bit 9)                                        */
14458 #define GPIO_INT1CLR_GPIO41_Msk           (0x200UL)                 /*!< GPIO41 (Bitfield-Mask: 0x01)                          */
14459 #define GPIO_INT1CLR_GPIO40_Pos           (8UL)                     /*!< GPIO40 (Bit 8)                                        */
14460 #define GPIO_INT1CLR_GPIO40_Msk           (0x100UL)                 /*!< GPIO40 (Bitfield-Mask: 0x01)                          */
14461 #define GPIO_INT1CLR_GPIO39_Pos           (7UL)                     /*!< GPIO39 (Bit 7)                                        */
14462 #define GPIO_INT1CLR_GPIO39_Msk           (0x80UL)                  /*!< GPIO39 (Bitfield-Mask: 0x01)                          */
14463 #define GPIO_INT1CLR_GPIO38_Pos           (6UL)                     /*!< GPIO38 (Bit 6)                                        */
14464 #define GPIO_INT1CLR_GPIO38_Msk           (0x40UL)                  /*!< GPIO38 (Bitfield-Mask: 0x01)                          */
14465 #define GPIO_INT1CLR_GPIO37_Pos           (5UL)                     /*!< GPIO37 (Bit 5)                                        */
14466 #define GPIO_INT1CLR_GPIO37_Msk           (0x20UL)                  /*!< GPIO37 (Bitfield-Mask: 0x01)                          */
14467 #define GPIO_INT1CLR_GPIO36_Pos           (4UL)                     /*!< GPIO36 (Bit 4)                                        */
14468 #define GPIO_INT1CLR_GPIO36_Msk           (0x10UL)                  /*!< GPIO36 (Bitfield-Mask: 0x01)                          */
14469 #define GPIO_INT1CLR_GPIO35_Pos           (3UL)                     /*!< GPIO35 (Bit 3)                                        */
14470 #define GPIO_INT1CLR_GPIO35_Msk           (0x8UL)                   /*!< GPIO35 (Bitfield-Mask: 0x01)                          */
14471 #define GPIO_INT1CLR_GPIO34_Pos           (2UL)                     /*!< GPIO34 (Bit 2)                                        */
14472 #define GPIO_INT1CLR_GPIO34_Msk           (0x4UL)                   /*!< GPIO34 (Bitfield-Mask: 0x01)                          */
14473 #define GPIO_INT1CLR_GPIO33_Pos           (1UL)                     /*!< GPIO33 (Bit 1)                                        */
14474 #define GPIO_INT1CLR_GPIO33_Msk           (0x2UL)                   /*!< GPIO33 (Bitfield-Mask: 0x01)                          */
14475 #define GPIO_INT1CLR_GPIO32_Pos           (0UL)                     /*!< GPIO32 (Bit 0)                                        */
14476 #define GPIO_INT1CLR_GPIO32_Msk           (0x1UL)                   /*!< GPIO32 (Bitfield-Mask: 0x01)                          */
14477 /* ========================================================  INT1SET  ======================================================== */
14478 #define GPIO_INT1SET_GPIO63_Pos           (31UL)                    /*!< GPIO63 (Bit 31)                                       */
14479 #define GPIO_INT1SET_GPIO63_Msk           (0x80000000UL)            /*!< GPIO63 (Bitfield-Mask: 0x01)                          */
14480 #define GPIO_INT1SET_GPIO62_Pos           (30UL)                    /*!< GPIO62 (Bit 30)                                       */
14481 #define GPIO_INT1SET_GPIO62_Msk           (0x40000000UL)            /*!< GPIO62 (Bitfield-Mask: 0x01)                          */
14482 #define GPIO_INT1SET_GPIO61_Pos           (29UL)                    /*!< GPIO61 (Bit 29)                                       */
14483 #define GPIO_INT1SET_GPIO61_Msk           (0x20000000UL)            /*!< GPIO61 (Bitfield-Mask: 0x01)                          */
14484 #define GPIO_INT1SET_GPIO60_Pos           (28UL)                    /*!< GPIO60 (Bit 28)                                       */
14485 #define GPIO_INT1SET_GPIO60_Msk           (0x10000000UL)            /*!< GPIO60 (Bitfield-Mask: 0x01)                          */
14486 #define GPIO_INT1SET_GPIO59_Pos           (27UL)                    /*!< GPIO59 (Bit 27)                                       */
14487 #define GPIO_INT1SET_GPIO59_Msk           (0x8000000UL)             /*!< GPIO59 (Bitfield-Mask: 0x01)                          */
14488 #define GPIO_INT1SET_GPIO58_Pos           (26UL)                    /*!< GPIO58 (Bit 26)                                       */
14489 #define GPIO_INT1SET_GPIO58_Msk           (0x4000000UL)             /*!< GPIO58 (Bitfield-Mask: 0x01)                          */
14490 #define GPIO_INT1SET_GPIO57_Pos           (25UL)                    /*!< GPIO57 (Bit 25)                                       */
14491 #define GPIO_INT1SET_GPIO57_Msk           (0x2000000UL)             /*!< GPIO57 (Bitfield-Mask: 0x01)                          */
14492 #define GPIO_INT1SET_GPIO56_Pos           (24UL)                    /*!< GPIO56 (Bit 24)                                       */
14493 #define GPIO_INT1SET_GPIO56_Msk           (0x1000000UL)             /*!< GPIO56 (Bitfield-Mask: 0x01)                          */
14494 #define GPIO_INT1SET_GPIO55_Pos           (23UL)                    /*!< GPIO55 (Bit 23)                                       */
14495 #define GPIO_INT1SET_GPIO55_Msk           (0x800000UL)              /*!< GPIO55 (Bitfield-Mask: 0x01)                          */
14496 #define GPIO_INT1SET_GPIO54_Pos           (22UL)                    /*!< GPIO54 (Bit 22)                                       */
14497 #define GPIO_INT1SET_GPIO54_Msk           (0x400000UL)              /*!< GPIO54 (Bitfield-Mask: 0x01)                          */
14498 #define GPIO_INT1SET_GPIO53_Pos           (21UL)                    /*!< GPIO53 (Bit 21)                                       */
14499 #define GPIO_INT1SET_GPIO53_Msk           (0x200000UL)              /*!< GPIO53 (Bitfield-Mask: 0x01)                          */
14500 #define GPIO_INT1SET_GPIO52_Pos           (20UL)                    /*!< GPIO52 (Bit 20)                                       */
14501 #define GPIO_INT1SET_GPIO52_Msk           (0x100000UL)              /*!< GPIO52 (Bitfield-Mask: 0x01)                          */
14502 #define GPIO_INT1SET_GPIO51_Pos           (19UL)                    /*!< GPIO51 (Bit 19)                                       */
14503 #define GPIO_INT1SET_GPIO51_Msk           (0x80000UL)               /*!< GPIO51 (Bitfield-Mask: 0x01)                          */
14504 #define GPIO_INT1SET_GPIO50_Pos           (18UL)                    /*!< GPIO50 (Bit 18)                                       */
14505 #define GPIO_INT1SET_GPIO50_Msk           (0x40000UL)               /*!< GPIO50 (Bitfield-Mask: 0x01)                          */
14506 #define GPIO_INT1SET_GPIO49_Pos           (17UL)                    /*!< GPIO49 (Bit 17)                                       */
14507 #define GPIO_INT1SET_GPIO49_Msk           (0x20000UL)               /*!< GPIO49 (Bitfield-Mask: 0x01)                          */
14508 #define GPIO_INT1SET_GPIO48_Pos           (16UL)                    /*!< GPIO48 (Bit 16)                                       */
14509 #define GPIO_INT1SET_GPIO48_Msk           (0x10000UL)               /*!< GPIO48 (Bitfield-Mask: 0x01)                          */
14510 #define GPIO_INT1SET_GPIO47_Pos           (15UL)                    /*!< GPIO47 (Bit 15)                                       */
14511 #define GPIO_INT1SET_GPIO47_Msk           (0x8000UL)                /*!< GPIO47 (Bitfield-Mask: 0x01)                          */
14512 #define GPIO_INT1SET_GPIO46_Pos           (14UL)                    /*!< GPIO46 (Bit 14)                                       */
14513 #define GPIO_INT1SET_GPIO46_Msk           (0x4000UL)                /*!< GPIO46 (Bitfield-Mask: 0x01)                          */
14514 #define GPIO_INT1SET_GPIO45_Pos           (13UL)                    /*!< GPIO45 (Bit 13)                                       */
14515 #define GPIO_INT1SET_GPIO45_Msk           (0x2000UL)                /*!< GPIO45 (Bitfield-Mask: 0x01)                          */
14516 #define GPIO_INT1SET_GPIO44_Pos           (12UL)                    /*!< GPIO44 (Bit 12)                                       */
14517 #define GPIO_INT1SET_GPIO44_Msk           (0x1000UL)                /*!< GPIO44 (Bitfield-Mask: 0x01)                          */
14518 #define GPIO_INT1SET_GPIO43_Pos           (11UL)                    /*!< GPIO43 (Bit 11)                                       */
14519 #define GPIO_INT1SET_GPIO43_Msk           (0x800UL)                 /*!< GPIO43 (Bitfield-Mask: 0x01)                          */
14520 #define GPIO_INT1SET_GPIO42_Pos           (10UL)                    /*!< GPIO42 (Bit 10)                                       */
14521 #define GPIO_INT1SET_GPIO42_Msk           (0x400UL)                 /*!< GPIO42 (Bitfield-Mask: 0x01)                          */
14522 #define GPIO_INT1SET_GPIO41_Pos           (9UL)                     /*!< GPIO41 (Bit 9)                                        */
14523 #define GPIO_INT1SET_GPIO41_Msk           (0x200UL)                 /*!< GPIO41 (Bitfield-Mask: 0x01)                          */
14524 #define GPIO_INT1SET_GPIO40_Pos           (8UL)                     /*!< GPIO40 (Bit 8)                                        */
14525 #define GPIO_INT1SET_GPIO40_Msk           (0x100UL)                 /*!< GPIO40 (Bitfield-Mask: 0x01)                          */
14526 #define GPIO_INT1SET_GPIO39_Pos           (7UL)                     /*!< GPIO39 (Bit 7)                                        */
14527 #define GPIO_INT1SET_GPIO39_Msk           (0x80UL)                  /*!< GPIO39 (Bitfield-Mask: 0x01)                          */
14528 #define GPIO_INT1SET_GPIO38_Pos           (6UL)                     /*!< GPIO38 (Bit 6)                                        */
14529 #define GPIO_INT1SET_GPIO38_Msk           (0x40UL)                  /*!< GPIO38 (Bitfield-Mask: 0x01)                          */
14530 #define GPIO_INT1SET_GPIO37_Pos           (5UL)                     /*!< GPIO37 (Bit 5)                                        */
14531 #define GPIO_INT1SET_GPIO37_Msk           (0x20UL)                  /*!< GPIO37 (Bitfield-Mask: 0x01)                          */
14532 #define GPIO_INT1SET_GPIO36_Pos           (4UL)                     /*!< GPIO36 (Bit 4)                                        */
14533 #define GPIO_INT1SET_GPIO36_Msk           (0x10UL)                  /*!< GPIO36 (Bitfield-Mask: 0x01)                          */
14534 #define GPIO_INT1SET_GPIO35_Pos           (3UL)                     /*!< GPIO35 (Bit 3)                                        */
14535 #define GPIO_INT1SET_GPIO35_Msk           (0x8UL)                   /*!< GPIO35 (Bitfield-Mask: 0x01)                          */
14536 #define GPIO_INT1SET_GPIO34_Pos           (2UL)                     /*!< GPIO34 (Bit 2)                                        */
14537 #define GPIO_INT1SET_GPIO34_Msk           (0x4UL)                   /*!< GPIO34 (Bitfield-Mask: 0x01)                          */
14538 #define GPIO_INT1SET_GPIO33_Pos           (1UL)                     /*!< GPIO33 (Bit 1)                                        */
14539 #define GPIO_INT1SET_GPIO33_Msk           (0x2UL)                   /*!< GPIO33 (Bitfield-Mask: 0x01)                          */
14540 #define GPIO_INT1SET_GPIO32_Pos           (0UL)                     /*!< GPIO32 (Bit 0)                                        */
14541 #define GPIO_INT1SET_GPIO32_Msk           (0x1UL)                   /*!< GPIO32 (Bitfield-Mask: 0x01)                          */
14542 /* ========================================================  INT2EN  ========================================================= */
14543 #define GPIO_INT2EN_GPIO73_Pos            (9UL)                     /*!< GPIO73 (Bit 9)                                        */
14544 #define GPIO_INT2EN_GPIO73_Msk            (0x200UL)                 /*!< GPIO73 (Bitfield-Mask: 0x01)                          */
14545 #define GPIO_INT2EN_GPIO72_Pos            (8UL)                     /*!< GPIO72 (Bit 8)                                        */
14546 #define GPIO_INT2EN_GPIO72_Msk            (0x100UL)                 /*!< GPIO72 (Bitfield-Mask: 0x01)                          */
14547 #define GPIO_INT2EN_GPIO71_Pos            (7UL)                     /*!< GPIO71 (Bit 7)                                        */
14548 #define GPIO_INT2EN_GPIO71_Msk            (0x80UL)                  /*!< GPIO71 (Bitfield-Mask: 0x01)                          */
14549 #define GPIO_INT2EN_GPIO70_Pos            (6UL)                     /*!< GPIO70 (Bit 6)                                        */
14550 #define GPIO_INT2EN_GPIO70_Msk            (0x40UL)                  /*!< GPIO70 (Bitfield-Mask: 0x01)                          */
14551 #define GPIO_INT2EN_GPIO69_Pos            (5UL)                     /*!< GPIO69 (Bit 5)                                        */
14552 #define GPIO_INT2EN_GPIO69_Msk            (0x20UL)                  /*!< GPIO69 (Bitfield-Mask: 0x01)                          */
14553 #define GPIO_INT2EN_GPIO68_Pos            (4UL)                     /*!< GPIO68 (Bit 4)                                        */
14554 #define GPIO_INT2EN_GPIO68_Msk            (0x10UL)                  /*!< GPIO68 (Bitfield-Mask: 0x01)                          */
14555 #define GPIO_INT2EN_GPIO67_Pos            (3UL)                     /*!< GPIO67 (Bit 3)                                        */
14556 #define GPIO_INT2EN_GPIO67_Msk            (0x8UL)                   /*!< GPIO67 (Bitfield-Mask: 0x01)                          */
14557 #define GPIO_INT2EN_GPIO66_Pos            (2UL)                     /*!< GPIO66 (Bit 2)                                        */
14558 #define GPIO_INT2EN_GPIO66_Msk            (0x4UL)                   /*!< GPIO66 (Bitfield-Mask: 0x01)                          */
14559 #define GPIO_INT2EN_GPIO65_Pos            (1UL)                     /*!< GPIO65 (Bit 1)                                        */
14560 #define GPIO_INT2EN_GPIO65_Msk            (0x2UL)                   /*!< GPIO65 (Bitfield-Mask: 0x01)                          */
14561 #define GPIO_INT2EN_GPIO64_Pos            (0UL)                     /*!< GPIO64 (Bit 0)                                        */
14562 #define GPIO_INT2EN_GPIO64_Msk            (0x1UL)                   /*!< GPIO64 (Bitfield-Mask: 0x01)                          */
14563 /* =======================================================  INT2STAT  ======================================================== */
14564 #define GPIO_INT2STAT_GPIO73_Pos          (9UL)                     /*!< GPIO73 (Bit 9)                                        */
14565 #define GPIO_INT2STAT_GPIO73_Msk          (0x200UL)                 /*!< GPIO73 (Bitfield-Mask: 0x01)                          */
14566 #define GPIO_INT2STAT_GPIO72_Pos          (8UL)                     /*!< GPIO72 (Bit 8)                                        */
14567 #define GPIO_INT2STAT_GPIO72_Msk          (0x100UL)                 /*!< GPIO72 (Bitfield-Mask: 0x01)                          */
14568 #define GPIO_INT2STAT_GPIO71_Pos          (7UL)                     /*!< GPIO71 (Bit 7)                                        */
14569 #define GPIO_INT2STAT_GPIO71_Msk          (0x80UL)                  /*!< GPIO71 (Bitfield-Mask: 0x01)                          */
14570 #define GPIO_INT2STAT_GPIO70_Pos          (6UL)                     /*!< GPIO70 (Bit 6)                                        */
14571 #define GPIO_INT2STAT_GPIO70_Msk          (0x40UL)                  /*!< GPIO70 (Bitfield-Mask: 0x01)                          */
14572 #define GPIO_INT2STAT_GPIO69_Pos          (5UL)                     /*!< GPIO69 (Bit 5)                                        */
14573 #define GPIO_INT2STAT_GPIO69_Msk          (0x20UL)                  /*!< GPIO69 (Bitfield-Mask: 0x01)                          */
14574 #define GPIO_INT2STAT_GPIO68_Pos          (4UL)                     /*!< GPIO68 (Bit 4)                                        */
14575 #define GPIO_INT2STAT_GPIO68_Msk          (0x10UL)                  /*!< GPIO68 (Bitfield-Mask: 0x01)                          */
14576 #define GPIO_INT2STAT_GPIO67_Pos          (3UL)                     /*!< GPIO67 (Bit 3)                                        */
14577 #define GPIO_INT2STAT_GPIO67_Msk          (0x8UL)                   /*!< GPIO67 (Bitfield-Mask: 0x01)                          */
14578 #define GPIO_INT2STAT_GPIO66_Pos          (2UL)                     /*!< GPIO66 (Bit 2)                                        */
14579 #define GPIO_INT2STAT_GPIO66_Msk          (0x4UL)                   /*!< GPIO66 (Bitfield-Mask: 0x01)                          */
14580 #define GPIO_INT2STAT_GPIO65_Pos          (1UL)                     /*!< GPIO65 (Bit 1)                                        */
14581 #define GPIO_INT2STAT_GPIO65_Msk          (0x2UL)                   /*!< GPIO65 (Bitfield-Mask: 0x01)                          */
14582 #define GPIO_INT2STAT_GPIO64_Pos          (0UL)                     /*!< GPIO64 (Bit 0)                                        */
14583 #define GPIO_INT2STAT_GPIO64_Msk          (0x1UL)                   /*!< GPIO64 (Bitfield-Mask: 0x01)                          */
14584 /* ========================================================  INT2CLR  ======================================================== */
14585 #define GPIO_INT2CLR_GPIO73_Pos           (9UL)                     /*!< GPIO73 (Bit 9)                                        */
14586 #define GPIO_INT2CLR_GPIO73_Msk           (0x200UL)                 /*!< GPIO73 (Bitfield-Mask: 0x01)                          */
14587 #define GPIO_INT2CLR_GPIO72_Pos           (8UL)                     /*!< GPIO72 (Bit 8)                                        */
14588 #define GPIO_INT2CLR_GPIO72_Msk           (0x100UL)                 /*!< GPIO72 (Bitfield-Mask: 0x01)                          */
14589 #define GPIO_INT2CLR_GPIO71_Pos           (7UL)                     /*!< GPIO71 (Bit 7)                                        */
14590 #define GPIO_INT2CLR_GPIO71_Msk           (0x80UL)                  /*!< GPIO71 (Bitfield-Mask: 0x01)                          */
14591 #define GPIO_INT2CLR_GPIO70_Pos           (6UL)                     /*!< GPIO70 (Bit 6)                                        */
14592 #define GPIO_INT2CLR_GPIO70_Msk           (0x40UL)                  /*!< GPIO70 (Bitfield-Mask: 0x01)                          */
14593 #define GPIO_INT2CLR_GPIO69_Pos           (5UL)                     /*!< GPIO69 (Bit 5)                                        */
14594 #define GPIO_INT2CLR_GPIO69_Msk           (0x20UL)                  /*!< GPIO69 (Bitfield-Mask: 0x01)                          */
14595 #define GPIO_INT2CLR_GPIO68_Pos           (4UL)                     /*!< GPIO68 (Bit 4)                                        */
14596 #define GPIO_INT2CLR_GPIO68_Msk           (0x10UL)                  /*!< GPIO68 (Bitfield-Mask: 0x01)                          */
14597 #define GPIO_INT2CLR_GPIO67_Pos           (3UL)                     /*!< GPIO67 (Bit 3)                                        */
14598 #define GPIO_INT2CLR_GPIO67_Msk           (0x8UL)                   /*!< GPIO67 (Bitfield-Mask: 0x01)                          */
14599 #define GPIO_INT2CLR_GPIO66_Pos           (2UL)                     /*!< GPIO66 (Bit 2)                                        */
14600 #define GPIO_INT2CLR_GPIO66_Msk           (0x4UL)                   /*!< GPIO66 (Bitfield-Mask: 0x01)                          */
14601 #define GPIO_INT2CLR_GPIO65_Pos           (1UL)                     /*!< GPIO65 (Bit 1)                                        */
14602 #define GPIO_INT2CLR_GPIO65_Msk           (0x2UL)                   /*!< GPIO65 (Bitfield-Mask: 0x01)                          */
14603 #define GPIO_INT2CLR_GPIO64_Pos           (0UL)                     /*!< GPIO64 (Bit 0)                                        */
14604 #define GPIO_INT2CLR_GPIO64_Msk           (0x1UL)                   /*!< GPIO64 (Bitfield-Mask: 0x01)                          */
14605 /* ========================================================  INT2SET  ======================================================== */
14606 #define GPIO_INT2SET_GPIO73_Pos           (9UL)                     /*!< GPIO73 (Bit 9)                                        */
14607 #define GPIO_INT2SET_GPIO73_Msk           (0x200UL)                 /*!< GPIO73 (Bitfield-Mask: 0x01)                          */
14608 #define GPIO_INT2SET_GPIO72_Pos           (8UL)                     /*!< GPIO72 (Bit 8)                                        */
14609 #define GPIO_INT2SET_GPIO72_Msk           (0x100UL)                 /*!< GPIO72 (Bitfield-Mask: 0x01)                          */
14610 #define GPIO_INT2SET_GPIO71_Pos           (7UL)                     /*!< GPIO71 (Bit 7)                                        */
14611 #define GPIO_INT2SET_GPIO71_Msk           (0x80UL)                  /*!< GPIO71 (Bitfield-Mask: 0x01)                          */
14612 #define GPIO_INT2SET_GPIO70_Pos           (6UL)                     /*!< GPIO70 (Bit 6)                                        */
14613 #define GPIO_INT2SET_GPIO70_Msk           (0x40UL)                  /*!< GPIO70 (Bitfield-Mask: 0x01)                          */
14614 #define GPIO_INT2SET_GPIO69_Pos           (5UL)                     /*!< GPIO69 (Bit 5)                                        */
14615 #define GPIO_INT2SET_GPIO69_Msk           (0x20UL)                  /*!< GPIO69 (Bitfield-Mask: 0x01)                          */
14616 #define GPIO_INT2SET_GPIO68_Pos           (4UL)                     /*!< GPIO68 (Bit 4)                                        */
14617 #define GPIO_INT2SET_GPIO68_Msk           (0x10UL)                  /*!< GPIO68 (Bitfield-Mask: 0x01)                          */
14618 #define GPIO_INT2SET_GPIO67_Pos           (3UL)                     /*!< GPIO67 (Bit 3)                                        */
14619 #define GPIO_INT2SET_GPIO67_Msk           (0x8UL)                   /*!< GPIO67 (Bitfield-Mask: 0x01)                          */
14620 #define GPIO_INT2SET_GPIO66_Pos           (2UL)                     /*!< GPIO66 (Bit 2)                                        */
14621 #define GPIO_INT2SET_GPIO66_Msk           (0x4UL)                   /*!< GPIO66 (Bitfield-Mask: 0x01)                          */
14622 #define GPIO_INT2SET_GPIO65_Pos           (1UL)                     /*!< GPIO65 (Bit 1)                                        */
14623 #define GPIO_INT2SET_GPIO65_Msk           (0x2UL)                   /*!< GPIO65 (Bitfield-Mask: 0x01)                          */
14624 #define GPIO_INT2SET_GPIO64_Pos           (0UL)                     /*!< GPIO64 (Bit 0)                                        */
14625 #define GPIO_INT2SET_GPIO64_Msk           (0x1UL)                   /*!< GPIO64 (Bitfield-Mask: 0x01)                          */
14626 /* ========================================================  DBGCTRL  ======================================================== */
14627 #define GPIO_DBGCTRL_GCLK5_Pos            (5UL)                     /*!< GCLK5 (Bit 5)                                         */
14628 #define GPIO_DBGCTRL_GCLK5_Msk            (0x20UL)                  /*!< GCLK5 (Bitfield-Mask: 0x01)                           */
14629 #define GPIO_DBGCTRL_GCLK4_Pos            (4UL)                     /*!< GCLK4 (Bit 4)                                         */
14630 #define GPIO_DBGCTRL_GCLK4_Msk            (0x10UL)                  /*!< GCLK4 (Bitfield-Mask: 0x01)                           */
14631 #define GPIO_DBGCTRL_GCLK3_Pos            (3UL)                     /*!< GCLK3 (Bit 3)                                         */
14632 #define GPIO_DBGCTRL_GCLK3_Msk            (0x8UL)                   /*!< GCLK3 (Bitfield-Mask: 0x01)                           */
14633 #define GPIO_DBGCTRL_GCLK2_Pos            (2UL)                     /*!< GCLK2 (Bit 2)                                         */
14634 #define GPIO_DBGCTRL_GCLK2_Msk            (0x4UL)                   /*!< GCLK2 (Bitfield-Mask: 0x01)                           */
14635 #define GPIO_DBGCTRL_GCLK1_Pos            (1UL)                     /*!< GCLK1 (Bit 1)                                         */
14636 #define GPIO_DBGCTRL_GCLK1_Msk            (0x2UL)                   /*!< GCLK1 (Bitfield-Mask: 0x01)                           */
14637 #define GPIO_DBGCTRL_GCLK0_Pos            (0UL)                     /*!< GCLK0 (Bit 0)                                         */
14638 #define GPIO_DBGCTRL_GCLK0_Msk            (0x1UL)                   /*!< GCLK0 (Bitfield-Mask: 0x01)                           */
14639 
14640 
14641 /* =========================================================================================================================== */
14642 /* ================                                           IOM0                                            ================ */
14643 /* =========================================================================================================================== */
14644 
14645 /* =========================================================  FIFO  ========================================================== */
14646 #define IOM0_FIFO_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
14647 #define IOM0_FIFO_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
14648 /* ========================================================  FIFOPTR  ======================================================== */
14649 #define IOM0_FIFOPTR_FIFO1REM_Pos         (24UL)                    /*!< FIFO1REM (Bit 24)                                     */
14650 #define IOM0_FIFOPTR_FIFO1REM_Msk         (0xff000000UL)            /*!< FIFO1REM (Bitfield-Mask: 0xff)                        */
14651 #define IOM0_FIFOPTR_FIFO1SIZ_Pos         (16UL)                    /*!< FIFO1SIZ (Bit 16)                                     */
14652 #define IOM0_FIFOPTR_FIFO1SIZ_Msk         (0xff0000UL)              /*!< FIFO1SIZ (Bitfield-Mask: 0xff)                        */
14653 #define IOM0_FIFOPTR_FIFO0REM_Pos         (8UL)                     /*!< FIFO0REM (Bit 8)                                      */
14654 #define IOM0_FIFOPTR_FIFO0REM_Msk         (0xff00UL)                /*!< FIFO0REM (Bitfield-Mask: 0xff)                        */
14655 #define IOM0_FIFOPTR_FIFO0SIZ_Pos         (0UL)                     /*!< FIFO0SIZ (Bit 0)                                      */
14656 #define IOM0_FIFOPTR_FIFO0SIZ_Msk         (0xffUL)                  /*!< FIFO0SIZ (Bitfield-Mask: 0xff)                        */
14657 /* ========================================================  FIFOTHR  ======================================================== */
14658 #define IOM0_FIFOTHR_FIFOWTHR_Pos         (8UL)                     /*!< FIFOWTHR (Bit 8)                                      */
14659 #define IOM0_FIFOTHR_FIFOWTHR_Msk         (0x3f00UL)                /*!< FIFOWTHR (Bitfield-Mask: 0x3f)                        */
14660 #define IOM0_FIFOTHR_FIFORTHR_Pos         (0UL)                     /*!< FIFORTHR (Bit 0)                                      */
14661 #define IOM0_FIFOTHR_FIFORTHR_Msk         (0x3fUL)                  /*!< FIFORTHR (Bitfield-Mask: 0x3f)                        */
14662 /* ========================================================  FIFOPOP  ======================================================== */
14663 #define IOM0_FIFOPOP_FIFODOUT_Pos         (0UL)                     /*!< FIFODOUT (Bit 0)                                      */
14664 #define IOM0_FIFOPOP_FIFODOUT_Msk         (0xffffffffUL)            /*!< FIFODOUT (Bitfield-Mask: 0xffffffff)                  */
14665 /* =======================================================  FIFOPUSH  ======================================================== */
14666 #define IOM0_FIFOPUSH_FIFODIN_Pos         (0UL)                     /*!< FIFODIN (Bit 0)                                       */
14667 #define IOM0_FIFOPUSH_FIFODIN_Msk         (0xffffffffUL)            /*!< FIFODIN (Bitfield-Mask: 0xffffffff)                   */
14668 /* =======================================================  FIFOCTRL  ======================================================== */
14669 #define IOM0_FIFOCTRL_FIFORSTN_Pos        (1UL)                     /*!< FIFORSTN (Bit 1)                                      */
14670 #define IOM0_FIFOCTRL_FIFORSTN_Msk        (0x2UL)                   /*!< FIFORSTN (Bitfield-Mask: 0x01)                        */
14671 #define IOM0_FIFOCTRL_POPWR_Pos           (0UL)                     /*!< POPWR (Bit 0)                                         */
14672 #define IOM0_FIFOCTRL_POPWR_Msk           (0x1UL)                   /*!< POPWR (Bitfield-Mask: 0x01)                           */
14673 /* ========================================================  FIFOLOC  ======================================================== */
14674 #define IOM0_FIFOLOC_FIFORPTR_Pos         (8UL)                     /*!< FIFORPTR (Bit 8)                                      */
14675 #define IOM0_FIFOLOC_FIFORPTR_Msk         (0xf00UL)                 /*!< FIFORPTR (Bitfield-Mask: 0x0f)                        */
14676 #define IOM0_FIFOLOC_FIFOWPTR_Pos         (0UL)                     /*!< FIFOWPTR (Bit 0)                                      */
14677 #define IOM0_FIFOLOC_FIFOWPTR_Msk         (0xfUL)                   /*!< FIFOWPTR (Bitfield-Mask: 0x0f)                        */
14678 /* =========================================================  INTEN  ========================================================= */
14679 #define IOM0_INTEN_CQERR_Pos              (14UL)                    /*!< CQERR (Bit 14)                                        */
14680 #define IOM0_INTEN_CQERR_Msk              (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
14681 #define IOM0_INTEN_CQUPD_Pos              (13UL)                    /*!< CQUPD (Bit 13)                                        */
14682 #define IOM0_INTEN_CQUPD_Msk              (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
14683 #define IOM0_INTEN_CQPAUSED_Pos           (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
14684 #define IOM0_INTEN_CQPAUSED_Msk           (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
14685 #define IOM0_INTEN_DERR_Pos               (11UL)                    /*!< DERR (Bit 11)                                         */
14686 #define IOM0_INTEN_DERR_Msk               (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
14687 #define IOM0_INTEN_DCMP_Pos               (10UL)                    /*!< DCMP (Bit 10)                                         */
14688 #define IOM0_INTEN_DCMP_Msk               (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
14689 #define IOM0_INTEN_ARB_Pos                (9UL)                     /*!< ARB (Bit 9)                                           */
14690 #define IOM0_INTEN_ARB_Msk                (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
14691 #define IOM0_INTEN_STOP_Pos               (8UL)                     /*!< STOP (Bit 8)                                          */
14692 #define IOM0_INTEN_STOP_Msk               (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
14693 #define IOM0_INTEN_START_Pos              (7UL)                     /*!< START (Bit 7)                                         */
14694 #define IOM0_INTEN_START_Msk              (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
14695 #define IOM0_INTEN_ICMD_Pos               (6UL)                     /*!< ICMD (Bit 6)                                          */
14696 #define IOM0_INTEN_ICMD_Msk               (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
14697 #define IOM0_INTEN_IACC_Pos               (5UL)                     /*!< IACC (Bit 5)                                          */
14698 #define IOM0_INTEN_IACC_Msk               (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
14699 #define IOM0_INTEN_NAK_Pos                (4UL)                     /*!< NAK (Bit 4)                                           */
14700 #define IOM0_INTEN_NAK_Msk                (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
14701 #define IOM0_INTEN_FOVFL_Pos              (3UL)                     /*!< FOVFL (Bit 3)                                         */
14702 #define IOM0_INTEN_FOVFL_Msk              (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
14703 #define IOM0_INTEN_FUNDFL_Pos             (2UL)                     /*!< FUNDFL (Bit 2)                                        */
14704 #define IOM0_INTEN_FUNDFL_Msk             (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
14705 #define IOM0_INTEN_THR_Pos                (1UL)                     /*!< THR (Bit 1)                                           */
14706 #define IOM0_INTEN_THR_Msk                (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
14707 #define IOM0_INTEN_CMDCMP_Pos             (0UL)                     /*!< CMDCMP (Bit 0)                                        */
14708 #define IOM0_INTEN_CMDCMP_Msk             (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
14709 /* ========================================================  INTSTAT  ======================================================== */
14710 #define IOM0_INTSTAT_CQERR_Pos            (14UL)                    /*!< CQERR (Bit 14)                                        */
14711 #define IOM0_INTSTAT_CQERR_Msk            (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
14712 #define IOM0_INTSTAT_CQUPD_Pos            (13UL)                    /*!< CQUPD (Bit 13)                                        */
14713 #define IOM0_INTSTAT_CQUPD_Msk            (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
14714 #define IOM0_INTSTAT_CQPAUSED_Pos         (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
14715 #define IOM0_INTSTAT_CQPAUSED_Msk         (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
14716 #define IOM0_INTSTAT_DERR_Pos             (11UL)                    /*!< DERR (Bit 11)                                         */
14717 #define IOM0_INTSTAT_DERR_Msk             (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
14718 #define IOM0_INTSTAT_DCMP_Pos             (10UL)                    /*!< DCMP (Bit 10)                                         */
14719 #define IOM0_INTSTAT_DCMP_Msk             (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
14720 #define IOM0_INTSTAT_ARB_Pos              (9UL)                     /*!< ARB (Bit 9)                                           */
14721 #define IOM0_INTSTAT_ARB_Msk              (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
14722 #define IOM0_INTSTAT_STOP_Pos             (8UL)                     /*!< STOP (Bit 8)                                          */
14723 #define IOM0_INTSTAT_STOP_Msk             (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
14724 #define IOM0_INTSTAT_START_Pos            (7UL)                     /*!< START (Bit 7)                                         */
14725 #define IOM0_INTSTAT_START_Msk            (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
14726 #define IOM0_INTSTAT_ICMD_Pos             (6UL)                     /*!< ICMD (Bit 6)                                          */
14727 #define IOM0_INTSTAT_ICMD_Msk             (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
14728 #define IOM0_INTSTAT_IACC_Pos             (5UL)                     /*!< IACC (Bit 5)                                          */
14729 #define IOM0_INTSTAT_IACC_Msk             (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
14730 #define IOM0_INTSTAT_NAK_Pos              (4UL)                     /*!< NAK (Bit 4)                                           */
14731 #define IOM0_INTSTAT_NAK_Msk              (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
14732 #define IOM0_INTSTAT_FOVFL_Pos            (3UL)                     /*!< FOVFL (Bit 3)                                         */
14733 #define IOM0_INTSTAT_FOVFL_Msk            (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
14734 #define IOM0_INTSTAT_FUNDFL_Pos           (2UL)                     /*!< FUNDFL (Bit 2)                                        */
14735 #define IOM0_INTSTAT_FUNDFL_Msk           (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
14736 #define IOM0_INTSTAT_THR_Pos              (1UL)                     /*!< THR (Bit 1)                                           */
14737 #define IOM0_INTSTAT_THR_Msk              (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
14738 #define IOM0_INTSTAT_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
14739 #define IOM0_INTSTAT_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
14740 /* ========================================================  INTCLR  ========================================================= */
14741 #define IOM0_INTCLR_CQERR_Pos             (14UL)                    /*!< CQERR (Bit 14)                                        */
14742 #define IOM0_INTCLR_CQERR_Msk             (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
14743 #define IOM0_INTCLR_CQUPD_Pos             (13UL)                    /*!< CQUPD (Bit 13)                                        */
14744 #define IOM0_INTCLR_CQUPD_Msk             (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
14745 #define IOM0_INTCLR_CQPAUSED_Pos          (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
14746 #define IOM0_INTCLR_CQPAUSED_Msk          (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
14747 #define IOM0_INTCLR_DERR_Pos              (11UL)                    /*!< DERR (Bit 11)                                         */
14748 #define IOM0_INTCLR_DERR_Msk              (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
14749 #define IOM0_INTCLR_DCMP_Pos              (10UL)                    /*!< DCMP (Bit 10)                                         */
14750 #define IOM0_INTCLR_DCMP_Msk              (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
14751 #define IOM0_INTCLR_ARB_Pos               (9UL)                     /*!< ARB (Bit 9)                                           */
14752 #define IOM0_INTCLR_ARB_Msk               (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
14753 #define IOM0_INTCLR_STOP_Pos              (8UL)                     /*!< STOP (Bit 8)                                          */
14754 #define IOM0_INTCLR_STOP_Msk              (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
14755 #define IOM0_INTCLR_START_Pos             (7UL)                     /*!< START (Bit 7)                                         */
14756 #define IOM0_INTCLR_START_Msk             (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
14757 #define IOM0_INTCLR_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
14758 #define IOM0_INTCLR_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
14759 #define IOM0_INTCLR_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
14760 #define IOM0_INTCLR_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
14761 #define IOM0_INTCLR_NAK_Pos               (4UL)                     /*!< NAK (Bit 4)                                           */
14762 #define IOM0_INTCLR_NAK_Msk               (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
14763 #define IOM0_INTCLR_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
14764 #define IOM0_INTCLR_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
14765 #define IOM0_INTCLR_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
14766 #define IOM0_INTCLR_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
14767 #define IOM0_INTCLR_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
14768 #define IOM0_INTCLR_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
14769 #define IOM0_INTCLR_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
14770 #define IOM0_INTCLR_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
14771 /* ========================================================  INTSET  ========================================================= */
14772 #define IOM0_INTSET_CQERR_Pos             (14UL)                    /*!< CQERR (Bit 14)                                        */
14773 #define IOM0_INTSET_CQERR_Msk             (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
14774 #define IOM0_INTSET_CQUPD_Pos             (13UL)                    /*!< CQUPD (Bit 13)                                        */
14775 #define IOM0_INTSET_CQUPD_Msk             (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
14776 #define IOM0_INTSET_CQPAUSED_Pos          (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
14777 #define IOM0_INTSET_CQPAUSED_Msk          (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
14778 #define IOM0_INTSET_DERR_Pos              (11UL)                    /*!< DERR (Bit 11)                                         */
14779 #define IOM0_INTSET_DERR_Msk              (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
14780 #define IOM0_INTSET_DCMP_Pos              (10UL)                    /*!< DCMP (Bit 10)                                         */
14781 #define IOM0_INTSET_DCMP_Msk              (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
14782 #define IOM0_INTSET_ARB_Pos               (9UL)                     /*!< ARB (Bit 9)                                           */
14783 #define IOM0_INTSET_ARB_Msk               (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
14784 #define IOM0_INTSET_STOP_Pos              (8UL)                     /*!< STOP (Bit 8)                                          */
14785 #define IOM0_INTSET_STOP_Msk              (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
14786 #define IOM0_INTSET_START_Pos             (7UL)                     /*!< START (Bit 7)                                         */
14787 #define IOM0_INTSET_START_Msk             (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
14788 #define IOM0_INTSET_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
14789 #define IOM0_INTSET_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
14790 #define IOM0_INTSET_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
14791 #define IOM0_INTSET_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
14792 #define IOM0_INTSET_NAK_Pos               (4UL)                     /*!< NAK (Bit 4)                                           */
14793 #define IOM0_INTSET_NAK_Msk               (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
14794 #define IOM0_INTSET_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
14795 #define IOM0_INTSET_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
14796 #define IOM0_INTSET_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
14797 #define IOM0_INTSET_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
14798 #define IOM0_INTSET_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
14799 #define IOM0_INTSET_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
14800 #define IOM0_INTSET_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
14801 #define IOM0_INTSET_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
14802 /* ========================================================  CLKCFG  ========================================================= */
14803 #define IOM0_CLKCFG_TOTPER_Pos            (24UL)                    /*!< TOTPER (Bit 24)                                       */
14804 #define IOM0_CLKCFG_TOTPER_Msk            (0xff000000UL)            /*!< TOTPER (Bitfield-Mask: 0xff)                          */
14805 #define IOM0_CLKCFG_LOWPER_Pos            (16UL)                    /*!< LOWPER (Bit 16)                                       */
14806 #define IOM0_CLKCFG_LOWPER_Msk            (0xff0000UL)              /*!< LOWPER (Bitfield-Mask: 0xff)                          */
14807 #define IOM0_CLKCFG_DIVEN_Pos             (12UL)                    /*!< DIVEN (Bit 12)                                        */
14808 #define IOM0_CLKCFG_DIVEN_Msk             (0x1000UL)                /*!< DIVEN (Bitfield-Mask: 0x01)                           */
14809 #define IOM0_CLKCFG_DIV3_Pos              (11UL)                    /*!< DIV3 (Bit 11)                                         */
14810 #define IOM0_CLKCFG_DIV3_Msk              (0x800UL)                 /*!< DIV3 (Bitfield-Mask: 0x01)                            */
14811 #define IOM0_CLKCFG_FSEL_Pos              (8UL)                     /*!< FSEL (Bit 8)                                          */
14812 #define IOM0_CLKCFG_FSEL_Msk              (0x700UL)                 /*!< FSEL (Bitfield-Mask: 0x07)                            */
14813 #define IOM0_CLKCFG_IOCLKEN_Pos           (0UL)                     /*!< IOCLKEN (Bit 0)                                       */
14814 #define IOM0_CLKCFG_IOCLKEN_Msk           (0x1UL)                   /*!< IOCLKEN (Bitfield-Mask: 0x01)                         */
14815 /* ======================================================  SUBMODCTRL  ======================================================= */
14816 #define IOM0_SUBMODCTRL_SMOD1TYPE_Pos     (5UL)                     /*!< SMOD1TYPE (Bit 5)                                     */
14817 #define IOM0_SUBMODCTRL_SMOD1TYPE_Msk     (0xe0UL)                  /*!< SMOD1TYPE (Bitfield-Mask: 0x07)                       */
14818 #define IOM0_SUBMODCTRL_SMOD1EN_Pos       (4UL)                     /*!< SMOD1EN (Bit 4)                                       */
14819 #define IOM0_SUBMODCTRL_SMOD1EN_Msk       (0x10UL)                  /*!< SMOD1EN (Bitfield-Mask: 0x01)                         */
14820 #define IOM0_SUBMODCTRL_SMOD0TYPE_Pos     (1UL)                     /*!< SMOD0TYPE (Bit 1)                                     */
14821 #define IOM0_SUBMODCTRL_SMOD0TYPE_Msk     (0xeUL)                   /*!< SMOD0TYPE (Bitfield-Mask: 0x07)                       */
14822 #define IOM0_SUBMODCTRL_SMOD0EN_Pos       (0UL)                     /*!< SMOD0EN (Bit 0)                                       */
14823 #define IOM0_SUBMODCTRL_SMOD0EN_Msk       (0x1UL)                   /*!< SMOD0EN (Bitfield-Mask: 0x01)                         */
14824 /* ==========================================================  CMD  ========================================================== */
14825 #define IOM0_CMD_OFFSETLO_Pos             (24UL)                    /*!< OFFSETLO (Bit 24)                                     */
14826 #define IOM0_CMD_OFFSETLO_Msk             (0xff000000UL)            /*!< OFFSETLO (Bitfield-Mask: 0xff)                        */
14827 #define IOM0_CMD_CMDSEL_Pos               (20UL)                    /*!< CMDSEL (Bit 20)                                       */
14828 #define IOM0_CMD_CMDSEL_Msk               (0x300000UL)              /*!< CMDSEL (Bitfield-Mask: 0x03)                          */
14829 #define IOM0_CMD_TSIZE_Pos                (8UL)                     /*!< TSIZE (Bit 8)                                         */
14830 #define IOM0_CMD_TSIZE_Msk                (0xfff00UL)               /*!< TSIZE (Bitfield-Mask: 0xfff)                          */
14831 #define IOM0_CMD_CONT_Pos                 (7UL)                     /*!< CONT (Bit 7)                                          */
14832 #define IOM0_CMD_CONT_Msk                 (0x80UL)                  /*!< CONT (Bitfield-Mask: 0x01)                            */
14833 #define IOM0_CMD_OFFSETCNT_Pos            (5UL)                     /*!< OFFSETCNT (Bit 5)                                     */
14834 #define IOM0_CMD_OFFSETCNT_Msk            (0x60UL)                  /*!< OFFSETCNT (Bitfield-Mask: 0x03)                       */
14835 #define IOM0_CMD_CMD_Pos                  (0UL)                     /*!< CMD (Bit 0)                                           */
14836 #define IOM0_CMD_CMD_Msk                  (0x1fUL)                  /*!< CMD (Bitfield-Mask: 0x1f)                             */
14837 /* ==========================================================  DCX  ========================================================== */
14838 #define IOM0_DCX_DCXEN_Pos                (4UL)                     /*!< DCXEN (Bit 4)                                         */
14839 #define IOM0_DCX_DCXEN_Msk                (0x10UL)                  /*!< DCXEN (Bitfield-Mask: 0x01)                           */
14840 #define IOM0_DCX_CE3OUT_Pos               (3UL)                     /*!< CE3OUT (Bit 3)                                        */
14841 #define IOM0_DCX_CE3OUT_Msk               (0x8UL)                   /*!< CE3OUT (Bitfield-Mask: 0x01)                          */
14842 #define IOM0_DCX_CE2OUT_Pos               (2UL)                     /*!< CE2OUT (Bit 2)                                        */
14843 #define IOM0_DCX_CE2OUT_Msk               (0x4UL)                   /*!< CE2OUT (Bitfield-Mask: 0x01)                          */
14844 #define IOM0_DCX_CE1OUT_Pos               (1UL)                     /*!< CE1OUT (Bit 1)                                        */
14845 #define IOM0_DCX_CE1OUT_Msk               (0x2UL)                   /*!< CE1OUT (Bitfield-Mask: 0x01)                          */
14846 #define IOM0_DCX_CE0OUT_Pos               (0UL)                     /*!< CE0OUT (Bit 0)                                        */
14847 #define IOM0_DCX_CE0OUT_Msk               (0x1UL)                   /*!< CE0OUT (Bitfield-Mask: 0x01)                          */
14848 /* =======================================================  OFFSETHI  ======================================================== */
14849 #define IOM0_OFFSETHI_OFFSETHI_Pos        (0UL)                     /*!< OFFSETHI (Bit 0)                                      */
14850 #define IOM0_OFFSETHI_OFFSETHI_Msk        (0xffffUL)                /*!< OFFSETHI (Bitfield-Mask: 0xffff)                      */
14851 /* ========================================================  CMDSTAT  ======================================================== */
14852 #define IOM0_CMDSTAT_CTSIZE_Pos           (8UL)                     /*!< CTSIZE (Bit 8)                                        */
14853 #define IOM0_CMDSTAT_CTSIZE_Msk           (0xfff00UL)               /*!< CTSIZE (Bitfield-Mask: 0xfff)                         */
14854 #define IOM0_CMDSTAT_CMDSTAT_Pos          (5UL)                     /*!< CMDSTAT (Bit 5)                                       */
14855 #define IOM0_CMDSTAT_CMDSTAT_Msk          (0xe0UL)                  /*!< CMDSTAT (Bitfield-Mask: 0x07)                         */
14856 #define IOM0_CMDSTAT_CCMD_Pos             (0UL)                     /*!< CCMD (Bit 0)                                          */
14857 #define IOM0_CMDSTAT_CCMD_Msk             (0x1fUL)                  /*!< CCMD (Bitfield-Mask: 0x1f)                            */
14858 /* =======================================================  DMATRIGEN  ======================================================= */
14859 #define IOM0_DMATRIGEN_DTHREN_Pos         (1UL)                     /*!< DTHREN (Bit 1)                                        */
14860 #define IOM0_DMATRIGEN_DTHREN_Msk         (0x2UL)                   /*!< DTHREN (Bitfield-Mask: 0x01)                          */
14861 #define IOM0_DMATRIGEN_DCMDCMPEN_Pos      (0UL)                     /*!< DCMDCMPEN (Bit 0)                                     */
14862 #define IOM0_DMATRIGEN_DCMDCMPEN_Msk      (0x1UL)                   /*!< DCMDCMPEN (Bitfield-Mask: 0x01)                       */
14863 /* ======================================================  DMATRIGSTAT  ====================================================== */
14864 #define IOM0_DMATRIGSTAT_DTOTCMP_Pos      (2UL)                     /*!< DTOTCMP (Bit 2)                                       */
14865 #define IOM0_DMATRIGSTAT_DTOTCMP_Msk      (0x4UL)                   /*!< DTOTCMP (Bitfield-Mask: 0x01)                         */
14866 #define IOM0_DMATRIGSTAT_DTHR_Pos         (1UL)                     /*!< DTHR (Bit 1)                                          */
14867 #define IOM0_DMATRIGSTAT_DTHR_Msk         (0x2UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
14868 #define IOM0_DMATRIGSTAT_DCMDCMP_Pos      (0UL)                     /*!< DCMDCMP (Bit 0)                                       */
14869 #define IOM0_DMATRIGSTAT_DCMDCMP_Msk      (0x1UL)                   /*!< DCMDCMP (Bitfield-Mask: 0x01)                         */
14870 /* ========================================================  DMACFG  ========================================================= */
14871 #define IOM0_DMACFG_DPWROFF_Pos           (9UL)                     /*!< DPWROFF (Bit 9)                                       */
14872 #define IOM0_DMACFG_DPWROFF_Msk           (0x200UL)                 /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
14873 #define IOM0_DMACFG_DMAPRI_Pos            (8UL)                     /*!< DMAPRI (Bit 8)                                        */
14874 #define IOM0_DMACFG_DMAPRI_Msk            (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
14875 #define IOM0_DMACFG_DMADIR_Pos            (1UL)                     /*!< DMADIR (Bit 1)                                        */
14876 #define IOM0_DMACFG_DMADIR_Msk            (0x2UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
14877 #define IOM0_DMACFG_DMAEN_Pos             (0UL)                     /*!< DMAEN (Bit 0)                                         */
14878 #define IOM0_DMACFG_DMAEN_Msk             (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
14879 /* ======================================================  DMATOTCOUNT  ====================================================== */
14880 #define IOM0_DMATOTCOUNT_TOTCOUNT_Pos     (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
14881 #define IOM0_DMATOTCOUNT_TOTCOUNT_Msk     (0xfffUL)                 /*!< TOTCOUNT (Bitfield-Mask: 0xfff)                       */
14882 /* ======================================================  DMATARGADDR  ====================================================== */
14883 #define IOM0_DMATARGADDR_TARGADDR28_Pos   (28UL)                    /*!< TARGADDR28 (Bit 28)                                   */
14884 #define IOM0_DMATARGADDR_TARGADDR28_Msk   (0x10000000UL)            /*!< TARGADDR28 (Bitfield-Mask: 0x01)                      */
14885 #define IOM0_DMATARGADDR_TARGADDR_Pos     (0UL)                     /*!< TARGADDR (Bit 0)                                      */
14886 #define IOM0_DMATARGADDR_TARGADDR_Msk     (0x1fffffUL)              /*!< TARGADDR (Bitfield-Mask: 0x1fffff)                    */
14887 /* ========================================================  DMASTAT  ======================================================== */
14888 #define IOM0_DMASTAT_DMAERR_Pos           (2UL)                     /*!< DMAERR (Bit 2)                                        */
14889 #define IOM0_DMASTAT_DMAERR_Msk           (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
14890 #define IOM0_DMASTAT_DMACPL_Pos           (1UL)                     /*!< DMACPL (Bit 1)                                        */
14891 #define IOM0_DMASTAT_DMACPL_Msk           (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
14892 #define IOM0_DMASTAT_DMATIP_Pos           (0UL)                     /*!< DMATIP (Bit 0)                                        */
14893 #define IOM0_DMASTAT_DMATIP_Msk           (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
14894 /* =========================================================  CQCFG  ========================================================= */
14895 #define IOM0_CQCFG_MSPIFLGSEL_Pos         (2UL)                     /*!< MSPIFLGSEL (Bit 2)                                    */
14896 #define IOM0_CQCFG_MSPIFLGSEL_Msk         (0xcUL)                   /*!< MSPIFLGSEL (Bitfield-Mask: 0x03)                      */
14897 #define IOM0_CQCFG_CQPRI_Pos              (1UL)                     /*!< CQPRI (Bit 1)                                         */
14898 #define IOM0_CQCFG_CQPRI_Msk              (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
14899 #define IOM0_CQCFG_CQEN_Pos               (0UL)                     /*!< CQEN (Bit 0)                                          */
14900 #define IOM0_CQCFG_CQEN_Msk               (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
14901 /* ========================================================  CQADDR  ========================================================= */
14902 #define IOM0_CQADDR_CQADDR28_Pos          (28UL)                    /*!< CQADDR28 (Bit 28)                                     */
14903 #define IOM0_CQADDR_CQADDR28_Msk          (0x10000000UL)            /*!< CQADDR28 (Bitfield-Mask: 0x01)                        */
14904 #define IOM0_CQADDR_CQADDR_Pos            (2UL)                     /*!< CQADDR (Bit 2)                                        */
14905 #define IOM0_CQADDR_CQADDR_Msk            (0x1ffffcUL)              /*!< CQADDR (Bitfield-Mask: 0x7ffff)                       */
14906 /* ========================================================  CQSTAT  ========================================================= */
14907 #define IOM0_CQSTAT_CQERR_Pos             (2UL)                     /*!< CQERR (Bit 2)                                         */
14908 #define IOM0_CQSTAT_CQERR_Msk             (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
14909 #define IOM0_CQSTAT_CQPAUSED_Pos          (1UL)                     /*!< CQPAUSED (Bit 1)                                      */
14910 #define IOM0_CQSTAT_CQPAUSED_Msk          (0x2UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
14911 #define IOM0_CQSTAT_CQTIP_Pos             (0UL)                     /*!< CQTIP (Bit 0)                                         */
14912 #define IOM0_CQSTAT_CQTIP_Msk             (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
14913 /* ========================================================  CQFLAGS  ======================================================== */
14914 #define IOM0_CQFLAGS_CQIRQMASK_Pos        (16UL)                    /*!< CQIRQMASK (Bit 16)                                    */
14915 #define IOM0_CQFLAGS_CQIRQMASK_Msk        (0xffff0000UL)            /*!< CQIRQMASK (Bitfield-Mask: 0xffff)                     */
14916 #define IOM0_CQFLAGS_CQFLAGS_Pos          (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
14917 #define IOM0_CQFLAGS_CQFLAGS_Msk          (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
14918 /* ======================================================  CQSETCLEAR  ======================================================= */
14919 #define IOM0_CQSETCLEAR_CQFCLR_Pos        (16UL)                    /*!< CQFCLR (Bit 16)                                       */
14920 #define IOM0_CQSETCLEAR_CQFCLR_Msk        (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
14921 #define IOM0_CQSETCLEAR_CQFTGL_Pos        (8UL)                     /*!< CQFTGL (Bit 8)                                        */
14922 #define IOM0_CQSETCLEAR_CQFTGL_Msk        (0xff00UL)                /*!< CQFTGL (Bitfield-Mask: 0xff)                          */
14923 #define IOM0_CQSETCLEAR_CQFSET_Pos        (0UL)                     /*!< CQFSET (Bit 0)                                        */
14924 #define IOM0_CQSETCLEAR_CQFSET_Msk        (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
14925 /* =======================================================  CQPAUSEEN  ======================================================= */
14926 #define IOM0_CQPAUSEEN_CQPEN_Pos          (0UL)                     /*!< CQPEN (Bit 0)                                         */
14927 #define IOM0_CQPAUSEEN_CQPEN_Msk          (0xffffUL)                /*!< CQPEN (Bitfield-Mask: 0xffff)                         */
14928 /* =======================================================  CQCURIDX  ======================================================== */
14929 #define IOM0_CQCURIDX_CQCURIDX_Pos        (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
14930 #define IOM0_CQCURIDX_CQCURIDX_Msk        (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
14931 /* =======================================================  CQENDIDX  ======================================================== */
14932 #define IOM0_CQENDIDX_CQENDIDX_Pos        (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
14933 #define IOM0_CQENDIDX_CQENDIDX_Msk        (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
14934 /* ========================================================  STATUS  ========================================================= */
14935 #define IOM0_STATUS_IDLEST_Pos            (2UL)                     /*!< IDLEST (Bit 2)                                        */
14936 #define IOM0_STATUS_IDLEST_Msk            (0x4UL)                   /*!< IDLEST (Bitfield-Mask: 0x01)                          */
14937 #define IOM0_STATUS_CMDACT_Pos            (1UL)                     /*!< CMDACT (Bit 1)                                        */
14938 #define IOM0_STATUS_CMDACT_Msk            (0x2UL)                   /*!< CMDACT (Bitfield-Mask: 0x01)                          */
14939 #define IOM0_STATUS_ERR_Pos               (0UL)                     /*!< ERR (Bit 0)                                           */
14940 #define IOM0_STATUS_ERR_Msk               (0x1UL)                   /*!< ERR (Bitfield-Mask: 0x01)                             */
14941 /* ========================================================  MSPICFG  ======================================================== */
14942 #define IOM0_MSPICFG_MSPIRST_Pos          (30UL)                    /*!< MSPIRST (Bit 30)                                      */
14943 #define IOM0_MSPICFG_MSPIRST_Msk          (0x40000000UL)            /*!< MSPIRST (Bitfield-Mask: 0x01)                         */
14944 #define IOM0_MSPICFG_DOUTDLY_Pos          (27UL)                    /*!< DOUTDLY (Bit 27)                                      */
14945 #define IOM0_MSPICFG_DOUTDLY_Msk          (0x38000000UL)            /*!< DOUTDLY (Bitfield-Mask: 0x07)                         */
14946 #define IOM0_MSPICFG_DINDLY_Pos           (24UL)                    /*!< DINDLY (Bit 24)                                       */
14947 #define IOM0_MSPICFG_DINDLY_Msk           (0x7000000UL)             /*!< DINDLY (Bitfield-Mask: 0x07)                          */
14948 #define IOM0_MSPICFG_SPILSB_Pos           (23UL)                    /*!< SPILSB (Bit 23)                                       */
14949 #define IOM0_MSPICFG_SPILSB_Msk           (0x800000UL)              /*!< SPILSB (Bitfield-Mask: 0x01)                          */
14950 #define IOM0_MSPICFG_RDFCPOL_Pos          (22UL)                    /*!< RDFCPOL (Bit 22)                                      */
14951 #define IOM0_MSPICFG_RDFCPOL_Msk          (0x400000UL)              /*!< RDFCPOL (Bitfield-Mask: 0x01)                         */
14952 #define IOM0_MSPICFG_WTFCPOL_Pos          (21UL)                    /*!< WTFCPOL (Bit 21)                                      */
14953 #define IOM0_MSPICFG_WTFCPOL_Msk          (0x200000UL)              /*!< WTFCPOL (Bitfield-Mask: 0x01)                         */
14954 #define IOM0_MSPICFG_WTFCIRQ_Pos          (20UL)                    /*!< WTFCIRQ (Bit 20)                                      */
14955 #define IOM0_MSPICFG_WTFCIRQ_Msk          (0x100000UL)              /*!< WTFCIRQ (Bitfield-Mask: 0x01)                         */
14956 #define IOM0_MSPICFG_MOSIINV_Pos          (18UL)                    /*!< MOSIINV (Bit 18)                                      */
14957 #define IOM0_MSPICFG_MOSIINV_Msk          (0x40000UL)               /*!< MOSIINV (Bitfield-Mask: 0x01)                         */
14958 #define IOM0_MSPICFG_RDFC_Pos             (17UL)                    /*!< RDFC (Bit 17)                                         */
14959 #define IOM0_MSPICFG_RDFC_Msk             (0x20000UL)               /*!< RDFC (Bitfield-Mask: 0x01)                            */
14960 #define IOM0_MSPICFG_WTFC_Pos             (16UL)                    /*!< WTFC (Bit 16)                                         */
14961 #define IOM0_MSPICFG_WTFC_Msk             (0x10000UL)               /*!< WTFC (Bitfield-Mask: 0x01)                            */
14962 #define IOM0_MSPICFG_FULLDUP_Pos          (2UL)                     /*!< FULLDUP (Bit 2)                                       */
14963 #define IOM0_MSPICFG_FULLDUP_Msk          (0x4UL)                   /*!< FULLDUP (Bitfield-Mask: 0x01)                         */
14964 #define IOM0_MSPICFG_SPHA_Pos             (1UL)                     /*!< SPHA (Bit 1)                                          */
14965 #define IOM0_MSPICFG_SPHA_Msk             (0x2UL)                   /*!< SPHA (Bitfield-Mask: 0x01)                            */
14966 #define IOM0_MSPICFG_SPOL_Pos             (0UL)                     /*!< SPOL (Bit 0)                                          */
14967 #define IOM0_MSPICFG_SPOL_Msk             (0x1UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
14968 /* ========================================================  MI2CCFG  ======================================================== */
14969 #define IOM0_MI2CCFG_STRDIS_Pos           (24UL)                    /*!< STRDIS (Bit 24)                                       */
14970 #define IOM0_MI2CCFG_STRDIS_Msk           (0x1000000UL)             /*!< STRDIS (Bitfield-Mask: 0x01)                          */
14971 #define IOM0_MI2CCFG_SMPCNT_Pos           (16UL)                    /*!< SMPCNT (Bit 16)                                       */
14972 #define IOM0_MI2CCFG_SMPCNT_Msk           (0xff0000UL)              /*!< SMPCNT (Bitfield-Mask: 0xff)                          */
14973 #define IOM0_MI2CCFG_SDAENDLY_Pos         (12UL)                    /*!< SDAENDLY (Bit 12)                                     */
14974 #define IOM0_MI2CCFG_SDAENDLY_Msk         (0xf000UL)                /*!< SDAENDLY (Bitfield-Mask: 0x0f)                        */
14975 #define IOM0_MI2CCFG_SCLENDLY_Pos         (8UL)                     /*!< SCLENDLY (Bit 8)                                      */
14976 #define IOM0_MI2CCFG_SCLENDLY_Msk         (0xf00UL)                 /*!< SCLENDLY (Bitfield-Mask: 0x0f)                        */
14977 #define IOM0_MI2CCFG_MI2CRST_Pos          (6UL)                     /*!< MI2CRST (Bit 6)                                       */
14978 #define IOM0_MI2CCFG_MI2CRST_Msk          (0x40UL)                  /*!< MI2CRST (Bitfield-Mask: 0x01)                         */
14979 #define IOM0_MI2CCFG_SDADLY_Pos           (4UL)                     /*!< SDADLY (Bit 4)                                        */
14980 #define IOM0_MI2CCFG_SDADLY_Msk           (0x30UL)                  /*!< SDADLY (Bitfield-Mask: 0x03)                          */
14981 #define IOM0_MI2CCFG_ARBEN_Pos            (2UL)                     /*!< ARBEN (Bit 2)                                         */
14982 #define IOM0_MI2CCFG_ARBEN_Msk            (0x4UL)                   /*!< ARBEN (Bitfield-Mask: 0x01)                           */
14983 #define IOM0_MI2CCFG_I2CLSB_Pos           (1UL)                     /*!< I2CLSB (Bit 1)                                        */
14984 #define IOM0_MI2CCFG_I2CLSB_Msk           (0x2UL)                   /*!< I2CLSB (Bitfield-Mask: 0x01)                          */
14985 #define IOM0_MI2CCFG_ADDRSZ_Pos           (0UL)                     /*!< ADDRSZ (Bit 0)                                        */
14986 #define IOM0_MI2CCFG_ADDRSZ_Msk           (0x1UL)                   /*!< ADDRSZ (Bitfield-Mask: 0x01)                          */
14987 /* ========================================================  DEVCFG  ========================================================= */
14988 #define IOM0_DEVCFG_DEVADDR_Pos           (0UL)                     /*!< DEVADDR (Bit 0)                                       */
14989 #define IOM0_DEVCFG_DEVADDR_Msk           (0x3ffUL)                 /*!< DEVADDR (Bitfield-Mask: 0x3ff)                        */
14990 /* ========================================================  IOMDBG  ========================================================= */
14991 #define IOM0_IOMDBG_DBGDATA_Pos           (3UL)                     /*!< DBGDATA (Bit 3)                                       */
14992 #define IOM0_IOMDBG_DBGDATA_Msk           (0xfffffff8UL)            /*!< DBGDATA (Bitfield-Mask: 0x1fffffff)                   */
14993 #define IOM0_IOMDBG_APBCLKON_Pos          (2UL)                     /*!< APBCLKON (Bit 2)                                      */
14994 #define IOM0_IOMDBG_APBCLKON_Msk          (0x4UL)                   /*!< APBCLKON (Bitfield-Mask: 0x01)                        */
14995 #define IOM0_IOMDBG_IOCLKON_Pos           (1UL)                     /*!< IOCLKON (Bit 1)                                       */
14996 #define IOM0_IOMDBG_IOCLKON_Msk           (0x2UL)                   /*!< IOCLKON (Bitfield-Mask: 0x01)                         */
14997 #define IOM0_IOMDBG_DBGEN_Pos             (0UL)                     /*!< DBGEN (Bit 0)                                         */
14998 #define IOM0_IOMDBG_DBGEN_Msk             (0x1UL)                   /*!< DBGEN (Bitfield-Mask: 0x01)                           */
14999 
15000 
15001 /* =========================================================================================================================== */
15002 /* ================                                          IOSLAVE                                          ================ */
15003 /* =========================================================================================================================== */
15004 
15005 /* ========================================================  FIFOPTR  ======================================================== */
15006 #define IOSLAVE_FIFOPTR_FIFOSIZ_Pos       (8UL)                     /*!< FIFOSIZ (Bit 8)                                       */
15007 #define IOSLAVE_FIFOPTR_FIFOSIZ_Msk       (0xff00UL)                /*!< FIFOSIZ (Bitfield-Mask: 0xff)                         */
15008 #define IOSLAVE_FIFOPTR_FIFOPTR_Pos       (0UL)                     /*!< FIFOPTR (Bit 0)                                       */
15009 #define IOSLAVE_FIFOPTR_FIFOPTR_Msk       (0xffUL)                  /*!< FIFOPTR (Bitfield-Mask: 0xff)                         */
15010 /* ========================================================  FIFOCFG  ======================================================== */
15011 #define IOSLAVE_FIFOCFG_ROBASE_Pos        (24UL)                    /*!< ROBASE (Bit 24)                                       */
15012 #define IOSLAVE_FIFOCFG_ROBASE_Msk        (0x3f000000UL)            /*!< ROBASE (Bitfield-Mask: 0x3f)                          */
15013 #define IOSLAVE_FIFOCFG_FIFOMAX_Pos       (8UL)                     /*!< FIFOMAX (Bit 8)                                       */
15014 #define IOSLAVE_FIFOCFG_FIFOMAX_Msk       (0x3f00UL)                /*!< FIFOMAX (Bitfield-Mask: 0x3f)                         */
15015 #define IOSLAVE_FIFOCFG_FIFOBASE_Pos      (0UL)                     /*!< FIFOBASE (Bit 0)                                      */
15016 #define IOSLAVE_FIFOCFG_FIFOBASE_Msk      (0x1fUL)                  /*!< FIFOBASE (Bitfield-Mask: 0x1f)                        */
15017 /* ========================================================  FIFOTHR  ======================================================== */
15018 #define IOSLAVE_FIFOTHR_FIFOTHR_Pos       (0UL)                     /*!< FIFOTHR (Bit 0)                                       */
15019 #define IOSLAVE_FIFOTHR_FIFOTHR_Msk       (0xffUL)                  /*!< FIFOTHR (Bitfield-Mask: 0xff)                         */
15020 /* =========================================================  FUPD  ========================================================== */
15021 #define IOSLAVE_FUPD_IOREAD_Pos           (1UL)                     /*!< IOREAD (Bit 1)                                        */
15022 #define IOSLAVE_FUPD_IOREAD_Msk           (0x2UL)                   /*!< IOREAD (Bitfield-Mask: 0x01)                          */
15023 #define IOSLAVE_FUPD_FIFOUPD_Pos          (0UL)                     /*!< FIFOUPD (Bit 0)                                       */
15024 #define IOSLAVE_FUPD_FIFOUPD_Msk          (0x1UL)                   /*!< FIFOUPD (Bitfield-Mask: 0x01)                         */
15025 /* ========================================================  FIFOCTR  ======================================================== */
15026 #define IOSLAVE_FIFOCTR_FIFOCTR_Pos       (0UL)                     /*!< FIFOCTR (Bit 0)                                       */
15027 #define IOSLAVE_FIFOCTR_FIFOCTR_Msk       (0x3ffUL)                 /*!< FIFOCTR (Bitfield-Mask: 0x3ff)                        */
15028 /* ========================================================  FIFOINC  ======================================================== */
15029 #define IOSLAVE_FIFOINC_FIFOINC_Pos       (0UL)                     /*!< FIFOINC (Bit 0)                                       */
15030 #define IOSLAVE_FIFOINC_FIFOINC_Msk       (0x3ffUL)                 /*!< FIFOINC (Bitfield-Mask: 0x3ff)                        */
15031 /* ==========================================================  CFG  ========================================================== */
15032 #define IOSLAVE_CFG_IFCEN_Pos             (31UL)                    /*!< IFCEN (Bit 31)                                        */
15033 #define IOSLAVE_CFG_IFCEN_Msk             (0x80000000UL)            /*!< IFCEN (Bitfield-Mask: 0x01)                           */
15034 #define IOSLAVE_CFG_I2CADDR_Pos           (8UL)                     /*!< I2CADDR (Bit 8)                                       */
15035 #define IOSLAVE_CFG_I2CADDR_Msk           (0xfff00UL)               /*!< I2CADDR (Bitfield-Mask: 0xfff)                        */
15036 #define IOSLAVE_CFG_STARTRD_Pos           (4UL)                     /*!< STARTRD (Bit 4)                                       */
15037 #define IOSLAVE_CFG_STARTRD_Msk           (0x10UL)                  /*!< STARTRD (Bitfield-Mask: 0x01)                         */
15038 #define IOSLAVE_CFG_LSB_Pos               (2UL)                     /*!< LSB (Bit 2)                                           */
15039 #define IOSLAVE_CFG_LSB_Msk               (0x4UL)                   /*!< LSB (Bitfield-Mask: 0x01)                             */
15040 #define IOSLAVE_CFG_SPOL_Pos              (1UL)                     /*!< SPOL (Bit 1)                                          */
15041 #define IOSLAVE_CFG_SPOL_Msk              (0x2UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
15042 #define IOSLAVE_CFG_IFCSEL_Pos            (0UL)                     /*!< IFCSEL (Bit 0)                                        */
15043 #define IOSLAVE_CFG_IFCSEL_Msk            (0x1UL)                   /*!< IFCSEL (Bitfield-Mask: 0x01)                          */
15044 /* =========================================================  PRENC  ========================================================= */
15045 #define IOSLAVE_PRENC_PRENC_Pos           (0UL)                     /*!< PRENC (Bit 0)                                         */
15046 #define IOSLAVE_PRENC_PRENC_Msk           (0x1fUL)                  /*!< PRENC (Bitfield-Mask: 0x1f)                           */
15047 /* =======================================================  IOINTCTL  ======================================================== */
15048 #define IOSLAVE_IOINTCTL_IOINTSET_Pos     (24UL)                    /*!< IOINTSET (Bit 24)                                     */
15049 #define IOSLAVE_IOINTCTL_IOINTSET_Msk     (0xff000000UL)            /*!< IOINTSET (Bitfield-Mask: 0xff)                        */
15050 #define IOSLAVE_IOINTCTL_IOINTCLR_Pos     (16UL)                    /*!< IOINTCLR (Bit 16)                                     */
15051 #define IOSLAVE_IOINTCTL_IOINTCLR_Msk     (0x10000UL)               /*!< IOINTCLR (Bitfield-Mask: 0x01)                        */
15052 #define IOSLAVE_IOINTCTL_IOINT_Pos        (8UL)                     /*!< IOINT (Bit 8)                                         */
15053 #define IOSLAVE_IOINTCTL_IOINT_Msk        (0xff00UL)                /*!< IOINT (Bitfield-Mask: 0xff)                           */
15054 #define IOSLAVE_IOINTCTL_IOINTEN_Pos      (0UL)                     /*!< IOINTEN (Bit 0)                                       */
15055 #define IOSLAVE_IOINTCTL_IOINTEN_Msk      (0xffUL)                  /*!< IOINTEN (Bitfield-Mask: 0xff)                         */
15056 /* ========================================================  GENADD  ========================================================= */
15057 #define IOSLAVE_GENADD_GADATA_Pos         (0UL)                     /*!< GADATA (Bit 0)                                        */
15058 #define IOSLAVE_GENADD_GADATA_Msk         (0xffUL)                  /*!< GADATA (Bitfield-Mask: 0xff)                          */
15059 /* =========================================================  INTEN  ========================================================= */
15060 #define IOSLAVE_INTEN_XCMPWR_Pos          (9UL)                     /*!< XCMPWR (Bit 9)                                        */
15061 #define IOSLAVE_INTEN_XCMPWR_Msk          (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
15062 #define IOSLAVE_INTEN_XCMPWF_Pos          (8UL)                     /*!< XCMPWF (Bit 8)                                        */
15063 #define IOSLAVE_INTEN_XCMPWF_Msk          (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
15064 #define IOSLAVE_INTEN_XCMPRR_Pos          (7UL)                     /*!< XCMPRR (Bit 7)                                        */
15065 #define IOSLAVE_INTEN_XCMPRR_Msk          (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
15066 #define IOSLAVE_INTEN_XCMPRF_Pos          (6UL)                     /*!< XCMPRF (Bit 6)                                        */
15067 #define IOSLAVE_INTEN_XCMPRF_Msk          (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
15068 #define IOSLAVE_INTEN_IOINTW_Pos          (5UL)                     /*!< IOINTW (Bit 5)                                        */
15069 #define IOSLAVE_INTEN_IOINTW_Msk          (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
15070 #define IOSLAVE_INTEN_GENAD_Pos           (4UL)                     /*!< GENAD (Bit 4)                                         */
15071 #define IOSLAVE_INTEN_GENAD_Msk           (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
15072 #define IOSLAVE_INTEN_FRDERR_Pos          (3UL)                     /*!< FRDERR (Bit 3)                                        */
15073 #define IOSLAVE_INTEN_FRDERR_Msk          (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
15074 #define IOSLAVE_INTEN_FUNDFL_Pos          (2UL)                     /*!< FUNDFL (Bit 2)                                        */
15075 #define IOSLAVE_INTEN_FUNDFL_Msk          (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
15076 #define IOSLAVE_INTEN_FOVFL_Pos           (1UL)                     /*!< FOVFL (Bit 1)                                         */
15077 #define IOSLAVE_INTEN_FOVFL_Msk           (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
15078 #define IOSLAVE_INTEN_FSIZE_Pos           (0UL)                     /*!< FSIZE (Bit 0)                                         */
15079 #define IOSLAVE_INTEN_FSIZE_Msk           (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
15080 /* ========================================================  INTSTAT  ======================================================== */
15081 #define IOSLAVE_INTSTAT_XCMPWR_Pos        (9UL)                     /*!< XCMPWR (Bit 9)                                        */
15082 #define IOSLAVE_INTSTAT_XCMPWR_Msk        (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
15083 #define IOSLAVE_INTSTAT_XCMPWF_Pos        (8UL)                     /*!< XCMPWF (Bit 8)                                        */
15084 #define IOSLAVE_INTSTAT_XCMPWF_Msk        (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
15085 #define IOSLAVE_INTSTAT_XCMPRR_Pos        (7UL)                     /*!< XCMPRR (Bit 7)                                        */
15086 #define IOSLAVE_INTSTAT_XCMPRR_Msk        (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
15087 #define IOSLAVE_INTSTAT_XCMPRF_Pos        (6UL)                     /*!< XCMPRF (Bit 6)                                        */
15088 #define IOSLAVE_INTSTAT_XCMPRF_Msk        (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
15089 #define IOSLAVE_INTSTAT_IOINTW_Pos        (5UL)                     /*!< IOINTW (Bit 5)                                        */
15090 #define IOSLAVE_INTSTAT_IOINTW_Msk        (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
15091 #define IOSLAVE_INTSTAT_GENAD_Pos         (4UL)                     /*!< GENAD (Bit 4)                                         */
15092 #define IOSLAVE_INTSTAT_GENAD_Msk         (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
15093 #define IOSLAVE_INTSTAT_FRDERR_Pos        (3UL)                     /*!< FRDERR (Bit 3)                                        */
15094 #define IOSLAVE_INTSTAT_FRDERR_Msk        (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
15095 #define IOSLAVE_INTSTAT_FUNDFL_Pos        (2UL)                     /*!< FUNDFL (Bit 2)                                        */
15096 #define IOSLAVE_INTSTAT_FUNDFL_Msk        (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
15097 #define IOSLAVE_INTSTAT_FOVFL_Pos         (1UL)                     /*!< FOVFL (Bit 1)                                         */
15098 #define IOSLAVE_INTSTAT_FOVFL_Msk         (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
15099 #define IOSLAVE_INTSTAT_FSIZE_Pos         (0UL)                     /*!< FSIZE (Bit 0)                                         */
15100 #define IOSLAVE_INTSTAT_FSIZE_Msk         (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
15101 /* ========================================================  INTCLR  ========================================================= */
15102 #define IOSLAVE_INTCLR_XCMPWR_Pos         (9UL)                     /*!< XCMPWR (Bit 9)                                        */
15103 #define IOSLAVE_INTCLR_XCMPWR_Msk         (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
15104 #define IOSLAVE_INTCLR_XCMPWF_Pos         (8UL)                     /*!< XCMPWF (Bit 8)                                        */
15105 #define IOSLAVE_INTCLR_XCMPWF_Msk         (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
15106 #define IOSLAVE_INTCLR_XCMPRR_Pos         (7UL)                     /*!< XCMPRR (Bit 7)                                        */
15107 #define IOSLAVE_INTCLR_XCMPRR_Msk         (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
15108 #define IOSLAVE_INTCLR_XCMPRF_Pos         (6UL)                     /*!< XCMPRF (Bit 6)                                        */
15109 #define IOSLAVE_INTCLR_XCMPRF_Msk         (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
15110 #define IOSLAVE_INTCLR_IOINTW_Pos         (5UL)                     /*!< IOINTW (Bit 5)                                        */
15111 #define IOSLAVE_INTCLR_IOINTW_Msk         (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
15112 #define IOSLAVE_INTCLR_GENAD_Pos          (4UL)                     /*!< GENAD (Bit 4)                                         */
15113 #define IOSLAVE_INTCLR_GENAD_Msk          (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
15114 #define IOSLAVE_INTCLR_FRDERR_Pos         (3UL)                     /*!< FRDERR (Bit 3)                                        */
15115 #define IOSLAVE_INTCLR_FRDERR_Msk         (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
15116 #define IOSLAVE_INTCLR_FUNDFL_Pos         (2UL)                     /*!< FUNDFL (Bit 2)                                        */
15117 #define IOSLAVE_INTCLR_FUNDFL_Msk         (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
15118 #define IOSLAVE_INTCLR_FOVFL_Pos          (1UL)                     /*!< FOVFL (Bit 1)                                         */
15119 #define IOSLAVE_INTCLR_FOVFL_Msk          (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
15120 #define IOSLAVE_INTCLR_FSIZE_Pos          (0UL)                     /*!< FSIZE (Bit 0)                                         */
15121 #define IOSLAVE_INTCLR_FSIZE_Msk          (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
15122 /* ========================================================  INTSET  ========================================================= */
15123 #define IOSLAVE_INTSET_XCMPWR_Pos         (9UL)                     /*!< XCMPWR (Bit 9)                                        */
15124 #define IOSLAVE_INTSET_XCMPWR_Msk         (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
15125 #define IOSLAVE_INTSET_XCMPWF_Pos         (8UL)                     /*!< XCMPWF (Bit 8)                                        */
15126 #define IOSLAVE_INTSET_XCMPWF_Msk         (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
15127 #define IOSLAVE_INTSET_XCMPRR_Pos         (7UL)                     /*!< XCMPRR (Bit 7)                                        */
15128 #define IOSLAVE_INTSET_XCMPRR_Msk         (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
15129 #define IOSLAVE_INTSET_XCMPRF_Pos         (6UL)                     /*!< XCMPRF (Bit 6)                                        */
15130 #define IOSLAVE_INTSET_XCMPRF_Msk         (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
15131 #define IOSLAVE_INTSET_IOINTW_Pos         (5UL)                     /*!< IOINTW (Bit 5)                                        */
15132 #define IOSLAVE_INTSET_IOINTW_Msk         (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
15133 #define IOSLAVE_INTSET_GENAD_Pos          (4UL)                     /*!< GENAD (Bit 4)                                         */
15134 #define IOSLAVE_INTSET_GENAD_Msk          (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
15135 #define IOSLAVE_INTSET_FRDERR_Pos         (3UL)                     /*!< FRDERR (Bit 3)                                        */
15136 #define IOSLAVE_INTSET_FRDERR_Msk         (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
15137 #define IOSLAVE_INTSET_FUNDFL_Pos         (2UL)                     /*!< FUNDFL (Bit 2)                                        */
15138 #define IOSLAVE_INTSET_FUNDFL_Msk         (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
15139 #define IOSLAVE_INTSET_FOVFL_Pos          (1UL)                     /*!< FOVFL (Bit 1)                                         */
15140 #define IOSLAVE_INTSET_FOVFL_Msk          (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
15141 #define IOSLAVE_INTSET_FSIZE_Pos          (0UL)                     /*!< FSIZE (Bit 0)                                         */
15142 #define IOSLAVE_INTSET_FSIZE_Msk          (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
15143 /* ======================================================  REGACCINTEN  ====================================================== */
15144 #define IOSLAVE_REGACCINTEN_REGACC_Pos    (0UL)                     /*!< REGACC (Bit 0)                                        */
15145 #define IOSLAVE_REGACCINTEN_REGACC_Msk    (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
15146 /* =====================================================  REGACCINTSTAT  ===================================================== */
15147 #define IOSLAVE_REGACCINTSTAT_REGACC_Pos  (0UL)                     /*!< REGACC (Bit 0)                                        */
15148 #define IOSLAVE_REGACCINTSTAT_REGACC_Msk  (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
15149 /* =====================================================  REGACCINTCLR  ====================================================== */
15150 #define IOSLAVE_REGACCINTCLR_REGACC_Pos   (0UL)                     /*!< REGACC (Bit 0)                                        */
15151 #define IOSLAVE_REGACCINTCLR_REGACC_Msk   (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
15152 /* =====================================================  REGACCINTSET  ====================================================== */
15153 #define IOSLAVE_REGACCINTSET_REGACC_Pos   (0UL)                     /*!< REGACC (Bit 0)                                        */
15154 #define IOSLAVE_REGACCINTSET_REGACC_Msk   (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
15155 
15156 
15157 /* =========================================================================================================================== */
15158 /* ================                                          MCUCTRL                                          ================ */
15159 /* =========================================================================================================================== */
15160 
15161 /* ========================================================  CHIPPN  ========================================================= */
15162 #define MCUCTRL_CHIPPN_PARTNUM_Pos        (0UL)                     /*!< PARTNUM (Bit 0)                                       */
15163 #define MCUCTRL_CHIPPN_PARTNUM_Msk        (0xffffffffUL)            /*!< PARTNUM (Bitfield-Mask: 0xffffffff)                   */
15164 /* ========================================================  CHIPID0  ======================================================== */
15165 #define MCUCTRL_CHIPID0_CHIPID0_Pos       (0UL)                     /*!< CHIPID0 (Bit 0)                                       */
15166 #define MCUCTRL_CHIPID0_CHIPID0_Msk       (0xffffffffUL)            /*!< CHIPID0 (Bitfield-Mask: 0xffffffff)                   */
15167 /* ========================================================  CHIPID1  ======================================================== */
15168 #define MCUCTRL_CHIPID1_CHIPID1_Pos       (0UL)                     /*!< CHIPID1 (Bit 0)                                       */
15169 #define MCUCTRL_CHIPID1_CHIPID1_Msk       (0xffffffffUL)            /*!< CHIPID1 (Bitfield-Mask: 0xffffffff)                   */
15170 /* ========================================================  CHIPREV  ======================================================== */
15171 #define MCUCTRL_CHIPREV_SIPART_Pos        (8UL)                     /*!< SIPART (Bit 8)                                        */
15172 #define MCUCTRL_CHIPREV_SIPART_Msk        (0xfff00UL)               /*!< SIPART (Bitfield-Mask: 0xfff)                         */
15173 #define MCUCTRL_CHIPREV_REVMAJ_Pos        (4UL)                     /*!< REVMAJ (Bit 4)                                        */
15174 #define MCUCTRL_CHIPREV_REVMAJ_Msk        (0xf0UL)                  /*!< REVMAJ (Bitfield-Mask: 0x0f)                          */
15175 #define MCUCTRL_CHIPREV_REVMIN_Pos        (0UL)                     /*!< REVMIN (Bit 0)                                        */
15176 #define MCUCTRL_CHIPREV_REVMIN_Msk        (0xfUL)                   /*!< REVMIN (Bitfield-Mask: 0x0f)                          */
15177 /* =======================================================  VENDORID  ======================================================== */
15178 #define MCUCTRL_VENDORID_VENDORID_Pos     (0UL)                     /*!< VENDORID (Bit 0)                                      */
15179 #define MCUCTRL_VENDORID_VENDORID_Msk     (0xffffffffUL)            /*!< VENDORID (Bitfield-Mask: 0xffffffff)                  */
15180 /* ==========================================================  SKU  ========================================================== */
15181 #define MCUCTRL_SKU_SECBOOT_Pos           (2UL)                     /*!< SECBOOT (Bit 2)                                       */
15182 #define MCUCTRL_SKU_SECBOOT_Msk           (0x4UL)                   /*!< SECBOOT (Bitfield-Mask: 0x01)                         */
15183 #define MCUCTRL_SKU_ALLOWBLE_Pos          (1UL)                     /*!< ALLOWBLE (Bit 1)                                      */
15184 #define MCUCTRL_SKU_ALLOWBLE_Msk          (0x2UL)                   /*!< ALLOWBLE (Bitfield-Mask: 0x01)                        */
15185 #define MCUCTRL_SKU_ALLOWBURST_Pos        (0UL)                     /*!< ALLOWBURST (Bit 0)                                    */
15186 #define MCUCTRL_SKU_ALLOWBURST_Msk        (0x1UL)                   /*!< ALLOWBURST (Bitfield-Mask: 0x01)                      */
15187 /* =====================================================  FEATUREENABLE  ===================================================== */
15188 #define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Pos (6UL)                  /*!< BURSTAVAIL (Bit 6)                                    */
15189 #define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Msk (0x40UL)               /*!< BURSTAVAIL (Bitfield-Mask: 0x01)                      */
15190 #define MCUCTRL_FEATUREENABLE_BURSTACK_Pos (5UL)                    /*!< BURSTACK (Bit 5)                                      */
15191 #define MCUCTRL_FEATUREENABLE_BURSTACK_Msk (0x20UL)                 /*!< BURSTACK (Bitfield-Mask: 0x01)                        */
15192 #define MCUCTRL_FEATUREENABLE_BURSTREQ_Pos (4UL)                    /*!< BURSTREQ (Bit 4)                                      */
15193 #define MCUCTRL_FEATUREENABLE_BURSTREQ_Msk (0x10UL)                 /*!< BURSTREQ (Bitfield-Mask: 0x01)                        */
15194 #define MCUCTRL_FEATUREENABLE_BLEAVAIL_Pos (2UL)                    /*!< BLEAVAIL (Bit 2)                                      */
15195 #define MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk (0x4UL)                  /*!< BLEAVAIL (Bitfield-Mask: 0x01)                        */
15196 #define MCUCTRL_FEATUREENABLE_BLEACK_Pos  (1UL)                     /*!< BLEACK (Bit 1)                                        */
15197 #define MCUCTRL_FEATUREENABLE_BLEACK_Msk  (0x2UL)                   /*!< BLEACK (Bitfield-Mask: 0x01)                          */
15198 #define MCUCTRL_FEATUREENABLE_BLEREQ_Pos  (0UL)                     /*!< BLEREQ (Bit 0)                                        */
15199 #define MCUCTRL_FEATUREENABLE_BLEREQ_Msk  (0x1UL)                   /*!< BLEREQ (Bitfield-Mask: 0x01)                          */
15200 /* =======================================================  DEBUGGER  ======================================================== */
15201 #define MCUCTRL_DEBUGGER_LOCKOUT_Pos      (0UL)                     /*!< LOCKOUT (Bit 0)                                       */
15202 #define MCUCTRL_DEBUGGER_LOCKOUT_Msk      (0x1UL)                   /*!< LOCKOUT (Bitfield-Mask: 0x01)                         */
15203 /* =================================================  DMASRAMWRITEPROTECT2  ================================================== */
15204 #define MCUCTRL_DMASRAMWRITEPROTECT2_DMA_WPROT2_Pos (0UL)           /*!< DMA_WPROT2 (Bit 0)                                    */
15205 #define MCUCTRL_DMASRAMWRITEPROTECT2_DMA_WPROT2_Msk (0xffffffffUL)  /*!< DMA_WPROT2 (Bitfield-Mask: 0xffffffff)                */
15206 /* ========================================================  VRCTRL1  ======================================================== */
15207 #define MCUCTRL_VRCTRL1_BLEBUCKOVER_Pos   (8UL)                     /*!< BLEBUCKOVER (Bit 8)                                   */
15208 #define MCUCTRL_VRCTRL1_BLEBUCKOVER_Msk   (0x100UL)                 /*!< BLEBUCKOVER (Bitfield-Mask: 0x01)                     */
15209 #define MCUCTRL_VRCTRL1_BLEBUCKPDNB_Pos   (7UL)                     /*!< BLEBUCKPDNB (Bit 7)                                   */
15210 #define MCUCTRL_VRCTRL1_BLEBUCKPDNB_Msk   (0x80UL)                  /*!< BLEBUCKPDNB (Bitfield-Mask: 0x01)                     */
15211 #define MCUCTRL_VRCTRL1_BLEBUCKACTIVE_Pos (6UL)                     /*!< BLEBUCKACTIVE (Bit 6)                                 */
15212 #define MCUCTRL_VRCTRL1_BLEBUCKACTIVE_Msk (0x40UL)                  /*!< BLEBUCKACTIVE (Bitfield-Mask: 0x01)                   */
15213 #define MCUCTRL_VRCTRL1_BLEBUCKRSTB_Pos   (5UL)                     /*!< BLEBUCKRSTB (Bit 5)                                   */
15214 #define MCUCTRL_VRCTRL1_BLEBUCKRSTB_Msk   (0x20UL)                  /*!< BLEBUCKRSTB (Bitfield-Mask: 0x01)                     */
15215 /* ========================================================  VRCTRL2  ======================================================== */
15216 #define MCUCTRL_VRCTRL2_BURSTLDOOVER_Pos  (4UL)                     /*!< BURSTLDOOVER (Bit 4)                                  */
15217 #define MCUCTRL_VRCTRL2_BURSTLDOOVER_Msk  (0x10UL)                  /*!< BURSTLDOOVER (Bitfield-Mask: 0x01)                    */
15218 #define MCUCTRL_VRCTRL2_BURSTLDOPDNB_Pos  (3UL)                     /*!< BURSTLDOPDNB (Bit 3)                                  */
15219 #define MCUCTRL_VRCTRL2_BURSTLDOPDNB_Msk  (0x8UL)                   /*!< BURSTLDOPDNB (Bitfield-Mask: 0x01)                    */
15220 #define MCUCTRL_VRCTRL2_BURSTLDOACTIVEEARLY_Pos (2UL)               /*!< BURSTLDOACTIVEEARLY (Bit 2)                           */
15221 #define MCUCTRL_VRCTRL2_BURSTLDOACTIVEEARLY_Msk (0x4UL)             /*!< BURSTLDOACTIVEEARLY (Bitfield-Mask: 0x01)             */
15222 #define MCUCTRL_VRCTRL2_BURSTLDOACTIVE_Pos (1UL)                    /*!< BURSTLDOACTIVE (Bit 1)                                */
15223 #define MCUCTRL_VRCTRL2_BURSTLDOACTIVE_Msk (0x2UL)                  /*!< BURSTLDOACTIVE (Bitfield-Mask: 0x01)                  */
15224 #define MCUCTRL_VRCTRL2_BURSTLDOCOLDSTARTEN_Pos (0UL)               /*!< BURSTLDOCOLDSTARTEN (Bit 0)                           */
15225 #define MCUCTRL_VRCTRL2_BURSTLDOCOLDSTARTEN_Msk (0x1UL)             /*!< BURSTLDOCOLDSTARTEN (Bitfield-Mask: 0x01)             */
15226 /* ========================================================  LDOREG1  ======================================================== */
15227 #define MCUCTRL_LDOREG1_CORELDOIBIASSEL_Pos (21UL)                  /*!< CORELDOIBIASSEL (Bit 21)                              */
15228 #define MCUCTRL_LDOREG1_CORELDOIBIASSEL_Msk (0x200000UL)            /*!< CORELDOIBIASSEL (Bitfield-Mask: 0x01)                 */
15229 #define MCUCTRL_LDOREG1_CORELDOIBIASTRIM_Pos (20UL)                 /*!< CORELDOIBIASTRIM (Bit 20)                             */
15230 #define MCUCTRL_LDOREG1_CORELDOIBIASTRIM_Msk (0x100000UL)           /*!< CORELDOIBIASTRIM (Bitfield-Mask: 0x01)                */
15231 #define MCUCTRL_LDOREG1_CORELDOLPTRIM_Pos (14UL)                    /*!< CORELDOLPTRIM (Bit 14)                                */
15232 #define MCUCTRL_LDOREG1_CORELDOLPTRIM_Msk (0xfc000UL)               /*!< CORELDOLPTRIM (Bitfield-Mask: 0x3f)                   */
15233 #define MCUCTRL_LDOREG1_CORELDOTEMPCOTRIM_Pos (10UL)                /*!< CORELDOTEMPCOTRIM (Bit 10)                            */
15234 #define MCUCTRL_LDOREG1_CORELDOTEMPCOTRIM_Msk (0x3c00UL)            /*!< CORELDOTEMPCOTRIM (Bitfield-Mask: 0x0f)               */
15235 #define MCUCTRL_LDOREG1_CORELDOACTIVETRIM_Pos (0UL)                 /*!< CORELDOACTIVETRIM (Bit 0)                             */
15236 #define MCUCTRL_LDOREG1_CORELDOACTIVETRIM_Msk (0x3ffUL)             /*!< CORELDOACTIVETRIM (Bitfield-Mask: 0x3ff)              */
15237 /* ========================================================  LDOREG2  ======================================================== */
15238 #define MCUCTRL_LDOREG2_TRIMANALDO_Pos    (26UL)                    /*!< TRIMANALDO (Bit 26)                                   */
15239 #define MCUCTRL_LDOREG2_TRIMANALDO_Msk    (0x3c000000UL)            /*!< TRIMANALDO (Bitfield-Mask: 0x0f)                      */
15240 #define MCUCTRL_LDOREG2_MEMLDOIBIASSEL_Pos (25UL)                   /*!< MEMLDOIBIASSEL (Bit 25)                               */
15241 #define MCUCTRL_LDOREG2_MEMLDOIBIASSEL_Msk (0x2000000UL)            /*!< MEMLDOIBIASSEL (Bitfield-Mask: 0x01)                  */
15242 #define MCUCTRL_LDOREG2_MEMLPLDOIBIASTRIM_Pos (24UL)                /*!< MEMLPLDOIBIASTRIM (Bit 24)                            */
15243 #define MCUCTRL_LDOREG2_MEMLPLDOIBIASTRIM_Msk (0x1000000UL)         /*!< MEMLPLDOIBIASTRIM (Bitfield-Mask: 0x01)               */
15244 #define MCUCTRL_LDOREG2_MEMLPLDOTRIM_Pos  (18UL)                    /*!< MEMLPLDOTRIM (Bit 18)                                 */
15245 #define MCUCTRL_LDOREG2_MEMLPLDOTRIM_Msk  (0xfc0000UL)              /*!< MEMLPLDOTRIM (Bitfield-Mask: 0x3f)                    */
15246 #define MCUCTRL_LDOREG2_MEMLDOLPALTTRIM_Pos (12UL)                  /*!< MEMLDOLPALTTRIM (Bit 12)                              */
15247 #define MCUCTRL_LDOREG2_MEMLDOLPALTTRIM_Msk (0x3f000UL)             /*!< MEMLDOLPALTTRIM (Bitfield-Mask: 0x3f)                 */
15248 #define MCUCTRL_LDOREG2_MEMLDOLPTRIM_Pos  (6UL)                     /*!< MEMLDOLPTRIM (Bit 6)                                  */
15249 #define MCUCTRL_LDOREG2_MEMLDOLPTRIM_Msk  (0xfc0UL)                 /*!< MEMLDOLPTRIM (Bitfield-Mask: 0x3f)                    */
15250 #define MCUCTRL_LDOREG2_MEMLDOACTIVETRIM_Pos (0UL)                  /*!< MEMLDOACTIVETRIM (Bit 0)                              */
15251 #define MCUCTRL_LDOREG2_MEMLDOACTIVETRIM_Msk (0x3fUL)               /*!< MEMLDOACTIVETRIM (Bitfield-Mask: 0x3f)                */
15252 /* =======================================================  ADCPWRDLY  ======================================================= */
15253 #define MCUCTRL_ADCPWRDLY_ADCPWR1_Pos     (8UL)                     /*!< ADCPWR1 (Bit 8)                                       */
15254 #define MCUCTRL_ADCPWRDLY_ADCPWR1_Msk     (0xff00UL)                /*!< ADCPWR1 (Bitfield-Mask: 0xff)                         */
15255 #define MCUCTRL_ADCPWRDLY_ADCPWR0_Pos     (0UL)                     /*!< ADCPWR0 (Bit 0)                                       */
15256 #define MCUCTRL_ADCPWRDLY_ADCPWR0_Msk     (0xffUL)                  /*!< ADCPWR0 (Bitfield-Mask: 0xff)                         */
15257 /* ========================================================  ADCCAL  ========================================================= */
15258 #define MCUCTRL_ADCCAL_ADCCALIBRATED_Pos  (1UL)                     /*!< ADCCALIBRATED (Bit 1)                                 */
15259 #define MCUCTRL_ADCCAL_ADCCALIBRATED_Msk  (0x2UL)                   /*!< ADCCALIBRATED (Bitfield-Mask: 0x01)                   */
15260 #define MCUCTRL_ADCCAL_CALONPWRUP_Pos     (0UL)                     /*!< CALONPWRUP (Bit 0)                                    */
15261 #define MCUCTRL_ADCCAL_CALONPWRUP_Msk     (0x1UL)                   /*!< CALONPWRUP (Bitfield-Mask: 0x01)                      */
15262 /* ======================================================  ADCBATTLOAD  ====================================================== */
15263 #define MCUCTRL_ADCBATTLOAD_BATTLOAD_Pos  (0UL)                     /*!< BATTLOAD (Bit 0)                                      */
15264 #define MCUCTRL_ADCBATTLOAD_BATTLOAD_Msk  (0x1UL)                   /*!< BATTLOAD (Bitfield-Mask: 0x01)                        */
15265 /* ========================================================  ADCTRIM  ======================================================== */
15266 #define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Pos (11UL)                   /*!< ADCRFBUFIBTRIM (Bit 11)                               */
15267 #define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Msk (0x1800UL)               /*!< ADCRFBUFIBTRIM (Bitfield-Mask: 0x03)                  */
15268 #define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Pos (6UL)                     /*!< ADCREFBUFTRIM (Bit 6)                                 */
15269 #define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Msk (0x7c0UL)                 /*!< ADCREFBUFTRIM (Bitfield-Mask: 0x1f)                   */
15270 #define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Pos (0UL)                  /*!< ADCREFKEEPIBTRIM (Bit 0)                              */
15271 #define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Msk (0x3UL)                /*!< ADCREFKEEPIBTRIM (Bitfield-Mask: 0x03)                */
15272 /* ======================================================  ADCREFCOMP  ======================================================= */
15273 #define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Pos (16UL)                    /*!< ADCRFCMPEN (Bit 16)                                   */
15274 #define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Msk (0x10000UL)               /*!< ADCRFCMPEN (Bitfield-Mask: 0x01)                      */
15275 #define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Pos (8UL)                 /*!< ADCREFKEEPTRIM (Bit 8)                                */
15276 #define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Msk (0x1f00UL)            /*!< ADCREFKEEPTRIM (Bitfield-Mask: 0x1f)                  */
15277 #define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Pos (0UL)                /*!< ADC_REFCOMP_OUT (Bit 0)                               */
15278 #define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Msk (0x1UL)              /*!< ADC_REFCOMP_OUT (Bitfield-Mask: 0x01)                 */
15279 /* =======================================================  XTALCTRL  ======================================================== */
15280 #define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Pos (8UL)                    /*!< XTALICOMPTRIM (Bit 8)                                 */
15281 #define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Msk (0x300UL)                /*!< XTALICOMPTRIM (Bitfield-Mask: 0x03)                   */
15282 #define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Pos (6UL)                     /*!< XTALIBUFTRIM (Bit 6)                                  */
15283 #define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Msk (0xc0UL)                  /*!< XTALIBUFTRIM (Bitfield-Mask: 0x03)                    */
15284 #define MCUCTRL_XTALCTRL_PWDBODXTAL_Pos   (5UL)                     /*!< PWDBODXTAL (Bit 5)                                    */
15285 #define MCUCTRL_XTALCTRL_PWDBODXTAL_Msk   (0x20UL)                  /*!< PWDBODXTAL (Bitfield-Mask: 0x01)                      */
15286 #define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Pos (4UL)                     /*!< PDNBCMPRXTAL (Bit 4)                                  */
15287 #define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk (0x10UL)                  /*!< PDNBCMPRXTAL (Bitfield-Mask: 0x01)                    */
15288 #define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Pos (3UL)                     /*!< PDNBCOREXTAL (Bit 3)                                  */
15289 #define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk (0x8UL)                   /*!< PDNBCOREXTAL (Bitfield-Mask: 0x01)                    */
15290 #define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Pos  (2UL)                     /*!< BYPCMPRXTAL (Bit 2)                                   */
15291 #define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk  (0x4UL)                   /*!< BYPCMPRXTAL (Bitfield-Mask: 0x01)                     */
15292 #define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Pos (1UL)                     /*!< FDBKDSBLXTAL (Bit 1)                                  */
15293 #define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk (0x2UL)                   /*!< FDBKDSBLXTAL (Bitfield-Mask: 0x01)                    */
15294 #define MCUCTRL_XTALCTRL_XTALSWE_Pos      (0UL)                     /*!< XTALSWE (Bit 0)                                       */
15295 #define MCUCTRL_XTALCTRL_XTALSWE_Msk      (0x1UL)                   /*!< XTALSWE (Bitfield-Mask: 0x01)                         */
15296 /* ======================================================  XTALGENCTRL  ====================================================== */
15297 #define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Pos (8UL)                /*!< XTALKSBIASTRIM (Bit 8)                                */
15298 #define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Msk (0x3f00UL)           /*!< XTALKSBIASTRIM (Bitfield-Mask: 0x3f)                  */
15299 #define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Pos (2UL)                  /*!< XTALBIASTRIM (Bit 2)                                  */
15300 #define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Msk (0xfcUL)               /*!< XTALBIASTRIM (Bitfield-Mask: 0x3f)                    */
15301 #define MCUCTRL_XTALGENCTRL_ACWARMUP_Pos  (0UL)                     /*!< ACWARMUP (Bit 0)                                      */
15302 #define MCUCTRL_XTALGENCTRL_ACWARMUP_Msk  (0x3UL)                   /*!< ACWARMUP (Bitfield-Mask: 0x03)                        */
15303 /* ======================================================  MISCPWRCTRL  ====================================================== */
15304 #define MCUCTRL_MISCPWRCTRL_VDDRBURSTOVER_Pos (17UL)                /*!< VDDRBURSTOVER (Bit 17)                                */
15305 #define MCUCTRL_MISCPWRCTRL_VDDRBURSTOVER_Msk (0x20000UL)           /*!< VDDRBURSTOVER (Bitfield-Mask: 0x01)                   */
15306 #define MCUCTRL_MISCPWRCTRL_PWRSWVDDRBURSTEN_Pos (16UL)             /*!< PWRSWVDDRBURSTEN (Bit 16)                             */
15307 #define MCUCTRL_MISCPWRCTRL_PWRSWVDDRBURSTEN_Msk (0x10000UL)        /*!< PWRSWVDDRBURSTEN (Bitfield-Mask: 0x01)                */
15308 #define MCUCTRL_MISCPWRCTRL_VDDRACTIVEOVER_Pos (15UL)               /*!< VDDRACTIVEOVER (Bit 15)                               */
15309 #define MCUCTRL_MISCPWRCTRL_VDDRACTIVEOVER_Msk (0x8000UL)           /*!< VDDRACTIVEOVER (Bitfield-Mask: 0x01)                  */
15310 #define MCUCTRL_MISCPWRCTRL_PWRSWVDDRACTIVEEN_Pos (14UL)            /*!< PWRSWVDDRACTIVEEN (Bit 14)                            */
15311 #define MCUCTRL_MISCPWRCTRL_PWRSWVDDRACTIVEEN_Msk (0x4000UL)        /*!< PWRSWVDDRACTIVEEN (Bitfield-Mask: 0x01)               */
15312 #define MCUCTRL_MISCPWRCTRL_VDDLHBURSTOVER_Pos (13UL)               /*!< VDDLHBURSTOVER (Bit 13)                               */
15313 #define MCUCTRL_MISCPWRCTRL_VDDLHBURSTOVER_Msk (0x2000UL)           /*!< VDDLHBURSTOVER (Bitfield-Mask: 0x01)                  */
15314 #define MCUCTRL_MISCPWRCTRL_PWRSWVDDLHBURSTEN_Pos (12UL)            /*!< PWRSWVDDLHBURSTEN (Bit 12)                            */
15315 #define MCUCTRL_MISCPWRCTRL_PWRSWVDDLHBURSTEN_Msk (0x1000UL)        /*!< PWRSWVDDLHBURSTEN (Bitfield-Mask: 0x01)               */
15316 /* =======================================================  MISCCTRL  ======================================================== */
15317 #define MCUCTRL_MISCCTRL_BLE_RESETN_Pos   (5UL)                     /*!< BLE_RESETN (Bit 5)                                    */
15318 #define MCUCTRL_MISCCTRL_BLE_RESETN_Msk   (0x20UL)                  /*!< BLE_RESETN (Bitfield-Mask: 0x01)                      */
15319 /* ======================================================  BOOTLOADER  ======================================================= */
15320 #define MCUCTRL_BOOTLOADER_SECBOOTONRST_Pos (30UL)                  /*!< SECBOOTONRST (Bit 30)                                 */
15321 #define MCUCTRL_BOOTLOADER_SECBOOTONRST_Msk (0xc0000000UL)          /*!< SECBOOTONRST (Bitfield-Mask: 0x03)                    */
15322 #define MCUCTRL_BOOTLOADER_SECBOOT_Pos    (28UL)                    /*!< SECBOOT (Bit 28)                                      */
15323 #define MCUCTRL_BOOTLOADER_SECBOOT_Msk    (0x30000000UL)            /*!< SECBOOT (Bitfield-Mask: 0x03)                         */
15324 #define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Pos (26UL)                /*!< SECBOOTFEATURE (Bit 26)                               */
15325 #define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Msk (0xc000000UL)         /*!< SECBOOTFEATURE (Bitfield-Mask: 0x03)                  */
15326 #define MCUCTRL_BOOTLOADER_PROTLOCK_Pos   (2UL)                     /*!< PROTLOCK (Bit 2)                                      */
15327 #define MCUCTRL_BOOTLOADER_PROTLOCK_Msk   (0x4UL)                   /*!< PROTLOCK (Bitfield-Mask: 0x01)                        */
15328 #define MCUCTRL_BOOTLOADER_SBLOCK_Pos     (1UL)                     /*!< SBLOCK (Bit 1)                                        */
15329 #define MCUCTRL_BOOTLOADER_SBLOCK_Msk     (0x2UL)                   /*!< SBLOCK (Bitfield-Mask: 0x01)                          */
15330 #define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Pos (0UL)                  /*!< BOOTLOADERLOW (Bit 0)                                 */
15331 #define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Msk (0x1UL)                /*!< BOOTLOADERLOW (Bitfield-Mask: 0x01)                   */
15332 /* ======================================================  SHADOWVALID  ====================================================== */
15333 #define MCUCTRL_SHADOWVALID_INFO0_VALID_Pos (2UL)                   /*!< INFO0_VALID (Bit 2)                                   */
15334 #define MCUCTRL_SHADOWVALID_INFO0_VALID_Msk (0x4UL)                 /*!< INFO0_VALID (Bitfield-Mask: 0x01)                     */
15335 #define MCUCTRL_SHADOWVALID_BLDSLEEP_Pos  (1UL)                     /*!< BLDSLEEP (Bit 1)                                      */
15336 #define MCUCTRL_SHADOWVALID_BLDSLEEP_Msk  (0x2UL)                   /*!< BLDSLEEP (Bitfield-Mask: 0x01)                        */
15337 #define MCUCTRL_SHADOWVALID_VALID_Pos     (0UL)                     /*!< VALID (Bit 0)                                         */
15338 #define MCUCTRL_SHADOWVALID_VALID_Msk     (0x1UL)                   /*!< VALID (Bitfield-Mask: 0x01)                           */
15339 /* =======================================================  SCRATCH0  ======================================================== */
15340 #define MCUCTRL_SCRATCH0_SCRATCH0_Pos     (0UL)                     /*!< SCRATCH0 (Bit 0)                                      */
15341 #define MCUCTRL_SCRATCH0_SCRATCH0_Msk     (0xffffffffUL)            /*!< SCRATCH0 (Bitfield-Mask: 0xffffffff)                  */
15342 /* =======================================================  SCRATCH1  ======================================================== */
15343 #define MCUCTRL_SCRATCH1_SCRATCH1_Pos     (0UL)                     /*!< SCRATCH1 (Bit 0)                                      */
15344 #define MCUCTRL_SCRATCH1_SCRATCH1_Msk     (0xffffffffUL)            /*!< SCRATCH1 (Bitfield-Mask: 0xffffffff)                  */
15345 /* ====================================================  ICODEFAULTADDR  ===================================================== */
15346 #define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Pos (0UL)             /*!< ICODEFAULTADDR (Bit 0)                                */
15347 #define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Msk (0xffffffffUL)    /*!< ICODEFAULTADDR (Bitfield-Mask: 0xffffffff)            */
15348 /* ====================================================  DCODEFAULTADDR  ===================================================== */
15349 #define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Pos (0UL)             /*!< DCODEFAULTADDR (Bit 0)                                */
15350 #define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Msk (0xffffffffUL)    /*!< DCODEFAULTADDR (Bitfield-Mask: 0xffffffff)            */
15351 /* =====================================================  SYSFAULTADDR  ====================================================== */
15352 #define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Pos (0UL)                 /*!< SYSFAULTADDR (Bit 0)                                  */
15353 #define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Msk (0xffffffffUL)        /*!< SYSFAULTADDR (Bitfield-Mask: 0xffffffff)              */
15354 /* ======================================================  FAULTSTATUS  ====================================================== */
15355 #define MCUCTRL_FAULTSTATUS_SYSFAULT_Pos  (2UL)                     /*!< SYSFAULT (Bit 2)                                      */
15356 #define MCUCTRL_FAULTSTATUS_SYSFAULT_Msk  (0x4UL)                   /*!< SYSFAULT (Bitfield-Mask: 0x01)                        */
15357 #define MCUCTRL_FAULTSTATUS_DCODEFAULT_Pos (1UL)                    /*!< DCODEFAULT (Bit 1)                                    */
15358 #define MCUCTRL_FAULTSTATUS_DCODEFAULT_Msk (0x2UL)                  /*!< DCODEFAULT (Bitfield-Mask: 0x01)                      */
15359 #define MCUCTRL_FAULTSTATUS_ICODEFAULT_Pos (0UL)                    /*!< ICODEFAULT (Bit 0)                                    */
15360 #define MCUCTRL_FAULTSTATUS_ICODEFAULT_Msk (0x1UL)                  /*!< ICODEFAULT (Bitfield-Mask: 0x01)                      */
15361 /* ====================================================  FAULTCAPTUREEN  ===================================================== */
15362 #define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Pos (0UL)             /*!< FAULTCAPTUREEN (Bit 0)                                */
15363 #define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Msk (0x1UL)           /*!< FAULTCAPTUREEN (Bitfield-Mask: 0x01)                  */
15364 /* =========================================================  DBGR1  ========================================================= */
15365 #define MCUCTRL_DBGR1_ONETO8_Pos          (0UL)                     /*!< ONETO8 (Bit 0)                                        */
15366 #define MCUCTRL_DBGR1_ONETO8_Msk          (0xffffffffUL)            /*!< ONETO8 (Bitfield-Mask: 0xffffffff)                    */
15367 /* =========================================================  DBGR2  ========================================================= */
15368 #define MCUCTRL_DBGR2_COOLCODE_Pos        (0UL)                     /*!< COOLCODE (Bit 0)                                      */
15369 #define MCUCTRL_DBGR2_COOLCODE_Msk        (0xffffffffUL)            /*!< COOLCODE (Bitfield-Mask: 0xffffffff)                  */
15370 /* =======================================================  PMUENABLE  ======================================================= */
15371 #define MCUCTRL_PMUENABLE_ENABLE_Pos      (0UL)                     /*!< ENABLE (Bit 0)                                        */
15372 #define MCUCTRL_PMUENABLE_ENABLE_Msk      (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
15373 /* =======================================================  TPIUCTRL  ======================================================== */
15374 #define MCUCTRL_TPIUCTRL_CLKSEL_Pos       (8UL)                     /*!< CLKSEL (Bit 8)                                        */
15375 #define MCUCTRL_TPIUCTRL_CLKSEL_Msk       (0x700UL)                 /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
15376 #define MCUCTRL_TPIUCTRL_ENABLE_Pos       (0UL)                     /*!< ENABLE (Bit 0)                                        */
15377 #define MCUCTRL_TPIUCTRL_ENABLE_Msk       (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
15378 /* ======================================================  OTAPOINTER  ======================================================= */
15379 #define MCUCTRL_OTAPOINTER_OTAPOINTER_Pos (2UL)                     /*!< OTAPOINTER (Bit 2)                                    */
15380 #define MCUCTRL_OTAPOINTER_OTAPOINTER_Msk (0xfffffffcUL)            /*!< OTAPOINTER (Bitfield-Mask: 0x3fffffff)                */
15381 #define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Pos (1UL)                   /*!< OTASBLUPDATE (Bit 1)                                  */
15382 #define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Msk (0x2UL)                 /*!< OTASBLUPDATE (Bitfield-Mask: 0x01)                    */
15383 #define MCUCTRL_OTAPOINTER_OTAVALID_Pos   (0UL)                     /*!< OTAVALID (Bit 0)                                      */
15384 #define MCUCTRL_OTAPOINTER_OTAVALID_Msk   (0x1UL)                   /*!< OTAVALID (Bitfield-Mask: 0x01)                        */
15385 /* =======================================================  SRAMMODE  ======================================================== */
15386 #define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Pos (5UL)                  /*!< DPREFETCH_CACHE (Bit 5)                               */
15387 #define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk (0x20UL)               /*!< DPREFETCH_CACHE (Bitfield-Mask: 0x01)                 */
15388 #define MCUCTRL_SRAMMODE_DPREFETCH_Pos    (4UL)                     /*!< DPREFETCH (Bit 4)                                     */
15389 #define MCUCTRL_SRAMMODE_DPREFETCH_Msk    (0x10UL)                  /*!< DPREFETCH (Bitfield-Mask: 0x01)                       */
15390 #define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Pos (1UL)                  /*!< IPREFETCH_CACHE (Bit 1)                               */
15391 #define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk (0x2UL)                /*!< IPREFETCH_CACHE (Bitfield-Mask: 0x01)                 */
15392 #define MCUCTRL_SRAMMODE_IPREFETCH_Pos    (0UL)                     /*!< IPREFETCH (Bit 0)                                     */
15393 #define MCUCTRL_SRAMMODE_IPREFETCH_Msk    (0x1UL)                   /*!< IPREFETCH (Bitfield-Mask: 0x01)                       */
15394 /* ======================================================  KEXTCLKSEL  ======================================================= */
15395 #define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Pos (0UL)                     /*!< KEXTCLKSEL (Bit 0)                                    */
15396 #define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Msk (0xffffffffUL)            /*!< KEXTCLKSEL (Bitfield-Mask: 0xffffffff)                */
15397 /* =======================================================  SIMOBUCK1  ======================================================= */
15398 #define MCUCTRL_SIMOBUCK1_CORETEMPCOTRIM_Pos (28UL)                 /*!< CORETEMPCOTRIM (Bit 28)                               */
15399 #define MCUCTRL_SIMOBUCK1_CORETEMPCOTRIM_Msk (0xf0000000UL)         /*!< CORETEMPCOTRIM (Bitfield-Mask: 0x0f)                  */
15400 #define MCUCTRL_SIMOBUCK1_SIMOBUCKMEMLPTRIM_Pos (22UL)              /*!< SIMOBUCKMEMLPTRIM (Bit 22)                            */
15401 #define MCUCTRL_SIMOBUCK1_SIMOBUCKMEMLPTRIM_Msk (0xfc00000UL)       /*!< SIMOBUCKMEMLPTRIM (Bitfield-Mask: 0x3f)               */
15402 #define MCUCTRL_SIMOBUCK1_MEMACTIVETRIM_Pos (16UL)                  /*!< MEMACTIVETRIM (Bit 16)                                */
15403 #define MCUCTRL_SIMOBUCK1_MEMACTIVETRIM_Msk (0x3f0000UL)            /*!< MEMACTIVETRIM (Bitfield-Mask: 0x3f)                   */
15404 #define MCUCTRL_SIMOBUCK1_SIMOBUCKCORELPTRIM_Pos (10UL)             /*!< SIMOBUCKCORELPTRIM (Bit 10)                           */
15405 #define MCUCTRL_SIMOBUCK1_SIMOBUCKCORELPTRIM_Msk (0xfc00UL)         /*!< SIMOBUCKCORELPTRIM (Bitfield-Mask: 0x3f)              */
15406 #define MCUCTRL_SIMOBUCK1_COREACTIVETRIM_Pos (0UL)                  /*!< COREACTIVETRIM (Bit 0)                                */
15407 #define MCUCTRL_SIMOBUCK1_COREACTIVETRIM_Msk (0x3ffUL)              /*!< COREACTIVETRIM (Bitfield-Mask: 0x3ff)                 */
15408 /* =======================================================  SIMOBUCK2  ======================================================= */
15409 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELEAKAGETRIM_Pos (28UL)        /*!< SIMOBUCKCORELEAKAGETRIM (Bit 28)                      */
15410 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELEAKAGETRIM_Msk (0x30000000UL) /*!< SIMOBUCKCORELEAKAGETRIM (Bitfield-Mask: 0x03)        */
15411 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPLOWTONTRIM_Pos (20UL)       /*!< SIMOBUCKCORELPLOWTONTRIM (Bit 20)                     */
15412 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPLOWTONTRIM_Msk (0xf00000UL) /*!< SIMOBUCKCORELPLOWTONTRIM (Bitfield-Mask: 0x0f)        */
15413 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPHIGHTONTRIM_Pos (16UL)      /*!< SIMOBUCKCORELPHIGHTONTRIM (Bit 16)                    */
15414 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPHIGHTONTRIM_Msk (0xf0000UL) /*!< SIMOBUCKCORELPHIGHTONTRIM (Bitfield-Mask: 0x0f)       */
15415 #define MCUCTRL_SIMOBUCK2_SIMOBUCKTONGENTRIM_Pos (0UL)              /*!< SIMOBUCKTONGENTRIM (Bit 0)                            */
15416 #define MCUCTRL_SIMOBUCK2_SIMOBUCKTONGENTRIM_Msk (0x1fUL)           /*!< SIMOBUCKTONGENTRIM (Bitfield-Mask: 0x1f)              */
15417 /* =======================================================  SIMOBUCK3  ======================================================= */
15418 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTONTRIM_Pos (27UL)       /*!< SIMOBUCKMEMLPHIGHTONTRIM (Bit 27)                     */
15419 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTONTRIM_Msk (0x78000000UL) /*!< SIMOBUCKMEMLPHIGHTONTRIM (Bitfield-Mask: 0x0f)      */
15420 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPLOWTOFFTRIM_Pos (12UL)       /*!< SIMOBUCKMEMLPLOWTOFFTRIM (Bit 12)                     */
15421 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPLOWTOFFTRIM_Msk (0xf000UL)   /*!< SIMOBUCKMEMLPLOWTOFFTRIM (Bitfield-Mask: 0x0f)        */
15422 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTOFFTRIM_Pos (8UL)       /*!< SIMOBUCKMEMLPHIGHTOFFTRIM (Bit 8)                     */
15423 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTOFFTRIM_Msk (0xf00UL)   /*!< SIMOBUCKMEMLPHIGHTOFFTRIM (Bitfield-Mask: 0x0f)       */
15424 #define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPLOWTOFFTRIM_Pos (4UL)       /*!< SIMOBUCKCORELPLOWTOFFTRIM (Bit 4)                     */
15425 #define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPLOWTOFFTRIM_Msk (0xf0UL)    /*!< SIMOBUCKCORELPLOWTOFFTRIM (Bitfield-Mask: 0x0f)       */
15426 #define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPHIGHTOFFTRIM_Pos (0UL)      /*!< SIMOBUCKCORELPHIGHTOFFTRIM (Bit 0)                    */
15427 #define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPHIGHTOFFTRIM_Msk (0xfUL)    /*!< SIMOBUCKCORELPHIGHTOFFTRIM (Bitfield-Mask: 0x0f)      */
15428 /* =======================================================  SIMOBUCK4  ======================================================= */
15429 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2TIMEOUTEN_Pos (24UL)         /*!< SIMOBUCKCOMP2TIMEOUTEN (Bit 24)                       */
15430 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2TIMEOUTEN_Msk (0x1000000UL)  /*!< SIMOBUCKCOMP2TIMEOUTEN (Bitfield-Mask: 0x01)          */
15431 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2LPEN_Pos (23UL)              /*!< SIMOBUCKCOMP2LPEN (Bit 23)                            */
15432 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2LPEN_Msk (0x800000UL)        /*!< SIMOBUCKCOMP2LPEN (Bitfield-Mask: 0x01)               */
15433 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Pos (21UL)              /*!< SIMOBUCKCLKDIVSEL (Bit 21)                            */
15434 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Msk (0x600000UL)        /*!< SIMOBUCKCLKDIVSEL (Bitfield-Mask: 0x03)               */
15435 #define MCUCTRL_SIMOBUCK4_SIMOBUCKMEMLPLOWTONTRIM_Pos (0UL)         /*!< SIMOBUCKMEMLPLOWTONTRIM (Bit 0)                       */
15436 #define MCUCTRL_SIMOBUCK4_SIMOBUCKMEMLPLOWTONTRIM_Msk (0xfUL)       /*!< SIMOBUCKMEMLPLOWTONTRIM (Bitfield-Mask: 0x0f)         */
15437 /* =======================================================  BLEBUCK1  ======================================================== */
15438 #define MCUCTRL_BLEBUCK1_BLEBUCKPULLUPTRIM_Pos (15UL)               /*!< BLEBUCKPULLUPTRIM (Bit 15)                            */
15439 #define MCUCTRL_BLEBUCK1_BLEBUCKPULLUPTRIM_Msk (0x78000UL)          /*!< BLEBUCKPULLUPTRIM (Bitfield-Mask: 0x0f)               */
15440 /* =======================================================  BLEBUCK2  ======================================================== */
15441 #define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Pos (12UL)               /*!< BLEBUCKTOND2ATRIM (Bit 12)                            */
15442 #define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Msk (0x3f000UL)          /*!< BLEBUCKTOND2ATRIM (Bitfield-Mask: 0x3f)               */
15443 #define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Pos (6UL)                 /*!< BLEBUCKTONHITRIM (Bit 6)                              */
15444 #define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Msk (0xfc0UL)             /*!< BLEBUCKTONHITRIM (Bitfield-Mask: 0x3f)                */
15445 #define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Pos (0UL)                /*!< BLEBUCKTONLOWTRIM (Bit 0)                             */
15446 #define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Msk (0x3fUL)             /*!< BLEBUCKTONLOWTRIM (Bitfield-Mask: 0x3f)               */
15447 /* ======================================================  FLASHWPROT0  ====================================================== */
15448 #define MCUCTRL_FLASHWPROT0_FW0BITS_Pos   (0UL)                     /*!< FW0BITS (Bit 0)                                       */
15449 #define MCUCTRL_FLASHWPROT0_FW0BITS_Msk   (0xffffffffUL)            /*!< FW0BITS (Bitfield-Mask: 0xffffffff)                   */
15450 /* ======================================================  FLASHWPROT1  ====================================================== */
15451 #define MCUCTRL_FLASHWPROT1_FW1BITS_Pos   (0UL)                     /*!< FW1BITS (Bit 0)                                       */
15452 #define MCUCTRL_FLASHWPROT1_FW1BITS_Msk   (0xffffffffUL)            /*!< FW1BITS (Bitfield-Mask: 0xffffffff)                   */
15453 /* ======================================================  FLASHWPROT2  ====================================================== */
15454 #define MCUCTRL_FLASHWPROT2_FW2BITS_Pos   (0UL)                     /*!< FW2BITS (Bit 0)                                       */
15455 #define MCUCTRL_FLASHWPROT2_FW2BITS_Msk   (0xffffffffUL)            /*!< FW2BITS (Bitfield-Mask: 0xffffffff)                   */
15456 /* ======================================================  FLASHWPROT3  ====================================================== */
15457 #define MCUCTRL_FLASHWPROT3_FW3BITS_Pos   (0UL)                     /*!< FW3BITS (Bit 0)                                       */
15458 #define MCUCTRL_FLASHWPROT3_FW3BITS_Msk   (0xffffffffUL)            /*!< FW3BITS (Bitfield-Mask: 0xffffffff)                   */
15459 /* ======================================================  FLASHRPROT0  ====================================================== */
15460 #define MCUCTRL_FLASHRPROT0_FR0BITS_Pos   (0UL)                     /*!< FR0BITS (Bit 0)                                       */
15461 #define MCUCTRL_FLASHRPROT0_FR0BITS_Msk   (0xffffffffUL)            /*!< FR0BITS (Bitfield-Mask: 0xffffffff)                   */
15462 /* ======================================================  FLASHRPROT1  ====================================================== */
15463 #define MCUCTRL_FLASHRPROT1_FR1BITS_Pos   (0UL)                     /*!< FR1BITS (Bit 0)                                       */
15464 #define MCUCTRL_FLASHRPROT1_FR1BITS_Msk   (0xffffffffUL)            /*!< FR1BITS (Bitfield-Mask: 0xffffffff)                   */
15465 /* ======================================================  FLASHRPROT2  ====================================================== */
15466 #define MCUCTRL_FLASHRPROT2_FR2BITS_Pos   (0UL)                     /*!< FR2BITS (Bit 0)                                       */
15467 #define MCUCTRL_FLASHRPROT2_FR2BITS_Msk   (0xffffffffUL)            /*!< FR2BITS (Bitfield-Mask: 0xffffffff)                   */
15468 /* ======================================================  FLASHRPROT3  ====================================================== */
15469 #define MCUCTRL_FLASHRPROT3_FR3BITS_Pos   (0UL)                     /*!< FR3BITS (Bit 0)                                       */
15470 #define MCUCTRL_FLASHRPROT3_FR3BITS_Msk   (0xffffffffUL)            /*!< FR3BITS (Bitfield-Mask: 0xffffffff)                   */
15471 /* =================================================  DMASRAMWRITEPROTECT0  ================================================== */
15472 #define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Pos (0UL)           /*!< DMA_WPROT0 (Bit 0)                                    */
15473 #define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Msk (0xffffffffUL)  /*!< DMA_WPROT0 (Bitfield-Mask: 0xffffffff)                */
15474 /* =================================================  DMASRAMWRITEPROTECT1  ================================================== */
15475 #define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Pos (0UL)           /*!< DMA_WPROT1 (Bit 0)                                    */
15476 #define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Msk (0xffffffffUL)  /*!< DMA_WPROT1 (Bitfield-Mask: 0xffffffff)                */
15477 /* ==================================================  DMASRAMREADPROTECT0  ================================================== */
15478 #define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Pos (0UL)            /*!< DMA_RPROT0 (Bit 0)                                    */
15479 #define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Msk (0xffffffffUL)   /*!< DMA_RPROT0 (Bitfield-Mask: 0xffffffff)                */
15480 /* ==================================================  DMASRAMREADPROTECT1  ================================================== */
15481 #define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Pos (0UL)            /*!< DMA_RPROT1 (Bit 0)                                    */
15482 #define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Msk (0xffffffffUL)   /*!< DMA_RPROT1 (Bitfield-Mask: 0xffffffff)                */
15483 /* ==================================================  DMASRAMREADPROTECT2  ================================================== */
15484 #define MCUCTRL_DMASRAMREADPROTECT2_DMA_RPROT2_Pos (0UL)            /*!< DMA_RPROT2 (Bit 0)                                    */
15485 #define MCUCTRL_DMASRAMREADPROTECT2_DMA_RPROT2_Msk (0xffffffffUL)   /*!< DMA_RPROT2 (Bitfield-Mask: 0xffffffff)                */
15486 
15487 
15488 /* =========================================================================================================================== */
15489 /* ================                                           MSPI0                                           ================ */
15490 /* =========================================================================================================================== */
15491 
15492 /* =========================================================  CTRL  ========================================================== */
15493 #define MSPI0_CTRL_XFERBYTES_Pos          (16UL)                    /*!< XFERBYTES (Bit 16)                                    */
15494 #define MSPI0_CTRL_XFERBYTES_Msk          (0xffff0000UL)            /*!< XFERBYTES (Bitfield-Mask: 0xffff)                     */
15495 #define MSPI0_CTRL_ENDCX_Pos              (12UL)                    /*!< ENDCX (Bit 12)                                        */
15496 #define MSPI0_CTRL_ENDCX_Msk              (0x1000UL)                /*!< ENDCX (Bitfield-Mask: 0x01)                           */
15497 #define MSPI0_CTRL_PIOSCRAMBLE_Pos        (11UL)                    /*!< PIOSCRAMBLE (Bit 11)                                  */
15498 #define MSPI0_CTRL_PIOSCRAMBLE_Msk        (0x800UL)                 /*!< PIOSCRAMBLE (Bitfield-Mask: 0x01)                     */
15499 #define MSPI0_CTRL_TXRX_Pos               (10UL)                    /*!< TXRX (Bit 10)                                         */
15500 #define MSPI0_CTRL_TXRX_Msk               (0x400UL)                 /*!< TXRX (Bitfield-Mask: 0x01)                            */
15501 #define MSPI0_CTRL_SENDI_Pos              (9UL)                     /*!< SENDI (Bit 9)                                         */
15502 #define MSPI0_CTRL_SENDI_Msk              (0x200UL)                 /*!< SENDI (Bitfield-Mask: 0x01)                           */
15503 #define MSPI0_CTRL_SENDA_Pos              (8UL)                     /*!< SENDA (Bit 8)                                         */
15504 #define MSPI0_CTRL_SENDA_Msk              (0x100UL)                 /*!< SENDA (Bitfield-Mask: 0x01)                           */
15505 #define MSPI0_CTRL_ENTURN_Pos             (7UL)                     /*!< ENTURN (Bit 7)                                        */
15506 #define MSPI0_CTRL_ENTURN_Msk             (0x80UL)                  /*!< ENTURN (Bitfield-Mask: 0x01)                          */
15507 #define MSPI0_CTRL_BIGENDIAN_Pos          (6UL)                     /*!< BIGENDIAN (Bit 6)                                     */
15508 #define MSPI0_CTRL_BIGENDIAN_Msk          (0x40UL)                  /*!< BIGENDIAN (Bitfield-Mask: 0x01)                       */
15509 #define MSPI0_CTRL_CONT_Pos               (5UL)                     /*!< CONT (Bit 5)                                          */
15510 #define MSPI0_CTRL_CONT_Msk               (0x20UL)                  /*!< CONT (Bitfield-Mask: 0x01)                            */
15511 #define MSPI0_CTRL_ENWLAT_Pos             (4UL)                     /*!< ENWLAT (Bit 4)                                        */
15512 #define MSPI0_CTRL_ENWLAT_Msk             (0x10UL)                  /*!< ENWLAT (Bitfield-Mask: 0x01)                          */
15513 #define MSPI0_CTRL_QUADCMD_Pos            (3UL)                     /*!< QUADCMD (Bit 3)                                       */
15514 #define MSPI0_CTRL_QUADCMD_Msk            (0x8UL)                   /*!< QUADCMD (Bitfield-Mask: 0x01)                         */
15515 #define MSPI0_CTRL_BUSY_Pos               (2UL)                     /*!< BUSY (Bit 2)                                          */
15516 #define MSPI0_CTRL_BUSY_Msk               (0x4UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
15517 #define MSPI0_CTRL_STATUS_Pos             (1UL)                     /*!< STATUS (Bit 1)                                        */
15518 #define MSPI0_CTRL_STATUS_Msk             (0x2UL)                   /*!< STATUS (Bitfield-Mask: 0x01)                          */
15519 #define MSPI0_CTRL_START_Pos              (0UL)                     /*!< START (Bit 0)                                         */
15520 #define MSPI0_CTRL_START_Msk              (0x1UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
15521 /* ==========================================================  CFG  ========================================================== */
15522 #define MSPI0_CFG_WRITELATENCY_Pos        (20UL)                    /*!< WRITELATENCY (Bit 20)                                 */
15523 #define MSPI0_CFG_WRITELATENCY_Msk        (0x3f00000UL)             /*!< WRITELATENCY (Bitfield-Mask: 0x3f)                    */
15524 #define MSPI0_CFG_CPOL_Pos                (17UL)                    /*!< CPOL (Bit 17)                                         */
15525 #define MSPI0_CFG_CPOL_Msk                (0x20000UL)               /*!< CPOL (Bitfield-Mask: 0x01)                            */
15526 #define MSPI0_CFG_CPHA_Pos                (16UL)                    /*!< CPHA (Bit 16)                                         */
15527 #define MSPI0_CFG_CPHA_Msk                (0x10000UL)               /*!< CPHA (Bitfield-Mask: 0x01)                            */
15528 #define MSPI0_CFG_TURNAROUND_Pos          (8UL)                     /*!< TURNAROUND (Bit 8)                                    */
15529 #define MSPI0_CFG_TURNAROUND_Msk          (0x3f00UL)                /*!< TURNAROUND (Bitfield-Mask: 0x3f)                      */
15530 #define MSPI0_CFG_SEPIO_Pos               (7UL)                     /*!< SEPIO (Bit 7)                                         */
15531 #define MSPI0_CFG_SEPIO_Msk               (0x80UL)                  /*!< SEPIO (Bitfield-Mask: 0x01)                           */
15532 #define MSPI0_CFG_ISIZE_Pos               (6UL)                     /*!< ISIZE (Bit 6)                                         */
15533 #define MSPI0_CFG_ISIZE_Msk               (0x40UL)                  /*!< ISIZE (Bitfield-Mask: 0x01)                           */
15534 #define MSPI0_CFG_ASIZE_Pos               (4UL)                     /*!< ASIZE (Bit 4)                                         */
15535 #define MSPI0_CFG_ASIZE_Msk               (0x30UL)                  /*!< ASIZE (Bitfield-Mask: 0x03)                           */
15536 #define MSPI0_CFG_DEVCFG_Pos              (0UL)                     /*!< DEVCFG (Bit 0)                                        */
15537 #define MSPI0_CFG_DEVCFG_Msk              (0xfUL)                   /*!< DEVCFG (Bitfield-Mask: 0x0f)                          */
15538 /* =========================================================  ADDR  ========================================================== */
15539 #define MSPI0_ADDR_ADDR_Pos               (0UL)                     /*!< ADDR (Bit 0)                                          */
15540 #define MSPI0_ADDR_ADDR_Msk               (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
15541 /* =========================================================  INSTR  ========================================================= */
15542 #define MSPI0_INSTR_INSTR_Pos             (0UL)                     /*!< INSTR (Bit 0)                                         */
15543 #define MSPI0_INSTR_INSTR_Msk             (0xffffUL)                /*!< INSTR (Bitfield-Mask: 0xffff)                         */
15544 /* ========================================================  TXFIFO  ========================================================= */
15545 #define MSPI0_TXFIFO_TXFIFO_Pos           (0UL)                     /*!< TXFIFO (Bit 0)                                        */
15546 #define MSPI0_TXFIFO_TXFIFO_Msk           (0xffffffffUL)            /*!< TXFIFO (Bitfield-Mask: 0xffffffff)                    */
15547 /* ========================================================  RXFIFO  ========================================================= */
15548 #define MSPI0_RXFIFO_RXFIFO_Pos           (0UL)                     /*!< RXFIFO (Bit 0)                                        */
15549 #define MSPI0_RXFIFO_RXFIFO_Msk           (0xffffffffUL)            /*!< RXFIFO (Bitfield-Mask: 0xffffffff)                    */
15550 /* =======================================================  TXENTRIES  ======================================================= */
15551 #define MSPI0_TXENTRIES_TXENTRIES_Pos     (0UL)                     /*!< TXENTRIES (Bit 0)                                     */
15552 #define MSPI0_TXENTRIES_TXENTRIES_Msk     (0x3fUL)                  /*!< TXENTRIES (Bitfield-Mask: 0x3f)                       */
15553 /* =======================================================  RXENTRIES  ======================================================= */
15554 #define MSPI0_RXENTRIES_RXENTRIES_Pos     (0UL)                     /*!< RXENTRIES (Bit 0)                                     */
15555 #define MSPI0_RXENTRIES_RXENTRIES_Msk     (0x3fUL)                  /*!< RXENTRIES (Bitfield-Mask: 0x3f)                       */
15556 /* =======================================================  THRESHOLD  ======================================================= */
15557 #define MSPI0_THRESHOLD_RXTHRESH_Pos      (8UL)                     /*!< RXTHRESH (Bit 8)                                      */
15558 #define MSPI0_THRESHOLD_RXTHRESH_Msk      (0x3f00UL)                /*!< RXTHRESH (Bitfield-Mask: 0x3f)                        */
15559 #define MSPI0_THRESHOLD_TXTHRESH_Pos      (0UL)                     /*!< TXTHRESH (Bit 0)                                      */
15560 #define MSPI0_THRESHOLD_TXTHRESH_Msk      (0x3fUL)                  /*!< TXTHRESH (Bitfield-Mask: 0x3f)                        */
15561 /* ========================================================  MSPICFG  ======================================================== */
15562 #define MSPI0_MSPICFG_PRSTN_Pos           (31UL)                    /*!< PRSTN (Bit 31)                                        */
15563 #define MSPI0_MSPICFG_PRSTN_Msk           (0x80000000UL)            /*!< PRSTN (Bitfield-Mask: 0x01)                           */
15564 #define MSPI0_MSPICFG_IPRSTN_Pos          (30UL)                    /*!< IPRSTN (Bit 30)                                       */
15565 #define MSPI0_MSPICFG_IPRSTN_Msk          (0x40000000UL)            /*!< IPRSTN (Bitfield-Mask: 0x01)                          */
15566 #define MSPI0_MSPICFG_FIFORESET_Pos       (29UL)                    /*!< FIFORESET (Bit 29)                                    */
15567 #define MSPI0_MSPICFG_FIFORESET_Msk       (0x20000000UL)            /*!< FIFORESET (Bitfield-Mask: 0x01)                       */
15568 #define MSPI0_MSPICFG_CLKDIV_Pos          (8UL)                     /*!< CLKDIV (Bit 8)                                        */
15569 #define MSPI0_MSPICFG_CLKDIV_Msk          (0x3f00UL)                /*!< CLKDIV (Bitfield-Mask: 0x3f)                          */
15570 #define MSPI0_MSPICFG_IOMSEL_Pos          (4UL)                     /*!< IOMSEL (Bit 4)                                        */
15571 #define MSPI0_MSPICFG_IOMSEL_Msk          (0xf0UL)                  /*!< IOMSEL (Bitfield-Mask: 0x0f)                          */
15572 #define MSPI0_MSPICFG_TXNEG_Pos           (3UL)                     /*!< TXNEG (Bit 3)                                         */
15573 #define MSPI0_MSPICFG_TXNEG_Msk           (0x8UL)                   /*!< TXNEG (Bitfield-Mask: 0x01)                           */
15574 #define MSPI0_MSPICFG_RXNEG_Pos           (2UL)                     /*!< RXNEG (Bit 2)                                         */
15575 #define MSPI0_MSPICFG_RXNEG_Msk           (0x4UL)                   /*!< RXNEG (Bitfield-Mask: 0x01)                           */
15576 #define MSPI0_MSPICFG_RXCAP_Pos           (1UL)                     /*!< RXCAP (Bit 1)                                         */
15577 #define MSPI0_MSPICFG_RXCAP_Msk           (0x2UL)                   /*!< RXCAP (Bitfield-Mask: 0x01)                           */
15578 #define MSPI0_MSPICFG_APBCLK_Pos          (0UL)                     /*!< APBCLK (Bit 0)                                        */
15579 #define MSPI0_MSPICFG_APBCLK_Msk          (0x1UL)                   /*!< APBCLK (Bitfield-Mask: 0x01)                          */
15580 /* ========================================================  MSPIDDR  ======================================================== */
15581 #define MSPI0_MSPIDDR_TXDQSDELAY_Pos      (16UL)                    /*!< TXDQSDELAY (Bit 16)                                   */
15582 #define MSPI0_MSPIDDR_TXDQSDELAY_Msk      (0x1f0000UL)              /*!< TXDQSDELAY (Bitfield-Mask: 0x1f)                      */
15583 #define MSPI0_MSPIDDR_RXDQSDELAY_Pos      (8UL)                     /*!< RXDQSDELAY (Bit 8)                                    */
15584 #define MSPI0_MSPIDDR_RXDQSDELAY_Msk      (0x1f00UL)                /*!< RXDQSDELAY (Bitfield-Mask: 0x1f)                      */
15585 #define MSPI0_MSPIDDR_ENABLEFINEDELAY_Pos (6UL)                     /*!< ENABLEFINEDELAY (Bit 6)                               */
15586 #define MSPI0_MSPIDDR_ENABLEFINEDELAY_Msk (0x40UL)                  /*!< ENABLEFINEDELAY (Bitfield-Mask: 0x01)                 */
15587 #define MSPI0_MSPIDDR_OVERRIDEDDRCLKOUTDELAY_Pos (5UL)              /*!< OVERRIDEDDRCLKOUTDELAY (Bit 5)                        */
15588 #define MSPI0_MSPIDDR_OVERRIDEDDRCLKOUTDELAY_Msk (0x20UL)           /*!< OVERRIDEDDRCLKOUTDELAY (Bitfield-Mask: 0x01)          */
15589 #define MSPI0_MSPIDDR_OVERRIDERXDQSDELAY_Pos (4UL)                  /*!< OVERRIDERXDQSDELAY (Bit 4)                            */
15590 #define MSPI0_MSPIDDR_OVERRIDERXDQSDELAY_Msk (0x10UL)               /*!< OVERRIDERXDQSDELAY (Bitfield-Mask: 0x01)              */
15591 #define MSPI0_MSPIDDR_DQSSYNCNEG_Pos      (3UL)                     /*!< DQSSYNCNEG (Bit 3)                                    */
15592 #define MSPI0_MSPIDDR_DQSSYNCNEG_Msk      (0x8UL)                   /*!< DQSSYNCNEG (Bitfield-Mask: 0x01)                      */
15593 #define MSPI0_MSPIDDR_ENABLEDQS_Pos       (2UL)                     /*!< ENABLEDQS (Bit 2)                                     */
15594 #define MSPI0_MSPIDDR_ENABLEDQS_Msk       (0x4UL)                   /*!< ENABLEDQS (Bitfield-Mask: 0x01)                       */
15595 #define MSPI0_MSPIDDR_QUADDDR_Pos         (1UL)                     /*!< QUADDDR (Bit 1)                                       */
15596 #define MSPI0_MSPIDDR_QUADDDR_Msk         (0x2UL)                   /*!< QUADDDR (Bitfield-Mask: 0x01)                         */
15597 #define MSPI0_MSPIDDR_EMULATEDDR_Pos      (0UL)                     /*!< EMULATEDDR (Bit 0)                                    */
15598 #define MSPI0_MSPIDDR_EMULATEDDR_Msk      (0x1UL)                   /*!< EMULATEDDR (Bitfield-Mask: 0x01)                      */
15599 /* ========================================================  PADCFG  ========================================================= */
15600 #define MSPI0_PADCFG_REVCS_Pos            (21UL)                    /*!< REVCS (Bit 21)                                        */
15601 #define MSPI0_PADCFG_REVCS_Msk            (0x200000UL)              /*!< REVCS (Bitfield-Mask: 0x01)                           */
15602 #define MSPI0_PADCFG_IN3_Pos              (20UL)                    /*!< IN3 (Bit 20)                                          */
15603 #define MSPI0_PADCFG_IN3_Msk              (0x100000UL)              /*!< IN3 (Bitfield-Mask: 0x01)                             */
15604 #define MSPI0_PADCFG_IN2_Pos              (19UL)                    /*!< IN2 (Bit 19)                                          */
15605 #define MSPI0_PADCFG_IN2_Msk              (0x80000UL)               /*!< IN2 (Bitfield-Mask: 0x01)                             */
15606 #define MSPI0_PADCFG_IN1_Pos              (18UL)                    /*!< IN1 (Bit 18)                                          */
15607 #define MSPI0_PADCFG_IN1_Msk              (0x40000UL)               /*!< IN1 (Bitfield-Mask: 0x01)                             */
15608 #define MSPI0_PADCFG_IN0_Pos              (16UL)                    /*!< IN0 (Bit 16)                                          */
15609 #define MSPI0_PADCFG_IN0_Msk              (0x30000UL)               /*!< IN0 (Bitfield-Mask: 0x03)                             */
15610 #define MSPI0_PADCFG_OUT7_Pos             (4UL)                     /*!< OUT7 (Bit 4)                                          */
15611 #define MSPI0_PADCFG_OUT7_Msk             (0x10UL)                  /*!< OUT7 (Bitfield-Mask: 0x01)                            */
15612 #define MSPI0_PADCFG_OUT6_Pos             (3UL)                     /*!< OUT6 (Bit 3)                                          */
15613 #define MSPI0_PADCFG_OUT6_Msk             (0x8UL)                   /*!< OUT6 (Bitfield-Mask: 0x01)                            */
15614 #define MSPI0_PADCFG_OUT5_Pos             (2UL)                     /*!< OUT5 (Bit 2)                                          */
15615 #define MSPI0_PADCFG_OUT5_Msk             (0x4UL)                   /*!< OUT5 (Bitfield-Mask: 0x01)                            */
15616 #define MSPI0_PADCFG_OUT4_Pos             (1UL)                     /*!< OUT4 (Bit 1)                                          */
15617 #define MSPI0_PADCFG_OUT4_Msk             (0x2UL)                   /*!< OUT4 (Bitfield-Mask: 0x01)                            */
15618 #define MSPI0_PADCFG_OUT3_Pos             (0UL)                     /*!< OUT3 (Bit 0)                                          */
15619 #define MSPI0_PADCFG_OUT3_Msk             (0x1UL)                   /*!< OUT3 (Bitfield-Mask: 0x01)                            */
15620 /* =======================================================  PADOUTEN  ======================================================== */
15621 #define MSPI0_PADOUTEN_OUTEN_Pos          (0UL)                     /*!< OUTEN (Bit 0)                                         */
15622 #define MSPI0_PADOUTEN_OUTEN_Msk          (0x3ffUL)                 /*!< OUTEN (Bitfield-Mask: 0x3ff)                          */
15623 /* =======================================================  PADOVEREN  ======================================================= */
15624 #define MSPI0_PADOVEREN_OVERRIDEEN_Pos    (0UL)                     /*!< OVERRIDEEN (Bit 0)                                    */
15625 #define MSPI0_PADOVEREN_OVERRIDEEN_Msk    (0x3ffUL)                 /*!< OVERRIDEEN (Bitfield-Mask: 0x3ff)                     */
15626 /* ========================================================  PADOVER  ======================================================== */
15627 #define MSPI0_PADOVER_OVERRIDE_Pos        (0UL)                     /*!< OVERRIDE (Bit 0)                                      */
15628 #define MSPI0_PADOVER_OVERRIDE_Msk        (0x3ffUL)                 /*!< OVERRIDE (Bitfield-Mask: 0x3ff)                       */
15629 /* =========================================================  FLASH  ========================================================= */
15630 #define MSPI0_FLASH_XIPENWLAT_Pos         (11UL)                    /*!< XIPENWLAT (Bit 11)                                    */
15631 #define MSPI0_FLASH_XIPENWLAT_Msk         (0x800UL)                 /*!< XIPENWLAT (Bitfield-Mask: 0x01)                       */
15632 #define MSPI0_FLASH_XIPMIXED_Pos          (8UL)                     /*!< XIPMIXED (Bit 8)                                      */
15633 #define MSPI0_FLASH_XIPMIXED_Msk          (0x700UL)                 /*!< XIPMIXED (Bitfield-Mask: 0x07)                        */
15634 #define MSPI0_FLASH_XIPSENDI_Pos          (7UL)                     /*!< XIPSENDI (Bit 7)                                      */
15635 #define MSPI0_FLASH_XIPSENDI_Msk          (0x80UL)                  /*!< XIPSENDI (Bitfield-Mask: 0x01)                        */
15636 #define MSPI0_FLASH_XIPSENDA_Pos          (6UL)                     /*!< XIPSENDA (Bit 6)                                      */
15637 #define MSPI0_FLASH_XIPSENDA_Msk          (0x40UL)                  /*!< XIPSENDA (Bitfield-Mask: 0x01)                        */
15638 #define MSPI0_FLASH_XIPENTURN_Pos         (5UL)                     /*!< XIPENTURN (Bit 5)                                     */
15639 #define MSPI0_FLASH_XIPENTURN_Msk         (0x20UL)                  /*!< XIPENTURN (Bitfield-Mask: 0x01)                       */
15640 #define MSPI0_FLASH_XIPBIGENDIAN_Pos      (4UL)                     /*!< XIPBIGENDIAN (Bit 4)                                  */
15641 #define MSPI0_FLASH_XIPBIGENDIAN_Msk      (0x10UL)                  /*!< XIPBIGENDIAN (Bitfield-Mask: 0x01)                    */
15642 #define MSPI0_FLASH_XIPACK_Pos            (2UL)                     /*!< XIPACK (Bit 2)                                        */
15643 #define MSPI0_FLASH_XIPACK_Msk            (0xcUL)                   /*!< XIPACK (Bitfield-Mask: 0x03)                          */
15644 #define MSPI0_FLASH_XIPENDCX_Pos          (1UL)                     /*!< XIPENDCX (Bit 1)                                      */
15645 #define MSPI0_FLASH_XIPENDCX_Msk          (0x2UL)                   /*!< XIPENDCX (Bitfield-Mask: 0x01)                        */
15646 #define MSPI0_FLASH_XIPEN_Pos             (0UL)                     /*!< XIPEN (Bit 0)                                         */
15647 #define MSPI0_FLASH_XIPEN_Msk             (0x1UL)                   /*!< XIPEN (Bitfield-Mask: 0x01)                           */
15648 /* =======================================================  XIPINSTR  ======================================================== */
15649 #define MSPI0_XIPINSTR_READINSTR_Pos      (16UL)                    /*!< READINSTR (Bit 16)                                    */
15650 #define MSPI0_XIPINSTR_READINSTR_Msk      (0xffff0000UL)            /*!< READINSTR (Bitfield-Mask: 0xffff)                     */
15651 #define MSPI0_XIPINSTR_WRITEINSTR_Pos     (0UL)                     /*!< WRITEINSTR (Bit 0)                                    */
15652 #define MSPI0_XIPINSTR_WRITEINSTR_Msk     (0xffffUL)                /*!< WRITEINSTR (Bitfield-Mask: 0xffff)                    */
15653 /* ======================================================  SCRAMBLING  ======================================================= */
15654 #define MSPI0_SCRAMBLING_SCRENABLE_Pos    (31UL)                    /*!< SCRENABLE (Bit 31)                                    */
15655 #define MSPI0_SCRAMBLING_SCRENABLE_Msk    (0x80000000UL)            /*!< SCRENABLE (Bitfield-Mask: 0x01)                       */
15656 #define MSPI0_SCRAMBLING_SCREND_Pos       (16UL)                    /*!< SCREND (Bit 16)                                       */
15657 #define MSPI0_SCRAMBLING_SCREND_Msk       (0x3ff0000UL)             /*!< SCREND (Bitfield-Mask: 0x3ff)                         */
15658 #define MSPI0_SCRAMBLING_SCRSTART_Pos     (0UL)                     /*!< SCRSTART (Bit 0)                                      */
15659 #define MSPI0_SCRAMBLING_SCRSTART_Msk     (0x3ffUL)                 /*!< SCRSTART (Bitfield-Mask: 0x3ff)                       */
15660 /* =========================================================  INTEN  ========================================================= */
15661 #define MSPI0_INTEN_SCRERR_Pos            (12UL)                    /*!< SCRERR (Bit 12)                                       */
15662 #define MSPI0_INTEN_SCRERR_Msk            (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
15663 #define MSPI0_INTEN_CQERR_Pos             (11UL)                    /*!< CQERR (Bit 11)                                        */
15664 #define MSPI0_INTEN_CQERR_Msk             (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
15665 #define MSPI0_INTEN_CQPAUSED_Pos          (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
15666 #define MSPI0_INTEN_CQPAUSED_Msk          (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
15667 #define MSPI0_INTEN_CQUPD_Pos             (9UL)                     /*!< CQUPD (Bit 9)                                         */
15668 #define MSPI0_INTEN_CQUPD_Msk             (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
15669 #define MSPI0_INTEN_CQCMP_Pos             (8UL)                     /*!< CQCMP (Bit 8)                                         */
15670 #define MSPI0_INTEN_CQCMP_Msk             (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
15671 #define MSPI0_INTEN_DERR_Pos              (7UL)                     /*!< DERR (Bit 7)                                          */
15672 #define MSPI0_INTEN_DERR_Msk              (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
15673 #define MSPI0_INTEN_DCMP_Pos              (6UL)                     /*!< DCMP (Bit 6)                                          */
15674 #define MSPI0_INTEN_DCMP_Msk              (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
15675 #define MSPI0_INTEN_RXF_Pos               (5UL)                     /*!< RXF (Bit 5)                                           */
15676 #define MSPI0_INTEN_RXF_Msk               (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
15677 #define MSPI0_INTEN_RXO_Pos               (4UL)                     /*!< RXO (Bit 4)                                           */
15678 #define MSPI0_INTEN_RXO_Msk               (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
15679 #define MSPI0_INTEN_RXU_Pos               (3UL)                     /*!< RXU (Bit 3)                                           */
15680 #define MSPI0_INTEN_RXU_Msk               (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
15681 #define MSPI0_INTEN_TXO_Pos               (2UL)                     /*!< TXO (Bit 2)                                           */
15682 #define MSPI0_INTEN_TXO_Msk               (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
15683 #define MSPI0_INTEN_TXE_Pos               (1UL)                     /*!< TXE (Bit 1)                                           */
15684 #define MSPI0_INTEN_TXE_Msk               (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
15685 #define MSPI0_INTEN_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
15686 #define MSPI0_INTEN_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
15687 /* ========================================================  INTSTAT  ======================================================== */
15688 #define MSPI0_INTSTAT_SCRERR_Pos          (12UL)                    /*!< SCRERR (Bit 12)                                       */
15689 #define MSPI0_INTSTAT_SCRERR_Msk          (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
15690 #define MSPI0_INTSTAT_CQERR_Pos           (11UL)                    /*!< CQERR (Bit 11)                                        */
15691 #define MSPI0_INTSTAT_CQERR_Msk           (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
15692 #define MSPI0_INTSTAT_CQPAUSED_Pos        (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
15693 #define MSPI0_INTSTAT_CQPAUSED_Msk        (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
15694 #define MSPI0_INTSTAT_CQUPD_Pos           (9UL)                     /*!< CQUPD (Bit 9)                                         */
15695 #define MSPI0_INTSTAT_CQUPD_Msk           (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
15696 #define MSPI0_INTSTAT_CQCMP_Pos           (8UL)                     /*!< CQCMP (Bit 8)                                         */
15697 #define MSPI0_INTSTAT_CQCMP_Msk           (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
15698 #define MSPI0_INTSTAT_DERR_Pos            (7UL)                     /*!< DERR (Bit 7)                                          */
15699 #define MSPI0_INTSTAT_DERR_Msk            (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
15700 #define MSPI0_INTSTAT_DCMP_Pos            (6UL)                     /*!< DCMP (Bit 6)                                          */
15701 #define MSPI0_INTSTAT_DCMP_Msk            (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
15702 #define MSPI0_INTSTAT_RXF_Pos             (5UL)                     /*!< RXF (Bit 5)                                           */
15703 #define MSPI0_INTSTAT_RXF_Msk             (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
15704 #define MSPI0_INTSTAT_RXO_Pos             (4UL)                     /*!< RXO (Bit 4)                                           */
15705 #define MSPI0_INTSTAT_RXO_Msk             (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
15706 #define MSPI0_INTSTAT_RXU_Pos             (3UL)                     /*!< RXU (Bit 3)                                           */
15707 #define MSPI0_INTSTAT_RXU_Msk             (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
15708 #define MSPI0_INTSTAT_TXO_Pos             (2UL)                     /*!< TXO (Bit 2)                                           */
15709 #define MSPI0_INTSTAT_TXO_Msk             (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
15710 #define MSPI0_INTSTAT_TXE_Pos             (1UL)                     /*!< TXE (Bit 1)                                           */
15711 #define MSPI0_INTSTAT_TXE_Msk             (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
15712 #define MSPI0_INTSTAT_CMDCMP_Pos          (0UL)                     /*!< CMDCMP (Bit 0)                                        */
15713 #define MSPI0_INTSTAT_CMDCMP_Msk          (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
15714 /* ========================================================  INTCLR  ========================================================= */
15715 #define MSPI0_INTCLR_SCRERR_Pos           (12UL)                    /*!< SCRERR (Bit 12)                                       */
15716 #define MSPI0_INTCLR_SCRERR_Msk           (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
15717 #define MSPI0_INTCLR_CQERR_Pos            (11UL)                    /*!< CQERR (Bit 11)                                        */
15718 #define MSPI0_INTCLR_CQERR_Msk            (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
15719 #define MSPI0_INTCLR_CQPAUSED_Pos         (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
15720 #define MSPI0_INTCLR_CQPAUSED_Msk         (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
15721 #define MSPI0_INTCLR_CQUPD_Pos            (9UL)                     /*!< CQUPD (Bit 9)                                         */
15722 #define MSPI0_INTCLR_CQUPD_Msk            (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
15723 #define MSPI0_INTCLR_CQCMP_Pos            (8UL)                     /*!< CQCMP (Bit 8)                                         */
15724 #define MSPI0_INTCLR_CQCMP_Msk            (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
15725 #define MSPI0_INTCLR_DERR_Pos             (7UL)                     /*!< DERR (Bit 7)                                          */
15726 #define MSPI0_INTCLR_DERR_Msk             (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
15727 #define MSPI0_INTCLR_DCMP_Pos             (6UL)                     /*!< DCMP (Bit 6)                                          */
15728 #define MSPI0_INTCLR_DCMP_Msk             (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
15729 #define MSPI0_INTCLR_RXF_Pos              (5UL)                     /*!< RXF (Bit 5)                                           */
15730 #define MSPI0_INTCLR_RXF_Msk              (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
15731 #define MSPI0_INTCLR_RXO_Pos              (4UL)                     /*!< RXO (Bit 4)                                           */
15732 #define MSPI0_INTCLR_RXO_Msk              (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
15733 #define MSPI0_INTCLR_RXU_Pos              (3UL)                     /*!< RXU (Bit 3)                                           */
15734 #define MSPI0_INTCLR_RXU_Msk              (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
15735 #define MSPI0_INTCLR_TXO_Pos              (2UL)                     /*!< TXO (Bit 2)                                           */
15736 #define MSPI0_INTCLR_TXO_Msk              (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
15737 #define MSPI0_INTCLR_TXE_Pos              (1UL)                     /*!< TXE (Bit 1)                                           */
15738 #define MSPI0_INTCLR_TXE_Msk              (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
15739 #define MSPI0_INTCLR_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
15740 #define MSPI0_INTCLR_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
15741 /* ========================================================  INTSET  ========================================================= */
15742 #define MSPI0_INTSET_SCRERR_Pos           (12UL)                    /*!< SCRERR (Bit 12)                                       */
15743 #define MSPI0_INTSET_SCRERR_Msk           (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
15744 #define MSPI0_INTSET_CQERR_Pos            (11UL)                    /*!< CQERR (Bit 11)                                        */
15745 #define MSPI0_INTSET_CQERR_Msk            (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
15746 #define MSPI0_INTSET_CQPAUSED_Pos         (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
15747 #define MSPI0_INTSET_CQPAUSED_Msk         (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
15748 #define MSPI0_INTSET_CQUPD_Pos            (9UL)                     /*!< CQUPD (Bit 9)                                         */
15749 #define MSPI0_INTSET_CQUPD_Msk            (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
15750 #define MSPI0_INTSET_CQCMP_Pos            (8UL)                     /*!< CQCMP (Bit 8)                                         */
15751 #define MSPI0_INTSET_CQCMP_Msk            (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
15752 #define MSPI0_INTSET_DERR_Pos             (7UL)                     /*!< DERR (Bit 7)                                          */
15753 #define MSPI0_INTSET_DERR_Msk             (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
15754 #define MSPI0_INTSET_DCMP_Pos             (6UL)                     /*!< DCMP (Bit 6)                                          */
15755 #define MSPI0_INTSET_DCMP_Msk             (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
15756 #define MSPI0_INTSET_RXF_Pos              (5UL)                     /*!< RXF (Bit 5)                                           */
15757 #define MSPI0_INTSET_RXF_Msk              (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
15758 #define MSPI0_INTSET_RXO_Pos              (4UL)                     /*!< RXO (Bit 4)                                           */
15759 #define MSPI0_INTSET_RXO_Msk              (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
15760 #define MSPI0_INTSET_RXU_Pos              (3UL)                     /*!< RXU (Bit 3)                                           */
15761 #define MSPI0_INTSET_RXU_Msk              (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
15762 #define MSPI0_INTSET_TXO_Pos              (2UL)                     /*!< TXO (Bit 2)                                           */
15763 #define MSPI0_INTSET_TXO_Msk              (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
15764 #define MSPI0_INTSET_TXE_Pos              (1UL)                     /*!< TXE (Bit 1)                                           */
15765 #define MSPI0_INTSET_TXE_Msk              (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
15766 #define MSPI0_INTSET_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
15767 #define MSPI0_INTSET_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
15768 /* ========================================================  DMACFG  ========================================================= */
15769 #define MSPI0_DMACFG_DMAPWROFF_Pos        (18UL)                    /*!< DMAPWROFF (Bit 18)                                    */
15770 #define MSPI0_DMACFG_DMAPWROFF_Msk        (0x40000UL)               /*!< DMAPWROFF (Bitfield-Mask: 0x01)                       */
15771 #define MSPI0_DMACFG_DMAPRI_Pos           (3UL)                     /*!< DMAPRI (Bit 3)                                        */
15772 #define MSPI0_DMACFG_DMAPRI_Msk           (0x18UL)                  /*!< DMAPRI (Bitfield-Mask: 0x03)                          */
15773 #define MSPI0_DMACFG_DMADIR_Pos           (2UL)                     /*!< DMADIR (Bit 2)                                        */
15774 #define MSPI0_DMACFG_DMADIR_Msk           (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
15775 #define MSPI0_DMACFG_DMAEN_Pos            (0UL)                     /*!< DMAEN (Bit 0)                                         */
15776 #define MSPI0_DMACFG_DMAEN_Msk            (0x3UL)                   /*!< DMAEN (Bitfield-Mask: 0x03)                           */
15777 /* ========================================================  DMASTAT  ======================================================== */
15778 #define MSPI0_DMASTAT_SCRERR_Pos          (3UL)                     /*!< SCRERR (Bit 3)                                        */
15779 #define MSPI0_DMASTAT_SCRERR_Msk          (0x8UL)                   /*!< SCRERR (Bitfield-Mask: 0x01)                          */
15780 #define MSPI0_DMASTAT_DMAERR_Pos          (2UL)                     /*!< DMAERR (Bit 2)                                        */
15781 #define MSPI0_DMASTAT_DMAERR_Msk          (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
15782 #define MSPI0_DMASTAT_DMACPL_Pos          (1UL)                     /*!< DMACPL (Bit 1)                                        */
15783 #define MSPI0_DMASTAT_DMACPL_Msk          (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
15784 #define MSPI0_DMASTAT_DMATIP_Pos          (0UL)                     /*!< DMATIP (Bit 0)                                        */
15785 #define MSPI0_DMASTAT_DMATIP_Msk          (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
15786 /* ======================================================  DMATARGADDR  ====================================================== */
15787 #define MSPI0_DMATARGADDR_TARGADDR_Pos    (0UL)                     /*!< TARGADDR (Bit 0)                                      */
15788 #define MSPI0_DMATARGADDR_TARGADDR_Msk    (0xffffffffUL)            /*!< TARGADDR (Bitfield-Mask: 0xffffffff)                  */
15789 /* ======================================================  DMADEVADDR  ======================================================= */
15790 #define MSPI0_DMADEVADDR_DEVADDR_Pos      (0UL)                     /*!< DEVADDR (Bit 0)                                       */
15791 #define MSPI0_DMADEVADDR_DEVADDR_Msk      (0xffffffffUL)            /*!< DEVADDR (Bitfield-Mask: 0xffffffff)                   */
15792 /* ======================================================  DMATOTCOUNT  ====================================================== */
15793 #define MSPI0_DMATOTCOUNT_TOTCOUNT_Pos    (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
15794 #define MSPI0_DMATOTCOUNT_TOTCOUNT_Msk    (0xffffffUL)              /*!< TOTCOUNT (Bitfield-Mask: 0xffffff)                    */
15795 /* =======================================================  DMABCOUNT  ======================================================= */
15796 #define MSPI0_DMABCOUNT_BCOUNT_Pos        (0UL)                     /*!< BCOUNT (Bit 0)                                        */
15797 #define MSPI0_DMABCOUNT_BCOUNT_Msk        (0xffUL)                  /*!< BCOUNT (Bitfield-Mask: 0xff)                          */
15798 /* =======================================================  DMATHRESH  ======================================================= */
15799 #define MSPI0_DMATHRESH_DMARXTHRESH_Pos   (8UL)                     /*!< DMARXTHRESH (Bit 8)                                   */
15800 #define MSPI0_DMATHRESH_DMARXTHRESH_Msk   (0x1f00UL)                /*!< DMARXTHRESH (Bitfield-Mask: 0x1f)                     */
15801 #define MSPI0_DMATHRESH_DMATXTHRESH_Pos   (0UL)                     /*!< DMATXTHRESH (Bit 0)                                   */
15802 #define MSPI0_DMATHRESH_DMATXTHRESH_Msk   (0x1fUL)                  /*!< DMATXTHRESH (Bitfield-Mask: 0x1f)                     */
15803 /* ======================================================  DMABOUNDARY  ====================================================== */
15804 #define MSPI0_DMABOUNDARY_DMABOUND_Pos    (12UL)                    /*!< DMABOUND (Bit 12)                                     */
15805 #define MSPI0_DMABOUNDARY_DMABOUND_Msk    (0xf000UL)                /*!< DMABOUND (Bitfield-Mask: 0x0f)                        */
15806 #define MSPI0_DMABOUNDARY_DMATIMELIMIT_Pos (0UL)                    /*!< DMATIMELIMIT (Bit 0)                                  */
15807 #define MSPI0_DMABOUNDARY_DMATIMELIMIT_Msk (0xfffUL)                /*!< DMATIMELIMIT (Bitfield-Mask: 0xfff)                   */
15808 /* =========================================================  CQCFG  ========================================================= */
15809 #define MSPI0_CQCFG_CQAUTOCLEARMASK_Pos   (3UL)                     /*!< CQAUTOCLEARMASK (Bit 3)                               */
15810 #define MSPI0_CQCFG_CQAUTOCLEARMASK_Msk   (0x8UL)                   /*!< CQAUTOCLEARMASK (Bitfield-Mask: 0x01)                 */
15811 #define MSPI0_CQCFG_CQPWROFF_Pos          (2UL)                     /*!< CQPWROFF (Bit 2)                                      */
15812 #define MSPI0_CQCFG_CQPWROFF_Msk          (0x4UL)                   /*!< CQPWROFF (Bitfield-Mask: 0x01)                        */
15813 #define MSPI0_CQCFG_CQPRI_Pos             (1UL)                     /*!< CQPRI (Bit 1)                                         */
15814 #define MSPI0_CQCFG_CQPRI_Msk             (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
15815 #define MSPI0_CQCFG_CQEN_Pos              (0UL)                     /*!< CQEN (Bit 0)                                          */
15816 #define MSPI0_CQCFG_CQEN_Msk              (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
15817 /* ========================================================  CQADDR  ========================================================= */
15818 #define MSPI0_CQADDR_CQADDR_Pos           (0UL)                     /*!< CQADDR (Bit 0)                                        */
15819 #define MSPI0_CQADDR_CQADDR_Msk           (0x1fffffffUL)            /*!< CQADDR (Bitfield-Mask: 0x1fffffff)                    */
15820 /* ========================================================  CQSTAT  ========================================================= */
15821 #define MSPI0_CQSTAT_CQPAUSED_Pos         (3UL)                     /*!< CQPAUSED (Bit 3)                                      */
15822 #define MSPI0_CQSTAT_CQPAUSED_Msk         (0x8UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
15823 #define MSPI0_CQSTAT_CQERR_Pos            (2UL)                     /*!< CQERR (Bit 2)                                         */
15824 #define MSPI0_CQSTAT_CQERR_Msk            (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
15825 #define MSPI0_CQSTAT_CQCPL_Pos            (1UL)                     /*!< CQCPL (Bit 1)                                         */
15826 #define MSPI0_CQSTAT_CQCPL_Msk            (0x2UL)                   /*!< CQCPL (Bitfield-Mask: 0x01)                           */
15827 #define MSPI0_CQSTAT_CQTIP_Pos            (0UL)                     /*!< CQTIP (Bit 0)                                         */
15828 #define MSPI0_CQSTAT_CQTIP_Msk            (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
15829 /* ========================================================  CQFLAGS  ======================================================== */
15830 #define MSPI0_CQFLAGS_CQFLAGS_Pos         (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
15831 #define MSPI0_CQFLAGS_CQFLAGS_Msk         (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
15832 /* ======================================================  CQSETCLEAR  ======================================================= */
15833 #define MSPI0_CQSETCLEAR_CQFCLR_Pos       (16UL)                    /*!< CQFCLR (Bit 16)                                       */
15834 #define MSPI0_CQSETCLEAR_CQFCLR_Msk       (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
15835 #define MSPI0_CQSETCLEAR_CQFTOGGLE_Pos    (8UL)                     /*!< CQFTOGGLE (Bit 8)                                     */
15836 #define MSPI0_CQSETCLEAR_CQFTOGGLE_Msk    (0xff00UL)                /*!< CQFTOGGLE (Bitfield-Mask: 0xff)                       */
15837 #define MSPI0_CQSETCLEAR_CQFSET_Pos       (0UL)                     /*!< CQFSET (Bit 0)                                        */
15838 #define MSPI0_CQSETCLEAR_CQFSET_Msk       (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
15839 /* ========================================================  CQPAUSE  ======================================================== */
15840 #define MSPI0_CQPAUSE_CQMASK_Pos          (0UL)                     /*!< CQMASK (Bit 0)                                        */
15841 #define MSPI0_CQPAUSE_CQMASK_Msk          (0xffffUL)                /*!< CQMASK (Bitfield-Mask: 0xffff)                        */
15842 /* =======================================================  CQCURIDX  ======================================================== */
15843 #define MSPI0_CQCURIDX_CQCURIDX_Pos       (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
15844 #define MSPI0_CQCURIDX_CQCURIDX_Msk       (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
15845 /* =======================================================  CQENDIDX  ======================================================== */
15846 #define MSPI0_CQENDIDX_CQENDIDX_Pos       (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
15847 #define MSPI0_CQENDIDX_CQENDIDX_Msk       (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
15848 
15849 
15850 /* =========================================================================================================================== */
15851 /* ================                                            PDM                                            ================ */
15852 /* =========================================================================================================================== */
15853 
15854 /* =========================================================  PCFG  ========================================================== */
15855 #define PDM_PCFG_LRSWAP_Pos               (31UL)                    /*!< LRSWAP (Bit 31)                                       */
15856 #define PDM_PCFG_LRSWAP_Msk               (0x80000000UL)            /*!< LRSWAP (Bitfield-Mask: 0x01)                          */
15857 #define PDM_PCFG_PGARIGHT_Pos             (26UL)                    /*!< PGARIGHT (Bit 26)                                     */
15858 #define PDM_PCFG_PGARIGHT_Msk             (0x7c000000UL)            /*!< PGARIGHT (Bitfield-Mask: 0x1f)                        */
15859 #define PDM_PCFG_PGALEFT_Pos              (21UL)                    /*!< PGALEFT (Bit 21)                                      */
15860 #define PDM_PCFG_PGALEFT_Msk              (0x3e00000UL)             /*!< PGALEFT (Bitfield-Mask: 0x1f)                         */
15861 #define PDM_PCFG_MCLKDIV_Pos              (17UL)                    /*!< MCLKDIV (Bit 17)                                      */
15862 #define PDM_PCFG_MCLKDIV_Msk              (0x60000UL)               /*!< MCLKDIV (Bitfield-Mask: 0x03)                         */
15863 #define PDM_PCFG_SINCRATE_Pos             (10UL)                    /*!< SINCRATE (Bit 10)                                     */
15864 #define PDM_PCFG_SINCRATE_Msk             (0x1fc00UL)               /*!< SINCRATE (Bitfield-Mask: 0x7f)                        */
15865 #define PDM_PCFG_ADCHPD_Pos               (9UL)                     /*!< ADCHPD (Bit 9)                                        */
15866 #define PDM_PCFG_ADCHPD_Msk               (0x200UL)                 /*!< ADCHPD (Bitfield-Mask: 0x01)                          */
15867 #define PDM_PCFG_HPCUTOFF_Pos             (5UL)                     /*!< HPCUTOFF (Bit 5)                                      */
15868 #define PDM_PCFG_HPCUTOFF_Msk             (0x1e0UL)                 /*!< HPCUTOFF (Bitfield-Mask: 0x0f)                        */
15869 #define PDM_PCFG_CYCLES_Pos               (2UL)                     /*!< CYCLES (Bit 2)                                        */
15870 #define PDM_PCFG_CYCLES_Msk               (0x1cUL)                  /*!< CYCLES (Bitfield-Mask: 0x07)                          */
15871 #define PDM_PCFG_SOFTMUTE_Pos             (1UL)                     /*!< SOFTMUTE (Bit 1)                                      */
15872 #define PDM_PCFG_SOFTMUTE_Msk             (0x2UL)                   /*!< SOFTMUTE (Bitfield-Mask: 0x01)                        */
15873 #define PDM_PCFG_PDMCOREEN_Pos            (0UL)                     /*!< PDMCOREEN (Bit 0)                                     */
15874 #define PDM_PCFG_PDMCOREEN_Msk            (0x1UL)                   /*!< PDMCOREEN (Bitfield-Mask: 0x01)                       */
15875 /* =========================================================  VCFG  ========================================================== */
15876 #define PDM_VCFG_IOCLKEN_Pos              (31UL)                    /*!< IOCLKEN (Bit 31)                                      */
15877 #define PDM_VCFG_IOCLKEN_Msk              (0x80000000UL)            /*!< IOCLKEN (Bitfield-Mask: 0x01)                         */
15878 #define PDM_VCFG_RSTB_Pos                 (30UL)                    /*!< RSTB (Bit 30)                                         */
15879 #define PDM_VCFG_RSTB_Msk                 (0x40000000UL)            /*!< RSTB (Bitfield-Mask: 0x01)                            */
15880 #define PDM_VCFG_PDMCLKSEL_Pos            (27UL)                    /*!< PDMCLKSEL (Bit 27)                                    */
15881 #define PDM_VCFG_PDMCLKSEL_Msk            (0x38000000UL)            /*!< PDMCLKSEL (Bitfield-Mask: 0x07)                       */
15882 #define PDM_VCFG_PDMCLKEN_Pos             (26UL)                    /*!< PDMCLKEN (Bit 26)                                     */
15883 #define PDM_VCFG_PDMCLKEN_Msk             (0x4000000UL)             /*!< PDMCLKEN (Bitfield-Mask: 0x01)                        */
15884 #define PDM_VCFG_I2SEN_Pos                (20UL)                    /*!< I2SEN (Bit 20)                                        */
15885 #define PDM_VCFG_I2SEN_Msk                (0x100000UL)              /*!< I2SEN (Bitfield-Mask: 0x01)                           */
15886 #define PDM_VCFG_BCLKINV_Pos              (19UL)                    /*!< BCLKINV (Bit 19)                                      */
15887 #define PDM_VCFG_BCLKINV_Msk              (0x80000UL)               /*!< BCLKINV (Bitfield-Mask: 0x01)                         */
15888 #define PDM_VCFG_DMICKDEL_Pos             (17UL)                    /*!< DMICKDEL (Bit 17)                                     */
15889 #define PDM_VCFG_DMICKDEL_Msk             (0x20000UL)               /*!< DMICKDEL (Bitfield-Mask: 0x01)                        */
15890 #define PDM_VCFG_SELAP_Pos                (16UL)                    /*!< SELAP (Bit 16)                                        */
15891 #define PDM_VCFG_SELAP_Msk                (0x10000UL)               /*!< SELAP (Bitfield-Mask: 0x01)                           */
15892 #define PDM_VCFG_PCMPACK_Pos              (8UL)                     /*!< PCMPACK (Bit 8)                                       */
15893 #define PDM_VCFG_PCMPACK_Msk              (0x100UL)                 /*!< PCMPACK (Bitfield-Mask: 0x01)                         */
15894 #define PDM_VCFG_CHSET_Pos                (3UL)                     /*!< CHSET (Bit 3)                                         */
15895 #define PDM_VCFG_CHSET_Msk                (0x18UL)                  /*!< CHSET (Bitfield-Mask: 0x03)                           */
15896 /* =======================================================  VOICESTAT  ======================================================= */
15897 #define PDM_VOICESTAT_FIFOCNT_Pos         (0UL)                     /*!< FIFOCNT (Bit 0)                                       */
15898 #define PDM_VOICESTAT_FIFOCNT_Msk         (0x3fUL)                  /*!< FIFOCNT (Bitfield-Mask: 0x3f)                         */
15899 /* =======================================================  FIFOREAD  ======================================================== */
15900 #define PDM_FIFOREAD_FIFOREAD_Pos         (0UL)                     /*!< FIFOREAD (Bit 0)                                      */
15901 #define PDM_FIFOREAD_FIFOREAD_Msk         (0xffffffffUL)            /*!< FIFOREAD (Bitfield-Mask: 0xffffffff)                  */
15902 /* =======================================================  FIFOFLUSH  ======================================================= */
15903 #define PDM_FIFOFLUSH_FIFOFLUSH_Pos       (0UL)                     /*!< FIFOFLUSH (Bit 0)                                     */
15904 #define PDM_FIFOFLUSH_FIFOFLUSH_Msk       (0x1UL)                   /*!< FIFOFLUSH (Bitfield-Mask: 0x01)                       */
15905 /* ========================================================  FIFOTHR  ======================================================== */
15906 #define PDM_FIFOTHR_FIFOTHR_Pos           (0UL)                     /*!< FIFOTHR (Bit 0)                                       */
15907 #define PDM_FIFOTHR_FIFOTHR_Msk           (0x1fUL)                  /*!< FIFOTHR (Bitfield-Mask: 0x1f)                         */
15908 /* =========================================================  INTEN  ========================================================= */
15909 #define PDM_INTEN_DERR_Pos                (4UL)                     /*!< DERR (Bit 4)                                          */
15910 #define PDM_INTEN_DERR_Msk                (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
15911 #define PDM_INTEN_DCMP_Pos                (3UL)                     /*!< DCMP (Bit 3)                                          */
15912 #define PDM_INTEN_DCMP_Msk                (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
15913 #define PDM_INTEN_UNDFL_Pos               (2UL)                     /*!< UNDFL (Bit 2)                                         */
15914 #define PDM_INTEN_UNDFL_Msk               (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
15915 #define PDM_INTEN_OVF_Pos                 (1UL)                     /*!< OVF (Bit 1)                                           */
15916 #define PDM_INTEN_OVF_Msk                 (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
15917 #define PDM_INTEN_THR_Pos                 (0UL)                     /*!< THR (Bit 0)                                           */
15918 #define PDM_INTEN_THR_Msk                 (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
15919 /* ========================================================  INTSTAT  ======================================================== */
15920 #define PDM_INTSTAT_DERR_Pos              (4UL)                     /*!< DERR (Bit 4)                                          */
15921 #define PDM_INTSTAT_DERR_Msk              (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
15922 #define PDM_INTSTAT_DCMP_Pos              (3UL)                     /*!< DCMP (Bit 3)                                          */
15923 #define PDM_INTSTAT_DCMP_Msk              (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
15924 #define PDM_INTSTAT_UNDFL_Pos             (2UL)                     /*!< UNDFL (Bit 2)                                         */
15925 #define PDM_INTSTAT_UNDFL_Msk             (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
15926 #define PDM_INTSTAT_OVF_Pos               (1UL)                     /*!< OVF (Bit 1)                                           */
15927 #define PDM_INTSTAT_OVF_Msk               (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
15928 #define PDM_INTSTAT_THR_Pos               (0UL)                     /*!< THR (Bit 0)                                           */
15929 #define PDM_INTSTAT_THR_Msk               (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
15930 /* ========================================================  INTCLR  ========================================================= */
15931 #define PDM_INTCLR_DERR_Pos               (4UL)                     /*!< DERR (Bit 4)                                          */
15932 #define PDM_INTCLR_DERR_Msk               (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
15933 #define PDM_INTCLR_DCMP_Pos               (3UL)                     /*!< DCMP (Bit 3)                                          */
15934 #define PDM_INTCLR_DCMP_Msk               (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
15935 #define PDM_INTCLR_UNDFL_Pos              (2UL)                     /*!< UNDFL (Bit 2)                                         */
15936 #define PDM_INTCLR_UNDFL_Msk              (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
15937 #define PDM_INTCLR_OVF_Pos                (1UL)                     /*!< OVF (Bit 1)                                           */
15938 #define PDM_INTCLR_OVF_Msk                (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
15939 #define PDM_INTCLR_THR_Pos                (0UL)                     /*!< THR (Bit 0)                                           */
15940 #define PDM_INTCLR_THR_Msk                (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
15941 /* ========================================================  INTSET  ========================================================= */
15942 #define PDM_INTSET_DERR_Pos               (4UL)                     /*!< DERR (Bit 4)                                          */
15943 #define PDM_INTSET_DERR_Msk               (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
15944 #define PDM_INTSET_DCMP_Pos               (3UL)                     /*!< DCMP (Bit 3)                                          */
15945 #define PDM_INTSET_DCMP_Msk               (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
15946 #define PDM_INTSET_UNDFL_Pos              (2UL)                     /*!< UNDFL (Bit 2)                                         */
15947 #define PDM_INTSET_UNDFL_Msk              (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
15948 #define PDM_INTSET_OVF_Pos                (1UL)                     /*!< OVF (Bit 1)                                           */
15949 #define PDM_INTSET_OVF_Msk                (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
15950 #define PDM_INTSET_THR_Pos                (0UL)                     /*!< THR (Bit 0)                                           */
15951 #define PDM_INTSET_THR_Msk                (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
15952 /* =======================================================  DMATRIGEN  ======================================================= */
15953 #define PDM_DMATRIGEN_DTHR90_Pos          (1UL)                     /*!< DTHR90 (Bit 1)                                        */
15954 #define PDM_DMATRIGEN_DTHR90_Msk          (0x2UL)                   /*!< DTHR90 (Bitfield-Mask: 0x01)                          */
15955 #define PDM_DMATRIGEN_DTHR_Pos            (0UL)                     /*!< DTHR (Bit 0)                                          */
15956 #define PDM_DMATRIGEN_DTHR_Msk            (0x1UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
15957 /* ======================================================  DMATRIGSTAT  ====================================================== */
15958 #define PDM_DMATRIGSTAT_DTHR90STAT_Pos    (1UL)                     /*!< DTHR90STAT (Bit 1)                                    */
15959 #define PDM_DMATRIGSTAT_DTHR90STAT_Msk    (0x2UL)                   /*!< DTHR90STAT (Bitfield-Mask: 0x01)                      */
15960 #define PDM_DMATRIGSTAT_DTHRSTAT_Pos      (0UL)                     /*!< DTHRSTAT (Bit 0)                                      */
15961 #define PDM_DMATRIGSTAT_DTHRSTAT_Msk      (0x1UL)                   /*!< DTHRSTAT (Bitfield-Mask: 0x01)                        */
15962 /* ========================================================  DMACFG  ========================================================= */
15963 #define PDM_DMACFG_DPWROFF_Pos            (10UL)                    /*!< DPWROFF (Bit 10)                                      */
15964 #define PDM_DMACFG_DPWROFF_Msk            (0x400UL)                 /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
15965 #define PDM_DMACFG_DAUTOHIP_Pos           (9UL)                     /*!< DAUTOHIP (Bit 9)                                      */
15966 #define PDM_DMACFG_DAUTOHIP_Msk           (0x200UL)                 /*!< DAUTOHIP (Bitfield-Mask: 0x01)                        */
15967 #define PDM_DMACFG_DMAPRI_Pos             (8UL)                     /*!< DMAPRI (Bit 8)                                        */
15968 #define PDM_DMACFG_DMAPRI_Msk             (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
15969 #define PDM_DMACFG_DMADIR_Pos             (2UL)                     /*!< DMADIR (Bit 2)                                        */
15970 #define PDM_DMACFG_DMADIR_Msk             (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
15971 #define PDM_DMACFG_DMAEN_Pos              (0UL)                     /*!< DMAEN (Bit 0)                                         */
15972 #define PDM_DMACFG_DMAEN_Msk              (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
15973 /* ======================================================  DMATOTCOUNT  ====================================================== */
15974 #define PDM_DMATOTCOUNT_TOTCOUNT_Pos      (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
15975 #define PDM_DMATOTCOUNT_TOTCOUNT_Msk      (0xfffffUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xfffff)                     */
15976 /* ======================================================  DMATARGADDR  ====================================================== */
15977 #define PDM_DMATARGADDR_UTARGADDR_Pos     (21UL)                    /*!< UTARGADDR (Bit 21)                                    */
15978 #define PDM_DMATARGADDR_UTARGADDR_Msk     (0xffe00000UL)            /*!< UTARGADDR (Bitfield-Mask: 0x7ff)                      */
15979 #define PDM_DMATARGADDR_LTARGADDR_Pos     (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
15980 #define PDM_DMATARGADDR_LTARGADDR_Msk     (0x1fffffUL)              /*!< LTARGADDR (Bitfield-Mask: 0x1fffff)                   */
15981 /* ========================================================  DMASTAT  ======================================================== */
15982 #define PDM_DMASTAT_DMAERR_Pos            (2UL)                     /*!< DMAERR (Bit 2)                                        */
15983 #define PDM_DMASTAT_DMAERR_Msk            (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
15984 #define PDM_DMASTAT_DMACPL_Pos            (1UL)                     /*!< DMACPL (Bit 1)                                        */
15985 #define PDM_DMASTAT_DMACPL_Msk            (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
15986 #define PDM_DMASTAT_DMATIP_Pos            (0UL)                     /*!< DMATIP (Bit 0)                                        */
15987 #define PDM_DMASTAT_DMATIP_Msk            (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
15988 
15989 
15990 /* =========================================================================================================================== */
15991 /* ================                                          PWRCTRL                                          ================ */
15992 /* =========================================================================================================================== */
15993 
15994 /* =======================================================  SUPPLYSRC  ======================================================= */
15995 #define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Pos   (0UL)                     /*!< BLEBUCKEN (Bit 0)                                     */
15996 #define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Msk   (0x1UL)                   /*!< BLEBUCKEN (Bitfield-Mask: 0x01)                       */
15997 /* =====================================================  SUPPLYSTATUS  ====================================================== */
15998 #define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Pos (1UL)                    /*!< BLEBUCKON (Bit 1)                                     */
15999 #define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Msk (0x2UL)                  /*!< BLEBUCKON (Bitfield-Mask: 0x01)                       */
16000 #define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Pos (0UL)                   /*!< SIMOBUCKON (Bit 0)                                    */
16001 #define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Msk (0x1UL)                 /*!< SIMOBUCKON (Bitfield-Mask: 0x01)                      */
16002 /* =======================================================  DEVPWREN  ======================================================== */
16003 #define PWRCTRL_DEVPWREN_PWRBLEL_Pos      (15UL)                    /*!< PWRBLEL (Bit 15)                                      */
16004 #define PWRCTRL_DEVPWREN_PWRBLEL_Msk      (0x8000UL)                /*!< PWRBLEL (Bitfield-Mask: 0x01)                         */
16005 #define PWRCTRL_DEVPWREN_PWRPDM_Pos       (14UL)                    /*!< PWRPDM (Bit 14)                                       */
16006 #define PWRCTRL_DEVPWREN_PWRPDM_Msk       (0x4000UL)                /*!< PWRPDM (Bitfield-Mask: 0x01)                          */
16007 #define PWRCTRL_DEVPWREN_PWRMSPI2_Pos     (13UL)                    /*!< PWRMSPI2 (Bit 13)                                     */
16008 #define PWRCTRL_DEVPWREN_PWRMSPI2_Msk     (0x2000UL)                /*!< PWRMSPI2 (Bitfield-Mask: 0x01)                        */
16009 #define PWRCTRL_DEVPWREN_PWRMSPI1_Pos     (12UL)                    /*!< PWRMSPI1 (Bit 12)                                     */
16010 #define PWRCTRL_DEVPWREN_PWRMSPI1_Msk     (0x1000UL)                /*!< PWRMSPI1 (Bitfield-Mask: 0x01)                        */
16011 #define PWRCTRL_DEVPWREN_PWRMSPI0_Pos     (11UL)                    /*!< PWRMSPI0 (Bit 11)                                     */
16012 #define PWRCTRL_DEVPWREN_PWRMSPI0_Msk     (0x800UL)                 /*!< PWRMSPI0 (Bitfield-Mask: 0x01)                        */
16013 #define PWRCTRL_DEVPWREN_PWRSCARD_Pos     (10UL)                    /*!< PWRSCARD (Bit 10)                                     */
16014 #define PWRCTRL_DEVPWREN_PWRSCARD_Msk     (0x400UL)                 /*!< PWRSCARD (Bitfield-Mask: 0x01)                        */
16015 #define PWRCTRL_DEVPWREN_PWRADC_Pos       (9UL)                     /*!< PWRADC (Bit 9)                                        */
16016 #define PWRCTRL_DEVPWREN_PWRADC_Msk       (0x200UL)                 /*!< PWRADC (Bitfield-Mask: 0x01)                          */
16017 #define PWRCTRL_DEVPWREN_PWRUART1_Pos     (8UL)                     /*!< PWRUART1 (Bit 8)                                      */
16018 #define PWRCTRL_DEVPWREN_PWRUART1_Msk     (0x100UL)                 /*!< PWRUART1 (Bitfield-Mask: 0x01)                        */
16019 #define PWRCTRL_DEVPWREN_PWRUART0_Pos     (7UL)                     /*!< PWRUART0 (Bit 7)                                      */
16020 #define PWRCTRL_DEVPWREN_PWRUART0_Msk     (0x80UL)                  /*!< PWRUART0 (Bitfield-Mask: 0x01)                        */
16021 #define PWRCTRL_DEVPWREN_PWRIOM5_Pos      (6UL)                     /*!< PWRIOM5 (Bit 6)                                       */
16022 #define PWRCTRL_DEVPWREN_PWRIOM5_Msk      (0x40UL)                  /*!< PWRIOM5 (Bitfield-Mask: 0x01)                         */
16023 #define PWRCTRL_DEVPWREN_PWRIOM4_Pos      (5UL)                     /*!< PWRIOM4 (Bit 5)                                       */
16024 #define PWRCTRL_DEVPWREN_PWRIOM4_Msk      (0x20UL)                  /*!< PWRIOM4 (Bitfield-Mask: 0x01)                         */
16025 #define PWRCTRL_DEVPWREN_PWRIOM3_Pos      (4UL)                     /*!< PWRIOM3 (Bit 4)                                       */
16026 #define PWRCTRL_DEVPWREN_PWRIOM3_Msk      (0x10UL)                  /*!< PWRIOM3 (Bitfield-Mask: 0x01)                         */
16027 #define PWRCTRL_DEVPWREN_PWRIOM2_Pos      (3UL)                     /*!< PWRIOM2 (Bit 3)                                       */
16028 #define PWRCTRL_DEVPWREN_PWRIOM2_Msk      (0x8UL)                   /*!< PWRIOM2 (Bitfield-Mask: 0x01)                         */
16029 #define PWRCTRL_DEVPWREN_PWRIOM1_Pos      (2UL)                     /*!< PWRIOM1 (Bit 2)                                       */
16030 #define PWRCTRL_DEVPWREN_PWRIOM1_Msk      (0x4UL)                   /*!< PWRIOM1 (Bitfield-Mask: 0x01)                         */
16031 #define PWRCTRL_DEVPWREN_PWRIOM0_Pos      (1UL)                     /*!< PWRIOM0 (Bit 1)                                       */
16032 #define PWRCTRL_DEVPWREN_PWRIOM0_Msk      (0x2UL)                   /*!< PWRIOM0 (Bitfield-Mask: 0x01)                         */
16033 #define PWRCTRL_DEVPWREN_PWRIOS_Pos       (0UL)                     /*!< PWRIOS (Bit 0)                                        */
16034 #define PWRCTRL_DEVPWREN_PWRIOS_Msk       (0x1UL)                   /*!< PWRIOS (Bitfield-Mask: 0x01)                          */
16035 /* =====================================================  MEMPWDINSLEEP  ===================================================== */
16036 #define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Pos (31UL)                /*!< CACHEPWDSLP (Bit 31)                                  */
16037 #define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Msk (0x80000000UL)        /*!< CACHEPWDSLP (Bitfield-Mask: 0x01)                     */
16038 #define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Pos (14UL)               /*!< FLASH1PWDSLP (Bit 14)                                 */
16039 #define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Msk (0x4000UL)           /*!< FLASH1PWDSLP (Bitfield-Mask: 0x01)                    */
16040 #define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Pos (13UL)               /*!< FLASH0PWDSLP (Bit 13)                                 */
16041 #define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk (0x2000UL)           /*!< FLASH0PWDSLP (Bitfield-Mask: 0x01)                    */
16042 #define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Pos (3UL)                  /*!< SRAMPWDSLP (Bit 3)                                    */
16043 #define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Msk (0x1ff8UL)             /*!< SRAMPWDSLP (Bitfield-Mask: 0x3ff)                     */
16044 #define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Pos (0UL)                  /*!< DTCMPWDSLP (Bit 0)                                    */
16045 #define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Msk (0x7UL)                /*!< DTCMPWDSLP (Bitfield-Mask: 0x07)                      */
16046 /* =======================================================  MEMPWREN  ======================================================== */
16047 #define PWRCTRL_MEMPWREN_CACHEB2_Pos      (31UL)                    /*!< CACHEB2 (Bit 31)                                      */
16048 #define PWRCTRL_MEMPWREN_CACHEB2_Msk      (0x80000000UL)            /*!< CACHEB2 (Bitfield-Mask: 0x01)                         */
16049 #define PWRCTRL_MEMPWREN_CACHEB0_Pos      (30UL)                    /*!< CACHEB0 (Bit 30)                                      */
16050 #define PWRCTRL_MEMPWREN_CACHEB0_Msk      (0x40000000UL)            /*!< CACHEB0 (Bitfield-Mask: 0x01)                         */
16051 #define PWRCTRL_MEMPWREN_FLASH1_Pos       (14UL)                    /*!< FLASH1 (Bit 14)                                       */
16052 #define PWRCTRL_MEMPWREN_FLASH1_Msk       (0x4000UL)                /*!< FLASH1 (Bitfield-Mask: 0x01)                          */
16053 #define PWRCTRL_MEMPWREN_FLASH0_Pos       (13UL)                    /*!< FLASH0 (Bit 13)                                       */
16054 #define PWRCTRL_MEMPWREN_FLASH0_Msk       (0x2000UL)                /*!< FLASH0 (Bitfield-Mask: 0x01)                          */
16055 #define PWRCTRL_MEMPWREN_SRAM_Pos         (3UL)                     /*!< SRAM (Bit 3)                                          */
16056 #define PWRCTRL_MEMPWREN_SRAM_Msk         (0x1ff8UL)                /*!< SRAM (Bitfield-Mask: 0x3ff)                           */
16057 #define PWRCTRL_MEMPWREN_DTCM_Pos         (0UL)                     /*!< DTCM (Bit 0)                                          */
16058 #define PWRCTRL_MEMPWREN_DTCM_Msk         (0x7UL)                   /*!< DTCM (Bitfield-Mask: 0x07)                            */
16059 /* =====================================================  MEMPWRSTATUS  ====================================================== */
16060 #define PWRCTRL_MEMPWRSTATUS_CACHEB2_Pos  (16UL)                    /*!< CACHEB2 (Bit 16)                                      */
16061 #define PWRCTRL_MEMPWRSTATUS_CACHEB2_Msk  (0x10000UL)               /*!< CACHEB2 (Bitfield-Mask: 0x01)                         */
16062 #define PWRCTRL_MEMPWRSTATUS_CACHEB0_Pos  (15UL)                    /*!< CACHEB0 (Bit 15)                                      */
16063 #define PWRCTRL_MEMPWRSTATUS_CACHEB0_Msk  (0x8000UL)                /*!< CACHEB0 (Bitfield-Mask: 0x01)                         */
16064 #define PWRCTRL_MEMPWRSTATUS_FLASH1_Pos   (14UL)                    /*!< FLASH1 (Bit 14)                                       */
16065 #define PWRCTRL_MEMPWRSTATUS_FLASH1_Msk   (0x4000UL)                /*!< FLASH1 (Bitfield-Mask: 0x01)                          */
16066 #define PWRCTRL_MEMPWRSTATUS_FLASH0_Pos   (13UL)                    /*!< FLASH0 (Bit 13)                                       */
16067 #define PWRCTRL_MEMPWRSTATUS_FLASH0_Msk   (0x2000UL)                /*!< FLASH0 (Bitfield-Mask: 0x01)                          */
16068 #define PWRCTRL_MEMPWRSTATUS_SRAM9_Pos    (12UL)                    /*!< SRAM9 (Bit 12)                                        */
16069 #define PWRCTRL_MEMPWRSTATUS_SRAM9_Msk    (0x1000UL)                /*!< SRAM9 (Bitfield-Mask: 0x01)                           */
16070 #define PWRCTRL_MEMPWRSTATUS_SRAM8_Pos    (11UL)                    /*!< SRAM8 (Bit 11)                                        */
16071 #define PWRCTRL_MEMPWRSTATUS_SRAM8_Msk    (0x800UL)                 /*!< SRAM8 (Bitfield-Mask: 0x01)                           */
16072 #define PWRCTRL_MEMPWRSTATUS_SRAM7_Pos    (10UL)                    /*!< SRAM7 (Bit 10)                                        */
16073 #define PWRCTRL_MEMPWRSTATUS_SRAM7_Msk    (0x400UL)                 /*!< SRAM7 (Bitfield-Mask: 0x01)                           */
16074 #define PWRCTRL_MEMPWRSTATUS_SRAM6_Pos    (9UL)                     /*!< SRAM6 (Bit 9)                                         */
16075 #define PWRCTRL_MEMPWRSTATUS_SRAM6_Msk    (0x200UL)                 /*!< SRAM6 (Bitfield-Mask: 0x01)                           */
16076 #define PWRCTRL_MEMPWRSTATUS_SRAM5_Pos    (8UL)                     /*!< SRAM5 (Bit 8)                                         */
16077 #define PWRCTRL_MEMPWRSTATUS_SRAM5_Msk    (0x100UL)                 /*!< SRAM5 (Bitfield-Mask: 0x01)                           */
16078 #define PWRCTRL_MEMPWRSTATUS_SRAM4_Pos    (7UL)                     /*!< SRAM4 (Bit 7)                                         */
16079 #define PWRCTRL_MEMPWRSTATUS_SRAM4_Msk    (0x80UL)                  /*!< SRAM4 (Bitfield-Mask: 0x01)                           */
16080 #define PWRCTRL_MEMPWRSTATUS_SRAM3_Pos    (6UL)                     /*!< SRAM3 (Bit 6)                                         */
16081 #define PWRCTRL_MEMPWRSTATUS_SRAM3_Msk    (0x40UL)                  /*!< SRAM3 (Bitfield-Mask: 0x01)                           */
16082 #define PWRCTRL_MEMPWRSTATUS_SRAM2_Pos    (5UL)                     /*!< SRAM2 (Bit 5)                                         */
16083 #define PWRCTRL_MEMPWRSTATUS_SRAM2_Msk    (0x20UL)                  /*!< SRAM2 (Bitfield-Mask: 0x01)                           */
16084 #define PWRCTRL_MEMPWRSTATUS_SRAM1_Pos    (4UL)                     /*!< SRAM1 (Bit 4)                                         */
16085 #define PWRCTRL_MEMPWRSTATUS_SRAM1_Msk    (0x10UL)                  /*!< SRAM1 (Bitfield-Mask: 0x01)                           */
16086 #define PWRCTRL_MEMPWRSTATUS_SRAM0_Pos    (3UL)                     /*!< SRAM0 (Bit 3)                                         */
16087 #define PWRCTRL_MEMPWRSTATUS_SRAM0_Msk    (0x8UL)                   /*!< SRAM0 (Bitfield-Mask: 0x01)                           */
16088 #define PWRCTRL_MEMPWRSTATUS_DTCM1_Pos    (2UL)                     /*!< DTCM1 (Bit 2)                                         */
16089 #define PWRCTRL_MEMPWRSTATUS_DTCM1_Msk    (0x4UL)                   /*!< DTCM1 (Bitfield-Mask: 0x01)                           */
16090 #define PWRCTRL_MEMPWRSTATUS_DTCM01_Pos   (1UL)                     /*!< DTCM01 (Bit 1)                                        */
16091 #define PWRCTRL_MEMPWRSTATUS_DTCM01_Msk   (0x2UL)                   /*!< DTCM01 (Bitfield-Mask: 0x01)                          */
16092 #define PWRCTRL_MEMPWRSTATUS_DTCM00_Pos   (0UL)                     /*!< DTCM00 (Bit 0)                                        */
16093 #define PWRCTRL_MEMPWRSTATUS_DTCM00_Msk   (0x1UL)                   /*!< DTCM00 (Bitfield-Mask: 0x01)                          */
16094 /* =====================================================  DEVPWRSTATUS  ====================================================== */
16095 #define PWRCTRL_DEVPWRSTATUS_BLEH_Pos     (9UL)                     /*!< BLEH (Bit 9)                                          */
16096 #define PWRCTRL_DEVPWRSTATUS_BLEH_Msk     (0x200UL)                 /*!< BLEH (Bitfield-Mask: 0x01)                            */
16097 #define PWRCTRL_DEVPWRSTATUS_BLEL_Pos     (8UL)                     /*!< BLEL (Bit 8)                                          */
16098 #define PWRCTRL_DEVPWRSTATUS_BLEL_Msk     (0x100UL)                 /*!< BLEL (Bitfield-Mask: 0x01)                            */
16099 #define PWRCTRL_DEVPWRSTATUS_PWRPDM_Pos   (7UL)                     /*!< PWRPDM (Bit 7)                                        */
16100 #define PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk   (0x80UL)                  /*!< PWRPDM (Bitfield-Mask: 0x01)                          */
16101 #define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Pos  (6UL)                     /*!< PWRMSPI (Bit 6)                                       */
16102 #define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk  (0x40UL)                  /*!< PWRMSPI (Bitfield-Mask: 0x01)                         */
16103 #define PWRCTRL_DEVPWRSTATUS_PWRADC_Pos   (5UL)                     /*!< PWRADC (Bit 5)                                        */
16104 #define PWRCTRL_DEVPWRSTATUS_PWRADC_Msk   (0x20UL)                  /*!< PWRADC (Bitfield-Mask: 0x01)                          */
16105 #define PWRCTRL_DEVPWRSTATUS_HCPC_Pos     (4UL)                     /*!< HCPC (Bit 4)                                          */
16106 #define PWRCTRL_DEVPWRSTATUS_HCPC_Msk     (0x10UL)                  /*!< HCPC (Bitfield-Mask: 0x01)                            */
16107 #define PWRCTRL_DEVPWRSTATUS_HCPB_Pos     (3UL)                     /*!< HCPB (Bit 3)                                          */
16108 #define PWRCTRL_DEVPWRSTATUS_HCPB_Msk     (0x8UL)                   /*!< HCPB (Bitfield-Mask: 0x01)                            */
16109 #define PWRCTRL_DEVPWRSTATUS_HCPA_Pos     (2UL)                     /*!< HCPA (Bit 2)                                          */
16110 #define PWRCTRL_DEVPWRSTATUS_HCPA_Msk     (0x4UL)                   /*!< HCPA (Bitfield-Mask: 0x01)                            */
16111 #define PWRCTRL_DEVPWRSTATUS_MCUH_Pos     (1UL)                     /*!< MCUH (Bit 1)                                          */
16112 #define PWRCTRL_DEVPWRSTATUS_MCUH_Msk     (0x2UL)                   /*!< MCUH (Bitfield-Mask: 0x01)                            */
16113 #define PWRCTRL_DEVPWRSTATUS_MCUL_Pos     (0UL)                     /*!< MCUL (Bit 0)                                          */
16114 #define PWRCTRL_DEVPWRSTATUS_MCUL_Msk     (0x1UL)                   /*!< MCUL (Bitfield-Mask: 0x01)                            */
16115 /* =======================================================  SRAMCTRL  ======================================================== */
16116 #define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Pos (8UL)                   /*!< SRAMLIGHTSLEEP (Bit 8)                                */
16117 #define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Msk (0xfff00UL)             /*!< SRAMLIGHTSLEEP (Bitfield-Mask: 0xfff)                 */
16118 #define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Pos (2UL)                /*!< SRAMMASTERCLKGATE (Bit 2)                             */
16119 #define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Msk (0x4UL)              /*!< SRAMMASTERCLKGATE (Bitfield-Mask: 0x01)               */
16120 #define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Pos  (1UL)                     /*!< SRAMCLKGATE (Bit 1)                                   */
16121 #define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Msk  (0x2UL)                   /*!< SRAMCLKGATE (Bitfield-Mask: 0x01)                     */
16122 /* =======================================================  ADCSTATUS  ======================================================= */
16123 #define PWRCTRL_ADCSTATUS_REFBUFPWD_Pos   (5UL)                     /*!< REFBUFPWD (Bit 5)                                     */
16124 #define PWRCTRL_ADCSTATUS_REFBUFPWD_Msk   (0x20UL)                  /*!< REFBUFPWD (Bitfield-Mask: 0x01)                       */
16125 #define PWRCTRL_ADCSTATUS_REFKEEPPWD_Pos  (4UL)                     /*!< REFKEEPPWD (Bit 4)                                    */
16126 #define PWRCTRL_ADCSTATUS_REFKEEPPWD_Msk  (0x10UL)                  /*!< REFKEEPPWD (Bitfield-Mask: 0x01)                      */
16127 #define PWRCTRL_ADCSTATUS_VBATPWD_Pos     (3UL)                     /*!< VBATPWD (Bit 3)                                       */
16128 #define PWRCTRL_ADCSTATUS_VBATPWD_Msk     (0x8UL)                   /*!< VBATPWD (Bitfield-Mask: 0x01)                         */
16129 #define PWRCTRL_ADCSTATUS_VPTATPWD_Pos    (2UL)                     /*!< VPTATPWD (Bit 2)                                      */
16130 #define PWRCTRL_ADCSTATUS_VPTATPWD_Msk    (0x4UL)                   /*!< VPTATPWD (Bitfield-Mask: 0x01)                        */
16131 #define PWRCTRL_ADCSTATUS_BGTPWD_Pos      (1UL)                     /*!< BGTPWD (Bit 1)                                        */
16132 #define PWRCTRL_ADCSTATUS_BGTPWD_Msk      (0x2UL)                   /*!< BGTPWD (Bitfield-Mask: 0x01)                          */
16133 #define PWRCTRL_ADCSTATUS_ADCPWD_Pos      (0UL)                     /*!< ADCPWD (Bit 0)                                        */
16134 #define PWRCTRL_ADCSTATUS_ADCPWD_Msk      (0x1UL)                   /*!< ADCPWD (Bitfield-Mask: 0x01)                          */
16135 /* =========================================================  MISC  ========================================================== */
16136 #define PWRCTRL_MISC_FORCEBLEBUCKACT_Pos  (7UL)                     /*!< FORCEBLEBUCKACT (Bit 7)                               */
16137 #define PWRCTRL_MISC_FORCEBLEBUCKACT_Msk  (0x80UL)                  /*!< FORCEBLEBUCKACT (Bitfield-Mask: 0x01)                 */
16138 #define PWRCTRL_MISC_MEMVRLPBLE_Pos       (6UL)                     /*!< MEMVRLPBLE (Bit 6)                                    */
16139 #define PWRCTRL_MISC_MEMVRLPBLE_Msk       (0x40UL)                  /*!< MEMVRLPBLE (Bitfield-Mask: 0x01)                      */
16140 #define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Pos (3UL)                   /*!< FORCEMEMVRLPTIMERS (Bit 3)                            */
16141 #define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Msk (0x8UL)                 /*!< FORCEMEMVRLPTIMERS (Bitfield-Mask: 0x01)              */
16142 #define PWRCTRL_MISC_SIMOBUCKEN_Pos       (0UL)                     /*!< SIMOBUCKEN (Bit 0)                                    */
16143 #define PWRCTRL_MISC_SIMOBUCKEN_Msk       (0x1UL)                   /*!< SIMOBUCKEN (Bitfield-Mask: 0x01)                      */
16144 /* =====================================================  DEVPWREVENTEN  ===================================================== */
16145 #define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Pos (31UL)                  /*!< BURSTEVEN (Bit 31)                                    */
16146 #define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Msk (0x80000000UL)          /*!< BURSTEVEN (Bitfield-Mask: 0x01)                       */
16147 #define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Pos (30UL)           /*!< BURSTFEATUREEVEN (Bit 30)                             */
16148 #define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Msk (0x40000000UL)   /*!< BURSTFEATUREEVEN (Bitfield-Mask: 0x01)                */
16149 #define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Pos (29UL)             /*!< BLEFEATUREEVEN (Bit 29)                               */
16150 #define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Msk (0x20000000UL)     /*!< BLEFEATUREEVEN (Bitfield-Mask: 0x01)                  */
16151 #define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Pos (8UL)                    /*!< BLELEVEN (Bit 8)                                      */
16152 #define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Msk (0x100UL)                /*!< BLELEVEN (Bitfield-Mask: 0x01)                        */
16153 #define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Pos (7UL)                     /*!< PDMEVEN (Bit 7)                                       */
16154 #define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Msk (0x80UL)                  /*!< PDMEVEN (Bitfield-Mask: 0x01)                         */
16155 #define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Pos (6UL)                    /*!< MSPIEVEN (Bit 6)                                      */
16156 #define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Msk (0x40UL)                 /*!< MSPIEVEN (Bitfield-Mask: 0x01)                        */
16157 #define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Pos (5UL)                     /*!< ADCEVEN (Bit 5)                                       */
16158 #define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Msk (0x20UL)                  /*!< ADCEVEN (Bitfield-Mask: 0x01)                         */
16159 #define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Pos (4UL)                    /*!< HCPCEVEN (Bit 4)                                      */
16160 #define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Msk (0x10UL)                 /*!< HCPCEVEN (Bitfield-Mask: 0x01)                        */
16161 #define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Pos (3UL)                    /*!< HCPBEVEN (Bit 3)                                      */
16162 #define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Msk (0x8UL)                  /*!< HCPBEVEN (Bitfield-Mask: 0x01)                        */
16163 #define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Pos (2UL)                    /*!< HCPAEVEN (Bit 2)                                      */
16164 #define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Msk (0x4UL)                  /*!< HCPAEVEN (Bitfield-Mask: 0x01)                        */
16165 #define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Pos (1UL)                    /*!< MCUHEVEN (Bit 1)                                      */
16166 #define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Msk (0x2UL)                  /*!< MCUHEVEN (Bitfield-Mask: 0x01)                        */
16167 #define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Pos (0UL)                    /*!< MCULEVEN (Bit 0)                                      */
16168 #define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Msk (0x1UL)                  /*!< MCULEVEN (Bitfield-Mask: 0x01)                        */
16169 /* =====================================================  MEMPWREVENTEN  ===================================================== */
16170 #define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Pos (31UL)                  /*!< CACHEB2EN (Bit 31)                                    */
16171 #define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Msk (0x80000000UL)          /*!< CACHEB2EN (Bitfield-Mask: 0x01)                       */
16172 #define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Pos (30UL)                  /*!< CACHEB0EN (Bit 30)                                    */
16173 #define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Msk (0x40000000UL)          /*!< CACHEB0EN (Bitfield-Mask: 0x01)                       */
16174 #define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Pos (14UL)                   /*!< FLASH1EN (Bit 14)                                     */
16175 #define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Msk (0x4000UL)               /*!< FLASH1EN (Bitfield-Mask: 0x01)                        */
16176 #define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Pos (13UL)                   /*!< FLASH0EN (Bit 13)                                     */
16177 #define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Msk (0x2000UL)               /*!< FLASH0EN (Bitfield-Mask: 0x01)                        */
16178 #define PWRCTRL_MEMPWREVENTEN_SRAMEN_Pos  (3UL)                     /*!< SRAMEN (Bit 3)                                        */
16179 #define PWRCTRL_MEMPWREVENTEN_SRAMEN_Msk  (0x1ff8UL)                /*!< SRAMEN (Bitfield-Mask: 0x3ff)                         */
16180 #define PWRCTRL_MEMPWREVENTEN_DTCMEN_Pos  (0UL)                     /*!< DTCMEN (Bit 0)                                        */
16181 #define PWRCTRL_MEMPWREVENTEN_DTCMEN_Msk  (0x7UL)                   /*!< DTCMEN (Bitfield-Mask: 0x07)                          */
16182 
16183 
16184 /* =========================================================================================================================== */
16185 /* ================                                          RSTGEN                                           ================ */
16186 /* =========================================================================================================================== */
16187 
16188 /* ==========================================================  CFG  ========================================================== */
16189 #define RSTGEN_CFG_WDREN_Pos              (1UL)                     /*!< WDREN (Bit 1)                                         */
16190 #define RSTGEN_CFG_WDREN_Msk              (0x2UL)                   /*!< WDREN (Bitfield-Mask: 0x01)                           */
16191 #define RSTGEN_CFG_BODHREN_Pos            (0UL)                     /*!< BODHREN (Bit 0)                                       */
16192 #define RSTGEN_CFG_BODHREN_Msk            (0x1UL)                   /*!< BODHREN (Bitfield-Mask: 0x01)                         */
16193 /* =========================================================  SWPOI  ========================================================= */
16194 #define RSTGEN_SWPOI_SWPOIKEY_Pos         (0UL)                     /*!< SWPOIKEY (Bit 0)                                      */
16195 #define RSTGEN_SWPOI_SWPOIKEY_Msk         (0xffUL)                  /*!< SWPOIKEY (Bitfield-Mask: 0xff)                        */
16196 /* =========================================================  SWPOR  ========================================================= */
16197 #define RSTGEN_SWPOR_SWPORKEY_Pos         (0UL)                     /*!< SWPORKEY (Bit 0)                                      */
16198 #define RSTGEN_SWPOR_SWPORKEY_Msk         (0xffUL)                  /*!< SWPORKEY (Bitfield-Mask: 0xff)                        */
16199 /* ========================================================  TPIURST  ======================================================== */
16200 #define RSTGEN_TPIURST_TPIURST_Pos        (0UL)                     /*!< TPIURST (Bit 0)                                       */
16201 #define RSTGEN_TPIURST_TPIURST_Msk        (0x1UL)                   /*!< TPIURST (Bitfield-Mask: 0x01)                         */
16202 /* =========================================================  INTEN  ========================================================= */
16203 #define RSTGEN_INTEN_BODH_Pos             (0UL)                     /*!< BODH (Bit 0)                                          */
16204 #define RSTGEN_INTEN_BODH_Msk             (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
16205 /* ========================================================  INTSTAT  ======================================================== */
16206 #define RSTGEN_INTSTAT_BODH_Pos           (0UL)                     /*!< BODH (Bit 0)                                          */
16207 #define RSTGEN_INTSTAT_BODH_Msk           (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
16208 /* ========================================================  INTCLR  ========================================================= */
16209 #define RSTGEN_INTCLR_BODH_Pos            (0UL)                     /*!< BODH (Bit 0)                                          */
16210 #define RSTGEN_INTCLR_BODH_Msk            (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
16211 /* ========================================================  INTSET  ========================================================= */
16212 #define RSTGEN_INTSET_BODH_Pos            (0UL)                     /*!< BODH (Bit 0)                                          */
16213 #define RSTGEN_INTSET_BODH_Msk            (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
16214 /* =========================================================  STAT  ========================================================== */
16215 #define RSTGEN_STAT_SBOOT_Pos             (31UL)                    /*!< SBOOT (Bit 31)                                        */
16216 #define RSTGEN_STAT_SBOOT_Msk             (0x80000000UL)            /*!< SBOOT (Bitfield-Mask: 0x01)                           */
16217 #define RSTGEN_STAT_FBOOT_Pos             (30UL)                    /*!< FBOOT (Bit 30)                                        */
16218 #define RSTGEN_STAT_FBOOT_Msk             (0x40000000UL)            /*!< FBOOT (Bitfield-Mask: 0x01)                           */
16219 #define RSTGEN_STAT_BOBSTAT_Pos           (10UL)                    /*!< BOBSTAT (Bit 10)                                      */
16220 #define RSTGEN_STAT_BOBSTAT_Msk           (0x400UL)                 /*!< BOBSTAT (Bitfield-Mask: 0x01)                         */
16221 #define RSTGEN_STAT_BOFSTAT_Pos           (9UL)                     /*!< BOFSTAT (Bit 9)                                       */
16222 #define RSTGEN_STAT_BOFSTAT_Msk           (0x200UL)                 /*!< BOFSTAT (Bitfield-Mask: 0x01)                         */
16223 #define RSTGEN_STAT_BOCSTAT_Pos           (8UL)                     /*!< BOCSTAT (Bit 8)                                       */
16224 #define RSTGEN_STAT_BOCSTAT_Msk           (0x100UL)                 /*!< BOCSTAT (Bitfield-Mask: 0x01)                         */
16225 #define RSTGEN_STAT_BOUSTAT_Pos           (7UL)                     /*!< BOUSTAT (Bit 7)                                       */
16226 #define RSTGEN_STAT_BOUSTAT_Msk           (0x80UL)                  /*!< BOUSTAT (Bitfield-Mask: 0x01)                         */
16227 #define RSTGEN_STAT_WDRSTAT_Pos           (6UL)                     /*!< WDRSTAT (Bit 6)                                       */
16228 #define RSTGEN_STAT_WDRSTAT_Msk           (0x40UL)                  /*!< WDRSTAT (Bitfield-Mask: 0x01)                         */
16229 #define RSTGEN_STAT_DBGRSTAT_Pos          (5UL)                     /*!< DBGRSTAT (Bit 5)                                      */
16230 #define RSTGEN_STAT_DBGRSTAT_Msk          (0x20UL)                  /*!< DBGRSTAT (Bitfield-Mask: 0x01)                        */
16231 #define RSTGEN_STAT_POIRSTAT_Pos          (4UL)                     /*!< POIRSTAT (Bit 4)                                      */
16232 #define RSTGEN_STAT_POIRSTAT_Msk          (0x10UL)                  /*!< POIRSTAT (Bitfield-Mask: 0x01)                        */
16233 #define RSTGEN_STAT_SWRSTAT_Pos           (3UL)                     /*!< SWRSTAT (Bit 3)                                       */
16234 #define RSTGEN_STAT_SWRSTAT_Msk           (0x8UL)                   /*!< SWRSTAT (Bitfield-Mask: 0x01)                         */
16235 #define RSTGEN_STAT_BORSTAT_Pos           (2UL)                     /*!< BORSTAT (Bit 2)                                       */
16236 #define RSTGEN_STAT_BORSTAT_Msk           (0x4UL)                   /*!< BORSTAT (Bitfield-Mask: 0x01)                         */
16237 #define RSTGEN_STAT_PORSTAT_Pos           (1UL)                     /*!< PORSTAT (Bit 1)                                       */
16238 #define RSTGEN_STAT_PORSTAT_Msk           (0x2UL)                   /*!< PORSTAT (Bitfield-Mask: 0x01)                         */
16239 #define RSTGEN_STAT_EXRSTAT_Pos           (0UL)                     /*!< EXRSTAT (Bit 0)                                       */
16240 #define RSTGEN_STAT_EXRSTAT_Msk           (0x1UL)                   /*!< EXRSTAT (Bitfield-Mask: 0x01)                         */
16241 
16242 
16243 /* =========================================================================================================================== */
16244 /* ================                                            RTC                                            ================ */
16245 /* =========================================================================================================================== */
16246 
16247 /* ========================================================  CTRLOW  ========================================================= */
16248 #define RTC_CTRLOW_CTRHR_Pos              (24UL)                    /*!< CTRHR (Bit 24)                                        */
16249 #define RTC_CTRLOW_CTRHR_Msk              (0x3f000000UL)            /*!< CTRHR (Bitfield-Mask: 0x3f)                           */
16250 #define RTC_CTRLOW_CTRMIN_Pos             (16UL)                    /*!< CTRMIN (Bit 16)                                       */
16251 #define RTC_CTRLOW_CTRMIN_Msk             (0x7f0000UL)              /*!< CTRMIN (Bitfield-Mask: 0x7f)                          */
16252 #define RTC_CTRLOW_CTRSEC_Pos             (8UL)                     /*!< CTRSEC (Bit 8)                                        */
16253 #define RTC_CTRLOW_CTRSEC_Msk             (0x7f00UL)                /*!< CTRSEC (Bitfield-Mask: 0x7f)                          */
16254 #define RTC_CTRLOW_CTR100_Pos             (0UL)                     /*!< CTR100 (Bit 0)                                        */
16255 #define RTC_CTRLOW_CTR100_Msk             (0xffUL)                  /*!< CTR100 (Bitfield-Mask: 0xff)                          */
16256 /* =========================================================  CTRUP  ========================================================= */
16257 #define RTC_CTRUP_CTERR_Pos               (31UL)                    /*!< CTERR (Bit 31)                                        */
16258 #define RTC_CTRUP_CTERR_Msk               (0x80000000UL)            /*!< CTERR (Bitfield-Mask: 0x01)                           */
16259 #define RTC_CTRUP_CEB_Pos                 (28UL)                    /*!< CEB (Bit 28)                                          */
16260 #define RTC_CTRUP_CEB_Msk                 (0x10000000UL)            /*!< CEB (Bitfield-Mask: 0x01)                             */
16261 #define RTC_CTRUP_CB_Pos                  (27UL)                    /*!< CB (Bit 27)                                           */
16262 #define RTC_CTRUP_CB_Msk                  (0x8000000UL)             /*!< CB (Bitfield-Mask: 0x01)                              */
16263 #define RTC_CTRUP_CTRWKDY_Pos             (24UL)                    /*!< CTRWKDY (Bit 24)                                      */
16264 #define RTC_CTRUP_CTRWKDY_Msk             (0x7000000UL)             /*!< CTRWKDY (Bitfield-Mask: 0x07)                         */
16265 #define RTC_CTRUP_CTRYR_Pos               (16UL)                    /*!< CTRYR (Bit 16)                                        */
16266 #define RTC_CTRUP_CTRYR_Msk               (0xff0000UL)              /*!< CTRYR (Bitfield-Mask: 0xff)                           */
16267 #define RTC_CTRUP_CTRMO_Pos               (8UL)                     /*!< CTRMO (Bit 8)                                         */
16268 #define RTC_CTRUP_CTRMO_Msk               (0x1f00UL)                /*!< CTRMO (Bitfield-Mask: 0x1f)                           */
16269 #define RTC_CTRUP_CTRDATE_Pos             (0UL)                     /*!< CTRDATE (Bit 0)                                       */
16270 #define RTC_CTRUP_CTRDATE_Msk             (0x3fUL)                  /*!< CTRDATE (Bitfield-Mask: 0x3f)                         */
16271 /* ========================================================  ALMLOW  ========================================================= */
16272 #define RTC_ALMLOW_ALMHR_Pos              (24UL)                    /*!< ALMHR (Bit 24)                                        */
16273 #define RTC_ALMLOW_ALMHR_Msk              (0x3f000000UL)            /*!< ALMHR (Bitfield-Mask: 0x3f)                           */
16274 #define RTC_ALMLOW_ALMMIN_Pos             (16UL)                    /*!< ALMMIN (Bit 16)                                       */
16275 #define RTC_ALMLOW_ALMMIN_Msk             (0x7f0000UL)              /*!< ALMMIN (Bitfield-Mask: 0x7f)                          */
16276 #define RTC_ALMLOW_ALMSEC_Pos             (8UL)                     /*!< ALMSEC (Bit 8)                                        */
16277 #define RTC_ALMLOW_ALMSEC_Msk             (0x7f00UL)                /*!< ALMSEC (Bitfield-Mask: 0x7f)                          */
16278 #define RTC_ALMLOW_ALM100_Pos             (0UL)                     /*!< ALM100 (Bit 0)                                        */
16279 #define RTC_ALMLOW_ALM100_Msk             (0xffUL)                  /*!< ALM100 (Bitfield-Mask: 0xff)                          */
16280 /* =========================================================  ALMUP  ========================================================= */
16281 #define RTC_ALMUP_ALMWKDY_Pos             (16UL)                    /*!< ALMWKDY (Bit 16)                                      */
16282 #define RTC_ALMUP_ALMWKDY_Msk             (0x70000UL)               /*!< ALMWKDY (Bitfield-Mask: 0x07)                         */
16283 #define RTC_ALMUP_ALMMO_Pos               (8UL)                     /*!< ALMMO (Bit 8)                                         */
16284 #define RTC_ALMUP_ALMMO_Msk               (0x1f00UL)                /*!< ALMMO (Bitfield-Mask: 0x1f)                           */
16285 #define RTC_ALMUP_ALMDATE_Pos             (0UL)                     /*!< ALMDATE (Bit 0)                                       */
16286 #define RTC_ALMUP_ALMDATE_Msk             (0x3fUL)                  /*!< ALMDATE (Bitfield-Mask: 0x3f)                         */
16287 /* ========================================================  RTCCTL  ========================================================= */
16288 #define RTC_RTCCTL_HR1224_Pos             (5UL)                     /*!< HR1224 (Bit 5)                                        */
16289 #define RTC_RTCCTL_HR1224_Msk             (0x20UL)                  /*!< HR1224 (Bitfield-Mask: 0x01)                          */
16290 #define RTC_RTCCTL_RSTOP_Pos              (4UL)                     /*!< RSTOP (Bit 4)                                         */
16291 #define RTC_RTCCTL_RSTOP_Msk              (0x10UL)                  /*!< RSTOP (Bitfield-Mask: 0x01)                           */
16292 #define RTC_RTCCTL_RPT_Pos                (1UL)                     /*!< RPT (Bit 1)                                           */
16293 #define RTC_RTCCTL_RPT_Msk                (0xeUL)                   /*!< RPT (Bitfield-Mask: 0x07)                             */
16294 #define RTC_RTCCTL_WRTC_Pos               (0UL)                     /*!< WRTC (Bit 0)                                          */
16295 #define RTC_RTCCTL_WRTC_Msk               (0x1UL)                   /*!< WRTC (Bitfield-Mask: 0x01)                            */
16296 /* =========================================================  INTEN  ========================================================= */
16297 #define RTC_INTEN_ALM_Pos                 (0UL)                     /*!< ALM (Bit 0)                                           */
16298 #define RTC_INTEN_ALM_Msk                 (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
16299 /* ========================================================  INTSTAT  ======================================================== */
16300 #define RTC_INTSTAT_ALM_Pos               (0UL)                     /*!< ALM (Bit 0)                                           */
16301 #define RTC_INTSTAT_ALM_Msk               (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
16302 /* ========================================================  INTCLR  ========================================================= */
16303 #define RTC_INTCLR_ALM_Pos                (0UL)                     /*!< ALM (Bit 0)                                           */
16304 #define RTC_INTCLR_ALM_Msk                (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
16305 /* ========================================================  INTSET  ========================================================= */
16306 #define RTC_INTSET_ALM_Pos                (0UL)                     /*!< ALM (Bit 0)                                           */
16307 #define RTC_INTSET_ALM_Msk                (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
16308 
16309 
16310 /* =========================================================================================================================== */
16311 /* ================                                           SCARD                                           ================ */
16312 /* =========================================================================================================================== */
16313 
16314 /* ==========================================================  SR  =========================================================== */
16315 #define SCARD_SR_FHF_Pos                  (6UL)                     /*!< FHF (Bit 6)                                           */
16316 #define SCARD_SR_FHF_Msk                  (0x40UL)                  /*!< FHF (Bitfield-Mask: 0x01)                             */
16317 #define SCARD_SR_FT2REND_Pos              (5UL)                     /*!< FT2REND (Bit 5)                                       */
16318 #define SCARD_SR_FT2REND_Msk              (0x20UL)                  /*!< FT2REND (Bitfield-Mask: 0x01)                         */
16319 #define SCARD_SR_PE_Pos                   (4UL)                     /*!< PE (Bit 4)                                            */
16320 #define SCARD_SR_PE_Msk                   (0x10UL)                  /*!< PE (Bitfield-Mask: 0x01)                              */
16321 #define SCARD_SR_OVR_Pos                  (3UL)                     /*!< OVR (Bit 3)                                           */
16322 #define SCARD_SR_OVR_Msk                  (0x8UL)                   /*!< OVR (Bitfield-Mask: 0x01)                             */
16323 #define SCARD_SR_FER_Pos                  (2UL)                     /*!< FER (Bit 2)                                           */
16324 #define SCARD_SR_FER_Msk                  (0x4UL)                   /*!< FER (Bitfield-Mask: 0x01)                             */
16325 #define SCARD_SR_TBERBF_Pos               (1UL)                     /*!< TBERBF (Bit 1)                                        */
16326 #define SCARD_SR_TBERBF_Msk               (0x2UL)                   /*!< TBERBF (Bitfield-Mask: 0x01)                          */
16327 #define SCARD_SR_FNE_Pos                  (0UL)                     /*!< FNE (Bit 0)                                           */
16328 #define SCARD_SR_FNE_Msk                  (0x1UL)                   /*!< FNE (Bitfield-Mask: 0x01)                             */
16329 /* ==========================================================  IER  ========================================================== */
16330 #define SCARD_IER_FHFEN_Pos               (6UL)                     /*!< FHFEN (Bit 6)                                         */
16331 #define SCARD_IER_FHFEN_Msk               (0x40UL)                  /*!< FHFEN (Bitfield-Mask: 0x01)                           */
16332 #define SCARD_IER_FT2RENDEN_Pos           (5UL)                     /*!< FT2RENDEN (Bit 5)                                     */
16333 #define SCARD_IER_FT2RENDEN_Msk           (0x20UL)                  /*!< FT2RENDEN (Bitfield-Mask: 0x01)                       */
16334 #define SCARD_IER_PEEN_Pos                (4UL)                     /*!< PEEN (Bit 4)                                          */
16335 #define SCARD_IER_PEEN_Msk                (0x10UL)                  /*!< PEEN (Bitfield-Mask: 0x01)                            */
16336 #define SCARD_IER_OVREN_Pos               (3UL)                     /*!< OVREN (Bit 3)                                         */
16337 #define SCARD_IER_OVREN_Msk               (0x8UL)                   /*!< OVREN (Bitfield-Mask: 0x01)                           */
16338 #define SCARD_IER_FEREN_Pos               (2UL)                     /*!< FEREN (Bit 2)                                         */
16339 #define SCARD_IER_FEREN_Msk               (0x4UL)                   /*!< FEREN (Bitfield-Mask: 0x01)                           */
16340 #define SCARD_IER_TBERBFEN_Pos            (1UL)                     /*!< TBERBFEN (Bit 1)                                      */
16341 #define SCARD_IER_TBERBFEN_Msk            (0x2UL)                   /*!< TBERBFEN (Bitfield-Mask: 0x01)                        */
16342 #define SCARD_IER_FNEEN_Pos               (0UL)                     /*!< FNEEN (Bit 0)                                         */
16343 #define SCARD_IER_FNEEN_Msk               (0x1UL)                   /*!< FNEEN (Bitfield-Mask: 0x01)                           */
16344 /* ==========================================================  TCR  ========================================================== */
16345 #define SCARD_TCR_DMAMD_Pos               (7UL)                     /*!< DMAMD (Bit 7)                                         */
16346 #define SCARD_TCR_DMAMD_Msk               (0x80UL)                  /*!< DMAMD (Bitfield-Mask: 0x01)                           */
16347 #define SCARD_TCR_FIP_Pos                 (6UL)                     /*!< FIP (Bit 6)                                           */
16348 #define SCARD_TCR_FIP_Msk                 (0x40UL)                  /*!< FIP (Bitfield-Mask: 0x01)                             */
16349 #define SCARD_TCR_AUTOCONV_Pos            (5UL)                     /*!< AUTOCONV (Bit 5)                                      */
16350 #define SCARD_TCR_AUTOCONV_Msk            (0x20UL)                  /*!< AUTOCONV (Bitfield-Mask: 0x01)                        */
16351 #define SCARD_TCR_PROT_Pos                (4UL)                     /*!< PROT (Bit 4)                                          */
16352 #define SCARD_TCR_PROT_Msk                (0x10UL)                  /*!< PROT (Bitfield-Mask: 0x01)                            */
16353 #define SCARD_TCR_TR_Pos                  (3UL)                     /*!< TR (Bit 3)                                            */
16354 #define SCARD_TCR_TR_Msk                  (0x8UL)                   /*!< TR (Bitfield-Mask: 0x01)                              */
16355 #define SCARD_TCR_LCT_Pos                 (2UL)                     /*!< LCT (Bit 2)                                           */
16356 #define SCARD_TCR_LCT_Msk                 (0x4UL)                   /*!< LCT (Bitfield-Mask: 0x01)                             */
16357 #define SCARD_TCR_SS_Pos                  (1UL)                     /*!< SS (Bit 1)                                            */
16358 #define SCARD_TCR_SS_Msk                  (0x2UL)                   /*!< SS (Bitfield-Mask: 0x01)                              */
16359 #define SCARD_TCR_CONV_Pos                (0UL)                     /*!< CONV (Bit 0)                                          */
16360 #define SCARD_TCR_CONV_Msk                (0x1UL)                   /*!< CONV (Bitfield-Mask: 0x01)                            */
16361 /* ==========================================================  UCR  ========================================================== */
16362 #define SCARD_UCR_RETXEN_Pos              (3UL)                     /*!< RETXEN (Bit 3)                                        */
16363 #define SCARD_UCR_RETXEN_Msk              (0x8UL)                   /*!< RETXEN (Bitfield-Mask: 0x01)                          */
16364 #define SCARD_UCR_RSTIN_Pos               (2UL)                     /*!< RSTIN (Bit 2)                                         */
16365 #define SCARD_UCR_RSTIN_Msk               (0x4UL)                   /*!< RSTIN (Bitfield-Mask: 0x01)                           */
16366 #define SCARD_UCR_RIU_Pos                 (1UL)                     /*!< RIU (Bit 1)                                           */
16367 #define SCARD_UCR_RIU_Msk                 (0x2UL)                   /*!< RIU (Bitfield-Mask: 0x01)                             */
16368 #define SCARD_UCR_CST_Pos                 (0UL)                     /*!< CST (Bit 0)                                           */
16369 #define SCARD_UCR_CST_Msk                 (0x1UL)                   /*!< CST (Bitfield-Mask: 0x01)                             */
16370 /* ==========================================================  DR  =========================================================== */
16371 #define SCARD_DR_DR_Pos                   (0UL)                     /*!< DR (Bit 0)                                            */
16372 #define SCARD_DR_DR_Msk                   (0xffUL)                  /*!< DR (Bitfield-Mask: 0xff)                              */
16373 /* =========================================================  BPRL  ========================================================== */
16374 #define SCARD_BPRL_BPRL_Pos               (0UL)                     /*!< BPRL (Bit 0)                                          */
16375 #define SCARD_BPRL_BPRL_Msk               (0xffUL)                  /*!< BPRL (Bitfield-Mask: 0xff)                            */
16376 /* =========================================================  BPRH  ========================================================== */
16377 #define SCARD_BPRH_BPRH_Pos               (0UL)                     /*!< BPRH (Bit 0)                                          */
16378 #define SCARD_BPRH_BPRH_Msk               (0xfUL)                   /*!< BPRH (Bitfield-Mask: 0x0f)                            */
16379 /* =========================================================  UCR1  ========================================================== */
16380 #define SCARD_UCR1_ENLASTB_Pos            (5UL)                     /*!< ENLASTB (Bit 5)                                       */
16381 #define SCARD_UCR1_ENLASTB_Msk            (0x20UL)                  /*!< ENLASTB (Bitfield-Mask: 0x01)                         */
16382 #define SCARD_UCR1_CLKIOV_Pos             (4UL)                     /*!< CLKIOV (Bit 4)                                        */
16383 #define SCARD_UCR1_CLKIOV_Msk             (0x10UL)                  /*!< CLKIOV (Bitfield-Mask: 0x01)                          */
16384 #define SCARD_UCR1_T1PAREN_Pos            (3UL)                     /*!< T1PAREN (Bit 3)                                       */
16385 #define SCARD_UCR1_T1PAREN_Msk            (0x8UL)                   /*!< T1PAREN (Bitfield-Mask: 0x01)                         */
16386 #define SCARD_UCR1_STSP_Pos               (2UL)                     /*!< STSP (Bit 2)                                          */
16387 #define SCARD_UCR1_STSP_Msk               (0x4UL)                   /*!< STSP (Bitfield-Mask: 0x01)                            */
16388 #define SCARD_UCR1_PR_Pos                 (0UL)                     /*!< PR (Bit 0)                                            */
16389 #define SCARD_UCR1_PR_Msk                 (0x1UL)                   /*!< PR (Bitfield-Mask: 0x01)                              */
16390 /* ==========================================================  SR1  ========================================================== */
16391 #define SCARD_SR1_IDLE_Pos                (3UL)                     /*!< IDLE (Bit 3)                                          */
16392 #define SCARD_SR1_IDLE_Msk                (0x8UL)                   /*!< IDLE (Bitfield-Mask: 0x01)                            */
16393 #define SCARD_SR1_SYNCEND_Pos             (2UL)                     /*!< SYNCEND (Bit 2)                                       */
16394 #define SCARD_SR1_SYNCEND_Msk             (0x4UL)                   /*!< SYNCEND (Bitfield-Mask: 0x01)                         */
16395 #define SCARD_SR1_PRL_Pos                 (1UL)                     /*!< PRL (Bit 1)                                           */
16396 #define SCARD_SR1_PRL_Msk                 (0x2UL)                   /*!< PRL (Bitfield-Mask: 0x01)                             */
16397 #define SCARD_SR1_ECNTOVER_Pos            (0UL)                     /*!< ECNTOVER (Bit 0)                                      */
16398 #define SCARD_SR1_ECNTOVER_Msk            (0x1UL)                   /*!< ECNTOVER (Bitfield-Mask: 0x01)                        */
16399 /* =========================================================  IER1  ========================================================== */
16400 #define SCARD_IER1_SYNCENDEN_Pos          (2UL)                     /*!< SYNCENDEN (Bit 2)                                     */
16401 #define SCARD_IER1_SYNCENDEN_Msk          (0x4UL)                   /*!< SYNCENDEN (Bitfield-Mask: 0x01)                       */
16402 #define SCARD_IER1_PRLEN_Pos              (1UL)                     /*!< PRLEN (Bit 1)                                         */
16403 #define SCARD_IER1_PRLEN_Msk              (0x2UL)                   /*!< PRLEN (Bitfield-Mask: 0x01)                           */
16404 #define SCARD_IER1_ECNTOVEREN_Pos         (0UL)                     /*!< ECNTOVEREN (Bit 0)                                    */
16405 #define SCARD_IER1_ECNTOVEREN_Msk         (0x1UL)                   /*!< ECNTOVEREN (Bitfield-Mask: 0x01)                      */
16406 /* =========================================================  ECNTL  ========================================================= */
16407 #define SCARD_ECNTL_ECNTL_Pos             (0UL)                     /*!< ECNTL (Bit 0)                                         */
16408 #define SCARD_ECNTL_ECNTL_Msk             (0xffUL)                  /*!< ECNTL (Bitfield-Mask: 0xff)                           */
16409 /* =========================================================  ECNTH  ========================================================= */
16410 #define SCARD_ECNTH_ECNTH_Pos             (0UL)                     /*!< ECNTH (Bit 0)                                         */
16411 #define SCARD_ECNTH_ECNTH_Msk             (0xffUL)                  /*!< ECNTH (Bitfield-Mask: 0xff)                           */
16412 /* ==========================================================  GTR  ========================================================== */
16413 #define SCARD_GTR_GTR_Pos                 (0UL)                     /*!< GTR (Bit 0)                                           */
16414 #define SCARD_GTR_GTR_Msk                 (0xffUL)                  /*!< GTR (Bitfield-Mask: 0xff)                             */
16415 /* ========================================================  RETXCNT  ======================================================== */
16416 #define SCARD_RETXCNT_RETXCNT_Pos         (0UL)                     /*!< RETXCNT (Bit 0)                                       */
16417 #define SCARD_RETXCNT_RETXCNT_Msk         (0xfUL)                   /*!< RETXCNT (Bitfield-Mask: 0x0f)                         */
16418 /* ======================================================  RETXCNTRMI  ======================================================= */
16419 #define SCARD_RETXCNTRMI_RETXCNTRMI_Pos   (0UL)                     /*!< RETXCNTRMI (Bit 0)                                    */
16420 #define SCARD_RETXCNTRMI_RETXCNTRMI_Msk   (0xfUL)                   /*!< RETXCNTRMI (Bitfield-Mask: 0x0f)                      */
16421 /* ========================================================  CLKCTRL  ======================================================== */
16422 #define SCARD_CLKCTRL_APBCLKEN_Pos        (1UL)                     /*!< APBCLKEN (Bit 1)                                      */
16423 #define SCARD_CLKCTRL_APBCLKEN_Msk        (0x2UL)                   /*!< APBCLKEN (Bitfield-Mask: 0x01)                        */
16424 #define SCARD_CLKCTRL_CLKEN_Pos           (0UL)                     /*!< CLKEN (Bit 0)                                         */
16425 #define SCARD_CLKCTRL_CLKEN_Msk           (0x1UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
16426 
16427 
16428 /* =========================================================================================================================== */
16429 /* ================                                         SECURITY                                          ================ */
16430 /* =========================================================================================================================== */
16431 
16432 /* =========================================================  CTRL  ========================================================== */
16433 #define SECURITY_CTRL_CRCERROR_Pos        (31UL)                    /*!< CRCERROR (Bit 31)                                     */
16434 #define SECURITY_CTRL_CRCERROR_Msk        (0x80000000UL)            /*!< CRCERROR (Bitfield-Mask: 0x01)                        */
16435 #define SECURITY_CTRL_FUNCTION_Pos        (4UL)                     /*!< FUNCTION (Bit 4)                                      */
16436 #define SECURITY_CTRL_FUNCTION_Msk        (0xf0UL)                  /*!< FUNCTION (Bitfield-Mask: 0x0f)                        */
16437 #define SECURITY_CTRL_ENABLE_Pos          (0UL)                     /*!< ENABLE (Bit 0)                                        */
16438 #define SECURITY_CTRL_ENABLE_Msk          (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
16439 /* ========================================================  SRCADDR  ======================================================== */
16440 #define SECURITY_SRCADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
16441 #define SECURITY_SRCADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
16442 /* ==========================================================  LEN  ========================================================== */
16443 #define SECURITY_LEN_LEN_Pos              (2UL)                     /*!< LEN (Bit 2)                                           */
16444 #define SECURITY_LEN_LEN_Msk              (0xfffffcUL)              /*!< LEN (Bitfield-Mask: 0x3fffff)                         */
16445 /* ========================================================  RESULT  ========================================================= */
16446 #define SECURITY_RESULT_CRC_Pos           (0UL)                     /*!< CRC (Bit 0)                                           */
16447 #define SECURITY_RESULT_CRC_Msk           (0xffffffffUL)            /*!< CRC (Bitfield-Mask: 0xffffffff)                       */
16448 /* =======================================================  LOCKCTRL  ======================================================== */
16449 #define SECURITY_LOCKCTRL_SELECT_Pos      (0UL)                     /*!< SELECT (Bit 0)                                        */
16450 #define SECURITY_LOCKCTRL_SELECT_Msk      (0xffUL)                  /*!< SELECT (Bitfield-Mask: 0xff)                          */
16451 /* =======================================================  LOCKSTAT  ======================================================== */
16452 #define SECURITY_LOCKSTAT_STATUS_Pos      (0UL)                     /*!< STATUS (Bit 0)                                        */
16453 #define SECURITY_LOCKSTAT_STATUS_Msk      (0xffffffffUL)            /*!< STATUS (Bitfield-Mask: 0xffffffff)                    */
16454 /* =========================================================  KEY0  ========================================================== */
16455 #define SECURITY_KEY0_KEY0_Pos            (0UL)                     /*!< KEY0 (Bit 0)                                          */
16456 #define SECURITY_KEY0_KEY0_Msk            (0xffffffffUL)            /*!< KEY0 (Bitfield-Mask: 0xffffffff)                      */
16457 /* =========================================================  KEY1  ========================================================== */
16458 #define SECURITY_KEY1_KEY1_Pos            (0UL)                     /*!< KEY1 (Bit 0)                                          */
16459 #define SECURITY_KEY1_KEY1_Msk            (0xffffffffUL)            /*!< KEY1 (Bitfield-Mask: 0xffffffff)                      */
16460 /* =========================================================  KEY2  ========================================================== */
16461 #define SECURITY_KEY2_KEY2_Pos            (0UL)                     /*!< KEY2 (Bit 0)                                          */
16462 #define SECURITY_KEY2_KEY2_Msk            (0xffffffffUL)            /*!< KEY2 (Bitfield-Mask: 0xffffffff)                      */
16463 /* =========================================================  KEY3  ========================================================== */
16464 #define SECURITY_KEY3_KEY3_Pos            (0UL)                     /*!< KEY3 (Bit 0)                                          */
16465 #define SECURITY_KEY3_KEY3_Msk            (0xffffffffUL)            /*!< KEY3 (Bitfield-Mask: 0xffffffff)                      */
16466 
16467 
16468 /* =========================================================================================================================== */
16469 /* ================                                           UART0                                           ================ */
16470 /* =========================================================================================================================== */
16471 
16472 /* ==========================================================  DR  =========================================================== */
16473 #define UART0_DR_OEDATA_Pos               (11UL)                    /*!< OEDATA (Bit 11)                                       */
16474 #define UART0_DR_OEDATA_Msk               (0x800UL)                 /*!< OEDATA (Bitfield-Mask: 0x01)                          */
16475 #define UART0_DR_BEDATA_Pos               (10UL)                    /*!< BEDATA (Bit 10)                                       */
16476 #define UART0_DR_BEDATA_Msk               (0x400UL)                 /*!< BEDATA (Bitfield-Mask: 0x01)                          */
16477 #define UART0_DR_PEDATA_Pos               (9UL)                     /*!< PEDATA (Bit 9)                                        */
16478 #define UART0_DR_PEDATA_Msk               (0x200UL)                 /*!< PEDATA (Bitfield-Mask: 0x01)                          */
16479 #define UART0_DR_FEDATA_Pos               (8UL)                     /*!< FEDATA (Bit 8)                                        */
16480 #define UART0_DR_FEDATA_Msk               (0x100UL)                 /*!< FEDATA (Bitfield-Mask: 0x01)                          */
16481 #define UART0_DR_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
16482 #define UART0_DR_DATA_Msk                 (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
16483 /* ==========================================================  RSR  ========================================================== */
16484 #define UART0_RSR_OESTAT_Pos              (3UL)                     /*!< OESTAT (Bit 3)                                        */
16485 #define UART0_RSR_OESTAT_Msk              (0x8UL)                   /*!< OESTAT (Bitfield-Mask: 0x01)                          */
16486 #define UART0_RSR_BESTAT_Pos              (2UL)                     /*!< BESTAT (Bit 2)                                        */
16487 #define UART0_RSR_BESTAT_Msk              (0x4UL)                   /*!< BESTAT (Bitfield-Mask: 0x01)                          */
16488 #define UART0_RSR_PESTAT_Pos              (1UL)                     /*!< PESTAT (Bit 1)                                        */
16489 #define UART0_RSR_PESTAT_Msk              (0x2UL)                   /*!< PESTAT (Bitfield-Mask: 0x01)                          */
16490 #define UART0_RSR_FESTAT_Pos              (0UL)                     /*!< FESTAT (Bit 0)                                        */
16491 #define UART0_RSR_FESTAT_Msk              (0x1UL)                   /*!< FESTAT (Bitfield-Mask: 0x01)                          */
16492 /* ==========================================================  FR  =========================================================== */
16493 #define UART0_FR_TXBUSY_Pos               (8UL)                     /*!< TXBUSY (Bit 8)                                        */
16494 #define UART0_FR_TXBUSY_Msk               (0x100UL)                 /*!< TXBUSY (Bitfield-Mask: 0x01)                          */
16495 #define UART0_FR_TXFE_Pos                 (7UL)                     /*!< TXFE (Bit 7)                                          */
16496 #define UART0_FR_TXFE_Msk                 (0x80UL)                  /*!< TXFE (Bitfield-Mask: 0x01)                            */
16497 #define UART0_FR_RXFF_Pos                 (6UL)                     /*!< RXFF (Bit 6)                                          */
16498 #define UART0_FR_RXFF_Msk                 (0x40UL)                  /*!< RXFF (Bitfield-Mask: 0x01)                            */
16499 #define UART0_FR_TXFF_Pos                 (5UL)                     /*!< TXFF (Bit 5)                                          */
16500 #define UART0_FR_TXFF_Msk                 (0x20UL)                  /*!< TXFF (Bitfield-Mask: 0x01)                            */
16501 #define UART0_FR_RXFE_Pos                 (4UL)                     /*!< RXFE (Bit 4)                                          */
16502 #define UART0_FR_RXFE_Msk                 (0x10UL)                  /*!< RXFE (Bitfield-Mask: 0x01)                            */
16503 #define UART0_FR_BUSY_Pos                 (3UL)                     /*!< BUSY (Bit 3)                                          */
16504 #define UART0_FR_BUSY_Msk                 (0x8UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
16505 #define UART0_FR_DCD_Pos                  (2UL)                     /*!< DCD (Bit 2)                                           */
16506 #define UART0_FR_DCD_Msk                  (0x4UL)                   /*!< DCD (Bitfield-Mask: 0x01)                             */
16507 #define UART0_FR_DSR_Pos                  (1UL)                     /*!< DSR (Bit 1)                                           */
16508 #define UART0_FR_DSR_Msk                  (0x2UL)                   /*!< DSR (Bitfield-Mask: 0x01)                             */
16509 #define UART0_FR_CTS_Pos                  (0UL)                     /*!< CTS (Bit 0)                                           */
16510 #define UART0_FR_CTS_Msk                  (0x1UL)                   /*!< CTS (Bitfield-Mask: 0x01)                             */
16511 /* =========================================================  ILPR  ========================================================== */
16512 #define UART0_ILPR_ILPDVSR_Pos            (0UL)                     /*!< ILPDVSR (Bit 0)                                       */
16513 #define UART0_ILPR_ILPDVSR_Msk            (0xffUL)                  /*!< ILPDVSR (Bitfield-Mask: 0xff)                         */
16514 /* =========================================================  IBRD  ========================================================== */
16515 #define UART0_IBRD_DIVINT_Pos             (0UL)                     /*!< DIVINT (Bit 0)                                        */
16516 #define UART0_IBRD_DIVINT_Msk             (0xffffUL)                /*!< DIVINT (Bitfield-Mask: 0xffff)                        */
16517 /* =========================================================  FBRD  ========================================================== */
16518 #define UART0_FBRD_DIVFRAC_Pos            (0UL)                     /*!< DIVFRAC (Bit 0)                                       */
16519 #define UART0_FBRD_DIVFRAC_Msk            (0x3fUL)                  /*!< DIVFRAC (Bitfield-Mask: 0x3f)                         */
16520 /* =========================================================  LCRH  ========================================================== */
16521 #define UART0_LCRH_SPS_Pos                (7UL)                     /*!< SPS (Bit 7)                                           */
16522 #define UART0_LCRH_SPS_Msk                (0x80UL)                  /*!< SPS (Bitfield-Mask: 0x01)                             */
16523 #define UART0_LCRH_WLEN_Pos               (5UL)                     /*!< WLEN (Bit 5)                                          */
16524 #define UART0_LCRH_WLEN_Msk               (0x60UL)                  /*!< WLEN (Bitfield-Mask: 0x03)                            */
16525 #define UART0_LCRH_FEN_Pos                (4UL)                     /*!< FEN (Bit 4)                                           */
16526 #define UART0_LCRH_FEN_Msk                (0x10UL)                  /*!< FEN (Bitfield-Mask: 0x01)                             */
16527 #define UART0_LCRH_STP2_Pos               (3UL)                     /*!< STP2 (Bit 3)                                          */
16528 #define UART0_LCRH_STP2_Msk               (0x8UL)                   /*!< STP2 (Bitfield-Mask: 0x01)                            */
16529 #define UART0_LCRH_EPS_Pos                (2UL)                     /*!< EPS (Bit 2)                                           */
16530 #define UART0_LCRH_EPS_Msk                (0x4UL)                   /*!< EPS (Bitfield-Mask: 0x01)                             */
16531 #define UART0_LCRH_PEN_Pos                (1UL)                     /*!< PEN (Bit 1)                                           */
16532 #define UART0_LCRH_PEN_Msk                (0x2UL)                   /*!< PEN (Bitfield-Mask: 0x01)                             */
16533 #define UART0_LCRH_BRK_Pos                (0UL)                     /*!< BRK (Bit 0)                                           */
16534 #define UART0_LCRH_BRK_Msk                (0x1UL)                   /*!< BRK (Bitfield-Mask: 0x01)                             */
16535 /* ==========================================================  CR  =========================================================== */
16536 #define UART0_CR_CTSEN_Pos                (15UL)                    /*!< CTSEN (Bit 15)                                        */
16537 #define UART0_CR_CTSEN_Msk                (0x8000UL)                /*!< CTSEN (Bitfield-Mask: 0x01)                           */
16538 #define UART0_CR_RTSEN_Pos                (14UL)                    /*!< RTSEN (Bit 14)                                        */
16539 #define UART0_CR_RTSEN_Msk                (0x4000UL)                /*!< RTSEN (Bitfield-Mask: 0x01)                           */
16540 #define UART0_CR_OUT2_Pos                 (13UL)                    /*!< OUT2 (Bit 13)                                         */
16541 #define UART0_CR_OUT2_Msk                 (0x2000UL)                /*!< OUT2 (Bitfield-Mask: 0x01)                            */
16542 #define UART0_CR_OUT1_Pos                 (12UL)                    /*!< OUT1 (Bit 12)                                         */
16543 #define UART0_CR_OUT1_Msk                 (0x1000UL)                /*!< OUT1 (Bitfield-Mask: 0x01)                            */
16544 #define UART0_CR_RTS_Pos                  (11UL)                    /*!< RTS (Bit 11)                                          */
16545 #define UART0_CR_RTS_Msk                  (0x800UL)                 /*!< RTS (Bitfield-Mask: 0x01)                             */
16546 #define UART0_CR_DTR_Pos                  (10UL)                    /*!< DTR (Bit 10)                                          */
16547 #define UART0_CR_DTR_Msk                  (0x400UL)                 /*!< DTR (Bitfield-Mask: 0x01)                             */
16548 #define UART0_CR_RXE_Pos                  (9UL)                     /*!< RXE (Bit 9)                                           */
16549 #define UART0_CR_RXE_Msk                  (0x200UL)                 /*!< RXE (Bitfield-Mask: 0x01)                             */
16550 #define UART0_CR_TXE_Pos                  (8UL)                     /*!< TXE (Bit 8)                                           */
16551 #define UART0_CR_TXE_Msk                  (0x100UL)                 /*!< TXE (Bitfield-Mask: 0x01)                             */
16552 #define UART0_CR_LBE_Pos                  (7UL)                     /*!< LBE (Bit 7)                                           */
16553 #define UART0_CR_LBE_Msk                  (0x80UL)                  /*!< LBE (Bitfield-Mask: 0x01)                             */
16554 #define UART0_CR_CLKSEL_Pos               (4UL)                     /*!< CLKSEL (Bit 4)                                        */
16555 #define UART0_CR_CLKSEL_Msk               (0x70UL)                  /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
16556 #define UART0_CR_CLKEN_Pos                (3UL)                     /*!< CLKEN (Bit 3)                                         */
16557 #define UART0_CR_CLKEN_Msk                (0x8UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
16558 #define UART0_CR_SIRLP_Pos                (2UL)                     /*!< SIRLP (Bit 2)                                         */
16559 #define UART0_CR_SIRLP_Msk                (0x4UL)                   /*!< SIRLP (Bitfield-Mask: 0x01)                           */
16560 #define UART0_CR_SIREN_Pos                (1UL)                     /*!< SIREN (Bit 1)                                         */
16561 #define UART0_CR_SIREN_Msk                (0x2UL)                   /*!< SIREN (Bitfield-Mask: 0x01)                           */
16562 #define UART0_CR_UARTEN_Pos               (0UL)                     /*!< UARTEN (Bit 0)                                        */
16563 #define UART0_CR_UARTEN_Msk               (0x1UL)                   /*!< UARTEN (Bitfield-Mask: 0x01)                          */
16564 /* =========================================================  IFLS  ========================================================== */
16565 #define UART0_IFLS_RXIFLSEL_Pos           (3UL)                     /*!< RXIFLSEL (Bit 3)                                      */
16566 #define UART0_IFLS_RXIFLSEL_Msk           (0x38UL)                  /*!< RXIFLSEL (Bitfield-Mask: 0x07)                        */
16567 #define UART0_IFLS_TXIFLSEL_Pos           (0UL)                     /*!< TXIFLSEL (Bit 0)                                      */
16568 #define UART0_IFLS_TXIFLSEL_Msk           (0x7UL)                   /*!< TXIFLSEL (Bitfield-Mask: 0x07)                        */
16569 /* ==========================================================  IER  ========================================================== */
16570 #define UART0_IER_OEIM_Pos                (10UL)                    /*!< OEIM (Bit 10)                                         */
16571 #define UART0_IER_OEIM_Msk                (0x400UL)                 /*!< OEIM (Bitfield-Mask: 0x01)                            */
16572 #define UART0_IER_BEIM_Pos                (9UL)                     /*!< BEIM (Bit 9)                                          */
16573 #define UART0_IER_BEIM_Msk                (0x200UL)                 /*!< BEIM (Bitfield-Mask: 0x01)                            */
16574 #define UART0_IER_PEIM_Pos                (8UL)                     /*!< PEIM (Bit 8)                                          */
16575 #define UART0_IER_PEIM_Msk                (0x100UL)                 /*!< PEIM (Bitfield-Mask: 0x01)                            */
16576 #define UART0_IER_FEIM_Pos                (7UL)                     /*!< FEIM (Bit 7)                                          */
16577 #define UART0_IER_FEIM_Msk                (0x80UL)                  /*!< FEIM (Bitfield-Mask: 0x01)                            */
16578 #define UART0_IER_RTIM_Pos                (6UL)                     /*!< RTIM (Bit 6)                                          */
16579 #define UART0_IER_RTIM_Msk                (0x40UL)                  /*!< RTIM (Bitfield-Mask: 0x01)                            */
16580 #define UART0_IER_TXIM_Pos                (5UL)                     /*!< TXIM (Bit 5)                                          */
16581 #define UART0_IER_TXIM_Msk                (0x20UL)                  /*!< TXIM (Bitfield-Mask: 0x01)                            */
16582 #define UART0_IER_RXIM_Pos                (4UL)                     /*!< RXIM (Bit 4)                                          */
16583 #define UART0_IER_RXIM_Msk                (0x10UL)                  /*!< RXIM (Bitfield-Mask: 0x01)                            */
16584 #define UART0_IER_DSRMIM_Pos              (3UL)                     /*!< DSRMIM (Bit 3)                                        */
16585 #define UART0_IER_DSRMIM_Msk              (0x8UL)                   /*!< DSRMIM (Bitfield-Mask: 0x01)                          */
16586 #define UART0_IER_DCDMIM_Pos              (2UL)                     /*!< DCDMIM (Bit 2)                                        */
16587 #define UART0_IER_DCDMIM_Msk              (0x4UL)                   /*!< DCDMIM (Bitfield-Mask: 0x01)                          */
16588 #define UART0_IER_CTSMIM_Pos              (1UL)                     /*!< CTSMIM (Bit 1)                                        */
16589 #define UART0_IER_CTSMIM_Msk              (0x2UL)                   /*!< CTSMIM (Bitfield-Mask: 0x01)                          */
16590 #define UART0_IER_TXCMPMIM_Pos            (0UL)                     /*!< TXCMPMIM (Bit 0)                                      */
16591 #define UART0_IER_TXCMPMIM_Msk            (0x1UL)                   /*!< TXCMPMIM (Bitfield-Mask: 0x01)                        */
16592 /* ==========================================================  IES  ========================================================== */
16593 #define UART0_IES_OERIS_Pos               (10UL)                    /*!< OERIS (Bit 10)                                        */
16594 #define UART0_IES_OERIS_Msk               (0x400UL)                 /*!< OERIS (Bitfield-Mask: 0x01)                           */
16595 #define UART0_IES_BERIS_Pos               (9UL)                     /*!< BERIS (Bit 9)                                         */
16596 #define UART0_IES_BERIS_Msk               (0x200UL)                 /*!< BERIS (Bitfield-Mask: 0x01)                           */
16597 #define UART0_IES_PERIS_Pos               (8UL)                     /*!< PERIS (Bit 8)                                         */
16598 #define UART0_IES_PERIS_Msk               (0x100UL)                 /*!< PERIS (Bitfield-Mask: 0x01)                           */
16599 #define UART0_IES_FERIS_Pos               (7UL)                     /*!< FERIS (Bit 7)                                         */
16600 #define UART0_IES_FERIS_Msk               (0x80UL)                  /*!< FERIS (Bitfield-Mask: 0x01)                           */
16601 #define UART0_IES_RTRIS_Pos               (6UL)                     /*!< RTRIS (Bit 6)                                         */
16602 #define UART0_IES_RTRIS_Msk               (0x40UL)                  /*!< RTRIS (Bitfield-Mask: 0x01)                           */
16603 #define UART0_IES_TXRIS_Pos               (5UL)                     /*!< TXRIS (Bit 5)                                         */
16604 #define UART0_IES_TXRIS_Msk               (0x20UL)                  /*!< TXRIS (Bitfield-Mask: 0x01)                           */
16605 #define UART0_IES_RXRIS_Pos               (4UL)                     /*!< RXRIS (Bit 4)                                         */
16606 #define UART0_IES_RXRIS_Msk               (0x10UL)                  /*!< RXRIS (Bitfield-Mask: 0x01)                           */
16607 #define UART0_IES_DSRMRIS_Pos             (3UL)                     /*!< DSRMRIS (Bit 3)                                       */
16608 #define UART0_IES_DSRMRIS_Msk             (0x8UL)                   /*!< DSRMRIS (Bitfield-Mask: 0x01)                         */
16609 #define UART0_IES_DCDMRIS_Pos             (2UL)                     /*!< DCDMRIS (Bit 2)                                       */
16610 #define UART0_IES_DCDMRIS_Msk             (0x4UL)                   /*!< DCDMRIS (Bitfield-Mask: 0x01)                         */
16611 #define UART0_IES_CTSMRIS_Pos             (1UL)                     /*!< CTSMRIS (Bit 1)                                       */
16612 #define UART0_IES_CTSMRIS_Msk             (0x2UL)                   /*!< CTSMRIS (Bitfield-Mask: 0x01)                         */
16613 #define UART0_IES_TXCMPMRIS_Pos           (0UL)                     /*!< TXCMPMRIS (Bit 0)                                     */
16614 #define UART0_IES_TXCMPMRIS_Msk           (0x1UL)                   /*!< TXCMPMRIS (Bitfield-Mask: 0x01)                       */
16615 /* ==========================================================  MIS  ========================================================== */
16616 #define UART0_MIS_OEMIS_Pos               (10UL)                    /*!< OEMIS (Bit 10)                                        */
16617 #define UART0_MIS_OEMIS_Msk               (0x400UL)                 /*!< OEMIS (Bitfield-Mask: 0x01)                           */
16618 #define UART0_MIS_BEMIS_Pos               (9UL)                     /*!< BEMIS (Bit 9)                                         */
16619 #define UART0_MIS_BEMIS_Msk               (0x200UL)                 /*!< BEMIS (Bitfield-Mask: 0x01)                           */
16620 #define UART0_MIS_PEMIS_Pos               (8UL)                     /*!< PEMIS (Bit 8)                                         */
16621 #define UART0_MIS_PEMIS_Msk               (0x100UL)                 /*!< PEMIS (Bitfield-Mask: 0x01)                           */
16622 #define UART0_MIS_FEMIS_Pos               (7UL)                     /*!< FEMIS (Bit 7)                                         */
16623 #define UART0_MIS_FEMIS_Msk               (0x80UL)                  /*!< FEMIS (Bitfield-Mask: 0x01)                           */
16624 #define UART0_MIS_RTMIS_Pos               (6UL)                     /*!< RTMIS (Bit 6)                                         */
16625 #define UART0_MIS_RTMIS_Msk               (0x40UL)                  /*!< RTMIS (Bitfield-Mask: 0x01)                           */
16626 #define UART0_MIS_TXMIS_Pos               (5UL)                     /*!< TXMIS (Bit 5)                                         */
16627 #define UART0_MIS_TXMIS_Msk               (0x20UL)                  /*!< TXMIS (Bitfield-Mask: 0x01)                           */
16628 #define UART0_MIS_RXMIS_Pos               (4UL)                     /*!< RXMIS (Bit 4)                                         */
16629 #define UART0_MIS_RXMIS_Msk               (0x10UL)                  /*!< RXMIS (Bitfield-Mask: 0x01)                           */
16630 #define UART0_MIS_DSRMMIS_Pos             (3UL)                     /*!< DSRMMIS (Bit 3)                                       */
16631 #define UART0_MIS_DSRMMIS_Msk             (0x8UL)                   /*!< DSRMMIS (Bitfield-Mask: 0x01)                         */
16632 #define UART0_MIS_DCDMMIS_Pos             (2UL)                     /*!< DCDMMIS (Bit 2)                                       */
16633 #define UART0_MIS_DCDMMIS_Msk             (0x4UL)                   /*!< DCDMMIS (Bitfield-Mask: 0x01)                         */
16634 #define UART0_MIS_CTSMMIS_Pos             (1UL)                     /*!< CTSMMIS (Bit 1)                                       */
16635 #define UART0_MIS_CTSMMIS_Msk             (0x2UL)                   /*!< CTSMMIS (Bitfield-Mask: 0x01)                         */
16636 #define UART0_MIS_TXCMPMMIS_Pos           (0UL)                     /*!< TXCMPMMIS (Bit 0)                                     */
16637 #define UART0_MIS_TXCMPMMIS_Msk           (0x1UL)                   /*!< TXCMPMMIS (Bitfield-Mask: 0x01)                       */
16638 /* ==========================================================  IEC  ========================================================== */
16639 #define UART0_IEC_OEIC_Pos                (10UL)                    /*!< OEIC (Bit 10)                                         */
16640 #define UART0_IEC_OEIC_Msk                (0x400UL)                 /*!< OEIC (Bitfield-Mask: 0x01)                            */
16641 #define UART0_IEC_BEIC_Pos                (9UL)                     /*!< BEIC (Bit 9)                                          */
16642 #define UART0_IEC_BEIC_Msk                (0x200UL)                 /*!< BEIC (Bitfield-Mask: 0x01)                            */
16643 #define UART0_IEC_PEIC_Pos                (8UL)                     /*!< PEIC (Bit 8)                                          */
16644 #define UART0_IEC_PEIC_Msk                (0x100UL)                 /*!< PEIC (Bitfield-Mask: 0x01)                            */
16645 #define UART0_IEC_FEIC_Pos                (7UL)                     /*!< FEIC (Bit 7)                                          */
16646 #define UART0_IEC_FEIC_Msk                (0x80UL)                  /*!< FEIC (Bitfield-Mask: 0x01)                            */
16647 #define UART0_IEC_RTIC_Pos                (6UL)                     /*!< RTIC (Bit 6)                                          */
16648 #define UART0_IEC_RTIC_Msk                (0x40UL)                  /*!< RTIC (Bitfield-Mask: 0x01)                            */
16649 #define UART0_IEC_TXIC_Pos                (5UL)                     /*!< TXIC (Bit 5)                                          */
16650 #define UART0_IEC_TXIC_Msk                (0x20UL)                  /*!< TXIC (Bitfield-Mask: 0x01)                            */
16651 #define UART0_IEC_RXIC_Pos                (4UL)                     /*!< RXIC (Bit 4)                                          */
16652 #define UART0_IEC_RXIC_Msk                (0x10UL)                  /*!< RXIC (Bitfield-Mask: 0x01)                            */
16653 #define UART0_IEC_DSRMIC_Pos              (3UL)                     /*!< DSRMIC (Bit 3)                                        */
16654 #define UART0_IEC_DSRMIC_Msk              (0x8UL)                   /*!< DSRMIC (Bitfield-Mask: 0x01)                          */
16655 #define UART0_IEC_DCDMIC_Pos              (2UL)                     /*!< DCDMIC (Bit 2)                                        */
16656 #define UART0_IEC_DCDMIC_Msk              (0x4UL)                   /*!< DCDMIC (Bitfield-Mask: 0x01)                          */
16657 #define UART0_IEC_CTSMIC_Pos              (1UL)                     /*!< CTSMIC (Bit 1)                                        */
16658 #define UART0_IEC_CTSMIC_Msk              (0x2UL)                   /*!< CTSMIC (Bitfield-Mask: 0x01)                          */
16659 #define UART0_IEC_TXCMPMIC_Pos            (0UL)                     /*!< TXCMPMIC (Bit 0)                                      */
16660 #define UART0_IEC_TXCMPMIC_Msk            (0x1UL)                   /*!< TXCMPMIC (Bitfield-Mask: 0x01)                        */
16661 
16662 
16663 /* =========================================================================================================================== */
16664 /* ================                                           VCOMP                                           ================ */
16665 /* =========================================================================================================================== */
16666 
16667 /* ==========================================================  CFG  ========================================================== */
16668 #define VCOMP_CFG_LVLSEL_Pos              (16UL)                    /*!< LVLSEL (Bit 16)                                       */
16669 #define VCOMP_CFG_LVLSEL_Msk              (0xf0000UL)               /*!< LVLSEL (Bitfield-Mask: 0x0f)                          */
16670 #define VCOMP_CFG_NSEL_Pos                (8UL)                     /*!< NSEL (Bit 8)                                          */
16671 #define VCOMP_CFG_NSEL_Msk                (0x300UL)                 /*!< NSEL (Bitfield-Mask: 0x03)                            */
16672 #define VCOMP_CFG_PSEL_Pos                (0UL)                     /*!< PSEL (Bit 0)                                          */
16673 #define VCOMP_CFG_PSEL_Msk                (0x3UL)                   /*!< PSEL (Bitfield-Mask: 0x03)                            */
16674 /* =========================================================  STAT  ========================================================== */
16675 #define VCOMP_STAT_PWDSTAT_Pos            (1UL)                     /*!< PWDSTAT (Bit 1)                                       */
16676 #define VCOMP_STAT_PWDSTAT_Msk            (0x2UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
16677 #define VCOMP_STAT_CMPOUT_Pos             (0UL)                     /*!< CMPOUT (Bit 0)                                        */
16678 #define VCOMP_STAT_CMPOUT_Msk             (0x1UL)                   /*!< CMPOUT (Bitfield-Mask: 0x01)                          */
16679 /* ========================================================  PWDKEY  ========================================================= */
16680 #define VCOMP_PWDKEY_PWDKEY_Pos           (0UL)                     /*!< PWDKEY (Bit 0)                                        */
16681 #define VCOMP_PWDKEY_PWDKEY_Msk           (0xffffffffUL)            /*!< PWDKEY (Bitfield-Mask: 0xffffffff)                    */
16682 /* =========================================================  INTEN  ========================================================= */
16683 #define VCOMP_INTEN_OUTHI_Pos             (1UL)                     /*!< OUTHI (Bit 1)                                         */
16684 #define VCOMP_INTEN_OUTHI_Msk             (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
16685 #define VCOMP_INTEN_OUTLOW_Pos            (0UL)                     /*!< OUTLOW (Bit 0)                                        */
16686 #define VCOMP_INTEN_OUTLOW_Msk            (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
16687 /* ========================================================  INTSTAT  ======================================================== */
16688 #define VCOMP_INTSTAT_OUTHI_Pos           (1UL)                     /*!< OUTHI (Bit 1)                                         */
16689 #define VCOMP_INTSTAT_OUTHI_Msk           (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
16690 #define VCOMP_INTSTAT_OUTLOW_Pos          (0UL)                     /*!< OUTLOW (Bit 0)                                        */
16691 #define VCOMP_INTSTAT_OUTLOW_Msk          (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
16692 /* ========================================================  INTCLR  ========================================================= */
16693 #define VCOMP_INTCLR_OUTHI_Pos            (1UL)                     /*!< OUTHI (Bit 1)                                         */
16694 #define VCOMP_INTCLR_OUTHI_Msk            (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
16695 #define VCOMP_INTCLR_OUTLOW_Pos           (0UL)                     /*!< OUTLOW (Bit 0)                                        */
16696 #define VCOMP_INTCLR_OUTLOW_Msk           (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
16697 /* ========================================================  INTSET  ========================================================= */
16698 #define VCOMP_INTSET_OUTHI_Pos            (1UL)                     /*!< OUTHI (Bit 1)                                         */
16699 #define VCOMP_INTSET_OUTHI_Msk            (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
16700 #define VCOMP_INTSET_OUTLOW_Pos           (0UL)                     /*!< OUTLOW (Bit 0)                                        */
16701 #define VCOMP_INTSET_OUTLOW_Msk           (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
16702 
16703 
16704 /* =========================================================================================================================== */
16705 /* ================                                            WDT                                            ================ */
16706 /* =========================================================================================================================== */
16707 
16708 /* ==========================================================  CFG  ========================================================== */
16709 #define WDT_CFG_CLKSEL_Pos                (24UL)                    /*!< CLKSEL (Bit 24)                                       */
16710 #define WDT_CFG_CLKSEL_Msk                (0x7000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
16711 #define WDT_CFG_INTVAL_Pos                (16UL)                    /*!< INTVAL (Bit 16)                                       */
16712 #define WDT_CFG_INTVAL_Msk                (0xff0000UL)              /*!< INTVAL (Bitfield-Mask: 0xff)                          */
16713 #define WDT_CFG_RESVAL_Pos                (8UL)                     /*!< RESVAL (Bit 8)                                        */
16714 #define WDT_CFG_RESVAL_Msk                (0xff00UL)                /*!< RESVAL (Bitfield-Mask: 0xff)                          */
16715 #define WDT_CFG_RESEN_Pos                 (2UL)                     /*!< RESEN (Bit 2)                                         */
16716 #define WDT_CFG_RESEN_Msk                 (0x4UL)                   /*!< RESEN (Bitfield-Mask: 0x01)                           */
16717 #define WDT_CFG_INTEN_Pos                 (1UL)                     /*!< INTEN (Bit 1)                                         */
16718 #define WDT_CFG_INTEN_Msk                 (0x2UL)                   /*!< INTEN (Bitfield-Mask: 0x01)                           */
16719 #define WDT_CFG_WDTEN_Pos                 (0UL)                     /*!< WDTEN (Bit 0)                                         */
16720 #define WDT_CFG_WDTEN_Msk                 (0x1UL)                   /*!< WDTEN (Bitfield-Mask: 0x01)                           */
16721 /* =========================================================  RSTRT  ========================================================= */
16722 #define WDT_RSTRT_RSTRT_Pos               (0UL)                     /*!< RSTRT (Bit 0)                                         */
16723 #define WDT_RSTRT_RSTRT_Msk               (0xffUL)                  /*!< RSTRT (Bitfield-Mask: 0xff)                           */
16724 /* =========================================================  LOCK  ========================================================== */
16725 #define WDT_LOCK_LOCK_Pos                 (0UL)                     /*!< LOCK (Bit 0)                                          */
16726 #define WDT_LOCK_LOCK_Msk                 (0xffUL)                  /*!< LOCK (Bitfield-Mask: 0xff)                            */
16727 /* =========================================================  COUNT  ========================================================= */
16728 #define WDT_COUNT_COUNT_Pos               (0UL)                     /*!< COUNT (Bit 0)                                         */
16729 #define WDT_COUNT_COUNT_Msk               (0xffUL)                  /*!< COUNT (Bitfield-Mask: 0xff)                           */
16730 /* =========================================================  INTEN  ========================================================= */
16731 #define WDT_INTEN_WDTINT_Pos              (0UL)                     /*!< WDTINT (Bit 0)                                        */
16732 #define WDT_INTEN_WDTINT_Msk              (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
16733 /* ========================================================  INTSTAT  ======================================================== */
16734 #define WDT_INTSTAT_WDTINT_Pos            (0UL)                     /*!< WDTINT (Bit 0)                                        */
16735 #define WDT_INTSTAT_WDTINT_Msk            (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
16736 /* ========================================================  INTCLR  ========================================================= */
16737 #define WDT_INTCLR_WDTINT_Pos             (0UL)                     /*!< WDTINT (Bit 0)                                        */
16738 #define WDT_INTCLR_WDTINT_Msk             (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
16739 /* ========================================================  INTSET  ========================================================= */
16740 #define WDT_INTSET_WDTINT_Pos             (0UL)                     /*!< WDTINT (Bit 0)                                        */
16741 #define WDT_INTSET_WDTINT_Msk             (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
16742 
16743 /** @} */ /* End of group PosMask_peripherals */
16744 
16745 
16746 /* =========================================================================================================================== */
16747 /* ================                           Enumerated Values Peripheral Section                            ================ */
16748 /* =========================================================================================================================== */
16749 
16750 
16751 /** @addtogroup EnumValue_peripherals
16752   * @{
16753   */
16754 
16755 
16756 
16757 /* =========================================================================================================================== */
16758 /* ================                                            ADC                                            ================ */
16759 /* =========================================================================================================================== */
16760 
16761 /* ==========================================================  CFG  ========================================================== */
16762 /* ================================================  ADC CFG CLKSEL [24..25]  ================================================ */
16763 typedef enum {                                  /*!< ADC_CFG_CLKSEL                                                            */
16764   ADC_CFG_CLKSEL_OFF                   = 0,     /*!< OFF : Off mode. The HFRC or HFRC_DIV2 clock must be selected
16765                                                      for the ADC to function. The ADC controller automatically
16766                                                      shuts off the clock in it's low power modes. When setting
16767                                                      ADCEN to '0', the CLKSEL should remain set to one of the
16768                                                      two clock selects for proper power down sequencing.                       */
16769   ADC_CFG_CLKSEL_HFRC                  = 1,     /*!< HFRC : HFRC Core Clock divided by (CORESEL+1)                             */
16770   ADC_CFG_CLKSEL_HFRC_DIV2             = 2,     /*!< HFRC_DIV2 : HFRC Core Clock / 2 further divided by (CORESEL+1)            */
16771 } ADC_CFG_CLKSEL_Enum;
16772 
16773 /* ===============================================  ADC CFG TRIGPOL [19..19]  ================================================ */
16774 typedef enum {                                  /*!< ADC_CFG_TRIGPOL                                                           */
16775   ADC_CFG_TRIGPOL_RISING_EDGE          = 0,     /*!< RISING_EDGE : Trigger on rising edge.                                     */
16776   ADC_CFG_TRIGPOL_FALLING_EDGE         = 1,     /*!< FALLING_EDGE : Trigger on falling edge.                                   */
16777 } ADC_CFG_TRIGPOL_Enum;
16778 
16779 /* ===============================================  ADC CFG TRIGSEL [16..18]  ================================================ */
16780 typedef enum {                                  /*!< ADC_CFG_TRIGSEL                                                           */
16781   ADC_CFG_TRIGSEL_EXT0                 = 0,     /*!< EXT0 : Off chip External Trigger0 (ADC_ET0)                               */
16782   ADC_CFG_TRIGSEL_EXT1                 = 1,     /*!< EXT1 : Off chip External Trigger1 (ADC_ET1)                               */
16783   ADC_CFG_TRIGSEL_EXT2                 = 2,     /*!< EXT2 : Off chip External Trigger2 (ADC_ET2)                               */
16784   ADC_CFG_TRIGSEL_EXT3                 = 3,     /*!< EXT3 : Off chip External Trigger3 (ADC_ET3)                               */
16785   ADC_CFG_TRIGSEL_VCOMP                = 4,     /*!< VCOMP : Voltage Comparator Output                                         */
16786   ADC_CFG_TRIGSEL_SWT                  = 7,     /*!< SWT : Software Trigger                                                    */
16787 } ADC_CFG_TRIGSEL_Enum;
16788 
16789 /* ==============================================  ADC CFG DFIFORDEN [12..12]  =============================================== */
16790 typedef enum {                                  /*!< ADC_CFG_DFIFORDEN                                                         */
16791   ADC_CFG_DFIFORDEN_DIS                = 0,     /*!< DIS : Destructive Reads are prevented. Reads to the FIFOPR register
16792                                                      will not POP an entry off the FIFO.                                       */
16793   ADC_CFG_DFIFORDEN_EN                 = 1,     /*!< EN : Reads to the FIFOPR register will automatically pop an
16794                                                      entry off the FIFO.                                                       */
16795 } ADC_CFG_DFIFORDEN_Enum;
16796 
16797 /* =================================================  ADC CFG REFSEL [8..9]  ================================================= */
16798 typedef enum {                                  /*!< ADC_CFG_REFSEL                                                            */
16799   ADC_CFG_REFSEL_INT2P0                = 0,     /*!< INT2P0 : Internal 2.0V Bandgap Reference Voltage                          */
16800   ADC_CFG_REFSEL_INT1P5                = 1,     /*!< INT1P5 : Internal 1.5V Bandgap Reference Voltage                          */
16801   ADC_CFG_REFSEL_EXT2P0                = 2,     /*!< EXT2P0 : Off Chip 2.0V Reference                                          */
16802   ADC_CFG_REFSEL_EXT1P5                = 3,     /*!< EXT1P5 : Off Chip 1.5V Reference                                          */
16803 } ADC_CFG_REFSEL_Enum;
16804 
16805 /* =================================================  ADC CFG CKMODE [4..4]  ================================================= */
16806 typedef enum {                                  /*!< ADC_CFG_CKMODE                                                            */
16807   ADC_CFG_CKMODE_LPCKMODE              = 0,     /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set
16808                                                      LPCKMODE to 0x1 while configuring the ADC.                                */
16809   ADC_CFG_CKMODE_LLCKMODE              = 1,     /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk
16810                                                      will remain on while in functioning in LPMODE0.                           */
16811 } ADC_CFG_CKMODE_Enum;
16812 
16813 /* =================================================  ADC CFG LPMODE [3..3]  ================================================= */
16814 typedef enum {                                  /*!< ADC_CFG_LPMODE                                                            */
16815   ADC_CFG_LPMODE_MODE0                 = 0,     /*!< MODE0 : Low Power Mode 0. Leaves the ADC fully powered between
16816                                                      scans with minimum latency between a trigger event and
16817                                                      sample data collection.                                                   */
16818   ADC_CFG_LPMODE_MODE1                 = 1,     /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks
16819                                                      associated with the ADC until the next trigger event. Between
16820                                                      scans, the reference buffer requires up to 50us of delay
16821                                                      from a scan trigger event before the conversion will commence
16822                                                      while operating in this mode.                                             */
16823 } ADC_CFG_LPMODE_Enum;
16824 
16825 /* =================================================  ADC CFG RPTEN [2..2]  ================================================== */
16826 typedef enum {                                  /*!< ADC_CFG_RPTEN                                                             */
16827   ADC_CFG_RPTEN_SINGLE_SCAN            = 0,     /*!< SINGLE_SCAN : In Single Scan Mode, the ADC will complete a single
16828                                                      scan upon each trigger event.                                             */
16829   ADC_CFG_RPTEN_REPEATING_SCAN         = 1,     /*!< REPEATING_SCAN : In Repeating Scan Mode, the ADC will complete
16830                                                      it's first scan upon the initial trigger event and all
16831                                                      subsequent scans will occur at regular intervals defined
16832                                                      by the configuration programmed for the CTTMRA3 internal
16833                                                      timer until the timer is disabled or the ADC is disabled.
16834                                                      When disabling the ADC (setting ADCEN to '0'), the RPTEN
16835                                                      bit should be cleared.                                                    */
16836 } ADC_CFG_RPTEN_Enum;
16837 
16838 /* =================================================  ADC CFG ADCEN [0..0]  ================================================== */
16839 typedef enum {                                  /*!< ADC_CFG_ADCEN                                                             */
16840   ADC_CFG_ADCEN_DIS                    = 0,     /*!< DIS : Disable the ADC module.                                             */
16841   ADC_CFG_ADCEN_EN                     = 1,     /*!< EN : Enable the ADC module.                                               */
16842 } ADC_CFG_ADCEN_Enum;
16843 
16844 /* =========================================================  STAT  ========================================================== */
16845 /* ================================================  ADC STAT PWDSTAT [0..0]  ================================================ */
16846 typedef enum {                                  /*!< ADC_STAT_PWDSTAT                                                          */
16847   ADC_STAT_PWDSTAT_ON                  = 0,     /*!< ON : Powered on.                                                          */
16848   ADC_STAT_PWDSTAT_POWERED_DOWN        = 1,     /*!< POWERED_DOWN : ADC Low Power Mode 1.                                      */
16849 } ADC_STAT_PWDSTAT_Enum;
16850 
16851 /* ==========================================================  SWT  ========================================================== */
16852 /* ==================================================  ADC SWT SWT [0..7]  =================================================== */
16853 typedef enum {                                  /*!< ADC_SWT_SWT                                                               */
16854   ADC_SWT_SWT_GEN_SW_TRIGGER           = 55,    /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger.         */
16855 } ADC_SWT_SWT_Enum;
16856 
16857 /* ========================================================  SL0CFG  ========================================================= */
16858 /* ==============================================  ADC SL0CFG ADSEL0 [24..26]  =============================================== */
16859 typedef enum {                                  /*!< ADC_SL0CFG_ADSEL0                                                         */
16860   ADC_SL0CFG_ADSEL0_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
16861                                                      module for this slot.                                                     */
16862   ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
16863                                                      module for this slot.                                                     */
16864   ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
16865                                                      module for this slot.                                                     */
16866   ADC_SL0CFG_ADSEL0_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
16867                                                      module for this slot.                                                     */
16868   ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
16869                                                      divide module for this slot.                                              */
16870   ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
16871                                                      divide module for this slot.                                              */
16872   ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
16873                                                      divide module for this slot.                                              */
16874   ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
16875                                                      divide module for this slot.                                              */
16876 } ADC_SL0CFG_ADSEL0_Enum;
16877 
16878 /* ==============================================  ADC SL0CFG PRMODE0 [16..17]  ============================================== */
16879 typedef enum {                                  /*!< ADC_SL0CFG_PRMODE0                                                        */
16880   ADC_SL0CFG_PRMODE0_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
16881   ADC_SL0CFG_PRMODE0_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
16882   ADC_SL0CFG_PRMODE0_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
16883   ADC_SL0CFG_PRMODE0_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
16884 } ADC_SL0CFG_PRMODE0_Enum;
16885 
16886 /* ===============================================  ADC SL0CFG CHSEL0 [8..11]  =============================================== */
16887 typedef enum {                                  /*!< ADC_SL0CFG_CHSEL0                                                         */
16888   ADC_SL0CFG_CHSEL0_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
16889   ADC_SL0CFG_CHSEL0_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
16890   ADC_SL0CFG_CHSEL0_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
16891   ADC_SL0CFG_CHSEL0_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
16892   ADC_SL0CFG_CHSEL0_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
16893   ADC_SL0CFG_CHSEL0_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
16894   ADC_SL0CFG_CHSEL0_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
16895   ADC_SL0CFG_CHSEL0_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
16896   ADC_SL0CFG_CHSEL0_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
16897   ADC_SL0CFG_CHSEL0_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
16898   ADC_SL0CFG_CHSEL0_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
16899                                                      pad13(P).                                                                 */
16900   ADC_SL0CFG_CHSEL0_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
16901                                                      pad14(P).                                                                 */
16902   ADC_SL0CFG_CHSEL0_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
16903   ADC_SL0CFG_CHSEL0_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
16904   ADC_SL0CFG_CHSEL0_VSS                = 14,    /*!< VSS : Input VSS                                                           */
16905 } ADC_SL0CFG_CHSEL0_Enum;
16906 
16907 /* ================================================  ADC SL0CFG WCEN0 [1..1]  ================================================ */
16908 typedef enum {                                  /*!< ADC_SL0CFG_WCEN0                                                          */
16909   ADC_SL0CFG_WCEN0_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 0.                              */
16910 } ADC_SL0CFG_WCEN0_Enum;
16911 
16912 /* ================================================  ADC SL0CFG SLEN0 [0..0]  ================================================ */
16913 typedef enum {                                  /*!< ADC_SL0CFG_SLEN0                                                          */
16914   ADC_SL0CFG_SLEN0_SLEN                = 1,     /*!< SLEN : Enable slot 0 for ADC conversions.                                 */
16915 } ADC_SL0CFG_SLEN0_Enum;
16916 
16917 /* ========================================================  SL1CFG  ========================================================= */
16918 /* ==============================================  ADC SL1CFG ADSEL1 [24..26]  =============================================== */
16919 typedef enum {                                  /*!< ADC_SL1CFG_ADSEL1                                                         */
16920   ADC_SL1CFG_ADSEL1_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
16921                                                      module for this slot.                                                     */
16922   ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
16923                                                      module for this slot.                                                     */
16924   ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
16925                                                      module for this slot.                                                     */
16926   ADC_SL1CFG_ADSEL1_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
16927                                                      module for this slot.                                                     */
16928   ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
16929                                                      divide module for this slot.                                              */
16930   ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
16931                                                      divide module for this slot.                                              */
16932   ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
16933                                                      divide module for this slot.                                              */
16934   ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
16935                                                      divide module for this slot.                                              */
16936 } ADC_SL1CFG_ADSEL1_Enum;
16937 
16938 /* ==============================================  ADC SL1CFG PRMODE1 [16..17]  ============================================== */
16939 typedef enum {                                  /*!< ADC_SL1CFG_PRMODE1                                                        */
16940   ADC_SL1CFG_PRMODE1_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
16941   ADC_SL1CFG_PRMODE1_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
16942   ADC_SL1CFG_PRMODE1_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
16943   ADC_SL1CFG_PRMODE1_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
16944 } ADC_SL1CFG_PRMODE1_Enum;
16945 
16946 /* ===============================================  ADC SL1CFG CHSEL1 [8..11]  =============================================== */
16947 typedef enum {                                  /*!< ADC_SL1CFG_CHSEL1                                                         */
16948   ADC_SL1CFG_CHSEL1_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
16949   ADC_SL1CFG_CHSEL1_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
16950   ADC_SL1CFG_CHSEL1_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
16951   ADC_SL1CFG_CHSEL1_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
16952   ADC_SL1CFG_CHSEL1_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
16953   ADC_SL1CFG_CHSEL1_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
16954   ADC_SL1CFG_CHSEL1_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
16955   ADC_SL1CFG_CHSEL1_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
16956   ADC_SL1CFG_CHSEL1_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
16957   ADC_SL1CFG_CHSEL1_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
16958   ADC_SL1CFG_CHSEL1_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
16959                                                      pad13(P).                                                                 */
16960   ADC_SL1CFG_CHSEL1_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
16961                                                      pad14(P).                                                                 */
16962   ADC_SL1CFG_CHSEL1_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
16963   ADC_SL1CFG_CHSEL1_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
16964   ADC_SL1CFG_CHSEL1_VSS                = 14,    /*!< VSS : Input VSS                                                           */
16965 } ADC_SL1CFG_CHSEL1_Enum;
16966 
16967 /* ================================================  ADC SL1CFG WCEN1 [1..1]  ================================================ */
16968 typedef enum {                                  /*!< ADC_SL1CFG_WCEN1                                                          */
16969   ADC_SL1CFG_WCEN1_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 1.                              */
16970 } ADC_SL1CFG_WCEN1_Enum;
16971 
16972 /* ================================================  ADC SL1CFG SLEN1 [0..0]  ================================================ */
16973 typedef enum {                                  /*!< ADC_SL1CFG_SLEN1                                                          */
16974   ADC_SL1CFG_SLEN1_SLEN                = 1,     /*!< SLEN : Enable slot 1 for ADC conversions.                                 */
16975 } ADC_SL1CFG_SLEN1_Enum;
16976 
16977 /* ========================================================  SL2CFG  ========================================================= */
16978 /* ==============================================  ADC SL2CFG ADSEL2 [24..26]  =============================================== */
16979 typedef enum {                                  /*!< ADC_SL2CFG_ADSEL2                                                         */
16980   ADC_SL2CFG_ADSEL2_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
16981                                                      module for this slot.                                                     */
16982   ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
16983                                                      module for this slot.                                                     */
16984   ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
16985                                                      module for this slot.                                                     */
16986   ADC_SL2CFG_ADSEL2_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
16987                                                      module for this slot.                                                     */
16988   ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
16989                                                      divide module for this slot.                                              */
16990   ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
16991                                                      divide module for this slot.                                              */
16992   ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
16993                                                      divide module for this slot.                                              */
16994   ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
16995                                                      divide module for this slot.                                              */
16996 } ADC_SL2CFG_ADSEL2_Enum;
16997 
16998 /* ==============================================  ADC SL2CFG PRMODE2 [16..17]  ============================================== */
16999 typedef enum {                                  /*!< ADC_SL2CFG_PRMODE2                                                        */
17000   ADC_SL2CFG_PRMODE2_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
17001   ADC_SL2CFG_PRMODE2_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
17002   ADC_SL2CFG_PRMODE2_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
17003   ADC_SL2CFG_PRMODE2_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
17004 } ADC_SL2CFG_PRMODE2_Enum;
17005 
17006 /* ===============================================  ADC SL2CFG CHSEL2 [8..11]  =============================================== */
17007 typedef enum {                                  /*!< ADC_SL2CFG_CHSEL2                                                         */
17008   ADC_SL2CFG_CHSEL2_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
17009   ADC_SL2CFG_CHSEL2_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
17010   ADC_SL2CFG_CHSEL2_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
17011   ADC_SL2CFG_CHSEL2_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
17012   ADC_SL2CFG_CHSEL2_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
17013   ADC_SL2CFG_CHSEL2_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
17014   ADC_SL2CFG_CHSEL2_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
17015   ADC_SL2CFG_CHSEL2_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
17016   ADC_SL2CFG_CHSEL2_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
17017   ADC_SL2CFG_CHSEL2_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
17018   ADC_SL2CFG_CHSEL2_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
17019                                                      pad13(P).                                                                 */
17020   ADC_SL2CFG_CHSEL2_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
17021                                                      pad14(P).                                                                 */
17022   ADC_SL2CFG_CHSEL2_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
17023   ADC_SL2CFG_CHSEL2_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
17024   ADC_SL2CFG_CHSEL2_VSS                = 14,    /*!< VSS : Input VSS                                                           */
17025 } ADC_SL2CFG_CHSEL2_Enum;
17026 
17027 /* ================================================  ADC SL2CFG WCEN2 [1..1]  ================================================ */
17028 typedef enum {                                  /*!< ADC_SL2CFG_WCEN2                                                          */
17029   ADC_SL2CFG_WCEN2_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 2.                              */
17030 } ADC_SL2CFG_WCEN2_Enum;
17031 
17032 /* ================================================  ADC SL2CFG SLEN2 [0..0]  ================================================ */
17033 typedef enum {                                  /*!< ADC_SL2CFG_SLEN2                                                          */
17034   ADC_SL2CFG_SLEN2_SLEN                = 1,     /*!< SLEN : Enable slot 2 for ADC conversions.                                 */
17035 } ADC_SL2CFG_SLEN2_Enum;
17036 
17037 /* ========================================================  SL3CFG  ========================================================= */
17038 /* ==============================================  ADC SL3CFG ADSEL3 [24..26]  =============================================== */
17039 typedef enum {                                  /*!< ADC_SL3CFG_ADSEL3                                                         */
17040   ADC_SL3CFG_ADSEL3_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
17041                                                      module for this slot.                                                     */
17042   ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
17043                                                      module for this slot.                                                     */
17044   ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
17045                                                      module for this slot.                                                     */
17046   ADC_SL3CFG_ADSEL3_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
17047                                                      module for this slot.                                                     */
17048   ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
17049                                                      divide module for this slot.                                              */
17050   ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
17051                                                      divide module for this slot.                                              */
17052   ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
17053                                                      divide module for this slot.                                              */
17054   ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
17055                                                      divide module for this slot.                                              */
17056 } ADC_SL3CFG_ADSEL3_Enum;
17057 
17058 /* ==============================================  ADC SL3CFG PRMODE3 [16..17]  ============================================== */
17059 typedef enum {                                  /*!< ADC_SL3CFG_PRMODE3                                                        */
17060   ADC_SL3CFG_PRMODE3_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
17061   ADC_SL3CFG_PRMODE3_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
17062   ADC_SL3CFG_PRMODE3_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
17063   ADC_SL3CFG_PRMODE3_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
17064 } ADC_SL3CFG_PRMODE3_Enum;
17065 
17066 /* ===============================================  ADC SL3CFG CHSEL3 [8..11]  =============================================== */
17067 typedef enum {                                  /*!< ADC_SL3CFG_CHSEL3                                                         */
17068   ADC_SL3CFG_CHSEL3_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
17069   ADC_SL3CFG_CHSEL3_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
17070   ADC_SL3CFG_CHSEL3_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
17071   ADC_SL3CFG_CHSEL3_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
17072   ADC_SL3CFG_CHSEL3_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
17073   ADC_SL3CFG_CHSEL3_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
17074   ADC_SL3CFG_CHSEL3_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
17075   ADC_SL3CFG_CHSEL3_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
17076   ADC_SL3CFG_CHSEL3_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
17077   ADC_SL3CFG_CHSEL3_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
17078   ADC_SL3CFG_CHSEL3_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
17079                                                      pad13(P).                                                                 */
17080   ADC_SL3CFG_CHSEL3_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
17081                                                      pad14(P).                                                                 */
17082   ADC_SL3CFG_CHSEL3_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
17083   ADC_SL3CFG_CHSEL3_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
17084   ADC_SL3CFG_CHSEL3_VSS                = 14,    /*!< VSS : Input VSS                                                           */
17085 } ADC_SL3CFG_CHSEL3_Enum;
17086 
17087 /* ================================================  ADC SL3CFG WCEN3 [1..1]  ================================================ */
17088 typedef enum {                                  /*!< ADC_SL3CFG_WCEN3                                                          */
17089   ADC_SL3CFG_WCEN3_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 3.                              */
17090 } ADC_SL3CFG_WCEN3_Enum;
17091 
17092 /* ================================================  ADC SL3CFG SLEN3 [0..0]  ================================================ */
17093 typedef enum {                                  /*!< ADC_SL3CFG_SLEN3                                                          */
17094   ADC_SL3CFG_SLEN3_SLEN                = 1,     /*!< SLEN : Enable slot 3 for ADC conversions.                                 */
17095 } ADC_SL3CFG_SLEN3_Enum;
17096 
17097 /* ========================================================  SL4CFG  ========================================================= */
17098 /* ==============================================  ADC SL4CFG ADSEL4 [24..26]  =============================================== */
17099 typedef enum {                                  /*!< ADC_SL4CFG_ADSEL4                                                         */
17100   ADC_SL4CFG_ADSEL4_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
17101                                                      module for this slot.                                                     */
17102   ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
17103                                                      module for this slot.                                                     */
17104   ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
17105                                                      module for this slot.                                                     */
17106   ADC_SL4CFG_ADSEL4_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
17107                                                      module for this slot.                                                     */
17108   ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
17109                                                      divide module for this slot.                                              */
17110   ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
17111                                                      divide module for this slot.                                              */
17112   ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
17113                                                      divide module for this slot.                                              */
17114   ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
17115                                                      divide module for this slot.                                              */
17116 } ADC_SL4CFG_ADSEL4_Enum;
17117 
17118 /* ==============================================  ADC SL4CFG PRMODE4 [16..17]  ============================================== */
17119 typedef enum {                                  /*!< ADC_SL4CFG_PRMODE4                                                        */
17120   ADC_SL4CFG_PRMODE4_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
17121   ADC_SL4CFG_PRMODE4_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
17122   ADC_SL4CFG_PRMODE4_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
17123   ADC_SL4CFG_PRMODE4_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
17124 } ADC_SL4CFG_PRMODE4_Enum;
17125 
17126 /* ===============================================  ADC SL4CFG CHSEL4 [8..11]  =============================================== */
17127 typedef enum {                                  /*!< ADC_SL4CFG_CHSEL4                                                         */
17128   ADC_SL4CFG_CHSEL4_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
17129   ADC_SL4CFG_CHSEL4_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
17130   ADC_SL4CFG_CHSEL4_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
17131   ADC_SL4CFG_CHSEL4_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
17132   ADC_SL4CFG_CHSEL4_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
17133   ADC_SL4CFG_CHSEL4_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
17134   ADC_SL4CFG_CHSEL4_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
17135   ADC_SL4CFG_CHSEL4_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
17136   ADC_SL4CFG_CHSEL4_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
17137   ADC_SL4CFG_CHSEL4_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
17138   ADC_SL4CFG_CHSEL4_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
17139                                                      pad13(P).                                                                 */
17140   ADC_SL4CFG_CHSEL4_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
17141                                                      pad14(P).                                                                 */
17142   ADC_SL4CFG_CHSEL4_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
17143   ADC_SL4CFG_CHSEL4_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
17144   ADC_SL4CFG_CHSEL4_VSS                = 14,    /*!< VSS : Input VSS                                                           */
17145 } ADC_SL4CFG_CHSEL4_Enum;
17146 
17147 /* ================================================  ADC SL4CFG WCEN4 [1..1]  ================================================ */
17148 typedef enum {                                  /*!< ADC_SL4CFG_WCEN4                                                          */
17149   ADC_SL4CFG_WCEN4_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 4.                              */
17150 } ADC_SL4CFG_WCEN4_Enum;
17151 
17152 /* ================================================  ADC SL4CFG SLEN4 [0..0]  ================================================ */
17153 typedef enum {                                  /*!< ADC_SL4CFG_SLEN4                                                          */
17154   ADC_SL4CFG_SLEN4_SLEN                = 1,     /*!< SLEN : Enable slot 4 for ADC conversions.                                 */
17155 } ADC_SL4CFG_SLEN4_Enum;
17156 
17157 /* ========================================================  SL5CFG  ========================================================= */
17158 /* ==============================================  ADC SL5CFG ADSEL5 [24..26]  =============================================== */
17159 typedef enum {                                  /*!< ADC_SL5CFG_ADSEL5                                                         */
17160   ADC_SL5CFG_ADSEL5_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
17161                                                      module for this slot.                                                     */
17162   ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
17163                                                      module for this slot.                                                     */
17164   ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
17165                                                      module for this slot.                                                     */
17166   ADC_SL5CFG_ADSEL5_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
17167                                                      module for this slot.                                                     */
17168   ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
17169                                                      divide module for this slot.                                              */
17170   ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
17171                                                      divide module for this slot.                                              */
17172   ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
17173                                                      divide module for this slot.                                              */
17174   ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
17175                                                      divide module for this slot.                                              */
17176 } ADC_SL5CFG_ADSEL5_Enum;
17177 
17178 /* ==============================================  ADC SL5CFG PRMODE5 [16..17]  ============================================== */
17179 typedef enum {                                  /*!< ADC_SL5CFG_PRMODE5                                                        */
17180   ADC_SL5CFG_PRMODE5_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
17181   ADC_SL5CFG_PRMODE5_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
17182   ADC_SL5CFG_PRMODE5_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
17183   ADC_SL5CFG_PRMODE5_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
17184 } ADC_SL5CFG_PRMODE5_Enum;
17185 
17186 /* ===============================================  ADC SL5CFG CHSEL5 [8..11]  =============================================== */
17187 typedef enum {                                  /*!< ADC_SL5CFG_CHSEL5                                                         */
17188   ADC_SL5CFG_CHSEL5_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
17189   ADC_SL5CFG_CHSEL5_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
17190   ADC_SL5CFG_CHSEL5_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
17191   ADC_SL5CFG_CHSEL5_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
17192   ADC_SL5CFG_CHSEL5_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
17193   ADC_SL5CFG_CHSEL5_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
17194   ADC_SL5CFG_CHSEL5_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
17195   ADC_SL5CFG_CHSEL5_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
17196   ADC_SL5CFG_CHSEL5_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
17197   ADC_SL5CFG_CHSEL5_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
17198   ADC_SL5CFG_CHSEL5_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
17199                                                      pad13(P).                                                                 */
17200   ADC_SL5CFG_CHSEL5_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
17201                                                      pad14(P).                                                                 */
17202   ADC_SL5CFG_CHSEL5_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
17203   ADC_SL5CFG_CHSEL5_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
17204   ADC_SL5CFG_CHSEL5_VSS                = 14,    /*!< VSS : Input VSS                                                           */
17205 } ADC_SL5CFG_CHSEL5_Enum;
17206 
17207 /* ================================================  ADC SL5CFG WCEN5 [1..1]  ================================================ */
17208 typedef enum {                                  /*!< ADC_SL5CFG_WCEN5                                                          */
17209   ADC_SL5CFG_WCEN5_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 5.                              */
17210 } ADC_SL5CFG_WCEN5_Enum;
17211 
17212 /* ================================================  ADC SL5CFG SLEN5 [0..0]  ================================================ */
17213 typedef enum {                                  /*!< ADC_SL5CFG_SLEN5                                                          */
17214   ADC_SL5CFG_SLEN5_SLEN                = 1,     /*!< SLEN : Enable slot 5 for ADC conversions.                                 */
17215 } ADC_SL5CFG_SLEN5_Enum;
17216 
17217 /* ========================================================  SL6CFG  ========================================================= */
17218 /* ==============================================  ADC SL6CFG ADSEL6 [24..26]  =============================================== */
17219 typedef enum {                                  /*!< ADC_SL6CFG_ADSEL6                                                         */
17220   ADC_SL6CFG_ADSEL6_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
17221                                                      module for this slot.                                                     */
17222   ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
17223                                                      module for this slot.                                                     */
17224   ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
17225                                                      module for this slot.                                                     */
17226   ADC_SL6CFG_ADSEL6_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
17227                                                      module for this slot.                                                     */
17228   ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
17229                                                      divide module for this slot.                                              */
17230   ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
17231                                                      divide module for this slot.                                              */
17232   ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
17233                                                      divide module for this slot.                                              */
17234   ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
17235                                                      divide module for this slot.                                              */
17236 } ADC_SL6CFG_ADSEL6_Enum;
17237 
17238 /* ==============================================  ADC SL6CFG PRMODE6 [16..17]  ============================================== */
17239 typedef enum {                                  /*!< ADC_SL6CFG_PRMODE6                                                        */
17240   ADC_SL6CFG_PRMODE6_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
17241   ADC_SL6CFG_PRMODE6_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
17242   ADC_SL6CFG_PRMODE6_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
17243   ADC_SL6CFG_PRMODE6_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
17244 } ADC_SL6CFG_PRMODE6_Enum;
17245 
17246 /* ===============================================  ADC SL6CFG CHSEL6 [8..11]  =============================================== */
17247 typedef enum {                                  /*!< ADC_SL6CFG_CHSEL6                                                         */
17248   ADC_SL6CFG_CHSEL6_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
17249   ADC_SL6CFG_CHSEL6_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
17250   ADC_SL6CFG_CHSEL6_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
17251   ADC_SL6CFG_CHSEL6_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
17252   ADC_SL6CFG_CHSEL6_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
17253   ADC_SL6CFG_CHSEL6_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
17254   ADC_SL6CFG_CHSEL6_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
17255   ADC_SL6CFG_CHSEL6_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
17256   ADC_SL6CFG_CHSEL6_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
17257   ADC_SL6CFG_CHSEL6_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
17258   ADC_SL6CFG_CHSEL6_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
17259                                                      pad13(P).                                                                 */
17260   ADC_SL6CFG_CHSEL6_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
17261                                                      pad14(P).                                                                 */
17262   ADC_SL6CFG_CHSEL6_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
17263   ADC_SL6CFG_CHSEL6_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
17264   ADC_SL6CFG_CHSEL6_VSS                = 14,    /*!< VSS : Input VSS                                                           */
17265 } ADC_SL6CFG_CHSEL6_Enum;
17266 
17267 /* ================================================  ADC SL6CFG WCEN6 [1..1]  ================================================ */
17268 typedef enum {                                  /*!< ADC_SL6CFG_WCEN6                                                          */
17269   ADC_SL6CFG_WCEN6_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 6.                              */
17270 } ADC_SL6CFG_WCEN6_Enum;
17271 
17272 /* ================================================  ADC SL6CFG SLEN6 [0..0]  ================================================ */
17273 typedef enum {                                  /*!< ADC_SL6CFG_SLEN6                                                          */
17274   ADC_SL6CFG_SLEN6_SLEN                = 1,     /*!< SLEN : Enable slot 6 for ADC conversions.                                 */
17275 } ADC_SL6CFG_SLEN6_Enum;
17276 
17277 /* ========================================================  SL7CFG  ========================================================= */
17278 /* ==============================================  ADC SL7CFG ADSEL7 [24..26]  =============================================== */
17279 typedef enum {                                  /*!< ADC_SL7CFG_ADSEL7                                                         */
17280   ADC_SL7CFG_ADSEL7_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
17281                                                      module for this slot.                                                     */
17282   ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
17283                                                      module for this slot.                                                     */
17284   ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
17285                                                      module for this slot.                                                     */
17286   ADC_SL7CFG_ADSEL7_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
17287                                                      module for this slot.                                                     */
17288   ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
17289                                                      divide module for this slot.                                              */
17290   ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
17291                                                      divide module for this slot.                                              */
17292   ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
17293                                                      divide module for this slot.                                              */
17294   ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
17295                                                      divide module for this slot.                                              */
17296 } ADC_SL7CFG_ADSEL7_Enum;
17297 
17298 /* ==============================================  ADC SL7CFG PRMODE7 [16..17]  ============================================== */
17299 typedef enum {                                  /*!< ADC_SL7CFG_PRMODE7                                                        */
17300   ADC_SL7CFG_PRMODE7_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
17301   ADC_SL7CFG_PRMODE7_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
17302   ADC_SL7CFG_PRMODE7_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
17303   ADC_SL7CFG_PRMODE7_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
17304 } ADC_SL7CFG_PRMODE7_Enum;
17305 
17306 /* ===============================================  ADC SL7CFG CHSEL7 [8..11]  =============================================== */
17307 typedef enum {                                  /*!< ADC_SL7CFG_CHSEL7                                                         */
17308   ADC_SL7CFG_CHSEL7_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
17309   ADC_SL7CFG_CHSEL7_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
17310   ADC_SL7CFG_CHSEL7_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
17311   ADC_SL7CFG_CHSEL7_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
17312   ADC_SL7CFG_CHSEL7_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
17313   ADC_SL7CFG_CHSEL7_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
17314   ADC_SL7CFG_CHSEL7_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
17315   ADC_SL7CFG_CHSEL7_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
17316   ADC_SL7CFG_CHSEL7_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
17317   ADC_SL7CFG_CHSEL7_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
17318   ADC_SL7CFG_CHSEL7_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
17319                                                      pad13(P).                                                                 */
17320   ADC_SL7CFG_CHSEL7_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
17321                                                      pad14(P).                                                                 */
17322   ADC_SL7CFG_CHSEL7_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
17323   ADC_SL7CFG_CHSEL7_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
17324   ADC_SL7CFG_CHSEL7_VSS                = 14,    /*!< VSS : Input VSS                                                           */
17325 } ADC_SL7CFG_CHSEL7_Enum;
17326 
17327 /* ================================================  ADC SL7CFG WCEN7 [1..1]  ================================================ */
17328 typedef enum {                                  /*!< ADC_SL7CFG_WCEN7                                                          */
17329   ADC_SL7CFG_WCEN7_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 7.                              */
17330 } ADC_SL7CFG_WCEN7_Enum;
17331 
17332 /* ================================================  ADC SL7CFG SLEN7 [0..0]  ================================================ */
17333 typedef enum {                                  /*!< ADC_SL7CFG_SLEN7                                                          */
17334   ADC_SL7CFG_SLEN7_SLEN                = 1,     /*!< SLEN : Enable slot 7 for ADC conversions.                                 */
17335 } ADC_SL7CFG_SLEN7_Enum;
17336 
17337 /* =========================================================  WULIM  ========================================================= */
17338 /* =========================================================  WLLIM  ========================================================= */
17339 /* ========================================================  SCWLIM  ========================================================= */
17340 /* =========================================================  FIFO  ========================================================== */
17341 /* ========================================================  FIFOPR  ========================================================= */
17342 /* =========================================================  INTEN  ========================================================= */
17343 /* =================================================  ADC INTEN DERR [7..7]  ================================================= */
17344 typedef enum {                                  /*!< ADC_INTEN_DERR                                                            */
17345   ADC_INTEN_DERR_DMAERROR              = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
17346 } ADC_INTEN_DERR_Enum;
17347 
17348 /* =================================================  ADC INTEN DCMP [6..6]  ================================================= */
17349 typedef enum {                                  /*!< ADC_INTEN_DCMP                                                            */
17350   ADC_INTEN_DCMP_DMACOMPLETE           = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
17351 } ADC_INTEN_DCMP_Enum;
17352 
17353 /* ================================================  ADC INTEN WCINC [5..5]  ================================================= */
17354 typedef enum {                                  /*!< ADC_INTEN_WCINC                                                           */
17355   ADC_INTEN_WCINC_WCINCINT             = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
17356 } ADC_INTEN_WCINC_Enum;
17357 
17358 /* ================================================  ADC INTEN WCEXC [4..4]  ================================================= */
17359 typedef enum {                                  /*!< ADC_INTEN_WCEXC                                                           */
17360   ADC_INTEN_WCEXC_WCEXCINT             = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
17361 } ADC_INTEN_WCEXC_Enum;
17362 
17363 /* ===============================================  ADC INTEN FIFOOVR2 [3..3]  =============================================== */
17364 typedef enum {                                  /*!< ADC_INTEN_FIFOOVR2                                                        */
17365   ADC_INTEN_FIFOOVR2_FIFOFULLINT       = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
17366 } ADC_INTEN_FIFOOVR2_Enum;
17367 
17368 /* ===============================================  ADC INTEN FIFOOVR1 [2..2]  =============================================== */
17369 typedef enum {                                  /*!< ADC_INTEN_FIFOOVR1                                                        */
17370   ADC_INTEN_FIFOOVR1_FIFO75INT         = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
17371 } ADC_INTEN_FIFOOVR1_Enum;
17372 
17373 /* ================================================  ADC INTEN SCNCMP [1..1]  ================================================ */
17374 typedef enum {                                  /*!< ADC_INTEN_SCNCMP                                                          */
17375   ADC_INTEN_SCNCMP_SCNCMPINT           = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
17376 } ADC_INTEN_SCNCMP_Enum;
17377 
17378 /* ================================================  ADC INTEN CNVCMP [0..0]  ================================================ */
17379 typedef enum {                                  /*!< ADC_INTEN_CNVCMP                                                          */
17380   ADC_INTEN_CNVCMP_CNVCMPINT           = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
17381 } ADC_INTEN_CNVCMP_Enum;
17382 
17383 /* ========================================================  INTSTAT  ======================================================== */
17384 /* ================================================  ADC INTSTAT DERR [7..7]  ================================================ */
17385 typedef enum {                                  /*!< ADC_INTSTAT_DERR                                                          */
17386   ADC_INTSTAT_DERR_DMAERROR            = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
17387 } ADC_INTSTAT_DERR_Enum;
17388 
17389 /* ================================================  ADC INTSTAT DCMP [6..6]  ================================================ */
17390 typedef enum {                                  /*!< ADC_INTSTAT_DCMP                                                          */
17391   ADC_INTSTAT_DCMP_DMACOMPLETE         = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
17392 } ADC_INTSTAT_DCMP_Enum;
17393 
17394 /* ===============================================  ADC INTSTAT WCINC [5..5]  ================================================ */
17395 typedef enum {                                  /*!< ADC_INTSTAT_WCINC                                                         */
17396   ADC_INTSTAT_WCINC_WCINCINT           = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
17397 } ADC_INTSTAT_WCINC_Enum;
17398 
17399 /* ===============================================  ADC INTSTAT WCEXC [4..4]  ================================================ */
17400 typedef enum {                                  /*!< ADC_INTSTAT_WCEXC                                                         */
17401   ADC_INTSTAT_WCEXC_WCEXCINT           = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
17402 } ADC_INTSTAT_WCEXC_Enum;
17403 
17404 /* ==============================================  ADC INTSTAT FIFOOVR2 [3..3]  ============================================== */
17405 typedef enum {                                  /*!< ADC_INTSTAT_FIFOOVR2                                                      */
17406   ADC_INTSTAT_FIFOOVR2_FIFOFULLINT     = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
17407 } ADC_INTSTAT_FIFOOVR2_Enum;
17408 
17409 /* ==============================================  ADC INTSTAT FIFOOVR1 [2..2]  ============================================== */
17410 typedef enum {                                  /*!< ADC_INTSTAT_FIFOOVR1                                                      */
17411   ADC_INTSTAT_FIFOOVR1_FIFO75INT       = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
17412 } ADC_INTSTAT_FIFOOVR1_Enum;
17413 
17414 /* ===============================================  ADC INTSTAT SCNCMP [1..1]  =============================================== */
17415 typedef enum {                                  /*!< ADC_INTSTAT_SCNCMP                                                        */
17416   ADC_INTSTAT_SCNCMP_SCNCMPINT         = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
17417 } ADC_INTSTAT_SCNCMP_Enum;
17418 
17419 /* ===============================================  ADC INTSTAT CNVCMP [0..0]  =============================================== */
17420 typedef enum {                                  /*!< ADC_INTSTAT_CNVCMP                                                        */
17421   ADC_INTSTAT_CNVCMP_CNVCMPINT         = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
17422 } ADC_INTSTAT_CNVCMP_Enum;
17423 
17424 /* ========================================================  INTCLR  ========================================================= */
17425 /* ================================================  ADC INTCLR DERR [7..7]  ================================================= */
17426 typedef enum {                                  /*!< ADC_INTCLR_DERR                                                           */
17427   ADC_INTCLR_DERR_DMAERROR             = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
17428 } ADC_INTCLR_DERR_Enum;
17429 
17430 /* ================================================  ADC INTCLR DCMP [6..6]  ================================================= */
17431 typedef enum {                                  /*!< ADC_INTCLR_DCMP                                                           */
17432   ADC_INTCLR_DCMP_DMACOMPLETE          = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
17433 } ADC_INTCLR_DCMP_Enum;
17434 
17435 /* ================================================  ADC INTCLR WCINC [5..5]  ================================================ */
17436 typedef enum {                                  /*!< ADC_INTCLR_WCINC                                                          */
17437   ADC_INTCLR_WCINC_WCINCINT            = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
17438 } ADC_INTCLR_WCINC_Enum;
17439 
17440 /* ================================================  ADC INTCLR WCEXC [4..4]  ================================================ */
17441 typedef enum {                                  /*!< ADC_INTCLR_WCEXC                                                          */
17442   ADC_INTCLR_WCEXC_WCEXCINT            = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
17443 } ADC_INTCLR_WCEXC_Enum;
17444 
17445 /* ==============================================  ADC INTCLR FIFOOVR2 [3..3]  =============================================== */
17446 typedef enum {                                  /*!< ADC_INTCLR_FIFOOVR2                                                       */
17447   ADC_INTCLR_FIFOOVR2_FIFOFULLINT      = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
17448 } ADC_INTCLR_FIFOOVR2_Enum;
17449 
17450 /* ==============================================  ADC INTCLR FIFOOVR1 [2..2]  =============================================== */
17451 typedef enum {                                  /*!< ADC_INTCLR_FIFOOVR1                                                       */
17452   ADC_INTCLR_FIFOOVR1_FIFO75INT        = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
17453 } ADC_INTCLR_FIFOOVR1_Enum;
17454 
17455 /* ===============================================  ADC INTCLR SCNCMP [1..1]  ================================================ */
17456 typedef enum {                                  /*!< ADC_INTCLR_SCNCMP                                                         */
17457   ADC_INTCLR_SCNCMP_SCNCMPINT          = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
17458 } ADC_INTCLR_SCNCMP_Enum;
17459 
17460 /* ===============================================  ADC INTCLR CNVCMP [0..0]  ================================================ */
17461 typedef enum {                                  /*!< ADC_INTCLR_CNVCMP                                                         */
17462   ADC_INTCLR_CNVCMP_CNVCMPINT          = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
17463 } ADC_INTCLR_CNVCMP_Enum;
17464 
17465 /* ========================================================  INTSET  ========================================================= */
17466 /* ================================================  ADC INTSET DERR [7..7]  ================================================= */
17467 typedef enum {                                  /*!< ADC_INTSET_DERR                                                           */
17468   ADC_INTSET_DERR_DMAERROR             = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
17469 } ADC_INTSET_DERR_Enum;
17470 
17471 /* ================================================  ADC INTSET DCMP [6..6]  ================================================= */
17472 typedef enum {                                  /*!< ADC_INTSET_DCMP                                                           */
17473   ADC_INTSET_DCMP_DMACOMPLETE          = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
17474 } ADC_INTSET_DCMP_Enum;
17475 
17476 /* ================================================  ADC INTSET WCINC [5..5]  ================================================ */
17477 typedef enum {                                  /*!< ADC_INTSET_WCINC                                                          */
17478   ADC_INTSET_WCINC_WCINCINT            = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
17479 } ADC_INTSET_WCINC_Enum;
17480 
17481 /* ================================================  ADC INTSET WCEXC [4..4]  ================================================ */
17482 typedef enum {                                  /*!< ADC_INTSET_WCEXC                                                          */
17483   ADC_INTSET_WCEXC_WCEXCINT            = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
17484 } ADC_INTSET_WCEXC_Enum;
17485 
17486 /* ==============================================  ADC INTSET FIFOOVR2 [3..3]  =============================================== */
17487 typedef enum {                                  /*!< ADC_INTSET_FIFOOVR2                                                       */
17488   ADC_INTSET_FIFOOVR2_FIFOFULLINT      = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
17489 } ADC_INTSET_FIFOOVR2_Enum;
17490 
17491 /* ==============================================  ADC INTSET FIFOOVR1 [2..2]  =============================================== */
17492 typedef enum {                                  /*!< ADC_INTSET_FIFOOVR1                                                       */
17493   ADC_INTSET_FIFOOVR1_FIFO75INT        = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
17494 } ADC_INTSET_FIFOOVR1_Enum;
17495 
17496 /* ===============================================  ADC INTSET SCNCMP [1..1]  ================================================ */
17497 typedef enum {                                  /*!< ADC_INTSET_SCNCMP                                                         */
17498   ADC_INTSET_SCNCMP_SCNCMPINT          = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
17499 } ADC_INTSET_SCNCMP_Enum;
17500 
17501 /* ===============================================  ADC INTSET CNVCMP [0..0]  ================================================ */
17502 typedef enum {                                  /*!< ADC_INTSET_CNVCMP                                                         */
17503   ADC_INTSET_CNVCMP_CNVCMPINT          = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
17504 } ADC_INTSET_CNVCMP_Enum;
17505 
17506 /* =======================================================  DMATRIGEN  ======================================================= */
17507 /* ======================================================  DMATRIGSTAT  ====================================================== */
17508 /* ========================================================  DMACFG  ========================================================= */
17509 /* ==============================================  ADC DMACFG DMAMSK [17..17]  =============================================== */
17510 typedef enum {                                  /*!< ADC_DMACFG_DMAMSK                                                         */
17511   ADC_DMACFG_DMAMSK_DIS                = 0,     /*!< DIS : FIFO Contents are copied directly to memory without modification.   */
17512   ADC_DMACFG_DMAMSK_EN                 = 1,     /*!< EN : Only the FIFODATA contents are copied to memory on DMA
17513                                                      transfers. The SLOTNUM and FIFOCNT contents are cleared
17514                                                      to zero.                                                                  */
17515 } ADC_DMACFG_DMAMSK_Enum;
17516 
17517 /* ============================================  ADC DMACFG DMAHONSTAT [16..16]  ============================================= */
17518 typedef enum {                                  /*!< ADC_DMACFG_DMAHONSTAT                                                     */
17519   ADC_DMACFG_DMAHONSTAT_DIS            = 0,     /*!< DIS : ADC conversions will continue regardless of DMA status
17520                                                      register                                                                  */
17521   ADC_DMACFG_DMAHONSTAT_EN             = 1,     /*!< EN : ADC conversions will not progress if DMAERR or DMACPL bits
17522                                                      in DMA status register are set.                                           */
17523 } ADC_DMACFG_DMAHONSTAT_Enum;
17524 
17525 /* ==============================================  ADC DMACFG DMADYNPRI [9..9]  ============================================== */
17526 typedef enum {                                  /*!< ADC_DMACFG_DMADYNPRI                                                      */
17527   ADC_DMACFG_DMADYNPRI_DIS             = 0,     /*!< DIS : Disable dynamic priority (use DMAPRI setting only)                  */
17528   ADC_DMACFG_DMADYNPRI_EN              = 1,     /*!< EN : Enable dynamic priority                                              */
17529 } ADC_DMACFG_DMADYNPRI_Enum;
17530 
17531 /* ===============================================  ADC DMACFG DMAPRI [8..8]  ================================================ */
17532 typedef enum {                                  /*!< ADC_DMACFG_DMAPRI                                                         */
17533   ADC_DMACFG_DMAPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
17534   ADC_DMACFG_DMAPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
17535 } ADC_DMACFG_DMAPRI_Enum;
17536 
17537 /* ===============================================  ADC DMACFG DMADIR [2..2]  ================================================ */
17538 typedef enum {                                  /*!< ADC_DMACFG_DMADIR                                                         */
17539   ADC_DMACFG_DMADIR_P2M                = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
17540   ADC_DMACFG_DMADIR_M2P                = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
17541 } ADC_DMACFG_DMADIR_Enum;
17542 
17543 /* ================================================  ADC DMACFG DMAEN [0..0]  ================================================ */
17544 typedef enum {                                  /*!< ADC_DMACFG_DMAEN                                                          */
17545   ADC_DMACFG_DMAEN_DIS                 = 0,     /*!< DIS : Disable DMA Function                                                */
17546   ADC_DMACFG_DMAEN_EN                  = 1,     /*!< EN : Enable DMA Function                                                  */
17547 } ADC_DMACFG_DMAEN_Enum;
17548 
17549 /* ======================================================  DMATOTCOUNT  ====================================================== */
17550 /* ======================================================  DMATARGADDR  ====================================================== */
17551 /* ========================================================  DMASTAT  ======================================================== */
17552 
17553 
17554 /* =========================================================================================================================== */
17555 /* ================                                          APBDMA                                           ================ */
17556 /* =========================================================================================================================== */
17557 
17558 /* ========================================================  BBVALUE  ======================================================== */
17559 /* ======================================================  BBSETCLEAR  ======================================================= */
17560 /* ========================================================  BBINPUT  ======================================================== */
17561 /* =======================================================  DEBUGDATA  ======================================================= */
17562 /* =========================================================  DEBUG  ========================================================= */
17563 /* ==============================================  APBDMA DEBUG DEBUGEN [0..3]  ============================================== */
17564 typedef enum {                                  /*!< APBDMA_DEBUG_DEBUGEN                                                      */
17565   APBDMA_DEBUG_DEBUGEN_OFF             = 0,     /*!< OFF : Debug Disabled                                                      */
17566   APBDMA_DEBUG_DEBUGEN_ARB             = 1,     /*!< ARB : Debug ARB values                                                    */
17567 } APBDMA_DEBUG_DEBUGEN_Enum;
17568 
17569 
17570 
17571 /* =========================================================================================================================== */
17572 /* ================                                           BLEIF                                           ================ */
17573 /* =========================================================================================================================== */
17574 
17575 /* =========================================================  FIFO  ========================================================== */
17576 /* ========================================================  FIFOPTR  ======================================================== */
17577 /* ========================================================  FIFOTHR  ======================================================== */
17578 /* ========================================================  FIFOPOP  ======================================================== */
17579 /* =======================================================  FIFOPUSH  ======================================================== */
17580 /* =======================================================  FIFOCTRL  ======================================================== */
17581 /* ========================================================  FIFOLOC  ======================================================== */
17582 /* ========================================================  CLKCFG  ========================================================= */
17583 /* ===============================================  BLEIF CLKCFG FSEL [8..10]  =============================================== */
17584 typedef enum {                                  /*!< BLEIF_CLKCFG_FSEL                                                         */
17585   BLEIF_CLKCFG_FSEL_MIN_PWR            = 0,     /*!< MIN_PWR : Selects the minimum power clock. This setting should
17586                                                      be used whenever the IOM is not active.                                   */
17587   BLEIF_CLKCFG_FSEL_HFRC               = 1,     /*!< HFRC : Selects the HFRC as the input clock.                               */
17588   BLEIF_CLKCFG_FSEL_HFRC_DIV2          = 2,     /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock.                      */
17589   BLEIF_CLKCFG_FSEL_HFRC_DIV4          = 3,     /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock.                      */
17590   BLEIF_CLKCFG_FSEL_HFRC_DIV8          = 4,     /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock.                      */
17591   BLEIF_CLKCFG_FSEL_HFRC_DIV16         = 5,     /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock.                    */
17592   BLEIF_CLKCFG_FSEL_HFRC_DIV32         = 6,     /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock.                    */
17593   BLEIF_CLKCFG_FSEL_HFRC_DIV64         = 7,     /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock.                    */
17594 } BLEIF_CLKCFG_FSEL_Enum;
17595 
17596 /* ==========================================================  CMD  ========================================================== */
17597 /* =================================================  BLEIF CMD CMD [0..4]  ================================================== */
17598 typedef enum {                                  /*!< BLEIF_CMD_CMD                                                             */
17599   BLEIF_CMD_CMD_WRITE                  = 1,     /*!< WRITE : Write command using count of offset bytes specified
17600                                                      in the OFFSETCNT field                                                    */
17601   BLEIF_CMD_CMD_READ                   = 2,     /*!< READ : Read command using count of offset bytes specified in
17602                                                      the OFFSETCNT field                                                       */
17603 } BLEIF_CMD_CMD_Enum;
17604 
17605 /* ========================================================  CMDRPT  ========================================================= */
17606 /* =======================================================  OFFSETHI  ======================================================== */
17607 /* ========================================================  CMDSTAT  ======================================================== */
17608 /* =============================================  BLEIF CMDSTAT CMDSTAT [5..7]  ============================================== */
17609 typedef enum {                                  /*!< BLEIF_CMDSTAT_CMDSTAT                                                     */
17610   BLEIF_CMDSTAT_CMDSTAT_ERR            = 1,     /*!< ERR : Error encountered with command                                      */
17611   BLEIF_CMDSTAT_CMDSTAT_ACTIVE         = 2,     /*!< ACTIVE : Actively processing command                                      */
17612   BLEIF_CMDSTAT_CMDSTAT_IDLE           = 4,     /*!< IDLE : Idle state, no active command, no error                            */
17613   BLEIF_CMDSTAT_CMDSTAT_WAIT           = 6,     /*!< WAIT : Command in progress, but waiting on data from host                 */
17614 } BLEIF_CMDSTAT_CMDSTAT_Enum;
17615 
17616 /* =========================================================  INTEN  ========================================================= */
17617 /* ========================================================  INTSTAT  ======================================================== */
17618 /* ========================================================  INTCLR  ========================================================= */
17619 /* ========================================================  INTSET  ========================================================= */
17620 /* =======================================================  DMATRIGEN  ======================================================= */
17621 /* ======================================================  DMATRIGSTAT  ====================================================== */
17622 /* ========================================================  DMACFG  ========================================================= */
17623 /* ==============================================  BLEIF DMACFG DMAPRI [8..8]  =============================================== */
17624 typedef enum {                                  /*!< BLEIF_DMACFG_DMAPRI                                                       */
17625   BLEIF_DMACFG_DMAPRI_LOW              = 0,     /*!< LOW : Low Priority (service as best effort)                               */
17626   BLEIF_DMACFG_DMAPRI_HIGH             = 1,     /*!< HIGH : High Priority (service immediately)                                */
17627 } BLEIF_DMACFG_DMAPRI_Enum;
17628 
17629 /* ==============================================  BLEIF DMACFG DMADIR [1..1]  =============================================== */
17630 typedef enum {                                  /*!< BLEIF_DMACFG_DMADIR                                                       */
17631   BLEIF_DMACFG_DMADIR_P2M              = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when
17632                                                      doing IOM read operations, i.e., reading data from external
17633                                                      devices.                                                                  */
17634   BLEIF_DMACFG_DMADIR_M2P              = 1,     /*!< M2P : Memory to Peripheral transaction. To be set when doing
17635                                                      IOM write operations, i.e., writing data to external devices.             */
17636 } BLEIF_DMACFG_DMADIR_Enum;
17637 
17638 /* ===============================================  BLEIF DMACFG DMAEN [0..0]  =============================================== */
17639 typedef enum {                                  /*!< BLEIF_DMACFG_DMAEN                                                        */
17640   BLEIF_DMACFG_DMAEN_DIS               = 0,     /*!< DIS : Disable DMA Function                                                */
17641   BLEIF_DMACFG_DMAEN_EN                = 1,     /*!< EN : Enable DMA Function                                                  */
17642 } BLEIF_DMACFG_DMAEN_Enum;
17643 
17644 /* ======================================================  DMATOTCOUNT  ====================================================== */
17645 /* ======================================================  DMATARGADDR  ====================================================== */
17646 /* ========================================================  DMASTAT  ======================================================== */
17647 /* =========================================================  CQCFG  ========================================================= */
17648 /* ===============================================  BLEIF CQCFG CQPRI [1..1]  ================================================ */
17649 typedef enum {                                  /*!< BLEIF_CQCFG_CQPRI                                                         */
17650   BLEIF_CQCFG_CQPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
17651   BLEIF_CQCFG_CQPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
17652 } BLEIF_CQCFG_CQPRI_Enum;
17653 
17654 /* ================================================  BLEIF CQCFG CQEN [0..0]  ================================================ */
17655 typedef enum {                                  /*!< BLEIF_CQCFG_CQEN                                                          */
17656   BLEIF_CQCFG_CQEN_DIS                 = 0,     /*!< DIS : Disable CQ Function                                                 */
17657   BLEIF_CQCFG_CQEN_EN                  = 1,     /*!< EN : Enable CQ Function                                                   */
17658 } BLEIF_CQCFG_CQEN_Enum;
17659 
17660 /* ========================================================  CQADDR  ========================================================= */
17661 /* ========================================================  CQSTAT  ========================================================= */
17662 /* ========================================================  CQFLAGS  ======================================================== */
17663 /* ======================================================  CQSETCLEAR  ======================================================= */
17664 /* =======================================================  CQPAUSEEN  ======================================================= */
17665 /* =============================================  BLEIF CQPAUSEEN CQPEN [0..15]  ============================================= */
17666 typedef enum {                                  /*!< BLEIF_CQPAUSEEN_CQPEN                                                     */
17667   BLEIF_CQPAUSEEN_CQPEN_CNTEQ          = 32768, /*!< CNTEQ : Pauses command queue processing when HWCNT matches SWCNT          */
17668   BLEIF_CQPAUSEEN_CQPEN_BLEXOREN       = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with
17669                                                      SWFLAG4 is '1'                                                            */
17670   BLEIF_CQPAUSEEN_CQPEN_IOMXOREN       = 8192,  /*!< IOMXOREN : Pause command queue when input IOM bit XORed with
17671                                                      SWFLAG3 is '1'                                                            */
17672   BLEIF_CQPAUSEEN_CQPEN_GPIOXOREN      = 4096,  /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed
17673                                                      with SWFLAG2 is '1'                                                       */
17674   BLEIF_CQPAUSEEN_CQPEN_MSPI1XNOREN    = 2048,  /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed
17675                                                      with SWFLAG1 is '1'                                                       */
17676   BLEIF_CQPAUSEEN_CQPEN_MSPI0XNOREN    = 1024,  /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed
17677                                                      with SWFLAG0 is '1'                                                       */
17678   BLEIF_CQPAUSEEN_CQPEN_MSPI1XOREN     = 512,   /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed
17679                                                      with SWFLAG1 is '1'                                                       */
17680   BLEIF_CQPAUSEEN_CQPEN_MSPI0XOREN     = 256,   /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed
17681                                                      with SWFLAG0 is '1'                                                       */
17682   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN7      = 128,   /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7
17683                                                      is '1'.                                                                   */
17684   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN6      = 64,    /*!< SWFLAGEN6 : Pause the command queue when software flag bit 7
17685                                                      is '1'                                                                    */
17686   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN5      = 32,    /*!< SWFLAGEN5 : Pause the command queue when software flag bit 7
17687                                                      is '1'                                                                    */
17688   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN4      = 16,    /*!< SWFLAGEN4 : Pause the command queue when software flag bit 7
17689                                                      is '1'                                                                    */
17690   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN3      = 8,     /*!< SWFLAGEN3 : Pause the command queue when software flag bit 7
17691                                                      is '1'                                                                    */
17692   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN2      = 4,     /*!< SWFLAGEN2 : Pause the command queue when software flag bit 7
17693                                                      is '1'                                                                    */
17694   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN1      = 2,     /*!< SWFLAGEN1 : Pause the command queue when software flag bit 7
17695                                                      is '1'                                                                    */
17696   BLEIF_CQPAUSEEN_CQPEN_SWFLGEN0       = 1,     /*!< SWFLGEN0 : Pause the command queue when software flag bit 7
17697                                                      is '1'                                                                    */
17698 } BLEIF_CQPAUSEEN_CQPEN_Enum;
17699 
17700 /* =======================================================  CQCURIDX  ======================================================== */
17701 /* =======================================================  CQENDIDX  ======================================================== */
17702 /* ========================================================  STATUS  ========================================================= */
17703 /* ==============================================  BLEIF STATUS IDLEST [2..2]  =============================================== */
17704 typedef enum {                                  /*!< BLEIF_STATUS_IDLEST                                                       */
17705   BLEIF_STATUS_IDLEST_IDLE             = 1,     /*!< IDLE : The I/O state machine is in the idle state.                        */
17706 } BLEIF_STATUS_IDLEST_Enum;
17707 
17708 /* ==============================================  BLEIF STATUS CMDACT [1..1]  =============================================== */
17709 typedef enum {                                  /*!< BLEIF_STATUS_CMDACT                                                       */
17710   BLEIF_STATUS_CMDACT_ACTIVE           = 1,     /*!< ACTIVE : An I/O command is active. Indicates the active module
17711                                                      has an active command and is processing this. Deasserted
17712                                                      when the command is completed.                                            */
17713 } BLEIF_STATUS_CMDACT_Enum;
17714 
17715 /* ================================================  BLEIF STATUS ERR [0..0]  ================================================ */
17716 typedef enum {                                  /*!< BLEIF_STATUS_ERR                                                          */
17717   BLEIF_STATUS_ERR_ERROR               = 1,     /*!< ERROR : Bit has been deprecated and will always return 0.                 */
17718 } BLEIF_STATUS_ERR_Enum;
17719 
17720 /* ========================================================  MSPICFG  ======================================================== */
17721 /* =============================================  BLEIF MSPICFG SPILSB [23..23]  ============================================= */
17722 typedef enum {                                  /*!< BLEIF_MSPICFG_SPILSB                                                      */
17723   BLEIF_MSPICFG_SPILSB_MSB             = 0,     /*!< MSB : Send and receive MSB bit first                                      */
17724   BLEIF_MSPICFG_SPILSB_LSB             = 1,     /*!< LSB : Send and receive LSB bit first                                      */
17725 } BLEIF_MSPICFG_SPILSB_Enum;
17726 
17727 /* ============================================  BLEIF MSPICFG RDFCPOL [22..22]  ============================================= */
17728 typedef enum {                                  /*!< BLEIF_MSPICFG_RDFCPOL                                                     */
17729   BLEIF_MSPICFG_RDFCPOL_NORMAL         = 0,     /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow
17730                                                      control and new read SPI transactions will not be started
17731                                                      until the signal goes low.(default)                                       */
17732   BLEIF_MSPICFG_RDFCPOL_INVERTED       = 1,     /*!< INVERTED : SPI_STATUS signal from BLE Core low(0) creates flow
17733                                                      control and new read SPI transactions will not be started
17734                                                      until the signal goes high.                                               */
17735 } BLEIF_MSPICFG_RDFCPOL_Enum;
17736 
17737 /* ============================================  BLEIF MSPICFG WTFCPOL [21..21]  ============================================= */
17738 typedef enum {                                  /*!< BLEIF_MSPICFG_WTFCPOL                                                     */
17739   BLEIF_MSPICFG_WTFCPOL_NORMAL         = 0,     /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow
17740                                                      control and new write SPI transactions will not be started
17741                                                      until the signal goes low.(default)                                       */
17742   BLEIF_MSPICFG_WTFCPOL_INVERTED       = 1,     /*!< INVERTED : SPI_STATUS signal from BLE Core high(1) creates low(0)
17743                                                      control and new write SPI transactions will not be started
17744                                                      until the signal goes high.                                               */
17745 } BLEIF_MSPICFG_WTFCPOL_Enum;
17746 
17747 /* ==============================================  BLEIF MSPICFG RDFC [17..17]  ============================================== */
17748 typedef enum {                                  /*!< BLEIF_MSPICFG_RDFC                                                        */
17749   BLEIF_MSPICFG_RDFC_DIS               = 0,     /*!< DIS : Read mode flow control disabled.                                    */
17750   BLEIF_MSPICFG_RDFC_EN                = 1,     /*!< EN : Read mode flow control enabled.                                      */
17751 } BLEIF_MSPICFG_RDFC_Enum;
17752 
17753 /* ==============================================  BLEIF MSPICFG WTFC [16..16]  ============================================== */
17754 typedef enum {                                  /*!< BLEIF_MSPICFG_WTFC                                                        */
17755   BLEIF_MSPICFG_WTFC_DIS               = 0,     /*!< DIS : Write mode flow control disabled.                                   */
17756   BLEIF_MSPICFG_WTFC_EN                = 1,     /*!< EN : Write mode flow control enabled.                                     */
17757 } BLEIF_MSPICFG_WTFC_Enum;
17758 
17759 /* ===============================================  BLEIF MSPICFG SPHA [1..1]  =============================================== */
17760 typedef enum {                                  /*!< BLEIF_MSPICFG_SPHA                                                        */
17761   BLEIF_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0,   /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge,
17762                                                      rising or falling dependent on the value of SPOL                          */
17763   BLEIF_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1,  /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock
17764                                                      edge, rising of falling dependent on the value of SPOL                    */
17765 } BLEIF_MSPICFG_SPHA_Enum;
17766 
17767 /* ===============================================  BLEIF MSPICFG SPOL [0..0]  =============================================== */
17768 typedef enum {                                  /*!< BLEIF_MSPICFG_SPOL                                                        */
17769   BLEIF_MSPICFG_SPOL_CLK_BASE_0        = 0,     /*!< CLK_BASE_0 : The initial value of the clock is 0.                         */
17770   BLEIF_MSPICFG_SPOL_CLK_BASE_1        = 1,     /*!< CLK_BASE_1 : The initial value of the clock is 1.                         */
17771 } BLEIF_MSPICFG_SPOL_Enum;
17772 
17773 /* ========================================================  BLECFG  ========================================================= */
17774 /* ============================================  BLEIF BLECFG SPIISOCTL [14..15]  ============================================ */
17775 typedef enum {                                  /*!< BLEIF_BLECFG_SPIISOCTL                                                    */
17776   BLEIF_BLECFG_SPIISOCTL_ON            = 3,     /*!< ON : SPI signals from BLE Core to/from MCU Core are isolated.             */
17777   BLEIF_BLECFG_SPIISOCTL_OFF           = 2,     /*!< OFF : SPI signals from BLE Core to/from MCU Core are not isolated.        */
17778   BLEIF_BLECFG_SPIISOCTL_AUTO          = 0,     /*!< AUTO : SPI signals from BLE Core to/from MCU Core are automatically
17779                                                      isolated by the logic                                                     */
17780 } BLEIF_BLECFG_SPIISOCTL_Enum;
17781 
17782 /* ============================================  BLEIF BLECFG PWRISOCTL [12..13]  ============================================ */
17783 typedef enum {                                  /*!< BLEIF_BLECFG_PWRISOCTL                                                    */
17784   BLEIF_BLECFG_PWRISOCTL_ON            = 3,     /*!< ON : BLEH power signal isolation to on (isolated).                        */
17785   BLEIF_BLECFG_PWRISOCTL_OFF           = 2,     /*!< OFF : BLEH power signal isolation to off (not isolated).                  */
17786   BLEIF_BLECFG_PWRISOCTL_AUTO          = 0,     /*!< AUTO : BLEH Power signal isolation is controlled automatically
17787                                                      through the interface logic                                               */
17788 } BLEIF_BLECFG_PWRISOCTL_Enum;
17789 
17790 /* ============================================  BLEIF BLECFG BLEHREQCTL [6..7]  ============================================= */
17791 typedef enum {                                  /*!< BLEIF_BLECFG_BLEHREQCTL                                                   */
17792   BLEIF_BLECFG_BLEHREQCTL_ON           = 3,     /*!< ON : BLEH Power-on reg signal is set to on (1).                           */
17793   BLEIF_BLECFG_BLEHREQCTL_OFF          = 2,     /*!< OFF : BLEH Power-on signal is set to off (0).                             */
17794   BLEIF_BLECFG_BLEHREQCTL_AUTO         = 0,     /*!< AUTO : BLEH Power-on signal is controlled by the PWRSM logic
17795                                                      and automatically controlled                                              */
17796 } BLEIF_BLECFG_BLEHREQCTL_Enum;
17797 
17798 /* ============================================  BLEIF BLECFG DCDCFLGCTL [4..5]  ============================================= */
17799 typedef enum {                                  /*!< BLEIF_BLECFG_DCDCFLGCTL                                                   */
17800   BLEIF_BLECFG_DCDCFLGCTL_ON           = 3,     /*!< ON : DCDC Flag signal is set to on (1).                                   */
17801   BLEIF_BLECFG_DCDCFLGCTL_OFF          = 2,     /*!< OFF : DCDC Flag signal is set to off (0).                                 */
17802   BLEIF_BLECFG_DCDCFLGCTL_AUTO         = 0,     /*!< AUTO : DCDC Flag signal is controlled by the PWRSM logic and
17803                                                      automatically controlled                                                  */
17804 } BLEIF_BLECFG_DCDCFLGCTL_Enum;
17805 
17806 /* =============================================  BLEIF BLECFG WAKEUPCTL [2..3]  ============================================= */
17807 typedef enum {                                  /*!< BLEIF_BLECFG_WAKEUPCTL                                                    */
17808   BLEIF_BLECFG_WAKEUPCTL_ON            = 3,     /*!< ON : Wake signal is set to on (1).                                        */
17809   BLEIF_BLECFG_WAKEUPCTL_OFF           = 2,     /*!< OFF : Wake signal is set to off (0).                                      */
17810   BLEIF_BLECFG_WAKEUPCTL_AUTO          = 0,     /*!< AUTO : Wake signal is controlled by the PWRSM logic and automatically
17811                                                      controlled                                                                */
17812 } BLEIF_BLECFG_WAKEUPCTL_Enum;
17813 
17814 /* ==============================================  BLEIF BLECFG BLERSTN [1..1]  ============================================== */
17815 typedef enum {                                  /*!< BLEIF_BLECFG_BLERSTN                                                      */
17816   BLEIF_BLECFG_BLERSTN_ACTIVE          = 1,     /*!< ACTIVE : The reset signal is active (0)                                   */
17817   BLEIF_BLECFG_BLERSTN_INACTIVE        = 0,     /*!< INACTIVE : The reset signal is inactive (1)                               */
17818 } BLEIF_BLECFG_BLERSTN_Enum;
17819 
17820 /* ==============================================  BLEIF BLECFG PWRSMEN [0..0]  ============================================== */
17821 typedef enum {                                  /*!< BLEIF_BLECFG_PWRSMEN                                                      */
17822   BLEIF_BLECFG_PWRSMEN_ON              = 1,     /*!< ON : Internal power state machine is enabled and will sequence
17823                                                      the BLEH power domain as indicated in the design document.
17824                                                      Overrides for the power signals are not enabled.                          */
17825   BLEIF_BLECFG_PWRSMEN_OFF             = 0,     /*!< OFF : Internal power state machine is disabled and will not
17826                                                      sequence the BLEH power domain. The values of the overrides
17827                                                      will be used to drive the output sequencing signals                       */
17828 } BLEIF_BLECFG_PWRSMEN_Enum;
17829 
17830 /* ========================================================  PWRCMD  ========================================================= */
17831 /* ========================================================  BSTATUS  ======================================================== */
17832 /* ==============================================  BLEIF BSTATUS PWRST [8..10]  ============================================== */
17833 typedef enum {                                  /*!< BLEIF_BSTATUS_PWRST                                                       */
17834   BLEIF_BSTATUS_PWRST_OFF              = 0,     /*!< OFF : Internal power state machine is disabled and will not
17835                                                      sequence the BLEH power domain. The values of the overrides
17836                                                      will be used to drive the output sequencing signals                       */
17837   BLEIF_BSTATUS_PWRST_INIT             = 1,     /*!< INIT : Initialization state. BLEH not powered                             */
17838   BLEIF_BSTATUS_PWRST_PWRON            = 2,     /*!< PWRON : Waiting for the power-up of the BLEH                              */
17839   BLEIF_BSTATUS_PWRST_ACTIVE           = 3,     /*!< ACTIVE : The BLE Core is powered and active                               */
17840   BLEIF_BSTATUS_PWRST_SLEEP            = 6,     /*!< SLEEP : The BLE Core has entered sleep mode and the power request
17841                                                      is inactive                                                               */
17842   BLEIF_BSTATUS_PWRST_SHUTDOWN         = 4,     /*!< SHUTDOWN : The BLE Core is in shutdown mode                               */
17843 } BLEIF_BSTATUS_PWRST_Enum;
17844 
17845 /* =============================================  BLEIF BSTATUS B2MSTATE [0..2]  ============================================= */
17846 typedef enum {                                  /*!< BLEIF_BSTATUS_B2MSTATE                                                    */
17847   BLEIF_BSTATUS_B2MSTATE_RESET         = 0,     /*!< RESET : Reset State                                                       */
17848   BLEIF_BSTATUS_B2MSTATE_Sleep         = 1,     /*!< Sleep : Sleep state.                                                      */
17849   BLEIF_BSTATUS_B2MSTATE_Standby       = 2,     /*!< Standby : Standby State                                                   */
17850   BLEIF_BSTATUS_B2MSTATE_Idle          = 3,     /*!< Idle : Idle state                                                         */
17851   BLEIF_BSTATUS_B2MSTATE_Active        = 4,     /*!< Active : Active state.                                                    */
17852 } BLEIF_BSTATUS_B2MSTATE_Enum;
17853 
17854 /* ========================================================  BLEDBG  ========================================================= */
17855 
17856 
17857 /* =========================================================================================================================== */
17858 /* ================                                         CACHECTRL                                         ================ */
17859 /* =========================================================================================================================== */
17860 
17861 /* =======================================================  CACHECFG  ======================================================== */
17862 /* ===========================================  CACHECTRL CACHECFG CONFIG [4..7]  ============================================ */
17863 typedef enum {                                  /*!< CACHECTRL_CACHECFG_CONFIG                                                 */
17864   CACHECTRL_CACHECFG_CONFIG_W1_128B_512E = 4,   /*!< W1_128B_512E : Direct mapped, 128-bit line size, 512 entries
17865                                                      (4 SRAMs active)                                                          */
17866   CACHECTRL_CACHECFG_CONFIG_W2_128B_512E = 5,   /*!< W2_128B_512E : Two-way set associative, 128-bit line size, 512
17867                                                      entries (8 SRAMs active)                                                  */
17868   CACHECTRL_CACHECFG_CONFIG_W1_128B_1024E = 8,  /*!< W1_128B_1024E : Direct mapped, 128-bit line size, 1024 entries
17869                                                      (8 SRAMs active)                                                          */
17870 } CACHECTRL_CACHECFG_CONFIG_Enum;
17871 
17872 /* =========================================================  CTRL  ========================================================== */
17873 /* ===========================================  CACHECTRL CTRL RESET_STAT [1..1]  ============================================ */
17874 typedef enum {                                  /*!< CACHECTRL_CTRL_RESET_STAT                                                 */
17875   CACHECTRL_CTRL_RESET_STAT_CLEAR      = 1,     /*!< CLEAR : Clear Cache Stats                                                 */
17876 } CACHECTRL_CTRL_RESET_STAT_Enum;
17877 
17878 /* =======================================================  NCR0START  ======================================================= */
17879 /* ========================================================  NCR0END  ======================================================== */
17880 /* =======================================================  NCR1START  ======================================================= */
17881 /* ========================================================  NCR1END  ======================================================== */
17882 /* =========================================================  DMON0  ========================================================= */
17883 /* =========================================================  DMON1  ========================================================= */
17884 /* =========================================================  DMON2  ========================================================= */
17885 /* =========================================================  DMON3  ========================================================= */
17886 /* =========================================================  IMON0  ========================================================= */
17887 /* =========================================================  IMON1  ========================================================= */
17888 /* =========================================================  IMON2  ========================================================= */
17889 /* =========================================================  IMON3  ========================================================= */
17890 /* =======================================================  FLASH0CFG  ======================================================= */
17891 /* =========================================  CACHECTRL FLASH0CFG LPMMODE0 [12..13]  ========================================= */
17892 typedef enum {                                  /*!< CACHECTRL_FLASH0CFG_LPMMODE0                                              */
17893   CACHECTRL_FLASH0CFG_LPMMODE0_NEVER   = 0,     /*!< NEVER : High power mode (LPM not used).                                   */
17894   CACHECTRL_FLASH0CFG_LPMMODE0_STANDBY = 1,     /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations,
17895                                                      but asserted while FLASH IDLE.                                            */
17896   CACHECTRL_FLASH0CFG_LPMMODE0_ALWAYS  = 2,     /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT
17897                                                      must be programmed to accommodate longer read access times.               */
17898 } CACHECTRL_FLASH0CFG_LPMMODE0_Enum;
17899 
17900 /* =======================================================  FLASH1CFG  ======================================================= */
17901 /* =========================================  CACHECTRL FLASH1CFG LPMMODE1 [12..13]  ========================================= */
17902 typedef enum {                                  /*!< CACHECTRL_FLASH1CFG_LPMMODE1                                              */
17903   CACHECTRL_FLASH1CFG_LPMMODE1_NEVER   = 0,     /*!< NEVER : High power mode (LPM not used).                                   */
17904   CACHECTRL_FLASH1CFG_LPMMODE1_STANDBY = 1,     /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations,
17905                                                      but asserted while FLASH IDLE.                                            */
17906   CACHECTRL_FLASH1CFG_LPMMODE1_ALWAYS  = 2,     /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT
17907                                                      must be programmed to accommodate longer read access times.               */
17908 } CACHECTRL_FLASH1CFG_LPMMODE1_Enum;
17909 
17910 /* =======================================================  FLASH2CFG  ======================================================= */
17911 /* =========================================  CACHECTRL FLASH2CFG LPMMODE2 [12..13]  ========================================= */
17912 typedef enum {                                  /*!< CACHECTRL_FLASH2CFG_LPMMODE2                                              */
17913   CACHECTRL_FLASH2CFG_LPMMODE2_NEVER   = 0,     /*!< NEVER : High power mode (LPM not used).                                   */
17914   CACHECTRL_FLASH2CFG_LPMMODE2_STANDBY = 1,     /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations,
17915                                                      but asserted while FLASH IDLE.                                            */
17916   CACHECTRL_FLASH2CFG_LPMMODE2_ALWAYS  = 2,     /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT
17917                                                      must be programmed to accommodate longer read access times.               */
17918 } CACHECTRL_FLASH2CFG_LPMMODE2_Enum;
17919 
17920 /* =======================================================  FLASH3CFG  ======================================================= */
17921 /* =========================================  CACHECTRL FLASH3CFG LPMMODE3 [12..13]  ========================================= */
17922 typedef enum {                                  /*!< CACHECTRL_FLASH3CFG_LPMMODE3                                              */
17923   CACHECTRL_FLASH3CFG_LPMMODE3_NEVER   = 0,     /*!< NEVER : High power mode (LPM not used).                                   */
17924   CACHECTRL_FLASH3CFG_LPMMODE3_STANDBY = 1,     /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations,
17925                                                      but asserted while FLASH IDLE.                                            */
17926   CACHECTRL_FLASH3CFG_LPMMODE3_ALWAYS  = 2,     /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT
17927                                                      must be programmed to accommodate longer read access times.               */
17928 } CACHECTRL_FLASH3CFG_LPMMODE3_Enum;
17929 
17930 
17931 
17932 /* =========================================================================================================================== */
17933 /* ================                                          CLKGEN                                           ================ */
17934 /* =========================================================================================================================== */
17935 
17936 /* =========================================================  CALXT  ========================================================= */
17937 /* =========================================================  CALRC  ========================================================= */
17938 /* ========================================================  ACALCTR  ======================================================== */
17939 /* =========================================================  OCTRL  ========================================================= */
17940 /* ===============================================  CLKGEN OCTRL ACAL [8..10]  =============================================== */
17941 typedef enum {                                  /*!< CLKGEN_OCTRL_ACAL                                                         */
17942   CLKGEN_OCTRL_ACAL_DIS                = 0,     /*!< DIS : Disable Autocalibration                                             */
17943   CLKGEN_OCTRL_ACAL_1024SEC            = 2,     /*!< 1024SEC : Autocalibrate every 1024 seconds. Once autocalibration
17944                                                      is done, an interrupt will be triggered at the end of 1024
17945                                                      seconds.                                                                  */
17946   CLKGEN_OCTRL_ACAL_512SEC             = 3,     /*!< 512SEC : Autocalibrate every 512 seconds. Once autocalibration
17947                                                      is done, an interrupt will be trigged at the end of 512
17948                                                      seconds.                                                                  */
17949   CLKGEN_OCTRL_ACAL_XTFREQ             = 6,     /*!< XTFREQ : Frequency measurement using XT. The XT clock is normally
17950                                                      considered much more accurate than the LFRC clock source.                 */
17951   CLKGEN_OCTRL_ACAL_EXTFREQ            = 7,     /*!< EXTFREQ : Frequency measurement using external clock.                     */
17952 } CLKGEN_OCTRL_ACAL_Enum;
17953 
17954 /* ===============================================  CLKGEN OCTRL OSEL [7..7]  ================================================ */
17955 typedef enum {                                  /*!< CLKGEN_OCTRL_OSEL                                                         */
17956   CLKGEN_OCTRL_OSEL_RTC_XT             = 0,     /*!< RTC_XT : RTC uses the XT                                                  */
17957   CLKGEN_OCTRL_OSEL_RTC_LFRC           = 1,     /*!< RTC_LFRC : RTC uses the LFRC                                              */
17958 } CLKGEN_OCTRL_OSEL_Enum;
17959 
17960 /* ================================================  CLKGEN OCTRL FOS [6..6]  ================================================ */
17961 typedef enum {                                  /*!< CLKGEN_OCTRL_FOS                                                          */
17962   CLKGEN_OCTRL_FOS_DIS                 = 0,     /*!< DIS : Disable the oscillator switch on failure function.                  */
17963   CLKGEN_OCTRL_FOS_EN                  = 1,     /*!< EN : Enable the oscillator switch on failure function.                    */
17964 } CLKGEN_OCTRL_FOS_Enum;
17965 
17966 /* ==============================================  CLKGEN OCTRL STOPRC [1..1]  =============================================== */
17967 typedef enum {                                  /*!< CLKGEN_OCTRL_STOPRC                                                       */
17968   CLKGEN_OCTRL_STOPRC_EN               = 0,     /*!< EN : Enable the LFRC Oscillator to drive the RTC                          */
17969   CLKGEN_OCTRL_STOPRC_STOP             = 1,     /*!< STOP : Stop the LFRC Oscillator when driving the RTC                      */
17970 } CLKGEN_OCTRL_STOPRC_Enum;
17971 
17972 /* ==============================================  CLKGEN OCTRL STOPXT [0..0]  =============================================== */
17973 typedef enum {                                  /*!< CLKGEN_OCTRL_STOPXT                                                       */
17974   CLKGEN_OCTRL_STOPXT_EN               = 0,     /*!< EN : Enable the XT Oscillator to drive the RTC                            */
17975   CLKGEN_OCTRL_STOPXT_STOP             = 1,     /*!< STOP : Stop the XT Oscillator when driving the RTC                        */
17976 } CLKGEN_OCTRL_STOPXT_Enum;
17977 
17978 /* ========================================================  CLKOUT  ========================================================= */
17979 /* ===============================================  CLKGEN CLKOUT CKEN [7..7]  =============================================== */
17980 typedef enum {                                  /*!< CLKGEN_CLKOUT_CKEN                                                        */
17981   CLKGEN_CLKOUT_CKEN_DIS               = 0,     /*!< DIS : Disable CLKOUT                                                      */
17982   CLKGEN_CLKOUT_CKEN_EN                = 1,     /*!< EN : Enable CLKOUT                                                        */
17983 } CLKGEN_CLKOUT_CKEN_Enum;
17984 
17985 /* ==============================================  CLKGEN CLKOUT CKSEL [0..5]  =============================================== */
17986 typedef enum {                                  /*!< CLKGEN_CLKOUT_CKSEL                                                       */
17987   CLKGEN_CLKOUT_CKSEL_LFRC             = 0,     /*!< LFRC : LFRC Low Frequency RC                                              */
17988   CLKGEN_CLKOUT_CKSEL_XT_DIV2          = 1,     /*!< XT_DIV2 : XT / 2                                                          */
17989   CLKGEN_CLKOUT_CKSEL_XT_DIV4          = 2,     /*!< XT_DIV4 : XT / 4                                                          */
17990   CLKGEN_CLKOUT_CKSEL_XT_DIV8          = 3,     /*!< XT_DIV8 : XT / 8                                                          */
17991   CLKGEN_CLKOUT_CKSEL_XT_DIV16         = 4,     /*!< XT_DIV16 : XT / 16                                                        */
17992   CLKGEN_CLKOUT_CKSEL_XT_DIV32         = 5,     /*!< XT_DIV32 : XT / 32                                                        */
17993   CLKGEN_CLKOUT_CKSEL_RTC_1Hz          = 16,    /*!< RTC_1Hz : 1 Hz as selected in RTC                                         */
17994   CLKGEN_CLKOUT_CKSEL_XT_DIV2M         = 22,    /*!< XT_DIV2M : XT / 2^21                                                      */
17995   CLKGEN_CLKOUT_CKSEL_XT               = 23,    /*!< XT : Crystal                                                              */
17996   CLKGEN_CLKOUT_CKSEL_CG_100Hz         = 24,    /*!< CG_100Hz : 100 Hz as selected in CLKGEN                                   */
17997   CLKGEN_CLKOUT_CKSEL_HFRC             = 25,    /*!< HFRC : High Frequency RC                                                  */
17998   CLKGEN_CLKOUT_CKSEL_HFRC_DIV4        = 26,    /*!< HFRC_DIV4 : HFRC / 4                                                      */
17999   CLKGEN_CLKOUT_CKSEL_HFRC_DIV8        = 27,    /*!< HFRC_DIV8 : HFRC / 8                                                      */
18000   CLKGEN_CLKOUT_CKSEL_HFRC_DIV16       = 28,    /*!< HFRC_DIV16 : HFRC / 16                                                    */
18001   CLKGEN_CLKOUT_CKSEL_HFRC_DIV64       = 29,    /*!< HFRC_DIV64 : HFRC / 64                                                    */
18002   CLKGEN_CLKOUT_CKSEL_HFRC_DIV128      = 30,    /*!< HFRC_DIV128 : HFRC / 128                                                  */
18003   CLKGEN_CLKOUT_CKSEL_HFRC_DIV256      = 31,    /*!< HFRC_DIV256 : HFRC / 256                                                  */
18004   CLKGEN_CLKOUT_CKSEL_HFRC_DIV512      = 32,    /*!< HFRC_DIV512 : HFRC / 512                                                  */
18005   CLKGEN_CLKOUT_CKSEL_FLASH_CLK        = 34,    /*!< FLASH_CLK : Flash Clock                                                   */
18006   CLKGEN_CLKOUT_CKSEL_LFRC_DIV2        = 35,    /*!< LFRC_DIV2 : LFRC / 2                                                      */
18007   CLKGEN_CLKOUT_CKSEL_LFRC_DIV32       = 36,    /*!< LFRC_DIV32 : LFRC / 32                                                    */
18008   CLKGEN_CLKOUT_CKSEL_LFRC_DIV512      = 37,    /*!< LFRC_DIV512 : LFRC / 512                                                  */
18009   CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K      = 38,    /*!< LFRC_DIV32K : LFRC / 32768                                                */
18010   CLKGEN_CLKOUT_CKSEL_XT_DIV256        = 39,    /*!< XT_DIV256 : XT / 256                                                      */
18011   CLKGEN_CLKOUT_CKSEL_XT_DIV8K         = 40,    /*!< XT_DIV8K : XT / 8192                                                      */
18012   CLKGEN_CLKOUT_CKSEL_XT_DIV64K        = 41,    /*!< XT_DIV64K : XT / 2^16                                                     */
18013   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16      = 42,    /*!< ULFRC_DIV16 : Uncal LFRC / 16                                             */
18014   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128     = 43,    /*!< ULFRC_DIV128 : Uncal LFRC / 128                                           */
18015   CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz        = 44,    /*!< ULFRC_1Hz : Uncal LFRC / 1024                                             */
18016   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K      = 45,    /*!< ULFRC_DIV4K : Uncal LFRC / 4096                                           */
18017   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M      = 46,    /*!< ULFRC_DIV1M : Uncal LFRC / 2^20                                           */
18018   CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K      = 47,    /*!< HFRC_DIV64K : HFRC / 2^16                                                 */
18019   CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M      = 48,    /*!< HFRC_DIV16M : HFRC / 2^24                                                 */
18020   CLKGEN_CLKOUT_CKSEL_LFRC_DIV1M       = 49,    /*!< LFRC_DIV1M : LFRC / 2^20                                                  */
18021   CLKGEN_CLKOUT_CKSEL_HFRCNE           = 50,    /*!< HFRCNE : HFRC (not autoenabled)                                           */
18022   CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8      = 51,    /*!< HFRCNE_DIV8 : HFRC / 8 (not autoenabled)                                  */
18023   CLKGEN_CLKOUT_CKSEL_XTNE             = 53,    /*!< XTNE : XT (not autoenabled)                                               */
18024   CLKGEN_CLKOUT_CKSEL_XTNE_DIV16       = 54,    /*!< XTNE_DIV16 : XT / 16 (not autoenabled)                                    */
18025   CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32     = 55,    /*!< LFRCNE_DIV32 : LFRC / 32 (not autoenabled)                                */
18026   CLKGEN_CLKOUT_CKSEL_LFRCNE           = 57,    /*!< LFRCNE : LFRC (not autoenabled) - Default for undefined values            */
18027 } CLKGEN_CLKOUT_CKSEL_Enum;
18028 
18029 /* ========================================================  CLKKEY  ========================================================= */
18030 /* =============================================  CLKGEN CLKKEY CLKKEY [0..31]  ============================================== */
18031 typedef enum {                                  /*!< CLKGEN_CLKKEY_CLKKEY                                                      */
18032   CLKGEN_CLKKEY_CLKKEY_Key             = 71,    /*!< Key : Key value to unlock the register.                                   */
18033 } CLKGEN_CLKKEY_CLKKEY_Enum;
18034 
18035 /* =========================================================  CCTRL  ========================================================= */
18036 /* ==============================================  CLKGEN CCTRL CORESEL [0..0]  ============================================== */
18037 typedef enum {                                  /*!< CLKGEN_CCTRL_CORESEL                                                      */
18038   CLKGEN_CCTRL_CORESEL_HFRC            = 0,     /*!< HFRC : Core Clock is HFRC                                                 */
18039   CLKGEN_CCTRL_CORESEL_HFRC_DIV2       = 1,     /*!< HFRC_DIV2 : Core Clock is HFRC / 2                                        */
18040 } CLKGEN_CCTRL_CORESEL_Enum;
18041 
18042 /* ========================================================  STATUS  ========================================================= */
18043 /* =========================================================  HFADJ  ========================================================= */
18044 /* ============================================  CLKGEN HFADJ HFADJGAIN [21..23]  ============================================ */
18045 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJGAIN                                                    */
18046   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1     = 0,     /*!< Gain_of_1 : HF Adjust with Gain of 1                                      */
18047   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2 = 1,    /*!< Gain_of_1_in_2 : HF Adjust with Gain of 0.5                               */
18048   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_4 = 2,    /*!< Gain_of_1_in_4 : HF Adjust with Gain of 0.25                              */
18049   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_8 = 3,    /*!< Gain_of_1_in_8 : HF Adjust with Gain of 0.125                             */
18050   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_16 = 4,   /*!< Gain_of_1_in_16 : HF Adjust with Gain of 0.0625                           */
18051   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_32 = 5,   /*!< Gain_of_1_in_32 : HF Adjust with Gain of 0.03125                          */
18052 } CLKGEN_HFADJ_HFADJGAIN_Enum;
18053 
18054 /* ============================================  CLKGEN HFADJ HFWARMUP [20..20]  ============================================= */
18055 typedef enum {                                  /*!< CLKGEN_HFADJ_HFWARMUP                                                     */
18056   CLKGEN_HFADJ_HFWARMUP_1SEC           = 0,     /*!< 1SEC : Autoadjust XT warm-up period = 1-2 seconds                         */
18057   CLKGEN_HFADJ_HFWARMUP_2SEC           = 1,     /*!< 2SEC : Autoadjust XT warm-up period = 2-4 seconds                         */
18058 } CLKGEN_HFADJ_HFWARMUP_Enum;
18059 
18060 /* ==============================================  CLKGEN HFADJ HFADJCK [1..3]  ============================================== */
18061 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJCK                                                      */
18062   CLKGEN_HFADJ_HFADJCK_4SEC            = 0,     /*!< 4SEC : Autoadjust repeat period = 4 seconds                               */
18063   CLKGEN_HFADJ_HFADJCK_16SEC           = 1,     /*!< 16SEC : Autoadjust repeat period = 16 seconds                             */
18064   CLKGEN_HFADJ_HFADJCK_32SEC           = 2,     /*!< 32SEC : Autoadjust repeat period = 32 seconds                             */
18065   CLKGEN_HFADJ_HFADJCK_64SEC           = 3,     /*!< 64SEC : Autoadjust repeat period = 64 seconds                             */
18066   CLKGEN_HFADJ_HFADJCK_128SEC          = 4,     /*!< 128SEC : Autoadjust repeat period = 128 seconds                           */
18067   CLKGEN_HFADJ_HFADJCK_256SEC          = 5,     /*!< 256SEC : Autoadjust repeat period = 256 seconds                           */
18068   CLKGEN_HFADJ_HFADJCK_512SEC          = 6,     /*!< 512SEC : Autoadjust repeat period = 512 seconds                           */
18069   CLKGEN_HFADJ_HFADJCK_1024SEC         = 7,     /*!< 1024SEC : Autoadjust repeat period = 1024 seconds                         */
18070 } CLKGEN_HFADJ_HFADJCK_Enum;
18071 
18072 /* ==============================================  CLKGEN HFADJ HFADJEN [0..0]  ============================================== */
18073 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJEN                                                      */
18074   CLKGEN_HFADJ_HFADJEN_DIS             = 0,     /*!< DIS : Disable the HFRC adjustment                                         */
18075   CLKGEN_HFADJ_HFADJEN_EN              = 1,     /*!< EN : Enable the HFRC adjustment                                           */
18076 } CLKGEN_HFADJ_HFADJEN_Enum;
18077 
18078 /* ======================================================  CLOCKENSTAT  ====================================================== */
18079 /* ========================================  CLKGEN CLOCKENSTAT CLOCKENSTAT [0..31]  ========================================= */
18080 typedef enum {                                  /*!< CLKGEN_CLOCKENSTAT_CLOCKENSTAT                                            */
18081   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_ADC_CLKEN = 0x1, /*!< ADC_CLKEN : Clock enable for the ADC.                                     */
18082   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_ACTIVITY_CLKEN = 0x2,/*!< APBDMA_ACTIVITY_CLKEN : Clock enable for the APBDMA ACTIVITY   */
18083   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOH_CLKEN = 0x4,/*!< APBDMA_AOH_CLKEN : Clock enable for the APBDMA AOH DOMAIN           */
18084   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOL_CLKEN = 0x8,/*!< APBDMA_AOL_CLKEN : Clock enable for the APBDMA AOL DOMAIN           */
18085   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_APB_CLKEN = 0x10,/*!< APBDMA_APB_CLKEN : Clock enable for the APBDMA_APB                 */
18086   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_BLEL_CLKEN = 0x20,/*!< APBDMA_BLEL_CLKEN : Clock enable for the APBDMA_BLEL              */
18087   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPA_CLKEN = 0x40,/*!< APBDMA_HCPA_CLKEN : Clock enable for the APBDMA_HCPA              */
18088   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPB_CLKEN = 0x80,/*!< APBDMA_HCPB_CLKEN : Clock enable for the APBDMA_HCPB             */
18089   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPC_CLKEN = 0x100,/*!< APBDMA_HCPC_CLKEN : Clock enable for the APBDMA_HCPC             */
18090   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_MSPI_CLKEN = 0x200,/*!< APBDMA_MSPI_CLKEN : Clock enable for the APBDMA_MSPI             */
18091   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_MSPI1_CLKEN = 0x400,/*!< APBDMA_MSPI1_CLKEN : Clock enable for the APBDMA_MSPI1         */
18092   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_MSPI2_CLKEN = 0x800,/*!< APBDMA_MSPI2_CLKEN : Clock enable for the APBDMA_MSPI2         */
18093   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_PDM_CLKEN = 0x1000,/*!< APBDMA_PDM_CLKEN : Clock enable for the APBDMA_PDM               */
18094   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK_CLKEN = 0x2000,/*!< BLEIF_CLK_CLKEN : Clock enable for the BLEIF                      */
18095   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK32K_CLKEN = 0x4000,/*!< BLEIF_CLK32K_CLKEN : Clock enable for the BLEIF 32khZ CLOCK   */
18096   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER_CLKEN = 0x8000,/*!< CTIMER_CLKEN : Clock enable for the CTIMER BLOCK                    */
18097   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0A_CLKEN = 0x10000,/*!< CTIMER0A_CLKEN : Clock enable for the CTIMER0A                    */
18098   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0B_CLKEN = 0x20000,/*!< CTIMER0B_CLKEN : Clock enable for the CTIMER0B                   */
18099   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1A_CLKEN = 0x40000,/*!< CTIMER1A_CLKEN : Clock enable for the CTIMER1A                   */
18100   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1B_CLKEN = 0x80000,/*!< CTIMER1B_CLKEN : Clock enable for the CTIMER1B                   */
18101   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2A_CLKEN = 0x100000,/*!< CTIMER2A_CLKEN : Clock enable for the CTIMER2A                  */
18102   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2B_CLKEN = 0x200000,/*!< CTIMER2B_CLKEN : Clock enable for the CTIMER2B                  */
18103   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3A_CLKEN = 0x400000,/*!< CTIMER3A_CLKEN : Clock enable for the CTIMER3A                  */
18104   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3B_CLKEN = 0x800000,/*!< CTIMER3B_CLKEN : Clock enable for the CTIMER3B                  */
18105   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4A_CLKEN = 0x1000000,/*!< CTIMER4A_CLKEN : Clock enable for the CTIMER4A                 */
18106   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4B_CLKEN = 0x2000000,/*!< CTIMER4B_CLKEN : Clock enable for the CTIMER4B                 */
18107   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5A_CLKEN = 0x4000000,/*!< CTIMER5A_CLKEN : Clock enable for the CTIMER5A                 */
18108   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5B_CLKEN = 0x8000000,/*!< CTIMER5B_CLKEN : Clock enable for the CTIMER5B                */
18109   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6A_CLKEN = 0x10000000,/*!< CTIMER6A_CLKEN : Clock enable for the CTIMER6A                */
18110   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6B_CLKEN = 0x20000000,/*!< CTIMER6B_CLKEN : Clock enable for the CTIMER6B                */
18111   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7A_CLKEN = 0x40000000,/*!< CTIMER7A_CLKEN : Clock enable for the CTIMER7A               */
18112   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7B_CLKEN = 0x80000000,/*!< CTIMER7B_CLKEN : Clock enable for the CTIMER7B              */
18113 } CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Enum;
18114 
18115 /* =====================================================  CLOCKEN2STAT  ====================================================== */
18116 /* =======================================  CLKGEN CLOCKEN2STAT CLOCKEN2STAT [0..31]  ======================================== */
18117 typedef enum {                                  /*!< CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT                                          */
18118   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DAP_CLKEN = 0x1,/*!< DAP_CLKEN : Clock enable for the DAP                                     */
18119   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC0_CLKEN = 0x2,/*!< IOMSTRIFC0_CLKEN : Clock enable for the IO MASTER 0x00 IFC INTERFACE */
18120   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC1_CLKEN = 0x4,/*!< IOMSTRIFC1_CLKEN : Clock enable for the IO MASTER 0x01 IFC INTERFACE */
18121   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC2_CLKEN = 0x8,/*!< IOMSTRIFC2_CLKEN : Clock enable for the IO MASTER 0x02 IFC INTERFACE */
18122   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC3_CLKEN = 0x10,/*!< IOMSTRIFC3_CLKEN : Clock enable for the IO MASTER 0x03 IFC INTERFACE */
18123   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC4_CLKEN = 0x20,/*!< IOMSTRIFC4_CLKEN : Clock enable for the IO MASTER 0x04 IFC INTERFACE */
18124   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC5_CLKEN = 0x40,/*!< IOMSTRIFC5_CLKEN : Clock enable for the IO MASTER 0x05 IFC INTERFACE */
18125   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDM_CLKEN = 0x80,/*!< PDM_CLKEN : Clock enable for the PDM                                   */
18126   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDMIFC_CLKEN = 0x100,/*!< PDMIFC_CLKEN : Clock enable for the PDM INTERFACE                   */
18127   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_CLKEN = 0x200,/*!< PWRCTRL_CLKEN : Clock enable for the PWRCTRL                       */
18128   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_COUNT_CLKEN = 0x400,/*!< PWRCTRL_COUNT_CLKEN : Clock enable for the PWRCTRL counter  */
18129   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_RSTGEN_CLKEN = 0x800,/*!< RSTGEN_CLKEN : Clock enable for the RSTGEN                         */
18130   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_CLKEN = 0x1000,/*!< SCARD_CLKEN : Clock enable for the SCARD                            */
18131   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_ALTAPB_CLKEN = 0x2000,/*!< SCARD_ALTAPB_CLKEN : Clock enable for the SCARD ALTAPB       */
18132   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_STIMER_CNT_CLKEN = 0x4000,/*!< STIMER_CNT_CLKEN : Clock enable for the STIMER_CNT_CLKEN      */
18133   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_TPIU_CLKEN = 0x8000,/*!< TPIU_CLKEN : Clock enable for the TPIU_CLKEN                        */
18134   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART0HF_CLKEN = 0x10000,/*!< UART0HF_CLKEN : Clock enable for the UART0 HF                    */
18135   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART1HF_CLKEN = 0x20000,/*!< UART1HF_CLKEN : Clock enable for the UART1 HF                   */
18136   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_WDT_CLKEN = 0x40000,/*!< WDT_CLKEN : Clock enable for the Watchdog timer                     */
18137   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_XT_32KHZ_EN = 0x40000000,/*!< XT_32KHZ_EN : Clock enable for the XT 32KHZ                   */
18138   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_FORCEHFRC = 0x80000000,/*!< FORCEHFRC : HFRC is forced on Status.                          */
18139 } CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Enum;
18140 
18141 /* =====================================================  CLOCKEN3STAT  ====================================================== */
18142 /* =======================================  CLKGEN CLOCKEN3STAT CLOCKEN3STAT [0..31]  ======================================== */
18143 typedef enum {                                  /*!< CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT                                          */
18144   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DAP_enabled = 0x20000,/*!< DAP_enabled : DAP clock is enabled [0x11]                           */
18145   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_VCOMP_enabled = 0x40000,/*!< VCOMP_enabled : VCOMP power-down indicator [0x12]                 */
18146   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_XTAL_enabled = 0x1000000,/*!< XTAL_enabled : XTAL is enabled [0x18]                            */
18147   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_enabled = 0x2000000,/*!< HFRC_enabled : HFRC is enabled [0x19]                            */
18148   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFADJEN = 0x4000000,/*!< HFADJEN : HFRC Adjust enabled [0x1a]                                  */
18149   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_en_out = 0x8000000,/*!< HFRC_en_out : HFRC Enabled out [0x1b]                            */
18150   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RTC_XT = 0x10000000,/*!< RTC_XT : RTC use XT [0x1c]                                            */
18151   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_xtal_en = 0x20000000,/*!< clkout_xtal_en : XTAL clkout enabled [0x1d]                   */
18152   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_hfrc_en = 0x40000000,/*!< clkout_hfrc_en : HFRC clkout enabled [0x1e]                  */
18153   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_flashclk_en = 0x80000000,/*!< flashclk_en : Flash clk is enabled [31]                      */
18154 } CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Enum;
18155 
18156 /* =======================================================  FREQCTRL  ======================================================== */
18157 /* ============================================  CLKGEN FREQCTRL BURSTREQ [0..0]  ============================================ */
18158 typedef enum {                                  /*!< CLKGEN_FREQCTRL_BURSTREQ                                                  */
18159   CLKGEN_FREQCTRL_BURSTREQ_DIS         = 0,     /*!< DIS : Frequency for ARM core stays at 48MHz                               */
18160   CLKGEN_FREQCTRL_BURSTREQ_EN          = 1,     /*!< EN : Frequency for ARM core is increased to 96MHz                         */
18161 } CLKGEN_FREQCTRL_BURSTREQ_Enum;
18162 
18163 /* =====================================================  BLEBUCKTONADJ  ===================================================== */
18164 /* =====================================  CLKGEN BLEBUCKTONADJ ZEROLENDETECTEN [27..27]  ===================================== */
18165 typedef enum {                                  /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN                                      */
18166   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_DIS = 0, /*!< DIS : Disable Zero Length Detect                                          */
18167   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_EN = 1,  /*!< EN : Enable Zero Length Detect                                            */
18168 } CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Enum;
18169 
18170 /* ====================================  CLKGEN BLEBUCKTONADJ ZEROLENDETECTTRIM [23..26]  ==================================== */
18171 typedef enum {                                  /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM                                    */
18172   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetF = 15,/*!< SetF : Indicator send when the BLE BUCK asserts blebuck_comp1
18173                                                      for about 81 us (10 percent margin of error) or more                      */
18174   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetE = 14,/*!< SetE : Indicator send when the BLE BUCK asserts blebuck_comp1
18175                                                      for about 75.6 us (10 percent margin of error) or more                    */
18176   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetD = 13,/*!< SetD : Indicator send when the BLE BUCK asserts blebuck_comp1
18177                                                      for about 70.2 us (10 percent margin of error) or more                    */
18178   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetC = 12,/*!< SetC : Indicator send when the BLE BUCK asserts blebuck_comp1
18179                                                      for about 64.8 us (10 percent margin of error) or more                    */
18180   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetB = 11,/*!< SetB : Indicator send when the BLE BUCK asserts blebuck_comp1
18181                                                      for about 59.4 us (10 percent margin of error) or more                    */
18182   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetA = 10,/*!< SetA : Indicator send when the BLE BUCK asserts blebuck_comp1
18183                                                      for about 54.0 us (10 percent margin of error) or more                    */
18184   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set9 = 9,/*!< Set9 : Indicator send when the BLE BUCK asserts blebuck_comp1
18185                                                      for about 48.6 us (10 percent margin of error) or more                    */
18186   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set8 = 8,/*!< Set8 : Indicator send when the BLE BUCK asserts blebuck_comp1
18187                                                      for about 43.2 us (10 percent margin of error) or more                    */
18188   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set7 = 7,/*!< Set7 : Indicator send when the BLE BUCK asserts blebuck_comp1
18189                                                      for about 37.8 us (10 percent margin of error) or more                    */
18190   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set6 = 6,/*!< Set6 : Indicator send when the BLE BUCK asserts blebuck_comp1
18191                                                      for about 32.4 us (10 percent margin of error) or more                    */
18192   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set5 = 5,/*!< Set5 : Indicator send when the BLE BUCK asserts blebuck_comp1
18193                                                      for about 27.0 us (10 percent margin of error) or more                    */
18194   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set4 = 4,/*!< Set4 : Indicator send when the BLE BUCK asserts blebuck_comp1
18195                                                      for about 21.6 us (10 percent margin of error) or more                    */
18196   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set3 = 3,/*!< Set3 : Indicator send when the BLE BUCK asserts blebuck_comp1
18197                                                      for about 16.2 us (10 percent margin of error) or more                    */
18198   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set2 = 2,/*!< Set2 : Indicator send when the BLE BUCK asserts blebuck_comp1
18199                                                      for about 10.8 us (10 percent margin of error) or more                    */
18200   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set1 = 1,/*!< Set1 : Indicator send when the BLE BUCK asserts blebuck_comp1
18201                                                      for about 5.4 us (10 percent margin of error) or more                     */
18202   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set0 = 0,/*!< Set0 : Indicator send when the BLE BUCK asserts blebuck_comp1
18203                                                      for about 2.0 us (10 percent margin of error) or more                     */
18204 } CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Enum;
18205 
18206 /* =======================================  CLKGEN BLEBUCKTONADJ TONADJUSTEN [22..22]  ======================================= */
18207 typedef enum {                                  /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTEN                                          */
18208   CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_DIS = 0,     /*!< DIS : Disable Adjust for BLE BUCK TON trim                                */
18209   CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_EN  = 1,     /*!< EN : Enable Adjust for BLE BUCK TON trim                                  */
18210 } CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Enum;
18211 
18212 /* =====================================  CLKGEN BLEBUCKTONADJ TONADJUSTPERIOD [20..21]  ===================================== */
18213 typedef enum {                                  /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD                                      */
18214   CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_3KHz = 3,/*!< HFRC_3KHz : Adjust done for every 1 3KHz period                      */
18215   CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_12KHz = 2,/*!< HFRC_12KHz : Adjust done for every 1 12KHz period                   */
18216   CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_47KHz = 1,/*!< HFRC_47KHz : Adjust done for every 1 47KHz period                   */
18217   CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_94KHz = 0,/*!< HFRC_94KHz : Adjust done for every 1 94KHz period                   */
18218 } CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Enum;
18219 
18220 /* =======================================================  INTRPTEN  ======================================================== */
18221 /* ======================================================  INTRPTSTAT  ======================================================= */
18222 /* =======================================================  INTRPTCLR  ======================================================= */
18223 /* =======================================================  INTRPTSET  ======================================================= */
18224 
18225 
18226 /* =========================================================================================================================== */
18227 /* ================                                          CTIMER                                           ================ */
18228 /* =========================================================================================================================== */
18229 
18230 /* =========================================================  TMR0  ========================================================== */
18231 /* ========================================================  CMPRA0  ========================================================= */
18232 /* ========================================================  CMPRB0  ========================================================= */
18233 /* =========================================================  CTRL0  ========================================================= */
18234 /* =============================================  CTIMER CTRL0 CTLINK0 [31..31]  ============================================= */
18235 typedef enum {                                  /*!< CTIMER_CTRL0_CTLINK0                                                      */
18236   CTIMER_CTRL0_CTLINK0_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A0/B0 timers as two independent 16-bit
18237                                                      timers (default).                                                         */
18238   CTIMER_CTRL0_CTLINK0_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A0/B0 timers into a single 32-bit timer.               */
18239 } CTIMER_CTRL0_CTLINK0_Enum;
18240 
18241 /* ============================================  CTIMER CTRL0 TMRB0POL [28..28]  ============================================= */
18242 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0POL                                                     */
18243   CTIMER_CTRL0_TMRB0POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB0 pin is the same as the
18244                                                      timer output.                                                             */
18245   CTIMER_CTRL0_TMRB0POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB0 pin is the inverse of
18246                                                      the timer output.                                                         */
18247 } CTIMER_CTRL0_TMRB0POL_Enum;
18248 
18249 /* ============================================  CTIMER CTRL0 TMRB0CLR [27..27]  ============================================= */
18250 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0CLR                                                     */
18251   CTIMER_CTRL0_TMRB0CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B0 to run                                       */
18252   CTIMER_CTRL0_TMRB0CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B0 at 0x0000.                                 */
18253 } CTIMER_CTRL0_TMRB0CLR_Enum;
18254 
18255 /* ============================================  CTIMER CTRL0 TMRB0IE1 [26..26]  ============================================= */
18256 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0IE1                                                     */
18257   CTIMER_CTRL0_TMRB0IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B0 from generating an interrupt
18258                                                      based on COMPR1.                                                          */
18259   CTIMER_CTRL0_TMRB0IE1_EN             = 1,     /*!< EN : Enable counter/timer B0 to generate an interrupt based
18260                                                      on COMPR1.                                                                */
18261 } CTIMER_CTRL0_TMRB0IE1_Enum;
18262 
18263 /* ============================================  CTIMER CTRL0 TMRB0IE0 [25..25]  ============================================= */
18264 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0IE0                                                     */
18265   CTIMER_CTRL0_TMRB0IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B0 from generating an interrupt
18266                                                      based on COMPR0.                                                          */
18267   CTIMER_CTRL0_TMRB0IE0_EN             = 1,     /*!< EN : Enable counter/timer B0 to generate an interrupt based
18268                                                      on COMPR0                                                                 */
18269 } CTIMER_CTRL0_TMRB0IE0_Enum;
18270 
18271 /* =============================================  CTIMER CTRL0 TMRB0FN [22..24]  ============================================= */
18272 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0FN                                                      */
18273   CTIMER_CTRL0_TMRB0FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
18274                                                      to CMPR0B0, stop.                                                         */
18275   CTIMER_CTRL0_TMRB0FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
18276                                                      pulses). Count to CMPR0B0, restart.                                       */
18277   CTIMER_CTRL0_TMRB0FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B0, assert,
18278                                                      count to CMPR1B0, deassert, stop.                                         */
18279   CTIMER_CTRL0_TMRB0FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B0, assert, count
18280                                                      to CMPR1B0, deassert, restart.                                            */
18281   CTIMER_CTRL0_TMRB0FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
18282   CTIMER_CTRL0_TMRB0FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
18283   CTIMER_CTRL0_TMRB0FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
18284   CTIMER_CTRL0_TMRB0FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
18285 } CTIMER_CTRL0_TMRB0FN_Enum;
18286 
18287 /* ============================================  CTIMER CTRL0 TMRB0CLK [17..21]  ============================================= */
18288 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0CLK                                                     */
18289   CTIMER_CTRL0_TMRB0CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
18290   CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
18291   CTIMER_CTRL0_TMRB0CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
18292   CTIMER_CTRL0_TMRB0CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
18293   CTIMER_CTRL0_TMRB0CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
18294   CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
18295   CTIMER_CTRL0_TMRB0CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
18296   CTIMER_CTRL0_TMRB0CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
18297   CTIMER_CTRL0_TMRB0CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
18298   CTIMER_CTRL0_TMRB0CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
18299   CTIMER_CTRL0_TMRB0CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
18300   CTIMER_CTRL0_TMRB0CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
18301   CTIMER_CTRL0_TMRB0CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
18302   CTIMER_CTRL0_TMRB0CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
18303   CTIMER_CTRL0_TMRB0CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
18304   CTIMER_CTRL0_TMRB0CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
18305                                                      available when MCU is in active mode)                                     */
18306   CTIMER_CTRL0_TMRB0CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
18307   CTIMER_CTRL0_TMRB0CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
18308   CTIMER_CTRL0_TMRB0CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
18309   CTIMER_CTRL0_TMRB0CLK_CTMRA0         = 20,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
18310   CTIMER_CTRL0_TMRB0CLK_CTMRB1         = 21,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
18311   CTIMER_CTRL0_TMRB0CLK_CTMRA1         = 22,    /*!< CTMRA1 : Clock source is CTIMERA1 OUT.                                    */
18312   CTIMER_CTRL0_TMRB0CLK_CTMRA2         = 23,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
18313   CTIMER_CTRL0_TMRB0CLK_CTMRB2         = 24,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
18314   CTIMER_CTRL0_TMRB0CLK_CTMRB3         = 25,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
18315   CTIMER_CTRL0_TMRB0CLK_CTMRB4         = 26,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
18316   CTIMER_CTRL0_TMRB0CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
18317   CTIMER_CTRL0_TMRB0CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
18318   CTIMER_CTRL0_TMRB0CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
18319   CTIMER_CTRL0_TMRB0CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
18320   CTIMER_CTRL0_TMRB0CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
18321 } CTIMER_CTRL0_TMRB0CLK_Enum;
18322 
18323 /* =============================================  CTIMER CTRL0 TMRB0EN [16..16]  ============================================= */
18324 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0EN                                                      */
18325   CTIMER_CTRL0_TMRB0EN_DIS             = 0,     /*!< DIS : Counter/Timer B0 Disable.                                           */
18326   CTIMER_CTRL0_TMRB0EN_EN              = 1,     /*!< EN : Counter/Timer B0 Enable.                                             */
18327 } CTIMER_CTRL0_TMRB0EN_Enum;
18328 
18329 /* ============================================  CTIMER CTRL0 TMRA0POL [12..12]  ============================================= */
18330 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0POL                                                     */
18331   CTIMER_CTRL0_TMRA0POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA0 pin is the same as the
18332                                                      timer output.                                                             */
18333   CTIMER_CTRL0_TMRA0POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA0 pin is the inverse of
18334                                                      the timer output.                                                         */
18335 } CTIMER_CTRL0_TMRA0POL_Enum;
18336 
18337 /* ============================================  CTIMER CTRL0 TMRA0CLR [11..11]  ============================================= */
18338 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0CLR                                                     */
18339   CTIMER_CTRL0_TMRA0CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A0 to run                                       */
18340   CTIMER_CTRL0_TMRA0CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A0 at 0x0000.                                 */
18341 } CTIMER_CTRL0_TMRA0CLR_Enum;
18342 
18343 /* ============================================  CTIMER CTRL0 TMRA0IE1 [10..10]  ============================================= */
18344 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0IE1                                                     */
18345   CTIMER_CTRL0_TMRA0IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A0 from generating an interrupt
18346                                                      based on COMPR1.                                                          */
18347   CTIMER_CTRL0_TMRA0IE1_EN             = 1,     /*!< EN : Enable counter/timer A0 to generate an interrupt based
18348                                                      on COMPR1.                                                                */
18349 } CTIMER_CTRL0_TMRA0IE1_Enum;
18350 
18351 /* =============================================  CTIMER CTRL0 TMRA0IE0 [9..9]  ============================================== */
18352 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0IE0                                                     */
18353   CTIMER_CTRL0_TMRA0IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A0 from generating an interrupt
18354                                                      based on COMPR0.                                                          */
18355   CTIMER_CTRL0_TMRA0IE0_EN             = 1,     /*!< EN : Enable counter/timer A0 to generate an interrupt based
18356                                                      on COMPR0.                                                                */
18357 } CTIMER_CTRL0_TMRA0IE0_Enum;
18358 
18359 /* ==============================================  CTIMER CTRL0 TMRA0FN [6..8]  ============================================== */
18360 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0FN                                                      */
18361   CTIMER_CTRL0_TMRA0FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
18362                                                      to CMPR0A0, stop.                                                         */
18363   CTIMER_CTRL0_TMRA0FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
18364                                                      pulses). Count to CMPR0A0, restart.                                       */
18365   CTIMER_CTRL0_TMRA0FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A0, assert,
18366                                                      count to CMPR1A0, deassert, stop.                                         */
18367   CTIMER_CTRL0_TMRA0FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A0, assert, count
18368                                                      to CMPR1A0, deassert, restart.                                            */
18369   CTIMER_CTRL0_TMRA0FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
18370   CTIMER_CTRL0_TMRA0FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
18371   CTIMER_CTRL0_TMRA0FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
18372   CTIMER_CTRL0_TMRA0FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
18373 } CTIMER_CTRL0_TMRA0FN_Enum;
18374 
18375 /* =============================================  CTIMER CTRL0 TMRA0CLK [1..5]  ============================================== */
18376 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0CLK                                                     */
18377   CTIMER_CTRL0_TMRA0CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
18378   CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
18379   CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
18380   CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
18381   CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
18382   CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
18383   CTIMER_CTRL0_TMRA0CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
18384   CTIMER_CTRL0_TMRA0CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
18385   CTIMER_CTRL0_TMRA0CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
18386   CTIMER_CTRL0_TMRA0CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
18387   CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
18388   CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
18389   CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
18390   CTIMER_CTRL0_TMRA0CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
18391   CTIMER_CTRL0_TMRA0CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
18392   CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
18393                                                      available when MCU is in active mode)                                     */
18394   CTIMER_CTRL0_TMRA0CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
18395   CTIMER_CTRL0_TMRA0CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
18396   CTIMER_CTRL0_TMRA0CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
18397   CTIMER_CTRL0_TMRA0CLK_CTMRB0         = 20,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
18398   CTIMER_CTRL0_TMRA0CLK_CTMRA1         = 21,    /*!< CTMRA1 : Clock source is CTIMERA1 OUT.                                    */
18399   CTIMER_CTRL0_TMRA0CLK_CTMRB1         = 22,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
18400   CTIMER_CTRL0_TMRA0CLK_CTMRA2         = 23,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
18401   CTIMER_CTRL0_TMRA0CLK_CTMRB2         = 24,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
18402   CTIMER_CTRL0_TMRA0CLK_CTMRB3         = 25,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
18403   CTIMER_CTRL0_TMRA0CLK_CTMRB4         = 26,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
18404   CTIMER_CTRL0_TMRA0CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
18405   CTIMER_CTRL0_TMRA0CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
18406   CTIMER_CTRL0_TMRA0CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
18407   CTIMER_CTRL0_TMRA0CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
18408   CTIMER_CTRL0_TMRA0CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
18409 } CTIMER_CTRL0_TMRA0CLK_Enum;
18410 
18411 /* ==============================================  CTIMER CTRL0 TMRA0EN [0..0]  ============================================== */
18412 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0EN                                                      */
18413   CTIMER_CTRL0_TMRA0EN_DIS             = 0,     /*!< DIS : Counter/Timer A0 Disable.                                           */
18414   CTIMER_CTRL0_TMRA0EN_EN              = 1,     /*!< EN : Counter/Timer A0 Enable.                                             */
18415 } CTIMER_CTRL0_TMRA0EN_Enum;
18416 
18417 /* =======================================================  CMPRAUXA0  ======================================================= */
18418 /* =======================================================  CMPRAUXB0  ======================================================= */
18419 /* =========================================================  AUX0  ========================================================== */
18420 /* ============================================  CTIMER AUX0 TMRB0EN23 [30..30]  ============================================= */
18421 typedef enum {                                  /*!< CTIMER_AUX0_TMRB0EN23                                                     */
18422   CTIMER_AUX0_TMRB0EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
18423   CTIMER_AUX0_TMRB0EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
18424 } CTIMER_AUX0_TMRB0EN23_Enum;
18425 
18426 /* ============================================  CTIMER AUX0 TMRB0POL23 [29..29]  ============================================ */
18427 typedef enum {                                  /*!< CTIMER_AUX0_TMRB0POL23                                                    */
18428   CTIMER_AUX0_TMRB0POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
18429   CTIMER_AUX0_TMRB0POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
18430 } CTIMER_AUX0_TMRB0POL23_Enum;
18431 
18432 /* ============================================  CTIMER AUX0 TMRB0TINV [28..28]  ============================================= */
18433 typedef enum {                                  /*!< CTIMER_AUX0_TMRB0TINV                                                     */
18434   CTIMER_AUX0_TMRB0TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
18435   CTIMER_AUX0_TMRB0TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
18436 } CTIMER_AUX0_TMRB0TINV_Enum;
18437 
18438 /* ===========================================  CTIMER AUX0 TMRB0NOSYNC [27..27]  ============================================ */
18439 typedef enum {                                  /*!< CTIMER_AUX0_TMRB0NOSYNC                                                   */
18440   CTIMER_AUX0_TMRB0NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
18441   CTIMER_AUX0_TMRB0NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
18442 } CTIMER_AUX0_TMRB0NOSYNC_Enum;
18443 
18444 /* ============================================  CTIMER AUX0 TMRB0TRIG [23..26]  ============================================= */
18445 typedef enum {                                  /*!< CTIMER_AUX0_TMRB0TRIG                                                     */
18446   CTIMER_AUX0_TMRB0TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
18447   CTIMER_AUX0_TMRB0TRIG_A0OUT          = 1,     /*!< A0OUT : Trigger source is CTIMERA0 OUT.                                   */
18448   CTIMER_AUX0_TMRB0TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
18449   CTIMER_AUX0_TMRB0TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
18450   CTIMER_AUX0_TMRB0TRIG_B2OUT          = 4,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
18451   CTIMER_AUX0_TMRB0TRIG_B5OUT          = 5,     /*!< B5OUT : Trigger source is CTIMERB5 OUT.                                   */
18452   CTIMER_AUX0_TMRB0TRIG_A4OUT          = 6,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
18453   CTIMER_AUX0_TMRB0TRIG_B4OUT          = 7,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
18454   CTIMER_AUX0_TMRB0TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
18455   CTIMER_AUX0_TMRB0TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
18456   CTIMER_AUX0_TMRB0TRIG_B7OUT2         = 10,    /*!< B7OUT2 : Trigger source is CTIMERB7 OUT2.                                 */
18457   CTIMER_AUX0_TMRB0TRIG_A2OUT2         = 11,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
18458   CTIMER_AUX0_TMRB0TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
18459   CTIMER_AUX0_TMRB0TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
18460   CTIMER_AUX0_TMRB0TRIG_B5OUT2DUAL     = 14,    /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge.                  */
18461   CTIMER_AUX0_TMRB0TRIG_A5OUT2DUAL     = 15,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
18462 } CTIMER_AUX0_TMRB0TRIG_Enum;
18463 
18464 /* ============================================  CTIMER AUX0 TMRA0EN23 [14..14]  ============================================= */
18465 typedef enum {                                  /*!< CTIMER_AUX0_TMRA0EN23                                                     */
18466   CTIMER_AUX0_TMRA0EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
18467   CTIMER_AUX0_TMRA0EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
18468 } CTIMER_AUX0_TMRA0EN23_Enum;
18469 
18470 /* ============================================  CTIMER AUX0 TMRA0POL23 [13..13]  ============================================ */
18471 typedef enum {                                  /*!< CTIMER_AUX0_TMRA0POL23                                                    */
18472   CTIMER_AUX0_TMRA0POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
18473   CTIMER_AUX0_TMRA0POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
18474 } CTIMER_AUX0_TMRA0POL23_Enum;
18475 
18476 /* ============================================  CTIMER AUX0 TMRA0TINV [12..12]  ============================================= */
18477 typedef enum {                                  /*!< CTIMER_AUX0_TMRA0TINV                                                     */
18478   CTIMER_AUX0_TMRA0TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
18479   CTIMER_AUX0_TMRA0TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
18480 } CTIMER_AUX0_TMRA0TINV_Enum;
18481 
18482 /* ===========================================  CTIMER AUX0 TMRA0NOSYNC [11..11]  ============================================ */
18483 typedef enum {                                  /*!< CTIMER_AUX0_TMRA0NOSYNC                                                   */
18484   CTIMER_AUX0_TMRA0NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
18485   CTIMER_AUX0_TMRA0NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
18486 } CTIMER_AUX0_TMRA0NOSYNC_Enum;
18487 
18488 /* =============================================  CTIMER AUX0 TMRA0TRIG [7..10]  ============================================= */
18489 typedef enum {                                  /*!< CTIMER_AUX0_TMRA0TRIG                                                     */
18490   CTIMER_AUX0_TMRA0TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
18491   CTIMER_AUX0_TMRA0TRIG_B0OUT          = 1,     /*!< B0OUT : Trigger source is CTIMERB0 OUT.                                   */
18492   CTIMER_AUX0_TMRA0TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
18493   CTIMER_AUX0_TMRA0TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
18494   CTIMER_AUX0_TMRA0TRIG_A1OUT          = 4,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
18495   CTIMER_AUX0_TMRA0TRIG_B1OUT          = 5,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
18496   CTIMER_AUX0_TMRA0TRIG_A5OUT          = 6,     /*!< A5OUT : Trigger source is CTIMERA5 OUT.                                   */
18497   CTIMER_AUX0_TMRA0TRIG_B5OUT          = 7,     /*!< B5OUT : Trigger source is CTIMERB5 OUT.                                   */
18498   CTIMER_AUX0_TMRA0TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
18499   CTIMER_AUX0_TMRA0TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
18500   CTIMER_AUX0_TMRA0TRIG_B6OUT2         = 10,    /*!< B6OUT2 : Trigger source is CTIMERB6 OUT2.                                 */
18501   CTIMER_AUX0_TMRA0TRIG_A2OUT2         = 11,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
18502   CTIMER_AUX0_TMRA0TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
18503   CTIMER_AUX0_TMRA0TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
18504   CTIMER_AUX0_TMRA0TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
18505   CTIMER_AUX0_TMRA0TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
18506 } CTIMER_AUX0_TMRA0TRIG_Enum;
18507 
18508 /* =========================================================  TMR1  ========================================================== */
18509 /* ========================================================  CMPRA1  ========================================================= */
18510 /* ========================================================  CMPRB1  ========================================================= */
18511 /* =========================================================  CTRL1  ========================================================= */
18512 /* =============================================  CTIMER CTRL1 CTLINK1 [31..31]  ============================================= */
18513 typedef enum {                                  /*!< CTIMER_CTRL1_CTLINK1                                                      */
18514   CTIMER_CTRL1_CTLINK1_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A1/B1 timers as two independent 16-bit
18515                                                      timers (default).                                                         */
18516   CTIMER_CTRL1_CTLINK1_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A1/B1 timers into a single 32-bit timer.               */
18517 } CTIMER_CTRL1_CTLINK1_Enum;
18518 
18519 /* ============================================  CTIMER CTRL1 TMRB1POL [28..28]  ============================================= */
18520 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1POL                                                     */
18521   CTIMER_CTRL1_TMRB1POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB1 pin is the same as the
18522                                                      timer output.                                                             */
18523   CTIMER_CTRL1_TMRB1POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB1 pin is the inverse of
18524                                                      the timer output.                                                         */
18525 } CTIMER_CTRL1_TMRB1POL_Enum;
18526 
18527 /* ============================================  CTIMER CTRL1 TMRB1CLR [27..27]  ============================================= */
18528 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1CLR                                                     */
18529   CTIMER_CTRL1_TMRB1CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B1 to run                                       */
18530   CTIMER_CTRL1_TMRB1CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B1 at 0x0000.                                 */
18531 } CTIMER_CTRL1_TMRB1CLR_Enum;
18532 
18533 /* ============================================  CTIMER CTRL1 TMRB1IE1 [26..26]  ============================================= */
18534 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1IE1                                                     */
18535   CTIMER_CTRL1_TMRB1IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B1 from generating an interrupt
18536                                                      based on COMPR1.                                                          */
18537   CTIMER_CTRL1_TMRB1IE1_EN             = 1,     /*!< EN : Enable counter/timer B1 to generate an interrupt based
18538                                                      on COMPR1.                                                                */
18539 } CTIMER_CTRL1_TMRB1IE1_Enum;
18540 
18541 /* ============================================  CTIMER CTRL1 TMRB1IE0 [25..25]  ============================================= */
18542 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1IE0                                                     */
18543   CTIMER_CTRL1_TMRB1IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B1 from generating an interrupt
18544                                                      based on COMPR0.                                                          */
18545   CTIMER_CTRL1_TMRB1IE0_EN             = 1,     /*!< EN : Enable counter/timer B1 to generate an interrupt based
18546                                                      on COMPR0                                                                 */
18547 } CTIMER_CTRL1_TMRB1IE0_Enum;
18548 
18549 /* =============================================  CTIMER CTRL1 TMRB1FN [22..24]  ============================================= */
18550 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1FN                                                      */
18551   CTIMER_CTRL1_TMRB1FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
18552                                                      to CMPR0B1, stop.                                                         */
18553   CTIMER_CTRL1_TMRB1FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
18554                                                      pulses). Count to CMPR0B1, restart.                                       */
18555   CTIMER_CTRL1_TMRB1FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B1, assert,
18556                                                      count to CMPR1B1, deassert, stop.                                         */
18557   CTIMER_CTRL1_TMRB1FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B1, assert, count
18558                                                      to CMPR1B1, deassert, restart.                                            */
18559   CTIMER_CTRL1_TMRB1FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
18560   CTIMER_CTRL1_TMRB1FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
18561   CTIMER_CTRL1_TMRB1FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
18562   CTIMER_CTRL1_TMRB1FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
18563 } CTIMER_CTRL1_TMRB1FN_Enum;
18564 
18565 /* ============================================  CTIMER CTRL1 TMRB1CLK [17..21]  ============================================= */
18566 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1CLK                                                     */
18567   CTIMER_CTRL1_TMRB1CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
18568   CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
18569   CTIMER_CTRL1_TMRB1CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
18570   CTIMER_CTRL1_TMRB1CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
18571   CTIMER_CTRL1_TMRB1CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
18572   CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
18573   CTIMER_CTRL1_TMRB1CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
18574   CTIMER_CTRL1_TMRB1CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
18575   CTIMER_CTRL1_TMRB1CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
18576   CTIMER_CTRL1_TMRB1CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
18577   CTIMER_CTRL1_TMRB1CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
18578   CTIMER_CTRL1_TMRB1CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
18579   CTIMER_CTRL1_TMRB1CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
18580   CTIMER_CTRL1_TMRB1CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
18581   CTIMER_CTRL1_TMRB1CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
18582   CTIMER_CTRL1_TMRB1CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
18583                                                      available when MCU is in active mode)                                     */
18584   CTIMER_CTRL1_TMRB1CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
18585   CTIMER_CTRL1_TMRB1CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
18586   CTIMER_CTRL1_TMRB1CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
18587   CTIMER_CTRL1_TMRB1CLK_CTMRA1         = 20,    /*!< CTMRA1 : Clock source is CTIMERA1 OUT.                                    */
18588   CTIMER_CTRL1_TMRB1CLK_CTMRA0         = 21,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
18589   CTIMER_CTRL1_TMRB1CLK_CTMRB0         = 22,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
18590   CTIMER_CTRL1_TMRB1CLK_CTMRA2         = 23,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
18591   CTIMER_CTRL1_TMRB1CLK_CTMRB2         = 24,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
18592   CTIMER_CTRL1_TMRB1CLK_CTMRB3         = 25,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
18593   CTIMER_CTRL1_TMRB1CLK_CTMRB4         = 26,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
18594   CTIMER_CTRL1_TMRB1CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
18595   CTIMER_CTRL1_TMRB1CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
18596   CTIMER_CTRL1_TMRB1CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
18597   CTIMER_CTRL1_TMRB1CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
18598   CTIMER_CTRL1_TMRB1CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
18599 } CTIMER_CTRL1_TMRB1CLK_Enum;
18600 
18601 /* =============================================  CTIMER CTRL1 TMRB1EN [16..16]  ============================================= */
18602 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1EN                                                      */
18603   CTIMER_CTRL1_TMRB1EN_DIS             = 0,     /*!< DIS : Counter/Timer B1 Disable.                                           */
18604   CTIMER_CTRL1_TMRB1EN_EN              = 1,     /*!< EN : Counter/Timer B1 Enable.                                             */
18605 } CTIMER_CTRL1_TMRB1EN_Enum;
18606 
18607 /* ============================================  CTIMER CTRL1 TMRA1POL [12..12]  ============================================= */
18608 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1POL                                                     */
18609   CTIMER_CTRL1_TMRA1POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA1 pin is the same as the
18610                                                      timer output.                                                             */
18611   CTIMER_CTRL1_TMRA1POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA1 pin is the inverse of
18612                                                      the timer output.                                                         */
18613 } CTIMER_CTRL1_TMRA1POL_Enum;
18614 
18615 /* ============================================  CTIMER CTRL1 TMRA1CLR [11..11]  ============================================= */
18616 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1CLR                                                     */
18617   CTIMER_CTRL1_TMRA1CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A1 to run                                       */
18618   CTIMER_CTRL1_TMRA1CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A1 at 0x0000.                                 */
18619 } CTIMER_CTRL1_TMRA1CLR_Enum;
18620 
18621 /* ============================================  CTIMER CTRL1 TMRA1IE1 [10..10]  ============================================= */
18622 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1IE1                                                     */
18623   CTIMER_CTRL1_TMRA1IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A1 from generating an interrupt
18624                                                      based on COMPR1.                                                          */
18625   CTIMER_CTRL1_TMRA1IE1_EN             = 1,     /*!< EN : Enable counter/timer A1 to generate an interrupt based
18626                                                      on COMPR1.                                                                */
18627 } CTIMER_CTRL1_TMRA1IE1_Enum;
18628 
18629 /* =============================================  CTIMER CTRL1 TMRA1IE0 [9..9]  ============================================== */
18630 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1IE0                                                     */
18631   CTIMER_CTRL1_TMRA1IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A1 from generating an interrupt
18632                                                      based on COMPR0.                                                          */
18633   CTIMER_CTRL1_TMRA1IE0_EN             = 1,     /*!< EN : Enable counter/timer A1 to generate an interrupt based
18634                                                      on COMPR0.                                                                */
18635 } CTIMER_CTRL1_TMRA1IE0_Enum;
18636 
18637 /* ==============================================  CTIMER CTRL1 TMRA1FN [6..8]  ============================================== */
18638 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1FN                                                      */
18639   CTIMER_CTRL1_TMRA1FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
18640                                                      to CMPR0A1, stop.                                                         */
18641   CTIMER_CTRL1_TMRA1FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
18642                                                      pulses). Count to CMPR0A1, restart.                                       */
18643   CTIMER_CTRL1_TMRA1FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A1, assert,
18644                                                      count to CMPR1A1, deassert, stop.                                         */
18645   CTIMER_CTRL1_TMRA1FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A1, assert, count
18646                                                      to CMPR1A1, deassert, restart.                                            */
18647   CTIMER_CTRL1_TMRA1FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
18648   CTIMER_CTRL1_TMRA1FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
18649   CTIMER_CTRL1_TMRA1FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
18650   CTIMER_CTRL1_TMRA1FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
18651 } CTIMER_CTRL1_TMRA1FN_Enum;
18652 
18653 /* =============================================  CTIMER CTRL1 TMRA1CLK [1..5]  ============================================== */
18654 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1CLK                                                     */
18655   CTIMER_CTRL1_TMRA1CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
18656   CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
18657   CTIMER_CTRL1_TMRA1CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
18658   CTIMER_CTRL1_TMRA1CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
18659   CTIMER_CTRL1_TMRA1CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
18660   CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
18661   CTIMER_CTRL1_TMRA1CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
18662   CTIMER_CTRL1_TMRA1CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
18663   CTIMER_CTRL1_TMRA1CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
18664   CTIMER_CTRL1_TMRA1CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
18665   CTIMER_CTRL1_TMRA1CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
18666   CTIMER_CTRL1_TMRA1CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
18667   CTIMER_CTRL1_TMRA1CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
18668   CTIMER_CTRL1_TMRA1CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
18669   CTIMER_CTRL1_TMRA1CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
18670   CTIMER_CTRL1_TMRA1CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
18671                                                      available when MCU is in active mode)                                     */
18672   CTIMER_CTRL1_TMRA1CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
18673   CTIMER_CTRL1_TMRA1CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
18674   CTIMER_CTRL1_TMRA1CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
18675   CTIMER_CTRL1_TMRA1CLK_CTMRB1         = 20,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
18676   CTIMER_CTRL1_TMRA1CLK_CTMRA0         = 21,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
18677   CTIMER_CTRL1_TMRA1CLK_CTMRB0         = 22,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
18678   CTIMER_CTRL1_TMRA1CLK_CTMRA2         = 23,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
18679   CTIMER_CTRL1_TMRA1CLK_CTMRB2         = 24,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
18680   CTIMER_CTRL1_TMRA1CLK_CTMRB3         = 25,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
18681   CTIMER_CTRL1_TMRA1CLK_CTMRB4         = 26,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
18682   CTIMER_CTRL1_TMRA1CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
18683   CTIMER_CTRL1_TMRA1CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
18684   CTIMER_CTRL1_TMRA1CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
18685   CTIMER_CTRL1_TMRA1CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
18686   CTIMER_CTRL1_TMRA1CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
18687 } CTIMER_CTRL1_TMRA1CLK_Enum;
18688 
18689 /* ==============================================  CTIMER CTRL1 TMRA1EN [0..0]  ============================================== */
18690 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1EN                                                      */
18691   CTIMER_CTRL1_TMRA1EN_DIS             = 0,     /*!< DIS : Counter/Timer A1 Disable.                                           */
18692   CTIMER_CTRL1_TMRA1EN_EN              = 1,     /*!< EN : Counter/Timer A1 Enable.                                             */
18693 } CTIMER_CTRL1_TMRA1EN_Enum;
18694 
18695 /* =======================================================  CMPRAUXA1  ======================================================= */
18696 /* =======================================================  CMPRAUXB1  ======================================================= */
18697 /* =========================================================  AUX1  ========================================================== */
18698 /* ============================================  CTIMER AUX1 TMRB1EN23 [30..30]  ============================================= */
18699 typedef enum {                                  /*!< CTIMER_AUX1_TMRB1EN23                                                     */
18700   CTIMER_AUX1_TMRB1EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
18701   CTIMER_AUX1_TMRB1EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
18702 } CTIMER_AUX1_TMRB1EN23_Enum;
18703 
18704 /* ============================================  CTIMER AUX1 TMRB1POL23 [29..29]  ============================================ */
18705 typedef enum {                                  /*!< CTIMER_AUX1_TMRB1POL23                                                    */
18706   CTIMER_AUX1_TMRB1POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
18707   CTIMER_AUX1_TMRB1POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
18708 } CTIMER_AUX1_TMRB1POL23_Enum;
18709 
18710 /* ============================================  CTIMER AUX1 TMRB1TINV [28..28]  ============================================= */
18711 typedef enum {                                  /*!< CTIMER_AUX1_TMRB1TINV                                                     */
18712   CTIMER_AUX1_TMRB1TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
18713   CTIMER_AUX1_TMRB1TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
18714 } CTIMER_AUX1_TMRB1TINV_Enum;
18715 
18716 /* ===========================================  CTIMER AUX1 TMRB1NOSYNC [27..27]  ============================================ */
18717 typedef enum {                                  /*!< CTIMER_AUX1_TMRB1NOSYNC                                                   */
18718   CTIMER_AUX1_TMRB1NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
18719   CTIMER_AUX1_TMRB1NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
18720 } CTIMER_AUX1_TMRB1NOSYNC_Enum;
18721 
18722 /* ============================================  CTIMER AUX1 TMRB1TRIG [23..26]  ============================================= */
18723 typedef enum {                                  /*!< CTIMER_AUX1_TMRB1TRIG                                                     */
18724   CTIMER_AUX1_TMRB1TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
18725   CTIMER_AUX1_TMRB1TRIG_A1OUT          = 1,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
18726   CTIMER_AUX1_TMRB1TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
18727   CTIMER_AUX1_TMRB1TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
18728   CTIMER_AUX1_TMRB1TRIG_A6OUT          = 4,     /*!< A6OUT : Trigger source is CTIMERA6 OUT.                                   */
18729   CTIMER_AUX1_TMRB1TRIG_B6OUT          = 5,     /*!< B6OUT : Trigger source is CTIMERB6 OUT.                                   */
18730   CTIMER_AUX1_TMRB1TRIG_A0OUT          = 6,     /*!< A0OUT : Trigger source is CTIMERA0 OUT.                                   */
18731   CTIMER_AUX1_TMRB1TRIG_B0OUT          = 7,     /*!< B0OUT : Trigger source is CTIMERB0 OUT.                                   */
18732   CTIMER_AUX1_TMRB1TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
18733   CTIMER_AUX1_TMRB1TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
18734   CTIMER_AUX1_TMRB1TRIG_A4OUT2         = 10,    /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2.                                 */
18735   CTIMER_AUX1_TMRB1TRIG_B4OUT2         = 11,    /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2.                                 */
18736   CTIMER_AUX1_TMRB1TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
18737   CTIMER_AUX1_TMRB1TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
18738   CTIMER_AUX1_TMRB1TRIG_B5OUT2DUAL     = 14,    /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge.                  */
18739   CTIMER_AUX1_TMRB1TRIG_A5OUT2DUAL     = 15,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
18740 } CTIMER_AUX1_TMRB1TRIG_Enum;
18741 
18742 /* ============================================  CTIMER AUX1 TMRA1EN23 [14..14]  ============================================= */
18743 typedef enum {                                  /*!< CTIMER_AUX1_TMRA1EN23                                                     */
18744   CTIMER_AUX1_TMRA1EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
18745   CTIMER_AUX1_TMRA1EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
18746 } CTIMER_AUX1_TMRA1EN23_Enum;
18747 
18748 /* ============================================  CTIMER AUX1 TMRA1POL23 [13..13]  ============================================ */
18749 typedef enum {                                  /*!< CTIMER_AUX1_TMRA1POL23                                                    */
18750   CTIMER_AUX1_TMRA1POL23_NORMAL        = 0,     /*!< NORMAL : Upper output normal polarity                                     */
18751   CTIMER_AUX1_TMRA1POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
18752 } CTIMER_AUX1_TMRA1POL23_Enum;
18753 
18754 /* ============================================  CTIMER AUX1 TMRA1TINV [12..12]  ============================================= */
18755 typedef enum {                                  /*!< CTIMER_AUX1_TMRA1TINV                                                     */
18756   CTIMER_AUX1_TMRA1TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
18757   CTIMER_AUX1_TMRA1TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
18758 } CTIMER_AUX1_TMRA1TINV_Enum;
18759 
18760 /* ===========================================  CTIMER AUX1 TMRA1NOSYNC [11..11]  ============================================ */
18761 typedef enum {                                  /*!< CTIMER_AUX1_TMRA1NOSYNC                                                   */
18762   CTIMER_AUX1_TMRA1NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
18763   CTIMER_AUX1_TMRA1NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
18764 } CTIMER_AUX1_TMRA1NOSYNC_Enum;
18765 
18766 /* =============================================  CTIMER AUX1 TMRA1TRIG [7..10]  ============================================= */
18767 typedef enum {                                  /*!< CTIMER_AUX1_TMRA1TRIG                                                     */
18768   CTIMER_AUX1_TMRA1TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
18769   CTIMER_AUX1_TMRA1TRIG_B1OUT          = 1,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
18770   CTIMER_AUX1_TMRA1TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
18771   CTIMER_AUX1_TMRA1TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
18772   CTIMER_AUX1_TMRA1TRIG_A0OUT          = 4,     /*!< A0OUT : Trigger source is CTIMERA0 OUT.                                   */
18773   CTIMER_AUX1_TMRA1TRIG_B0OUT          = 5,     /*!< B0OUT : Trigger source is CTIMERB0 OUT.                                   */
18774   CTIMER_AUX1_TMRA1TRIG_A5OUT          = 6,     /*!< A5OUT : Trigger source is CTIMERA5 OUT.                                   */
18775   CTIMER_AUX1_TMRA1TRIG_B5OUT          = 7,     /*!< B5OUT : Trigger source is CTIMERB5 OUT.                                   */
18776   CTIMER_AUX1_TMRA1TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
18777   CTIMER_AUX1_TMRA1TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
18778   CTIMER_AUX1_TMRA1TRIG_A4OUT2         = 10,    /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2.                                 */
18779   CTIMER_AUX1_TMRA1TRIG_B4OUT2         = 11,    /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2.                                 */
18780   CTIMER_AUX1_TMRA1TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
18781   CTIMER_AUX1_TMRA1TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
18782   CTIMER_AUX1_TMRA1TRIG_B5OUT2DUAL     = 14,    /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge.                  */
18783   CTIMER_AUX1_TMRA1TRIG_A5OUT2DUAL     = 15,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
18784 } CTIMER_AUX1_TMRA1TRIG_Enum;
18785 
18786 /* =========================================================  TMR2  ========================================================== */
18787 /* ========================================================  CMPRA2  ========================================================= */
18788 /* ========================================================  CMPRB2  ========================================================= */
18789 /* =========================================================  CTRL2  ========================================================= */
18790 /* =============================================  CTIMER CTRL2 CTLINK2 [31..31]  ============================================= */
18791 typedef enum {                                  /*!< CTIMER_CTRL2_CTLINK2                                                      */
18792   CTIMER_CTRL2_CTLINK2_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A2/B2 timers as two independent 16-bit
18793                                                      timers (default).                                                         */
18794   CTIMER_CTRL2_CTLINK2_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A2/B2 timers into a single 32-bit timer.               */
18795 } CTIMER_CTRL2_CTLINK2_Enum;
18796 
18797 /* ============================================  CTIMER CTRL2 TMRB2POL [28..28]  ============================================= */
18798 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2POL                                                     */
18799   CTIMER_CTRL2_TMRB2POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB2 pin is the same as the
18800                                                      timer output.                                                             */
18801   CTIMER_CTRL2_TMRB2POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB2 pin is the inverse of
18802                                                      the timer output.                                                         */
18803 } CTIMER_CTRL2_TMRB2POL_Enum;
18804 
18805 /* ============================================  CTIMER CTRL2 TMRB2CLR [27..27]  ============================================= */
18806 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2CLR                                                     */
18807   CTIMER_CTRL2_TMRB2CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B2 to run                                       */
18808   CTIMER_CTRL2_TMRB2CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B2 at 0x0000.                                 */
18809 } CTIMER_CTRL2_TMRB2CLR_Enum;
18810 
18811 /* ============================================  CTIMER CTRL2 TMRB2IE1 [26..26]  ============================================= */
18812 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2IE1                                                     */
18813   CTIMER_CTRL2_TMRB2IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B2 from generating an interrupt
18814                                                      based on COMPR1.                                                          */
18815   CTIMER_CTRL2_TMRB2IE1_EN             = 1,     /*!< EN : Enable counter/timer B2 to generate an interrupt based
18816                                                      on COMPR1.                                                                */
18817 } CTIMER_CTRL2_TMRB2IE1_Enum;
18818 
18819 /* ============================================  CTIMER CTRL2 TMRB2IE0 [25..25]  ============================================= */
18820 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2IE0                                                     */
18821   CTIMER_CTRL2_TMRB2IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B2 from generating an interrupt
18822                                                      based on COMPR0.                                                          */
18823   CTIMER_CTRL2_TMRB2IE0_EN             = 1,     /*!< EN : Enable counter/timer B2 to generate an interrupt based
18824                                                      on COMPR0                                                                 */
18825 } CTIMER_CTRL2_TMRB2IE0_Enum;
18826 
18827 /* =============================================  CTIMER CTRL2 TMRB2FN [22..24]  ============================================= */
18828 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2FN                                                      */
18829   CTIMER_CTRL2_TMRB2FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
18830                                                      to CMPR0B2, stop.                                                         */
18831   CTIMER_CTRL2_TMRB2FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
18832                                                      pulses). Count to CMPR0B2, restart.                                       */
18833   CTIMER_CTRL2_TMRB2FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B2, assert,
18834                                                      count to CMPR1B2, deassert, stop.                                         */
18835   CTIMER_CTRL2_TMRB2FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B2, assert, count
18836                                                      to CMPR1B2, deassert, restart.                                            */
18837   CTIMER_CTRL2_TMRB2FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
18838   CTIMER_CTRL2_TMRB2FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
18839   CTIMER_CTRL2_TMRB2FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
18840   CTIMER_CTRL2_TMRB2FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
18841 } CTIMER_CTRL2_TMRB2FN_Enum;
18842 
18843 /* ============================================  CTIMER CTRL2 TMRB2CLK [17..21]  ============================================= */
18844 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2CLK                                                     */
18845   CTIMER_CTRL2_TMRB2CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
18846   CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
18847   CTIMER_CTRL2_TMRB2CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
18848   CTIMER_CTRL2_TMRB2CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
18849   CTIMER_CTRL2_TMRB2CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
18850   CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
18851   CTIMER_CTRL2_TMRB2CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
18852   CTIMER_CTRL2_TMRB2CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
18853   CTIMER_CTRL2_TMRB2CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
18854   CTIMER_CTRL2_TMRB2CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
18855   CTIMER_CTRL2_TMRB2CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
18856   CTIMER_CTRL2_TMRB2CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
18857   CTIMER_CTRL2_TMRB2CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
18858   CTIMER_CTRL2_TMRB2CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
18859   CTIMER_CTRL2_TMRB2CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
18860   CTIMER_CTRL2_TMRB2CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
18861                                                      available when MCU is in active mode)                                     */
18862   CTIMER_CTRL2_TMRB2CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
18863   CTIMER_CTRL2_TMRB2CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
18864   CTIMER_CTRL2_TMRB2CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
18865   CTIMER_CTRL2_TMRB2CLK_CTMRA2         = 20,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
18866   CTIMER_CTRL2_TMRB2CLK_CTMRB3         = 21,    /*!< CTMRB3 : Clock source is CTIMERA3 OUT.                                    */
18867   CTIMER_CTRL2_TMRB2CLK_CTMRA3         = 22,    /*!< CTMRA3 : Clock source is CTIMERB3 OUT.                                    */
18868   CTIMER_CTRL2_TMRB2CLK_CTMRA4         = 23,    /*!< CTMRA4 : Clock source is CTIMERA4 OUT.                                    */
18869   CTIMER_CTRL2_TMRB2CLK_CTMRB4         = 24,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
18870   CTIMER_CTRL2_TMRB2CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
18871   CTIMER_CTRL2_TMRB2CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
18872   CTIMER_CTRL2_TMRB2CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
18873   CTIMER_CTRL2_TMRB2CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
18874   CTIMER_CTRL2_TMRB2CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
18875   CTIMER_CTRL2_TMRB2CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
18876   CTIMER_CTRL2_TMRB2CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
18877 } CTIMER_CTRL2_TMRB2CLK_Enum;
18878 
18879 /* =============================================  CTIMER CTRL2 TMRB2EN [16..16]  ============================================= */
18880 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2EN                                                      */
18881   CTIMER_CTRL2_TMRB2EN_DIS             = 0,     /*!< DIS : Counter/Timer B2 Disable.                                           */
18882   CTIMER_CTRL2_TMRB2EN_EN              = 1,     /*!< EN : Counter/Timer B2 Enable.                                             */
18883 } CTIMER_CTRL2_TMRB2EN_Enum;
18884 
18885 /* ============================================  CTIMER CTRL2 TMRA2POL [12..12]  ============================================= */
18886 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2POL                                                     */
18887   CTIMER_CTRL2_TMRA2POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA2 pin is the same as the
18888                                                      timer output.                                                             */
18889   CTIMER_CTRL2_TMRA2POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA2 pin is the inverse of
18890                                                      the timer output.                                                         */
18891 } CTIMER_CTRL2_TMRA2POL_Enum;
18892 
18893 /* ============================================  CTIMER CTRL2 TMRA2CLR [11..11]  ============================================= */
18894 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2CLR                                                     */
18895   CTIMER_CTRL2_TMRA2CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A2 to run                                       */
18896   CTIMER_CTRL2_TMRA2CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A2 at 0x0000.                                 */
18897 } CTIMER_CTRL2_TMRA2CLR_Enum;
18898 
18899 /* ============================================  CTIMER CTRL2 TMRA2IE1 [10..10]  ============================================= */
18900 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2IE1                                                     */
18901   CTIMER_CTRL2_TMRA2IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A2 from generating an interrupt
18902                                                      based on COMPR1.                                                          */
18903   CTIMER_CTRL2_TMRA2IE1_EN             = 1,     /*!< EN : Enable counter/timer A2 to generate an interrupt based
18904                                                      on COMPR1.                                                                */
18905 } CTIMER_CTRL2_TMRA2IE1_Enum;
18906 
18907 /* =============================================  CTIMER CTRL2 TMRA2IE0 [9..9]  ============================================== */
18908 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2IE0                                                     */
18909   CTIMER_CTRL2_TMRA2IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A2 from generating an interrupt
18910                                                      based on COMPR0.                                                          */
18911   CTIMER_CTRL2_TMRA2IE0_EN             = 1,     /*!< EN : Enable counter/timer A2 to generate an interrupt based
18912                                                      on COMPR0.                                                                */
18913 } CTIMER_CTRL2_TMRA2IE0_Enum;
18914 
18915 /* ==============================================  CTIMER CTRL2 TMRA2FN [6..8]  ============================================== */
18916 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2FN                                                      */
18917   CTIMER_CTRL2_TMRA2FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
18918                                                      to CMPR0A2, stop.                                                         */
18919   CTIMER_CTRL2_TMRA2FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
18920                                                      pulses). Count to CMPR0A2, restart.                                       */
18921   CTIMER_CTRL2_TMRA2FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A2, assert,
18922                                                      count to CMPR1A2, deassert, stop.                                         */
18923   CTIMER_CTRL2_TMRA2FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A2, assert, count
18924                                                      to CMPR1A2, deassert, restart.                                            */
18925   CTIMER_CTRL2_TMRA2FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
18926   CTIMER_CTRL2_TMRA2FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
18927   CTIMER_CTRL2_TMRA2FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
18928   CTIMER_CTRL2_TMRA2FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
18929 } CTIMER_CTRL2_TMRA2FN_Enum;
18930 
18931 /* =============================================  CTIMER CTRL2 TMRA2CLK [1..5]  ============================================== */
18932 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2CLK                                                     */
18933   CTIMER_CTRL2_TMRA2CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
18934   CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
18935   CTIMER_CTRL2_TMRA2CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
18936   CTIMER_CTRL2_TMRA2CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
18937   CTIMER_CTRL2_TMRA2CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
18938   CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
18939   CTIMER_CTRL2_TMRA2CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
18940   CTIMER_CTRL2_TMRA2CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
18941   CTIMER_CTRL2_TMRA2CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
18942   CTIMER_CTRL2_TMRA2CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
18943   CTIMER_CTRL2_TMRA2CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
18944   CTIMER_CTRL2_TMRA2CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
18945   CTIMER_CTRL2_TMRA2CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
18946   CTIMER_CTRL2_TMRA2CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
18947   CTIMER_CTRL2_TMRA2CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
18948   CTIMER_CTRL2_TMRA2CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
18949                                                      available when MCU is in active mode)                                     */
18950   CTIMER_CTRL2_TMRA2CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
18951   CTIMER_CTRL2_TMRA2CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
18952   CTIMER_CTRL2_TMRA2CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
18953   CTIMER_CTRL2_TMRA2CLK_CTMRB2         = 20,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
18954   CTIMER_CTRL2_TMRA2CLK_CTMRB3         = 21,    /*!< CTMRB3 : Clock source is CTIMERA3 OUT.                                    */
18955   CTIMER_CTRL2_TMRA2CLK_CTMRA3         = 22,    /*!< CTMRA3 : Clock source is CTIMERB3 OUT.                                    */
18956   CTIMER_CTRL2_TMRA2CLK_CTMRA4         = 23,    /*!< CTMRA4 : Clock source is CTIMERA4 OUT.                                    */
18957   CTIMER_CTRL2_TMRA2CLK_CTMRB4         = 24,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
18958   CTIMER_CTRL2_TMRA2CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
18959   CTIMER_CTRL2_TMRA2CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
18960   CTIMER_CTRL2_TMRA2CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
18961   CTIMER_CTRL2_TMRA2CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
18962   CTIMER_CTRL2_TMRA2CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
18963   CTIMER_CTRL2_TMRA2CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
18964   CTIMER_CTRL2_TMRA2CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
18965 } CTIMER_CTRL2_TMRA2CLK_Enum;
18966 
18967 /* ==============================================  CTIMER CTRL2 TMRA2EN [0..0]  ============================================== */
18968 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2EN                                                      */
18969   CTIMER_CTRL2_TMRA2EN_DIS             = 0,     /*!< DIS : Counter/Timer A2 Disable.                                           */
18970   CTIMER_CTRL2_TMRA2EN_EN              = 1,     /*!< EN : Counter/Timer A2 Enable.                                             */
18971 } CTIMER_CTRL2_TMRA2EN_Enum;
18972 
18973 /* =======================================================  CMPRAUXA2  ======================================================= */
18974 /* =======================================================  CMPRAUXB2  ======================================================= */
18975 /* =========================================================  AUX2  ========================================================== */
18976 /* ============================================  CTIMER AUX2 TMRB2EN23 [30..30]  ============================================= */
18977 typedef enum {                                  /*!< CTIMER_AUX2_TMRB2EN23                                                     */
18978   CTIMER_AUX2_TMRB2EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
18979   CTIMER_AUX2_TMRB2EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
18980 } CTIMER_AUX2_TMRB2EN23_Enum;
18981 
18982 /* ============================================  CTIMER AUX2 TMRB2POL23 [29..29]  ============================================ */
18983 typedef enum {                                  /*!< CTIMER_AUX2_TMRB2POL23                                                    */
18984   CTIMER_AUX2_TMRB2POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
18985   CTIMER_AUX2_TMRB2POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
18986 } CTIMER_AUX2_TMRB2POL23_Enum;
18987 
18988 /* ============================================  CTIMER AUX2 TMRB2TINV [28..28]  ============================================= */
18989 typedef enum {                                  /*!< CTIMER_AUX2_TMRB2TINV                                                     */
18990   CTIMER_AUX2_TMRB2TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
18991   CTIMER_AUX2_TMRB2TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
18992 } CTIMER_AUX2_TMRB2TINV_Enum;
18993 
18994 /* ===========================================  CTIMER AUX2 TMRB2NOSYNC [27..27]  ============================================ */
18995 typedef enum {                                  /*!< CTIMER_AUX2_TMRB2NOSYNC                                                   */
18996   CTIMER_AUX2_TMRB2NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
18997   CTIMER_AUX2_TMRB2NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
18998 } CTIMER_AUX2_TMRB2NOSYNC_Enum;
18999 
19000 /* ============================================  CTIMER AUX2 TMRB2TRIG [23..26]  ============================================= */
19001 typedef enum {                                  /*!< CTIMER_AUX2_TMRB2TRIG                                                     */
19002   CTIMER_AUX2_TMRB2TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
19003   CTIMER_AUX2_TMRB2TRIG_A2OUT          = 1,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
19004   CTIMER_AUX2_TMRB2TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
19005   CTIMER_AUX2_TMRB2TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
19006   CTIMER_AUX2_TMRB2TRIG_A1OUT          = 4,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
19007   CTIMER_AUX2_TMRB2TRIG_B1OUT          = 5,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
19008   CTIMER_AUX2_TMRB2TRIG_A4OUT          = 6,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
19009   CTIMER_AUX2_TMRB2TRIG_B4OUT          = 7,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
19010   CTIMER_AUX2_TMRB2TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
19011   CTIMER_AUX2_TMRB2TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
19012   CTIMER_AUX2_TMRB2TRIG_A5OUT2         = 10,    /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2.                                 */
19013   CTIMER_AUX2_TMRB2TRIG_B5OUT2         = 11,    /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2.                                 */
19014   CTIMER_AUX2_TMRB2TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
19015   CTIMER_AUX2_TMRB2TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
19016   CTIMER_AUX2_TMRB2TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
19017   CTIMER_AUX2_TMRB2TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
19018 } CTIMER_AUX2_TMRB2TRIG_Enum;
19019 
19020 /* ============================================  CTIMER AUX2 TMRA2EN23 [14..14]  ============================================= */
19021 typedef enum {                                  /*!< CTIMER_AUX2_TMRA2EN23                                                     */
19022   CTIMER_AUX2_TMRA2EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
19023   CTIMER_AUX2_TMRA2EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
19024 } CTIMER_AUX2_TMRA2EN23_Enum;
19025 
19026 /* ============================================  CTIMER AUX2 TMRA2POL23 [13..13]  ============================================ */
19027 typedef enum {                                  /*!< CTIMER_AUX2_TMRA2POL23                                                    */
19028   CTIMER_AUX2_TMRA2POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
19029   CTIMER_AUX2_TMRA2POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
19030 } CTIMER_AUX2_TMRA2POL23_Enum;
19031 
19032 /* ============================================  CTIMER AUX2 TMRA2TINV [12..12]  ============================================= */
19033 typedef enum {                                  /*!< CTIMER_AUX2_TMRA2TINV                                                     */
19034   CTIMER_AUX2_TMRA2TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
19035   CTIMER_AUX2_TMRA2TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
19036 } CTIMER_AUX2_TMRA2TINV_Enum;
19037 
19038 /* ===========================================  CTIMER AUX2 TMRA2NOSYNC [11..11]  ============================================ */
19039 typedef enum {                                  /*!< CTIMER_AUX2_TMRA2NOSYNC                                                   */
19040   CTIMER_AUX2_TMRA2NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
19041   CTIMER_AUX2_TMRA2NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
19042 } CTIMER_AUX2_TMRA2NOSYNC_Enum;
19043 
19044 /* =============================================  CTIMER AUX2 TMRA2TRIG [7..10]  ============================================= */
19045 typedef enum {                                  /*!< CTIMER_AUX2_TMRA2TRIG                                                     */
19046   CTIMER_AUX2_TMRA2TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
19047   CTIMER_AUX2_TMRA2TRIG_B2OUT          = 1,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
19048   CTIMER_AUX2_TMRA2TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
19049   CTIMER_AUX2_TMRA2TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
19050   CTIMER_AUX2_TMRA2TRIG_A0OUT          = 4,     /*!< A0OUT : Trigger source is CTIMERA0 OUT.                                   */
19051   CTIMER_AUX2_TMRA2TRIG_B0OUT          = 5,     /*!< B0OUT : Trigger source is CTIMERB0 OUT.                                   */
19052   CTIMER_AUX2_TMRA2TRIG_A4OUT          = 6,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
19053   CTIMER_AUX2_TMRA2TRIG_B4OUT          = 7,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
19054   CTIMER_AUX2_TMRA2TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
19055   CTIMER_AUX2_TMRA2TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
19056   CTIMER_AUX2_TMRA2TRIG_A5OUT2         = 10,    /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2.                                 */
19057   CTIMER_AUX2_TMRA2TRIG_B5OUT2         = 11,    /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2.                                 */
19058   CTIMER_AUX2_TMRA2TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
19059   CTIMER_AUX2_TMRA2TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
19060   CTIMER_AUX2_TMRA2TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
19061   CTIMER_AUX2_TMRA2TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
19062 } CTIMER_AUX2_TMRA2TRIG_Enum;
19063 
19064 /* =========================================================  TMR3  ========================================================== */
19065 /* ========================================================  CMPRA3  ========================================================= */
19066 /* ========================================================  CMPRB3  ========================================================= */
19067 /* =========================================================  CTRL3  ========================================================= */
19068 /* =============================================  CTIMER CTRL3 CTLINK3 [31..31]  ============================================= */
19069 typedef enum {                                  /*!< CTIMER_CTRL3_CTLINK3                                                      */
19070   CTIMER_CTRL3_CTLINK3_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A3/B3 timers as two independent 16-bit
19071                                                      timers (default).                                                         */
19072   CTIMER_CTRL3_CTLINK3_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A3/B3 timers into a single 32-bit timer.               */
19073 } CTIMER_CTRL3_CTLINK3_Enum;
19074 
19075 /* ============================================  CTIMER CTRL3 TMRB3POL [28..28]  ============================================= */
19076 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3POL                                                     */
19077   CTIMER_CTRL3_TMRB3POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB3 pin is the same as the
19078                                                      timer output.                                                             */
19079   CTIMER_CTRL3_TMRB3POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB3 pin is the inverse of
19080                                                      the timer output.                                                         */
19081 } CTIMER_CTRL3_TMRB3POL_Enum;
19082 
19083 /* ============================================  CTIMER CTRL3 TMRB3CLR [27..27]  ============================================= */
19084 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3CLR                                                     */
19085   CTIMER_CTRL3_TMRB3CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B3 to run                                       */
19086   CTIMER_CTRL3_TMRB3CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B3 at 0x0000.                                 */
19087 } CTIMER_CTRL3_TMRB3CLR_Enum;
19088 
19089 /* ============================================  CTIMER CTRL3 TMRB3IE1 [26..26]  ============================================= */
19090 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3IE1                                                     */
19091   CTIMER_CTRL3_TMRB3IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B3 from generating an interrupt
19092                                                      based on COMPR1.                                                          */
19093   CTIMER_CTRL3_TMRB3IE1_EN             = 1,     /*!< EN : Enable counter/timer B3 to generate an interrupt based
19094                                                      on COMPR1.                                                                */
19095 } CTIMER_CTRL3_TMRB3IE1_Enum;
19096 
19097 /* ============================================  CTIMER CTRL3 TMRB3IE0 [25..25]  ============================================= */
19098 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3IE0                                                     */
19099   CTIMER_CTRL3_TMRB3IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B3 from generating an interrupt
19100                                                      based on COMPR0.                                                          */
19101   CTIMER_CTRL3_TMRB3IE0_EN             = 1,     /*!< EN : Enable counter/timer B3 to generate an interrupt based
19102                                                      on COMPR0                                                                 */
19103 } CTIMER_CTRL3_TMRB3IE0_Enum;
19104 
19105 /* =============================================  CTIMER CTRL3 TMRB3FN [22..24]  ============================================= */
19106 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3FN                                                      */
19107   CTIMER_CTRL3_TMRB3FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
19108                                                      to CMPR0B3, stop.                                                         */
19109   CTIMER_CTRL3_TMRB3FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
19110                                                      pulses). Count to CMPR0B3, restart.                                       */
19111   CTIMER_CTRL3_TMRB3FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B3, assert,
19112                                                      count to CMPR1B3, deassert, stop.                                         */
19113   CTIMER_CTRL3_TMRB3FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B3, assert, count
19114                                                      to CMPR1B3, deassert, restart.                                            */
19115   CTIMER_CTRL3_TMRB3FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
19116   CTIMER_CTRL3_TMRB3FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
19117   CTIMER_CTRL3_TMRB3FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
19118   CTIMER_CTRL3_TMRB3FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
19119 } CTIMER_CTRL3_TMRB3FN_Enum;
19120 
19121 /* ============================================  CTIMER CTRL3 TMRB3CLK [17..21]  ============================================= */
19122 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3CLK                                                     */
19123   CTIMER_CTRL3_TMRB3CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
19124   CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
19125   CTIMER_CTRL3_TMRB3CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
19126   CTIMER_CTRL3_TMRB3CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
19127   CTIMER_CTRL3_TMRB3CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
19128   CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
19129   CTIMER_CTRL3_TMRB3CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
19130   CTIMER_CTRL3_TMRB3CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
19131   CTIMER_CTRL3_TMRB3CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
19132   CTIMER_CTRL3_TMRB3CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
19133   CTIMER_CTRL3_TMRB3CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
19134   CTIMER_CTRL3_TMRB3CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
19135   CTIMER_CTRL3_TMRB3CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
19136   CTIMER_CTRL3_TMRB3CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
19137   CTIMER_CTRL3_TMRB3CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
19138   CTIMER_CTRL3_TMRB3CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
19139                                                      available when MCU is in active mode)                                     */
19140   CTIMER_CTRL3_TMRB3CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
19141   CTIMER_CTRL3_TMRB3CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
19142   CTIMER_CTRL3_TMRB3CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
19143   CTIMER_CTRL3_TMRB3CLK_CTMRA3         = 20,    /*!< CTMRA3 : Clock source is CTIMERA3 OUT.                                    */
19144   CTIMER_CTRL3_TMRB3CLK_CTMRA2         = 21,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
19145   CTIMER_CTRL3_TMRB3CLK_CTMRB2         = 22,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
19146   CTIMER_CTRL3_TMRB3CLK_CTMRA4         = 23,    /*!< CTMRA4 : Clock source is CTIMERA4 OUT.                                    */
19147   CTIMER_CTRL3_TMRB3CLK_CTMRB4         = 24,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
19148   CTIMER_CTRL3_TMRB3CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
19149   CTIMER_CTRL3_TMRB3CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
19150   CTIMER_CTRL3_TMRB3CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
19151   CTIMER_CTRL3_TMRB3CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
19152   CTIMER_CTRL3_TMRB3CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
19153   CTIMER_CTRL3_TMRB3CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
19154   CTIMER_CTRL3_TMRB3CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
19155 } CTIMER_CTRL3_TMRB3CLK_Enum;
19156 
19157 /* =============================================  CTIMER CTRL3 TMRB3EN [16..16]  ============================================= */
19158 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3EN                                                      */
19159   CTIMER_CTRL3_TMRB3EN_DIS             = 0,     /*!< DIS : Counter/Timer B3 Disable.                                           */
19160   CTIMER_CTRL3_TMRB3EN_EN              = 1,     /*!< EN : Counter/Timer B3 Enable.                                             */
19161 } CTIMER_CTRL3_TMRB3EN_Enum;
19162 
19163 /* ============================================  CTIMER CTRL3 TMRA3POL [12..12]  ============================================= */
19164 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3POL                                                     */
19165   CTIMER_CTRL3_TMRA3POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA3 pin is the same as the
19166                                                      timer output.                                                             */
19167   CTIMER_CTRL3_TMRA3POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA3 pin is the inverse of
19168                                                      the timer output.                                                         */
19169 } CTIMER_CTRL3_TMRA3POL_Enum;
19170 
19171 /* ============================================  CTIMER CTRL3 TMRA3CLR [11..11]  ============================================= */
19172 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3CLR                                                     */
19173   CTIMER_CTRL3_TMRA3CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A3 to run                                       */
19174   CTIMER_CTRL3_TMRA3CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A3 at 0x0000.                                 */
19175 } CTIMER_CTRL3_TMRA3CLR_Enum;
19176 
19177 /* ============================================  CTIMER CTRL3 TMRA3IE1 [10..10]  ============================================= */
19178 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3IE1                                                     */
19179   CTIMER_CTRL3_TMRA3IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A3 from generating an interrupt
19180                                                      based on COMPR1.                                                          */
19181   CTIMER_CTRL3_TMRA3IE1_EN             = 1,     /*!< EN : Enable counter/timer A3 to generate an interrupt based
19182                                                      on COMPR1.                                                                */
19183 } CTIMER_CTRL3_TMRA3IE1_Enum;
19184 
19185 /* =============================================  CTIMER CTRL3 TMRA3IE0 [9..9]  ============================================== */
19186 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3IE0                                                     */
19187   CTIMER_CTRL3_TMRA3IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A3 from generating an interrupt
19188                                                      based on COMPR0.                                                          */
19189   CTIMER_CTRL3_TMRA3IE0_EN             = 1,     /*!< EN : Enable counter/timer A3 to generate an interrupt based
19190                                                      on COMPR0.                                                                */
19191 } CTIMER_CTRL3_TMRA3IE0_Enum;
19192 
19193 /* ==============================================  CTIMER CTRL3 TMRA3FN [6..8]  ============================================== */
19194 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3FN                                                      */
19195   CTIMER_CTRL3_TMRA3FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
19196                                                      to CMPR0A3, stop.                                                         */
19197   CTIMER_CTRL3_TMRA3FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
19198                                                      pulses). Count to CMPR0A3, restart.                                       */
19199   CTIMER_CTRL3_TMRA3FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A3, assert,
19200                                                      count to CMPR1A3, deassert, stop.                                         */
19201   CTIMER_CTRL3_TMRA3FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A3, assert, count
19202                                                      to CMPR1A3, deassert, restart.                                            */
19203   CTIMER_CTRL3_TMRA3FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
19204   CTIMER_CTRL3_TMRA3FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
19205   CTIMER_CTRL3_TMRA3FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
19206   CTIMER_CTRL3_TMRA3FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
19207 } CTIMER_CTRL3_TMRA3FN_Enum;
19208 
19209 /* =============================================  CTIMER CTRL3 TMRA3CLK [1..5]  ============================================== */
19210 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3CLK                                                     */
19211   CTIMER_CTRL3_TMRA3CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
19212   CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
19213   CTIMER_CTRL3_TMRA3CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
19214   CTIMER_CTRL3_TMRA3CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
19215   CTIMER_CTRL3_TMRA3CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
19216   CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
19217   CTIMER_CTRL3_TMRA3CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
19218   CTIMER_CTRL3_TMRA3CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
19219   CTIMER_CTRL3_TMRA3CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
19220   CTIMER_CTRL3_TMRA3CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
19221   CTIMER_CTRL3_TMRA3CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
19222   CTIMER_CTRL3_TMRA3CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
19223   CTIMER_CTRL3_TMRA3CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
19224   CTIMER_CTRL3_TMRA3CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
19225   CTIMER_CTRL3_TMRA3CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
19226   CTIMER_CTRL3_TMRA3CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
19227                                                      available when MCU is in active mode)                                     */
19228   CTIMER_CTRL3_TMRA3CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
19229   CTIMER_CTRL3_TMRA3CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
19230   CTIMER_CTRL3_TMRA3CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
19231   CTIMER_CTRL3_TMRA3CLK_CTMRB3         = 20,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
19232   CTIMER_CTRL3_TMRA3CLK_CTMRA2         = 21,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
19233   CTIMER_CTRL3_TMRA3CLK_CTMRB2         = 22,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
19234   CTIMER_CTRL3_TMRA3CLK_CTMRA4         = 23,    /*!< CTMRA4 : Clock source is CTIMERA4 OUT.                                    */
19235   CTIMER_CTRL3_TMRA3CLK_CTMRB4         = 24,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
19236   CTIMER_CTRL3_TMRA3CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
19237   CTIMER_CTRL3_TMRA3CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
19238   CTIMER_CTRL3_TMRA3CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
19239   CTIMER_CTRL3_TMRA3CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
19240   CTIMER_CTRL3_TMRA3CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
19241   CTIMER_CTRL3_TMRA3CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
19242   CTIMER_CTRL3_TMRA3CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
19243 } CTIMER_CTRL3_TMRA3CLK_Enum;
19244 
19245 /* ==============================================  CTIMER CTRL3 TMRA3EN [0..0]  ============================================== */
19246 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3EN                                                      */
19247   CTIMER_CTRL3_TMRA3EN_DIS             = 0,     /*!< DIS : Counter/Timer A3 Disable.                                           */
19248   CTIMER_CTRL3_TMRA3EN_EN              = 1,     /*!< EN : Counter/Timer A3 Enable.                                             */
19249 } CTIMER_CTRL3_TMRA3EN_Enum;
19250 
19251 /* =======================================================  CMPRAUXA3  ======================================================= */
19252 /* =======================================================  CMPRAUXB3  ======================================================= */
19253 /* =========================================================  AUX3  ========================================================== */
19254 /* ============================================  CTIMER AUX3 TMRB3EN23 [30..30]  ============================================= */
19255 typedef enum {                                  /*!< CTIMER_AUX3_TMRB3EN23                                                     */
19256   CTIMER_AUX3_TMRB3EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
19257   CTIMER_AUX3_TMRB3EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
19258 } CTIMER_AUX3_TMRB3EN23_Enum;
19259 
19260 /* ============================================  CTIMER AUX3 TMRB3POL23 [29..29]  ============================================ */
19261 typedef enum {                                  /*!< CTIMER_AUX3_TMRB3POL23                                                    */
19262   CTIMER_AUX3_TMRB3POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
19263   CTIMER_AUX3_TMRB3POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
19264 } CTIMER_AUX3_TMRB3POL23_Enum;
19265 
19266 /* ============================================  CTIMER AUX3 TMRB3TINV [28..28]  ============================================= */
19267 typedef enum {                                  /*!< CTIMER_AUX3_TMRB3TINV                                                     */
19268   CTIMER_AUX3_TMRB3TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
19269   CTIMER_AUX3_TMRB3TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
19270 } CTIMER_AUX3_TMRB3TINV_Enum;
19271 
19272 /* ===========================================  CTIMER AUX3 TMRB3NOSYNC [27..27]  ============================================ */
19273 typedef enum {                                  /*!< CTIMER_AUX3_TMRB3NOSYNC                                                   */
19274   CTIMER_AUX3_TMRB3NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
19275   CTIMER_AUX3_TMRB3NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
19276 } CTIMER_AUX3_TMRB3NOSYNC_Enum;
19277 
19278 /* ============================================  CTIMER AUX3 TMRB3TRIG [23..26]  ============================================= */
19279 typedef enum {                                  /*!< CTIMER_AUX3_TMRB3TRIG                                                     */
19280   CTIMER_AUX3_TMRB3TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
19281   CTIMER_AUX3_TMRB3TRIG_A3OUT          = 1,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
19282   CTIMER_AUX3_TMRB3TRIG_B2OUT          = 2,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
19283   CTIMER_AUX3_TMRB3TRIG_A2OUT          = 3,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
19284   CTIMER_AUX3_TMRB3TRIG_A4OUT          = 4,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
19285   CTIMER_AUX3_TMRB3TRIG_B4OUT          = 5,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
19286   CTIMER_AUX3_TMRB3TRIG_A6OUT          = 6,     /*!< A6OUT : Trigger source is CTIMERA6 OUT.                                   */
19287   CTIMER_AUX3_TMRB3TRIG_B6OUT          = 7,     /*!< B6OUT : Trigger source is CTIMERB6 OUT.                                   */
19288   CTIMER_AUX3_TMRB3TRIG_B5OUT2         = 8,     /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2.                                 */
19289   CTIMER_AUX3_TMRB3TRIG_A5OUT2         = 9,     /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2.                                 */
19290   CTIMER_AUX3_TMRB3TRIG_A1OUT2         = 10,    /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2.                                 */
19291   CTIMER_AUX3_TMRB3TRIG_B1OUT2         = 11,    /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2.                                 */
19292   CTIMER_AUX3_TMRB3TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
19293   CTIMER_AUX3_TMRB3TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
19294   CTIMER_AUX3_TMRB3TRIG_B2OUT2DUAL     = 14,    /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge.                  */
19295   CTIMER_AUX3_TMRB3TRIG_A2OUT2DUAL     = 15,    /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge.                  */
19296 } CTIMER_AUX3_TMRB3TRIG_Enum;
19297 
19298 /* ============================================  CTIMER AUX3 TMRA3EN23 [14..14]  ============================================= */
19299 typedef enum {                                  /*!< CTIMER_AUX3_TMRA3EN23                                                     */
19300   CTIMER_AUX3_TMRA3EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
19301   CTIMER_AUX3_TMRA3EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
19302 } CTIMER_AUX3_TMRA3EN23_Enum;
19303 
19304 /* ============================================  CTIMER AUX3 TMRA3POL23 [13..13]  ============================================ */
19305 typedef enum {                                  /*!< CTIMER_AUX3_TMRA3POL23                                                    */
19306   CTIMER_AUX3_TMRA3POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
19307   CTIMER_AUX3_TMRA3POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
19308 } CTIMER_AUX3_TMRA3POL23_Enum;
19309 
19310 /* ============================================  CTIMER AUX3 TMRA3TINV [12..12]  ============================================= */
19311 typedef enum {                                  /*!< CTIMER_AUX3_TMRA3TINV                                                     */
19312   CTIMER_AUX3_TMRA3TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
19313   CTIMER_AUX3_TMRA3TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
19314 } CTIMER_AUX3_TMRA3TINV_Enum;
19315 
19316 /* ===========================================  CTIMER AUX3 TMRA3NOSYNC [11..11]  ============================================ */
19317 typedef enum {                                  /*!< CTIMER_AUX3_TMRA3NOSYNC                                                   */
19318   CTIMER_AUX3_TMRA3NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
19319   CTIMER_AUX3_TMRA3NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
19320 } CTIMER_AUX3_TMRA3NOSYNC_Enum;
19321 
19322 /* =============================================  CTIMER AUX3 TMRA3TRIG [7..10]  ============================================= */
19323 typedef enum {                                  /*!< CTIMER_AUX3_TMRA3TRIG                                                     */
19324   CTIMER_AUX3_TMRA3TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
19325   CTIMER_AUX3_TMRA3TRIG_B3OUT          = 1,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
19326   CTIMER_AUX3_TMRA3TRIG_B2OUT          = 2,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
19327   CTIMER_AUX3_TMRA3TRIG_A2OUT          = 3,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
19328   CTIMER_AUX3_TMRA3TRIG_A4OUT          = 4,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
19329   CTIMER_AUX3_TMRA3TRIG_B4OUT          = 5,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
19330   CTIMER_AUX3_TMRA3TRIG_A7OUT          = 6,     /*!< A7OUT : Trigger source is CTIMERA7 OUT.                                   */
19331   CTIMER_AUX3_TMRA3TRIG_B7OUT          = 7,     /*!< B7OUT : Trigger source is CTIMERB7 OUT.                                   */
19332   CTIMER_AUX3_TMRA3TRIG_B5OUT2         = 8,     /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2.                                 */
19333   CTIMER_AUX3_TMRA3TRIG_A5OUT2         = 9,     /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2.                                 */
19334   CTIMER_AUX3_TMRA3TRIG_A1OUT2         = 10,    /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2.                                 */
19335   CTIMER_AUX3_TMRA3TRIG_B1OUT2         = 11,    /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2.                                 */
19336   CTIMER_AUX3_TMRA3TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
19337   CTIMER_AUX3_TMRA3TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
19338   CTIMER_AUX3_TMRA3TRIG_B2OUT2DUAL     = 14,    /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge.                  */
19339   CTIMER_AUX3_TMRA3TRIG_A2OUT2DUAL     = 15,    /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge.                  */
19340 } CTIMER_AUX3_TMRA3TRIG_Enum;
19341 
19342 /* =========================================================  TMR4  ========================================================== */
19343 /* ========================================================  CMPRA4  ========================================================= */
19344 /* ========================================================  CMPRB4  ========================================================= */
19345 /* =========================================================  CTRL4  ========================================================= */
19346 /* =============================================  CTIMER CTRL4 CTLINK4 [31..31]  ============================================= */
19347 typedef enum {                                  /*!< CTIMER_CTRL4_CTLINK4                                                      */
19348   CTIMER_CTRL4_CTLINK4_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A4/B4 timers as two independent 16-bit
19349                                                      timers (default).                                                         */
19350   CTIMER_CTRL4_CTLINK4_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A4/B4 timers into a single 32-bit timer.               */
19351 } CTIMER_CTRL4_CTLINK4_Enum;
19352 
19353 /* ============================================  CTIMER CTRL4 TMRB4POL [28..28]  ============================================= */
19354 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4POL                                                     */
19355   CTIMER_CTRL4_TMRB4POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB4 pin is the same as the
19356                                                      timer output.                                                             */
19357   CTIMER_CTRL4_TMRB4POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB4 pin is the inverse of
19358                                                      the timer output.                                                         */
19359 } CTIMER_CTRL4_TMRB4POL_Enum;
19360 
19361 /* ============================================  CTIMER CTRL4 TMRB4CLR [27..27]  ============================================= */
19362 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4CLR                                                     */
19363   CTIMER_CTRL4_TMRB4CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B4 to run                                       */
19364   CTIMER_CTRL4_TMRB4CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B4 at 0x0000.                                 */
19365 } CTIMER_CTRL4_TMRB4CLR_Enum;
19366 
19367 /* ============================================  CTIMER CTRL4 TMRB4IE1 [26..26]  ============================================= */
19368 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4IE1                                                     */
19369   CTIMER_CTRL4_TMRB4IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B4 from generating an interrupt
19370                                                      based on COMPR1.                                                          */
19371   CTIMER_CTRL4_TMRB4IE1_EN             = 1,     /*!< EN : Enable counter/timer B4 to generate an interrupt based
19372                                                      on COMPR1.                                                                */
19373 } CTIMER_CTRL4_TMRB4IE1_Enum;
19374 
19375 /* ============================================  CTIMER CTRL4 TMRB4IE0 [25..25]  ============================================= */
19376 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4IE0                                                     */
19377   CTIMER_CTRL4_TMRB4IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B4 from generating an interrupt
19378                                                      based on COMPR0.                                                          */
19379   CTIMER_CTRL4_TMRB4IE0_EN             = 1,     /*!< EN : Enable counter/timer B4 to generate an interrupt based
19380                                                      on COMPR0                                                                 */
19381 } CTIMER_CTRL4_TMRB4IE0_Enum;
19382 
19383 /* =============================================  CTIMER CTRL4 TMRB4FN [22..24]  ============================================= */
19384 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4FN                                                      */
19385   CTIMER_CTRL4_TMRB4FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
19386                                                      to CMPR0B4, stop.                                                         */
19387   CTIMER_CTRL4_TMRB4FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
19388                                                      pulses). Count to CMPR0B4, restart.                                       */
19389   CTIMER_CTRL4_TMRB4FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B4, assert,
19390                                                      count to CMPR1B4, deassert, stop.                                         */
19391   CTIMER_CTRL4_TMRB4FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B4, assert, count
19392                                                      to CMPR1B4, deassert, restart.                                            */
19393   CTIMER_CTRL4_TMRB4FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
19394   CTIMER_CTRL4_TMRB4FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
19395   CTIMER_CTRL4_TMRB4FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
19396   CTIMER_CTRL4_TMRB4FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
19397 } CTIMER_CTRL4_TMRB4FN_Enum;
19398 
19399 /* ============================================  CTIMER CTRL4 TMRB4CLK [17..21]  ============================================= */
19400 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4CLK                                                     */
19401   CTIMER_CTRL4_TMRB4CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
19402   CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
19403   CTIMER_CTRL4_TMRB4CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
19404   CTIMER_CTRL4_TMRB4CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
19405   CTIMER_CTRL4_TMRB4CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
19406   CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
19407   CTIMER_CTRL4_TMRB4CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
19408   CTIMER_CTRL4_TMRB4CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
19409   CTIMER_CTRL4_TMRB4CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
19410   CTIMER_CTRL4_TMRB4CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
19411   CTIMER_CTRL4_TMRB4CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
19412   CTIMER_CTRL4_TMRB4CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
19413   CTIMER_CTRL4_TMRB4CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
19414   CTIMER_CTRL4_TMRB4CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
19415   CTIMER_CTRL4_TMRB4CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
19416   CTIMER_CTRL4_TMRB4CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
19417                                                      available when MCU is in active mode)                                     */
19418   CTIMER_CTRL4_TMRB4CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
19419   CTIMER_CTRL4_TMRB4CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
19420   CTIMER_CTRL4_TMRB4CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
19421   CTIMER_CTRL4_TMRB4CLK_CTMRA4         = 20,    /*!< CTMRA4 : Clock source is CTIMERA4 OUT.                                    */
19422   CTIMER_CTRL4_TMRB4CLK_CTMRA1         = 21,    /*!< CTMRA1 : Clock source is CTIMERA1 OUT.                                    */
19423   CTIMER_CTRL4_TMRB4CLK_CTMRB1         = 22,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
19424   CTIMER_CTRL4_TMRB4CLK_CTMRA5         = 23,    /*!< CTMRA5 : Clock source is CTIMERA5 OUT.                                    */
19425   CTIMER_CTRL4_TMRB4CLK_CTMRB5         = 24,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
19426   CTIMER_CTRL4_TMRB4CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
19427   CTIMER_CTRL4_TMRB4CLK_CTMRB2         = 26,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
19428   CTIMER_CTRL4_TMRB4CLK_CTMRB3         = 27,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
19429   CTIMER_CTRL4_TMRB4CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
19430   CTIMER_CTRL4_TMRB4CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
19431   CTIMER_CTRL4_TMRB4CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
19432   CTIMER_CTRL4_TMRB4CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
19433 } CTIMER_CTRL4_TMRB4CLK_Enum;
19434 
19435 /* =============================================  CTIMER CTRL4 TMRB4EN [16..16]  ============================================= */
19436 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4EN                                                      */
19437   CTIMER_CTRL4_TMRB4EN_DIS             = 0,     /*!< DIS : Counter/Timer B4 Disable.                                           */
19438   CTIMER_CTRL4_TMRB4EN_EN              = 1,     /*!< EN : Counter/Timer B4 Enable.                                             */
19439 } CTIMER_CTRL4_TMRB4EN_Enum;
19440 
19441 /* ============================================  CTIMER CTRL4 TMRA4POL [12..12]  ============================================= */
19442 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4POL                                                     */
19443   CTIMER_CTRL4_TMRA4POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA4 pin is the same as the
19444                                                      timer output.                                                             */
19445   CTIMER_CTRL4_TMRA4POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA4 pin is the inverse of
19446                                                      the timer output.                                                         */
19447 } CTIMER_CTRL4_TMRA4POL_Enum;
19448 
19449 /* ============================================  CTIMER CTRL4 TMRA4CLR [11..11]  ============================================= */
19450 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4CLR                                                     */
19451   CTIMER_CTRL4_TMRA4CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A4 to run                                       */
19452   CTIMER_CTRL4_TMRA4CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A4 at 0x0000.                                 */
19453 } CTIMER_CTRL4_TMRA4CLR_Enum;
19454 
19455 /* ============================================  CTIMER CTRL4 TMRA4IE1 [10..10]  ============================================= */
19456 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4IE1                                                     */
19457   CTIMER_CTRL4_TMRA4IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A4 from generating an interrupt
19458                                                      based on COMPR1.                                                          */
19459   CTIMER_CTRL4_TMRA4IE1_EN             = 1,     /*!< EN : Enable counter/timer A4 to generate an interrupt based
19460                                                      on COMPR1.                                                                */
19461 } CTIMER_CTRL4_TMRA4IE1_Enum;
19462 
19463 /* =============================================  CTIMER CTRL4 TMRA4IE0 [9..9]  ============================================== */
19464 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4IE0                                                     */
19465   CTIMER_CTRL4_TMRA4IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A4 from generating an interrupt
19466                                                      based on COMPR0.                                                          */
19467   CTIMER_CTRL4_TMRA4IE0_EN             = 1,     /*!< EN : Enable counter/timer A4 to generate an interrupt based
19468                                                      on COMPR0.                                                                */
19469 } CTIMER_CTRL4_TMRA4IE0_Enum;
19470 
19471 /* ==============================================  CTIMER CTRL4 TMRA4FN [6..8]  ============================================== */
19472 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4FN                                                      */
19473   CTIMER_CTRL4_TMRA4FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
19474                                                      to CMPR0A4, stop.                                                         */
19475   CTIMER_CTRL4_TMRA4FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
19476                                                      pulses). Count to CMPR0A4, restart.                                       */
19477   CTIMER_CTRL4_TMRA4FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A4, assert,
19478                                                      count to CMPR1A4, deassert, stop.                                         */
19479   CTIMER_CTRL4_TMRA4FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A4, assert, count
19480                                                      to CMPR1A4, deassert, restart.                                            */
19481   CTIMER_CTRL4_TMRA4FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
19482   CTIMER_CTRL4_TMRA4FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
19483   CTIMER_CTRL4_TMRA4FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
19484   CTIMER_CTRL4_TMRA4FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
19485 } CTIMER_CTRL4_TMRA4FN_Enum;
19486 
19487 /* =============================================  CTIMER CTRL4 TMRA4CLK [1..5]  ============================================== */
19488 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4CLK                                                     */
19489   CTIMER_CTRL4_TMRA4CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
19490   CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
19491   CTIMER_CTRL4_TMRA4CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
19492   CTIMER_CTRL4_TMRA4CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
19493   CTIMER_CTRL4_TMRA4CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
19494   CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
19495   CTIMER_CTRL4_TMRA4CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
19496   CTIMER_CTRL4_TMRA4CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
19497   CTIMER_CTRL4_TMRA4CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
19498   CTIMER_CTRL4_TMRA4CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
19499   CTIMER_CTRL4_TMRA4CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
19500   CTIMER_CTRL4_TMRA4CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
19501   CTIMER_CTRL4_TMRA4CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
19502   CTIMER_CTRL4_TMRA4CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
19503   CTIMER_CTRL4_TMRA4CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
19504   CTIMER_CTRL4_TMRA4CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4. (note: this clock is only
19505                                                      available when MCU is in active mode)                                     */
19506   CTIMER_CTRL4_TMRA4CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
19507   CTIMER_CTRL4_TMRA4CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
19508   CTIMER_CTRL4_TMRA4CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
19509   CTIMER_CTRL4_TMRA4CLK_CTMRB4         = 20,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
19510   CTIMER_CTRL4_TMRA4CLK_CTMRA1         = 21,    /*!< CTMRA1 : Clock source is CTIMERA1 OUT.                                    */
19511   CTIMER_CTRL4_TMRA4CLK_CTMRB1         = 22,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
19512   CTIMER_CTRL4_TMRA4CLK_CTMRA5         = 23,    /*!< CTMRA5 : Clock source is CTIMERA5 OUT.                                    */
19513   CTIMER_CTRL4_TMRA4CLK_CTMRB5         = 24,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
19514   CTIMER_CTRL4_TMRA4CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
19515   CTIMER_CTRL4_TMRA4CLK_CTMRB2         = 26,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
19516   CTIMER_CTRL4_TMRA4CLK_CTMRB3         = 27,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
19517   CTIMER_CTRL4_TMRA4CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
19518   CTIMER_CTRL4_TMRA4CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
19519   CTIMER_CTRL4_TMRA4CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
19520   CTIMER_CTRL4_TMRA4CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
19521 } CTIMER_CTRL4_TMRA4CLK_Enum;
19522 
19523 /* ==============================================  CTIMER CTRL4 TMRA4EN [0..0]  ============================================== */
19524 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4EN                                                      */
19525   CTIMER_CTRL4_TMRA4EN_DIS             = 0,     /*!< DIS : Counter/Timer A4 Disable.                                           */
19526   CTIMER_CTRL4_TMRA4EN_EN              = 1,     /*!< EN : Counter/Timer A4 Enable.                                             */
19527 } CTIMER_CTRL4_TMRA4EN_Enum;
19528 
19529 /* =======================================================  CMPRAUXA4  ======================================================= */
19530 /* =======================================================  CMPRAUXB4  ======================================================= */
19531 /* =========================================================  AUX4  ========================================================== */
19532 /* ============================================  CTIMER AUX4 TMRB4EN23 [30..30]  ============================================= */
19533 typedef enum {                                  /*!< CTIMER_AUX4_TMRB4EN23                                                     */
19534   CTIMER_AUX4_TMRB4EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
19535   CTIMER_AUX4_TMRB4EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
19536 } CTIMER_AUX4_TMRB4EN23_Enum;
19537 
19538 /* ============================================  CTIMER AUX4 TMRB4POL23 [29..29]  ============================================ */
19539 typedef enum {                                  /*!< CTIMER_AUX4_TMRB4POL23                                                    */
19540   CTIMER_AUX4_TMRB4POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
19541   CTIMER_AUX4_TMRB4POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
19542 } CTIMER_AUX4_TMRB4POL23_Enum;
19543 
19544 /* ============================================  CTIMER AUX4 TMRB4TINV [28..28]  ============================================= */
19545 typedef enum {                                  /*!< CTIMER_AUX4_TMRB4TINV                                                     */
19546   CTIMER_AUX4_TMRB4TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
19547   CTIMER_AUX4_TMRB4TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
19548 } CTIMER_AUX4_TMRB4TINV_Enum;
19549 
19550 /* ===========================================  CTIMER AUX4 TMRB4NOSYNC [27..27]  ============================================ */
19551 typedef enum {                                  /*!< CTIMER_AUX4_TMRB4NOSYNC                                                   */
19552   CTIMER_AUX4_TMRB4NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
19553   CTIMER_AUX4_TMRB4NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
19554 } CTIMER_AUX4_TMRB4NOSYNC_Enum;
19555 
19556 /* ============================================  CTIMER AUX4 TMRB4TRIG [23..26]  ============================================= */
19557 typedef enum {                                  /*!< CTIMER_AUX4_TMRB4TRIG                                                     */
19558   CTIMER_AUX4_TMRB4TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
19559   CTIMER_AUX4_TMRB4TRIG_A4OUT          = 1,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
19560   CTIMER_AUX4_TMRB4TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
19561   CTIMER_AUX4_TMRB4TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
19562   CTIMER_AUX4_TMRB4TRIG_A7OUT          = 4,     /*!< A7OUT : Trigger source is CTIMERA7 OUT.                                   */
19563   CTIMER_AUX4_TMRB4TRIG_B7OUT          = 5,     /*!< B7OUT : Trigger source is CTIMERB7 OUT.                                   */
19564   CTIMER_AUX4_TMRB4TRIG_A1OUT          = 6,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
19565   CTIMER_AUX4_TMRB4TRIG_B1OUT          = 7,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
19566   CTIMER_AUX4_TMRB4TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
19567   CTIMER_AUX4_TMRB4TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
19568   CTIMER_AUX4_TMRB4TRIG_A1OUT2         = 10,    /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2.                                 */
19569   CTIMER_AUX4_TMRB4TRIG_B1OUT2         = 11,    /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2.                                 */
19570   CTIMER_AUX4_TMRB4TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
19571   CTIMER_AUX4_TMRB4TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
19572   CTIMER_AUX4_TMRB4TRIG_B5OUT2DUAL     = 14,    /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge.                  */
19573   CTIMER_AUX4_TMRB4TRIG_A5OUT2DUAL     = 15,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
19574 } CTIMER_AUX4_TMRB4TRIG_Enum;
19575 
19576 /* ============================================  CTIMER AUX4 TMRA4EN23 [14..14]  ============================================= */
19577 typedef enum {                                  /*!< CTIMER_AUX4_TMRA4EN23                                                     */
19578   CTIMER_AUX4_TMRA4EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
19579   CTIMER_AUX4_TMRA4EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
19580 } CTIMER_AUX4_TMRA4EN23_Enum;
19581 
19582 /* ============================================  CTIMER AUX4 TMRA4POL23 [13..13]  ============================================ */
19583 typedef enum {                                  /*!< CTIMER_AUX4_TMRA4POL23                                                    */
19584   CTIMER_AUX4_TMRA4POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
19585   CTIMER_AUX4_TMRA4POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
19586 } CTIMER_AUX4_TMRA4POL23_Enum;
19587 
19588 /* ============================================  CTIMER AUX4 TMRA4TINV [12..12]  ============================================= */
19589 typedef enum {                                  /*!< CTIMER_AUX4_TMRA4TINV                                                     */
19590   CTIMER_AUX4_TMRA4TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
19591   CTIMER_AUX4_TMRA4TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
19592 } CTIMER_AUX4_TMRA4TINV_Enum;
19593 
19594 /* ===========================================  CTIMER AUX4 TMRA4NOSYNC [11..11]  ============================================ */
19595 typedef enum {                                  /*!< CTIMER_AUX4_TMRA4NOSYNC                                                   */
19596   CTIMER_AUX4_TMRA4NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
19597   CTIMER_AUX4_TMRA4NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
19598 } CTIMER_AUX4_TMRA4NOSYNC_Enum;
19599 
19600 /* =============================================  CTIMER AUX4 TMRA4TRIG [7..10]  ============================================= */
19601 typedef enum {                                  /*!< CTIMER_AUX4_TMRA4TRIG                                                     */
19602   CTIMER_AUX4_TMRA4TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
19603   CTIMER_AUX4_TMRA4TRIG_STIMER         = 1,     /*!< STIMER : Trigger source is STimer Interrupt. Only Active When
19604                                                      CTLINK==1 and TMRB4TRIG!=0. TMRB4TRIG selects an STIMER
19605                                                      interrupt                                                                 */
19606   CTIMER_AUX4_TMRA4TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
19607   CTIMER_AUX4_TMRA4TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
19608   CTIMER_AUX4_TMRA4TRIG_A6OUT          = 4,     /*!< A6OUT : Trigger source is CTIMERA6 OUT.                                   */
19609   CTIMER_AUX4_TMRA4TRIG_B6OUT          = 5,     /*!< B6OUT : Trigger source is CTIMERB6 OUT.                                   */
19610   CTIMER_AUX4_TMRA4TRIG_A2OUT          = 6,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
19611   CTIMER_AUX4_TMRA4TRIG_B2OUT          = 7,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
19612   CTIMER_AUX4_TMRA4TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
19613   CTIMER_AUX4_TMRA4TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
19614   CTIMER_AUX4_TMRA4TRIG_A1OUT2         = 10,    /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2.                                 */
19615   CTIMER_AUX4_TMRA4TRIG_B1OUT2         = 11,    /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2.                                 */
19616   CTIMER_AUX4_TMRA4TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
19617   CTIMER_AUX4_TMRA4TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
19618   CTIMER_AUX4_TMRA4TRIG_B5OUT2DUAL     = 14,    /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge.                  */
19619   CTIMER_AUX4_TMRA4TRIG_A5OUT2DUAL     = 15,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
19620 } CTIMER_AUX4_TMRA4TRIG_Enum;
19621 
19622 /* =========================================================  TMR5  ========================================================== */
19623 /* ========================================================  CMPRA5  ========================================================= */
19624 /* ========================================================  CMPRB5  ========================================================= */
19625 /* =========================================================  CTRL5  ========================================================= */
19626 /* =============================================  CTIMER CTRL5 CTLINK5 [31..31]  ============================================= */
19627 typedef enum {                                  /*!< CTIMER_CTRL5_CTLINK5                                                      */
19628   CTIMER_CTRL5_CTLINK5_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A5/B5 timers as two independent 16-bit
19629                                                      timers (default).                                                         */
19630   CTIMER_CTRL5_CTLINK5_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A5/B5 timers into a single 32-bit timer.               */
19631 } CTIMER_CTRL5_CTLINK5_Enum;
19632 
19633 /* ============================================  CTIMER CTRL5 TMRB5POL [28..28]  ============================================= */
19634 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5POL                                                     */
19635   CTIMER_CTRL5_TMRB5POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB5 pin is the same as the
19636                                                      timer output.                                                             */
19637   CTIMER_CTRL5_TMRB5POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB5 pin is the inverse of
19638                                                      the timer output.                                                         */
19639 } CTIMER_CTRL5_TMRB5POL_Enum;
19640 
19641 /* ============================================  CTIMER CTRL5 TMRB5CLR [27..27]  ============================================= */
19642 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5CLR                                                     */
19643   CTIMER_CTRL5_TMRB5CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B5 to run                                       */
19644   CTIMER_CTRL5_TMRB5CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B5 at 0x0000.                                 */
19645 } CTIMER_CTRL5_TMRB5CLR_Enum;
19646 
19647 /* ============================================  CTIMER CTRL5 TMRB5IE1 [26..26]  ============================================= */
19648 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5IE1                                                     */
19649   CTIMER_CTRL5_TMRB5IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B5 from generating an interrupt
19650                                                      based on COMPR1.                                                          */
19651   CTIMER_CTRL5_TMRB5IE1_EN             = 1,     /*!< EN : Enable counter/timer B5 to generate an interrupt based
19652                                                      on COMPR1.                                                                */
19653 } CTIMER_CTRL5_TMRB5IE1_Enum;
19654 
19655 /* ============================================  CTIMER CTRL5 TMRB5IE0 [25..25]  ============================================= */
19656 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5IE0                                                     */
19657   CTIMER_CTRL5_TMRB5IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B5 from generating an interrupt
19658                                                      based on COMPR0.                                                          */
19659   CTIMER_CTRL5_TMRB5IE0_EN             = 1,     /*!< EN : Enable counter/timer B5 to generate an interrupt based
19660                                                      on COMPR0                                                                 */
19661 } CTIMER_CTRL5_TMRB5IE0_Enum;
19662 
19663 /* =============================================  CTIMER CTRL5 TMRB5FN [22..24]  ============================================= */
19664 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5FN                                                      */
19665   CTIMER_CTRL5_TMRB5FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
19666                                                      to CMPR0B5, stop.                                                         */
19667   CTIMER_CTRL5_TMRB5FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
19668                                                      pulses). Count to CMPR0B5, restart.                                       */
19669   CTIMER_CTRL5_TMRB5FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B5, assert,
19670                                                      count to CMPR1B5, deassert, stop.                                         */
19671   CTIMER_CTRL5_TMRB5FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B5, assert, count
19672                                                      to CMPR1B5, deassert, restart.                                            */
19673   CTIMER_CTRL5_TMRB5FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
19674   CTIMER_CTRL5_TMRB5FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
19675   CTIMER_CTRL5_TMRB5FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
19676   CTIMER_CTRL5_TMRB5FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
19677 } CTIMER_CTRL5_TMRB5FN_Enum;
19678 
19679 /* ============================================  CTIMER CTRL5 TMRB5CLK [17..21]  ============================================= */
19680 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5CLK                                                     */
19681   CTIMER_CTRL5_TMRB5CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
19682   CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
19683   CTIMER_CTRL5_TMRB5CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
19684   CTIMER_CTRL5_TMRB5CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
19685   CTIMER_CTRL5_TMRB5CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
19686   CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
19687   CTIMER_CTRL5_TMRB5CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
19688   CTIMER_CTRL5_TMRB5CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
19689   CTIMER_CTRL5_TMRB5CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
19690   CTIMER_CTRL5_TMRB5CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
19691   CTIMER_CTRL5_TMRB5CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
19692   CTIMER_CTRL5_TMRB5CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
19693   CTIMER_CTRL5_TMRB5CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
19694   CTIMER_CTRL5_TMRB5CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
19695   CTIMER_CTRL5_TMRB5CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
19696   CTIMER_CTRL5_TMRB5CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
19697                                                      available when MCU is in active mode)                                     */
19698   CTIMER_CTRL5_TMRB5CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
19699   CTIMER_CTRL5_TMRB5CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
19700   CTIMER_CTRL5_TMRB5CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
19701   CTIMER_CTRL5_TMRB5CLK_CTMRA5         = 20,    /*!< CTMRA5 : Clock source is CTIMERA5 OUT.                                    */
19702   CTIMER_CTRL5_TMRB5CLK_CTMRA0         = 21,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
19703   CTIMER_CTRL5_TMRB5CLK_CTMRB0         = 22,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
19704   CTIMER_CTRL5_TMRB5CLK_CTMRA6         = 23,    /*!< CTMRA6 : Clock source is CTIMERA6 OUT.                                    */
19705   CTIMER_CTRL5_TMRB5CLK_CTMRB6         = 24,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
19706   CTIMER_CTRL5_TMRB5CLK_CTMRB1         = 25,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
19707   CTIMER_CTRL5_TMRB5CLK_CTMRB2         = 26,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
19708   CTIMER_CTRL5_TMRB5CLK_CTMRB3         = 27,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
19709   CTIMER_CTRL5_TMRB5CLK_CTMRB4         = 28,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
19710   CTIMER_CTRL5_TMRB5CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
19711   CTIMER_CTRL5_TMRB5CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
19712   CTIMER_CTRL5_TMRB5CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
19713 } CTIMER_CTRL5_TMRB5CLK_Enum;
19714 
19715 /* =============================================  CTIMER CTRL5 TMRB5EN [16..16]  ============================================= */
19716 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5EN                                                      */
19717   CTIMER_CTRL5_TMRB5EN_DIS             = 0,     /*!< DIS : Counter/Timer B5 Disable.                                           */
19718   CTIMER_CTRL5_TMRB5EN_EN              = 1,     /*!< EN : Counter/Timer B5 Enable.                                             */
19719 } CTIMER_CTRL5_TMRB5EN_Enum;
19720 
19721 /* ============================================  CTIMER CTRL5 TMRA5POL [12..12]  ============================================= */
19722 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5POL                                                     */
19723   CTIMER_CTRL5_TMRA5POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA5 pin is the same as the
19724                                                      timer output.                                                             */
19725   CTIMER_CTRL5_TMRA5POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA5 pin is the inverse of
19726                                                      the timer output.                                                         */
19727 } CTIMER_CTRL5_TMRA5POL_Enum;
19728 
19729 /* ============================================  CTIMER CTRL5 TMRA5CLR [11..11]  ============================================= */
19730 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5CLR                                                     */
19731   CTIMER_CTRL5_TMRA5CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A5 to run                                       */
19732   CTIMER_CTRL5_TMRA5CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A5 at 0x0000.                                 */
19733 } CTIMER_CTRL5_TMRA5CLR_Enum;
19734 
19735 /* ============================================  CTIMER CTRL5 TMRA5IE1 [10..10]  ============================================= */
19736 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5IE1                                                     */
19737   CTIMER_CTRL5_TMRA5IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A5 from generating an interrupt
19738                                                      based on COMPR1.                                                          */
19739   CTIMER_CTRL5_TMRA5IE1_EN             = 1,     /*!< EN : Enable counter/timer A5 to generate an interrupt based
19740                                                      on COMPR1.                                                                */
19741 } CTIMER_CTRL5_TMRA5IE1_Enum;
19742 
19743 /* =============================================  CTIMER CTRL5 TMRA5IE0 [9..9]  ============================================== */
19744 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5IE0                                                     */
19745   CTIMER_CTRL5_TMRA5IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A5 from generating an interrupt
19746                                                      based on COMPR0.                                                          */
19747   CTIMER_CTRL5_TMRA5IE0_EN             = 1,     /*!< EN : Enable counter/timer A5 to generate an interrupt based
19748                                                      on COMPR0.                                                                */
19749 } CTIMER_CTRL5_TMRA5IE0_Enum;
19750 
19751 /* ==============================================  CTIMER CTRL5 TMRA5FN [6..8]  ============================================== */
19752 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5FN                                                      */
19753   CTIMER_CTRL5_TMRA5FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
19754                                                      to CMPR0A5, stop.                                                         */
19755   CTIMER_CTRL5_TMRA5FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
19756                                                      pulses). Count to CMPR0A5, restart.                                       */
19757   CTIMER_CTRL5_TMRA5FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A5, assert,
19758                                                      count to CMPR1A5, deassert, stop.                                         */
19759   CTIMER_CTRL5_TMRA5FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A5, assert, count
19760                                                      to CMPR1A5, deassert, restart.                                            */
19761   CTIMER_CTRL5_TMRA5FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
19762   CTIMER_CTRL5_TMRA5FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
19763   CTIMER_CTRL5_TMRA5FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
19764   CTIMER_CTRL5_TMRA5FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
19765 } CTIMER_CTRL5_TMRA5FN_Enum;
19766 
19767 /* =============================================  CTIMER CTRL5 TMRA5CLK [1..5]  ============================================== */
19768 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5CLK                                                     */
19769   CTIMER_CTRL5_TMRA5CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
19770   CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
19771   CTIMER_CTRL5_TMRA5CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
19772   CTIMER_CTRL5_TMRA5CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
19773   CTIMER_CTRL5_TMRA5CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
19774   CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
19775   CTIMER_CTRL5_TMRA5CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
19776   CTIMER_CTRL5_TMRA5CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
19777   CTIMER_CTRL5_TMRA5CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
19778   CTIMER_CTRL5_TMRA5CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
19779   CTIMER_CTRL5_TMRA5CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
19780   CTIMER_CTRL5_TMRA5CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
19781   CTIMER_CTRL5_TMRA5CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
19782   CTIMER_CTRL5_TMRA5CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
19783   CTIMER_CTRL5_TMRA5CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
19784   CTIMER_CTRL5_TMRA5CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
19785                                                      available when MCU is in active mode)                                     */
19786   CTIMER_CTRL5_TMRA5CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
19787   CTIMER_CTRL5_TMRA5CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
19788   CTIMER_CTRL5_TMRA5CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
19789   CTIMER_CTRL5_TMRA5CLK_CTMRB5         = 20,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
19790   CTIMER_CTRL5_TMRA5CLK_CTMRA0         = 21,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
19791   CTIMER_CTRL5_TMRA5CLK_CTMRB0         = 22,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
19792   CTIMER_CTRL5_TMRA5CLK_CTMRA6         = 23,    /*!< CTMRA6 : Clock source is CTIMERA6 OUT.                                    */
19793   CTIMER_CTRL5_TMRA5CLK_CTMRB6         = 24,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
19794   CTIMER_CTRL5_TMRA5CLK_CTMRB1         = 25,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
19795   CTIMER_CTRL5_TMRA5CLK_CTMRB2         = 26,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
19796   CTIMER_CTRL5_TMRA5CLK_CTMRB3         = 27,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
19797   CTIMER_CTRL5_TMRA5CLK_CTMRB4         = 28,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
19798   CTIMER_CTRL5_TMRA5CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
19799   CTIMER_CTRL5_TMRA5CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
19800   CTIMER_CTRL5_TMRA5CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
19801 } CTIMER_CTRL5_TMRA5CLK_Enum;
19802 
19803 /* ==============================================  CTIMER CTRL5 TMRA5EN [0..0]  ============================================== */
19804 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5EN                                                      */
19805   CTIMER_CTRL5_TMRA5EN_DIS             = 0,     /*!< DIS : Counter/Timer A5 Disable.                                           */
19806   CTIMER_CTRL5_TMRA5EN_EN              = 1,     /*!< EN : Counter/Timer A5 Enable.                                             */
19807 } CTIMER_CTRL5_TMRA5EN_Enum;
19808 
19809 /* =======================================================  CMPRAUXA5  ======================================================= */
19810 /* =======================================================  CMPRAUXB5  ======================================================= */
19811 /* =========================================================  AUX5  ========================================================== */
19812 /* ============================================  CTIMER AUX5 TMRB5EN23 [30..30]  ============================================= */
19813 typedef enum {                                  /*!< CTIMER_AUX5_TMRB5EN23                                                     */
19814   CTIMER_AUX5_TMRB5EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
19815   CTIMER_AUX5_TMRB5EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
19816 } CTIMER_AUX5_TMRB5EN23_Enum;
19817 
19818 /* ============================================  CTIMER AUX5 TMRB5POL23 [29..29]  ============================================ */
19819 typedef enum {                                  /*!< CTIMER_AUX5_TMRB5POL23                                                    */
19820   CTIMER_AUX5_TMRB5POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
19821   CTIMER_AUX5_TMRB5POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
19822 } CTIMER_AUX5_TMRB5POL23_Enum;
19823 
19824 /* ============================================  CTIMER AUX5 TMRB5TINV [28..28]  ============================================= */
19825 typedef enum {                                  /*!< CTIMER_AUX5_TMRB5TINV                                                     */
19826   CTIMER_AUX5_TMRB5TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
19827   CTIMER_AUX5_TMRB5TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
19828 } CTIMER_AUX5_TMRB5TINV_Enum;
19829 
19830 /* ===========================================  CTIMER AUX5 TMRB5NOSYNC [27..27]  ============================================ */
19831 typedef enum {                                  /*!< CTIMER_AUX5_TMRB5NOSYNC                                                   */
19832   CTIMER_AUX5_TMRB5NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
19833   CTIMER_AUX5_TMRB5NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
19834 } CTIMER_AUX5_TMRB5NOSYNC_Enum;
19835 
19836 /* ============================================  CTIMER AUX5 TMRB5TRIG [23..26]  ============================================= */
19837 typedef enum {                                  /*!< CTIMER_AUX5_TMRB5TRIG                                                     */
19838   CTIMER_AUX5_TMRB5TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
19839   CTIMER_AUX5_TMRB5TRIG_A5OUT          = 1,     /*!< A5OUT : Trigger source is CTIMERA5 OUT.                                   */
19840   CTIMER_AUX5_TMRB5TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
19841   CTIMER_AUX5_TMRB5TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
19842   CTIMER_AUX5_TMRB5TRIG_A6OUT          = 4,     /*!< A6OUT : Trigger source is CTIMERA6 OUT.                                   */
19843   CTIMER_AUX5_TMRB5TRIG_B6OUT          = 5,     /*!< B6OUT : Trigger source is CTIMERB6 OUT.                                   */
19844   CTIMER_AUX5_TMRB5TRIG_A1OUT          = 6,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
19845   CTIMER_AUX5_TMRB5TRIG_B1OUT          = 7,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
19846   CTIMER_AUX5_TMRB5TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
19847   CTIMER_AUX5_TMRB5TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
19848   CTIMER_AUX5_TMRB5TRIG_A0OUT2         = 10,    /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2.                                 */
19849   CTIMER_AUX5_TMRB5TRIG_B0OUT2         = 11,    /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2.                                 */
19850   CTIMER_AUX5_TMRB5TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
19851   CTIMER_AUX5_TMRB5TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
19852   CTIMER_AUX5_TMRB5TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
19853   CTIMER_AUX5_TMRB5TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
19854 } CTIMER_AUX5_TMRB5TRIG_Enum;
19855 
19856 /* ============================================  CTIMER AUX5 TMRA5EN23 [14..14]  ============================================= */
19857 typedef enum {                                  /*!< CTIMER_AUX5_TMRA5EN23                                                     */
19858   CTIMER_AUX5_TMRA5EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
19859   CTIMER_AUX5_TMRA5EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
19860 } CTIMER_AUX5_TMRA5EN23_Enum;
19861 
19862 /* ============================================  CTIMER AUX5 TMRA5POL23 [13..13]  ============================================ */
19863 typedef enum {                                  /*!< CTIMER_AUX5_TMRA5POL23                                                    */
19864   CTIMER_AUX5_TMRA5POL23_NORMAL        = 0,     /*!< NORMAL : Upper output normal polarity                                     */
19865   CTIMER_AUX5_TMRA5POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
19866 } CTIMER_AUX5_TMRA5POL23_Enum;
19867 
19868 /* ============================================  CTIMER AUX5 TMRA5TINV [12..12]  ============================================= */
19869 typedef enum {                                  /*!< CTIMER_AUX5_TMRA5TINV                                                     */
19870   CTIMER_AUX5_TMRA5TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
19871   CTIMER_AUX5_TMRA5TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
19872 } CTIMER_AUX5_TMRA5TINV_Enum;
19873 
19874 /* ===========================================  CTIMER AUX5 TMRA5NOSYNC [11..11]  ============================================ */
19875 typedef enum {                                  /*!< CTIMER_AUX5_TMRA5NOSYNC                                                   */
19876   CTIMER_AUX5_TMRA5NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
19877   CTIMER_AUX5_TMRA5NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
19878 } CTIMER_AUX5_TMRA5NOSYNC_Enum;
19879 
19880 /* =============================================  CTIMER AUX5 TMRA5TRIG [7..10]  ============================================= */
19881 typedef enum {                                  /*!< CTIMER_AUX5_TMRA5TRIG                                                     */
19882   CTIMER_AUX5_TMRA5TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
19883   CTIMER_AUX5_TMRA5TRIG_STIMER         = 1,     /*!< STIMER : Trigger source is STimer Interrupt. Only Active When
19884                                                      CTLINK==1 and TMRB5TRIG!=0. TMRB5TRIG selects an STIMER
19885                                                      interrupt                                                                 */
19886   CTIMER_AUX5_TMRA5TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
19887   CTIMER_AUX5_TMRA5TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
19888   CTIMER_AUX5_TMRA5TRIG_A4OUT          = 4,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
19889   CTIMER_AUX5_TMRA5TRIG_B4OUT          = 5,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
19890   CTIMER_AUX5_TMRA5TRIG_A2OUT          = 6,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
19891   CTIMER_AUX5_TMRA5TRIG_B2OUT          = 7,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
19892   CTIMER_AUX5_TMRA5TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
19893   CTIMER_AUX5_TMRA5TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
19894   CTIMER_AUX5_TMRA5TRIG_A0OUT2         = 10,    /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2.                                 */
19895   CTIMER_AUX5_TMRA5TRIG_B0OUT2         = 11,    /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2.                                 */
19896   CTIMER_AUX5_TMRA5TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
19897   CTIMER_AUX5_TMRA5TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
19898   CTIMER_AUX5_TMRA5TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
19899   CTIMER_AUX5_TMRA5TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
19900 } CTIMER_AUX5_TMRA5TRIG_Enum;
19901 
19902 /* =========================================================  TMR6  ========================================================== */
19903 /* ========================================================  CMPRA6  ========================================================= */
19904 /* ========================================================  CMPRB6  ========================================================= */
19905 /* =========================================================  CTRL6  ========================================================= */
19906 /* =============================================  CTIMER CTRL6 CTLINK6 [31..31]  ============================================= */
19907 typedef enum {                                  /*!< CTIMER_CTRL6_CTLINK6                                                      */
19908   CTIMER_CTRL6_CTLINK6_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A6/B6 timers as two independent 16-bit
19909                                                      timers (default).                                                         */
19910   CTIMER_CTRL6_CTLINK6_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A6/B6 timers into a single 32-bit timer.               */
19911 } CTIMER_CTRL6_CTLINK6_Enum;
19912 
19913 /* ============================================  CTIMER CTRL6 TMRB6POL [28..28]  ============================================= */
19914 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6POL                                                     */
19915   CTIMER_CTRL6_TMRB6POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB6 pin is the same as the
19916                                                      timer output.                                                             */
19917   CTIMER_CTRL6_TMRB6POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB6 pin is the inverse of
19918                                                      the timer output.                                                         */
19919 } CTIMER_CTRL6_TMRB6POL_Enum;
19920 
19921 /* ============================================  CTIMER CTRL6 TMRB6CLR [27..27]  ============================================= */
19922 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6CLR                                                     */
19923   CTIMER_CTRL6_TMRB6CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B6 to run                                       */
19924   CTIMER_CTRL6_TMRB6CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B6 at 0x0000.                                 */
19925 } CTIMER_CTRL6_TMRB6CLR_Enum;
19926 
19927 /* ============================================  CTIMER CTRL6 TMRB6IE1 [26..26]  ============================================= */
19928 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6IE1                                                     */
19929   CTIMER_CTRL6_TMRB6IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B6 from generating an interrupt
19930                                                      based on COMPR1.                                                          */
19931   CTIMER_CTRL6_TMRB6IE1_EN             = 1,     /*!< EN : Enable counter/timer B6 to generate an interrupt based
19932                                                      on COMPR1.                                                                */
19933 } CTIMER_CTRL6_TMRB6IE1_Enum;
19934 
19935 /* ============================================  CTIMER CTRL6 TMRB6IE0 [25..25]  ============================================= */
19936 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6IE0                                                     */
19937   CTIMER_CTRL6_TMRB6IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B6 from generating an interrupt
19938                                                      based on COMPR0.                                                          */
19939   CTIMER_CTRL6_TMRB6IE0_EN             = 1,     /*!< EN : Enable counter/timer B6 to generate an interrupt based
19940                                                      on COMPR0                                                                 */
19941 } CTIMER_CTRL6_TMRB6IE0_Enum;
19942 
19943 /* =============================================  CTIMER CTRL6 TMRB6FN [22..24]  ============================================= */
19944 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6FN                                                      */
19945   CTIMER_CTRL6_TMRB6FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
19946                                                      to CMPR0B6, stop.                                                         */
19947   CTIMER_CTRL6_TMRB6FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
19948                                                      pulses). Count to CMPR0B6, restart.                                       */
19949   CTIMER_CTRL6_TMRB6FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B6, assert,
19950                                                      count to CMPR1B6, deassert, stop.                                         */
19951   CTIMER_CTRL6_TMRB6FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B6, assert, count
19952                                                      to CMPR1B6, deassert, restart.                                            */
19953   CTIMER_CTRL6_TMRB6FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
19954   CTIMER_CTRL6_TMRB6FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
19955   CTIMER_CTRL6_TMRB6FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
19956   CTIMER_CTRL6_TMRB6FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
19957 } CTIMER_CTRL6_TMRB6FN_Enum;
19958 
19959 /* ============================================  CTIMER CTRL6 TMRB6CLK [17..21]  ============================================= */
19960 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6CLK                                                     */
19961   CTIMER_CTRL6_TMRB6CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
19962   CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
19963   CTIMER_CTRL6_TMRB6CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
19964   CTIMER_CTRL6_TMRB6CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
19965   CTIMER_CTRL6_TMRB6CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
19966   CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
19967   CTIMER_CTRL6_TMRB6CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
19968   CTIMER_CTRL6_TMRB6CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
19969   CTIMER_CTRL6_TMRB6CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
19970   CTIMER_CTRL6_TMRB6CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
19971   CTIMER_CTRL6_TMRB6CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
19972   CTIMER_CTRL6_TMRB6CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
19973   CTIMER_CTRL6_TMRB6CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
19974   CTIMER_CTRL6_TMRB6CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
19975   CTIMER_CTRL6_TMRB6CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
19976   CTIMER_CTRL6_TMRB6CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
19977                                                      available when MCU is in active mode)                                     */
19978   CTIMER_CTRL6_TMRB6CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
19979   CTIMER_CTRL6_TMRB6CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
19980   CTIMER_CTRL6_TMRB6CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
19981   CTIMER_CTRL6_TMRB6CLK_CTMRA6         = 20,    /*!< CTMRA6 : Clock source is CTIMERA6 OUT.                                    */
19982   CTIMER_CTRL6_TMRB6CLK_CTMRA3         = 21,    /*!< CTMRA3 : Clock source is CTIMERA3 OUT.                                    */
19983   CTIMER_CTRL6_TMRB6CLK_CTMRB3         = 22,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
19984   CTIMER_CTRL6_TMRB6CLK_CTMRA7         = 23,    /*!< CTMRA7 : Clock source is CTIMERA7 OUT.                                    */
19985   CTIMER_CTRL6_TMRB6CLK_CTMRB7         = 24,    /*!< CTMRB7 : Clock source is CTIMERB7 OUT.                                    */
19986   CTIMER_CTRL6_TMRB6CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
19987   CTIMER_CTRL6_TMRB6CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
19988   CTIMER_CTRL6_TMRB6CLK_CTMRB2         = 27,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
19989   CTIMER_CTRL6_TMRB6CLK_CTMRB4         = 28,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
19990   CTIMER_CTRL6_TMRB6CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
19991   CTIMER_CTRL6_TMRB6CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
19992   CTIMER_CTRL6_TMRB6CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
19993 } CTIMER_CTRL6_TMRB6CLK_Enum;
19994 
19995 /* =============================================  CTIMER CTRL6 TMRB6EN [16..16]  ============================================= */
19996 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6EN                                                      */
19997   CTIMER_CTRL6_TMRB6EN_DIS             = 0,     /*!< DIS : Counter/Timer B6 Disable.                                           */
19998   CTIMER_CTRL6_TMRB6EN_EN              = 1,     /*!< EN : Counter/Timer B6 Enable.                                             */
19999 } CTIMER_CTRL6_TMRB6EN_Enum;
20000 
20001 /* ============================================  CTIMER CTRL6 TMRA6POL [12..12]  ============================================= */
20002 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6POL                                                     */
20003   CTIMER_CTRL6_TMRA6POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA6 pin is the same as the
20004                                                      timer output.                                                             */
20005   CTIMER_CTRL6_TMRA6POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA6 pin is the inverse of
20006                                                      the timer output.                                                         */
20007 } CTIMER_CTRL6_TMRA6POL_Enum;
20008 
20009 /* ============================================  CTIMER CTRL6 TMRA6CLR [11..11]  ============================================= */
20010 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6CLR                                                     */
20011   CTIMER_CTRL6_TMRA6CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A6 to run                                       */
20012   CTIMER_CTRL6_TMRA6CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A6 at 0x0000.                                 */
20013 } CTIMER_CTRL6_TMRA6CLR_Enum;
20014 
20015 /* ============================================  CTIMER CTRL6 TMRA6IE1 [10..10]  ============================================= */
20016 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6IE1                                                     */
20017   CTIMER_CTRL6_TMRA6IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A6 from generating an interrupt
20018                                                      based on COMPR1.                                                          */
20019   CTIMER_CTRL6_TMRA6IE1_EN             = 1,     /*!< EN : Enable counter/timer A6 to generate an interrupt based
20020                                                      on COMPR1.                                                                */
20021 } CTIMER_CTRL6_TMRA6IE1_Enum;
20022 
20023 /* =============================================  CTIMER CTRL6 TMRA6IE0 [9..9]  ============================================== */
20024 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6IE0                                                     */
20025   CTIMER_CTRL6_TMRA6IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A6 from generating an interrupt
20026                                                      based on COMPR0.                                                          */
20027   CTIMER_CTRL6_TMRA6IE0_EN             = 1,     /*!< EN : Enable counter/timer A6 to generate an interrupt based
20028                                                      on COMPR0.                                                                */
20029 } CTIMER_CTRL6_TMRA6IE0_Enum;
20030 
20031 /* ==============================================  CTIMER CTRL6 TMRA6FN [6..8]  ============================================== */
20032 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6FN                                                      */
20033   CTIMER_CTRL6_TMRA6FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
20034                                                      to CMPR0A6, stop.                                                         */
20035   CTIMER_CTRL6_TMRA6FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
20036                                                      pulses). Count to CMPR0A6, restart.                                       */
20037   CTIMER_CTRL6_TMRA6FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A6, assert,
20038                                                      count to CMPR1A6, deassert, stop.                                         */
20039   CTIMER_CTRL6_TMRA6FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A6, assert, count
20040                                                      to CMPR1A6, deassert, restart.                                            */
20041   CTIMER_CTRL6_TMRA6FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
20042   CTIMER_CTRL6_TMRA6FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
20043   CTIMER_CTRL6_TMRA6FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
20044   CTIMER_CTRL6_TMRA6FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
20045 } CTIMER_CTRL6_TMRA6FN_Enum;
20046 
20047 /* =============================================  CTIMER CTRL6 TMRA6CLK [1..5]  ============================================== */
20048 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6CLK                                                     */
20049   CTIMER_CTRL6_TMRA6CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
20050   CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
20051   CTIMER_CTRL6_TMRA6CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
20052   CTIMER_CTRL6_TMRA6CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
20053   CTIMER_CTRL6_TMRA6CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
20054   CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
20055   CTIMER_CTRL6_TMRA6CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
20056   CTIMER_CTRL6_TMRA6CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
20057   CTIMER_CTRL6_TMRA6CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
20058   CTIMER_CTRL6_TMRA6CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
20059   CTIMER_CTRL6_TMRA6CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
20060   CTIMER_CTRL6_TMRA6CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
20061   CTIMER_CTRL6_TMRA6CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
20062   CTIMER_CTRL6_TMRA6CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
20063   CTIMER_CTRL6_TMRA6CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
20064   CTIMER_CTRL6_TMRA6CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
20065                                                      available when MCU is in active mode)                                     */
20066   CTIMER_CTRL6_TMRA6CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
20067   CTIMER_CTRL6_TMRA6CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
20068   CTIMER_CTRL6_TMRA6CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
20069   CTIMER_CTRL6_TMRA6CLK_CTMRB6         = 20,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
20070   CTIMER_CTRL6_TMRA6CLK_CTMRA3         = 21,    /*!< CTMRA3 : Clock source is CTIMERA3 OUT.                                    */
20071   CTIMER_CTRL6_TMRA6CLK_CTMRB3         = 22,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
20072   CTIMER_CTRL6_TMRA6CLK_CTMRA7         = 23,    /*!< CTMRA7 : Clock source is CTIMERA7 OUT.                                    */
20073   CTIMER_CTRL6_TMRA6CLK_CTMRB7         = 24,    /*!< CTMRB7 : Clock source is CTIMERB7 OUT.                                    */
20074   CTIMER_CTRL6_TMRA6CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
20075   CTIMER_CTRL6_TMRA6CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
20076   CTIMER_CTRL6_TMRA6CLK_CTMRB2         = 27,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
20077   CTIMER_CTRL6_TMRA6CLK_CTMRB4         = 28,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
20078   CTIMER_CTRL6_TMRA6CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
20079   CTIMER_CTRL6_TMRA6CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
20080   CTIMER_CTRL6_TMRA6CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
20081 } CTIMER_CTRL6_TMRA6CLK_Enum;
20082 
20083 /* ==============================================  CTIMER CTRL6 TMRA6EN [0..0]  ============================================== */
20084 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6EN                                                      */
20085   CTIMER_CTRL6_TMRA6EN_DIS             = 0,     /*!< DIS : Counter/Timer A6 Disable.                                           */
20086   CTIMER_CTRL6_TMRA6EN_EN              = 1,     /*!< EN : Counter/Timer A6 Enable.                                             */
20087 } CTIMER_CTRL6_TMRA6EN_Enum;
20088 
20089 /* =======================================================  CMPRAUXA6  ======================================================= */
20090 /* =======================================================  CMPRAUXB6  ======================================================= */
20091 /* =========================================================  AUX6  ========================================================== */
20092 /* ============================================  CTIMER AUX6 TMRB6EN23 [30..30]  ============================================= */
20093 typedef enum {                                  /*!< CTIMER_AUX6_TMRB6EN23                                                     */
20094   CTIMER_AUX6_TMRB6EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
20095   CTIMER_AUX6_TMRB6EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
20096 } CTIMER_AUX6_TMRB6EN23_Enum;
20097 
20098 /* ============================================  CTIMER AUX6 TMRB6POL23 [29..29]  ============================================ */
20099 typedef enum {                                  /*!< CTIMER_AUX6_TMRB6POL23                                                    */
20100   CTIMER_AUX6_TMRB6POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
20101   CTIMER_AUX6_TMRB6POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
20102 } CTIMER_AUX6_TMRB6POL23_Enum;
20103 
20104 /* ============================================  CTIMER AUX6 TMRB6TINV [28..28]  ============================================= */
20105 typedef enum {                                  /*!< CTIMER_AUX6_TMRB6TINV                                                     */
20106   CTIMER_AUX6_TMRB6TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
20107   CTIMER_AUX6_TMRB6TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
20108 } CTIMER_AUX6_TMRB6TINV_Enum;
20109 
20110 /* ===========================================  CTIMER AUX6 TMRB6NOSYNC [27..27]  ============================================ */
20111 typedef enum {                                  /*!< CTIMER_AUX6_TMRB6NOSYNC                                                   */
20112   CTIMER_AUX6_TMRB6NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
20113   CTIMER_AUX6_TMRB6NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
20114 } CTIMER_AUX6_TMRB6NOSYNC_Enum;
20115 
20116 /* ============================================  CTIMER AUX6 TMRB6TRIG [23..26]  ============================================= */
20117 typedef enum {                                  /*!< CTIMER_AUX6_TMRB6TRIG                                                     */
20118   CTIMER_AUX6_TMRB6TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
20119   CTIMER_AUX6_TMRB6TRIG_A6OUT          = 1,     /*!< A6OUT : Trigger source is CTIMERA6 OUT.                                   */
20120   CTIMER_AUX6_TMRB6TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
20121   CTIMER_AUX6_TMRB6TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
20122   CTIMER_AUX6_TMRB6TRIG_A4OUT          = 4,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
20123   CTIMER_AUX6_TMRB6TRIG_B4OUT          = 5,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
20124   CTIMER_AUX6_TMRB6TRIG_A1OUT          = 6,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
20125   CTIMER_AUX6_TMRB6TRIG_B1OUT          = 7,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
20126   CTIMER_AUX6_TMRB6TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
20127   CTIMER_AUX6_TMRB6TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
20128   CTIMER_AUX6_TMRB6TRIG_A2OUT2         = 10,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
20129   CTIMER_AUX6_TMRB6TRIG_B2OUT2         = 11,    /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2.                                 */
20130   CTIMER_AUX6_TMRB6TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
20131   CTIMER_AUX6_TMRB6TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
20132   CTIMER_AUX6_TMRB6TRIG_B0OUT2DUAL     = 14,    /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge.                  */
20133   CTIMER_AUX6_TMRB6TRIG_A0OUT2DUAL     = 15,    /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge.                  */
20134 } CTIMER_AUX6_TMRB6TRIG_Enum;
20135 
20136 /* ============================================  CTIMER AUX6 TMRA6EN23 [14..14]  ============================================= */
20137 typedef enum {                                  /*!< CTIMER_AUX6_TMRA6EN23                                                     */
20138   CTIMER_AUX6_TMRA6EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
20139   CTIMER_AUX6_TMRA6EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
20140 } CTIMER_AUX6_TMRA6EN23_Enum;
20141 
20142 /* ============================================  CTIMER AUX6 TMRA6POL23 [13..13]  ============================================ */
20143 typedef enum {                                  /*!< CTIMER_AUX6_TMRA6POL23                                                    */
20144   CTIMER_AUX6_TMRA6POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
20145   CTIMER_AUX6_TMRA6POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
20146 } CTIMER_AUX6_TMRA6POL23_Enum;
20147 
20148 /* ============================================  CTIMER AUX6 TMRA6TINV [12..12]  ============================================= */
20149 typedef enum {                                  /*!< CTIMER_AUX6_TMRA6TINV                                                     */
20150   CTIMER_AUX6_TMRA6TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
20151   CTIMER_AUX6_TMRA6TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
20152 } CTIMER_AUX6_TMRA6TINV_Enum;
20153 
20154 /* ===========================================  CTIMER AUX6 TMRA6NOSYNC [11..11]  ============================================ */
20155 typedef enum {                                  /*!< CTIMER_AUX6_TMRA6NOSYNC                                                   */
20156   CTIMER_AUX6_TMRA6NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
20157   CTIMER_AUX6_TMRA6NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
20158 } CTIMER_AUX6_TMRA6NOSYNC_Enum;
20159 
20160 /* =============================================  CTIMER AUX6 TMRA6TRIG [7..10]  ============================================= */
20161 typedef enum {                                  /*!< CTIMER_AUX6_TMRA6TRIG                                                     */
20162   CTIMER_AUX6_TMRA6TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
20163   CTIMER_AUX6_TMRA6TRIG_B6OUT          = 1,     /*!< B6OUT : Trigger source is CTIMERB6 OUT.                                   */
20164   CTIMER_AUX6_TMRA6TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
20165   CTIMER_AUX6_TMRA6TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
20166   CTIMER_AUX6_TMRA6TRIG_A5OUT          = 4,     /*!< A5OUT : Trigger source is CTIMERA5 OUT.                                   */
20167   CTIMER_AUX6_TMRA6TRIG_B5OUT          = 5,     /*!< B5OUT : Trigger source is CTIMERB5 OUT.                                   */
20168   CTIMER_AUX6_TMRA6TRIG_A1OUT          = 6,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
20169   CTIMER_AUX6_TMRA6TRIG_B1OUT          = 7,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
20170   CTIMER_AUX6_TMRA6TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
20171   CTIMER_AUX6_TMRA6TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
20172   CTIMER_AUX6_TMRA6TRIG_A2OUT2         = 10,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
20173   CTIMER_AUX6_TMRA6TRIG_B2OUT2         = 11,    /*!< B2OUT2 : Trigger source is CTIMERBb OUT2.                                 */
20174   CTIMER_AUX6_TMRA6TRIG_A5OUT2DUAL     = 12,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
20175   CTIMER_AUX6_TMRA6TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
20176   CTIMER_AUX6_TMRA6TRIG_B0OUT2DUAL     = 14,    /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge.                  */
20177   CTIMER_AUX6_TMRA6TRIG_A0OUT2DUAL     = 15,    /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge.                  */
20178 } CTIMER_AUX6_TMRA6TRIG_Enum;
20179 
20180 /* =========================================================  TMR7  ========================================================== */
20181 /* ========================================================  CMPRA7  ========================================================= */
20182 /* ========================================================  CMPRB7  ========================================================= */
20183 /* =========================================================  CTRL7  ========================================================= */
20184 /* =============================================  CTIMER CTRL7 CTLINK7 [31..31]  ============================================= */
20185 typedef enum {                                  /*!< CTIMER_CTRL7_CTLINK7                                                      */
20186   CTIMER_CTRL7_CTLINK7_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A7/B7 timers as two independent 16-bit
20187                                                      timers (default).                                                         */
20188   CTIMER_CTRL7_CTLINK7_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A7/B7 timers into a single 32-bit timer.               */
20189 } CTIMER_CTRL7_CTLINK7_Enum;
20190 
20191 /* ============================================  CTIMER CTRL7 TMRB7POL [28..28]  ============================================= */
20192 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7POL                                                     */
20193   CTIMER_CTRL7_TMRB7POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB7 pin is the same as the
20194                                                      timer output.                                                             */
20195   CTIMER_CTRL7_TMRB7POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB7 pin is the inverse of
20196                                                      the timer output.                                                         */
20197 } CTIMER_CTRL7_TMRB7POL_Enum;
20198 
20199 /* ============================================  CTIMER CTRL7 TMRB7CLR [27..27]  ============================================= */
20200 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7CLR                                                     */
20201   CTIMER_CTRL7_TMRB7CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B7 to run                                       */
20202   CTIMER_CTRL7_TMRB7CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B7 at 0x0000.                                 */
20203 } CTIMER_CTRL7_TMRB7CLR_Enum;
20204 
20205 /* ============================================  CTIMER CTRL7 TMRB7IE1 [26..26]  ============================================= */
20206 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7IE1                                                     */
20207   CTIMER_CTRL7_TMRB7IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B7 from generating an interrupt
20208                                                      based on COMPR1.                                                          */
20209   CTIMER_CTRL7_TMRB7IE1_EN             = 1,     /*!< EN : Enable counter/timer B7 to generate an interrupt based
20210                                                      on COMPR1.                                                                */
20211 } CTIMER_CTRL7_TMRB7IE1_Enum;
20212 
20213 /* ============================================  CTIMER CTRL7 TMRB7IE0 [25..25]  ============================================= */
20214 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7IE0                                                     */
20215   CTIMER_CTRL7_TMRB7IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B7 from generating an interrupt
20216                                                      based on COMPR0.                                                          */
20217   CTIMER_CTRL7_TMRB7IE0_EN             = 1,     /*!< EN : Enable counter/timer B7 to generate an interrupt based
20218                                                      on COMPR0                                                                 */
20219 } CTIMER_CTRL7_TMRB7IE0_Enum;
20220 
20221 /* =============================================  CTIMER CTRL7 TMRB7FN [22..24]  ============================================= */
20222 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7FN                                                      */
20223   CTIMER_CTRL7_TMRB7FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
20224                                                      to CMPR0B7, stop.                                                         */
20225   CTIMER_CTRL7_TMRB7FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
20226                                                      pulses). Count to CMPR0B7, restart.                                       */
20227   CTIMER_CTRL7_TMRB7FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B7, assert,
20228                                                      count to CMPR1B7, deassert, stop.                                         */
20229   CTIMER_CTRL7_TMRB7FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B7, assert, count
20230                                                      to CMPR1B7, deassert, restart.                                            */
20231   CTIMER_CTRL7_TMRB7FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
20232   CTIMER_CTRL7_TMRB7FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
20233   CTIMER_CTRL7_TMRB7FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
20234   CTIMER_CTRL7_TMRB7FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
20235 } CTIMER_CTRL7_TMRB7FN_Enum;
20236 
20237 /* ============================================  CTIMER CTRL7 TMRB7CLK [17..21]  ============================================= */
20238 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7CLK                                                     */
20239   CTIMER_CTRL7_TMRB7CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
20240   CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
20241   CTIMER_CTRL7_TMRB7CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
20242   CTIMER_CTRL7_TMRB7CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
20243   CTIMER_CTRL7_TMRB7CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
20244   CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
20245   CTIMER_CTRL7_TMRB7CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
20246   CTIMER_CTRL7_TMRB7CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
20247   CTIMER_CTRL7_TMRB7CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
20248   CTIMER_CTRL7_TMRB7CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
20249   CTIMER_CTRL7_TMRB7CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
20250   CTIMER_CTRL7_TMRB7CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
20251   CTIMER_CTRL7_TMRB7CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
20252   CTIMER_CTRL7_TMRB7CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
20253   CTIMER_CTRL7_TMRB7CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
20254   CTIMER_CTRL7_TMRB7CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
20255                                                      available when MCU is in active mode)                                     */
20256   CTIMER_CTRL7_TMRB7CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
20257   CTIMER_CTRL7_TMRB7CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
20258   CTIMER_CTRL7_TMRB7CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
20259   CTIMER_CTRL7_TMRB7CLK_CTMRA7         = 20,    /*!< CTMRA7 : Clock source is CTIMERA7 OUT.                                    */
20260   CTIMER_CTRL7_TMRB7CLK_CTMRA2         = 21,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
20261   CTIMER_CTRL7_TMRB7CLK_CTMRB2         = 22,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
20262   CTIMER_CTRL7_TMRB7CLK_CTMRA0         = 23,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
20263   CTIMER_CTRL7_TMRB7CLK_CTMRB0         = 24,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
20264   CTIMER_CTRL7_TMRB7CLK_CTMRB1         = 25,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
20265   CTIMER_CTRL7_TMRB7CLK_CTMRB3         = 26,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
20266   CTIMER_CTRL7_TMRB7CLK_CTMRB4         = 27,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
20267   CTIMER_CTRL7_TMRB7CLK_CTMRB5         = 28,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
20268   CTIMER_CTRL7_TMRB7CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
20269   CTIMER_CTRL7_TMRB7CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
20270   CTIMER_CTRL7_TMRB7CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
20271 } CTIMER_CTRL7_TMRB7CLK_Enum;
20272 
20273 /* =============================================  CTIMER CTRL7 TMRB7EN [16..16]  ============================================= */
20274 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7EN                                                      */
20275   CTIMER_CTRL7_TMRB7EN_DIS             = 0,     /*!< DIS : Counter/Timer B7 Disable.                                           */
20276   CTIMER_CTRL7_TMRB7EN_EN              = 1,     /*!< EN : Counter/Timer B7 Enable.                                             */
20277 } CTIMER_CTRL7_TMRB7EN_Enum;
20278 
20279 /* ============================================  CTIMER CTRL7 TMRA7POL [12..12]  ============================================= */
20280 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7POL                                                     */
20281   CTIMER_CTRL7_TMRA7POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA7 pin is the same as the
20282                                                      timer output.                                                             */
20283   CTIMER_CTRL7_TMRA7POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA7 pin is the inverse of
20284                                                      the timer output.                                                         */
20285 } CTIMER_CTRL7_TMRA7POL_Enum;
20286 
20287 /* ============================================  CTIMER CTRL7 TMRA7CLR [11..11]  ============================================= */
20288 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7CLR                                                     */
20289   CTIMER_CTRL7_TMRA7CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A7 to run                                       */
20290   CTIMER_CTRL7_TMRA7CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A7 at 0x0000.                                 */
20291 } CTIMER_CTRL7_TMRA7CLR_Enum;
20292 
20293 /* ============================================  CTIMER CTRL7 TMRA7IE1 [10..10]  ============================================= */
20294 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7IE1                                                     */
20295   CTIMER_CTRL7_TMRA7IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A7 from generating an interrupt
20296                                                      based on COMPR1.                                                          */
20297   CTIMER_CTRL7_TMRA7IE1_EN             = 1,     /*!< EN : Enable counter/timer A7 to generate an interrupt based
20298                                                      on COMPR1.                                                                */
20299 } CTIMER_CTRL7_TMRA7IE1_Enum;
20300 
20301 /* =============================================  CTIMER CTRL7 TMRA7IE0 [9..9]  ============================================== */
20302 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7IE0                                                     */
20303   CTIMER_CTRL7_TMRA7IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A7 from generating an interrupt
20304                                                      based on COMPR0.                                                          */
20305   CTIMER_CTRL7_TMRA7IE0_EN             = 1,     /*!< EN : Enable counter/timer A7 to generate an interrupt based
20306                                                      on COMPR0.                                                                */
20307 } CTIMER_CTRL7_TMRA7IE0_Enum;
20308 
20309 /* ==============================================  CTIMER CTRL7 TMRA7FN [6..8]  ============================================== */
20310 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7FN                                                      */
20311   CTIMER_CTRL7_TMRA7FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
20312                                                      to CMPR0A7, stop.                                                         */
20313   CTIMER_CTRL7_TMRA7FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
20314                                                      pulses). Count to CMPR0A7, restart.                                       */
20315   CTIMER_CTRL7_TMRA7FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A7, assert,
20316                                                      count to CMPR1A7, deassert, stop.                                         */
20317   CTIMER_CTRL7_TMRA7FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A7, assert, count
20318                                                      to CMPR1A7, deassert, restart.                                            */
20319   CTIMER_CTRL7_TMRA7FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
20320   CTIMER_CTRL7_TMRA7FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
20321   CTIMER_CTRL7_TMRA7FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
20322   CTIMER_CTRL7_TMRA7FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
20323 } CTIMER_CTRL7_TMRA7FN_Enum;
20324 
20325 /* =============================================  CTIMER CTRL7 TMRA7CLK [1..5]  ============================================== */
20326 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7CLK                                                     */
20327   CTIMER_CTRL7_TMRA7CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
20328   CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
20329   CTIMER_CTRL7_TMRA7CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
20330   CTIMER_CTRL7_TMRA7CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
20331   CTIMER_CTRL7_TMRA7CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
20332   CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
20333   CTIMER_CTRL7_TMRA7CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
20334   CTIMER_CTRL7_TMRA7CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
20335   CTIMER_CTRL7_TMRA7CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
20336   CTIMER_CTRL7_TMRA7CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
20337   CTIMER_CTRL7_TMRA7CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
20338   CTIMER_CTRL7_TMRA7CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
20339   CTIMER_CTRL7_TMRA7CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
20340   CTIMER_CTRL7_TMRA7CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
20341   CTIMER_CTRL7_TMRA7CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
20342   CTIMER_CTRL7_TMRA7CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
20343                                                      available when MCU is in active mode)                                     */
20344   CTIMER_CTRL7_TMRA7CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
20345   CTIMER_CTRL7_TMRA7CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
20346   CTIMER_CTRL7_TMRA7CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
20347   CTIMER_CTRL7_TMRA7CLK_CTMRB7         = 20,    /*!< CTMRB7 : Clock source is CTIMERB7 OUT.                                    */
20348   CTIMER_CTRL7_TMRA7CLK_CTMRA2         = 21,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
20349   CTIMER_CTRL7_TMRA7CLK_CTMRB2         = 22,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
20350   CTIMER_CTRL7_TMRA7CLK_CTMRA0         = 23,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
20351   CTIMER_CTRL7_TMRA7CLK_CTMRB0         = 24,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
20352   CTIMER_CTRL7_TMRA7CLK_CTMRB1         = 25,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
20353   CTIMER_CTRL7_TMRA7CLK_CTMRB3         = 26,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
20354   CTIMER_CTRL7_TMRA7CLK_CTMRB4         = 27,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
20355   CTIMER_CTRL7_TMRA7CLK_CTMRB5         = 28,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
20356   CTIMER_CTRL7_TMRA7CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
20357   CTIMER_CTRL7_TMRA7CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
20358   CTIMER_CTRL7_TMRA7CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
20359 } CTIMER_CTRL7_TMRA7CLK_Enum;
20360 
20361 /* ==============================================  CTIMER CTRL7 TMRA7EN [0..0]  ============================================== */
20362 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7EN                                                      */
20363   CTIMER_CTRL7_TMRA7EN_DIS             = 0,     /*!< DIS : Counter/Timer A7 Disable.                                           */
20364   CTIMER_CTRL7_TMRA7EN_EN              = 1,     /*!< EN : Counter/Timer A7 Enable.                                             */
20365 } CTIMER_CTRL7_TMRA7EN_Enum;
20366 
20367 /* =======================================================  CMPRAUXA7  ======================================================= */
20368 /* =======================================================  CMPRAUXB7  ======================================================= */
20369 /* =========================================================  AUX7  ========================================================== */
20370 /* ============================================  CTIMER AUX7 TMRB7EN23 [30..30]  ============================================= */
20371 typedef enum {                                  /*!< CTIMER_AUX7_TMRB7EN23                                                     */
20372   CTIMER_AUX7_TMRB7EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
20373   CTIMER_AUX7_TMRB7EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
20374 } CTIMER_AUX7_TMRB7EN23_Enum;
20375 
20376 /* ============================================  CTIMER AUX7 TMRB7POL23 [29..29]  ============================================ */
20377 typedef enum {                                  /*!< CTIMER_AUX7_TMRB7POL23                                                    */
20378   CTIMER_AUX7_TMRB7POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
20379   CTIMER_AUX7_TMRB7POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
20380 } CTIMER_AUX7_TMRB7POL23_Enum;
20381 
20382 /* ============================================  CTIMER AUX7 TMRB7TINV [28..28]  ============================================= */
20383 typedef enum {                                  /*!< CTIMER_AUX7_TMRB7TINV                                                     */
20384   CTIMER_AUX7_TMRB7TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
20385   CTIMER_AUX7_TMRB7TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
20386 } CTIMER_AUX7_TMRB7TINV_Enum;
20387 
20388 /* ===========================================  CTIMER AUX7 TMRB7NOSYNC [27..27]  ============================================ */
20389 typedef enum {                                  /*!< CTIMER_AUX7_TMRB7NOSYNC                                                   */
20390   CTIMER_AUX7_TMRB7NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
20391   CTIMER_AUX7_TMRB7NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
20392 } CTIMER_AUX7_TMRB7NOSYNC_Enum;
20393 
20394 /* ============================================  CTIMER AUX7 TMRB7TRIG [23..26]  ============================================= */
20395 typedef enum {                                  /*!< CTIMER_AUX7_TMRB7TRIG                                                     */
20396   CTIMER_AUX7_TMRB7TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
20397   CTIMER_AUX7_TMRB7TRIG_A7OUT          = 1,     /*!< A7OUT : Trigger source is CTIMERA7 OUT.                                   */
20398   CTIMER_AUX7_TMRB7TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
20399   CTIMER_AUX7_TMRB7TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
20400   CTIMER_AUX7_TMRB7TRIG_A5OUT          = 4,     /*!< A5OUT : Trigger source is CTIMERA5 OUT.                                   */
20401   CTIMER_AUX7_TMRB7TRIG_B5OUT          = 5,     /*!< B5OUT : Trigger source is CTIMERB5 OUT.                                   */
20402   CTIMER_AUX7_TMRB7TRIG_A2OUT          = 6,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
20403   CTIMER_AUX7_TMRB7TRIG_B2OUT          = 7,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
20404   CTIMER_AUX7_TMRB7TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
20405   CTIMER_AUX7_TMRB7TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
20406   CTIMER_AUX7_TMRB7TRIG_A2OUT2         = 10,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
20407   CTIMER_AUX7_TMRB7TRIG_B2OUT2         = 11,    /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2.                                 */
20408   CTIMER_AUX7_TMRB7TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
20409   CTIMER_AUX7_TMRB7TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
20410   CTIMER_AUX7_TMRB7TRIG_B1OUT2DUAL     = 14,    /*!< B1OUT2DUAL : Trigger source is CTIMERB1 OUT2, dual edge.                  */
20411   CTIMER_AUX7_TMRB7TRIG_A1OUT2DUAL     = 15,    /*!< A1OUT2DUAL : Trigger source is CTIMERA1 OUT2, dual edge.                  */
20412 } CTIMER_AUX7_TMRB7TRIG_Enum;
20413 
20414 /* ============================================  CTIMER AUX7 TMRA7EN23 [14..14]  ============================================= */
20415 typedef enum {                                  /*!< CTIMER_AUX7_TMRA7EN23                                                     */
20416   CTIMER_AUX7_TMRA7EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
20417   CTIMER_AUX7_TMRA7EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
20418 } CTIMER_AUX7_TMRA7EN23_Enum;
20419 
20420 /* ============================================  CTIMER AUX7 TMRA7POL23 [13..13]  ============================================ */
20421 typedef enum {                                  /*!< CTIMER_AUX7_TMRA7POL23                                                    */
20422   CTIMER_AUX7_TMRA7POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
20423   CTIMER_AUX7_TMRA7POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
20424 } CTIMER_AUX7_TMRA7POL23_Enum;
20425 
20426 /* ============================================  CTIMER AUX7 TMRA7TINV [12..12]  ============================================= */
20427 typedef enum {                                  /*!< CTIMER_AUX7_TMRA7TINV                                                     */
20428   CTIMER_AUX7_TMRA7TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
20429   CTIMER_AUX7_TMRA7TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
20430 } CTIMER_AUX7_TMRA7TINV_Enum;
20431 
20432 /* ===========================================  CTIMER AUX7 TMRA7NOSYNC [11..11]  ============================================ */
20433 typedef enum {                                  /*!< CTIMER_AUX7_TMRA7NOSYNC                                                   */
20434   CTIMER_AUX7_TMRA7NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
20435   CTIMER_AUX7_TMRA7NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
20436 } CTIMER_AUX7_TMRA7NOSYNC_Enum;
20437 
20438 /* =============================================  CTIMER AUX7 TMRA7TRIG [7..10]  ============================================= */
20439 typedef enum {                                  /*!< CTIMER_AUX7_TMRA7TRIG                                                     */
20440   CTIMER_AUX7_TMRA7TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
20441   CTIMER_AUX7_TMRA7TRIG_B7OUT          = 1,     /*!< B7OUT : Trigger source is CTIMERB7 OUT.                                   */
20442   CTIMER_AUX7_TMRA7TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
20443   CTIMER_AUX7_TMRA7TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
20444   CTIMER_AUX7_TMRA7TRIG_A1OUT          = 4,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
20445   CTIMER_AUX7_TMRA7TRIG_B1OUT          = 5,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
20446   CTIMER_AUX7_TMRA7TRIG_A4OUT          = 6,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
20447   CTIMER_AUX7_TMRA7TRIG_B4OUT          = 7,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
20448   CTIMER_AUX7_TMRA7TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
20449   CTIMER_AUX7_TMRA7TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
20450   CTIMER_AUX7_TMRA7TRIG_A2OUT2         = 10,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
20451   CTIMER_AUX7_TMRA7TRIG_B2OUT2         = 11,    /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2.                                 */
20452   CTIMER_AUX7_TMRA7TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
20453   CTIMER_AUX7_TMRA7TRIG_A5OUT2DUAL     = 13,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
20454   CTIMER_AUX7_TMRA7TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
20455   CTIMER_AUX7_TMRA7TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
20456 } CTIMER_AUX7_TMRA7TRIG_Enum;
20457 
20458 /* ========================================================  GLOBEN  ========================================================= */
20459 /* ==============================================  CTIMER GLOBEN ENB7 [15..15]  ============================================== */
20460 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB7                                                        */
20461   CTIMER_GLOBEN_ENB7_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20462   CTIMER_GLOBEN_ENB7_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20463 } CTIMER_GLOBEN_ENB7_Enum;
20464 
20465 /* ==============================================  CTIMER GLOBEN ENA7 [14..14]  ============================================== */
20466 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA7                                                        */
20467   CTIMER_GLOBEN_ENA7_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20468   CTIMER_GLOBEN_ENA7_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20469 } CTIMER_GLOBEN_ENA7_Enum;
20470 
20471 /* ==============================================  CTIMER GLOBEN ENB6 [13..13]  ============================================== */
20472 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB6                                                        */
20473   CTIMER_GLOBEN_ENB6_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20474   CTIMER_GLOBEN_ENB6_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20475 } CTIMER_GLOBEN_ENB6_Enum;
20476 
20477 /* ==============================================  CTIMER GLOBEN ENA6 [12..12]  ============================================== */
20478 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA6                                                        */
20479   CTIMER_GLOBEN_ENA6_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20480   CTIMER_GLOBEN_ENA6_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20481 } CTIMER_GLOBEN_ENA6_Enum;
20482 
20483 /* ==============================================  CTIMER GLOBEN ENB5 [11..11]  ============================================== */
20484 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB5                                                        */
20485   CTIMER_GLOBEN_ENB5_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20486   CTIMER_GLOBEN_ENB5_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20487 } CTIMER_GLOBEN_ENB5_Enum;
20488 
20489 /* ==============================================  CTIMER GLOBEN ENA5 [10..10]  ============================================== */
20490 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA5                                                        */
20491   CTIMER_GLOBEN_ENA5_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20492   CTIMER_GLOBEN_ENA5_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20493 } CTIMER_GLOBEN_ENA5_Enum;
20494 
20495 /* ===============================================  CTIMER GLOBEN ENB4 [9..9]  =============================================== */
20496 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB4                                                        */
20497   CTIMER_GLOBEN_ENB4_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20498   CTIMER_GLOBEN_ENB4_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20499 } CTIMER_GLOBEN_ENB4_Enum;
20500 
20501 /* ===============================================  CTIMER GLOBEN ENA4 [8..8]  =============================================== */
20502 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA4                                                        */
20503   CTIMER_GLOBEN_ENA4_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20504   CTIMER_GLOBEN_ENA4_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20505 } CTIMER_GLOBEN_ENA4_Enum;
20506 
20507 /* ===============================================  CTIMER GLOBEN ENB3 [7..7]  =============================================== */
20508 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB3                                                        */
20509   CTIMER_GLOBEN_ENB3_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20510   CTIMER_GLOBEN_ENB3_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20511 } CTIMER_GLOBEN_ENB3_Enum;
20512 
20513 /* ===============================================  CTIMER GLOBEN ENA3 [6..6]  =============================================== */
20514 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA3                                                        */
20515   CTIMER_GLOBEN_ENA3_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20516   CTIMER_GLOBEN_ENA3_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20517 } CTIMER_GLOBEN_ENA3_Enum;
20518 
20519 /* ===============================================  CTIMER GLOBEN ENB2 [5..5]  =============================================== */
20520 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB2                                                        */
20521   CTIMER_GLOBEN_ENB2_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20522   CTIMER_GLOBEN_ENB2_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20523 } CTIMER_GLOBEN_ENB2_Enum;
20524 
20525 /* ===============================================  CTIMER GLOBEN ENA2 [4..4]  =============================================== */
20526 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA2                                                        */
20527   CTIMER_GLOBEN_ENA2_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20528   CTIMER_GLOBEN_ENA2_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20529 } CTIMER_GLOBEN_ENA2_Enum;
20530 
20531 /* ===============================================  CTIMER GLOBEN ENB1 [3..3]  =============================================== */
20532 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB1                                                        */
20533   CTIMER_GLOBEN_ENB1_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20534   CTIMER_GLOBEN_ENB1_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20535 } CTIMER_GLOBEN_ENB1_Enum;
20536 
20537 /* ===============================================  CTIMER GLOBEN ENA1 [2..2]  =============================================== */
20538 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA1                                                        */
20539   CTIMER_GLOBEN_ENA1_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20540   CTIMER_GLOBEN_ENA1_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20541 } CTIMER_GLOBEN_ENA1_Enum;
20542 
20543 /* ===============================================  CTIMER GLOBEN ENB0 [1..1]  =============================================== */
20544 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB0                                                        */
20545   CTIMER_GLOBEN_ENB0_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20546   CTIMER_GLOBEN_ENB0_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20547 } CTIMER_GLOBEN_ENB0_Enum;
20548 
20549 /* ===============================================  CTIMER GLOBEN ENA0 [0..0]  =============================================== */
20550 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA0                                                        */
20551   CTIMER_GLOBEN_ENA0_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
20552   CTIMER_GLOBEN_ENA0_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
20553 } CTIMER_GLOBEN_ENA0_Enum;
20554 
20555 /* ========================================================  OUTCFG0  ======================================================== */
20556 /* =============================================  CTIMER OUTCFG0 CFG9 [28..30]  ============================================== */
20557 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG9                                                       */
20558   CTIMER_OUTCFG0_CFG9_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20559   CTIMER_OUTCFG0_CFG9_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20560   CTIMER_OUTCFG0_CFG9_B0OUT            = 5,     /*!< B0OUT : Output is B0OUT.                                                  */
20561   CTIMER_OUTCFG0_CFG9_A4OUT            = 4,     /*!< A4OUT : Output is A4OUT.                                                  */
20562   CTIMER_OUTCFG0_CFG9_A2OUT            = 3,     /*!< A2OUT : Output is A2OUT.                                                  */
20563   CTIMER_OUTCFG0_CFG9_A2OUT2           = 2,     /*!< A2OUT2 : Output is A2OUT2                                                 */
20564   CTIMER_OUTCFG0_CFG9_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
20565   CTIMER_OUTCFG0_CFG9_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
20566 } CTIMER_OUTCFG0_CFG9_Enum;
20567 
20568 /* =============================================  CTIMER OUTCFG0 CFG8 [25..27]  ============================================== */
20569 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG8                                                       */
20570   CTIMER_OUTCFG0_CFG8_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20571   CTIMER_OUTCFG0_CFG8_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20572   CTIMER_OUTCFG0_CFG8_B6OUT            = 5,     /*!< B6OUT : Output is B6OUT.                                                  */
20573   CTIMER_OUTCFG0_CFG8_A4OUT2           = 4,     /*!< A4OUT2 : Output is A4OUT2.                                                */
20574   CTIMER_OUTCFG0_CFG8_A3OUT2           = 3,     /*!< A3OUT2 : Output is A3OUT.                                                 */
20575   CTIMER_OUTCFG0_CFG8_A2OUT            = 2,     /*!< A2OUT : Output is A2OUT                                                   */
20576   CTIMER_OUTCFG0_CFG8_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
20577   CTIMER_OUTCFG0_CFG8_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
20578 } CTIMER_OUTCFG0_CFG8_Enum;
20579 
20580 /* =============================================  CTIMER OUTCFG0 CFG7 [22..24]  ============================================== */
20581 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG7                                                       */
20582   CTIMER_OUTCFG0_CFG7_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20583   CTIMER_OUTCFG0_CFG7_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20584   CTIMER_OUTCFG0_CFG7_A7OUT            = 5,     /*!< A7OUT : Output is A7OUT.                                                  */
20585   CTIMER_OUTCFG0_CFG7_B5OUT            = 4,     /*!< B5OUT : Output is B5OUT.                                                  */
20586   CTIMER_OUTCFG0_CFG7_B1OUT            = 3,     /*!< B1OUT : Output is B1OUT.                                                  */
20587   CTIMER_OUTCFG0_CFG7_B1OUT2           = 2,     /*!< B1OUT2 : Output is B1OUT2                                                 */
20588   CTIMER_OUTCFG0_CFG7_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
20589   CTIMER_OUTCFG0_CFG7_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
20590 } CTIMER_OUTCFG0_CFG7_Enum;
20591 
20592 /* =============================================  CTIMER OUTCFG0 CFG6 [19..21]  ============================================== */
20593 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG6                                                       */
20594   CTIMER_OUTCFG0_CFG6_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20595   CTIMER_OUTCFG0_CFG6_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20596   CTIMER_OUTCFG0_CFG6_B7OUT            = 5,     /*!< B7OUT : Output is B7OUT.                                                  */
20597   CTIMER_OUTCFG0_CFG6_B5OUT2           = 4,     /*!< B5OUT2 : Output is B5OUT2.                                                */
20598   CTIMER_OUTCFG0_CFG6_A1OUT            = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
20599   CTIMER_OUTCFG0_CFG6_B1OUT            = 2,     /*!< B1OUT : Output is B1OUT                                                   */
20600   CTIMER_OUTCFG0_CFG6_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
20601   CTIMER_OUTCFG0_CFG6_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
20602 } CTIMER_OUTCFG0_CFG6_Enum;
20603 
20604 /* =============================================  CTIMER OUTCFG0 CFG5 [16..18]  ============================================== */
20605 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG5                                                       */
20606   CTIMER_OUTCFG0_CFG5_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20607   CTIMER_OUTCFG0_CFG5_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20608   CTIMER_OUTCFG0_CFG5_A7OUT            = 5,     /*!< A7OUT : Output is A7OUT.                                                  */
20609   CTIMER_OUTCFG0_CFG5_B6OUT            = 4,     /*!< B6OUT : Output is A5OUT.                                                  */
20610   CTIMER_OUTCFG0_CFG5_A1OUT            = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
20611   CTIMER_OUTCFG0_CFG5_A1OUT2           = 2,     /*!< A1OUT2 : Output is A1OUT2                                                 */
20612   CTIMER_OUTCFG0_CFG5_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
20613   CTIMER_OUTCFG0_CFG5_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
20614 } CTIMER_OUTCFG0_CFG5_Enum;
20615 
20616 /* =============================================  CTIMER OUTCFG0 CFG4 [12..14]  ============================================== */
20617 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG4                                                       */
20618   CTIMER_OUTCFG0_CFG4_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20619   CTIMER_OUTCFG0_CFG4_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20620   CTIMER_OUTCFG0_CFG4_B5OUT            = 5,     /*!< B5OUT : Output is B5OUT.                                                  */
20621   CTIMER_OUTCFG0_CFG4_A5OUT2           = 4,     /*!< A5OUT2 : Output is A5OUT2.                                                */
20622   CTIMER_OUTCFG0_CFG4_A2OUT2           = 3,     /*!< A2OUT2 : Output is A2OUT2.                                                */
20623   CTIMER_OUTCFG0_CFG4_A1OUT            = 2,     /*!< A1OUT : Output is A1OUT                                                   */
20624   CTIMER_OUTCFG0_CFG4_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
20625   CTIMER_OUTCFG0_CFG4_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
20626 } CTIMER_OUTCFG0_CFG4_Enum;
20627 
20628 /* ==============================================  CTIMER OUTCFG0 CFG3 [9..11]  ============================================== */
20629 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG3                                                       */
20630   CTIMER_OUTCFG0_CFG3_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20631   CTIMER_OUTCFG0_CFG3_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20632   CTIMER_OUTCFG0_CFG3_A6OUT            = 5,     /*!< A6OUT : Output is A6OUT.                                                  */
20633   CTIMER_OUTCFG0_CFG3_A1OUT            = 4,     /*!< A1OUT : Output is A1OUT.                                                  */
20634   CTIMER_OUTCFG0_CFG3_B0OUT            = 3,     /*!< B0OUT : Output is B0OUT.                                                  */
20635   CTIMER_OUTCFG0_CFG3_B0OUT2           = 2,     /*!< B0OUT2 : Output is B0OUT2                                                 */
20636   CTIMER_OUTCFG0_CFG3_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
20637   CTIMER_OUTCFG0_CFG3_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
20638 } CTIMER_OUTCFG0_CFG3_Enum;
20639 
20640 /* ==============================================  CTIMER OUTCFG0 CFG2 [6..8]  =============================================== */
20641 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG2                                                       */
20642   CTIMER_OUTCFG0_CFG2_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20643   CTIMER_OUTCFG0_CFG2_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20644   CTIMER_OUTCFG0_CFG2_A7OUT            = 5,     /*!< A7OUT : Output is A7OUT.                                                  */
20645   CTIMER_OUTCFG0_CFG2_B6OUT2           = 4,     /*!< B6OUT2 : Output is B6OUT2.                                                */
20646   CTIMER_OUTCFG0_CFG2_B1OUT2           = 3,     /*!< B1OUT2 : Output is B1OUT2.                                                */
20647   CTIMER_OUTCFG0_CFG2_B0OUT            = 2,     /*!< B0OUT : Output is B0OUT                                                   */
20648   CTIMER_OUTCFG0_CFG2_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
20649   CTIMER_OUTCFG0_CFG2_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
20650 } CTIMER_OUTCFG0_CFG2_Enum;
20651 
20652 /* ==============================================  CTIMER OUTCFG0 CFG1 [3..5]  =============================================== */
20653 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG1                                                       */
20654   CTIMER_OUTCFG0_CFG1_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20655   CTIMER_OUTCFG0_CFG1_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20656   CTIMER_OUTCFG0_CFG1_B7OUT2           = 5,     /*!< B7OUT2 : Output is B7OUT2.                                                */
20657   CTIMER_OUTCFG0_CFG1_A5OUT            = 4,     /*!< A5OUT : Output is A5OUT.                                                  */
20658   CTIMER_OUTCFG0_CFG1_A0OUT            = 3,     /*!< A0OUT : Output is A0OUT.                                                  */
20659   CTIMER_OUTCFG0_CFG1_A0OUT2           = 2,     /*!< A0OUT2 : Output is A0OUT2                                                 */
20660   CTIMER_OUTCFG0_CFG1_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
20661   CTIMER_OUTCFG0_CFG1_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
20662 } CTIMER_OUTCFG0_CFG1_Enum;
20663 
20664 /* ==============================================  CTIMER OUTCFG0 CFG0 [0..2]  =============================================== */
20665 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG0                                                       */
20666   CTIMER_OUTCFG0_CFG0_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20667   CTIMER_OUTCFG0_CFG0_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20668   CTIMER_OUTCFG0_CFG0_A6OUT            = 5,     /*!< A6OUT : Output is A6OUT.                                                  */
20669   CTIMER_OUTCFG0_CFG0_A5OUT2           = 4,     /*!< A5OUT2 : Output is A5OUT2.                                                */
20670   CTIMER_OUTCFG0_CFG0_B2OUT2           = 3,     /*!< B2OUT2 : Output is B2OUT2.                                                */
20671   CTIMER_OUTCFG0_CFG0_A0OUT            = 2,     /*!< A0OUT : Output is A0OUT                                                   */
20672   CTIMER_OUTCFG0_CFG0_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
20673   CTIMER_OUTCFG0_CFG0_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
20674 } CTIMER_OUTCFG0_CFG0_Enum;
20675 
20676 /* ========================================================  OUTCFG1  ======================================================== */
20677 /* =============================================  CTIMER OUTCFG1 CFG19 [28..30]  ============================================= */
20678 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG19                                                      */
20679   CTIMER_OUTCFG1_CFG19_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20680   CTIMER_OUTCFG1_CFG19_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20681   CTIMER_OUTCFG1_CFG19_B1OUT2          = 5,     /*!< B1OUT2 : Output is B1OUT2.                                                */
20682   CTIMER_OUTCFG1_CFG19_B4OUT           = 4,     /*!< B4OUT : Output is B4OUT.                                                  */
20683   CTIMER_OUTCFG1_CFG19_A2OUT           = 3,     /*!< A2OUT : Output is A2OUT.                                                  */
20684   CTIMER_OUTCFG1_CFG19_B4OUT2          = 2,     /*!< B4OUT2 : Output is B4OUT2                                                 */
20685   CTIMER_OUTCFG1_CFG19_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20686   CTIMER_OUTCFG1_CFG19_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20687 } CTIMER_OUTCFG1_CFG19_Enum;
20688 
20689 /* =============================================  CTIMER OUTCFG1 CFG18 [25..27]  ============================================= */
20690 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG18                                                      */
20691   CTIMER_OUTCFG1_CFG18_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20692   CTIMER_OUTCFG1_CFG18_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20693   CTIMER_OUTCFG1_CFG18_A3OUT2          = 5,     /*!< A3OUT2 : Output is A3OUT2.                                                */
20694   CTIMER_OUTCFG1_CFG18_A0OUT           = 4,     /*!< A0OUT : Output is A0OUT.                                                  */
20695   CTIMER_OUTCFG1_CFG18_B0OUT           = 3,     /*!< B0OUT : Output is B0OUT.                                                  */
20696   CTIMER_OUTCFG1_CFG18_B4OUT           = 2,     /*!< B4OUT : Output is B4OUT                                                   */
20697   CTIMER_OUTCFG1_CFG18_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20698   CTIMER_OUTCFG1_CFG18_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20699 } CTIMER_OUTCFG1_CFG18_Enum;
20700 
20701 /* =============================================  CTIMER OUTCFG1 CFG17 [22..24]  ============================================= */
20702 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG17                                                      */
20703   CTIMER_OUTCFG1_CFG17_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20704   CTIMER_OUTCFG1_CFG17_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20705   CTIMER_OUTCFG1_CFG17_A1OUT2          = 5,     /*!< A1OUT2 : Output is A1OUT2.                                                */
20706   CTIMER_OUTCFG1_CFG17_A4OUT           = 4,     /*!< A4OUT : Output is A4OUT.                                                  */
20707   CTIMER_OUTCFG1_CFG17_B7OUT           = 3,     /*!< B7OUT : Output is B7OUT.                                                  */
20708   CTIMER_OUTCFG1_CFG17_A4OUT2          = 2,     /*!< A4OUT2 : Output is A4OUT2                                                 */
20709   CTIMER_OUTCFG1_CFG17_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20710   CTIMER_OUTCFG1_CFG17_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20711 } CTIMER_OUTCFG1_CFG17_Enum;
20712 
20713 /* =============================================  CTIMER OUTCFG1 CFG16 [19..21]  ============================================= */
20714 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG16                                                      */
20715   CTIMER_OUTCFG1_CFG16_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20716   CTIMER_OUTCFG1_CFG16_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20717   CTIMER_OUTCFG1_CFG16_B3OUT2          = 5,     /*!< B3OUT2 : Output is B3OUT2.                                                */
20718   CTIMER_OUTCFG1_CFG16_A0OUT2          = 4,     /*!< A0OUT2 : Output is A0OUT2.                                                */
20719   CTIMER_OUTCFG1_CFG16_A0OUT           = 3,     /*!< A0OUT : Output is A0OUT.                                                  */
20720   CTIMER_OUTCFG1_CFG16_A4OUT           = 2,     /*!< A4OUT : Output is A4OUT                                                   */
20721   CTIMER_OUTCFG1_CFG16_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20722   CTIMER_OUTCFG1_CFG16_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20723 } CTIMER_OUTCFG1_CFG16_Enum;
20724 
20725 /* =============================================  CTIMER OUTCFG1 CFG15 [16..18]  ============================================= */
20726 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG15                                                      */
20727   CTIMER_OUTCFG1_CFG15_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20728   CTIMER_OUTCFG1_CFG15_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20729   CTIMER_OUTCFG1_CFG15_A4OUT2          = 5,     /*!< A4OUT2 : Output is A4OUT2.                                                */
20730   CTIMER_OUTCFG1_CFG15_A7OUT           = 4,     /*!< A7OUT : Output is A7OUT.                                                  */
20731   CTIMER_OUTCFG1_CFG15_B3OUT           = 3,     /*!< B3OUT : Output is B3OUT.                                                  */
20732   CTIMER_OUTCFG1_CFG15_B3OUT2          = 2,     /*!< B3OUT2 : Output is B3OUT2                                                 */
20733   CTIMER_OUTCFG1_CFG15_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20734   CTIMER_OUTCFG1_CFG15_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20735 } CTIMER_OUTCFG1_CFG15_Enum;
20736 
20737 /* =============================================  CTIMER OUTCFG1 CFG14 [12..14]  ============================================= */
20738 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG14                                                      */
20739   CTIMER_OUTCFG1_CFG14_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20740   CTIMER_OUTCFG1_CFG14_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20741   CTIMER_OUTCFG1_CFG14_A7OUT           = 5,     /*!< A7OUT : Output is A7OUT.                                                  */
20742   CTIMER_OUTCFG1_CFG14_B7OUT2          = 4,     /*!< B7OUT2 : Output is B7OUT2.                                                */
20743   CTIMER_OUTCFG1_CFG14_B1OUT           = 3,     /*!< B1OUT : Output is B1OUT.                                                  */
20744   CTIMER_OUTCFG1_CFG14_B3OUT           = 2,     /*!< B3OUT : Output is B3OUT                                                   */
20745   CTIMER_OUTCFG1_CFG14_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20746   CTIMER_OUTCFG1_CFG14_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20747 } CTIMER_OUTCFG1_CFG14_Enum;
20748 
20749 /* =============================================  CTIMER OUTCFG1 CFG13 [9..11]  ============================================== */
20750 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG13                                                      */
20751   CTIMER_OUTCFG1_CFG13_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20752   CTIMER_OUTCFG1_CFG13_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20753   CTIMER_OUTCFG1_CFG13_B4OUT2          = 5,     /*!< B4OUT2 : Output is B4OUT2.                                                */
20754   CTIMER_OUTCFG1_CFG13_A6OUT           = 4,     /*!< A6OUT : Output is A6OUT.                                                  */
20755   CTIMER_OUTCFG1_CFG13_A3OUT           = 3,     /*!< A3OUT : Output is A3OUT.                                                  */
20756   CTIMER_OUTCFG1_CFG13_A3OUT2          = 2,     /*!< A3OUT2 : Output is A3OUT2                                                 */
20757   CTIMER_OUTCFG1_CFG13_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20758   CTIMER_OUTCFG1_CFG13_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20759 } CTIMER_OUTCFG1_CFG13_Enum;
20760 
20761 /* ==============================================  CTIMER OUTCFG1 CFG12 [6..8]  ============================================== */
20762 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG12                                                      */
20763   CTIMER_OUTCFG1_CFG12_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20764   CTIMER_OUTCFG1_CFG12_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20765   CTIMER_OUTCFG1_CFG12_B6OUT2          = 5,     /*!< B6OUT2 : Output is B6OUT2.                                                */
20766   CTIMER_OUTCFG1_CFG12_B0OUT2          = 4,     /*!< B0OUT2 : Output is B0OUT2.                                                */
20767   CTIMER_OUTCFG1_CFG12_B1OUT           = 3,     /*!< B1OUT : Output is B1OUT.                                                  */
20768   CTIMER_OUTCFG1_CFG12_A3OUT           = 2,     /*!< A3OUT : Output is A3OUT                                                   */
20769   CTIMER_OUTCFG1_CFG12_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20770   CTIMER_OUTCFG1_CFG12_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20771 } CTIMER_OUTCFG1_CFG12_Enum;
20772 
20773 /* ==============================================  CTIMER OUTCFG1 CFG11 [3..5]  ============================================== */
20774 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG11                                                      */
20775   CTIMER_OUTCFG1_CFG11_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20776   CTIMER_OUTCFG1_CFG11_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20777   CTIMER_OUTCFG1_CFG11_B5OUT2          = 5,     /*!< B5OUT2 : Output is B5OUT2.                                                */
20778   CTIMER_OUTCFG1_CFG11_B4OUT           = 4,     /*!< B4OUT : Output is B4OUT.                                                  */
20779   CTIMER_OUTCFG1_CFG11_B2OUT           = 3,     /*!< B2OUT : Output is B2OUT.                                                  */
20780   CTIMER_OUTCFG1_CFG11_B2OUT2          = 2,     /*!< B2OUT2 : Output is B2OUT2                                                 */
20781   CTIMER_OUTCFG1_CFG11_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20782   CTIMER_OUTCFG1_CFG11_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20783 } CTIMER_OUTCFG1_CFG11_Enum;
20784 
20785 /* ==============================================  CTIMER OUTCFG1 CFG10 [0..2]  ============================================== */
20786 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG10                                                      */
20787   CTIMER_OUTCFG1_CFG10_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20788   CTIMER_OUTCFG1_CFG10_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20789   CTIMER_OUTCFG1_CFG10_A6OUT           = 5,     /*!< A6OUT : Output is A6OUT.                                                  */
20790   CTIMER_OUTCFG1_CFG10_B4OUT2          = 4,     /*!< B4OUT2 : Output is B4OUT2.                                                */
20791   CTIMER_OUTCFG1_CFG10_B3OUT2          = 3,     /*!< B3OUT2 : Output is B3OUT2.                                                */
20792   CTIMER_OUTCFG1_CFG10_B2OUT           = 2,     /*!< B2OUT : Output is B2OUT                                                   */
20793   CTIMER_OUTCFG1_CFG10_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20794   CTIMER_OUTCFG1_CFG10_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20795 } CTIMER_OUTCFG1_CFG10_Enum;
20796 
20797 /* ========================================================  OUTCFG2  ======================================================== */
20798 /* =============================================  CTIMER OUTCFG2 CFG29 [28..30]  ============================================= */
20799 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG29                                                      */
20800   CTIMER_OUTCFG2_CFG29_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20801   CTIMER_OUTCFG2_CFG29_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20802   CTIMER_OUTCFG2_CFG29_A3OUT2          = 5,     /*!< A3OUT2 : Output is A3OUT2.                                                */
20803   CTIMER_OUTCFG2_CFG29_A7OUT           = 4,     /*!< A7OUT : Output is A7OUT.                                                  */
20804   CTIMER_OUTCFG2_CFG29_A1OUT           = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
20805   CTIMER_OUTCFG2_CFG29_B5OUT2          = 2,     /*!< B5OUT2 : Output is B5OUT2                                                 */
20806   CTIMER_OUTCFG2_CFG29_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20807   CTIMER_OUTCFG2_CFG29_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20808 } CTIMER_OUTCFG2_CFG29_Enum;
20809 
20810 /* =============================================  CTIMER OUTCFG2 CFG28 [25..27]  ============================================= */
20811 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG28                                                      */
20812   CTIMER_OUTCFG2_CFG28_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20813   CTIMER_OUTCFG2_CFG28_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20814   CTIMER_OUTCFG2_CFG28_B0OUT2          = 5,     /*!< B0OUT2 : Output is B0OUT2.                                                */
20815   CTIMER_OUTCFG2_CFG28_A5OUT2          = 4,     /*!< A5OUT2 : Output is A5OUT2.                                                */
20816   CTIMER_OUTCFG2_CFG28_A3OUT           = 3,     /*!< A3OUT : Output is A3OUT.                                                  */
20817   CTIMER_OUTCFG2_CFG28_A7OUT           = 2,     /*!< A7OUT : Output is A7OUT                                                   */
20818   CTIMER_OUTCFG2_CFG28_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20819   CTIMER_OUTCFG2_CFG28_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20820 } CTIMER_OUTCFG2_CFG28_Enum;
20821 
20822 /* =============================================  CTIMER OUTCFG2 CFG27 [22..24]  ============================================= */
20823 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG27                                                      */
20824   CTIMER_OUTCFG2_CFG27_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20825   CTIMER_OUTCFG2_CFG27_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20826   CTIMER_OUTCFG2_CFG27_B2OUT2          = 5,     /*!< B2OUT2 : Output is B2OUT2.                                                */
20827   CTIMER_OUTCFG2_CFG27_B6OUT           = 4,     /*!< B6OUT : Output is B6OUT.                                                  */
20828   CTIMER_OUTCFG2_CFG27_A1OUT           = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
20829   CTIMER_OUTCFG2_CFG27_B6OUT2          = 2,     /*!< B6OUT2 : Output is B6OUT2                                                 */
20830   CTIMER_OUTCFG2_CFG27_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20831   CTIMER_OUTCFG2_CFG27_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20832 } CTIMER_OUTCFG2_CFG27_Enum;
20833 
20834 /* =============================================  CTIMER OUTCFG2 CFG26 [19..21]  ============================================= */
20835 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG26                                                      */
20836   CTIMER_OUTCFG2_CFG26_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20837   CTIMER_OUTCFG2_CFG26_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20838   CTIMER_OUTCFG2_CFG26_A1OUT2          = 5,     /*!< A1OUT2 : Output is A1OUT2.                                                */
20839   CTIMER_OUTCFG2_CFG26_A5OUT           = 4,     /*!< A5OUT : Output is A5OUT.                                                  */
20840   CTIMER_OUTCFG2_CFG26_B2OUT           = 3,     /*!< B2OUT : Output is B2OUT.                                                  */
20841   CTIMER_OUTCFG2_CFG26_B6OUT           = 2,     /*!< B6OUT : Output is B6OUT                                                   */
20842   CTIMER_OUTCFG2_CFG26_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20843   CTIMER_OUTCFG2_CFG26_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20844 } CTIMER_OUTCFG2_CFG26_Enum;
20845 
20846 /* =============================================  CTIMER OUTCFG2 CFG25 [16..18]  ============================================= */
20847 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG25                                                      */
20848   CTIMER_OUTCFG2_CFG25_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20849   CTIMER_OUTCFG2_CFG25_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20850   CTIMER_OUTCFG2_CFG25_A2OUT2          = 5,     /*!< A2OUT2 : Output is A2OUT2.                                                */
20851   CTIMER_OUTCFG2_CFG25_A6OUT           = 4,     /*!< A6OUT : Output is A6OUT.                                                  */
20852   CTIMER_OUTCFG2_CFG25_B2OUT           = 3,     /*!< B2OUT : Output is B2OUT.                                                  */
20853   CTIMER_OUTCFG2_CFG25_B4OUT2          = 2,     /*!< B4OUT2 : Output is B4OUT2                                                 */
20854   CTIMER_OUTCFG2_CFG25_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20855   CTIMER_OUTCFG2_CFG25_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20856 } CTIMER_OUTCFG2_CFG25_Enum;
20857 
20858 /* =============================================  CTIMER OUTCFG2 CFG24 [12..14]  ============================================= */
20859 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG24                                                      */
20860   CTIMER_OUTCFG2_CFG24_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20861   CTIMER_OUTCFG2_CFG24_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20862   CTIMER_OUTCFG2_CFG24_B1OUT2          = 5,     /*!< B1OUT2 : Output is B1OUT2.                                                */
20863   CTIMER_OUTCFG2_CFG24_A1OUT           = 4,     /*!< A1OUT : Output is A1OUT.                                                  */
20864   CTIMER_OUTCFG2_CFG24_A2OUT           = 3,     /*!< A2OUT : Output is A2OUT.                                                  */
20865   CTIMER_OUTCFG2_CFG24_A6OUT           = 2,     /*!< A6OUT : Output is A6OUT                                                   */
20866   CTIMER_OUTCFG2_CFG24_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20867   CTIMER_OUTCFG2_CFG24_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20868 } CTIMER_OUTCFG2_CFG24_Enum;
20869 
20870 /* =============================================  CTIMER OUTCFG2 CFG23 [9..11]  ============================================== */
20871 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG23                                                      */
20872   CTIMER_OUTCFG2_CFG23_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20873   CTIMER_OUTCFG2_CFG23_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20874   CTIMER_OUTCFG2_CFG23_B0OUT2          = 5,     /*!< B0OUT2 : Output is B0OUT2.                                                */
20875   CTIMER_OUTCFG2_CFG23_A5OUT           = 4,     /*!< A5OUT : Output is A5OUT.                                                  */
20876   CTIMER_OUTCFG2_CFG23_A7OUT           = 3,     /*!< A7OUT : Output is A7OUT.                                                  */
20877   CTIMER_OUTCFG2_CFG23_B5OUT2          = 2,     /*!< B5OUT2 : Output is B5OUT2                                                 */
20878   CTIMER_OUTCFG2_CFG23_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20879   CTIMER_OUTCFG2_CFG23_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20880 } CTIMER_OUTCFG2_CFG23_Enum;
20881 
20882 /* ==============================================  CTIMER OUTCFG2 CFG22 [6..8]  ============================================== */
20883 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG22                                                      */
20884   CTIMER_OUTCFG2_CFG22_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20885   CTIMER_OUTCFG2_CFG22_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20886   CTIMER_OUTCFG2_CFG22_A2OUT2          = 5,     /*!< A2OUT2 : Output is A2OUT2.                                                */
20887   CTIMER_OUTCFG2_CFG22_A1OUT           = 4,     /*!< A1OUT : Output is A1OUT.                                                  */
20888   CTIMER_OUTCFG2_CFG22_A6OUT           = 3,     /*!< A6OUT : Output is A6OUT.                                                  */
20889   CTIMER_OUTCFG2_CFG22_B5OUT           = 2,     /*!< B5OUT : Output is B5OUT                                                   */
20890   CTIMER_OUTCFG2_CFG22_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20891   CTIMER_OUTCFG2_CFG22_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20892 } CTIMER_OUTCFG2_CFG22_Enum;
20893 
20894 /* ==============================================  CTIMER OUTCFG2 CFG21 [3..5]  ============================================== */
20895 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG21                                                      */
20896   CTIMER_OUTCFG2_CFG21_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20897   CTIMER_OUTCFG2_CFG21_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20898   CTIMER_OUTCFG2_CFG21_A0OUT2          = 5,     /*!< A0OUT2 : Output is A0OUT2.                                                */
20899   CTIMER_OUTCFG2_CFG21_B5OUT           = 4,     /*!< B5OUT : Output is B5OUT.                                                  */
20900   CTIMER_OUTCFG2_CFG21_A1OUT           = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
20901   CTIMER_OUTCFG2_CFG21_A5OUT2          = 2,     /*!< A5OUT2 : Output is A5OUT2                                                 */
20902   CTIMER_OUTCFG2_CFG21_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20903   CTIMER_OUTCFG2_CFG21_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20904 } CTIMER_OUTCFG2_CFG21_Enum;
20905 
20906 /* ==============================================  CTIMER OUTCFG2 CFG20 [0..2]  ============================================== */
20907 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG20                                                      */
20908   CTIMER_OUTCFG2_CFG20_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20909   CTIMER_OUTCFG2_CFG20_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20910   CTIMER_OUTCFG2_CFG20_B2OUT2          = 5,     /*!< B2OUT2 : Output is B2OUT2.                                                */
20911   CTIMER_OUTCFG2_CFG20_A1OUT2          = 4,     /*!< A1OUT2 : Output is A1OUT2.                                                */
20912   CTIMER_OUTCFG2_CFG20_A1OUT           = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
20913   CTIMER_OUTCFG2_CFG20_A5OUT           = 2,     /*!< A5OUT : Output is A5OUT                                                   */
20914   CTIMER_OUTCFG2_CFG20_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20915   CTIMER_OUTCFG2_CFG20_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20916 } CTIMER_OUTCFG2_CFG20_Enum;
20917 
20918 /* ========================================================  OUTCFG3  ======================================================== */
20919 /* ==============================================  CTIMER OUTCFG3 CFG31 [3..5]  ============================================== */
20920 typedef enum {                                  /*!< CTIMER_OUTCFG3_CFG31                                                      */
20921   CTIMER_OUTCFG3_CFG31_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20922   CTIMER_OUTCFG3_CFG31_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20923   CTIMER_OUTCFG3_CFG31_B3OUT2          = 5,     /*!< B3OUT2 : Output is B3OUT2.                                                */
20924   CTIMER_OUTCFG3_CFG31_B7OUT           = 4,     /*!< B7OUT : Output is B7OUT.                                                  */
20925   CTIMER_OUTCFG3_CFG31_A6OUT           = 3,     /*!< A6OUT : Output is A6OUT.                                                  */
20926   CTIMER_OUTCFG3_CFG31_B7OUT2          = 2,     /*!< B7OUT2 : Output is B7OUT2                                                 */
20927   CTIMER_OUTCFG3_CFG31_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20928   CTIMER_OUTCFG3_CFG31_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20929 } CTIMER_OUTCFG3_CFG31_Enum;
20930 
20931 /* ==============================================  CTIMER OUTCFG3 CFG30 [0..2]  ============================================== */
20932 typedef enum {                                  /*!< CTIMER_OUTCFG3_CFG30                                                      */
20933   CTIMER_OUTCFG3_CFG30_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
20934   CTIMER_OUTCFG3_CFG30_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
20935   CTIMER_OUTCFG3_CFG30_A0OUT2          = 5,     /*!< A0OUT2 : Output is A0OUT2.                                                */
20936   CTIMER_OUTCFG3_CFG30_A4OUT2          = 4,     /*!< A4OUT2 : Output is A4OUT2.                                                */
20937   CTIMER_OUTCFG3_CFG30_B3OUT           = 3,     /*!< B3OUT : Output is B3OUT.                                                  */
20938   CTIMER_OUTCFG3_CFG30_B7OUT           = 2,     /*!< B7OUT : Output is B7OUT                                                   */
20939   CTIMER_OUTCFG3_CFG30_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
20940   CTIMER_OUTCFG3_CFG30_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
20941 } CTIMER_OUTCFG3_CFG30_Enum;
20942 
20943 /* =========================================================  INCFG  ========================================================= */
20944 /* ==============================================  CTIMER INCFG CFGB7 [15..15]  ============================================== */
20945 typedef enum {                                  /*!< CTIMER_INCFG_CFGB7                                                        */
20946   CTIMER_INCFG_CFGB7_CT31              = 1,     /*!< CT31 : Input is CT31                                                      */
20947   CTIMER_INCFG_CFGB7_CT30              = 0,     /*!< CT30 : Input is CT30                                                      */
20948 } CTIMER_INCFG_CFGB7_Enum;
20949 
20950 /* ==============================================  CTIMER INCFG CFGA7 [14..14]  ============================================== */
20951 typedef enum {                                  /*!< CTIMER_INCFG_CFGA7                                                        */
20952   CTIMER_INCFG_CFGA7_CT29              = 1,     /*!< CT29 : Input is CT29                                                      */
20953   CTIMER_INCFG_CFGA7_CT28              = 0,     /*!< CT28 : Input is CT28                                                      */
20954 } CTIMER_INCFG_CFGA7_Enum;
20955 
20956 /* ==============================================  CTIMER INCFG CFGB6 [13..13]  ============================================== */
20957 typedef enum {                                  /*!< CTIMER_INCFG_CFGB6                                                        */
20958   CTIMER_INCFG_CFGB6_CT27              = 1,     /*!< CT27 : Input is CT27                                                      */
20959   CTIMER_INCFG_CFGB6_CT26              = 0,     /*!< CT26 : Input is CT26                                                      */
20960 } CTIMER_INCFG_CFGB6_Enum;
20961 
20962 /* ==============================================  CTIMER INCFG CFGA6 [12..12]  ============================================== */
20963 typedef enum {                                  /*!< CTIMER_INCFG_CFGA6                                                        */
20964   CTIMER_INCFG_CFGA6_CT25              = 1,     /*!< CT25 : Input is CT25                                                      */
20965   CTIMER_INCFG_CFGA6_CT24              = 0,     /*!< CT24 : Input is CT24                                                      */
20966 } CTIMER_INCFG_CFGA6_Enum;
20967 
20968 /* ==============================================  CTIMER INCFG CFGB5 [11..11]  ============================================== */
20969 typedef enum {                                  /*!< CTIMER_INCFG_CFGB5                                                        */
20970   CTIMER_INCFG_CFGB5_CT23              = 1,     /*!< CT23 : Input is CT23                                                      */
20971   CTIMER_INCFG_CFGB5_CT22              = 0,     /*!< CT22 : Input is CT22                                                      */
20972 } CTIMER_INCFG_CFGB5_Enum;
20973 
20974 /* ==============================================  CTIMER INCFG CFGA5 [10..10]  ============================================== */
20975 typedef enum {                                  /*!< CTIMER_INCFG_CFGA5                                                        */
20976   CTIMER_INCFG_CFGA5_CT21              = 1,     /*!< CT21 : Input is CT21                                                      */
20977   CTIMER_INCFG_CFGA5_CT20              = 0,     /*!< CT20 : Input is CT20                                                      */
20978 } CTIMER_INCFG_CFGA5_Enum;
20979 
20980 /* ===============================================  CTIMER INCFG CFGB4 [9..9]  =============================================== */
20981 typedef enum {                                  /*!< CTIMER_INCFG_CFGB4                                                        */
20982   CTIMER_INCFG_CFGB4_CT19              = 1,     /*!< CT19 : Input is CT19                                                      */
20983   CTIMER_INCFG_CFGB4_CT18              = 0,     /*!< CT18 : Input is CT18                                                      */
20984 } CTIMER_INCFG_CFGB4_Enum;
20985 
20986 /* ===============================================  CTIMER INCFG CFGA4 [8..8]  =============================================== */
20987 typedef enum {                                  /*!< CTIMER_INCFG_CFGA4                                                        */
20988   CTIMER_INCFG_CFGA4_CT17              = 1,     /*!< CT17 : Input is CT17                                                      */
20989   CTIMER_INCFG_CFGA4_CT16              = 0,     /*!< CT16 : Input is CT16                                                      */
20990 } CTIMER_INCFG_CFGA4_Enum;
20991 
20992 /* ===============================================  CTIMER INCFG CFGB3 [7..7]  =============================================== */
20993 typedef enum {                                  /*!< CTIMER_INCFG_CFGB3                                                        */
20994   CTIMER_INCFG_CFGB3_CT15              = 1,     /*!< CT15 : Input is CT15                                                      */
20995   CTIMER_INCFG_CFGB3_CT14              = 0,     /*!< CT14 : Input is CT14                                                      */
20996 } CTIMER_INCFG_CFGB3_Enum;
20997 
20998 /* ===============================================  CTIMER INCFG CFGA3 [6..6]  =============================================== */
20999 typedef enum {                                  /*!< CTIMER_INCFG_CFGA3                                                        */
21000   CTIMER_INCFG_CFGA3_CT13              = 1,     /*!< CT13 : Input is CT13                                                      */
21001   CTIMER_INCFG_CFGA3_CT12              = 0,     /*!< CT12 : Input is CT12                                                      */
21002 } CTIMER_INCFG_CFGA3_Enum;
21003 
21004 /* ===============================================  CTIMER INCFG CFGB2 [5..5]  =============================================== */
21005 typedef enum {                                  /*!< CTIMER_INCFG_CFGB2                                                        */
21006   CTIMER_INCFG_CFGB2_CT11              = 1,     /*!< CT11 : Input is CT11                                                      */
21007   CTIMER_INCFG_CFGB2_CT10              = 0,     /*!< CT10 : Input is CT10                                                      */
21008 } CTIMER_INCFG_CFGB2_Enum;
21009 
21010 /* ===============================================  CTIMER INCFG CFGA2 [4..4]  =============================================== */
21011 typedef enum {                                  /*!< CTIMER_INCFG_CFGA2                                                        */
21012   CTIMER_INCFG_CFGA2_CT9               = 1,     /*!< CT9 : Input is CT9                                                        */
21013   CTIMER_INCFG_CFGA2_CT8               = 0,     /*!< CT8 : Input is CT8                                                        */
21014 } CTIMER_INCFG_CFGA2_Enum;
21015 
21016 /* ===============================================  CTIMER INCFG CFGB1 [3..3]  =============================================== */
21017 typedef enum {                                  /*!< CTIMER_INCFG_CFGB1                                                        */
21018   CTIMER_INCFG_CFGB1_CT7               = 1,     /*!< CT7 : Input is CT7                                                        */
21019   CTIMER_INCFG_CFGB1_CT6               = 0,     /*!< CT6 : Input is CT6                                                        */
21020 } CTIMER_INCFG_CFGB1_Enum;
21021 
21022 /* ===============================================  CTIMER INCFG CFGA1 [2..2]  =============================================== */
21023 typedef enum {                                  /*!< CTIMER_INCFG_CFGA1                                                        */
21024   CTIMER_INCFG_CFGA1_CT5               = 1,     /*!< CT5 : Input is CT5                                                        */
21025   CTIMER_INCFG_CFGA1_CT4               = 0,     /*!< CT4 : Input is CT4                                                        */
21026 } CTIMER_INCFG_CFGA1_Enum;
21027 
21028 /* ===============================================  CTIMER INCFG CFGB0 [1..1]  =============================================== */
21029 typedef enum {                                  /*!< CTIMER_INCFG_CFGB0                                                        */
21030   CTIMER_INCFG_CFGB0_CT3               = 1,     /*!< CT3 : Input is CT3                                                        */
21031   CTIMER_INCFG_CFGB0_CT2               = 0,     /*!< CT2 : Input is CT2                                                        */
21032 } CTIMER_INCFG_CFGB0_Enum;
21033 
21034 /* ===============================================  CTIMER INCFG CFGA0 [0..0]  =============================================== */
21035 typedef enum {                                  /*!< CTIMER_INCFG_CFGA0                                                        */
21036   CTIMER_INCFG_CFGA0_CT1               = 1,     /*!< CT1 : Input is CT1                                                        */
21037   CTIMER_INCFG_CFGA0_CT0               = 0,     /*!< CT0 : Input is CT0                                                        */
21038 } CTIMER_INCFG_CFGA0_Enum;
21039 
21040 /* =========================================================  STCFG  ========================================================= */
21041 /* =============================================  CTIMER STCFG FREEZE [31..31]  ============================================== */
21042 typedef enum {                                  /*!< CTIMER_STCFG_FREEZE                                                       */
21043   CTIMER_STCFG_FREEZE_THAW             = 0,     /*!< THAW : Let the COUNTER register run on its input clock.                   */
21044   CTIMER_STCFG_FREEZE_FREEZE           = 1,     /*!< FREEZE : Stop the COUNTER register for loading.                           */
21045 } CTIMER_STCFG_FREEZE_Enum;
21046 
21047 /* ==============================================  CTIMER STCFG CLEAR [30..30]  ============================================== */
21048 typedef enum {                                  /*!< CTIMER_STCFG_CLEAR                                                        */
21049   CTIMER_STCFG_CLEAR_RUN               = 0,     /*!< RUN : Let the COUNTER register run on its input clock.                    */
21050   CTIMER_STCFG_CLEAR_CLEAR             = 1,     /*!< CLEAR : Stop the COUNTER register for loading.                            */
21051 } CTIMER_STCFG_CLEAR_Enum;
21052 
21053 /* ==========================================  CTIMER STCFG COMPARE_H_EN [15..15]  =========================================== */
21054 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_H_EN                                                 */
21055   CTIMER_STCFG_COMPARE_H_EN_DISABLE    = 0,     /*!< DISABLE : Compare H disabled.                                             */
21056   CTIMER_STCFG_COMPARE_H_EN_ENABLE     = 1,     /*!< ENABLE : Compare H enabled.                                               */
21057 } CTIMER_STCFG_COMPARE_H_EN_Enum;
21058 
21059 /* ==========================================  CTIMER STCFG COMPARE_G_EN [14..14]  =========================================== */
21060 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_G_EN                                                 */
21061   CTIMER_STCFG_COMPARE_G_EN_DISABLE    = 0,     /*!< DISABLE : Compare G disabled.                                             */
21062   CTIMER_STCFG_COMPARE_G_EN_ENABLE     = 1,     /*!< ENABLE : Compare G enabled.                                               */
21063 } CTIMER_STCFG_COMPARE_G_EN_Enum;
21064 
21065 /* ==========================================  CTIMER STCFG COMPARE_F_EN [13..13]  =========================================== */
21066 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_F_EN                                                 */
21067   CTIMER_STCFG_COMPARE_F_EN_DISABLE    = 0,     /*!< DISABLE : Compare F disabled.                                             */
21068   CTIMER_STCFG_COMPARE_F_EN_ENABLE     = 1,     /*!< ENABLE : Compare F enabled.                                               */
21069 } CTIMER_STCFG_COMPARE_F_EN_Enum;
21070 
21071 /* ==========================================  CTIMER STCFG COMPARE_E_EN [12..12]  =========================================== */
21072 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_E_EN                                                 */
21073   CTIMER_STCFG_COMPARE_E_EN_DISABLE    = 0,     /*!< DISABLE : Compare E disabled.                                             */
21074   CTIMER_STCFG_COMPARE_E_EN_ENABLE     = 1,     /*!< ENABLE : Compare E enabled.                                               */
21075 } CTIMER_STCFG_COMPARE_E_EN_Enum;
21076 
21077 /* ==========================================  CTIMER STCFG COMPARE_D_EN [11..11]  =========================================== */
21078 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_D_EN                                                 */
21079   CTIMER_STCFG_COMPARE_D_EN_DISABLE    = 0,     /*!< DISABLE : Compare D disabled.                                             */
21080   CTIMER_STCFG_COMPARE_D_EN_ENABLE     = 1,     /*!< ENABLE : Compare D enabled.                                               */
21081 } CTIMER_STCFG_COMPARE_D_EN_Enum;
21082 
21083 /* ==========================================  CTIMER STCFG COMPARE_C_EN [10..10]  =========================================== */
21084 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_C_EN                                                 */
21085   CTIMER_STCFG_COMPARE_C_EN_DISABLE    = 0,     /*!< DISABLE : Compare C disabled.                                             */
21086   CTIMER_STCFG_COMPARE_C_EN_ENABLE     = 1,     /*!< ENABLE : Compare C enabled.                                               */
21087 } CTIMER_STCFG_COMPARE_C_EN_Enum;
21088 
21089 /* ===========================================  CTIMER STCFG COMPARE_B_EN [9..9]  ============================================ */
21090 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_B_EN                                                 */
21091   CTIMER_STCFG_COMPARE_B_EN_DISABLE    = 0,     /*!< DISABLE : Compare B disabled.                                             */
21092   CTIMER_STCFG_COMPARE_B_EN_ENABLE     = 1,     /*!< ENABLE : Compare B enabled.                                               */
21093 } CTIMER_STCFG_COMPARE_B_EN_Enum;
21094 
21095 /* ===========================================  CTIMER STCFG COMPARE_A_EN [8..8]  ============================================ */
21096 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_A_EN                                                 */
21097   CTIMER_STCFG_COMPARE_A_EN_DISABLE    = 0,     /*!< DISABLE : Compare A disabled.                                             */
21098   CTIMER_STCFG_COMPARE_A_EN_ENABLE     = 1,     /*!< ENABLE : Compare A enabled.                                               */
21099 } CTIMER_STCFG_COMPARE_A_EN_Enum;
21100 
21101 /* ==============================================  CTIMER STCFG CLKSEL [0..3]  =============================================== */
21102 typedef enum {                                  /*!< CTIMER_STCFG_CLKSEL                                                       */
21103   CTIMER_STCFG_CLKSEL_NOCLK            = 0,     /*!< NOCLK : No clock enabled.                                                 */
21104   CTIMER_STCFG_CLKSEL_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : 3MHz from the HFRC clock divider.                            */
21105   CTIMER_STCFG_CLKSEL_HFRC_DIV256      = 2,     /*!< HFRC_DIV256 : 187.5KHz from the HFRC clock divider.                       */
21106   CTIMER_STCFG_CLKSEL_XTAL_DIV1        = 3,     /*!< XTAL_DIV1 : 32768Hz from the crystal oscillator.                          */
21107   CTIMER_STCFG_CLKSEL_XTAL_DIV2        = 4,     /*!< XTAL_DIV2 : 16384Hz from the crystal oscillator.                          */
21108   CTIMER_STCFG_CLKSEL_XTAL_DIV32       = 5,     /*!< XTAL_DIV32 : 1024Hz from the crystal oscillator.                          */
21109   CTIMER_STCFG_CLKSEL_LFRC_DIV1        = 6,     /*!< LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated).   */
21110   CTIMER_STCFG_CLKSEL_CTIMER0A         = 7,     /*!< CTIMER0A : Use CTIMER 0 section A as a prescaler for the clock
21111                                                      source.                                                                   */
21112   CTIMER_STCFG_CLKSEL_CTIMER0B         = 8,     /*!< CTIMER0B : Use CTIMER 0 section B (or A and B linked together)
21113                                                      as a prescaler for the clock source.                                      */
21114 } CTIMER_STCFG_CLKSEL_Enum;
21115 
21116 /* =========================================================  STTMR  ========================================================= */
21117 /* ====================================================  CAPTURECONTROL  ===================================================== */
21118 /* =========================================  CTIMER CAPTURECONTROL CAPTURE3 [3..3]  ========================================= */
21119 typedef enum {                                  /*!< CTIMER_CAPTURECONTROL_CAPTURE3                                            */
21120   CTIMER_CAPTURECONTROL_CAPTURE3_DISABLE = 0,   /*!< DISABLE : Capture function disabled.                                      */
21121   CTIMER_CAPTURECONTROL_CAPTURE3_ENABLE = 1,    /*!< ENABLE : Capture function enabled.                                        */
21122 } CTIMER_CAPTURECONTROL_CAPTURE3_Enum;
21123 
21124 /* =========================================  CTIMER CAPTURECONTROL CAPTURE2 [2..2]  ========================================= */
21125 typedef enum {                                  /*!< CTIMER_CAPTURECONTROL_CAPTURE2                                            */
21126   CTIMER_CAPTURECONTROL_CAPTURE2_DISABLE = 0,   /*!< DISABLE : Capture function disabled.                                      */
21127   CTIMER_CAPTURECONTROL_CAPTURE2_ENABLE = 1,    /*!< ENABLE : Capture function enabled.                                        */
21128 } CTIMER_CAPTURECONTROL_CAPTURE2_Enum;
21129 
21130 /* =========================================  CTIMER CAPTURECONTROL CAPTURE1 [1..1]  ========================================= */
21131 typedef enum {                                  /*!< CTIMER_CAPTURECONTROL_CAPTURE1                                            */
21132   CTIMER_CAPTURECONTROL_CAPTURE1_DISABLE = 0,   /*!< DISABLE : Capture function disabled.                                      */
21133   CTIMER_CAPTURECONTROL_CAPTURE1_ENABLE = 1,    /*!< ENABLE : Capture function enabled.                                        */
21134 } CTIMER_CAPTURECONTROL_CAPTURE1_Enum;
21135 
21136 /* =========================================  CTIMER CAPTURECONTROL CAPTURE0 [0..0]  ========================================= */
21137 typedef enum {                                  /*!< CTIMER_CAPTURECONTROL_CAPTURE0                                            */
21138   CTIMER_CAPTURECONTROL_CAPTURE0_DISABLE = 0,   /*!< DISABLE : Capture function disabled.                                      */
21139   CTIMER_CAPTURECONTROL_CAPTURE0_ENABLE = 1,    /*!< ENABLE : Capture function enabled.                                        */
21140 } CTIMER_CAPTURECONTROL_CAPTURE0_Enum;
21141 
21142 /* ========================================================  SCMPR0  ========================================================= */
21143 /* ========================================================  SCMPR1  ========================================================= */
21144 /* ========================================================  SCMPR2  ========================================================= */
21145 /* ========================================================  SCMPR3  ========================================================= */
21146 /* ========================================================  SCMPR4  ========================================================= */
21147 /* ========================================================  SCMPR5  ========================================================= */
21148 /* ========================================================  SCMPR6  ========================================================= */
21149 /* ========================================================  SCMPR7  ========================================================= */
21150 /* ========================================================  SCAPT0  ========================================================= */
21151 /* ========================================================  SCAPT1  ========================================================= */
21152 /* ========================================================  SCAPT2  ========================================================= */
21153 /* ========================================================  SCAPT3  ========================================================= */
21154 /* =========================================================  SNVR0  ========================================================= */
21155 /* =========================================================  SNVR1  ========================================================= */
21156 /* =========================================================  SNVR2  ========================================================= */
21157 /* =========================================================  SNVR3  ========================================================= */
21158 /* =========================================================  INTEN  ========================================================= */
21159 /* ========================================================  INTSTAT  ======================================================== */
21160 /* ========================================================  INTCLR  ========================================================= */
21161 /* ========================================================  INTSET  ========================================================= */
21162 /* =======================================================  STMINTEN  ======================================================== */
21163 /* ===========================================  CTIMER STMINTEN CAPTURED [12..12]  =========================================== */
21164 typedef enum {                                  /*!< CTIMER_STMINTEN_CAPTURED                                                  */
21165   CTIMER_STMINTEN_CAPTURED_CAPD_INT    = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
21166 } CTIMER_STMINTEN_CAPTURED_Enum;
21167 
21168 /* ===========================================  CTIMER STMINTEN CAPTUREC [11..11]  =========================================== */
21169 typedef enum {                                  /*!< CTIMER_STMINTEN_CAPTUREC                                                  */
21170   CTIMER_STMINTEN_CAPTUREC_CAPC_INT    = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
21171 } CTIMER_STMINTEN_CAPTUREC_Enum;
21172 
21173 /* ===========================================  CTIMER STMINTEN CAPTUREB [10..10]  =========================================== */
21174 typedef enum {                                  /*!< CTIMER_STMINTEN_CAPTUREB                                                  */
21175   CTIMER_STMINTEN_CAPTUREB_CAPB_INT    = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
21176 } CTIMER_STMINTEN_CAPTUREB_Enum;
21177 
21178 /* ============================================  CTIMER STMINTEN CAPTUREA [9..9]  ============================================ */
21179 typedef enum {                                  /*!< CTIMER_STMINTEN_CAPTUREA                                                  */
21180   CTIMER_STMINTEN_CAPTUREA_CAPA_INT    = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
21181 } CTIMER_STMINTEN_CAPTUREA_Enum;
21182 
21183 /* ============================================  CTIMER STMINTEN OVERFLOW [8..8]  ============================================ */
21184 typedef enum {                                  /*!< CTIMER_STMINTEN_OVERFLOW                                                  */
21185   CTIMER_STMINTEN_OVERFLOW_OFLOW_INT   = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
21186 } CTIMER_STMINTEN_OVERFLOW_Enum;
21187 
21188 /* ============================================  CTIMER STMINTEN COMPAREH [7..7]  ============================================ */
21189 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREH                                                  */
21190   CTIMER_STMINTEN_COMPAREH_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21191 } CTIMER_STMINTEN_COMPAREH_Enum;
21192 
21193 /* ============================================  CTIMER STMINTEN COMPAREG [6..6]  ============================================ */
21194 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREG                                                  */
21195   CTIMER_STMINTEN_COMPAREG_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21196 } CTIMER_STMINTEN_COMPAREG_Enum;
21197 
21198 /* ============================================  CTIMER STMINTEN COMPAREF [5..5]  ============================================ */
21199 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREF                                                  */
21200   CTIMER_STMINTEN_COMPAREF_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21201 } CTIMER_STMINTEN_COMPAREF_Enum;
21202 
21203 /* ============================================  CTIMER STMINTEN COMPAREE [4..4]  ============================================ */
21204 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREE                                                  */
21205   CTIMER_STMINTEN_COMPAREE_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21206 } CTIMER_STMINTEN_COMPAREE_Enum;
21207 
21208 /* ============================================  CTIMER STMINTEN COMPARED [3..3]  ============================================ */
21209 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPARED                                                  */
21210   CTIMER_STMINTEN_COMPARED_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21211 } CTIMER_STMINTEN_COMPARED_Enum;
21212 
21213 /* ============================================  CTIMER STMINTEN COMPAREC [2..2]  ============================================ */
21214 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREC                                                  */
21215   CTIMER_STMINTEN_COMPAREC_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21216 } CTIMER_STMINTEN_COMPAREC_Enum;
21217 
21218 /* ============================================  CTIMER STMINTEN COMPAREB [1..1]  ============================================ */
21219 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREB                                                  */
21220   CTIMER_STMINTEN_COMPAREB_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21221 } CTIMER_STMINTEN_COMPAREB_Enum;
21222 
21223 /* ============================================  CTIMER STMINTEN COMPAREA [0..0]  ============================================ */
21224 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREA                                                  */
21225   CTIMER_STMINTEN_COMPAREA_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21226 } CTIMER_STMINTEN_COMPAREA_Enum;
21227 
21228 /* ======================================================  STMINTSTAT  ======================================================= */
21229 /* ==========================================  CTIMER STMINTSTAT CAPTURED [12..12]  ========================================== */
21230 typedef enum {                                  /*!< CTIMER_STMINTSTAT_CAPTURED                                                */
21231   CTIMER_STMINTSTAT_CAPTURED_CAPD_INT  = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
21232 } CTIMER_STMINTSTAT_CAPTURED_Enum;
21233 
21234 /* ==========================================  CTIMER STMINTSTAT CAPTUREC [11..11]  ========================================== */
21235 typedef enum {                                  /*!< CTIMER_STMINTSTAT_CAPTUREC                                                */
21236   CTIMER_STMINTSTAT_CAPTUREC_CAPC_INT  = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
21237 } CTIMER_STMINTSTAT_CAPTUREC_Enum;
21238 
21239 /* ==========================================  CTIMER STMINTSTAT CAPTUREB [10..10]  ========================================== */
21240 typedef enum {                                  /*!< CTIMER_STMINTSTAT_CAPTUREB                                                */
21241   CTIMER_STMINTSTAT_CAPTUREB_CAPB_INT  = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
21242 } CTIMER_STMINTSTAT_CAPTUREB_Enum;
21243 
21244 /* ===========================================  CTIMER STMINTSTAT CAPTUREA [9..9]  =========================================== */
21245 typedef enum {                                  /*!< CTIMER_STMINTSTAT_CAPTUREA                                                */
21246   CTIMER_STMINTSTAT_CAPTUREA_CAPA_INT  = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
21247 } CTIMER_STMINTSTAT_CAPTUREA_Enum;
21248 
21249 /* ===========================================  CTIMER STMINTSTAT OVERFLOW [8..8]  =========================================== */
21250 typedef enum {                                  /*!< CTIMER_STMINTSTAT_OVERFLOW                                                */
21251   CTIMER_STMINTSTAT_OVERFLOW_OFLOW_INT = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
21252 } CTIMER_STMINTSTAT_OVERFLOW_Enum;
21253 
21254 /* ===========================================  CTIMER STMINTSTAT COMPAREH [7..7]  =========================================== */
21255 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREH                                                */
21256   CTIMER_STMINTSTAT_COMPAREH_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21257 } CTIMER_STMINTSTAT_COMPAREH_Enum;
21258 
21259 /* ===========================================  CTIMER STMINTSTAT COMPAREG [6..6]  =========================================== */
21260 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREG                                                */
21261   CTIMER_STMINTSTAT_COMPAREG_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21262 } CTIMER_STMINTSTAT_COMPAREG_Enum;
21263 
21264 /* ===========================================  CTIMER STMINTSTAT COMPAREF [5..5]  =========================================== */
21265 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREF                                                */
21266   CTIMER_STMINTSTAT_COMPAREF_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21267 } CTIMER_STMINTSTAT_COMPAREF_Enum;
21268 
21269 /* ===========================================  CTIMER STMINTSTAT COMPAREE [4..4]  =========================================== */
21270 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREE                                                */
21271   CTIMER_STMINTSTAT_COMPAREE_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21272 } CTIMER_STMINTSTAT_COMPAREE_Enum;
21273 
21274 /* ===========================================  CTIMER STMINTSTAT COMPARED [3..3]  =========================================== */
21275 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPARED                                                */
21276   CTIMER_STMINTSTAT_COMPARED_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21277 } CTIMER_STMINTSTAT_COMPARED_Enum;
21278 
21279 /* ===========================================  CTIMER STMINTSTAT COMPAREC [2..2]  =========================================== */
21280 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREC                                                */
21281   CTIMER_STMINTSTAT_COMPAREC_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21282 } CTIMER_STMINTSTAT_COMPAREC_Enum;
21283 
21284 /* ===========================================  CTIMER STMINTSTAT COMPAREB [1..1]  =========================================== */
21285 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREB                                                */
21286   CTIMER_STMINTSTAT_COMPAREB_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21287 } CTIMER_STMINTSTAT_COMPAREB_Enum;
21288 
21289 /* ===========================================  CTIMER STMINTSTAT COMPAREA [0..0]  =========================================== */
21290 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREA                                                */
21291   CTIMER_STMINTSTAT_COMPAREA_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21292 } CTIMER_STMINTSTAT_COMPAREA_Enum;
21293 
21294 /* =======================================================  STMINTCLR  ======================================================= */
21295 /* ==========================================  CTIMER STMINTCLR CAPTURED [12..12]  =========================================== */
21296 typedef enum {                                  /*!< CTIMER_STMINTCLR_CAPTURED                                                 */
21297   CTIMER_STMINTCLR_CAPTURED_CAPD_INT   = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
21298 } CTIMER_STMINTCLR_CAPTURED_Enum;
21299 
21300 /* ==========================================  CTIMER STMINTCLR CAPTUREC [11..11]  =========================================== */
21301 typedef enum {                                  /*!< CTIMER_STMINTCLR_CAPTUREC                                                 */
21302   CTIMER_STMINTCLR_CAPTUREC_CAPC_INT   = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
21303 } CTIMER_STMINTCLR_CAPTUREC_Enum;
21304 
21305 /* ==========================================  CTIMER STMINTCLR CAPTUREB [10..10]  =========================================== */
21306 typedef enum {                                  /*!< CTIMER_STMINTCLR_CAPTUREB                                                 */
21307   CTIMER_STMINTCLR_CAPTUREB_CAPB_INT   = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
21308 } CTIMER_STMINTCLR_CAPTUREB_Enum;
21309 
21310 /* ===========================================  CTIMER STMINTCLR CAPTUREA [9..9]  ============================================ */
21311 typedef enum {                                  /*!< CTIMER_STMINTCLR_CAPTUREA                                                 */
21312   CTIMER_STMINTCLR_CAPTUREA_CAPA_INT   = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
21313 } CTIMER_STMINTCLR_CAPTUREA_Enum;
21314 
21315 /* ===========================================  CTIMER STMINTCLR OVERFLOW [8..8]  ============================================ */
21316 typedef enum {                                  /*!< CTIMER_STMINTCLR_OVERFLOW                                                 */
21317   CTIMER_STMINTCLR_OVERFLOW_OFLOW_INT  = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
21318 } CTIMER_STMINTCLR_OVERFLOW_Enum;
21319 
21320 /* ===========================================  CTIMER STMINTCLR COMPAREH [7..7]  ============================================ */
21321 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREH                                                 */
21322   CTIMER_STMINTCLR_COMPAREH_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21323 } CTIMER_STMINTCLR_COMPAREH_Enum;
21324 
21325 /* ===========================================  CTIMER STMINTCLR COMPAREG [6..6]  ============================================ */
21326 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREG                                                 */
21327   CTIMER_STMINTCLR_COMPAREG_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21328 } CTIMER_STMINTCLR_COMPAREG_Enum;
21329 
21330 /* ===========================================  CTIMER STMINTCLR COMPAREF [5..5]  ============================================ */
21331 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREF                                                 */
21332   CTIMER_STMINTCLR_COMPAREF_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21333 } CTIMER_STMINTCLR_COMPAREF_Enum;
21334 
21335 /* ===========================================  CTIMER STMINTCLR COMPAREE [4..4]  ============================================ */
21336 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREE                                                 */
21337   CTIMER_STMINTCLR_COMPAREE_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21338 } CTIMER_STMINTCLR_COMPAREE_Enum;
21339 
21340 /* ===========================================  CTIMER STMINTCLR COMPARED [3..3]  ============================================ */
21341 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPARED                                                 */
21342   CTIMER_STMINTCLR_COMPARED_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21343 } CTIMER_STMINTCLR_COMPARED_Enum;
21344 
21345 /* ===========================================  CTIMER STMINTCLR COMPAREC [2..2]  ============================================ */
21346 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREC                                                 */
21347   CTIMER_STMINTCLR_COMPAREC_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21348 } CTIMER_STMINTCLR_COMPAREC_Enum;
21349 
21350 /* ===========================================  CTIMER STMINTCLR COMPAREB [1..1]  ============================================ */
21351 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREB                                                 */
21352   CTIMER_STMINTCLR_COMPAREB_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21353 } CTIMER_STMINTCLR_COMPAREB_Enum;
21354 
21355 /* ===========================================  CTIMER STMINTCLR COMPAREA [0..0]  ============================================ */
21356 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREA                                                 */
21357   CTIMER_STMINTCLR_COMPAREA_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21358 } CTIMER_STMINTCLR_COMPAREA_Enum;
21359 
21360 /* =======================================================  STMINTSET  ======================================================= */
21361 /* ==========================================  CTIMER STMINTSET CAPTURED [12..12]  =========================================== */
21362 typedef enum {                                  /*!< CTIMER_STMINTSET_CAPTURED                                                 */
21363   CTIMER_STMINTSET_CAPTURED_CAPD_INT   = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
21364 } CTIMER_STMINTSET_CAPTURED_Enum;
21365 
21366 /* ==========================================  CTIMER STMINTSET CAPTUREC [11..11]  =========================================== */
21367 typedef enum {                                  /*!< CTIMER_STMINTSET_CAPTUREC                                                 */
21368   CTIMER_STMINTSET_CAPTUREC_CAPC_INT   = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
21369 } CTIMER_STMINTSET_CAPTUREC_Enum;
21370 
21371 /* ==========================================  CTIMER STMINTSET CAPTUREB [10..10]  =========================================== */
21372 typedef enum {                                  /*!< CTIMER_STMINTSET_CAPTUREB                                                 */
21373   CTIMER_STMINTSET_CAPTUREB_CAPB_INT   = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
21374 } CTIMER_STMINTSET_CAPTUREB_Enum;
21375 
21376 /* ===========================================  CTIMER STMINTSET CAPTUREA [9..9]  ============================================ */
21377 typedef enum {                                  /*!< CTIMER_STMINTSET_CAPTUREA                                                 */
21378   CTIMER_STMINTSET_CAPTUREA_CAPA_INT   = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
21379 } CTIMER_STMINTSET_CAPTUREA_Enum;
21380 
21381 /* ===========================================  CTIMER STMINTSET OVERFLOW [8..8]  ============================================ */
21382 typedef enum {                                  /*!< CTIMER_STMINTSET_OVERFLOW                                                 */
21383   CTIMER_STMINTSET_OVERFLOW_OFLOW_INT  = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
21384 } CTIMER_STMINTSET_OVERFLOW_Enum;
21385 
21386 /* ===========================================  CTIMER STMINTSET COMPAREH [7..7]  ============================================ */
21387 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREH                                                 */
21388   CTIMER_STMINTSET_COMPAREH_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21389 } CTIMER_STMINTSET_COMPAREH_Enum;
21390 
21391 /* ===========================================  CTIMER STMINTSET COMPAREG [6..6]  ============================================ */
21392 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREG                                                 */
21393   CTIMER_STMINTSET_COMPAREG_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21394 } CTIMER_STMINTSET_COMPAREG_Enum;
21395 
21396 /* ===========================================  CTIMER STMINTSET COMPAREF [5..5]  ============================================ */
21397 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREF                                                 */
21398   CTIMER_STMINTSET_COMPAREF_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21399 } CTIMER_STMINTSET_COMPAREF_Enum;
21400 
21401 /* ===========================================  CTIMER STMINTSET COMPAREE [4..4]  ============================================ */
21402 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREE                                                 */
21403   CTIMER_STMINTSET_COMPAREE_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21404 } CTIMER_STMINTSET_COMPAREE_Enum;
21405 
21406 /* ===========================================  CTIMER STMINTSET COMPARED [3..3]  ============================================ */
21407 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPARED                                                 */
21408   CTIMER_STMINTSET_COMPARED_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21409 } CTIMER_STMINTSET_COMPARED_Enum;
21410 
21411 /* ===========================================  CTIMER STMINTSET COMPAREC [2..2]  ============================================ */
21412 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREC                                                 */
21413   CTIMER_STMINTSET_COMPAREC_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21414 } CTIMER_STMINTSET_COMPAREC_Enum;
21415 
21416 /* ===========================================  CTIMER STMINTSET COMPAREB [1..1]  ============================================ */
21417 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREB                                                 */
21418   CTIMER_STMINTSET_COMPAREB_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21419 } CTIMER_STMINTSET_COMPAREB_Enum;
21420 
21421 /* ===========================================  CTIMER STMINTSET COMPAREA [0..0]  ============================================ */
21422 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREA                                                 */
21423   CTIMER_STMINTSET_COMPAREA_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
21424 } CTIMER_STMINTSET_COMPAREA_Enum;
21425 
21426 
21427 
21428 /* =========================================================================================================================== */
21429 /* ================                                           GPIO                                            ================ */
21430 /* =========================================================================================================================== */
21431 
21432 /* ========================================================  PADREGA  ======================================================== */
21433 /* ============================================  GPIO PADREGA PAD3PWRUP [30..30]  ============================================ */
21434 typedef enum {                                  /*!< GPIO_PADREGA_PAD3PWRUP                                                    */
21435   GPIO_PADREGA_PAD3PWRUP_DIS           = 0,     /*!< DIS : Power switch disabled                                               */
21436   GPIO_PADREGA_PAD3PWRUP_EN            = 1,     /*!< EN : Power switch enabled (switched to VDD)                               */
21437 } GPIO_PADREGA_PAD3PWRUP_Enum;
21438 
21439 /* ===========================================  GPIO PADREGA PAD3FNCSEL [27..29]  ============================================ */
21440 typedef enum {                                  /*!< GPIO_PADREGA_PAD3FNCSEL                                                   */
21441   GPIO_PADREGA_PAD3FNCSEL_UA0RTS       = 0,     /*!< UA0RTS : Configure as the UART0 RTS output                                */
21442   GPIO_PADREGA_PAD3FNCSEL_SLnCE        = 1,     /*!< SLnCE : Configure as the IOSLAVE SPI nCE signal                           */
21443   GPIO_PADREGA_PAD3FNCSEL_NCE3         = 2,     /*!< NCE3 : IOM/MSPI nCE group 3                                               */
21444   GPIO_PADREGA_PAD3FNCSEL_GPIO3        = 3,     /*!< GPIO3 : Configure as GPIO3                                                */
21445   GPIO_PADREGA_PAD3FNCSEL_MSPI7        = 5,     /*!< MSPI7 : MSPI data connection 7                                            */
21446   GPIO_PADREGA_PAD3FNCSEL_TRIG1        = 6,     /*!< TRIG1 : Configure as the ADC Trigger 1 signal                             */
21447   GPIO_PADREGA_PAD3FNCSEL_I2S_WCLK     = 7,     /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input                      */
21448 } GPIO_PADREGA_PAD3FNCSEL_Enum;
21449 
21450 /* ============================================  GPIO PADREGA PAD3STRNG [26..26]  ============================================ */
21451 typedef enum {                                  /*!< GPIO_PADREGA_PAD3STRNG                                                    */
21452   GPIO_PADREGA_PAD3STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
21453   GPIO_PADREGA_PAD3STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
21454 } GPIO_PADREGA_PAD3STRNG_Enum;
21455 
21456 /* ============================================  GPIO PADREGA PAD3INPEN [25..25]  ============================================ */
21457 typedef enum {                                  /*!< GPIO_PADREGA_PAD3INPEN                                                    */
21458   GPIO_PADREGA_PAD3INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
21459   GPIO_PADREGA_PAD3INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
21460 } GPIO_PADREGA_PAD3INPEN_Enum;
21461 
21462 /* ============================================  GPIO PADREGA PAD3PULL [24..24]  ============================================= */
21463 typedef enum {                                  /*!< GPIO_PADREGA_PAD3PULL                                                     */
21464   GPIO_PADREGA_PAD3PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
21465   GPIO_PADREGA_PAD3PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
21466 } GPIO_PADREGA_PAD3PULL_Enum;
21467 
21468 /* ===========================================  GPIO PADREGA PAD2FNCSEL [19..21]  ============================================ */
21469 typedef enum {                                  /*!< GPIO_PADREGA_PAD2FNCSEL                                                   */
21470   GPIO_PADREGA_PAD2FNCSEL_UART1RX      = 0,     /*!< UART1RX : Configure as the UART1 RX input.                                */
21471   GPIO_PADREGA_PAD2FNCSEL_SLMISO       = 1,     /*!< SLMISO : Configure as the IOSLAVE SPI MISO signal.                        */
21472   GPIO_PADREGA_PAD2FNCSEL_UART0RX      = 2,     /*!< UART0RX : Configure as the UART0 RX input.                                */
21473   GPIO_PADREGA_PAD2FNCSEL_GPIO2        = 3,     /*!< GPIO2 : Configure as GPIO2.                                               */
21474   GPIO_PADREGA_PAD2FNCSEL_MSPI6        = 5,     /*!< MSPI6 : MSPI data connection 6.                                           */
21475   GPIO_PADREGA_PAD2FNCSEL_NCE2         = 7,     /*!< NCE2 : IOM/MSPI nCE group 2                                               */
21476 } GPIO_PADREGA_PAD2FNCSEL_Enum;
21477 
21478 /* ============================================  GPIO PADREGA PAD2STRNG [18..18]  ============================================ */
21479 typedef enum {                                  /*!< GPIO_PADREGA_PAD2STRNG                                                    */
21480   GPIO_PADREGA_PAD2STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
21481   GPIO_PADREGA_PAD2STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
21482 } GPIO_PADREGA_PAD2STRNG_Enum;
21483 
21484 /* ============================================  GPIO PADREGA PAD2INPEN [17..17]  ============================================ */
21485 typedef enum {                                  /*!< GPIO_PADREGA_PAD2INPEN                                                    */
21486   GPIO_PADREGA_PAD2INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
21487   GPIO_PADREGA_PAD2INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
21488 } GPIO_PADREGA_PAD2INPEN_Enum;
21489 
21490 /* ============================================  GPIO PADREGA PAD2PULL [16..16]  ============================================= */
21491 typedef enum {                                  /*!< GPIO_PADREGA_PAD2PULL                                                     */
21492   GPIO_PADREGA_PAD2PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
21493   GPIO_PADREGA_PAD2PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
21494 } GPIO_PADREGA_PAD2PULL_Enum;
21495 
21496 /* ============================================  GPIO PADREGA PAD1RSEL [14..15]  ============================================= */
21497 typedef enum {                                  /*!< GPIO_PADREGA_PAD1RSEL                                                     */
21498   GPIO_PADREGA_PAD1RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
21499   GPIO_PADREGA_PAD1RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
21500   GPIO_PADREGA_PAD1RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
21501   GPIO_PADREGA_PAD1RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
21502 } GPIO_PADREGA_PAD1RSEL_Enum;
21503 
21504 /* ===========================================  GPIO PADREGA PAD1FNCSEL [11..13]  ============================================ */
21505 typedef enum {                                  /*!< GPIO_PADREGA_PAD1FNCSEL                                                   */
21506   GPIO_PADREGA_PAD1FNCSEL_SLSDAWIR3    = 0,     /*!< SLSDAWIR3 : Configure as the IOSLAVE I2C SDA or SPI WIR3 signal           */
21507   GPIO_PADREGA_PAD1FNCSEL_SLMOSI       = 1,     /*!< SLMOSI : Configure as the IOSLAVE SPI MOSI signal                         */
21508   GPIO_PADREGA_PAD1FNCSEL_UART0TX      = 2,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
21509   GPIO_PADREGA_PAD1FNCSEL_GPIO1        = 3,     /*!< GPIO1 : Configure as GPIO1                                                */
21510   GPIO_PADREGA_PAD1FNCSEL_MSPI5        = 5,     /*!< MSPI5 : MSPI data connection 5                                            */
21511   GPIO_PADREGA_PAD1FNCSEL_NCE1         = 7,     /*!< NCE1 : IOM/MSPI nCE group 1                                               */
21512 } GPIO_PADREGA_PAD1FNCSEL_Enum;
21513 
21514 /* ============================================  GPIO PADREGA PAD1STRNG [10..10]  ============================================ */
21515 typedef enum {                                  /*!< GPIO_PADREGA_PAD1STRNG                                                    */
21516   GPIO_PADREGA_PAD1STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
21517   GPIO_PADREGA_PAD1STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
21518 } GPIO_PADREGA_PAD1STRNG_Enum;
21519 
21520 /* =============================================  GPIO PADREGA PAD1INPEN [9..9]  ============================================= */
21521 typedef enum {                                  /*!< GPIO_PADREGA_PAD1INPEN                                                    */
21522   GPIO_PADREGA_PAD1INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
21523   GPIO_PADREGA_PAD1INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
21524 } GPIO_PADREGA_PAD1INPEN_Enum;
21525 
21526 /* =============================================  GPIO PADREGA PAD1PULL [8..8]  ============================================== */
21527 typedef enum {                                  /*!< GPIO_PADREGA_PAD1PULL                                                     */
21528   GPIO_PADREGA_PAD1PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
21529   GPIO_PADREGA_PAD1PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
21530 } GPIO_PADREGA_PAD1PULL_Enum;
21531 
21532 /* =============================================  GPIO PADREGA PAD0RSEL [6..7]  ============================================== */
21533 typedef enum {                                  /*!< GPIO_PADREGA_PAD0RSEL                                                     */
21534   GPIO_PADREGA_PAD0RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
21535   GPIO_PADREGA_PAD0RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
21536   GPIO_PADREGA_PAD0RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
21537   GPIO_PADREGA_PAD0RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
21538 } GPIO_PADREGA_PAD0RSEL_Enum;
21539 
21540 /* ============================================  GPIO PADREGA PAD0FNCSEL [3..5]  ============================================= */
21541 typedef enum {                                  /*!< GPIO_PADREGA_PAD0FNCSEL                                                   */
21542   GPIO_PADREGA_PAD0FNCSEL_SLSCL        = 0,     /*!< SLSCL : Configure as the IOSLAVE I2C SCL signal                           */
21543   GPIO_PADREGA_PAD0FNCSEL_SLSCK        = 1,     /*!< SLSCK : Configure as the IOSLAVE SPI SCK signal                           */
21544   GPIO_PADREGA_PAD0FNCSEL_CLKOUT       = 2,     /*!< CLKOUT : Configure as the CLKOUT signal                                   */
21545   GPIO_PADREGA_PAD0FNCSEL_GPIO0        = 3,     /*!< GPIO0 : Configure as GPIO0                                                */
21546   GPIO_PADREGA_PAD0FNCSEL_MSPI4        = 5,     /*!< MSPI4 : MSPI data connection 4                                            */
21547   GPIO_PADREGA_PAD0FNCSEL_NCE0         = 7,     /*!< NCE0 : IOM/MSPI nCE group 0                                               */
21548 } GPIO_PADREGA_PAD0FNCSEL_Enum;
21549 
21550 /* =============================================  GPIO PADREGA PAD0STRNG [2..2]  ============================================= */
21551 typedef enum {                                  /*!< GPIO_PADREGA_PAD0STRNG                                                    */
21552   GPIO_PADREGA_PAD0STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
21553   GPIO_PADREGA_PAD0STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
21554 } GPIO_PADREGA_PAD0STRNG_Enum;
21555 
21556 /* =============================================  GPIO PADREGA PAD0INPEN [1..1]  ============================================= */
21557 typedef enum {                                  /*!< GPIO_PADREGA_PAD0INPEN                                                    */
21558   GPIO_PADREGA_PAD0INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
21559   GPIO_PADREGA_PAD0INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
21560 } GPIO_PADREGA_PAD0INPEN_Enum;
21561 
21562 /* =============================================  GPIO PADREGA PAD0PULL [0..0]  ============================================== */
21563 typedef enum {                                  /*!< GPIO_PADREGA_PAD0PULL                                                     */
21564   GPIO_PADREGA_PAD0PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
21565   GPIO_PADREGA_PAD0PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
21566 } GPIO_PADREGA_PAD0PULL_Enum;
21567 
21568 /* ========================================================  PADREGB  ======================================================== */
21569 /* ===========================================  GPIO PADREGB PAD7FNCSEL [27..29]  ============================================ */
21570 typedef enum {                                  /*!< GPIO_PADREGB_PAD7FNCSEL                                                   */
21571   GPIO_PADREGB_PAD7FNCSEL_NCE7         = 0,     /*!< NCE7 : IOM/MSPI nCE group 7                                               */
21572   GPIO_PADREGB_PAD7FNCSEL_M0MOSI       = 1,     /*!< M0MOSI : Configure as the IOMSTR0 SPI MOSI signal                         */
21573   GPIO_PADREGB_PAD7FNCSEL_CLKOUT       = 2,     /*!< CLKOUT : Configure as the CLKOUT signal                                   */
21574   GPIO_PADREGB_PAD7FNCSEL_GPIO7        = 3,     /*!< GPIO7 : Configure as GPIO7                                                */
21575   GPIO_PADREGB_PAD7FNCSEL_TRIG0        = 4,     /*!< TRIG0 : Configure as the ADC Trigger 0 signal                             */
21576   GPIO_PADREGB_PAD7FNCSEL_UART0TX      = 5,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
21577   GPIO_PADREGB_PAD7FNCSEL_CT19         = 7,     /*!< CT19 : CTIMER connection 19                                               */
21578 } GPIO_PADREGB_PAD7FNCSEL_Enum;
21579 
21580 /* ============================================  GPIO PADREGB PAD7STRNG [26..26]  ============================================ */
21581 typedef enum {                                  /*!< GPIO_PADREGB_PAD7STRNG                                                    */
21582   GPIO_PADREGB_PAD7STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
21583   GPIO_PADREGB_PAD7STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
21584 } GPIO_PADREGB_PAD7STRNG_Enum;
21585 
21586 /* ============================================  GPIO PADREGB PAD7INPEN [25..25]  ============================================ */
21587 typedef enum {                                  /*!< GPIO_PADREGB_PAD7INPEN                                                    */
21588   GPIO_PADREGB_PAD7INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
21589   GPIO_PADREGB_PAD7INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
21590 } GPIO_PADREGB_PAD7INPEN_Enum;
21591 
21592 /* ============================================  GPIO PADREGB PAD7PULL [24..24]  ============================================= */
21593 typedef enum {                                  /*!< GPIO_PADREGB_PAD7PULL                                                     */
21594   GPIO_PADREGB_PAD7PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
21595   GPIO_PADREGB_PAD7PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
21596 } GPIO_PADREGB_PAD7PULL_Enum;
21597 
21598 /* ============================================  GPIO PADREGB PAD6RSEL [22..23]  ============================================= */
21599 typedef enum {                                  /*!< GPIO_PADREGB_PAD6RSEL                                                     */
21600   GPIO_PADREGB_PAD6RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
21601   GPIO_PADREGB_PAD6RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
21602   GPIO_PADREGB_PAD6RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
21603   GPIO_PADREGB_PAD6RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
21604 } GPIO_PADREGB_PAD6RSEL_Enum;
21605 
21606 /* ===========================================  GPIO PADREGB PAD6FNCSEL [19..21]  ============================================ */
21607 typedef enum {                                  /*!< GPIO_PADREGB_PAD6FNCSEL                                                   */
21608   GPIO_PADREGB_PAD6FNCSEL_M0SDAWIR3    = 0,     /*!< M0SDAWIR3 : Configure as the IOMSTR0 I2C SDA or SPI WIR3 signal           */
21609   GPIO_PADREGB_PAD6FNCSEL_M0MISO       = 1,     /*!< M0MISO : Configure as the IOMSTR0 SPI MISO signal                         */
21610   GPIO_PADREGB_PAD6FNCSEL_UA0CTS       = 2,     /*!< UA0CTS : Configure as the UART0 CTS input signal                          */
21611   GPIO_PADREGB_PAD6FNCSEL_GPIO6        = 3,     /*!< GPIO6 : Configure as GPIO6                                                */
21612   GPIO_PADREGB_PAD6FNCSEL_CT10         = 5,     /*!< CT10 : CTIMER connection 10                                               */
21613   GPIO_PADREGB_PAD6FNCSEL_I2S_DAT      = 7,     /*!< I2S_DAT : Configure as the PDM I2S Data output signal                     */
21614 } GPIO_PADREGB_PAD6FNCSEL_Enum;
21615 
21616 /* ============================================  GPIO PADREGB PAD6STRNG [18..18]  ============================================ */
21617 typedef enum {                                  /*!< GPIO_PADREGB_PAD6STRNG                                                    */
21618   GPIO_PADREGB_PAD6STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
21619   GPIO_PADREGB_PAD6STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
21620 } GPIO_PADREGB_PAD6STRNG_Enum;
21621 
21622 /* ============================================  GPIO PADREGB PAD6INPEN [17..17]  ============================================ */
21623 typedef enum {                                  /*!< GPIO_PADREGB_PAD6INPEN                                                    */
21624   GPIO_PADREGB_PAD6INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
21625   GPIO_PADREGB_PAD6INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
21626 } GPIO_PADREGB_PAD6INPEN_Enum;
21627 
21628 /* ============================================  GPIO PADREGB PAD6PULL [16..16]  ============================================= */
21629 typedef enum {                                  /*!< GPIO_PADREGB_PAD6PULL                                                     */
21630   GPIO_PADREGB_PAD6PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
21631   GPIO_PADREGB_PAD6PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
21632 } GPIO_PADREGB_PAD6PULL_Enum;
21633 
21634 /* ============================================  GPIO PADREGB PAD5RSEL [14..15]  ============================================= */
21635 typedef enum {                                  /*!< GPIO_PADREGB_PAD5RSEL                                                     */
21636   GPIO_PADREGB_PAD5RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
21637   GPIO_PADREGB_PAD5RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
21638   GPIO_PADREGB_PAD5RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
21639   GPIO_PADREGB_PAD5RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
21640 } GPIO_PADREGB_PAD5RSEL_Enum;
21641 
21642 /* ===========================================  GPIO PADREGB PAD5FNCSEL [11..13]  ============================================ */
21643 typedef enum {                                  /*!< GPIO_PADREGB_PAD5FNCSEL                                                   */
21644   GPIO_PADREGB_PAD5FNCSEL_M0SCL        = 0,     /*!< M0SCL : Configure as the IOMSTR0 I2C SCL signal                           */
21645   GPIO_PADREGB_PAD5FNCSEL_M0SCK        = 1,     /*!< M0SCK : Configure as the IOMSTR0 SPI SCK signal                           */
21646   GPIO_PADREGB_PAD5FNCSEL_UA0RTS       = 2,     /*!< UA0RTS : Configure as the UART0 RTS signal output                         */
21647   GPIO_PADREGB_PAD5FNCSEL_GPIO5        = 3,     /*!< GPIO5 : Configure as GPIO5                                                */
21648   GPIO_PADREGB_PAD5FNCSEL_EXTHFA       = 5,     /*!< EXTHFA : Configure as the External HFA input clock                        */
21649   GPIO_PADREGB_PAD5FNCSEL_CT8          = 7,     /*!< CT8 : CTIMER connection 8                                                 */
21650 } GPIO_PADREGB_PAD5FNCSEL_Enum;
21651 
21652 /* ============================================  GPIO PADREGB PAD5STRNG [10..10]  ============================================ */
21653 typedef enum {                                  /*!< GPIO_PADREGB_PAD5STRNG                                                    */
21654   GPIO_PADREGB_PAD5STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
21655   GPIO_PADREGB_PAD5STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
21656 } GPIO_PADREGB_PAD5STRNG_Enum;
21657 
21658 /* =============================================  GPIO PADREGB PAD5INPEN [9..9]  ============================================= */
21659 typedef enum {                                  /*!< GPIO_PADREGB_PAD5INPEN                                                    */
21660   GPIO_PADREGB_PAD5INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
21661   GPIO_PADREGB_PAD5INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
21662 } GPIO_PADREGB_PAD5INPEN_Enum;
21663 
21664 /* =============================================  GPIO PADREGB PAD5PULL [8..8]  ============================================== */
21665 typedef enum {                                  /*!< GPIO_PADREGB_PAD5PULL                                                     */
21666   GPIO_PADREGB_PAD5PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
21667   GPIO_PADREGB_PAD5PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
21668 } GPIO_PADREGB_PAD5PULL_Enum;
21669 
21670 /* ============================================  GPIO PADREGB PAD4FNCSEL [3..5]  ============================================= */
21671 typedef enum {                                  /*!< GPIO_PADREGB_PAD4FNCSEL                                                   */
21672   GPIO_PADREGB_PAD4FNCSEL_UA0CTS       = 0,     /*!< UA0CTS : Configure as the UART0 CTS input signal                          */
21673   GPIO_PADREGB_PAD4FNCSEL_SLINT        = 1,     /*!< SLINT : Configure as the IOSLAVE interrupt out signal                     */
21674   GPIO_PADREGB_PAD4FNCSEL_NCE4         = 2,     /*!< NCE4 : IOM/SPI nCE group 4                                                */
21675   GPIO_PADREGB_PAD4FNCSEL_GPIO4        = 3,     /*!< GPIO4 : Configure as GPIO4                                                */
21676   GPIO_PADREGB_PAD4FNCSEL_UART0RX      = 5,     /*!< UART0RX : Configure as the UART0 RX input                                 */
21677   GPIO_PADREGB_PAD4FNCSEL_CT17         = 6,     /*!< CT17 : CTIMER connection 17                                               */
21678   GPIO_PADREGB_PAD4FNCSEL_MSPI2        = 7,     /*!< MSPI2 : MSPI data connection 2                                            */
21679 } GPIO_PADREGB_PAD4FNCSEL_Enum;
21680 
21681 /* =============================================  GPIO PADREGB PAD4STRNG [2..2]  ============================================= */
21682 typedef enum {                                  /*!< GPIO_PADREGB_PAD4STRNG                                                    */
21683   GPIO_PADREGB_PAD4STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
21684   GPIO_PADREGB_PAD4STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
21685 } GPIO_PADREGB_PAD4STRNG_Enum;
21686 
21687 /* =============================================  GPIO PADREGB PAD4INPEN [1..1]  ============================================= */
21688 typedef enum {                                  /*!< GPIO_PADREGB_PAD4INPEN                                                    */
21689   GPIO_PADREGB_PAD4INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
21690   GPIO_PADREGB_PAD4INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
21691 } GPIO_PADREGB_PAD4INPEN_Enum;
21692 
21693 /* =============================================  GPIO PADREGB PAD4PULL [0..0]  ============================================== */
21694 typedef enum {                                  /*!< GPIO_PADREGB_PAD4PULL                                                     */
21695   GPIO_PADREGB_PAD4PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
21696   GPIO_PADREGB_PAD4PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
21697 } GPIO_PADREGB_PAD4PULL_Enum;
21698 
21699 /* ========================================================  PADREGC  ======================================================== */
21700 /* ===========================================  GPIO PADREGC PAD11FNCSEL [27..29]  =========================================== */
21701 typedef enum {                                  /*!< GPIO_PADREGC_PAD11FNCSEL                                                  */
21702   GPIO_PADREGC_PAD11FNCSEL_ADCSE2      = 0,     /*!< ADCSE2 : Configure as the analog input for ADC single ended
21703                                                      input 2                                                                   */
21704   GPIO_PADREGC_PAD11FNCSEL_NCE11       = 1,     /*!< NCE11 : IOM/MSPI nCE group 11                                             */
21705   GPIO_PADREGC_PAD11FNCSEL_CT31        = 2,     /*!< CT31 : CTIMER connection 31                                               */
21706   GPIO_PADREGC_PAD11FNCSEL_GPIO11      = 3,     /*!< GPIO11 : Configure as GPIO11                                              */
21707   GPIO_PADREGC_PAD11FNCSEL_SLINT       = 4,     /*!< SLINT : Configure as the IOSLAVE interrupt out signal                     */
21708   GPIO_PADREGC_PAD11FNCSEL_UA1CTS      = 5,     /*!< UA1CTS : Configure as the UART1 CTS input signal                          */
21709   GPIO_PADREGC_PAD11FNCSEL_UART0RX     = 6,     /*!< UART0RX : Configure as the UART0 RX input signal                          */
21710   GPIO_PADREGC_PAD11FNCSEL_PDM_DATA    = 7,     /*!< PDM_DATA : Configure as the PDM Data input signal                         */
21711 } GPIO_PADREGC_PAD11FNCSEL_Enum;
21712 
21713 /* ===========================================  GPIO PADREGC PAD11STRNG [26..26]  ============================================ */
21714 typedef enum {                                  /*!< GPIO_PADREGC_PAD11STRNG                                                   */
21715   GPIO_PADREGC_PAD11STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21716   GPIO_PADREGC_PAD11STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21717 } GPIO_PADREGC_PAD11STRNG_Enum;
21718 
21719 /* ===========================================  GPIO PADREGC PAD11INPEN [25..25]  ============================================ */
21720 typedef enum {                                  /*!< GPIO_PADREGC_PAD11INPEN                                                   */
21721   GPIO_PADREGC_PAD11INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21722   GPIO_PADREGC_PAD11INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21723 } GPIO_PADREGC_PAD11INPEN_Enum;
21724 
21725 /* ============================================  GPIO PADREGC PAD11PULL [24..24]  ============================================ */
21726 typedef enum {                                  /*!< GPIO_PADREGC_PAD11PULL                                                    */
21727   GPIO_PADREGC_PAD11PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21728   GPIO_PADREGC_PAD11PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21729 } GPIO_PADREGC_PAD11PULL_Enum;
21730 
21731 /* ===========================================  GPIO PADREGC PAD10FNCSEL [19..21]  =========================================== */
21732 typedef enum {                                  /*!< GPIO_PADREGC_PAD10FNCSEL                                                  */
21733   GPIO_PADREGC_PAD10FNCSEL_M1MOSI      = 1,     /*!< M1MOSI : Configure as the IOMSTR1 SPI MOSI signal                         */
21734   GPIO_PADREGC_PAD10FNCSEL_NCE10       = 2,     /*!< NCE10 : IOM/MSPI nCE group 10                                             */
21735   GPIO_PADREGC_PAD10FNCSEL_GPIO10      = 3,     /*!< GPIO10 : Configure as GPIO10                                              */
21736   GPIO_PADREGC_PAD10FNCSEL_PDMCLK      = 4,     /*!< PDMCLK : PDM serial clock out                                             */
21737   GPIO_PADREGC_PAD10FNCSEL_UA1RTS      = 5,     /*!< UA1RTS : Configure as the UART1 RTS output signal                         */
21738 } GPIO_PADREGC_PAD10FNCSEL_Enum;
21739 
21740 /* ===========================================  GPIO PADREGC PAD10STRNG [18..18]  ============================================ */
21741 typedef enum {                                  /*!< GPIO_PADREGC_PAD10STRNG                                                   */
21742   GPIO_PADREGC_PAD10STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21743   GPIO_PADREGC_PAD10STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21744 } GPIO_PADREGC_PAD10STRNG_Enum;
21745 
21746 /* ===========================================  GPIO PADREGC PAD10INPEN [17..17]  ============================================ */
21747 typedef enum {                                  /*!< GPIO_PADREGC_PAD10INPEN                                                   */
21748   GPIO_PADREGC_PAD10INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21749   GPIO_PADREGC_PAD10INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21750 } GPIO_PADREGC_PAD10INPEN_Enum;
21751 
21752 /* ============================================  GPIO PADREGC PAD10PULL [16..16]  ============================================ */
21753 typedef enum {                                  /*!< GPIO_PADREGC_PAD10PULL                                                    */
21754   GPIO_PADREGC_PAD10PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21755   GPIO_PADREGC_PAD10PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21756 } GPIO_PADREGC_PAD10PULL_Enum;
21757 
21758 /* ============================================  GPIO PADREGC PAD9RSEL [14..15]  ============================================= */
21759 typedef enum {                                  /*!< GPIO_PADREGC_PAD9RSEL                                                     */
21760   GPIO_PADREGC_PAD9RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
21761   GPIO_PADREGC_PAD9RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
21762   GPIO_PADREGC_PAD9RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
21763   GPIO_PADREGC_PAD9RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
21764 } GPIO_PADREGC_PAD9RSEL_Enum;
21765 
21766 /* ===========================================  GPIO PADREGC PAD9FNCSEL [11..13]  ============================================ */
21767 typedef enum {                                  /*!< GPIO_PADREGC_PAD9FNCSEL                                                   */
21768   GPIO_PADREGC_PAD9FNCSEL_M1SDAWIR3    = 0,     /*!< M1SDAWIR3 : Configure as the IOMSTR1 I2C SDA or SPI WIR3 signal           */
21769   GPIO_PADREGC_PAD9FNCSEL_M1MISO       = 1,     /*!< M1MISO : Configure as the IOMSTR1 SPI MISO signal                         */
21770   GPIO_PADREGC_PAD9FNCSEL_NCE9         = 2,     /*!< NCE9 : IOM/MSPI nCE group 9                                               */
21771   GPIO_PADREGC_PAD9FNCSEL_GPIO9        = 3,     /*!< GPIO9 : Configure as GPIO9                                                */
21772   GPIO_PADREGC_PAD9FNCSEL_SCCIO        = 4,     /*!< SCCIO : SCARD data I/O connection                                         */
21773   GPIO_PADREGC_PAD9FNCSEL_UART1RX      = 6,     /*!< UART1RX : Configure as UART1 RX input signal                              */
21774 } GPIO_PADREGC_PAD9FNCSEL_Enum;
21775 
21776 /* ============================================  GPIO PADREGC PAD9STRNG [10..10]  ============================================ */
21777 typedef enum {                                  /*!< GPIO_PADREGC_PAD9STRNG                                                    */
21778   GPIO_PADREGC_PAD9STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
21779   GPIO_PADREGC_PAD9STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
21780 } GPIO_PADREGC_PAD9STRNG_Enum;
21781 
21782 /* =============================================  GPIO PADREGC PAD9INPEN [9..9]  ============================================= */
21783 typedef enum {                                  /*!< GPIO_PADREGC_PAD9INPEN                                                    */
21784   GPIO_PADREGC_PAD9INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
21785   GPIO_PADREGC_PAD9INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
21786 } GPIO_PADREGC_PAD9INPEN_Enum;
21787 
21788 /* =============================================  GPIO PADREGC PAD9PULL [8..8]  ============================================== */
21789 typedef enum {                                  /*!< GPIO_PADREGC_PAD9PULL                                                     */
21790   GPIO_PADREGC_PAD9PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
21791   GPIO_PADREGC_PAD9PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
21792 } GPIO_PADREGC_PAD9PULL_Enum;
21793 
21794 /* =============================================  GPIO PADREGC PAD8RSEL [6..7]  ============================================== */
21795 typedef enum {                                  /*!< GPIO_PADREGC_PAD8RSEL                                                     */
21796   GPIO_PADREGC_PAD8RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
21797   GPIO_PADREGC_PAD8RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
21798   GPIO_PADREGC_PAD8RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
21799   GPIO_PADREGC_PAD8RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
21800 } GPIO_PADREGC_PAD8RSEL_Enum;
21801 
21802 /* ============================================  GPIO PADREGC PAD8FNCSEL [3..5]  ============================================= */
21803 typedef enum {                                  /*!< GPIO_PADREGC_PAD8FNCSEL                                                   */
21804   GPIO_PADREGC_PAD8FNCSEL_M1SCL        = 0,     /*!< M1SCL : Configure as the IOMSTR1 I2C SCL signal                           */
21805   GPIO_PADREGC_PAD8FNCSEL_M1SCK        = 1,     /*!< M1SCK : Configure as the IOMSTR1 SPI SCK signal                           */
21806   GPIO_PADREGC_PAD8FNCSEL_NCE8         = 2,     /*!< NCE8 : IOM/MSPI nCE group 8                                               */
21807   GPIO_PADREGC_PAD8FNCSEL_GPIO8        = 3,     /*!< GPIO8 : Configure as GPIO8                                                */
21808   GPIO_PADREGC_PAD8FNCSEL_SCCLK        = 4,     /*!< SCCLK : SCARD serial clock output                                         */
21809   GPIO_PADREGC_PAD8FNCSEL_UART1TX      = 6,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
21810 } GPIO_PADREGC_PAD8FNCSEL_Enum;
21811 
21812 /* =============================================  GPIO PADREGC PAD8STRNG [2..2]  ============================================= */
21813 typedef enum {                                  /*!< GPIO_PADREGC_PAD8STRNG                                                    */
21814   GPIO_PADREGC_PAD8STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
21815   GPIO_PADREGC_PAD8STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
21816 } GPIO_PADREGC_PAD8STRNG_Enum;
21817 
21818 /* =============================================  GPIO PADREGC PAD8INPEN [1..1]  ============================================= */
21819 typedef enum {                                  /*!< GPIO_PADREGC_PAD8INPEN                                                    */
21820   GPIO_PADREGC_PAD8INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
21821   GPIO_PADREGC_PAD8INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
21822 } GPIO_PADREGC_PAD8INPEN_Enum;
21823 
21824 /* =============================================  GPIO PADREGC PAD8PULL [0..0]  ============================================== */
21825 typedef enum {                                  /*!< GPIO_PADREGC_PAD8PULL                                                     */
21826   GPIO_PADREGC_PAD8PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
21827   GPIO_PADREGC_PAD8PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
21828 } GPIO_PADREGC_PAD8PULL_Enum;
21829 
21830 /* ========================================================  PADREGD  ======================================================== */
21831 /* ===========================================  GPIO PADREGD PAD15FNCSEL [27..29]  =========================================== */
21832 typedef enum {                                  /*!< GPIO_PADREGD_PAD15FNCSEL                                                  */
21833   GPIO_PADREGD_PAD15FNCSEL_ADCD1N      = 0,     /*!< ADCD1N : Configure as the analog ADC differential pair 1 N input
21834                                                      signal                                                                    */
21835   GPIO_PADREGD_PAD15FNCSEL_NCE15       = 1,     /*!< NCE15 : IOM/MSPI nCE group 15                                             */
21836   GPIO_PADREGD_PAD15FNCSEL_UART1RX     = 2,     /*!< UART1RX : Configure as the UART1 RX signal                                */
21837   GPIO_PADREGD_PAD15FNCSEL_GPIO15      = 3,     /*!< GPIO15 : Configure as GPIO15                                              */
21838   GPIO_PADREGD_PAD15FNCSEL_PDMDATA     = 4,     /*!< PDMDATA : PDM serial data input                                           */
21839   GPIO_PADREGD_PAD15FNCSEL_EXTXT       = 5,     /*!< EXTXT : Configure as the external XTAL oscillator input                   */
21840   GPIO_PADREGD_PAD15FNCSEL_SWDIO       = 6,     /*!< SWDIO : Configure as an alternate port for the SWDIO I/O signal           */
21841   GPIO_PADREGD_PAD15FNCSEL_SWO         = 7,     /*!< SWO : Configure as an SWO (Serial Wire Trace output)                      */
21842 } GPIO_PADREGD_PAD15FNCSEL_Enum;
21843 
21844 /* ===========================================  GPIO PADREGD PAD15STRNG [26..26]  ============================================ */
21845 typedef enum {                                  /*!< GPIO_PADREGD_PAD15STRNG                                                   */
21846   GPIO_PADREGD_PAD15STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21847   GPIO_PADREGD_PAD15STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21848 } GPIO_PADREGD_PAD15STRNG_Enum;
21849 
21850 /* ===========================================  GPIO PADREGD PAD15INPEN [25..25]  ============================================ */
21851 typedef enum {                                  /*!< GPIO_PADREGD_PAD15INPEN                                                   */
21852   GPIO_PADREGD_PAD15INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21853   GPIO_PADREGD_PAD15INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21854 } GPIO_PADREGD_PAD15INPEN_Enum;
21855 
21856 /* ============================================  GPIO PADREGD PAD15PULL [24..24]  ============================================ */
21857 typedef enum {                                  /*!< GPIO_PADREGD_PAD15PULL                                                    */
21858   GPIO_PADREGD_PAD15PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21859   GPIO_PADREGD_PAD15PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21860 } GPIO_PADREGD_PAD15PULL_Enum;
21861 
21862 /* ===========================================  GPIO PADREGD PAD14FNCSEL [19..21]  =========================================== */
21863 typedef enum {                                  /*!< GPIO_PADREGD_PAD14FNCSEL                                                  */
21864   GPIO_PADREGD_PAD14FNCSEL_ADCD1P      = 0,     /*!< ADCD1P : Configure as the analog ADC differential pair 1 P input
21865                                                      signal                                                                    */
21866   GPIO_PADREGD_PAD14FNCSEL_NCE14       = 1,     /*!< NCE14 : IOM/MSPI nCE group 14                                             */
21867   GPIO_PADREGD_PAD14FNCSEL_UART1TX     = 2,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
21868   GPIO_PADREGD_PAD14FNCSEL_GPIO14      = 3,     /*!< GPIO14 : Configure as GPIO14                                              */
21869   GPIO_PADREGD_PAD14FNCSEL_PDMCLK      = 4,     /*!< PDMCLK : PDM serial clock output                                          */
21870   GPIO_PADREGD_PAD14FNCSEL_EXTHFS      = 5,     /*!< EXTHFS : Configure as the External HFRC oscillator input select           */
21871   GPIO_PADREGD_PAD14FNCSEL_SWDCK       = 6,     /*!< SWDCK : Configure as the alternate input for the SWDCK input
21872                                                      signal                                                                    */
21873   GPIO_PADREGD_PAD14FNCSEL_32kHzXT     = 7,     /*!< 32kHzXT : Configure as the 32kHz crystal output signal                    */
21874 } GPIO_PADREGD_PAD14FNCSEL_Enum;
21875 
21876 /* ===========================================  GPIO PADREGD PAD14STRNG [18..18]  ============================================ */
21877 typedef enum {                                  /*!< GPIO_PADREGD_PAD14STRNG                                                   */
21878   GPIO_PADREGD_PAD14STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21879   GPIO_PADREGD_PAD14STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21880 } GPIO_PADREGD_PAD14STRNG_Enum;
21881 
21882 /* ===========================================  GPIO PADREGD PAD14INPEN [17..17]  ============================================ */
21883 typedef enum {                                  /*!< GPIO_PADREGD_PAD14INPEN                                                   */
21884   GPIO_PADREGD_PAD14INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21885   GPIO_PADREGD_PAD14INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21886 } GPIO_PADREGD_PAD14INPEN_Enum;
21887 
21888 /* ============================================  GPIO PADREGD PAD14PULL [16..16]  ============================================ */
21889 typedef enum {                                  /*!< GPIO_PADREGD_PAD14PULL                                                    */
21890   GPIO_PADREGD_PAD14PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21891   GPIO_PADREGD_PAD14PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21892 } GPIO_PADREGD_PAD14PULL_Enum;
21893 
21894 /* ===========================================  GPIO PADREGD PAD13FNCSEL [11..13]  =========================================== */
21895 typedef enum {                                  /*!< GPIO_PADREGD_PAD13FNCSEL                                                  */
21896   GPIO_PADREGD_PAD13FNCSEL_ADCD0PSE8   = 0,     /*!< ADCD0PSE8 : Configure as the ADC Differential pair 0 P, or Single
21897                                                      Ended input 8 analog input signal. Determination of the
21898                                                      D0P vs SE8 usage is done when the particular channel is
21899                                                      selected within the ADC module                                            */
21900   GPIO_PADREGD_PAD13FNCSEL_NCE13       = 1,     /*!< NCE13 : IOM/MSPI nCE group 13                                             */
21901   GPIO_PADREGD_PAD13FNCSEL_CT2         = 2,     /*!< CT2 : CTIMER connection 2                                                 */
21902   GPIO_PADREGD_PAD13FNCSEL_GPIO13      = 3,     /*!< GPIO13 : Configure as GPIO13                                              */
21903   GPIO_PADREGD_PAD13FNCSEL_I2SBCLK     = 4,     /*!< I2SBCLK : I2C interface bit clock                                         */
21904   GPIO_PADREGD_PAD13FNCSEL_EXTHFB      = 5,     /*!< EXTHFB : Configure as the external HFRC oscillator input                  */
21905   GPIO_PADREGD_PAD13FNCSEL_UA0RTS      = 6,     /*!< UA0RTS : Configure as the UART0 RTS signal output                         */
21906   GPIO_PADREGD_PAD13FNCSEL_UART1RX     = 7,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
21907 } GPIO_PADREGD_PAD13FNCSEL_Enum;
21908 
21909 /* ===========================================  GPIO PADREGD PAD13STRNG [10..10]  ============================================ */
21910 typedef enum {                                  /*!< GPIO_PADREGD_PAD13STRNG                                                   */
21911   GPIO_PADREGD_PAD13STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21912   GPIO_PADREGD_PAD13STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21913 } GPIO_PADREGD_PAD13STRNG_Enum;
21914 
21915 /* ============================================  GPIO PADREGD PAD13INPEN [9..9]  ============================================= */
21916 typedef enum {                                  /*!< GPIO_PADREGD_PAD13INPEN                                                   */
21917   GPIO_PADREGD_PAD13INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21918   GPIO_PADREGD_PAD13INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21919 } GPIO_PADREGD_PAD13INPEN_Enum;
21920 
21921 /* =============================================  GPIO PADREGD PAD13PULL [8..8]  ============================================= */
21922 typedef enum {                                  /*!< GPIO_PADREGD_PAD13PULL                                                    */
21923   GPIO_PADREGD_PAD13PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21924   GPIO_PADREGD_PAD13PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21925 } GPIO_PADREGD_PAD13PULL_Enum;
21926 
21927 /* ============================================  GPIO PADREGD PAD12FNCSEL [3..5]  ============================================ */
21928 typedef enum {                                  /*!< GPIO_PADREGD_PAD12FNCSEL                                                  */
21929   GPIO_PADREGD_PAD12FNCSEL_ADCD0NSE9   = 0,     /*!< ADCD0NSE9 : Configure as the ADC Differential pair 0 N, or Single
21930                                                      Ended input 9 analog input signal. Determination of the
21931                                                      D0N vs SE9 usage is done when the particular channel is
21932                                                      selected within the ADC module                                            */
21933   GPIO_PADREGD_PAD12FNCSEL_NCE12       = 1,     /*!< NCE12 : IOM/MSPI nCE group 12                                             */
21934   GPIO_PADREGD_PAD12FNCSEL_CT0         = 2,     /*!< CT0 : CTIMER connection 0                                                 */
21935   GPIO_PADREGD_PAD12FNCSEL_GPIO12      = 3,     /*!< GPIO12 : Configure as GPIO12                                              */
21936   GPIO_PADREGD_PAD12FNCSEL_PDMCLK      = 5,     /*!< PDMCLK : PDM serial clock output                                          */
21937   GPIO_PADREGD_PAD12FNCSEL_UA0CTS      = 6,     /*!< UA0CTS : Configure as the UART0 CTS input signal                          */
21938   GPIO_PADREGD_PAD12FNCSEL_UART1TX     = 7,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
21939 } GPIO_PADREGD_PAD12FNCSEL_Enum;
21940 
21941 /* ============================================  GPIO PADREGD PAD12STRNG [2..2]  ============================================= */
21942 typedef enum {                                  /*!< GPIO_PADREGD_PAD12STRNG                                                   */
21943   GPIO_PADREGD_PAD12STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21944   GPIO_PADREGD_PAD12STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21945 } GPIO_PADREGD_PAD12STRNG_Enum;
21946 
21947 /* ============================================  GPIO PADREGD PAD12INPEN [1..1]  ============================================= */
21948 typedef enum {                                  /*!< GPIO_PADREGD_PAD12INPEN                                                   */
21949   GPIO_PADREGD_PAD12INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21950   GPIO_PADREGD_PAD12INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21951 } GPIO_PADREGD_PAD12INPEN_Enum;
21952 
21953 /* =============================================  GPIO PADREGD PAD12PULL [0..0]  ============================================= */
21954 typedef enum {                                  /*!< GPIO_PADREGD_PAD12PULL                                                    */
21955   GPIO_PADREGD_PAD12PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21956   GPIO_PADREGD_PAD12PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21957 } GPIO_PADREGD_PAD12PULL_Enum;
21958 
21959 /* ========================================================  PADREGE  ======================================================== */
21960 /* ===========================================  GPIO PADREGE PAD19FNCSEL [27..29]  =========================================== */
21961 typedef enum {                                  /*!< GPIO_PADREGE_PAD19FNCSEL                                                  */
21962   GPIO_PADREGE_PAD19FNCSEL_CMPRF0      = 0,     /*!< CMPRF0 : Configure as the analog comparator reference 0 signal            */
21963   GPIO_PADREGE_PAD19FNCSEL_NCE19       = 1,     /*!< NCE19 : IOM/MSPI nCE group 19                                             */
21964   GPIO_PADREGE_PAD19FNCSEL_CT6         = 2,     /*!< CT6 : CTIMER connection 6                                                 */
21965   GPIO_PADREGE_PAD19FNCSEL_GPIO19      = 3,     /*!< GPIO19 : Configure as GPIO19                                              */
21966   GPIO_PADREGE_PAD19FNCSEL_SCCLK       = 4,     /*!< SCCLK : SCARD serial clock                                                */
21967   GPIO_PADREGE_PAD19FNCSEL_ANATEST1    = 5,     /*!< ANATEST1 : Configure as the ANATEST1 I/O signal                           */
21968   GPIO_PADREGE_PAD19FNCSEL_UART1RX     = 6,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
21969   GPIO_PADREGE_PAD19FNCSEL_I2SBCLK     = 7,     /*!< I2SBCLK : Configure as the PDM I2S bit clock input signal                 */
21970 } GPIO_PADREGE_PAD19FNCSEL_Enum;
21971 
21972 /* ===========================================  GPIO PADREGE PAD19STRNG [26..26]  ============================================ */
21973 typedef enum {                                  /*!< GPIO_PADREGE_PAD19STRNG                                                   */
21974   GPIO_PADREGE_PAD19STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21975   GPIO_PADREGE_PAD19STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21976 } GPIO_PADREGE_PAD19STRNG_Enum;
21977 
21978 /* ===========================================  GPIO PADREGE PAD19INPEN [25..25]  ============================================ */
21979 typedef enum {                                  /*!< GPIO_PADREGE_PAD19INPEN                                                   */
21980   GPIO_PADREGE_PAD19INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21981   GPIO_PADREGE_PAD19INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21982 } GPIO_PADREGE_PAD19INPEN_Enum;
21983 
21984 /* ============================================  GPIO PADREGE PAD19PULL [24..24]  ============================================ */
21985 typedef enum {                                  /*!< GPIO_PADREGE_PAD19PULL                                                    */
21986   GPIO_PADREGE_PAD19PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21987   GPIO_PADREGE_PAD19PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21988 } GPIO_PADREGE_PAD19PULL_Enum;
21989 
21990 /* ===========================================  GPIO PADREGE PAD18FNCSEL [19..21]  =========================================== */
21991 typedef enum {                                  /*!< GPIO_PADREGE_PAD18FNCSEL                                                  */
21992   GPIO_PADREGE_PAD18FNCSEL_CMPIN1      = 0,     /*!< CMPIN1 : Configure as the analog comparator input 1 signal                */
21993   GPIO_PADREGE_PAD18FNCSEL_NCE18       = 1,     /*!< NCE18 : IOM/MSPI nCE group 18                                             */
21994   GPIO_PADREGE_PAD18FNCSEL_CT4         = 2,     /*!< CT4 : CTIMER connection 4                                                 */
21995   GPIO_PADREGE_PAD18FNCSEL_GPIO18      = 3,     /*!< GPIO18 : Configure as GPIO18                                              */
21996   GPIO_PADREGE_PAD18FNCSEL_UA0RTS      = 4,     /*!< UA0RTS : Configure as UART0 RTS output signal                             */
21997   GPIO_PADREGE_PAD18FNCSEL_ANATEST2    = 5,     /*!< ANATEST2 : Configure as ANATEST2 I/O signal                               */
21998   GPIO_PADREGE_PAD18FNCSEL_UART1TX     = 6,     /*!< UART1TX : Configure as UART1 TX output signal                             */
21999   GPIO_PADREGE_PAD18FNCSEL_SCCIO       = 7,     /*!< SCCIO : SCARD data input/output connection                                */
22000 } GPIO_PADREGE_PAD18FNCSEL_Enum;
22001 
22002 /* ===========================================  GPIO PADREGE PAD18STRNG [18..18]  ============================================ */
22003 typedef enum {                                  /*!< GPIO_PADREGE_PAD18STRNG                                                   */
22004   GPIO_PADREGE_PAD18STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22005   GPIO_PADREGE_PAD18STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22006 } GPIO_PADREGE_PAD18STRNG_Enum;
22007 
22008 /* ===========================================  GPIO PADREGE PAD18INPEN [17..17]  ============================================ */
22009 typedef enum {                                  /*!< GPIO_PADREGE_PAD18INPEN                                                   */
22010   GPIO_PADREGE_PAD18INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22011   GPIO_PADREGE_PAD18INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22012 } GPIO_PADREGE_PAD18INPEN_Enum;
22013 
22014 /* ============================================  GPIO PADREGE PAD18PULL [16..16]  ============================================ */
22015 typedef enum {                                  /*!< GPIO_PADREGE_PAD18PULL                                                    */
22016   GPIO_PADREGE_PAD18PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22017   GPIO_PADREGE_PAD18PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22018 } GPIO_PADREGE_PAD18PULL_Enum;
22019 
22020 /* ===========================================  GPIO PADREGE PAD17FNCSEL [11..13]  =========================================== */
22021 typedef enum {                                  /*!< GPIO_PADREGE_PAD17FNCSEL                                                  */
22022   GPIO_PADREGE_PAD17FNCSEL_CMPRF1      = 0,     /*!< CMPRF1 : Configure as the analog comparator reference signal
22023                                                      1 input signal                                                            */
22024   GPIO_PADREGE_PAD17FNCSEL_NCE17       = 1,     /*!< NCE17 : IOM/MSPI nCE group 17                                             */
22025   GPIO_PADREGE_PAD17FNCSEL_TRIG1       = 2,     /*!< TRIG1 : Configure as the ADC Trigger 1 signal                             */
22026   GPIO_PADREGE_PAD17FNCSEL_GPIO17      = 3,     /*!< GPIO17 : Configure as GPIO17                                              */
22027   GPIO_PADREGE_PAD17FNCSEL_SCCCLK      = 4,     /*!< SCCCLK : SCARD serial clock output                                        */
22028   GPIO_PADREGE_PAD17FNCSEL_UART0RX     = 6,     /*!< UART0RX : Configure as UART0 RX input signal                              */
22029   GPIO_PADREGE_PAD17FNCSEL_UA1CTS      = 7,     /*!< UA1CTS : Configure as UART1 CTS input signal                              */
22030 } GPIO_PADREGE_PAD17FNCSEL_Enum;
22031 
22032 /* ===========================================  GPIO PADREGE PAD17STRNG [10..10]  ============================================ */
22033 typedef enum {                                  /*!< GPIO_PADREGE_PAD17STRNG                                                   */
22034   GPIO_PADREGE_PAD17STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22035   GPIO_PADREGE_PAD17STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22036 } GPIO_PADREGE_PAD17STRNG_Enum;
22037 
22038 /* ============================================  GPIO PADREGE PAD17INPEN [9..9]  ============================================= */
22039 typedef enum {                                  /*!< GPIO_PADREGE_PAD17INPEN                                                   */
22040   GPIO_PADREGE_PAD17INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22041   GPIO_PADREGE_PAD17INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22042 } GPIO_PADREGE_PAD17INPEN_Enum;
22043 
22044 /* =============================================  GPIO PADREGE PAD17PULL [8..8]  ============================================= */
22045 typedef enum {                                  /*!< GPIO_PADREGE_PAD17PULL                                                    */
22046   GPIO_PADREGE_PAD17PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22047   GPIO_PADREGE_PAD17PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22048 } GPIO_PADREGE_PAD17PULL_Enum;
22049 
22050 /* ============================================  GPIO PADREGE PAD16FNCSEL [3..5]  ============================================ */
22051 typedef enum {                                  /*!< GPIO_PADREGE_PAD16FNCSEL                                                  */
22052   GPIO_PADREGE_PAD16FNCSEL_ADCSE0      = 0,     /*!< ADCSE0 : Configure as the analog ADC single ended port 0 input
22053                                                      signal                                                                    */
22054   GPIO_PADREGE_PAD16FNCSEL_NCE16       = 1,     /*!< NCE16 : IOM/MSPI nCE group 16                                             */
22055   GPIO_PADREGE_PAD16FNCSEL_TRIG0       = 2,     /*!< TRIG0 : Configure as the ADC Trigger 0 signal                             */
22056   GPIO_PADREGE_PAD16FNCSEL_GPIO16      = 3,     /*!< GPIO16 : Configure as GPIO16                                              */
22057   GPIO_PADREGE_PAD16FNCSEL_SCCRST      = 4,     /*!< SCCRST : SCARD reset output                                               */
22058   GPIO_PADREGE_PAD16FNCSEL_CMPIN0      = 5,     /*!< CMPIN0 : Configure as comparator input 0 signal                           */
22059   GPIO_PADREGE_PAD16FNCSEL_UART0TX     = 6,     /*!< UART0TX : Configure as UART0 TX output signal                             */
22060   GPIO_PADREGE_PAD16FNCSEL_UA1RTS      = 7,     /*!< UA1RTS : Configure as UART1 RTS output signal                             */
22061 } GPIO_PADREGE_PAD16FNCSEL_Enum;
22062 
22063 /* ============================================  GPIO PADREGE PAD16STRNG [2..2]  ============================================= */
22064 typedef enum {                                  /*!< GPIO_PADREGE_PAD16STRNG                                                   */
22065   GPIO_PADREGE_PAD16STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22066   GPIO_PADREGE_PAD16STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22067 } GPIO_PADREGE_PAD16STRNG_Enum;
22068 
22069 /* ============================================  GPIO PADREGE PAD16INPEN [1..1]  ============================================= */
22070 typedef enum {                                  /*!< GPIO_PADREGE_PAD16INPEN                                                   */
22071   GPIO_PADREGE_PAD16INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22072   GPIO_PADREGE_PAD16INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22073 } GPIO_PADREGE_PAD16INPEN_Enum;
22074 
22075 /* =============================================  GPIO PADREGE PAD16PULL [0..0]  ============================================= */
22076 typedef enum {                                  /*!< GPIO_PADREGE_PAD16PULL                                                    */
22077   GPIO_PADREGE_PAD16PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22078   GPIO_PADREGE_PAD16PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22079 } GPIO_PADREGE_PAD16PULL_Enum;
22080 
22081 /* ========================================================  PADREGF  ======================================================== */
22082 /* ===========================================  GPIO PADREGF PAD23FNCSEL [27..29]  =========================================== */
22083 typedef enum {                                  /*!< GPIO_PADREGF_PAD23FNCSEL                                                  */
22084   GPIO_PADREGF_PAD23FNCSEL_UART0RX     = 0,     /*!< UART0RX : Configure as the UART0 RX signal                                */
22085   GPIO_PADREGF_PAD23FNCSEL_NCE23       = 1,     /*!< NCE23 : IOM/MSPI nCE group 23                                             */
22086   GPIO_PADREGF_PAD23FNCSEL_CT14        = 2,     /*!< CT14 : CTIMER connection 14                                               */
22087   GPIO_PADREGF_PAD23FNCSEL_GPIO23      = 3,     /*!< GPIO23 : Configure as GPIO23                                              */
22088   GPIO_PADREGF_PAD23FNCSEL_I2SWCLK     = 4,     /*!< I2SWCLK : I2S word clock input                                            */
22089   GPIO_PADREGF_PAD23FNCSEL_CMPOUT      = 5,     /*!< CMPOUT : Configure as voltage comparator output                           */
22090   GPIO_PADREGF_PAD23FNCSEL_MSPI3       = 6,     /*!< MSPI3 : MSPI data connection 3                                            */
22091   GPIO_PADREGF_PAD23FNCSEL_EXTXT       = 7,     /*!< EXTXT : External XTAL oscillator input                                    */
22092 } GPIO_PADREGF_PAD23FNCSEL_Enum;
22093 
22094 /* ===========================================  GPIO PADREGF PAD23STRNG [26..26]  ============================================ */
22095 typedef enum {                                  /*!< GPIO_PADREGF_PAD23STRNG                                                   */
22096   GPIO_PADREGF_PAD23STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22097   GPIO_PADREGF_PAD23STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22098 } GPIO_PADREGF_PAD23STRNG_Enum;
22099 
22100 /* ===========================================  GPIO PADREGF PAD23INPEN [25..25]  ============================================ */
22101 typedef enum {                                  /*!< GPIO_PADREGF_PAD23INPEN                                                   */
22102   GPIO_PADREGF_PAD23INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22103   GPIO_PADREGF_PAD23INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22104 } GPIO_PADREGF_PAD23INPEN_Enum;
22105 
22106 /* ============================================  GPIO PADREGF PAD23PULL [24..24]  ============================================ */
22107 typedef enum {                                  /*!< GPIO_PADREGF_PAD23PULL                                                    */
22108   GPIO_PADREGF_PAD23PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22109   GPIO_PADREGF_PAD23PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22110 } GPIO_PADREGF_PAD23PULL_Enum;
22111 
22112 /* ===========================================  GPIO PADREGF PAD22FNCSEL [19..21]  =========================================== */
22113 typedef enum {                                  /*!< GPIO_PADREGF_PAD22FNCSEL                                                  */
22114   GPIO_PADREGF_PAD22FNCSEL_UART0TX     = 0,     /*!< UART0TX : Configure as the UART0 TX signal                                */
22115   GPIO_PADREGF_PAD22FNCSEL_NCE22       = 1,     /*!< NCE22 : IOM/MSPI nCE group 22                                             */
22116   GPIO_PADREGF_PAD22FNCSEL_CT12        = 2,     /*!< CT12 : CTIMER connection 12                                               */
22117   GPIO_PADREGF_PAD22FNCSEL_GPIO22      = 3,     /*!< GPIO22 : Configure as GPIO22                                              */
22118   GPIO_PADREGF_PAD22FNCSEL_PDM_CLK     = 4,     /*!< PDM_CLK : Configure as the PDM CLK output                                 */
22119   GPIO_PADREGF_PAD22FNCSEL_EXTLF       = 5,     /*!< EXTLF : External LFRC input                                               */
22120   GPIO_PADREGF_PAD22FNCSEL_MSPI0       = 6,     /*!< MSPI0 : MSPI data connection 0                                            */
22121   GPIO_PADREGF_PAD22FNCSEL_SWO         = 7,     /*!< SWO : Configure as the serial trace data output signal                    */
22122 } GPIO_PADREGF_PAD22FNCSEL_Enum;
22123 
22124 /* ===========================================  GPIO PADREGF PAD22STRNG [18..18]  ============================================ */
22125 typedef enum {                                  /*!< GPIO_PADREGF_PAD22STRNG                                                   */
22126   GPIO_PADREGF_PAD22STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22127   GPIO_PADREGF_PAD22STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22128 } GPIO_PADREGF_PAD22STRNG_Enum;
22129 
22130 /* ===========================================  GPIO PADREGF PAD22INPEN [17..17]  ============================================ */
22131 typedef enum {                                  /*!< GPIO_PADREGF_PAD22INPEN                                                   */
22132   GPIO_PADREGF_PAD22INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22133   GPIO_PADREGF_PAD22INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22134 } GPIO_PADREGF_PAD22INPEN_Enum;
22135 
22136 /* ============================================  GPIO PADREGF PAD22PULL [16..16]  ============================================ */
22137 typedef enum {                                  /*!< GPIO_PADREGF_PAD22PULL                                                    */
22138   GPIO_PADREGF_PAD22PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22139   GPIO_PADREGF_PAD22PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22140 } GPIO_PADREGF_PAD22PULL_Enum;
22141 
22142 /* ===========================================  GPIO PADREGF PAD21FNCSEL [11..13]  =========================================== */
22143 typedef enum {                                  /*!< GPIO_PADREGF_PAD21FNCSEL                                                  */
22144   GPIO_PADREGF_PAD21FNCSEL_SWDIO       = 0,     /*!< SWDIO : Configure as the serial wire debug data signal                    */
22145   GPIO_PADREGF_PAD21FNCSEL_NCE21       = 1,     /*!< NCE21 : IOM/MSPI nCE group 21                                             */
22146   GPIO_PADREGF_PAD21FNCSEL_GPIO21      = 3,     /*!< GPIO21 : Configure as GPIO21                                              */
22147   GPIO_PADREGF_PAD21FNCSEL_UART0RX     = 4,     /*!< UART0RX : Configure as UART0 RX input signal                              */
22148   GPIO_PADREGF_PAD21FNCSEL_UART1RX     = 5,     /*!< UART1RX : Configure as UART1 RX input signal                              */
22149   GPIO_PADREGF_PAD21FNCSEL_I2SBCLK     = 6,     /*!< I2SBCLK : I2S byte clock input                                            */
22150   GPIO_PADREGF_PAD21FNCSEL_UA1CTS      = 7,     /*!< UA1CTS : Configure as UART1 CTS input signal                              */
22151 } GPIO_PADREGF_PAD21FNCSEL_Enum;
22152 
22153 /* ===========================================  GPIO PADREGF PAD21STRNG [10..10]  ============================================ */
22154 typedef enum {                                  /*!< GPIO_PADREGF_PAD21STRNG                                                   */
22155   GPIO_PADREGF_PAD21STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22156   GPIO_PADREGF_PAD21STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22157 } GPIO_PADREGF_PAD21STRNG_Enum;
22158 
22159 /* ============================================  GPIO PADREGF PAD21INPEN [9..9]  ============================================= */
22160 typedef enum {                                  /*!< GPIO_PADREGF_PAD21INPEN                                                   */
22161   GPIO_PADREGF_PAD21INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22162   GPIO_PADREGF_PAD21INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22163 } GPIO_PADREGF_PAD21INPEN_Enum;
22164 
22165 /* =============================================  GPIO PADREGF PAD21PULL [8..8]  ============================================= */
22166 typedef enum {                                  /*!< GPIO_PADREGF_PAD21PULL                                                    */
22167   GPIO_PADREGF_PAD21PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22168   GPIO_PADREGF_PAD21PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22169 } GPIO_PADREGF_PAD21PULL_Enum;
22170 
22171 /* ============================================  GPIO PADREGF PAD20FNCSEL [3..5]  ============================================ */
22172 typedef enum {                                  /*!< GPIO_PADREGF_PAD20FNCSEL                                                  */
22173   GPIO_PADREGF_PAD20FNCSEL_SWDCK       = 0,     /*!< SWDCK : Configure as the serial wire debug clock signal                   */
22174   GPIO_PADREGF_PAD20FNCSEL_NCE20       = 1,     /*!< NCE20 : IOM/MSPI nCE group 20                                             */
22175   GPIO_PADREGF_PAD20FNCSEL_GPIO20      = 3,     /*!< GPIO20 : Configure as GPIO20                                              */
22176   GPIO_PADREGF_PAD20FNCSEL_UART0TX     = 4,     /*!< UART0TX : Configure as UART0 TX output signal                             */
22177   GPIO_PADREGF_PAD20FNCSEL_UART1TX     = 5,     /*!< UART1TX : Configure as UART1 TX output signal                             */
22178   GPIO_PADREGF_PAD20FNCSEL_I2SBCLK     = 6,     /*!< I2SBCLK : I2S byte clock input                                            */
22179   GPIO_PADREGF_PAD20FNCSEL_UA1RTS      = 7,     /*!< UA1RTS : Configure as UART1 RTS output signal                             */
22180 } GPIO_PADREGF_PAD20FNCSEL_Enum;
22181 
22182 /* ============================================  GPIO PADREGF PAD20STRNG [2..2]  ============================================= */
22183 typedef enum {                                  /*!< GPIO_PADREGF_PAD20STRNG                                                   */
22184   GPIO_PADREGF_PAD20STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22185   GPIO_PADREGF_PAD20STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22186 } GPIO_PADREGF_PAD20STRNG_Enum;
22187 
22188 /* ============================================  GPIO PADREGF PAD20INPEN [1..1]  ============================================= */
22189 typedef enum {                                  /*!< GPIO_PADREGF_PAD20INPEN                                                   */
22190   GPIO_PADREGF_PAD20INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22191   GPIO_PADREGF_PAD20INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22192 } GPIO_PADREGF_PAD20INPEN_Enum;
22193 
22194 /* =============================================  GPIO PADREGF PAD20PULL [0..0]  ============================================= */
22195 typedef enum {                                  /*!< GPIO_PADREGF_PAD20PULL                                                    */
22196   GPIO_PADREGF_PAD20PULL_DIS           = 0,     /*!< DIS : Pulldown disabled                                                   */
22197   GPIO_PADREGF_PAD20PULL_EN            = 1,     /*!< EN : Pulldown enabled                                                     */
22198 } GPIO_PADREGF_PAD20PULL_Enum;
22199 
22200 /* ========================================================  PADREGG  ======================================================== */
22201 /* ============================================  GPIO PADREGG PAD27RSEL [30..31]  ============================================ */
22202 typedef enum {                                  /*!< GPIO_PADREGG_PAD27RSEL                                                    */
22203   GPIO_PADREGG_PAD27RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
22204   GPIO_PADREGG_PAD27RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
22205   GPIO_PADREGG_PAD27RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
22206   GPIO_PADREGG_PAD27RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
22207 } GPIO_PADREGG_PAD27RSEL_Enum;
22208 
22209 /* ===========================================  GPIO PADREGG PAD27FNCSEL [27..29]  =========================================== */
22210 typedef enum {                                  /*!< GPIO_PADREGG_PAD27FNCSEL                                                  */
22211   GPIO_PADREGG_PAD27FNCSEL_UART0RX     = 0,     /*!< UART0RX : Configure as UART0 RX input signal                              */
22212   GPIO_PADREGG_PAD27FNCSEL_NCE27       = 1,     /*!< NCE27 : IOM/MSPI nCE group 27                                             */
22213   GPIO_PADREGG_PAD27FNCSEL_CT5         = 2,     /*!< CT5 : CTIMER connection 5                                                 */
22214   GPIO_PADREGG_PAD27FNCSEL_GPIO27      = 3,     /*!< GPIO27 : Configure as GPIO27                                              */
22215   GPIO_PADREGG_PAD27FNCSEL_M2SCL       = 4,     /*!< M2SCL : Configure as I2C clock I/O signal from IOMSTR2                    */
22216   GPIO_PADREGG_PAD27FNCSEL_M2SCK       = 5,     /*!< M2SCK : Configure as SPI clock output signal from IOMSTR2                 */
22217 } GPIO_PADREGG_PAD27FNCSEL_Enum;
22218 
22219 /* ===========================================  GPIO PADREGG PAD27STRNG [26..26]  ============================================ */
22220 typedef enum {                                  /*!< GPIO_PADREGG_PAD27STRNG                                                   */
22221   GPIO_PADREGG_PAD27STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22222   GPIO_PADREGG_PAD27STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22223 } GPIO_PADREGG_PAD27STRNG_Enum;
22224 
22225 /* ===========================================  GPIO PADREGG PAD27INPEN [25..25]  ============================================ */
22226 typedef enum {                                  /*!< GPIO_PADREGG_PAD27INPEN                                                   */
22227   GPIO_PADREGG_PAD27INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22228   GPIO_PADREGG_PAD27INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22229 } GPIO_PADREGG_PAD27INPEN_Enum;
22230 
22231 /* ============================================  GPIO PADREGG PAD27PULL [24..24]  ============================================ */
22232 typedef enum {                                  /*!< GPIO_PADREGG_PAD27PULL                                                    */
22233   GPIO_PADREGG_PAD27PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22234   GPIO_PADREGG_PAD27PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22235 } GPIO_PADREGG_PAD27PULL_Enum;
22236 
22237 /* ===========================================  GPIO PADREGG PAD26FNCSEL [19..21]  =========================================== */
22238 typedef enum {                                  /*!< GPIO_PADREGG_PAD26FNCSEL                                                  */
22239   GPIO_PADREGG_PAD26FNCSEL_EXTHF       = 0,     /*!< EXTHF : Configure as the external HFRC oscillator input                   */
22240   GPIO_PADREGG_PAD26FNCSEL_NCE26       = 1,     /*!< NCE26 : IOM/MSPI nCE group 26                                             */
22241   GPIO_PADREGG_PAD26FNCSEL_CT3         = 2,     /*!< CT3 : CTIMER connection 3                                                 */
22242   GPIO_PADREGG_PAD26FNCSEL_GPIO26      = 3,     /*!< GPIO26 : Configure as GPIO26                                              */
22243   GPIO_PADREGG_PAD26FNCSEL_SCCRST      = 4,     /*!< SCCRST : SCARD reset output                                               */
22244   GPIO_PADREGG_PAD26FNCSEL_MSPI1       = 5,     /*!< MSPI1 : MSPI data connection 1                                            */
22245   GPIO_PADREGG_PAD26FNCSEL_UART0TX     = 6,     /*!< UART0TX : Configure as UART0 TX output signal                             */
22246   GPIO_PADREGG_PAD26FNCSEL_UA1CTS      = 7,     /*!< UA1CTS : Configure as UART1 CTS input signal                              */
22247 } GPIO_PADREGG_PAD26FNCSEL_Enum;
22248 
22249 /* ===========================================  GPIO PADREGG PAD26STRNG [18..18]  ============================================ */
22250 typedef enum {                                  /*!< GPIO_PADREGG_PAD26STRNG                                                   */
22251   GPIO_PADREGG_PAD26STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22252   GPIO_PADREGG_PAD26STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22253 } GPIO_PADREGG_PAD26STRNG_Enum;
22254 
22255 /* ===========================================  GPIO PADREGG PAD26INPEN [17..17]  ============================================ */
22256 typedef enum {                                  /*!< GPIO_PADREGG_PAD26INPEN                                                   */
22257   GPIO_PADREGG_PAD26INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22258   GPIO_PADREGG_PAD26INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22259 } GPIO_PADREGG_PAD26INPEN_Enum;
22260 
22261 /* ============================================  GPIO PADREGG PAD26PULL [16..16]  ============================================ */
22262 typedef enum {                                  /*!< GPIO_PADREGG_PAD26PULL                                                    */
22263   GPIO_PADREGG_PAD26PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22264   GPIO_PADREGG_PAD26PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22265 } GPIO_PADREGG_PAD26PULL_Enum;
22266 
22267 /* ============================================  GPIO PADREGG PAD25RSEL [14..15]  ============================================ */
22268 typedef enum {                                  /*!< GPIO_PADREGG_PAD25RSEL                                                    */
22269   GPIO_PADREGG_PAD25RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
22270   GPIO_PADREGG_PAD25RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
22271   GPIO_PADREGG_PAD25RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
22272   GPIO_PADREGG_PAD25RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
22273 } GPIO_PADREGG_PAD25RSEL_Enum;
22274 
22275 /* ===========================================  GPIO PADREGG PAD25FNCSEL [11..13]  =========================================== */
22276 typedef enum {                                  /*!< GPIO_PADREGG_PAD25FNCSEL                                                  */
22277   GPIO_PADREGG_PAD25FNCSEL_UART1RX     = 0,     /*!< UART1RX : Configure as UART1 RX input signal                              */
22278   GPIO_PADREGG_PAD25FNCSEL_NCE25       = 1,     /*!< NCE25 : IOM/MSPI nCE group 25                                             */
22279   GPIO_PADREGG_PAD25FNCSEL_CT1         = 2,     /*!< CT1 : CTIMER connection 1                                                 */
22280   GPIO_PADREGG_PAD25FNCSEL_GPIO25      = 3,     /*!< GPIO25 : Configure as GPIO25                                              */
22281   GPIO_PADREGG_PAD25FNCSEL_M2SDAWIR3   = 4,     /*!< M2SDAWIR3 : Configure as the IOMSTR2 I2C SDA or SPI WIR3 signal           */
22282   GPIO_PADREGG_PAD25FNCSEL_M2MISO      = 5,     /*!< M2MISO : Configure as the IOMSTR2 SPI MISO input signal                   */
22283 } GPIO_PADREGG_PAD25FNCSEL_Enum;
22284 
22285 /* ===========================================  GPIO PADREGG PAD25STRNG [10..10]  ============================================ */
22286 typedef enum {                                  /*!< GPIO_PADREGG_PAD25STRNG                                                   */
22287   GPIO_PADREGG_PAD25STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22288   GPIO_PADREGG_PAD25STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22289 } GPIO_PADREGG_PAD25STRNG_Enum;
22290 
22291 /* ============================================  GPIO PADREGG PAD25INPEN [9..9]  ============================================= */
22292 typedef enum {                                  /*!< GPIO_PADREGG_PAD25INPEN                                                   */
22293   GPIO_PADREGG_PAD25INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22294   GPIO_PADREGG_PAD25INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22295 } GPIO_PADREGG_PAD25INPEN_Enum;
22296 
22297 /* =============================================  GPIO PADREGG PAD25PULL [8..8]  ============================================= */
22298 typedef enum {                                  /*!< GPIO_PADREGG_PAD25PULL                                                    */
22299   GPIO_PADREGG_PAD25PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22300   GPIO_PADREGG_PAD25PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22301 } GPIO_PADREGG_PAD25PULL_Enum;
22302 
22303 /* ============================================  GPIO PADREGG PAD24FNCSEL [3..5]  ============================================ */
22304 typedef enum {                                  /*!< GPIO_PADREGG_PAD24FNCSEL                                                  */
22305   GPIO_PADREGG_PAD24FNCSEL_UART1TX     = 0,     /*!< UART1TX : Configure as UART1 TX output signal                             */
22306   GPIO_PADREGG_PAD24FNCSEL_NCE24       = 1,     /*!< NCE24 : IOM/MSPI nCE group 24                                             */
22307   GPIO_PADREGG_PAD24FNCSEL_MSPI8       = 2,     /*!< MSPI8 : MSPI data connection 8                                            */
22308   GPIO_PADREGG_PAD24FNCSEL_GPIO24      = 3,     /*!< GPIO24 : Configure as GPIO24                                              */
22309   GPIO_PADREGG_PAD24FNCSEL_UA0CTS      = 4,     /*!< UA0CTS : Configure as UART0 CTS input signal                              */
22310   GPIO_PADREGG_PAD24FNCSEL_CT21        = 5,     /*!< CT21 : CTIMER connection 21                                               */
22311   GPIO_PADREGG_PAD24FNCSEL_32kHzXT     = 6,     /*!< 32kHzXT : Configure as the 32kHz crystal output signal                    */
22312   GPIO_PADREGG_PAD24FNCSEL_SWO         = 7,     /*!< SWO : Configure as the serial trace data output signal                    */
22313 } GPIO_PADREGG_PAD24FNCSEL_Enum;
22314 
22315 /* ============================================  GPIO PADREGG PAD24STRNG [2..2]  ============================================= */
22316 typedef enum {                                  /*!< GPIO_PADREGG_PAD24STRNG                                                   */
22317   GPIO_PADREGG_PAD24STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22318   GPIO_PADREGG_PAD24STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22319 } GPIO_PADREGG_PAD24STRNG_Enum;
22320 
22321 /* ============================================  GPIO PADREGG PAD24INPEN [1..1]  ============================================= */
22322 typedef enum {                                  /*!< GPIO_PADREGG_PAD24INPEN                                                   */
22323   GPIO_PADREGG_PAD24INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22324   GPIO_PADREGG_PAD24INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22325 } GPIO_PADREGG_PAD24INPEN_Enum;
22326 
22327 /* =============================================  GPIO PADREGG PAD24PULL [0..0]  ============================================= */
22328 typedef enum {                                  /*!< GPIO_PADREGG_PAD24PULL                                                    */
22329   GPIO_PADREGG_PAD24PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22330   GPIO_PADREGG_PAD24PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22331 } GPIO_PADREGG_PAD24PULL_Enum;
22332 
22333 /* ========================================================  PADREGH  ======================================================== */
22334 /* ===========================================  GPIO PADREGH PAD31FNCSEL [27..29]  =========================================== */
22335 typedef enum {                                  /*!< GPIO_PADREGH_PAD31FNCSEL                                                  */
22336   GPIO_PADREGH_PAD31FNCSEL_ADCSE3      = 0,     /*!< ADCSE3 : Configure as the analog input for ADC single ended
22337                                                      input 3                                                                   */
22338   GPIO_PADREGH_PAD31FNCSEL_NCE31       = 1,     /*!< NCE31 : IOM/MSPI nCE group 31                                             */
22339   GPIO_PADREGH_PAD31FNCSEL_CT13        = 2,     /*!< CT13 : CTIMER connection 13                                               */
22340   GPIO_PADREGH_PAD31FNCSEL_GPIO31      = 3,     /*!< GPIO31 : Configure as GPIO31                                              */
22341   GPIO_PADREGH_PAD31FNCSEL_UART0RX     = 4,     /*!< UART0RX : Configure as the UART0 RX input signal                          */
22342   GPIO_PADREGH_PAD31FNCSEL_SCCCLK      = 5,     /*!< SCCCLK : SCARD serial clock output                                        */
22343   GPIO_PADREGH_PAD31FNCSEL_UA1RTS      = 7,     /*!< UA1RTS : Configure as UART1 RTS output signal                             */
22344 } GPIO_PADREGH_PAD31FNCSEL_Enum;
22345 
22346 /* ===========================================  GPIO PADREGH PAD31STRNG [26..26]  ============================================ */
22347 typedef enum {                                  /*!< GPIO_PADREGH_PAD31STRNG                                                   */
22348   GPIO_PADREGH_PAD31STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22349   GPIO_PADREGH_PAD31STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22350 } GPIO_PADREGH_PAD31STRNG_Enum;
22351 
22352 /* ===========================================  GPIO PADREGH PAD31INPEN [25..25]  ============================================ */
22353 typedef enum {                                  /*!< GPIO_PADREGH_PAD31INPEN                                                   */
22354   GPIO_PADREGH_PAD31INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22355   GPIO_PADREGH_PAD31INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22356 } GPIO_PADREGH_PAD31INPEN_Enum;
22357 
22358 /* ============================================  GPIO PADREGH PAD31PULL [24..24]  ============================================ */
22359 typedef enum {                                  /*!< GPIO_PADREGH_PAD31PULL                                                    */
22360   GPIO_PADREGH_PAD31PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22361   GPIO_PADREGH_PAD31PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22362 } GPIO_PADREGH_PAD31PULL_Enum;
22363 
22364 /* ===========================================  GPIO PADREGH PAD30FNCSEL [19..21]  =========================================== */
22365 typedef enum {                                  /*!< GPIO_PADREGH_PAD30FNCSEL                                                  */
22366   GPIO_PADREGH_PAD30FNCSEL_ANATEST1    = 0,     /*!< ANATEST1 : Configure as the ANATEST1 I/O signal                           */
22367   GPIO_PADREGH_PAD30FNCSEL_NCE30       = 1,     /*!< NCE30 : IOM/MSPI nCE group 30                                             */
22368   GPIO_PADREGH_PAD30FNCSEL_CT11        = 2,     /*!< CT11 : CTIMER connection 11                                               */
22369   GPIO_PADREGH_PAD30FNCSEL_GPIO30      = 3,     /*!< GPIO30 : Configure as GPIO30                                              */
22370   GPIO_PADREGH_PAD30FNCSEL_UART0TX     = 4,     /*!< UART0TX : Configure as UART0 TX output signal                             */
22371   GPIO_PADREGH_PAD30FNCSEL_UA1RTS      = 5,     /*!< UA1RTS : Configure as UART1 RTS output signal                             */
22372   GPIO_PADREGH_PAD30FNCSEL_I2S_DAT     = 7,     /*!< I2S_DAT : Configure as the PDM I2S Data output signal                     */
22373 } GPIO_PADREGH_PAD30FNCSEL_Enum;
22374 
22375 /* ===========================================  GPIO PADREGH PAD30STRNG [18..18]  ============================================ */
22376 typedef enum {                                  /*!< GPIO_PADREGH_PAD30STRNG                                                   */
22377   GPIO_PADREGH_PAD30STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22378   GPIO_PADREGH_PAD30STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22379 } GPIO_PADREGH_PAD30STRNG_Enum;
22380 
22381 /* ===========================================  GPIO PADREGH PAD30INPEN [17..17]  ============================================ */
22382 typedef enum {                                  /*!< GPIO_PADREGH_PAD30INPEN                                                   */
22383   GPIO_PADREGH_PAD30INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22384   GPIO_PADREGH_PAD30INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22385 } GPIO_PADREGH_PAD30INPEN_Enum;
22386 
22387 /* ============================================  GPIO PADREGH PAD30PULL [16..16]  ============================================ */
22388 typedef enum {                                  /*!< GPIO_PADREGH_PAD30PULL                                                    */
22389   GPIO_PADREGH_PAD30PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22390   GPIO_PADREGH_PAD30PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22391 } GPIO_PADREGH_PAD30PULL_Enum;
22392 
22393 /* ===========================================  GPIO PADREGH PAD29FNCSEL [11..13]  =========================================== */
22394 typedef enum {                                  /*!< GPIO_PADREGH_PAD29FNCSEL                                                  */
22395   GPIO_PADREGH_PAD29FNCSEL_ADCSE1      = 0,     /*!< ADCSE1 : Configure as the analog input for ADC single ended
22396                                                      input 1                                                                   */
22397   GPIO_PADREGH_PAD29FNCSEL_NCE29       = 1,     /*!< NCE29 : IOM/MSPI nCE group 29                                             */
22398   GPIO_PADREGH_PAD29FNCSEL_CT9         = 2,     /*!< CT9 : CTIMER connection 9                                                 */
22399   GPIO_PADREGH_PAD29FNCSEL_GPIO29      = 3,     /*!< GPIO29 : Configure as GPIO29                                              */
22400   GPIO_PADREGH_PAD29FNCSEL_UA0CTS      = 4,     /*!< UA0CTS : Configure as the UART0 CTS input signal                          */
22401   GPIO_PADREGH_PAD29FNCSEL_UA1CTS      = 5,     /*!< UA1CTS : Configure as the UART1 CTS input signal                          */
22402   GPIO_PADREGH_PAD29FNCSEL_UART0RX     = 6,     /*!< UART0RX : Configure as the UART0 RX input signal                          */
22403   GPIO_PADREGH_PAD29FNCSEL_PDM_DATA    = 7,     /*!< PDM_DATA : Configure as PDM DATA input                                    */
22404 } GPIO_PADREGH_PAD29FNCSEL_Enum;
22405 
22406 /* ===========================================  GPIO PADREGH PAD29STRNG [10..10]  ============================================ */
22407 typedef enum {                                  /*!< GPIO_PADREGH_PAD29STRNG                                                   */
22408   GPIO_PADREGH_PAD29STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22409   GPIO_PADREGH_PAD29STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22410 } GPIO_PADREGH_PAD29STRNG_Enum;
22411 
22412 /* ============================================  GPIO PADREGH PAD29INPEN [9..9]  ============================================= */
22413 typedef enum {                                  /*!< GPIO_PADREGH_PAD29INPEN                                                   */
22414   GPIO_PADREGH_PAD29INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22415   GPIO_PADREGH_PAD29INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22416 } GPIO_PADREGH_PAD29INPEN_Enum;
22417 
22418 /* =============================================  GPIO PADREGH PAD29PULL [8..8]  ============================================= */
22419 typedef enum {                                  /*!< GPIO_PADREGH_PAD29PULL                                                    */
22420   GPIO_PADREGH_PAD29PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22421   GPIO_PADREGH_PAD29PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22422 } GPIO_PADREGH_PAD29PULL_Enum;
22423 
22424 /* ============================================  GPIO PADREGH PAD28FNCSEL [3..5]  ============================================ */
22425 typedef enum {                                  /*!< GPIO_PADREGH_PAD28FNCSEL                                                  */
22426   GPIO_PADREGH_PAD28FNCSEL_I2S_WCLK    = 0,     /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input                      */
22427   GPIO_PADREGH_PAD28FNCSEL_NCE28       = 1,     /*!< NCE28 : IOM/MSPI nCE group 28                                             */
22428   GPIO_PADREGH_PAD28FNCSEL_CT7         = 2,     /*!< CT7 : CTIMER connection 7                                                 */
22429   GPIO_PADREGH_PAD28FNCSEL_GPIO28      = 3,     /*!< GPIO28 : Configure as GPIO28                                              */
22430   GPIO_PADREGH_PAD28FNCSEL_M2MOSI      = 5,     /*!< M2MOSI : Configure as the IOMSTR2 SPI MOSI output signal                  */
22431   GPIO_PADREGH_PAD28FNCSEL_UART0TX     = 6,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
22432 } GPIO_PADREGH_PAD28FNCSEL_Enum;
22433 
22434 /* ============================================  GPIO PADREGH PAD28STRNG [2..2]  ============================================= */
22435 typedef enum {                                  /*!< GPIO_PADREGH_PAD28STRNG                                                   */
22436   GPIO_PADREGH_PAD28STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22437   GPIO_PADREGH_PAD28STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22438 } GPIO_PADREGH_PAD28STRNG_Enum;
22439 
22440 /* ============================================  GPIO PADREGH PAD28INPEN [1..1]  ============================================= */
22441 typedef enum {                                  /*!< GPIO_PADREGH_PAD28INPEN                                                   */
22442   GPIO_PADREGH_PAD28INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22443   GPIO_PADREGH_PAD28INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22444 } GPIO_PADREGH_PAD28INPEN_Enum;
22445 
22446 /* =============================================  GPIO PADREGH PAD28PULL [0..0]  ============================================= */
22447 typedef enum {                                  /*!< GPIO_PADREGH_PAD28PULL                                                    */
22448   GPIO_PADREGH_PAD28PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22449   GPIO_PADREGH_PAD28PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22450 } GPIO_PADREGH_PAD28PULL_Enum;
22451 
22452 /* ========================================================  PADREGI  ======================================================== */
22453 /* ===========================================  GPIO PADREGI PAD35FNCSEL [27..29]  =========================================== */
22454 typedef enum {                                  /*!< GPIO_PADREGI_PAD35FNCSEL                                                  */
22455   GPIO_PADREGI_PAD35FNCSEL_ADCSE7      = 0,     /*!< ADCSE7 : Configure as the analog input for ADC single ended
22456                                                      input 7                                                                   */
22457   GPIO_PADREGI_PAD35FNCSEL_NCE35       = 1,     /*!< NCE35 : IOM/MSPI nCE group 35                                             */
22458   GPIO_PADREGI_PAD35FNCSEL_UART1TX     = 2,     /*!< UART1TX : Configure as the UART1 TX signal                                */
22459   GPIO_PADREGI_PAD35FNCSEL_GPIO35      = 3,     /*!< GPIO35 : Configure as GPIO35                                              */
22460   GPIO_PADREGI_PAD35FNCSEL_I2SDAT      = 4,     /*!< I2SDAT : I2S serial data output                                           */
22461   GPIO_PADREGI_PAD35FNCSEL_CT27        = 5,     /*!< CT27 : CTIMER connection 27                                               */
22462   GPIO_PADREGI_PAD35FNCSEL_UA0RTS      = 6,     /*!< UA0RTS : Configure as the UART0 RTS output                                */
22463 } GPIO_PADREGI_PAD35FNCSEL_Enum;
22464 
22465 /* ===========================================  GPIO PADREGI PAD35STRNG [26..26]  ============================================ */
22466 typedef enum {                                  /*!< GPIO_PADREGI_PAD35STRNG                                                   */
22467   GPIO_PADREGI_PAD35STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22468   GPIO_PADREGI_PAD35STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22469 } GPIO_PADREGI_PAD35STRNG_Enum;
22470 
22471 /* ===========================================  GPIO PADREGI PAD35INPEN [25..25]  ============================================ */
22472 typedef enum {                                  /*!< GPIO_PADREGI_PAD35INPEN                                                   */
22473   GPIO_PADREGI_PAD35INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22474   GPIO_PADREGI_PAD35INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22475 } GPIO_PADREGI_PAD35INPEN_Enum;
22476 
22477 /* ============================================  GPIO PADREGI PAD35PULL [24..24]  ============================================ */
22478 typedef enum {                                  /*!< GPIO_PADREGI_PAD35PULL                                                    */
22479   GPIO_PADREGI_PAD35PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22480   GPIO_PADREGI_PAD35PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22481 } GPIO_PADREGI_PAD35PULL_Enum;
22482 
22483 /* ===========================================  GPIO PADREGI PAD34FNCSEL [19..21]  =========================================== */
22484 typedef enum {                                  /*!< GPIO_PADREGI_PAD34FNCSEL                                                  */
22485   GPIO_PADREGI_PAD34FNCSEL_ADCSE6      = 0,     /*!< ADCSE6 : Configure as the analog input for ADC single ended
22486                                                      input 6                                                                   */
22487   GPIO_PADREGI_PAD34FNCSEL_NCE34       = 1,     /*!< NCE34 : IOM/MSPI nCE group 34                                             */
22488   GPIO_PADREGI_PAD34FNCSEL_UA1RTS      = 2,     /*!< UA1RTS : Configure as the UART1 RTS output                                */
22489   GPIO_PADREGI_PAD34FNCSEL_GPIO34      = 3,     /*!< GPIO34 : Configure as GPIO34                                              */
22490   GPIO_PADREGI_PAD34FNCSEL_CMPRF2      = 4,     /*!< CMPRF2 : Configure as the analog comparator reference 2 signal            */
22491   GPIO_PADREGI_PAD34FNCSEL_UA0RTS      = 5,     /*!< UA0RTS : Configure as the UART0 RTS output                                */
22492   GPIO_PADREGI_PAD34FNCSEL_UART0RX     = 6,     /*!< UART0RX : Configure as the UART0 RX input                                 */
22493   GPIO_PADREGI_PAD34FNCSEL_PDMDATA     = 7,     /*!< PDMDATA : PDM serial data input                                           */
22494 } GPIO_PADREGI_PAD34FNCSEL_Enum;
22495 
22496 /* ===========================================  GPIO PADREGI PAD34STRNG [18..18]  ============================================ */
22497 typedef enum {                                  /*!< GPIO_PADREGI_PAD34STRNG                                                   */
22498   GPIO_PADREGI_PAD34STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22499   GPIO_PADREGI_PAD34STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22500 } GPIO_PADREGI_PAD34STRNG_Enum;
22501 
22502 /* ===========================================  GPIO PADREGI PAD34INPEN [17..17]  ============================================ */
22503 typedef enum {                                  /*!< GPIO_PADREGI_PAD34INPEN                                                   */
22504   GPIO_PADREGI_PAD34INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22505   GPIO_PADREGI_PAD34INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22506 } GPIO_PADREGI_PAD34INPEN_Enum;
22507 
22508 /* ============================================  GPIO PADREGI PAD34PULL [16..16]  ============================================ */
22509 typedef enum {                                  /*!< GPIO_PADREGI_PAD34PULL                                                    */
22510   GPIO_PADREGI_PAD34PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22511   GPIO_PADREGI_PAD34PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22512 } GPIO_PADREGI_PAD34PULL_Enum;
22513 
22514 /* ===========================================  GPIO PADREGI PAD33FNCSEL [11..13]  =========================================== */
22515 typedef enum {                                  /*!< GPIO_PADREGI_PAD33FNCSEL                                                  */
22516   GPIO_PADREGI_PAD33FNCSEL_ADCSE5      = 0,     /*!< ADCSE5 : Configure as the analog ADC single ended port 5 input
22517                                                      signal                                                                    */
22518   GPIO_PADREGI_PAD33FNCSEL_NCE33       = 1,     /*!< NCE33 : IOM/MSPI nCE group 33                                             */
22519   GPIO_PADREGI_PAD33FNCSEL_32kHzXT     = 2,     /*!< 32kHzXT : Configure as the 32kHz crystal output signal                    */
22520   GPIO_PADREGI_PAD33FNCSEL_GPIO33      = 3,     /*!< GPIO33 : Configure as GPIO33                                              */
22521   GPIO_PADREGI_PAD33FNCSEL_UA0CTS      = 5,     /*!< UA0CTS : Configure as the UART0 CTS input                                 */
22522   GPIO_PADREGI_PAD33FNCSEL_CT23        = 6,     /*!< CT23 : CTIMER connection 23                                               */
22523   GPIO_PADREGI_PAD33FNCSEL_SWO         = 7,     /*!< SWO : Configure as the serial trace data output signal                    */
22524 } GPIO_PADREGI_PAD33FNCSEL_Enum;
22525 
22526 /* ===========================================  GPIO PADREGI PAD33STRNG [10..10]  ============================================ */
22527 typedef enum {                                  /*!< GPIO_PADREGI_PAD33STRNG                                                   */
22528   GPIO_PADREGI_PAD33STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22529   GPIO_PADREGI_PAD33STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22530 } GPIO_PADREGI_PAD33STRNG_Enum;
22531 
22532 /* ============================================  GPIO PADREGI PAD33INPEN [9..9]  ============================================= */
22533 typedef enum {                                  /*!< GPIO_PADREGI_PAD33INPEN                                                   */
22534   GPIO_PADREGI_PAD33INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22535   GPIO_PADREGI_PAD33INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22536 } GPIO_PADREGI_PAD33INPEN_Enum;
22537 
22538 /* =============================================  GPIO PADREGI PAD33PULL [8..8]  ============================================= */
22539 typedef enum {                                  /*!< GPIO_PADREGI_PAD33PULL                                                    */
22540   GPIO_PADREGI_PAD33PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22541   GPIO_PADREGI_PAD33PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22542 } GPIO_PADREGI_PAD33PULL_Enum;
22543 
22544 /* ============================================  GPIO PADREGI PAD32FNCSEL [3..5]  ============================================ */
22545 typedef enum {                                  /*!< GPIO_PADREGI_PAD32FNCSEL                                                  */
22546   GPIO_PADREGI_PAD32FNCSEL_ADCSE4      = 0,     /*!< ADCSE4 : Configure as the analog input for ADC single ended
22547                                                      input 4                                                                   */
22548   GPIO_PADREGI_PAD32FNCSEL_NCE32       = 1,     /*!< NCE32 : IOM/MSPI nCE group 32                                             */
22549   GPIO_PADREGI_PAD32FNCSEL_CT15        = 2,     /*!< CT15 : CTIMER connection 15                                               */
22550   GPIO_PADREGI_PAD32FNCSEL_GPIO32      = 3,     /*!< GPIO32 : Configure as GPIO32                                              */
22551   GPIO_PADREGI_PAD32FNCSEL_SCCIO       = 4,     /*!< SCCIO : SCARD serial data input/output                                    */
22552   GPIO_PADREGI_PAD32FNCSEL_EXTLF       = 5,     /*!< EXTLF : External input to the LFRC oscillator                             */
22553   GPIO_PADREGI_PAD32FNCSEL_UA1CTS      = 7,     /*!< UA1CTS : Configure as the UART1 CTS input                                 */
22554 } GPIO_PADREGI_PAD32FNCSEL_Enum;
22555 
22556 /* ============================================  GPIO PADREGI PAD32STRNG [2..2]  ============================================= */
22557 typedef enum {                                  /*!< GPIO_PADREGI_PAD32STRNG                                                   */
22558   GPIO_PADREGI_PAD32STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22559   GPIO_PADREGI_PAD32STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22560 } GPIO_PADREGI_PAD32STRNG_Enum;
22561 
22562 /* ============================================  GPIO PADREGI PAD32INPEN [1..1]  ============================================= */
22563 typedef enum {                                  /*!< GPIO_PADREGI_PAD32INPEN                                                   */
22564   GPIO_PADREGI_PAD32INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22565   GPIO_PADREGI_PAD32INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22566 } GPIO_PADREGI_PAD32INPEN_Enum;
22567 
22568 /* =============================================  GPIO PADREGI PAD32PULL [0..0]  ============================================= */
22569 typedef enum {                                  /*!< GPIO_PADREGI_PAD32PULL                                                    */
22570   GPIO_PADREGI_PAD32PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22571   GPIO_PADREGI_PAD32PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22572 } GPIO_PADREGI_PAD32PULL_Enum;
22573 
22574 /* ========================================================  PADREGJ  ======================================================== */
22575 /* ============================================  GPIO PADREGJ PAD39RSEL [30..31]  ============================================ */
22576 typedef enum {                                  /*!< GPIO_PADREGJ_PAD39RSEL                                                    */
22577   GPIO_PADREGJ_PAD39RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
22578   GPIO_PADREGJ_PAD39RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
22579   GPIO_PADREGJ_PAD39RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
22580   GPIO_PADREGJ_PAD39RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
22581 } GPIO_PADREGJ_PAD39RSEL_Enum;
22582 
22583 /* ===========================================  GPIO PADREGJ PAD39FNCSEL [27..29]  =========================================== */
22584 typedef enum {                                  /*!< GPIO_PADREGJ_PAD39FNCSEL                                                  */
22585   GPIO_PADREGJ_PAD39FNCSEL_UART0TX     = 0,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
22586   GPIO_PADREGJ_PAD39FNCSEL_UART1TX     = 1,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
22587   GPIO_PADREGJ_PAD39FNCSEL_CT25        = 2,     /*!< CT25 : CTIMER connection 25                                               */
22588   GPIO_PADREGJ_PAD39FNCSEL_GPIO39      = 3,     /*!< GPIO39 : Configure as GPIO39                                              */
22589   GPIO_PADREGJ_PAD39FNCSEL_M4SCL       = 4,     /*!< M4SCL : Configure as the IOMSTR4 I2C SCL signal                           */
22590   GPIO_PADREGJ_PAD39FNCSEL_M4SCK       = 5,     /*!< M4SCK : Configure as the IOMSTR4 SPI SCK signal                           */
22591 } GPIO_PADREGJ_PAD39FNCSEL_Enum;
22592 
22593 /* ===========================================  GPIO PADREGJ PAD39STRNG [26..26]  ============================================ */
22594 typedef enum {                                  /*!< GPIO_PADREGJ_PAD39STRNG                                                   */
22595   GPIO_PADREGJ_PAD39STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22596   GPIO_PADREGJ_PAD39STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22597 } GPIO_PADREGJ_PAD39STRNG_Enum;
22598 
22599 /* ===========================================  GPIO PADREGJ PAD39INPEN [25..25]  ============================================ */
22600 typedef enum {                                  /*!< GPIO_PADREGJ_PAD39INPEN                                                   */
22601   GPIO_PADREGJ_PAD39INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22602   GPIO_PADREGJ_PAD39INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22603 } GPIO_PADREGJ_PAD39INPEN_Enum;
22604 
22605 /* ============================================  GPIO PADREGJ PAD39PULL [24..24]  ============================================ */
22606 typedef enum {                                  /*!< GPIO_PADREGJ_PAD39PULL                                                    */
22607   GPIO_PADREGJ_PAD39PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22608   GPIO_PADREGJ_PAD39PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22609 } GPIO_PADREGJ_PAD39PULL_Enum;
22610 
22611 /* ===========================================  GPIO PADREGJ PAD38FNCSEL [19..21]  =========================================== */
22612 typedef enum {                                  /*!< GPIO_PADREGJ_PAD38FNCSEL                                                  */
22613   GPIO_PADREGJ_PAD38FNCSEL_TRIG3       = 0,     /*!< TRIG3 : Configure as the ADC Trigger 3 signal                             */
22614   GPIO_PADREGJ_PAD38FNCSEL_NCE38       = 1,     /*!< NCE38 : IOM/MSPI nCE group 38                                             */
22615   GPIO_PADREGJ_PAD38FNCSEL_UA0CTS      = 2,     /*!< UA0CTS : Configure as the UART0 CTS signal                                */
22616   GPIO_PADREGJ_PAD38FNCSEL_GPIO38      = 3,     /*!< GPIO38 : Configure as GPIO38                                              */
22617   GPIO_PADREGJ_PAD38FNCSEL_M3MOSI      = 5,     /*!< M3MOSI : Configure as the IOMSTR3 SPI MOSI output signal                  */
22618   GPIO_PADREGJ_PAD38FNCSEL_UART1RX     = 6,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
22619 } GPIO_PADREGJ_PAD38FNCSEL_Enum;
22620 
22621 /* ===========================================  GPIO PADREGJ PAD38STRNG [18..18]  ============================================ */
22622 typedef enum {                                  /*!< GPIO_PADREGJ_PAD38STRNG                                                   */
22623   GPIO_PADREGJ_PAD38STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22624   GPIO_PADREGJ_PAD38STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22625 } GPIO_PADREGJ_PAD38STRNG_Enum;
22626 
22627 /* ===========================================  GPIO PADREGJ PAD38INPEN [17..17]  ============================================ */
22628 typedef enum {                                  /*!< GPIO_PADREGJ_PAD38INPEN                                                   */
22629   GPIO_PADREGJ_PAD38INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22630   GPIO_PADREGJ_PAD38INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22631 } GPIO_PADREGJ_PAD38INPEN_Enum;
22632 
22633 /* ============================================  GPIO PADREGJ PAD38PULL [16..16]  ============================================ */
22634 typedef enum {                                  /*!< GPIO_PADREGJ_PAD38PULL                                                    */
22635   GPIO_PADREGJ_PAD38PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22636   GPIO_PADREGJ_PAD38PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22637 } GPIO_PADREGJ_PAD38PULL_Enum;
22638 
22639 /* ===========================================  GPIO PADREGJ PAD37PWRDN [15..15]  ============================================ */
22640 typedef enum {                                  /*!< GPIO_PADREGJ_PAD37PWRDN                                                   */
22641   GPIO_PADREGJ_PAD37PWRDN_DIS          = 0,     /*!< DIS : Power switch disabled                                               */
22642   GPIO_PADREGJ_PAD37PWRDN_EN           = 1,     /*!< EN : Power switch enabled (switch to GND)                                 */
22643 } GPIO_PADREGJ_PAD37PWRDN_Enum;
22644 
22645 /* ===========================================  GPIO PADREGJ PAD37FNCSEL [11..13]  =========================================== */
22646 typedef enum {                                  /*!< GPIO_PADREGJ_PAD37FNCSEL                                                  */
22647   GPIO_PADREGJ_PAD37FNCSEL_TRIG2       = 0,     /*!< TRIG2 : Configure as the ADC Trigger 2 signal                             */
22648   GPIO_PADREGJ_PAD37FNCSEL_NCE37       = 1,     /*!< NCE37 : IOM/MSPI nCE group 37                                             */
22649   GPIO_PADREGJ_PAD37FNCSEL_UA0RTS      = 2,     /*!< UA0RTS : Configure as the UART0 RTS output signal                         */
22650   GPIO_PADREGJ_PAD37FNCSEL_GPIO37      = 3,     /*!< GPIO37 : Configure as GPIO37                                              */
22651   GPIO_PADREGJ_PAD37FNCSEL_SCCIO       = 4,     /*!< SCCIO : SCARD serial data input/output                                    */
22652   GPIO_PADREGJ_PAD37FNCSEL_UART1TX     = 5,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
22653   GPIO_PADREGJ_PAD37FNCSEL_PDMCLK      = 6,     /*!< PDMCLK : Configure as the PDM CLK output signal                           */
22654   GPIO_PADREGJ_PAD37FNCSEL_CT29        = 7,     /*!< CT29 : CTIMER connection 29                                               */
22655 } GPIO_PADREGJ_PAD37FNCSEL_Enum;
22656 
22657 /* ===========================================  GPIO PADREGJ PAD37STRNG [10..10]  ============================================ */
22658 typedef enum {                                  /*!< GPIO_PADREGJ_PAD37STRNG                                                   */
22659   GPIO_PADREGJ_PAD37STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22660   GPIO_PADREGJ_PAD37STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22661 } GPIO_PADREGJ_PAD37STRNG_Enum;
22662 
22663 /* ============================================  GPIO PADREGJ PAD37INPEN [9..9]  ============================================= */
22664 typedef enum {                                  /*!< GPIO_PADREGJ_PAD37INPEN                                                   */
22665   GPIO_PADREGJ_PAD37INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22666   GPIO_PADREGJ_PAD37INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22667 } GPIO_PADREGJ_PAD37INPEN_Enum;
22668 
22669 /* =============================================  GPIO PADREGJ PAD37PULL [8..8]  ============================================= */
22670 typedef enum {                                  /*!< GPIO_PADREGJ_PAD37PULL                                                    */
22671   GPIO_PADREGJ_PAD37PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22672   GPIO_PADREGJ_PAD37PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22673 } GPIO_PADREGJ_PAD37PULL_Enum;
22674 
22675 /* ============================================  GPIO PADREGJ PAD36FNCSEL [3..5]  ============================================ */
22676 typedef enum {                                  /*!< GPIO_PADREGJ_PAD36FNCSEL                                                  */
22677   GPIO_PADREGJ_PAD36FNCSEL_TRIG1       = 0,     /*!< TRIG1 : Configure as the ADC Trigger 1 signal                             */
22678   GPIO_PADREGJ_PAD36FNCSEL_NCE36       = 1,     /*!< NCE36 : IOM/MSPI nCE group 36                                             */
22679   GPIO_PADREGJ_PAD36FNCSEL_UART1RX     = 2,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
22680   GPIO_PADREGJ_PAD36FNCSEL_GPIO36      = 3,     /*!< GPIO36 : Configure as GPIO36                                              */
22681   GPIO_PADREGJ_PAD36FNCSEL_32kHzXT     = 4,     /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal            */
22682   GPIO_PADREGJ_PAD36FNCSEL_UA1CTS      = 5,     /*!< UA1CTS : Configure as the UART1 CTS input signal                          */
22683   GPIO_PADREGJ_PAD36FNCSEL_UA0CTS      = 6,     /*!< UA0CTS : Configure as the UART0 CTS input signal                          */
22684   GPIO_PADREGJ_PAD36FNCSEL_PDMDATA     = 7,     /*!< PDMDATA : PDM serial data input                                           */
22685 } GPIO_PADREGJ_PAD36FNCSEL_Enum;
22686 
22687 /* ============================================  GPIO PADREGJ PAD36STRNG [2..2]  ============================================= */
22688 typedef enum {                                  /*!< GPIO_PADREGJ_PAD36STRNG                                                   */
22689   GPIO_PADREGJ_PAD36STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22690   GPIO_PADREGJ_PAD36STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22691 } GPIO_PADREGJ_PAD36STRNG_Enum;
22692 
22693 /* ============================================  GPIO PADREGJ PAD36INPEN [1..1]  ============================================= */
22694 typedef enum {                                  /*!< GPIO_PADREGJ_PAD36INPEN                                                   */
22695   GPIO_PADREGJ_PAD36INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22696   GPIO_PADREGJ_PAD36INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22697 } GPIO_PADREGJ_PAD36INPEN_Enum;
22698 
22699 /* =============================================  GPIO PADREGJ PAD36PULL [0..0]  ============================================= */
22700 typedef enum {                                  /*!< GPIO_PADREGJ_PAD36PULL                                                    */
22701   GPIO_PADREGJ_PAD36PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22702   GPIO_PADREGJ_PAD36PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22703 } GPIO_PADREGJ_PAD36PULL_Enum;
22704 
22705 /* ========================================================  PADREGK  ======================================================== */
22706 /* ============================================  GPIO PADREGK PAD43RSEL [30..31]  ============================================ */
22707 typedef enum {                                  /*!< GPIO_PADREGK_PAD43RSEL                                                    */
22708   GPIO_PADREGK_PAD43RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
22709   GPIO_PADREGK_PAD43RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
22710   GPIO_PADREGK_PAD43RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
22711   GPIO_PADREGK_PAD43RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
22712 } GPIO_PADREGK_PAD43RSEL_Enum;
22713 
22714 /* ===========================================  GPIO PADREGK PAD43FNCSEL [27..29]  =========================================== */
22715 typedef enum {                                  /*!< GPIO_PADREGK_PAD43FNCSEL                                                  */
22716   GPIO_PADREGK_PAD43FNCSEL_UART1RX     = 0,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
22717   GPIO_PADREGK_PAD43FNCSEL_NCE43       = 1,     /*!< NCE43 : IOM/MSPI nCE group 43                                             */
22718   GPIO_PADREGK_PAD43FNCSEL_CT18        = 2,     /*!< CT18 : CTIMER connection 18                                               */
22719   GPIO_PADREGK_PAD43FNCSEL_GPIO43      = 3,     /*!< GPIO43 : Configure as GPIO43                                              */
22720   GPIO_PADREGK_PAD43FNCSEL_M3SDAWIR3   = 4,     /*!< M3SDAWIR3 : Configure as the IOMSTR3 I2C SDA or SPI WIR3 signal           */
22721   GPIO_PADREGK_PAD43FNCSEL_M3MISO      = 5,     /*!< M3MISO : Configure as the IOMSTR3 SPI MISO signal                         */
22722 } GPIO_PADREGK_PAD43FNCSEL_Enum;
22723 
22724 /* ===========================================  GPIO PADREGK PAD43STRNG [26..26]  ============================================ */
22725 typedef enum {                                  /*!< GPIO_PADREGK_PAD43STRNG                                                   */
22726   GPIO_PADREGK_PAD43STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22727   GPIO_PADREGK_PAD43STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22728 } GPIO_PADREGK_PAD43STRNG_Enum;
22729 
22730 /* ===========================================  GPIO PADREGK PAD43INPEN [25..25]  ============================================ */
22731 typedef enum {                                  /*!< GPIO_PADREGK_PAD43INPEN                                                   */
22732   GPIO_PADREGK_PAD43INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22733   GPIO_PADREGK_PAD43INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22734 } GPIO_PADREGK_PAD43INPEN_Enum;
22735 
22736 /* ============================================  GPIO PADREGK PAD43PULL [24..24]  ============================================ */
22737 typedef enum {                                  /*!< GPIO_PADREGK_PAD43PULL                                                    */
22738   GPIO_PADREGK_PAD43PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22739   GPIO_PADREGK_PAD43PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22740 } GPIO_PADREGK_PAD43PULL_Enum;
22741 
22742 /* ============================================  GPIO PADREGK PAD42RSEL [22..23]  ============================================ */
22743 typedef enum {                                  /*!< GPIO_PADREGK_PAD42RSEL                                                    */
22744   GPIO_PADREGK_PAD42RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
22745   GPIO_PADREGK_PAD42RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
22746   GPIO_PADREGK_PAD42RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
22747   GPIO_PADREGK_PAD42RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
22748 } GPIO_PADREGK_PAD42RSEL_Enum;
22749 
22750 /* ===========================================  GPIO PADREGK PAD42FNCSEL [19..21]  =========================================== */
22751 typedef enum {                                  /*!< GPIO_PADREGK_PAD42FNCSEL                                                  */
22752   GPIO_PADREGK_PAD42FNCSEL_UART1TX     = 0,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
22753   GPIO_PADREGK_PAD42FNCSEL_NCE42       = 1,     /*!< NCE42 : IOM/MSPI nCE group 42                                             */
22754   GPIO_PADREGK_PAD42FNCSEL_CT16        = 2,     /*!< CT16 : CTIMER connection 16                                               */
22755   GPIO_PADREGK_PAD42FNCSEL_GPIO42      = 3,     /*!< GPIO42 : Configure as GPIO42                                              */
22756   GPIO_PADREGK_PAD42FNCSEL_M3SCL       = 4,     /*!< M3SCL : Configure as the IOMSTR3 I2C SCL clock I/O signal                 */
22757   GPIO_PADREGK_PAD42FNCSEL_M3SCK       = 5,     /*!< M3SCK : Configure as the IOMSTR3 SPI SCK output                           */
22758 } GPIO_PADREGK_PAD42FNCSEL_Enum;
22759 
22760 /* ===========================================  GPIO PADREGK PAD42STRNG [18..18]  ============================================ */
22761 typedef enum {                                  /*!< GPIO_PADREGK_PAD42STRNG                                                   */
22762   GPIO_PADREGK_PAD42STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22763   GPIO_PADREGK_PAD42STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22764 } GPIO_PADREGK_PAD42STRNG_Enum;
22765 
22766 /* ===========================================  GPIO PADREGK PAD42INPEN [17..17]  ============================================ */
22767 typedef enum {                                  /*!< GPIO_PADREGK_PAD42INPEN                                                   */
22768   GPIO_PADREGK_PAD42INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22769   GPIO_PADREGK_PAD42INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22770 } GPIO_PADREGK_PAD42INPEN_Enum;
22771 
22772 /* ============================================  GPIO PADREGK PAD42PULL [16..16]  ============================================ */
22773 typedef enum {                                  /*!< GPIO_PADREGK_PAD42PULL                                                    */
22774   GPIO_PADREGK_PAD42PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22775   GPIO_PADREGK_PAD42PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22776 } GPIO_PADREGK_PAD42PULL_Enum;
22777 
22778 /* ===========================================  GPIO PADREGK PAD41PWRDN [15..15]  ============================================ */
22779 typedef enum {                                  /*!< GPIO_PADREGK_PAD41PWRDN                                                   */
22780   GPIO_PADREGK_PAD41PWRDN_DIS          = 0,     /*!< DIS : Power switch disabled                                               */
22781   GPIO_PADREGK_PAD41PWRDN_EN           = 1,     /*!< EN : Power switch enabled (Switch pad to VSS)                             */
22782 } GPIO_PADREGK_PAD41PWRDN_Enum;
22783 
22784 /* ===========================================  GPIO PADREGK PAD41FNCSEL [11..13]  =========================================== */
22785 typedef enum {                                  /*!< GPIO_PADREGK_PAD41FNCSEL                                                  */
22786   GPIO_PADREGK_PAD41FNCSEL_NCE41       = 0,     /*!< NCE41 : IOM/MSPI nCE group 41                                             */
22787   GPIO_PADREGK_PAD41FNCSEL_SWO         = 2,     /*!< SWO : Configure as the serial wire debug SWO signal                       */
22788   GPIO_PADREGK_PAD41FNCSEL_GPIO41      = 3,     /*!< GPIO41 : Configure as GPIO41                                              */
22789   GPIO_PADREGK_PAD41FNCSEL_I2SWCLK     = 4,     /*!< I2SWCLK : I2S word clock input                                            */
22790   GPIO_PADREGK_PAD41FNCSEL_UA1RTS      = 5,     /*!< UA1RTS : Configure as the UART1 RTS output signal                         */
22791   GPIO_PADREGK_PAD41FNCSEL_UART0TX     = 6,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
22792   GPIO_PADREGK_PAD41FNCSEL_UA0RTS      = 7,     /*!< UA0RTS : Configure as the UART0 RTS output signal                         */
22793 } GPIO_PADREGK_PAD41FNCSEL_Enum;
22794 
22795 /* ===========================================  GPIO PADREGK PAD41STRNG [10..10]  ============================================ */
22796 typedef enum {                                  /*!< GPIO_PADREGK_PAD41STRNG                                                   */
22797   GPIO_PADREGK_PAD41STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22798   GPIO_PADREGK_PAD41STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22799 } GPIO_PADREGK_PAD41STRNG_Enum;
22800 
22801 /* ============================================  GPIO PADREGK PAD41INPEN [9..9]  ============================================= */
22802 typedef enum {                                  /*!< GPIO_PADREGK_PAD41INPEN                                                   */
22803   GPIO_PADREGK_PAD41INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22804   GPIO_PADREGK_PAD41INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22805 } GPIO_PADREGK_PAD41INPEN_Enum;
22806 
22807 /* =============================================  GPIO PADREGK PAD41PULL [8..8]  ============================================= */
22808 typedef enum {                                  /*!< GPIO_PADREGK_PAD41PULL                                                    */
22809   GPIO_PADREGK_PAD41PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22810   GPIO_PADREGK_PAD41PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22811 } GPIO_PADREGK_PAD41PULL_Enum;
22812 
22813 /* =============================================  GPIO PADREGK PAD40RSEL [6..7]  ============================================= */
22814 typedef enum {                                  /*!< GPIO_PADREGK_PAD40RSEL                                                    */
22815   GPIO_PADREGK_PAD40RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
22816   GPIO_PADREGK_PAD40RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
22817   GPIO_PADREGK_PAD40RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
22818   GPIO_PADREGK_PAD40RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
22819 } GPIO_PADREGK_PAD40RSEL_Enum;
22820 
22821 /* ============================================  GPIO PADREGK PAD40FNCSEL [3..5]  ============================================ */
22822 typedef enum {                                  /*!< GPIO_PADREGK_PAD40FNCSEL                                                  */
22823   GPIO_PADREGK_PAD40FNCSEL_UART0RX     = 0,     /*!< UART0RX : Configure as the UART0 RX input signal                          */
22824   GPIO_PADREGK_PAD40FNCSEL_UART1RX     = 1,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
22825   GPIO_PADREGK_PAD40FNCSEL_TRIG0       = 2,     /*!< TRIG0 : Configure as the ADC Trigger 0 signal                             */
22826   GPIO_PADREGK_PAD40FNCSEL_GPIO40      = 3,     /*!< GPIO40 : Configure as GPIO40                                              */
22827   GPIO_PADREGK_PAD40FNCSEL_M4SDAWIR3   = 4,     /*!< M4SDAWIR3 : Configure as the IOMSTR4 I2C SDA or SPI WIR3 signal           */
22828   GPIO_PADREGK_PAD40FNCSEL_M4MISO      = 5,     /*!< M4MISO : Configure as the IOMSTR4 SPI MISO input signal                   */
22829 } GPIO_PADREGK_PAD40FNCSEL_Enum;
22830 
22831 /* ============================================  GPIO PADREGK PAD40STRNG [2..2]  ============================================= */
22832 typedef enum {                                  /*!< GPIO_PADREGK_PAD40STRNG                                                   */
22833   GPIO_PADREGK_PAD40STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22834   GPIO_PADREGK_PAD40STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22835 } GPIO_PADREGK_PAD40STRNG_Enum;
22836 
22837 /* ============================================  GPIO PADREGK PAD40INPEN [1..1]  ============================================= */
22838 typedef enum {                                  /*!< GPIO_PADREGK_PAD40INPEN                                                   */
22839   GPIO_PADREGK_PAD40INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22840   GPIO_PADREGK_PAD40INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22841 } GPIO_PADREGK_PAD40INPEN_Enum;
22842 
22843 /* =============================================  GPIO PADREGK PAD40PULL [0..0]  ============================================= */
22844 typedef enum {                                  /*!< GPIO_PADREGK_PAD40PULL                                                    */
22845   GPIO_PADREGK_PAD40PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22846   GPIO_PADREGK_PAD40PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22847 } GPIO_PADREGK_PAD40PULL_Enum;
22848 
22849 /* ========================================================  PADREGL  ======================================================== */
22850 /* ===========================================  GPIO PADREGL PAD47FNCSEL [27..29]  =========================================== */
22851 typedef enum {                                  /*!< GPIO_PADREGL_PAD47FNCSEL                                                  */
22852   GPIO_PADREGL_PAD47FNCSEL_32kHzXT     = 0,     /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal            */
22853   GPIO_PADREGL_PAD47FNCSEL_NCE47       = 1,     /*!< NCE47 : IOM/MSPI nCE group 47                                             */
22854   GPIO_PADREGL_PAD47FNCSEL_CT26        = 2,     /*!< CT26 : CTIMER connection 26                                               */
22855   GPIO_PADREGL_PAD47FNCSEL_GPIO47      = 3,     /*!< GPIO47 : Configure as GPIO47                                              */
22856   GPIO_PADREGL_PAD47FNCSEL_M5MOSI      = 5,     /*!< M5MOSI : Configure as the IOMSTR5 SPI MOSI output signal                  */
22857   GPIO_PADREGL_PAD47FNCSEL_UART1RX     = 6,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
22858 } GPIO_PADREGL_PAD47FNCSEL_Enum;
22859 
22860 /* ===========================================  GPIO PADREGL PAD47STRNG [26..26]  ============================================ */
22861 typedef enum {                                  /*!< GPIO_PADREGL_PAD47STRNG                                                   */
22862   GPIO_PADREGL_PAD47STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22863   GPIO_PADREGL_PAD47STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22864 } GPIO_PADREGL_PAD47STRNG_Enum;
22865 
22866 /* ===========================================  GPIO PADREGL PAD47INPEN [25..25]  ============================================ */
22867 typedef enum {                                  /*!< GPIO_PADREGL_PAD47INPEN                                                   */
22868   GPIO_PADREGL_PAD47INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22869   GPIO_PADREGL_PAD47INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22870 } GPIO_PADREGL_PAD47INPEN_Enum;
22871 
22872 /* ============================================  GPIO PADREGL PAD47PULL [24..24]  ============================================ */
22873 typedef enum {                                  /*!< GPIO_PADREGL_PAD47PULL                                                    */
22874   GPIO_PADREGL_PAD47PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22875   GPIO_PADREGL_PAD47PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22876 } GPIO_PADREGL_PAD47PULL_Enum;
22877 
22878 /* ===========================================  GPIO PADREGL PAD46FNCSEL [19..21]  =========================================== */
22879 typedef enum {                                  /*!< GPIO_PADREGL_PAD46FNCSEL                                                  */
22880   GPIO_PADREGL_PAD46FNCSEL_32khz_XT    = 0,     /*!< 32khz_XT : Configure as the 32kHz output clock from the crystal           */
22881   GPIO_PADREGL_PAD46FNCSEL_NCE46       = 1,     /*!< NCE46 : IOM/MSPI nCE group 46                                             */
22882   GPIO_PADREGL_PAD46FNCSEL_CT24        = 2,     /*!< CT24 : CTIMER connection 24                                               */
22883   GPIO_PADREGL_PAD46FNCSEL_GPIO46      = 3,     /*!< GPIO46 : Configure as GPIO46                                              */
22884   GPIO_PADREGL_PAD46FNCSEL_SCCRST      = 4,     /*!< SCCRST : SCARD reset output                                               */
22885   GPIO_PADREGL_PAD46FNCSEL_PDMCLK      = 5,     /*!< PDMCLK : PDM serial clock output                                          */
22886   GPIO_PADREGL_PAD46FNCSEL_UART1TX     = 6,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
22887   GPIO_PADREGL_PAD46FNCSEL_SWO         = 7,     /*!< SWO : Configure as the serial wire debug SWO signal                       */
22888 } GPIO_PADREGL_PAD46FNCSEL_Enum;
22889 
22890 /* ===========================================  GPIO PADREGL PAD46STRNG [18..18]  ============================================ */
22891 typedef enum {                                  /*!< GPIO_PADREGL_PAD46STRNG                                                   */
22892   GPIO_PADREGL_PAD46STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22893   GPIO_PADREGL_PAD46STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22894 } GPIO_PADREGL_PAD46STRNG_Enum;
22895 
22896 /* ===========================================  GPIO PADREGL PAD46INPEN [17..17]  ============================================ */
22897 typedef enum {                                  /*!< GPIO_PADREGL_PAD46INPEN                                                   */
22898   GPIO_PADREGL_PAD46INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22899   GPIO_PADREGL_PAD46INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22900 } GPIO_PADREGL_PAD46INPEN_Enum;
22901 
22902 /* ============================================  GPIO PADREGL PAD46PULL [16..16]  ============================================ */
22903 typedef enum {                                  /*!< GPIO_PADREGL_PAD46PULL                                                    */
22904   GPIO_PADREGL_PAD46PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22905   GPIO_PADREGL_PAD46PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22906 } GPIO_PADREGL_PAD46PULL_Enum;
22907 
22908 /* ===========================================  GPIO PADREGL PAD45FNCSEL [11..13]  =========================================== */
22909 typedef enum {                                  /*!< GPIO_PADREGL_PAD45FNCSEL                                                  */
22910   GPIO_PADREGL_PAD45FNCSEL_UA1CTS      = 0,     /*!< UA1CTS : Configure as the UART1 CTS input signal                          */
22911   GPIO_PADREGL_PAD45FNCSEL_NCE45       = 1,     /*!< NCE45 : IOM/MSPI nCE group 45                                             */
22912   GPIO_PADREGL_PAD45FNCSEL_CT22        = 2,     /*!< CT22 : CTIMER connection 22                                               */
22913   GPIO_PADREGL_PAD45FNCSEL_GPIO45      = 3,     /*!< GPIO45 : Configure as GPIO45                                              */
22914   GPIO_PADREGL_PAD45FNCSEL_I2SDAT      = 4,     /*!< I2SDAT : I2S serial data output                                           */
22915   GPIO_PADREGL_PAD45FNCSEL_PDMDATA     = 5,     /*!< PDMDATA : PDM serial data input                                           */
22916   GPIO_PADREGL_PAD45FNCSEL_UART0RX     = 6,     /*!< UART0RX : Configure as the SPI channel 5 nCE signal from IOMSTR5          */
22917   GPIO_PADREGL_PAD45FNCSEL_SWO         = 7,     /*!< SWO : Configure as the serial wire debug SWO signal                       */
22918 } GPIO_PADREGL_PAD45FNCSEL_Enum;
22919 
22920 /* ===========================================  GPIO PADREGL PAD45STRNG [10..10]  ============================================ */
22921 typedef enum {                                  /*!< GPIO_PADREGL_PAD45STRNG                                                   */
22922   GPIO_PADREGL_PAD45STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22923   GPIO_PADREGL_PAD45STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22924 } GPIO_PADREGL_PAD45STRNG_Enum;
22925 
22926 /* ============================================  GPIO PADREGL PAD45INPEN [9..9]  ============================================= */
22927 typedef enum {                                  /*!< GPIO_PADREGL_PAD45INPEN                                                   */
22928   GPIO_PADREGL_PAD45INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22929   GPIO_PADREGL_PAD45INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22930 } GPIO_PADREGL_PAD45INPEN_Enum;
22931 
22932 /* =============================================  GPIO PADREGL PAD45PULL [8..8]  ============================================= */
22933 typedef enum {                                  /*!< GPIO_PADREGL_PAD45PULL                                                    */
22934   GPIO_PADREGL_PAD45PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22935   GPIO_PADREGL_PAD45PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22936 } GPIO_PADREGL_PAD45PULL_Enum;
22937 
22938 /* ============================================  GPIO PADREGL PAD44FNCSEL [3..5]  ============================================ */
22939 typedef enum {                                  /*!< GPIO_PADREGL_PAD44FNCSEL                                                  */
22940   GPIO_PADREGL_PAD44FNCSEL_UA1RTS      = 0,     /*!< UA1RTS : Configure as the UART1 RTS output signal                         */
22941   GPIO_PADREGL_PAD44FNCSEL_NCE44       = 1,     /*!< NCE44 : IOM/MSPI nCE group 44                                             */
22942   GPIO_PADREGL_PAD44FNCSEL_CT20        = 2,     /*!< CT20 : CTIMER connection 20                                               */
22943   GPIO_PADREGL_PAD44FNCSEL_GPIO44      = 3,     /*!< GPIO44 : Configure as GPIO44                                              */
22944   GPIO_PADREGL_PAD44FNCSEL_M4MOSI      = 5,     /*!< M4MOSI : Configure as the IOMSTR4 SPI MOSI signal                         */
22945   GPIO_PADREGL_PAD44FNCSEL_M5nCE6      = 6,     /*!< M5nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR5           */
22946 } GPIO_PADREGL_PAD44FNCSEL_Enum;
22947 
22948 /* ============================================  GPIO PADREGL PAD44STRNG [2..2]  ============================================= */
22949 typedef enum {                                  /*!< GPIO_PADREGL_PAD44STRNG                                                   */
22950   GPIO_PADREGL_PAD44STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22951   GPIO_PADREGL_PAD44STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22952 } GPIO_PADREGL_PAD44STRNG_Enum;
22953 
22954 /* ============================================  GPIO PADREGL PAD44INPEN [1..1]  ============================================= */
22955 typedef enum {                                  /*!< GPIO_PADREGL_PAD44INPEN                                                   */
22956   GPIO_PADREGL_PAD44INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22957   GPIO_PADREGL_PAD44INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22958 } GPIO_PADREGL_PAD44INPEN_Enum;
22959 
22960 /* =============================================  GPIO PADREGL PAD44PULL [0..0]  ============================================= */
22961 typedef enum {                                  /*!< GPIO_PADREGL_PAD44PULL                                                    */
22962   GPIO_PADREGL_PAD44PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22963   GPIO_PADREGL_PAD44PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22964 } GPIO_PADREGL_PAD44PULL_Enum;
22965 
22966 /* ========================================================  PADREGM  ======================================================== */
22967 /* ===========================================  GPIO PADREGM PAD51FNCSEL [27..29]  =========================================== */
22968 typedef enum {                                  /*!< GPIO_PADREGM_PAD51FNCSEL                                                  */
22969   GPIO_PADREGM_PAD51FNCSEL_MSPI1_0     = 0,     /*!< MSPI1_0 : Configure as the MSPI1 0 signal                                 */
22970   GPIO_PADREGM_PAD51FNCSEL_NCE51       = 1,     /*!< NCE51 : IOM/MSPI nCE group 51                                             */
22971   GPIO_PADREGM_PAD51FNCSEL_CT1         = 2,     /*!< CT1 : CTIMER connection 1                                                 */
22972   GPIO_PADREGM_PAD51FNCSEL_GPIO51      = 3,     /*!< GPIO51 : Configure as GPIO51                                              */
22973 } GPIO_PADREGM_PAD51FNCSEL_Enum;
22974 
22975 /* ===========================================  GPIO PADREGM PAD51STRNG [26..26]  ============================================ */
22976 typedef enum {                                  /*!< GPIO_PADREGM_PAD51STRNG                                                   */
22977   GPIO_PADREGM_PAD51STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
22978   GPIO_PADREGM_PAD51STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
22979 } GPIO_PADREGM_PAD51STRNG_Enum;
22980 
22981 /* ===========================================  GPIO PADREGM PAD51INPEN [25..25]  ============================================ */
22982 typedef enum {                                  /*!< GPIO_PADREGM_PAD51INPEN                                                   */
22983   GPIO_PADREGM_PAD51INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
22984   GPIO_PADREGM_PAD51INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
22985 } GPIO_PADREGM_PAD51INPEN_Enum;
22986 
22987 /* ============================================  GPIO PADREGM PAD51PULL [24..24]  ============================================ */
22988 typedef enum {                                  /*!< GPIO_PADREGM_PAD51PULL                                                    */
22989   GPIO_PADREGM_PAD51PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
22990   GPIO_PADREGM_PAD51PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
22991 } GPIO_PADREGM_PAD51PULL_Enum;
22992 
22993 /* ===========================================  GPIO PADREGM PAD50FNCSEL [19..21]  =========================================== */
22994 typedef enum {                                  /*!< GPIO_PADREGM_PAD50FNCSEL                                                  */
22995   GPIO_PADREGM_PAD50FNCSEL_SWO         = 0,     /*!< SWO : Configure as the SWO output                                         */
22996   GPIO_PADREGM_PAD50FNCSEL_NCE50       = 1,     /*!< NCE50 : IOM/MSPI nCE group 50                                             */
22997   GPIO_PADREGM_PAD50FNCSEL_CT0         = 2,     /*!< CT0 : CTIMER connection 0                                                 */
22998   GPIO_PADREGM_PAD50FNCSEL_GPIO50      = 3,     /*!< GPIO50 : Configure as GPIO50                                              */
22999   GPIO_PADREGM_PAD50FNCSEL_UART0TX     = 4,     /*!< UART0TX : Configure as the UART0 TX output                                */
23000   GPIO_PADREGM_PAD50FNCSEL_UART0RX     = 5,     /*!< UART0RX : Configure as the UART0 RX input                                 */
23001   GPIO_PADREGM_PAD50FNCSEL_UART1TX     = 6,     /*!< UART1TX : Configure as the UART1 TX output                                */
23002   GPIO_PADREGM_PAD50FNCSEL_UART1RX     = 7,     /*!< UART1RX : Configure as the UART1 RX input                                 */
23003 } GPIO_PADREGM_PAD50FNCSEL_Enum;
23004 
23005 /* ===========================================  GPIO PADREGM PAD50STRNG [18..18]  ============================================ */
23006 typedef enum {                                  /*!< GPIO_PADREGM_PAD50STRNG                                                   */
23007   GPIO_PADREGM_PAD50STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23008   GPIO_PADREGM_PAD50STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23009 } GPIO_PADREGM_PAD50STRNG_Enum;
23010 
23011 /* ===========================================  GPIO PADREGM PAD50INPEN [17..17]  ============================================ */
23012 typedef enum {                                  /*!< GPIO_PADREGM_PAD50INPEN                                                   */
23013   GPIO_PADREGM_PAD50INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23014   GPIO_PADREGM_PAD50INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23015 } GPIO_PADREGM_PAD50INPEN_Enum;
23016 
23017 /* ============================================  GPIO PADREGM PAD50PULL [16..16]  ============================================ */
23018 typedef enum {                                  /*!< GPIO_PADREGM_PAD50PULL                                                    */
23019   GPIO_PADREGM_PAD50PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23020   GPIO_PADREGM_PAD50PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23021 } GPIO_PADREGM_PAD50PULL_Enum;
23022 
23023 /* ============================================  GPIO PADREGM PAD49RSEL [14..15]  ============================================ */
23024 typedef enum {                                  /*!< GPIO_PADREGM_PAD49RSEL                                                    */
23025   GPIO_PADREGM_PAD49RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
23026   GPIO_PADREGM_PAD49RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
23027   GPIO_PADREGM_PAD49RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
23028   GPIO_PADREGM_PAD49RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
23029 } GPIO_PADREGM_PAD49RSEL_Enum;
23030 
23031 /* ===========================================  GPIO PADREGM PAD49FNCSEL [11..13]  =========================================== */
23032 typedef enum {                                  /*!< GPIO_PADREGM_PAD49FNCSEL                                                  */
23033   GPIO_PADREGM_PAD49FNCSEL_UART0RX     = 0,     /*!< UART0RX : Configure as the UART0 RX input signal                          */
23034   GPIO_PADREGM_PAD49FNCSEL_NCE49       = 1,     /*!< NCE49 : IOM/MSPPI nCE group 49                                            */
23035   GPIO_PADREGM_PAD49FNCSEL_CT30        = 2,     /*!< CT30 : CTIMER connection 30                                               */
23036   GPIO_PADREGM_PAD49FNCSEL_GPIO49      = 3,     /*!< GPIO49 : Configure as GPIO49                                              */
23037   GPIO_PADREGM_PAD49FNCSEL_M5SDAWIR3   = 4,     /*!< M5SDAWIR3 : Configure as the IOMSTR5 I2C SDA or SPI WIR3 signal           */
23038   GPIO_PADREGM_PAD49FNCSEL_M5MISO      = 5,     /*!< M5MISO : Configure as the IOMSTR5 SPI MISO input signal                   */
23039 } GPIO_PADREGM_PAD49FNCSEL_Enum;
23040 
23041 /* ===========================================  GPIO PADREGM PAD49STRNG [10..10]  ============================================ */
23042 typedef enum {                                  /*!< GPIO_PADREGM_PAD49STRNG                                                   */
23043   GPIO_PADREGM_PAD49STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23044   GPIO_PADREGM_PAD49STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23045 } GPIO_PADREGM_PAD49STRNG_Enum;
23046 
23047 /* ============================================  GPIO PADREGM PAD49INPEN [9..9]  ============================================= */
23048 typedef enum {                                  /*!< GPIO_PADREGM_PAD49INPEN                                                   */
23049   GPIO_PADREGM_PAD49INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23050   GPIO_PADREGM_PAD49INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23051 } GPIO_PADREGM_PAD49INPEN_Enum;
23052 
23053 /* =============================================  GPIO PADREGM PAD49PULL [8..8]  ============================================= */
23054 typedef enum {                                  /*!< GPIO_PADREGM_PAD49PULL                                                    */
23055   GPIO_PADREGM_PAD49PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23056   GPIO_PADREGM_PAD49PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23057 } GPIO_PADREGM_PAD49PULL_Enum;
23058 
23059 /* =============================================  GPIO PADREGM PAD48RSEL [6..7]  ============================================= */
23060 typedef enum {                                  /*!< GPIO_PADREGM_PAD48RSEL                                                    */
23061   GPIO_PADREGM_PAD48RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
23062   GPIO_PADREGM_PAD48RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
23063   GPIO_PADREGM_PAD48RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
23064   GPIO_PADREGM_PAD48RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
23065 } GPIO_PADREGM_PAD48RSEL_Enum;
23066 
23067 /* ============================================  GPIO PADREGM PAD48FNCSEL [3..5]  ============================================ */
23068 typedef enum {                                  /*!< GPIO_PADREGM_PAD48FNCSEL                                                  */
23069   GPIO_PADREGM_PAD48FNCSEL_UART0TX     = 0,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
23070   GPIO_PADREGM_PAD48FNCSEL_NCE48       = 1,     /*!< NCE48 : IOM/MSPI nCE group 48                                             */
23071   GPIO_PADREGM_PAD48FNCSEL_CT28        = 2,     /*!< CT28 : CTIMER connection 28                                               */
23072   GPIO_PADREGM_PAD48FNCSEL_GPIO48      = 3,     /*!< GPIO48 : Configure as GPIO48                                              */
23073   GPIO_PADREGM_PAD48FNCSEL_M5SCL       = 4,     /*!< M5SCL : Configure as the IOMSTR5 I2C SCL clock I/O signal                 */
23074   GPIO_PADREGM_PAD48FNCSEL_M5SCK       = 5,     /*!< M5SCK : Configure as the IOMSTR5 SPI SCK output                           */
23075 } GPIO_PADREGM_PAD48FNCSEL_Enum;
23076 
23077 /* ============================================  GPIO PADREGM PAD48STRNG [2..2]  ============================================= */
23078 typedef enum {                                  /*!< GPIO_PADREGM_PAD48STRNG                                                   */
23079   GPIO_PADREGM_PAD48STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23080   GPIO_PADREGM_PAD48STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23081 } GPIO_PADREGM_PAD48STRNG_Enum;
23082 
23083 /* ============================================  GPIO PADREGM PAD48INPEN [1..1]  ============================================= */
23084 typedef enum {                                  /*!< GPIO_PADREGM_PAD48INPEN                                                   */
23085   GPIO_PADREGM_PAD48INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23086   GPIO_PADREGM_PAD48INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23087 } GPIO_PADREGM_PAD48INPEN_Enum;
23088 
23089 /* =============================================  GPIO PADREGM PAD48PULL [0..0]  ============================================= */
23090 typedef enum {                                  /*!< GPIO_PADREGM_PAD48PULL                                                    */
23091   GPIO_PADREGM_PAD48PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23092   GPIO_PADREGM_PAD48PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23093 } GPIO_PADREGM_PAD48PULL_Enum;
23094 
23095 /* ========================================================  PADREGN  ======================================================== */
23096 /* ===========================================  GPIO PADREGN PAD55FNCSEL [27..29]  =========================================== */
23097 typedef enum {                                  /*!< GPIO_PADREGN_PAD55FNCSEL                                                  */
23098   GPIO_PADREGN_PAD55FNCSEL_MSPI1_4     = 0,     /*!< MSPI1_4 : Configure as the MSPI1 4 signal                                 */
23099   GPIO_PADREGN_PAD55FNCSEL_NCE55       = 1,     /*!< NCE55 : IOM/MSPI nCE group 55                                             */
23100   GPIO_PADREGN_PAD55FNCSEL_CT5         = 2,     /*!< CT5 : CTIMER connection 5                                                 */
23101   GPIO_PADREGN_PAD55FNCSEL_GPIO55      = 3,     /*!< GPIO55 : Configure as GPIO55                                              */
23102 } GPIO_PADREGN_PAD55FNCSEL_Enum;
23103 
23104 /* ===========================================  GPIO PADREGN PAD55STRNG [26..26]  ============================================ */
23105 typedef enum {                                  /*!< GPIO_PADREGN_PAD55STRNG                                                   */
23106   GPIO_PADREGN_PAD55STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23107   GPIO_PADREGN_PAD55STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23108 } GPIO_PADREGN_PAD55STRNG_Enum;
23109 
23110 /* ===========================================  GPIO PADREGN PAD55INPEN [25..25]  ============================================ */
23111 typedef enum {                                  /*!< GPIO_PADREGN_PAD55INPEN                                                   */
23112   GPIO_PADREGN_PAD55INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23113   GPIO_PADREGN_PAD55INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23114 } GPIO_PADREGN_PAD55INPEN_Enum;
23115 
23116 /* ============================================  GPIO PADREGN PAD55PULL [24..24]  ============================================ */
23117 typedef enum {                                  /*!< GPIO_PADREGN_PAD55PULL                                                    */
23118   GPIO_PADREGN_PAD55PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23119   GPIO_PADREGN_PAD55PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23120 } GPIO_PADREGN_PAD55PULL_Enum;
23121 
23122 /* ===========================================  GPIO PADREGN PAD54FNCSEL [19..21]  =========================================== */
23123 typedef enum {                                  /*!< GPIO_PADREGN_PAD54FNCSEL                                                  */
23124   GPIO_PADREGN_PAD54FNCSEL_MSPI1_3     = 0,     /*!< MSPI1_3 : Configure as the MSPI1 3 signal                                 */
23125   GPIO_PADREGN_PAD54FNCSEL_NCE54       = 1,     /*!< NCE54 : IOM/MSPI nCE group 54                                             */
23126   GPIO_PADREGN_PAD54FNCSEL_CT4         = 2,     /*!< CT4 : CTIMER connection 4                                                 */
23127   GPIO_PADREGN_PAD54FNCSEL_GPIO54      = 3,     /*!< GPIO54 : Configure as GPIO54                                              */
23128 } GPIO_PADREGN_PAD54FNCSEL_Enum;
23129 
23130 /* ===========================================  GPIO PADREGN PAD54STRNG [18..18]  ============================================ */
23131 typedef enum {                                  /*!< GPIO_PADREGN_PAD54STRNG                                                   */
23132   GPIO_PADREGN_PAD54STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23133   GPIO_PADREGN_PAD54STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23134 } GPIO_PADREGN_PAD54STRNG_Enum;
23135 
23136 /* ===========================================  GPIO PADREGN PAD54INPEN [17..17]  ============================================ */
23137 typedef enum {                                  /*!< GPIO_PADREGN_PAD54INPEN                                                   */
23138   GPIO_PADREGN_PAD54INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23139   GPIO_PADREGN_PAD54INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23140 } GPIO_PADREGN_PAD54INPEN_Enum;
23141 
23142 /* ============================================  GPIO PADREGN PAD54PULL [16..16]  ============================================ */
23143 typedef enum {                                  /*!< GPIO_PADREGN_PAD54PULL                                                    */
23144   GPIO_PADREGN_PAD54PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23145   GPIO_PADREGN_PAD54PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23146 } GPIO_PADREGN_PAD54PULL_Enum;
23147 
23148 /* ===========================================  GPIO PADREGN PAD53FNCSEL [11..13]  =========================================== */
23149 typedef enum {                                  /*!< GPIO_PADREGN_PAD53FNCSEL                                                  */
23150   GPIO_PADREGN_PAD53FNCSEL_MSPI1_2     = 0,     /*!< MSPI1_2 : Configure as the MSPI1 2 signal                                 */
23151   GPIO_PADREGN_PAD53FNCSEL_NCE53       = 1,     /*!< NCE53 : IOM/MSPI nCE group 53                                             */
23152   GPIO_PADREGN_PAD53FNCSEL_CT3         = 2,     /*!< CT3 : CTIMER connection 3                                                 */
23153   GPIO_PADREGN_PAD53FNCSEL_GPIO53      = 3,     /*!< GPIO53 : Configure as GPIO53                                              */
23154 } GPIO_PADREGN_PAD53FNCSEL_Enum;
23155 
23156 /* ===========================================  GPIO PADREGN PAD53STRNG [10..10]  ============================================ */
23157 typedef enum {                                  /*!< GPIO_PADREGN_PAD53STRNG                                                   */
23158   GPIO_PADREGN_PAD53STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23159   GPIO_PADREGN_PAD53STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23160 } GPIO_PADREGN_PAD53STRNG_Enum;
23161 
23162 /* ============================================  GPIO PADREGN PAD53INPEN [9..9]  ============================================= */
23163 typedef enum {                                  /*!< GPIO_PADREGN_PAD53INPEN                                                   */
23164   GPIO_PADREGN_PAD53INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23165   GPIO_PADREGN_PAD53INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23166 } GPIO_PADREGN_PAD53INPEN_Enum;
23167 
23168 /* =============================================  GPIO PADREGN PAD53PULL [8..8]  ============================================= */
23169 typedef enum {                                  /*!< GPIO_PADREGN_PAD53PULL                                                    */
23170   GPIO_PADREGN_PAD53PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23171   GPIO_PADREGN_PAD53PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23172 } GPIO_PADREGN_PAD53PULL_Enum;
23173 
23174 /* ============================================  GPIO PADREGN PAD52FNCSEL [3..5]  ============================================ */
23175 typedef enum {                                  /*!< GPIO_PADREGN_PAD52FNCSEL                                                  */
23176   GPIO_PADREGN_PAD52FNCSEL_MSPI1_1     = 0,     /*!< MSPI1_1 : Configure as the MSPI1 1 signal                                 */
23177   GPIO_PADREGN_PAD52FNCSEL_NCE52       = 1,     /*!< NCE52 : IOM/MSPI nCE group 52                                             */
23178   GPIO_PADREGN_PAD52FNCSEL_CT2         = 2,     /*!< CT2 : CTIMER connection 2                                                 */
23179   GPIO_PADREGN_PAD52FNCSEL_GPIO52      = 3,     /*!< GPIO52 : Configure as GPIO52                                              */
23180 } GPIO_PADREGN_PAD52FNCSEL_Enum;
23181 
23182 /* ============================================  GPIO PADREGN PAD52STRNG [2..2]  ============================================= */
23183 typedef enum {                                  /*!< GPIO_PADREGN_PAD52STRNG                                                   */
23184   GPIO_PADREGN_PAD52STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23185   GPIO_PADREGN_PAD52STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23186 } GPIO_PADREGN_PAD52STRNG_Enum;
23187 
23188 /* ============================================  GPIO PADREGN PAD52INPEN [1..1]  ============================================= */
23189 typedef enum {                                  /*!< GPIO_PADREGN_PAD52INPEN                                                   */
23190   GPIO_PADREGN_PAD52INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23191   GPIO_PADREGN_PAD52INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23192 } GPIO_PADREGN_PAD52INPEN_Enum;
23193 
23194 /* =============================================  GPIO PADREGN PAD52PULL [0..0]  ============================================= */
23195 typedef enum {                                  /*!< GPIO_PADREGN_PAD52PULL                                                    */
23196   GPIO_PADREGN_PAD52PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23197   GPIO_PADREGN_PAD52PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23198 } GPIO_PADREGN_PAD52PULL_Enum;
23199 
23200 /* ========================================================  PADREGO  ======================================================== */
23201 /* ===========================================  GPIO PADREGO PAD59FNCSEL [27..29]  =========================================== */
23202 typedef enum {                                  /*!< GPIO_PADREGO_PAD59FNCSEL                                                  */
23203   GPIO_PADREGO_PAD59FNCSEL_MSPI1_8     = 0,     /*!< MSPI1_8 : Configure as the MSPI1 8 signal                                 */
23204   GPIO_PADREGO_PAD59FNCSEL_NCE59       = 1,     /*!< NCE59 : IOM/MSPI nCE group 59                                             */
23205   GPIO_PADREGO_PAD59FNCSEL_CT9         = 2,     /*!< CT9 : CTIMER connection 9                                                 */
23206   GPIO_PADREGO_PAD59FNCSEL_GPIO59      = 3,     /*!< GPIO59 : Configure as GPIO59                                              */
23207 } GPIO_PADREGO_PAD59FNCSEL_Enum;
23208 
23209 /* ===========================================  GPIO PADREGO PAD59STRNG [26..26]  ============================================ */
23210 typedef enum {                                  /*!< GPIO_PADREGO_PAD59STRNG                                                   */
23211   GPIO_PADREGO_PAD59STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23212   GPIO_PADREGO_PAD59STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23213 } GPIO_PADREGO_PAD59STRNG_Enum;
23214 
23215 /* ===========================================  GPIO PADREGO PAD59INPEN [25..25]  ============================================ */
23216 typedef enum {                                  /*!< GPIO_PADREGO_PAD59INPEN                                                   */
23217   GPIO_PADREGO_PAD59INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23218   GPIO_PADREGO_PAD59INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23219 } GPIO_PADREGO_PAD59INPEN_Enum;
23220 
23221 /* ============================================  GPIO PADREGO PAD59PULL [24..24]  ============================================ */
23222 typedef enum {                                  /*!< GPIO_PADREGO_PAD59PULL                                                    */
23223   GPIO_PADREGO_PAD59PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23224   GPIO_PADREGO_PAD59PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23225 } GPIO_PADREGO_PAD59PULL_Enum;
23226 
23227 /* ===========================================  GPIO PADREGO PAD58FNCSEL [19..21]  =========================================== */
23228 typedef enum {                                  /*!< GPIO_PADREGO_PAD58FNCSEL                                                  */
23229   GPIO_PADREGO_PAD58FNCSEL_MSPI1_7     = 0,     /*!< MSPI1_7 : Configure as the MSPI1 7 signal                                 */
23230   GPIO_PADREGO_PAD58FNCSEL_NCE58       = 1,     /*!< NCE58 : IOM/MSPI nCE group 58                                             */
23231   GPIO_PADREGO_PAD58FNCSEL_CT8         = 2,     /*!< CT8 : CTIMER connection 8                                                 */
23232   GPIO_PADREGO_PAD58FNCSEL_GPIO58      = 3,     /*!< GPIO58 : Configure as GPIO58                                              */
23233 } GPIO_PADREGO_PAD58FNCSEL_Enum;
23234 
23235 /* ===========================================  GPIO PADREGO PAD58STRNG [18..18]  ============================================ */
23236 typedef enum {                                  /*!< GPIO_PADREGO_PAD58STRNG                                                   */
23237   GPIO_PADREGO_PAD58STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23238   GPIO_PADREGO_PAD58STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23239 } GPIO_PADREGO_PAD58STRNG_Enum;
23240 
23241 /* ===========================================  GPIO PADREGO PAD58INPEN [17..17]  ============================================ */
23242 typedef enum {                                  /*!< GPIO_PADREGO_PAD58INPEN                                                   */
23243   GPIO_PADREGO_PAD58INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23244   GPIO_PADREGO_PAD58INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23245 } GPIO_PADREGO_PAD58INPEN_Enum;
23246 
23247 /* ============================================  GPIO PADREGO PAD58PULL [16..16]  ============================================ */
23248 typedef enum {                                  /*!< GPIO_PADREGO_PAD58PULL                                                    */
23249   GPIO_PADREGO_PAD58PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23250   GPIO_PADREGO_PAD58PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23251 } GPIO_PADREGO_PAD58PULL_Enum;
23252 
23253 /* ===========================================  GPIO PADREGO PAD57FNCSEL [11..13]  =========================================== */
23254 typedef enum {                                  /*!< GPIO_PADREGO_PAD57FNCSEL                                                  */
23255   GPIO_PADREGO_PAD57FNCSEL_MSPI1_6     = 0,     /*!< MSPI1_6 : Configure as the MSPI1 6 signal                                 */
23256   GPIO_PADREGO_PAD57FNCSEL_NCE57       = 1,     /*!< NCE57 : IOM/MSPI nCE group 57                                             */
23257   GPIO_PADREGO_PAD57FNCSEL_CT7         = 2,     /*!< CT7 : CTIMER connection 7                                                 */
23258   GPIO_PADREGO_PAD57FNCSEL_GPIO57      = 3,     /*!< GPIO57 : Configure as GPIO57                                              */
23259 } GPIO_PADREGO_PAD57FNCSEL_Enum;
23260 
23261 /* ===========================================  GPIO PADREGO PAD57STRNG [10..10]  ============================================ */
23262 typedef enum {                                  /*!< GPIO_PADREGO_PAD57STRNG                                                   */
23263   GPIO_PADREGO_PAD57STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23264   GPIO_PADREGO_PAD57STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23265 } GPIO_PADREGO_PAD57STRNG_Enum;
23266 
23267 /* ============================================  GPIO PADREGO PAD57INPEN [9..9]  ============================================= */
23268 typedef enum {                                  /*!< GPIO_PADREGO_PAD57INPEN                                                   */
23269   GPIO_PADREGO_PAD57INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23270   GPIO_PADREGO_PAD57INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23271 } GPIO_PADREGO_PAD57INPEN_Enum;
23272 
23273 /* =============================================  GPIO PADREGO PAD57PULL [8..8]  ============================================= */
23274 typedef enum {                                  /*!< GPIO_PADREGO_PAD57PULL                                                    */
23275   GPIO_PADREGO_PAD57PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23276   GPIO_PADREGO_PAD57PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23277 } GPIO_PADREGO_PAD57PULL_Enum;
23278 
23279 /* ============================================  GPIO PADREGO PAD56FNCSEL [3..5]  ============================================ */
23280 typedef enum {                                  /*!< GPIO_PADREGO_PAD56FNCSEL                                                  */
23281   GPIO_PADREGO_PAD56FNCSEL_MSPI1_5     = 0,     /*!< MSPI1_5 : Configure as the MSPI1 5 signal                                 */
23282   GPIO_PADREGO_PAD56FNCSEL_NCE56       = 1,     /*!< NCE56 : IOM/MSPI nCE group 56                                             */
23283   GPIO_PADREGO_PAD56FNCSEL_CT6         = 2,     /*!< CT6 : CTIMER connection 6                                                 */
23284   GPIO_PADREGO_PAD56FNCSEL_GPIO56      = 3,     /*!< GPIO56 : Configure as GPIO56                                              */
23285 } GPIO_PADREGO_PAD56FNCSEL_Enum;
23286 
23287 /* ============================================  GPIO PADREGO PAD56STRNG [2..2]  ============================================= */
23288 typedef enum {                                  /*!< GPIO_PADREGO_PAD56STRNG                                                   */
23289   GPIO_PADREGO_PAD56STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23290   GPIO_PADREGO_PAD56STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23291 } GPIO_PADREGO_PAD56STRNG_Enum;
23292 
23293 /* ============================================  GPIO PADREGO PAD56INPEN [1..1]  ============================================= */
23294 typedef enum {                                  /*!< GPIO_PADREGO_PAD56INPEN                                                   */
23295   GPIO_PADREGO_PAD56INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23296   GPIO_PADREGO_PAD56INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23297 } GPIO_PADREGO_PAD56INPEN_Enum;
23298 
23299 /* =============================================  GPIO PADREGO PAD56PULL [0..0]  ============================================= */
23300 typedef enum {                                  /*!< GPIO_PADREGO_PAD56PULL                                                    */
23301   GPIO_PADREGO_PAD56PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23302   GPIO_PADREGO_PAD56PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23303 } GPIO_PADREGO_PAD56PULL_Enum;
23304 
23305 /* ========================================================  PADREGP  ======================================================== */
23306 /* ===========================================  GPIO PADREGP PAD63FNCSEL [27..29]  =========================================== */
23307 typedef enum {                                  /*!< GPIO_PADREGP_PAD63FNCSEL                                                  */
23308   GPIO_PADREGP_PAD63FNCSEL_SWO         = 0,     /*!< SWO : Configure as the SWO output                                         */
23309   GPIO_PADREGP_PAD63FNCSEL_NCE63       = 1,     /*!< NCE63 : IOM/MSPI nCE group 63                                             */
23310   GPIO_PADREGP_PAD63FNCSEL_CT13        = 2,     /*!< CT13 : CTIMER connection 13                                               */
23311   GPIO_PADREGP_PAD63FNCSEL_GPIO63      = 3,     /*!< GPIO63 : Configure as GPIO63                                              */
23312   GPIO_PADREGP_PAD63FNCSEL_UART0TX     = 4,     /*!< UART0TX : Configure as the UART0 TX output                                */
23313   GPIO_PADREGP_PAD63FNCSEL_UART0RX     = 5,     /*!< UART0RX : Configure as the UART0 RX input                                 */
23314   GPIO_PADREGP_PAD63FNCSEL_UART1TX     = 6,     /*!< UART1TX : Configure as the UART1 TX output                                */
23315   GPIO_PADREGP_PAD63FNCSEL_UART1RX     = 7,     /*!< UART1RX : Configure as the UART1 RX input                                 */
23316 } GPIO_PADREGP_PAD63FNCSEL_Enum;
23317 
23318 /* ===========================================  GPIO PADREGP PAD63STRNG [26..26]  ============================================ */
23319 typedef enum {                                  /*!< GPIO_PADREGP_PAD63STRNG                                                   */
23320   GPIO_PADREGP_PAD63STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23321   GPIO_PADREGP_PAD63STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23322 } GPIO_PADREGP_PAD63STRNG_Enum;
23323 
23324 /* ===========================================  GPIO PADREGP PAD63INPEN [25..25]  ============================================ */
23325 typedef enum {                                  /*!< GPIO_PADREGP_PAD63INPEN                                                   */
23326   GPIO_PADREGP_PAD63INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23327   GPIO_PADREGP_PAD63INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23328 } GPIO_PADREGP_PAD63INPEN_Enum;
23329 
23330 /* ============================================  GPIO PADREGP PAD63PULL [24..24]  ============================================ */
23331 typedef enum {                                  /*!< GPIO_PADREGP_PAD63PULL                                                    */
23332   GPIO_PADREGP_PAD63PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23333   GPIO_PADREGP_PAD63PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23334 } GPIO_PADREGP_PAD63PULL_Enum;
23335 
23336 /* ===========================================  GPIO PADREGP PAD62FNCSEL [19..21]  =========================================== */
23337 typedef enum {                                  /*!< GPIO_PADREGP_PAD62FNCSEL                                                  */
23338   GPIO_PADREGP_PAD62FNCSEL_SWO         = 0,     /*!< SWO : Configure as the SWO output                                         */
23339   GPIO_PADREGP_PAD62FNCSEL_NCE62       = 1,     /*!< NCE62 : IOM/MSPI nCE group 62                                             */
23340   GPIO_PADREGP_PAD62FNCSEL_CT12        = 2,     /*!< CT12 : CTIMER connection 12                                               */
23341   GPIO_PADREGP_PAD62FNCSEL_GPIO62      = 3,     /*!< GPIO62 : Configure as GPIO62                                              */
23342   GPIO_PADREGP_PAD62FNCSEL_UA0CTS      = 4,     /*!< UA0CTS : Configure as the UART0 CTS input                                 */
23343   GPIO_PADREGP_PAD62FNCSEL_UA0RTS      = 5,     /*!< UA0RTS : Configure as the UART0 RTS output                                */
23344   GPIO_PADREGP_PAD62FNCSEL_UA1CTS      = 6,     /*!< UA1CTS : Configure as the UART1 CTS input                                 */
23345   GPIO_PADREGP_PAD62FNCSEL_UA1RTS      = 7,     /*!< UA1RTS : Configure as the UART1 RTS output                                */
23346 } GPIO_PADREGP_PAD62FNCSEL_Enum;
23347 
23348 /* ===========================================  GPIO PADREGP PAD62STRNG [18..18]  ============================================ */
23349 typedef enum {                                  /*!< GPIO_PADREGP_PAD62STRNG                                                   */
23350   GPIO_PADREGP_PAD62STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23351   GPIO_PADREGP_PAD62STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23352 } GPIO_PADREGP_PAD62STRNG_Enum;
23353 
23354 /* ===========================================  GPIO PADREGP PAD62INPEN [17..17]  ============================================ */
23355 typedef enum {                                  /*!< GPIO_PADREGP_PAD62INPEN                                                   */
23356   GPIO_PADREGP_PAD62INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23357   GPIO_PADREGP_PAD62INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23358 } GPIO_PADREGP_PAD62INPEN_Enum;
23359 
23360 /* ============================================  GPIO PADREGP PAD62PULL [16..16]  ============================================ */
23361 typedef enum {                                  /*!< GPIO_PADREGP_PAD62PULL                                                    */
23362   GPIO_PADREGP_PAD62PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23363   GPIO_PADREGP_PAD62PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23364 } GPIO_PADREGP_PAD62PULL_Enum;
23365 
23366 /* ===========================================  GPIO PADREGP PAD61FNCSEL [11..13]  =========================================== */
23367 typedef enum {                                  /*!< GPIO_PADREGP_PAD61FNCSEL                                                  */
23368   GPIO_PADREGP_PAD61FNCSEL_SWO         = 0,     /*!< SWO : Configure as the SWO output                                         */
23369   GPIO_PADREGP_PAD61FNCSEL_NCE61       = 1,     /*!< NCE61 : IOM/MSPI nCE group 61                                             */
23370   GPIO_PADREGP_PAD61FNCSEL_CT11        = 2,     /*!< CT11 : CTIMER connection 11                                               */
23371   GPIO_PADREGP_PAD61FNCSEL_GPIO61      = 3,     /*!< GPIO61 : Configure as GPIO61                                              */
23372   GPIO_PADREGP_PAD61FNCSEL_UART0TX     = 4,     /*!< UART0TX : Configure as the UART0 TX output                                */
23373   GPIO_PADREGP_PAD61FNCSEL_UART0RX     = 5,     /*!< UART0RX : Configure as the UART0 RX input                                 */
23374   GPIO_PADREGP_PAD61FNCSEL_UART1TX     = 6,     /*!< UART1TX : Configure as the UART1 TX output                                */
23375   GPIO_PADREGP_PAD61FNCSEL_UART1RX     = 7,     /*!< UART1RX : Configure as the UART1 RX input                                 */
23376 } GPIO_PADREGP_PAD61FNCSEL_Enum;
23377 
23378 /* ===========================================  GPIO PADREGP PAD61STRNG [10..10]  ============================================ */
23379 typedef enum {                                  /*!< GPIO_PADREGP_PAD61STRNG                                                   */
23380   GPIO_PADREGP_PAD61STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23381   GPIO_PADREGP_PAD61STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23382 } GPIO_PADREGP_PAD61STRNG_Enum;
23383 
23384 /* ============================================  GPIO PADREGP PAD61INPEN [9..9]  ============================================= */
23385 typedef enum {                                  /*!< GPIO_PADREGP_PAD61INPEN                                                   */
23386   GPIO_PADREGP_PAD61INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23387   GPIO_PADREGP_PAD61INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23388 } GPIO_PADREGP_PAD61INPEN_Enum;
23389 
23390 /* =============================================  GPIO PADREGP PAD61PULL [8..8]  ============================================= */
23391 typedef enum {                                  /*!< GPIO_PADREGP_PAD61PULL                                                    */
23392   GPIO_PADREGP_PAD61PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23393   GPIO_PADREGP_PAD61PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23394 } GPIO_PADREGP_PAD61PULL_Enum;
23395 
23396 /* ============================================  GPIO PADREGP PAD60FNCSEL [3..5]  ============================================ */
23397 typedef enum {                                  /*!< GPIO_PADREGP_PAD60FNCSEL                                                  */
23398   GPIO_PADREGP_PAD60FNCSEL_MSPI1_9     = 0,     /*!< MSPI1_9 : Configure as the MSPI1 9 signal                                 */
23399   GPIO_PADREGP_PAD60FNCSEL_NCE60       = 1,     /*!< NCE60 : IOM/MSPI nCE group 60                                             */
23400   GPIO_PADREGP_PAD60FNCSEL_CT10        = 2,     /*!< CT10 : CTIMER connection 10                                               */
23401   GPIO_PADREGP_PAD60FNCSEL_GPIO60      = 3,     /*!< GPIO60 : Configure as GPIO60                                              */
23402 } GPIO_PADREGP_PAD60FNCSEL_Enum;
23403 
23404 /* ============================================  GPIO PADREGP PAD60STRNG [2..2]  ============================================= */
23405 typedef enum {                                  /*!< GPIO_PADREGP_PAD60STRNG                                                   */
23406   GPIO_PADREGP_PAD60STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23407   GPIO_PADREGP_PAD60STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23408 } GPIO_PADREGP_PAD60STRNG_Enum;
23409 
23410 /* ============================================  GPIO PADREGP PAD60INPEN [1..1]  ============================================= */
23411 typedef enum {                                  /*!< GPIO_PADREGP_PAD60INPEN                                                   */
23412   GPIO_PADREGP_PAD60INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23413   GPIO_PADREGP_PAD60INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23414 } GPIO_PADREGP_PAD60INPEN_Enum;
23415 
23416 /* =============================================  GPIO PADREGP PAD60PULL [0..0]  ============================================= */
23417 typedef enum {                                  /*!< GPIO_PADREGP_PAD60PULL                                                    */
23418   GPIO_PADREGP_PAD60PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23419   GPIO_PADREGP_PAD60PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23420 } GPIO_PADREGP_PAD60PULL_Enum;
23421 
23422 /* ========================================================  PADREGQ  ======================================================== */
23423 /* ===========================================  GPIO PADREGQ PAD67FNCSEL [27..29]  =========================================== */
23424 typedef enum {                                  /*!< GPIO_PADREGQ_PAD67FNCSEL                                                  */
23425   GPIO_PADREGQ_PAD67FNCSEL_MSPI2_3     = 0,     /*!< MSPI2_3 : Configure as the MSPI2 3 signal                                 */
23426   GPIO_PADREGQ_PAD67FNCSEL_NCE67       = 1,     /*!< NCE67 : IOM/MSPI nCE group 67                                             */
23427   GPIO_PADREGQ_PAD67FNCSEL_CT17        = 2,     /*!< CT17 : CTIMER connection 17                                               */
23428   GPIO_PADREGQ_PAD67FNCSEL_GPIO67      = 3,     /*!< GPIO67 : Configure as GPIO67                                              */
23429 } GPIO_PADREGQ_PAD67FNCSEL_Enum;
23430 
23431 /* ===========================================  GPIO PADREGQ PAD67STRNG [26..26]  ============================================ */
23432 typedef enum {                                  /*!< GPIO_PADREGQ_PAD67STRNG                                                   */
23433   GPIO_PADREGQ_PAD67STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23434   GPIO_PADREGQ_PAD67STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23435 } GPIO_PADREGQ_PAD67STRNG_Enum;
23436 
23437 /* ===========================================  GPIO PADREGQ PAD67INPEN [25..25]  ============================================ */
23438 typedef enum {                                  /*!< GPIO_PADREGQ_PAD67INPEN                                                   */
23439   GPIO_PADREGQ_PAD67INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23440   GPIO_PADREGQ_PAD67INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23441 } GPIO_PADREGQ_PAD67INPEN_Enum;
23442 
23443 /* ============================================  GPIO PADREGQ PAD67PULL [24..24]  ============================================ */
23444 typedef enum {                                  /*!< GPIO_PADREGQ_PAD67PULL                                                    */
23445   GPIO_PADREGQ_PAD67PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23446   GPIO_PADREGQ_PAD67PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23447 } GPIO_PADREGQ_PAD67PULL_Enum;
23448 
23449 /* ===========================================  GPIO PADREGQ PAD66FNCSEL [19..21]  =========================================== */
23450 typedef enum {                                  /*!< GPIO_PADREGQ_PAD66FNCSEL                                                  */
23451   GPIO_PADREGQ_PAD66FNCSEL_MSPI2_2     = 0,     /*!< MSPI2_2 : Configure as the MSPI2 2 signal                                 */
23452   GPIO_PADREGQ_PAD66FNCSEL_NCE66       = 1,     /*!< NCE66 : IOM/MSPI nCE group 66                                             */
23453   GPIO_PADREGQ_PAD66FNCSEL_CT16        = 2,     /*!< CT16 : CTIMER connection 16                                               */
23454   GPIO_PADREGQ_PAD66FNCSEL_GPIO66      = 3,     /*!< GPIO66 : Configure as GPIO66                                              */
23455 } GPIO_PADREGQ_PAD66FNCSEL_Enum;
23456 
23457 /* ===========================================  GPIO PADREGQ PAD66STRNG [18..18]  ============================================ */
23458 typedef enum {                                  /*!< GPIO_PADREGQ_PAD66STRNG                                                   */
23459   GPIO_PADREGQ_PAD66STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23460   GPIO_PADREGQ_PAD66STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23461 } GPIO_PADREGQ_PAD66STRNG_Enum;
23462 
23463 /* ===========================================  GPIO PADREGQ PAD66INPEN [17..17]  ============================================ */
23464 typedef enum {                                  /*!< GPIO_PADREGQ_PAD66INPEN                                                   */
23465   GPIO_PADREGQ_PAD66INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23466   GPIO_PADREGQ_PAD66INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23467 } GPIO_PADREGQ_PAD66INPEN_Enum;
23468 
23469 /* ============================================  GPIO PADREGQ PAD66PULL [16..16]  ============================================ */
23470 typedef enum {                                  /*!< GPIO_PADREGQ_PAD66PULL                                                    */
23471   GPIO_PADREGQ_PAD66PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23472   GPIO_PADREGQ_PAD66PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23473 } GPIO_PADREGQ_PAD66PULL_Enum;
23474 
23475 /* ===========================================  GPIO PADREGQ PAD65FNCSEL [11..13]  =========================================== */
23476 typedef enum {                                  /*!< GPIO_PADREGQ_PAD65FNCSEL                                                  */
23477   GPIO_PADREGQ_PAD65FNCSEL_MSPI2_1     = 0,     /*!< MSPI2_1 : Configure as the MSPI2 1 signal                                 */
23478   GPIO_PADREGQ_PAD65FNCSEL_NCE65       = 1,     /*!< NCE65 : IOM/MSPI nCE group 65                                             */
23479   GPIO_PADREGQ_PAD65FNCSEL_CT15        = 2,     /*!< CT15 : CTIMER connection 15                                               */
23480   GPIO_PADREGQ_PAD65FNCSEL_GPIO65      = 3,     /*!< GPIO65 : Configure as GPIO65                                              */
23481 } GPIO_PADREGQ_PAD65FNCSEL_Enum;
23482 
23483 /* ===========================================  GPIO PADREGQ PAD65STRNG [10..10]  ============================================ */
23484 typedef enum {                                  /*!< GPIO_PADREGQ_PAD65STRNG                                                   */
23485   GPIO_PADREGQ_PAD65STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23486   GPIO_PADREGQ_PAD65STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23487 } GPIO_PADREGQ_PAD65STRNG_Enum;
23488 
23489 /* ============================================  GPIO PADREGQ PAD65INPEN [9..9]  ============================================= */
23490 typedef enum {                                  /*!< GPIO_PADREGQ_PAD65INPEN                                                   */
23491   GPIO_PADREGQ_PAD65INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23492   GPIO_PADREGQ_PAD65INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23493 } GPIO_PADREGQ_PAD65INPEN_Enum;
23494 
23495 /* =============================================  GPIO PADREGQ PAD65PULL [8..8]  ============================================= */
23496 typedef enum {                                  /*!< GPIO_PADREGQ_PAD65PULL                                                    */
23497   GPIO_PADREGQ_PAD65PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23498   GPIO_PADREGQ_PAD65PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23499 } GPIO_PADREGQ_PAD65PULL_Enum;
23500 
23501 /* ============================================  GPIO PADREGQ PAD64FNCSEL [3..5]  ============================================ */
23502 typedef enum {                                  /*!< GPIO_PADREGQ_PAD64FNCSEL                                                  */
23503   GPIO_PADREGQ_PAD64FNCSEL_MSPI2_0     = 0,     /*!< MSPI2_0 : Configure as the MSPI2 0 signal                                 */
23504   GPIO_PADREGQ_PAD64FNCSEL_NCE64       = 1,     /*!< NCE64 : IOM/MSPI nCE group 64                                             */
23505   GPIO_PADREGQ_PAD64FNCSEL_CT14        = 2,     /*!< CT14 : CTIMER connection 14                                               */
23506   GPIO_PADREGQ_PAD64FNCSEL_GPIO64      = 3,     /*!< GPIO64 : Configure as GPIO64                                              */
23507 } GPIO_PADREGQ_PAD64FNCSEL_Enum;
23508 
23509 /* ============================================  GPIO PADREGQ PAD64STRNG [2..2]  ============================================= */
23510 typedef enum {                                  /*!< GPIO_PADREGQ_PAD64STRNG                                                   */
23511   GPIO_PADREGQ_PAD64STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23512   GPIO_PADREGQ_PAD64STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23513 } GPIO_PADREGQ_PAD64STRNG_Enum;
23514 
23515 /* ============================================  GPIO PADREGQ PAD64INPEN [1..1]  ============================================= */
23516 typedef enum {                                  /*!< GPIO_PADREGQ_PAD64INPEN                                                   */
23517   GPIO_PADREGQ_PAD64INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23518   GPIO_PADREGQ_PAD64INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23519 } GPIO_PADREGQ_PAD64INPEN_Enum;
23520 
23521 /* =============================================  GPIO PADREGQ PAD64PULL [0..0]  ============================================= */
23522 typedef enum {                                  /*!< GPIO_PADREGQ_PAD64PULL                                                    */
23523   GPIO_PADREGQ_PAD64PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23524   GPIO_PADREGQ_PAD64PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23525 } GPIO_PADREGQ_PAD64PULL_Enum;
23526 
23527 /* ========================================================  PADREGR  ======================================================== */
23528 /* ===========================================  GPIO PADREGR PAD71FNCSEL [27..29]  =========================================== */
23529 typedef enum {                                  /*!< GPIO_PADREGR_PAD71FNCSEL                                                  */
23530   GPIO_PADREGR_PAD71FNCSEL_SWO         = 0,     /*!< SWO : Configure as the SWO output                                         */
23531   GPIO_PADREGR_PAD71FNCSEL_NCE71       = 1,     /*!< NCE71 : IOM/MSPI nCE group 71                                             */
23532   GPIO_PADREGR_PAD71FNCSEL_CT21        = 2,     /*!< CT21 : CTIMER connection 21                                               */
23533   GPIO_PADREGR_PAD71FNCSEL_GPIO71      = 3,     /*!< GPIO71 : Configure as GPIO71                                              */
23534   GPIO_PADREGR_PAD71FNCSEL_UART0TX     = 4,     /*!< UART0TX : Configure as the UART0 TX output                                */
23535   GPIO_PADREGR_PAD71FNCSEL_UART0RX     = 5,     /*!< UART0RX : Configure as the UART0 RX input                                 */
23536   GPIO_PADREGR_PAD71FNCSEL_UART1TX     = 6,     /*!< UART1TX : Configure as the UART1 TX output                                */
23537   GPIO_PADREGR_PAD71FNCSEL_UART1RX     = 7,     /*!< UART1RX : Configure as the UART1 RX input                                 */
23538 } GPIO_PADREGR_PAD71FNCSEL_Enum;
23539 
23540 /* ===========================================  GPIO PADREGR PAD71STRNG [26..26]  ============================================ */
23541 typedef enum {                                  /*!< GPIO_PADREGR_PAD71STRNG                                                   */
23542   GPIO_PADREGR_PAD71STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23543   GPIO_PADREGR_PAD71STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23544 } GPIO_PADREGR_PAD71STRNG_Enum;
23545 
23546 /* ===========================================  GPIO PADREGR PAD71INPEN [25..25]  ============================================ */
23547 typedef enum {                                  /*!< GPIO_PADREGR_PAD71INPEN                                                   */
23548   GPIO_PADREGR_PAD71INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23549   GPIO_PADREGR_PAD71INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23550 } GPIO_PADREGR_PAD71INPEN_Enum;
23551 
23552 /* ============================================  GPIO PADREGR PAD71PULL [24..24]  ============================================ */
23553 typedef enum {                                  /*!< GPIO_PADREGR_PAD71PULL                                                    */
23554   GPIO_PADREGR_PAD71PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23555   GPIO_PADREGR_PAD71PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23556 } GPIO_PADREGR_PAD71PULL_Enum;
23557 
23558 /* ===========================================  GPIO PADREGR PAD70FNCSEL [19..21]  =========================================== */
23559 typedef enum {                                  /*!< GPIO_PADREGR_PAD70FNCSEL                                                  */
23560   GPIO_PADREGR_PAD70FNCSEL_SWO         = 0,     /*!< SWO : Configure as the SWO output                                         */
23561   GPIO_PADREGR_PAD70FNCSEL_NCE70       = 1,     /*!< NCE70 : IOM/MSPI nCE group 70                                             */
23562   GPIO_PADREGR_PAD70FNCSEL_CT20        = 2,     /*!< CT20 : CTIMER connection 20                                               */
23563   GPIO_PADREGR_PAD70FNCSEL_GPIO70      = 3,     /*!< GPIO70 : Configure as GPIO70                                              */
23564   GPIO_PADREGR_PAD70FNCSEL_UART0TX     = 4,     /*!< UART0TX : Configure as the UART0 TX output                                */
23565   GPIO_PADREGR_PAD70FNCSEL_UART0RX     = 5,     /*!< UART0RX : Configure as the UART0 RX input                                 */
23566   GPIO_PADREGR_PAD70FNCSEL_UART1TX     = 6,     /*!< UART1TX : Configure as the UART1 TX output                                */
23567   GPIO_PADREGR_PAD70FNCSEL_UART1RX     = 7,     /*!< UART1RX : Configure as the UART1 RX input                                 */
23568 } GPIO_PADREGR_PAD70FNCSEL_Enum;
23569 
23570 /* ===========================================  GPIO PADREGR PAD70STRNG [18..18]  ============================================ */
23571 typedef enum {                                  /*!< GPIO_PADREGR_PAD70STRNG                                                   */
23572   GPIO_PADREGR_PAD70STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23573   GPIO_PADREGR_PAD70STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23574 } GPIO_PADREGR_PAD70STRNG_Enum;
23575 
23576 /* ===========================================  GPIO PADREGR PAD70INPEN [17..17]  ============================================ */
23577 typedef enum {                                  /*!< GPIO_PADREGR_PAD70INPEN                                                   */
23578   GPIO_PADREGR_PAD70INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23579   GPIO_PADREGR_PAD70INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23580 } GPIO_PADREGR_PAD70INPEN_Enum;
23581 
23582 /* ============================================  GPIO PADREGR PAD70PULL [16..16]  ============================================ */
23583 typedef enum {                                  /*!< GPIO_PADREGR_PAD70PULL                                                    */
23584   GPIO_PADREGR_PAD70PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23585   GPIO_PADREGR_PAD70PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23586 } GPIO_PADREGR_PAD70PULL_Enum;
23587 
23588 /* ===========================================  GPIO PADREGR PAD69FNCSEL [11..13]  =========================================== */
23589 typedef enum {                                  /*!< GPIO_PADREGR_PAD69FNCSEL                                                  */
23590   GPIO_PADREGR_PAD69FNCSEL_SWO         = 0,     /*!< SWO : Configure as the SWO output                                         */
23591   GPIO_PADREGR_PAD69FNCSEL_NCE69       = 1,     /*!< NCE69 : IOM/MSPI nCE group 69                                             */
23592   GPIO_PADREGR_PAD69FNCSEL_CT19        = 2,     /*!< CT19 : CTIMER connection 19                                               */
23593   GPIO_PADREGR_PAD69FNCSEL_GPIO69      = 3,     /*!< GPIO69 : Configure as GPIO69                                              */
23594   GPIO_PADREGR_PAD69FNCSEL_UART0TX     = 4,     /*!< UART0TX : Configure as the UART0 TX output                                */
23595   GPIO_PADREGR_PAD69FNCSEL_UART0RX     = 5,     /*!< UART0RX : Configure as the UART0 RX input                                 */
23596   GPIO_PADREGR_PAD69FNCSEL_UART1TX     = 6,     /*!< UART1TX : Configure as the UART1 TX output                                */
23597   GPIO_PADREGR_PAD69FNCSEL_UART1RX     = 7,     /*!< UART1RX : Configure as the UART1 RX input                                 */
23598 } GPIO_PADREGR_PAD69FNCSEL_Enum;
23599 
23600 /* ===========================================  GPIO PADREGR PAD69STRNG [10..10]  ============================================ */
23601 typedef enum {                                  /*!< GPIO_PADREGR_PAD69STRNG                                                   */
23602   GPIO_PADREGR_PAD69STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23603   GPIO_PADREGR_PAD69STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23604 } GPIO_PADREGR_PAD69STRNG_Enum;
23605 
23606 /* ============================================  GPIO PADREGR PAD69INPEN [9..9]  ============================================= */
23607 typedef enum {                                  /*!< GPIO_PADREGR_PAD69INPEN                                                   */
23608   GPIO_PADREGR_PAD69INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23609   GPIO_PADREGR_PAD69INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23610 } GPIO_PADREGR_PAD69INPEN_Enum;
23611 
23612 /* =============================================  GPIO PADREGR PAD69PULL [8..8]  ============================================= */
23613 typedef enum {                                  /*!< GPIO_PADREGR_PAD69PULL                                                    */
23614   GPIO_PADREGR_PAD69PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23615   GPIO_PADREGR_PAD69PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23616 } GPIO_PADREGR_PAD69PULL_Enum;
23617 
23618 /* ============================================  GPIO PADREGR PAD68FNCSEL [3..5]  ============================================ */
23619 typedef enum {                                  /*!< GPIO_PADREGR_PAD68FNCSEL                                                  */
23620   GPIO_PADREGR_PAD68FNCSEL_MSPI2_4     = 0,     /*!< MSPI2_4 : Configure as the MSPI2 4 signal                                 */
23621   GPIO_PADREGR_PAD68FNCSEL_NCE68       = 1,     /*!< NCE68 : IOM/MSPI nCE group 68                                             */
23622   GPIO_PADREGR_PAD68FNCSEL_CT18        = 2,     /*!< CT18 : CTIMER connection 18                                               */
23623   GPIO_PADREGR_PAD68FNCSEL_GPIO68      = 3,     /*!< GPIO68 : Configure as GPIO68                                              */
23624 } GPIO_PADREGR_PAD68FNCSEL_Enum;
23625 
23626 /* ============================================  GPIO PADREGR PAD68STRNG [2..2]  ============================================= */
23627 typedef enum {                                  /*!< GPIO_PADREGR_PAD68STRNG                                                   */
23628   GPIO_PADREGR_PAD68STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23629   GPIO_PADREGR_PAD68STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23630 } GPIO_PADREGR_PAD68STRNG_Enum;
23631 
23632 /* ============================================  GPIO PADREGR PAD68INPEN [1..1]  ============================================= */
23633 typedef enum {                                  /*!< GPIO_PADREGR_PAD68INPEN                                                   */
23634   GPIO_PADREGR_PAD68INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23635   GPIO_PADREGR_PAD68INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23636 } GPIO_PADREGR_PAD68INPEN_Enum;
23637 
23638 /* =============================================  GPIO PADREGR PAD68PULL [0..0]  ============================================= */
23639 typedef enum {                                  /*!< GPIO_PADREGR_PAD68PULL                                                    */
23640   GPIO_PADREGR_PAD68PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23641   GPIO_PADREGR_PAD68PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23642 } GPIO_PADREGR_PAD68PULL_Enum;
23643 
23644 /* ========================================================  PADREGS  ======================================================== */
23645 /* ===========================================  GPIO PADREGS PAD73FNCSEL [11..13]  =========================================== */
23646 typedef enum {                                  /*!< GPIO_PADREGS_PAD73FNCSEL                                                  */
23647   GPIO_PADREGS_PAD73FNCSEL_SWO         = 0,     /*!< SWO : Configure as the SWO output                                         */
23648   GPIO_PADREGS_PAD73FNCSEL_NCE73       = 1,     /*!< NCE73 : IOM/MSPI nCE group 73                                             */
23649   GPIO_PADREGS_PAD73FNCSEL_CT23        = 2,     /*!< CT23 : CTIMER connection 23                                               */
23650   GPIO_PADREGS_PAD73FNCSEL_GPIO73      = 3,     /*!< GPIO73 : Configure as GPIO73                                              */
23651   GPIO_PADREGS_PAD73FNCSEL_UA0CTS      = 4,     /*!< UA0CTS : Configure as the UART0 CTS input                                 */
23652   GPIO_PADREGS_PAD73FNCSEL_UA0RTS      = 5,     /*!< UA0RTS : Configure as the UART0 RTS output                                */
23653   GPIO_PADREGS_PAD73FNCSEL_UA1CTS      = 6,     /*!< UA1CTS : Configure as the UART1 CTS input                                 */
23654   GPIO_PADREGS_PAD73FNCSEL_UA1RTS      = 7,     /*!< UA1RTS : Configure as the UART1 RTS output                                */
23655 } GPIO_PADREGS_PAD73FNCSEL_Enum;
23656 
23657 /* ===========================================  GPIO PADREGS PAD73STRNG [10..10]  ============================================ */
23658 typedef enum {                                  /*!< GPIO_PADREGS_PAD73STRNG                                                   */
23659   GPIO_PADREGS_PAD73STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23660   GPIO_PADREGS_PAD73STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23661 } GPIO_PADREGS_PAD73STRNG_Enum;
23662 
23663 /* ============================================  GPIO PADREGS PAD73INPEN [9..9]  ============================================= */
23664 typedef enum {                                  /*!< GPIO_PADREGS_PAD73INPEN                                                   */
23665   GPIO_PADREGS_PAD73INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23666   GPIO_PADREGS_PAD73INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23667 } GPIO_PADREGS_PAD73INPEN_Enum;
23668 
23669 /* =============================================  GPIO PADREGS PAD73PULL [8..8]  ============================================= */
23670 typedef enum {                                  /*!< GPIO_PADREGS_PAD73PULL                                                    */
23671   GPIO_PADREGS_PAD73PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23672   GPIO_PADREGS_PAD73PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23673 } GPIO_PADREGS_PAD73PULL_Enum;
23674 
23675 /* ============================================  GPIO PADREGS PAD72FNCSEL [3..5]  ============================================ */
23676 typedef enum {                                  /*!< GPIO_PADREGS_PAD72FNCSEL                                                  */
23677   GPIO_PADREGS_PAD72FNCSEL_SWO         = 0,     /*!< SWO : Configure as the SWO output                                         */
23678   GPIO_PADREGS_PAD72FNCSEL_NCE72       = 1,     /*!< NCE72 : IOM/MSPI nCE group 72                                             */
23679   GPIO_PADREGS_PAD72FNCSEL_CT22        = 2,     /*!< CT22 : CTIMER connection 22                                               */
23680   GPIO_PADREGS_PAD72FNCSEL_GPIO72      = 3,     /*!< GPIO72 : Configure as GPIO72                                              */
23681   GPIO_PADREGS_PAD72FNCSEL_UART0TX     = 4,     /*!< UART0TX : Configure as the UART0 TX output                                */
23682   GPIO_PADREGS_PAD72FNCSEL_UART0RX     = 5,     /*!< UART0RX : Configure as the UART0 RX input                                 */
23683   GPIO_PADREGS_PAD72FNCSEL_UART1TX     = 6,     /*!< UART1TX : Configure as the UART1 TX output                                */
23684   GPIO_PADREGS_PAD72FNCSEL_UART1RX     = 7,     /*!< UART1RX : Configure as the UART1 RX input                                 */
23685 } GPIO_PADREGS_PAD72FNCSEL_Enum;
23686 
23687 /* ============================================  GPIO PADREGS PAD72STRNG [2..2]  ============================================= */
23688 typedef enum {                                  /*!< GPIO_PADREGS_PAD72STRNG                                                   */
23689   GPIO_PADREGS_PAD72STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
23690   GPIO_PADREGS_PAD72STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
23691 } GPIO_PADREGS_PAD72STRNG_Enum;
23692 
23693 /* ============================================  GPIO PADREGS PAD72INPEN [1..1]  ============================================= */
23694 typedef enum {                                  /*!< GPIO_PADREGS_PAD72INPEN                                                   */
23695   GPIO_PADREGS_PAD72INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
23696   GPIO_PADREGS_PAD72INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
23697 } GPIO_PADREGS_PAD72INPEN_Enum;
23698 
23699 /* =============================================  GPIO PADREGS PAD72PULL [0..0]  ============================================= */
23700 typedef enum {                                  /*!< GPIO_PADREGS_PAD72PULL                                                    */
23701   GPIO_PADREGS_PAD72PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
23702   GPIO_PADREGS_PAD72PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
23703 } GPIO_PADREGS_PAD72PULL_Enum;
23704 
23705 /* =========================================================  CFGA  ========================================================== */
23706 /* =============================================  GPIO CFGA GPIO7INTD [31..31]  ============================================== */
23707 typedef enum {                                  /*!< GPIO_CFGA_GPIO7INTD                                                       */
23708   GPIO_CFGA_GPIO7INTD_nCELOW           = 0,     /*!< nCELOW : Applies when PAD7FNCSEL = NCE7 - nCE polarity active
23709                                                      low                                                                       */
23710   GPIO_CFGA_GPIO7INTD_nCEHIGH          = 1,     /*!< nCEHIGH : Applies when PAD7FNCSEL = NCE7 - nCE polarity active
23711                                                      high                                                                      */
23712 } GPIO_CFGA_GPIO7INTD_Enum;
23713 
23714 /* ============================================  GPIO CFGA GPIO7OUTCFG [29..30]  ============================================= */
23715 typedef enum {                                  /*!< GPIO_CFGA_GPIO7OUTCFG                                                     */
23716   GPIO_CFGA_GPIO7OUTCFG_DIS            = 0,     /*!< DIS : Applies when PAD7FNCSEL = GPIO - Output disabled                    */
23717   GPIO_CFGA_GPIO7OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : Applies when PAD7FNCSEL = GPIO - Output is push-pull           */
23718   GPIO_CFGA_GPIO7OUTCFG_OD             = 2,     /*!< OD : Applies when PAD7FNCSEL = GPIO - Output is open drain                */
23719   GPIO_CFGA_GPIO7OUTCFG_TS             = 3,     /*!< TS : Applies when PAD7FNCSEL = GPIO - Output is tri-state                 */
23720 } GPIO_CFGA_GPIO7OUTCFG_Enum;
23721 
23722 /* =============================================  GPIO CFGA GPIO7INCFG [28..28]  ============================================= */
23723 typedef enum {                                  /*!< GPIO_CFGA_GPIO7INCFG                                                      */
23724   GPIO_CFGA_GPIO7INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
23725   GPIO_CFGA_GPIO7INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23726 } GPIO_CFGA_GPIO7INCFG_Enum;
23727 
23728 /* =============================================  GPIO CFGA GPIO6INTD [27..27]  ============================================== */
23729 typedef enum {                                  /*!< GPIO_CFGA_GPIO6INTD                                                       */
23730   GPIO_CFGA_GPIO6INTD_INTDIS           = 0,     /*!< INTDIS : Applies when GPIO6INCFG = 1 - No interrupt on GPIO
23731                                                      transition                                                                */
23732   GPIO_CFGA_GPIO6INTD_INTBOTH          = 1,     /*!< INTBOTH : Applies when GPIO6INCFG = 1 - Interrupt on either
23733                                                      low to high or high to low GPIO transition                                */
23734 } GPIO_CFGA_GPIO6INTD_Enum;
23735 
23736 /* ============================================  GPIO CFGA GPIO6OUTCFG [25..26]  ============================================= */
23737 typedef enum {                                  /*!< GPIO_CFGA_GPIO6OUTCFG                                                     */
23738   GPIO_CFGA_GPIO6OUTCFG_DIS            = 0,     /*!< DIS : Applies when PAD6FNCSEL = GPIO - Output disabled                    */
23739   GPIO_CFGA_GPIO6OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : Applies when PAD6FNCSEL = GPIO - Output is push-pull           */
23740   GPIO_CFGA_GPIO6OUTCFG_OD             = 2,     /*!< OD : Applies when PAD6FNCSEL = GPIO - Output is open drain                */
23741   GPIO_CFGA_GPIO6OUTCFG_TS             = 3,     /*!< TS : Applies when PAD6FNCSEL = GPIO - Output is tri-state                 */
23742 } GPIO_CFGA_GPIO6OUTCFG_Enum;
23743 
23744 /* =============================================  GPIO CFGA GPIO6INCFG [24..24]  ============================================= */
23745 typedef enum {                                  /*!< GPIO_CFGA_GPIO6INCFG                                                      */
23746   GPIO_CFGA_GPIO6INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
23747   GPIO_CFGA_GPIO6INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23748 } GPIO_CFGA_GPIO6INCFG_Enum;
23749 
23750 /* =============================================  GPIO CFGA GPIO5INTD [23..23]  ============================================== */
23751 typedef enum {                                  /*!< GPIO_CFGA_GPIO5INTD                                                       */
23752   GPIO_CFGA_GPIO5INTD_INTDIS           = 0,     /*!< INTDIS : Applies when GPIO5INCFG = 1 - No interrupt on GPIO
23753                                                      transition                                                                */
23754   GPIO_CFGA_GPIO5INTD_INTBOTH          = 1,     /*!< INTBOTH : Applies when GPIO5INCFG = 1 - Interrupt on either
23755                                                      low to high or high to low GPIO transition                                */
23756 } GPIO_CFGA_GPIO5INTD_Enum;
23757 
23758 /* ============================================  GPIO CFGA GPIO5OUTCFG [21..22]  ============================================= */
23759 typedef enum {                                  /*!< GPIO_CFGA_GPIO5OUTCFG                                                     */
23760   GPIO_CFGA_GPIO5OUTCFG_DIS            = 0,     /*!< DIS : Applies when PAD5FNCSEL = GPIO - Output disabled                    */
23761   GPIO_CFGA_GPIO5OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : Applies when PAD5FNCSEL = GPIO - Output is push-pull           */
23762   GPIO_CFGA_GPIO5OUTCFG_OD             = 2,     /*!< OD : Applies when PAD5FNCSEL = GPIO - Output is open drain                */
23763   GPIO_CFGA_GPIO5OUTCFG_TS             = 3,     /*!< TS : Applies when PAD5FNCSEL = GPIO - Output is tri-state                 */
23764 } GPIO_CFGA_GPIO5OUTCFG_Enum;
23765 
23766 /* =============================================  GPIO CFGA GPIO5INCFG [20..20]  ============================================= */
23767 typedef enum {                                  /*!< GPIO_CFGA_GPIO5INCFG                                                      */
23768   GPIO_CFGA_GPIO5INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
23769   GPIO_CFGA_GPIO5INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23770 } GPIO_CFGA_GPIO5INCFG_Enum;
23771 
23772 /* =============================================  GPIO CFGA GPIO4INTD [19..19]  ============================================== */
23773 typedef enum {                                  /*!< GPIO_CFGA_GPIO4INTD                                                       */
23774   GPIO_CFGA_GPIO4INTD_nCELOW           = 0,     /*!< nCELOW : Applies when PAD4FNCSEL = NCE4 - nCE polarity active
23775                                                      low                                                                       */
23776   GPIO_CFGA_GPIO4INTD_nCEHIGH          = 1,     /*!< nCEHIGH : Applies when PAD4FNCSEL = NCE4 - nCE polarity active
23777                                                      high                                                                      */
23778 } GPIO_CFGA_GPIO4INTD_Enum;
23779 
23780 /* ============================================  GPIO CFGA GPIO4OUTCFG [17..18]  ============================================= */
23781 typedef enum {                                  /*!< GPIO_CFGA_GPIO4OUTCFG                                                     */
23782   GPIO_CFGA_GPIO4OUTCFG_DIS            = 0,     /*!< DIS : Applies when PAD4FNCSEL = GPIO - Output disabled                    */
23783   GPIO_CFGA_GPIO4OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : Applies when PAD4FNCSEL = GPIO - Output is push-pull           */
23784   GPIO_CFGA_GPIO4OUTCFG_OD             = 2,     /*!< OD : Applies when PAD4FNCSEL = GPIO - Output is open drain                */
23785   GPIO_CFGA_GPIO4OUTCFG_TS             = 3,     /*!< TS : Applies when PAD4FNCSEL = GPIO - Output is tri-state                 */
23786 } GPIO_CFGA_GPIO4OUTCFG_Enum;
23787 
23788 /* =============================================  GPIO CFGA GPIO4INCFG [16..16]  ============================================= */
23789 typedef enum {                                  /*!< GPIO_CFGA_GPIO4INCFG                                                      */
23790   GPIO_CFGA_GPIO4INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
23791   GPIO_CFGA_GPIO4INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23792 } GPIO_CFGA_GPIO4INCFG_Enum;
23793 
23794 /* =============================================  GPIO CFGA GPIO3INTD [15..15]  ============================================== */
23795 typedef enum {                                  /*!< GPIO_CFGA_GPIO3INTD                                                       */
23796   GPIO_CFGA_GPIO3INTD_nCELOW           = 0,     /*!< nCELOW : Applies when PAD3FNCSEL = NCE3 - nCE polarity active
23797                                                      low                                                                       */
23798   GPIO_CFGA_GPIO3INTD_nCEHIGH          = 1,     /*!< nCEHIGH : Applies when PAD3FNCSEL = NCE3 - nCE polarity active
23799                                                      high                                                                      */
23800 } GPIO_CFGA_GPIO3INTD_Enum;
23801 
23802 /* ============================================  GPIO CFGA GPIO3OUTCFG [13..14]  ============================================= */
23803 typedef enum {                                  /*!< GPIO_CFGA_GPIO3OUTCFG                                                     */
23804   GPIO_CFGA_GPIO3OUTCFG_DIS            = 0,     /*!< DIS : Applies when PAD3FNCSEL = GPIO - Output disabled                    */
23805   GPIO_CFGA_GPIO3OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : Applies when PAD3FNCSEL = GPIO - Output is push-pull           */
23806   GPIO_CFGA_GPIO3OUTCFG_OD             = 2,     /*!< OD : Applies when PAD3FNCSEL = GPIO - Output is open drain                */
23807   GPIO_CFGA_GPIO3OUTCFG_TS             = 3,     /*!< TS : Applies when PAD3FNCSEL = GPIO - Output is tri-state                 */
23808 } GPIO_CFGA_GPIO3OUTCFG_Enum;
23809 
23810 /* =============================================  GPIO CFGA GPIO3INCFG [12..12]  ============================================= */
23811 typedef enum {                                  /*!< GPIO_CFGA_GPIO3INCFG                                                      */
23812   GPIO_CFGA_GPIO3INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
23813   GPIO_CFGA_GPIO3INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23814 } GPIO_CFGA_GPIO3INCFG_Enum;
23815 
23816 /* =============================================  GPIO CFGA GPIO2INTD [11..11]  ============================================== */
23817 typedef enum {                                  /*!< GPIO_CFGA_GPIO2INTD                                                       */
23818   GPIO_CFGA_GPIO2INTD_nCELOW           = 0,     /*!< nCELOW : Applies when PAD2FNCSEL = NCE2 - nCE polarity active
23819                                                      low                                                                       */
23820   GPIO_CFGA_GPIO2INTD_nCEHIGH          = 1,     /*!< nCEHIGH : Applies when PAD2FNCSEL = NCE2 - nCE polarity active
23821                                                      high                                                                      */
23822 } GPIO_CFGA_GPIO2INTD_Enum;
23823 
23824 /* =============================================  GPIO CFGA GPIO2OUTCFG [9..10]  ============================================= */
23825 typedef enum {                                  /*!< GPIO_CFGA_GPIO2OUTCFG                                                     */
23826   GPIO_CFGA_GPIO2OUTCFG_DIS            = 0,     /*!< DIS : Applies when PAD2FNCSEL = GPIO - Output disabled                    */
23827   GPIO_CFGA_GPIO2OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : Applies when PAD2FNCSEL = GPIO - Output is push-pull           */
23828   GPIO_CFGA_GPIO2OUTCFG_OD             = 2,     /*!< OD : Applies when PAD2FNCSEL = GPIO - Output is open drain                */
23829   GPIO_CFGA_GPIO2OUTCFG_TS             = 3,     /*!< TS : Applies when PAD2FNCSEL = GPIO - Output is tri-state                 */
23830 } GPIO_CFGA_GPIO2OUTCFG_Enum;
23831 
23832 /* ==============================================  GPIO CFGA GPIO2INCFG [8..8]  ============================================== */
23833 typedef enum {                                  /*!< GPIO_CFGA_GPIO2INCFG                                                      */
23834   GPIO_CFGA_GPIO2INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
23835   GPIO_CFGA_GPIO2INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23836 } GPIO_CFGA_GPIO2INCFG_Enum;
23837 
23838 /* ==============================================  GPIO CFGA GPIO1INTD [7..7]  =============================================== */
23839 typedef enum {                                  /*!< GPIO_CFGA_GPIO1INTD                                                       */
23840   GPIO_CFGA_GPIO1INTD_nCELOW           = 0,     /*!< nCELOW : Applies when PAD1FNCSEL = NCE1 - nCE polarity active
23841                                                      low                                                                       */
23842   GPIO_CFGA_GPIO1INTD_nCEHIGH          = 1,     /*!< nCEHIGH : Applies when PAD1FNCSEL = NCE1 - nCE polarity active
23843                                                      high                                                                      */
23844 } GPIO_CFGA_GPIO1INTD_Enum;
23845 
23846 /* =============================================  GPIO CFGA GPIO1OUTCFG [5..6]  ============================================== */
23847 typedef enum {                                  /*!< GPIO_CFGA_GPIO1OUTCFG                                                     */
23848   GPIO_CFGA_GPIO1OUTCFG_DIS            = 0,     /*!< DIS : Applies when PAD1FNCSEL = GPIO - Output disabled                    */
23849   GPIO_CFGA_GPIO1OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : Applies when PAD1FNCSEL = GPIO - Output is push-pull           */
23850   GPIO_CFGA_GPIO1OUTCFG_OD             = 2,     /*!< OD : Applies when PAD1FNCSEL = GPIO - Output is open drain                */
23851   GPIO_CFGA_GPIO1OUTCFG_TS             = 3,     /*!< TS : Applies when PAD1FNCSEL = GPIO - Output is tri-state                 */
23852 } GPIO_CFGA_GPIO1OUTCFG_Enum;
23853 
23854 /* ==============================================  GPIO CFGA GPIO1INCFG [4..4]  ============================================== */
23855 typedef enum {                                  /*!< GPIO_CFGA_GPIO1INCFG                                                      */
23856   GPIO_CFGA_GPIO1INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
23857   GPIO_CFGA_GPIO1INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23858 } GPIO_CFGA_GPIO1INCFG_Enum;
23859 
23860 /* ==============================================  GPIO CFGA GPIO0INTD [3..3]  =============================================== */
23861 typedef enum {                                  /*!< GPIO_CFGA_GPIO0INTD                                                       */
23862   GPIO_CFGA_GPIO0INTD_nCELOW           = 0,     /*!< nCELOW : Applies when PAD0FNCSEL = NCE0 - nCE polarity active
23863                                                      low                                                                       */
23864   GPIO_CFGA_GPIO0INTD_nCEHIGH          = 1,     /*!< nCEHIGH : Applies when PAD0FNCSEL = NCE0 - nCE polarity active
23865                                                      high                                                                      */
23866 } GPIO_CFGA_GPIO0INTD_Enum;
23867 
23868 /* =============================================  GPIO CFGA GPIO0OUTCFG [1..2]  ============================================== */
23869 typedef enum {                                  /*!< GPIO_CFGA_GPIO0OUTCFG                                                     */
23870   GPIO_CFGA_GPIO0OUTCFG_DIS            = 0,     /*!< DIS : Applies when PAD0FNCSEL = GPIO - Output disabled                    */
23871   GPIO_CFGA_GPIO0OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : Applies when PAD0FNCSEL = GPIO - Output is push-pull           */
23872   GPIO_CFGA_GPIO0OUTCFG_OD             = 2,     /*!< OD : Applies when PAD0FNCSEL = GPIO - Output is open drain                */
23873   GPIO_CFGA_GPIO0OUTCFG_TS             = 3,     /*!< TS : Applies when PAD0FNCSEL = GPIO - Output is tri-state                 */
23874 } GPIO_CFGA_GPIO0OUTCFG_Enum;
23875 
23876 /* ==============================================  GPIO CFGA GPIO0INCFG [0..0]  ============================================== */
23877 typedef enum {                                  /*!< GPIO_CFGA_GPIO0INCFG                                                      */
23878   GPIO_CFGA_GPIO0INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
23879   GPIO_CFGA_GPIO0INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23880 } GPIO_CFGA_GPIO0INCFG_Enum;
23881 
23882 /* =========================================================  CFGB  ========================================================== */
23883 /* =============================================  GPIO CFGB GPIO15INTD [31..31]  ============================================= */
23884 typedef enum {                                  /*!< GPIO_CFGB_GPIO15INTD                                                      */
23885   GPIO_CFGB_GPIO15INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD15FNCSEL = NCE15 - nCE polarity active
23886                                                      low                                                                       */
23887   GPIO_CFGB_GPIO15INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD15FNCSEL = NCE15 - nCE polarity active
23888                                                      high                                                                      */
23889 } GPIO_CFGB_GPIO15INTD_Enum;
23890 
23891 /* ============================================  GPIO CFGB GPIO15OUTCFG [29..30]  ============================================ */
23892 typedef enum {                                  /*!< GPIO_CFGB_GPIO15OUTCFG                                                    */
23893   GPIO_CFGB_GPIO15OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD15FNCSEL = GPIO - Output disabled                   */
23894   GPIO_CFGB_GPIO15OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD15FNCSEL = GPIO - Output is push-pull          */
23895   GPIO_CFGB_GPIO15OUTCFG_OD            = 2,     /*!< OD : Applies when PAD15FNCSEL = GPIO - Output is open drain               */
23896   GPIO_CFGB_GPIO15OUTCFG_TS            = 3,     /*!< TS : Applies when PAD15FNCSEL = GPIO - Output is tri-state                */
23897 } GPIO_CFGB_GPIO15OUTCFG_Enum;
23898 
23899 /* ============================================  GPIO CFGB GPIO15INCFG [28..28]  ============================================= */
23900 typedef enum {                                  /*!< GPIO_CFGB_GPIO15INCFG                                                     */
23901   GPIO_CFGB_GPIO15INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
23902   GPIO_CFGB_GPIO15INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23903 } GPIO_CFGB_GPIO15INCFG_Enum;
23904 
23905 /* =============================================  GPIO CFGB GPIO14INTD [27..27]  ============================================= */
23906 typedef enum {                                  /*!< GPIO_CFGB_GPIO14INTD                                                      */
23907   GPIO_CFGB_GPIO14INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD14FNCSEL = NCE14 - nCE polarity active
23908                                                      low                                                                       */
23909   GPIO_CFGB_GPIO14INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD14FNCSEL = NCE14 - nCE polarity active
23910                                                      high                                                                      */
23911 } GPIO_CFGB_GPIO14INTD_Enum;
23912 
23913 /* ============================================  GPIO CFGB GPIO14OUTCFG [25..26]  ============================================ */
23914 typedef enum {                                  /*!< GPIO_CFGB_GPIO14OUTCFG                                                    */
23915   GPIO_CFGB_GPIO14OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD14FNCSEL = GPIO - Output disabled                   */
23916   GPIO_CFGB_GPIO14OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD14FNCSEL = GPIO - Output is push-pull          */
23917   GPIO_CFGB_GPIO14OUTCFG_OD            = 2,     /*!< OD : Applies when PAD14FNCSEL = GPIO - Output is open drain               */
23918   GPIO_CFGB_GPIO14OUTCFG_TS            = 3,     /*!< TS : Applies when PAD14FNCSEL = GPIO - Output is tri-state                */
23919 } GPIO_CFGB_GPIO14OUTCFG_Enum;
23920 
23921 /* ============================================  GPIO CFGB GPIO14INCFG [24..24]  ============================================= */
23922 typedef enum {                                  /*!< GPIO_CFGB_GPIO14INCFG                                                     */
23923   GPIO_CFGB_GPIO14INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
23924   GPIO_CFGB_GPIO14INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23925 } GPIO_CFGB_GPIO14INCFG_Enum;
23926 
23927 /* =============================================  GPIO CFGB GPIO13INTD [23..23]  ============================================= */
23928 typedef enum {                                  /*!< GPIO_CFGB_GPIO13INTD                                                      */
23929   GPIO_CFGB_GPIO13INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD13FNCSEL = NCE13 - nCE polarity active
23930                                                      low                                                                       */
23931   GPIO_CFGB_GPIO13INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD13FNCSEL = NCE13 - nCE polarity active
23932                                                      high                                                                      */
23933 } GPIO_CFGB_GPIO13INTD_Enum;
23934 
23935 /* ============================================  GPIO CFGB GPIO13OUTCFG [21..22]  ============================================ */
23936 typedef enum {                                  /*!< GPIO_CFGB_GPIO13OUTCFG                                                    */
23937   GPIO_CFGB_GPIO13OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD13FNCSEL = GPIO - Output disabled                   */
23938   GPIO_CFGB_GPIO13OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD13FNCSEL = GPIO - Output is push-pull          */
23939   GPIO_CFGB_GPIO13OUTCFG_OD            = 2,     /*!< OD : Applies when PAD13FNCSEL = GPIO - Output is open drain               */
23940   GPIO_CFGB_GPIO13OUTCFG_TS            = 3,     /*!< TS : Applies when PAD13FNCSEL = GPIO - Output is tri-state                */
23941 } GPIO_CFGB_GPIO13OUTCFG_Enum;
23942 
23943 /* ============================================  GPIO CFGB GPIO13INCFG [20..20]  ============================================= */
23944 typedef enum {                                  /*!< GPIO_CFGB_GPIO13INCFG                                                     */
23945   GPIO_CFGB_GPIO13INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
23946   GPIO_CFGB_GPIO13INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23947 } GPIO_CFGB_GPIO13INCFG_Enum;
23948 
23949 /* =============================================  GPIO CFGB GPIO12INTD [19..19]  ============================================= */
23950 typedef enum {                                  /*!< GPIO_CFGB_GPIO12INTD                                                      */
23951   GPIO_CFGB_GPIO12INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD12FNCSEL = NCE12 - nCE polarity active
23952                                                      low                                                                       */
23953   GPIO_CFGB_GPIO12INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD12FNCSEL = NCE12 - nCE polarity active
23954                                                      high                                                                      */
23955 } GPIO_CFGB_GPIO12INTD_Enum;
23956 
23957 /* ============================================  GPIO CFGB GPIO12OUTCFG [17..18]  ============================================ */
23958 typedef enum {                                  /*!< GPIO_CFGB_GPIO12OUTCFG                                                    */
23959   GPIO_CFGB_GPIO12OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD12FNCSEL = GPIO - Output disabled                   */
23960   GPIO_CFGB_GPIO12OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD12FNCSEL = GPIO - Output is push-pull          */
23961   GPIO_CFGB_GPIO12OUTCFG_OD            = 2,     /*!< OD : Applies when PAD12FNCSEL = GPIO - Output is open drain               */
23962   GPIO_CFGB_GPIO12OUTCFG_TS            = 3,     /*!< TS : Applies when PAD12FNCSEL = GPIO - Output is tri-state                */
23963 } GPIO_CFGB_GPIO12OUTCFG_Enum;
23964 
23965 /* ============================================  GPIO CFGB GPIO12INCFG [16..16]  ============================================= */
23966 typedef enum {                                  /*!< GPIO_CFGB_GPIO12INCFG                                                     */
23967   GPIO_CFGB_GPIO12INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
23968   GPIO_CFGB_GPIO12INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23969 } GPIO_CFGB_GPIO12INCFG_Enum;
23970 
23971 /* =============================================  GPIO CFGB GPIO11INTD [15..15]  ============================================= */
23972 typedef enum {                                  /*!< GPIO_CFGB_GPIO11INTD                                                      */
23973   GPIO_CFGB_GPIO11INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD11FNCSEL = NCE11 - nCE polarity active
23974                                                      low                                                                       */
23975   GPIO_CFGB_GPIO11INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD11FNCSEL = NCE11 - nCE polarity active
23976                                                      high                                                                      */
23977 } GPIO_CFGB_GPIO11INTD_Enum;
23978 
23979 /* ============================================  GPIO CFGB GPIO11OUTCFG [13..14]  ============================================ */
23980 typedef enum {                                  /*!< GPIO_CFGB_GPIO11OUTCFG                                                    */
23981   GPIO_CFGB_GPIO11OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD11FNCSEL = GPIO - Output disabled                   */
23982   GPIO_CFGB_GPIO11OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD11FNCSEL = GPIO - Output is push-pull          */
23983   GPIO_CFGB_GPIO11OUTCFG_OD            = 2,     /*!< OD : Applies when PAD11FNCSEL = GPIO - Output is open drain               */
23984   GPIO_CFGB_GPIO11OUTCFG_TS            = 3,     /*!< TS : Applies when PAD11FNCSEL = GPIO - Output is tri-state                */
23985 } GPIO_CFGB_GPIO11OUTCFG_Enum;
23986 
23987 /* ============================================  GPIO CFGB GPIO11INCFG [12..12]  ============================================= */
23988 typedef enum {                                  /*!< GPIO_CFGB_GPIO11INCFG                                                     */
23989   GPIO_CFGB_GPIO11INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
23990   GPIO_CFGB_GPIO11INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
23991 } GPIO_CFGB_GPIO11INCFG_Enum;
23992 
23993 /* =============================================  GPIO CFGB GPIO10INTD [11..11]  ============================================= */
23994 typedef enum {                                  /*!< GPIO_CFGB_GPIO10INTD                                                      */
23995   GPIO_CFGB_GPIO10INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD10FNCSEL = NCE10 - nCE polarity active
23996                                                      low                                                                       */
23997   GPIO_CFGB_GPIO10INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD10FNCSEL = NCE10 - nCE polarity active
23998                                                      high                                                                      */
23999 } GPIO_CFGB_GPIO10INTD_Enum;
24000 
24001 /* ============================================  GPIO CFGB GPIO10OUTCFG [9..10]  ============================================= */
24002 typedef enum {                                  /*!< GPIO_CFGB_GPIO10OUTCFG                                                    */
24003   GPIO_CFGB_GPIO10OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD10FNCSEL = GPIO - Output disabled                   */
24004   GPIO_CFGB_GPIO10OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD10FNCSEL = GPIO - Output is push-pull          */
24005   GPIO_CFGB_GPIO10OUTCFG_OD            = 2,     /*!< OD : Applies when PAD10FNCSEL = GPIO - Output is open drain               */
24006   GPIO_CFGB_GPIO10OUTCFG_TS            = 3,     /*!< TS : Applies when PAD10FNCSEL = GPIO - Output is tri-state                */
24007 } GPIO_CFGB_GPIO10OUTCFG_Enum;
24008 
24009 /* =============================================  GPIO CFGB GPIO10INCFG [8..8]  ============================================== */
24010 typedef enum {                                  /*!< GPIO_CFGB_GPIO10INCFG                                                     */
24011   GPIO_CFGB_GPIO10INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24012   GPIO_CFGB_GPIO10INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24013 } GPIO_CFGB_GPIO10INCFG_Enum;
24014 
24015 /* ==============================================  GPIO CFGB GPIO9INTD [7..7]  =============================================== */
24016 typedef enum {                                  /*!< GPIO_CFGB_GPIO9INTD                                                       */
24017   GPIO_CFGB_GPIO9INTD_nCELOW           = 0,     /*!< nCELOW : Applies when PAD9FNCSEL = NCE9 - nCE polarity active
24018                                                      low                                                                       */
24019   GPIO_CFGB_GPIO9INTD_nCEHIGH          = 1,     /*!< nCEHIGH : Applies when PAD9FNCSEL = NCE9 - nCE polarity active
24020                                                      high                                                                      */
24021 } GPIO_CFGB_GPIO9INTD_Enum;
24022 
24023 /* =============================================  GPIO CFGB GPIO9OUTCFG [5..6]  ============================================== */
24024 typedef enum {                                  /*!< GPIO_CFGB_GPIO9OUTCFG                                                     */
24025   GPIO_CFGB_GPIO9OUTCFG_DIS            = 0,     /*!< DIS : Applies when PAD9FNCSEL = GPIO - Output disabled                    */
24026   GPIO_CFGB_GPIO9OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : Applies when PAD9FNCSEL = GPIO - Output is push-pull           */
24027   GPIO_CFGB_GPIO9OUTCFG_OD             = 2,     /*!< OD : Applies when PAD9FNCSEL = GPIO - Output is open drain                */
24028   GPIO_CFGB_GPIO9OUTCFG_TS             = 3,     /*!< TS : Applies when PAD9FNCSEL = GPIO - Output is tri-state                 */
24029 } GPIO_CFGB_GPIO9OUTCFG_Enum;
24030 
24031 /* ==============================================  GPIO CFGB GPIO9INCFG [4..4]  ============================================== */
24032 typedef enum {                                  /*!< GPIO_CFGB_GPIO9INCFG                                                      */
24033   GPIO_CFGB_GPIO9INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
24034   GPIO_CFGB_GPIO9INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24035 } GPIO_CFGB_GPIO9INCFG_Enum;
24036 
24037 /* ==============================================  GPIO CFGB GPIO8INTD [3..3]  =============================================== */
24038 typedef enum {                                  /*!< GPIO_CFGB_GPIO8INTD                                                       */
24039   GPIO_CFGB_GPIO8INTD_nCELOW           = 0,     /*!< nCELOW : Applies when PAD8FNCSEL = NCE8 - nCE polarity active
24040                                                      low                                                                       */
24041   GPIO_CFGB_GPIO8INTD_nCEHIGH          = 1,     /*!< nCEHIGH : Applies when PAD8FNCSEL = NCE8 - nCE polarity active
24042                                                      high                                                                      */
24043 } GPIO_CFGB_GPIO8INTD_Enum;
24044 
24045 /* =============================================  GPIO CFGB GPIO8OUTCFG [1..2]  ============================================== */
24046 typedef enum {                                  /*!< GPIO_CFGB_GPIO8OUTCFG                                                     */
24047   GPIO_CFGB_GPIO8OUTCFG_DIS            = 0,     /*!< DIS : Applies when PAD8FNCSEL = GPIO - Output disabled                    */
24048   GPIO_CFGB_GPIO8OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : Applies when PAD8FNCSEL = GPIO - Output is push-pull           */
24049   GPIO_CFGB_GPIO8OUTCFG_OD             = 2,     /*!< OD : Applies when PAD8FNCSEL = GPIO - Output is open drain                */
24050   GPIO_CFGB_GPIO8OUTCFG_TS             = 3,     /*!< TS : Applies when PAD8FNCSEL = GPIO - Output is tri-state                 */
24051 } GPIO_CFGB_GPIO8OUTCFG_Enum;
24052 
24053 /* ==============================================  GPIO CFGB GPIO8INCFG [0..0]  ============================================== */
24054 typedef enum {                                  /*!< GPIO_CFGB_GPIO8INCFG                                                      */
24055   GPIO_CFGB_GPIO8INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
24056   GPIO_CFGB_GPIO8INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24057 } GPIO_CFGB_GPIO8INCFG_Enum;
24058 
24059 /* =========================================================  CFGC  ========================================================== */
24060 /* =============================================  GPIO CFGC GPIO23INTD [31..31]  ============================================= */
24061 typedef enum {                                  /*!< GPIO_CFGC_GPIO23INTD                                                      */
24062   GPIO_CFGC_GPIO23INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD23FNCSEL = NCE23 - nCE polarity active
24063                                                      low                                                                       */
24064   GPIO_CFGC_GPIO23INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD23FNCSEL = NCE23 - nCE polarity active
24065                                                      high                                                                      */
24066 } GPIO_CFGC_GPIO23INTD_Enum;
24067 
24068 /* ============================================  GPIO CFGC GPIO23OUTCFG [29..30]  ============================================ */
24069 typedef enum {                                  /*!< GPIO_CFGC_GPIO23OUTCFG                                                    */
24070   GPIO_CFGC_GPIO23OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD23FNCSEL = GPIO - Output disabled                   */
24071   GPIO_CFGC_GPIO23OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD23FNCSEL = GPIO - Output is push-pull          */
24072   GPIO_CFGC_GPIO23OUTCFG_OD            = 2,     /*!< OD : Applies when PAD23FNCSEL = GPIO - Output is open drain               */
24073   GPIO_CFGC_GPIO23OUTCFG_TS            = 3,     /*!< TS : Applies when PAD23FNCSEL = GPIO - Output is tri-state                */
24074 } GPIO_CFGC_GPIO23OUTCFG_Enum;
24075 
24076 /* ============================================  GPIO CFGC GPIO23INCFG [28..28]  ============================================= */
24077 typedef enum {                                  /*!< GPIO_CFGC_GPIO23INCFG                                                     */
24078   GPIO_CFGC_GPIO23INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24079   GPIO_CFGC_GPIO23INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24080 } GPIO_CFGC_GPIO23INCFG_Enum;
24081 
24082 /* =============================================  GPIO CFGC GPIO22INTD [27..27]  ============================================= */
24083 typedef enum {                                  /*!< GPIO_CFGC_GPIO22INTD                                                      */
24084   GPIO_CFGC_GPIO22INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD22FNCSEL = NCE22 - nCE polarity active
24085                                                      low                                                                       */
24086   GPIO_CFGC_GPIO22INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD22FNCSEL = NCE22 - nCE polarity active
24087                                                      high                                                                      */
24088 } GPIO_CFGC_GPIO22INTD_Enum;
24089 
24090 /* ============================================  GPIO CFGC GPIO22OUTCFG [25..26]  ============================================ */
24091 typedef enum {                                  /*!< GPIO_CFGC_GPIO22OUTCFG                                                    */
24092   GPIO_CFGC_GPIO22OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD22FNCSEL = GPIO - Output disabled                   */
24093   GPIO_CFGC_GPIO22OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD22FNCSEL = GPIO - Output is push-pull          */
24094   GPIO_CFGC_GPIO22OUTCFG_OD            = 2,     /*!< OD : Applies when PAD22FNCSEL = GPIO - Output is open drain               */
24095   GPIO_CFGC_GPIO22OUTCFG_TS            = 3,     /*!< TS : Applies when PAD22FNCSEL = GPIO - Output is tri-state                */
24096 } GPIO_CFGC_GPIO22OUTCFG_Enum;
24097 
24098 /* ============================================  GPIO CFGC GPIO22INCFG [24..24]  ============================================= */
24099 typedef enum {                                  /*!< GPIO_CFGC_GPIO22INCFG                                                     */
24100   GPIO_CFGC_GPIO22INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24101   GPIO_CFGC_GPIO22INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24102 } GPIO_CFGC_GPIO22INCFG_Enum;
24103 
24104 /* =============================================  GPIO CFGC GPIO21INTD [23..23]  ============================================= */
24105 typedef enum {                                  /*!< GPIO_CFGC_GPIO21INTD                                                      */
24106   GPIO_CFGC_GPIO21INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD21FNCSEL = NCE21 - nCE polarity active
24107                                                      low                                                                       */
24108   GPIO_CFGC_GPIO21INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD21FNCSEL = NCE21 - nCE polarity active
24109                                                      high                                                                      */
24110 } GPIO_CFGC_GPIO21INTD_Enum;
24111 
24112 /* ============================================  GPIO CFGC GPIO21OUTCFG [21..22]  ============================================ */
24113 typedef enum {                                  /*!< GPIO_CFGC_GPIO21OUTCFG                                                    */
24114   GPIO_CFGC_GPIO21OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD21FNCSEL = GPIO - Output disabled                   */
24115   GPIO_CFGC_GPIO21OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD21FNCSEL = GPIO - Output is push-pull          */
24116   GPIO_CFGC_GPIO21OUTCFG_OD            = 2,     /*!< OD : Applies when PAD21FNCSEL = GPIO - Output is open drain               */
24117   GPIO_CFGC_GPIO21OUTCFG_TS            = 3,     /*!< TS : Applies when PAD21FNCSEL = GPIO - Output is tri-state                */
24118 } GPIO_CFGC_GPIO21OUTCFG_Enum;
24119 
24120 /* ============================================  GPIO CFGC GPIO21INCFG [20..20]  ============================================= */
24121 typedef enum {                                  /*!< GPIO_CFGC_GPIO21INCFG                                                     */
24122   GPIO_CFGC_GPIO21INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24123   GPIO_CFGC_GPIO21INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24124 } GPIO_CFGC_GPIO21INCFG_Enum;
24125 
24126 /* =============================================  GPIO CFGC GPIO20INTD [19..19]  ============================================= */
24127 typedef enum {                                  /*!< GPIO_CFGC_GPIO20INTD                                                      */
24128   GPIO_CFGC_GPIO20INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD20FNCSEL = NCE20 - nCE polarity active
24129                                                      low                                                                       */
24130   GPIO_CFGC_GPIO20INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD20FNCSEL = NCE20 - nCE polarity active
24131                                                      high                                                                      */
24132 } GPIO_CFGC_GPIO20INTD_Enum;
24133 
24134 /* ============================================  GPIO CFGC GPIO20OUTCFG [17..18]  ============================================ */
24135 typedef enum {                                  /*!< GPIO_CFGC_GPIO20OUTCFG                                                    */
24136   GPIO_CFGC_GPIO20OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD20FNCSEL = GPIO - Output disabled                   */
24137   GPIO_CFGC_GPIO20OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD20FNCSEL = GPIO - Output is push-pull          */
24138   GPIO_CFGC_GPIO20OUTCFG_OD            = 2,     /*!< OD : Applies when PAD20FNCSEL = GPIO - Output is open drain               */
24139   GPIO_CFGC_GPIO20OUTCFG_TS            = 3,     /*!< TS : Applies when PAD20FNCSEL = GPIO - Output is tri-state                */
24140 } GPIO_CFGC_GPIO20OUTCFG_Enum;
24141 
24142 /* ============================================  GPIO CFGC GPIO20INCFG [16..16]  ============================================= */
24143 typedef enum {                                  /*!< GPIO_CFGC_GPIO20INCFG                                                     */
24144   GPIO_CFGC_GPIO20INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24145   GPIO_CFGC_GPIO20INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24146 } GPIO_CFGC_GPIO20INCFG_Enum;
24147 
24148 /* =============================================  GPIO CFGC GPIO19INTD [15..15]  ============================================= */
24149 typedef enum {                                  /*!< GPIO_CFGC_GPIO19INTD                                                      */
24150   GPIO_CFGC_GPIO19INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD19FNCSEL = NCE19 - nCE polarity active
24151                                                      low                                                                       */
24152   GPIO_CFGC_GPIO19INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD19FNCSEL = NCE19 - nCE polarity active
24153                                                      high                                                                      */
24154 } GPIO_CFGC_GPIO19INTD_Enum;
24155 
24156 /* ============================================  GPIO CFGC GPIO19OUTCFG [13..14]  ============================================ */
24157 typedef enum {                                  /*!< GPIO_CFGC_GPIO19OUTCFG                                                    */
24158   GPIO_CFGC_GPIO19OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD19FNCSEL = GPIO - Output disabled                   */
24159   GPIO_CFGC_GPIO19OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD19FNCSEL = GPIO - Output is push-pull          */
24160   GPIO_CFGC_GPIO19OUTCFG_OD            = 2,     /*!< OD : Applies when PAD19FNCSEL = GPIO - Output is open drain               */
24161   GPIO_CFGC_GPIO19OUTCFG_TS            = 3,     /*!< TS : Applies when PAD19FNCSEL = GPIO - Output is tri-state                */
24162 } GPIO_CFGC_GPIO19OUTCFG_Enum;
24163 
24164 /* ============================================  GPIO CFGC GPIO19INCFG [12..12]  ============================================= */
24165 typedef enum {                                  /*!< GPIO_CFGC_GPIO19INCFG                                                     */
24166   GPIO_CFGC_GPIO19INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24167   GPIO_CFGC_GPIO19INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24168 } GPIO_CFGC_GPIO19INCFG_Enum;
24169 
24170 /* =============================================  GPIO CFGC GPIO18INTD [11..11]  ============================================= */
24171 typedef enum {                                  /*!< GPIO_CFGC_GPIO18INTD                                                      */
24172   GPIO_CFGC_GPIO18INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD18FNCSEL = NCE18 - nCE polarity active
24173                                                      low                                                                       */
24174   GPIO_CFGC_GPIO18INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD18FNCSEL = NCE18 - nCE polarity active
24175                                                      high                                                                      */
24176 } GPIO_CFGC_GPIO18INTD_Enum;
24177 
24178 /* ============================================  GPIO CFGC GPIO18OUTCFG [9..10]  ============================================= */
24179 typedef enum {                                  /*!< GPIO_CFGC_GPIO18OUTCFG                                                    */
24180   GPIO_CFGC_GPIO18OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD18FNCSEL = GPIO - Output disabled                   */
24181   GPIO_CFGC_GPIO18OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD18FNCSEL = GPIO - Output is push-pull          */
24182   GPIO_CFGC_GPIO18OUTCFG_OD            = 2,     /*!< OD : Applies when PAD18FNCSEL = GPIO - Output is open drain               */
24183   GPIO_CFGC_GPIO18OUTCFG_TS            = 3,     /*!< TS : Applies when PAD18FNCSEL = GPIO - Output is tri-state                */
24184 } GPIO_CFGC_GPIO18OUTCFG_Enum;
24185 
24186 /* =============================================  GPIO CFGC GPIO18INCFG [8..8]  ============================================== */
24187 typedef enum {                                  /*!< GPIO_CFGC_GPIO18INCFG                                                     */
24188   GPIO_CFGC_GPIO18INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24189   GPIO_CFGC_GPIO18INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24190 } GPIO_CFGC_GPIO18INCFG_Enum;
24191 
24192 /* ==============================================  GPIO CFGC GPIO17INTD [7..7]  ============================================== */
24193 typedef enum {                                  /*!< GPIO_CFGC_GPIO17INTD                                                      */
24194   GPIO_CFGC_GPIO17INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD17FNCSEL = NCE17 - nCE polarity active
24195                                                      low                                                                       */
24196   GPIO_CFGC_GPIO17INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD17FNCSEL = NCE17 - nCE polarity active
24197                                                      high                                                                      */
24198 } GPIO_CFGC_GPIO17INTD_Enum;
24199 
24200 /* =============================================  GPIO CFGC GPIO17OUTCFG [5..6]  ============================================= */
24201 typedef enum {                                  /*!< GPIO_CFGC_GPIO17OUTCFG                                                    */
24202   GPIO_CFGC_GPIO17OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD17FNCSEL = GPIO - Output disabled                   */
24203   GPIO_CFGC_GPIO17OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD17FNCSEL = GPIO - Output is push-pull          */
24204   GPIO_CFGC_GPIO17OUTCFG_OD            = 2,     /*!< OD : Applies when PAD17FNCSEL = GPIO - Output is open drain               */
24205   GPIO_CFGC_GPIO17OUTCFG_TS            = 3,     /*!< TS : Applies when PAD17FNCSEL = GPIO - Output is tri-state                */
24206 } GPIO_CFGC_GPIO17OUTCFG_Enum;
24207 
24208 /* =============================================  GPIO CFGC GPIO17INCFG [4..4]  ============================================== */
24209 typedef enum {                                  /*!< GPIO_CFGC_GPIO17INCFG                                                     */
24210   GPIO_CFGC_GPIO17INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24211   GPIO_CFGC_GPIO17INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24212 } GPIO_CFGC_GPIO17INCFG_Enum;
24213 
24214 /* ==============================================  GPIO CFGC GPIO16INTD [3..3]  ============================================== */
24215 typedef enum {                                  /*!< GPIO_CFGC_GPIO16INTD                                                      */
24216   GPIO_CFGC_GPIO16INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD16FNCSEL = NCE16 - nCE polarity active
24217                                                      low                                                                       */
24218   GPIO_CFGC_GPIO16INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD16FNCSEL = NCE16 - nCE polarity active
24219                                                      high                                                                      */
24220 } GPIO_CFGC_GPIO16INTD_Enum;
24221 
24222 /* =============================================  GPIO CFGC GPIO16OUTCFG [1..2]  ============================================= */
24223 typedef enum {                                  /*!< GPIO_CFGC_GPIO16OUTCFG                                                    */
24224   GPIO_CFGC_GPIO16OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD16FNCSEL = GPIO - Output disabled                   */
24225   GPIO_CFGC_GPIO16OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD16FNCSEL = GPIO - Output is push-pull          */
24226   GPIO_CFGC_GPIO16OUTCFG_OD            = 2,     /*!< OD : Applies when PAD16FNCSEL = GPIO - Output is open drain               */
24227   GPIO_CFGC_GPIO16OUTCFG_TS            = 3,     /*!< TS : Applies when PAD16FNCSEL = GPIO - Output is tri-state                */
24228 } GPIO_CFGC_GPIO16OUTCFG_Enum;
24229 
24230 /* =============================================  GPIO CFGC GPIO16INCFG [0..0]  ============================================== */
24231 typedef enum {                                  /*!< GPIO_CFGC_GPIO16INCFG                                                     */
24232   GPIO_CFGC_GPIO16INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24233   GPIO_CFGC_GPIO16INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24234 } GPIO_CFGC_GPIO16INCFG_Enum;
24235 
24236 /* =========================================================  CFGD  ========================================================== */
24237 /* =============================================  GPIO CFGD GPIO31INTD [31..31]  ============================================= */
24238 typedef enum {                                  /*!< GPIO_CFGD_GPIO31INTD                                                      */
24239   GPIO_CFGD_GPIO31INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD31FNCSEL = NCE31 - nCE polarity active
24240                                                      low                                                                       */
24241   GPIO_CFGD_GPIO31INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD31FNCSEL = NCE31 - nCE polarity active
24242                                                      high                                                                      */
24243 } GPIO_CFGD_GPIO31INTD_Enum;
24244 
24245 /* ============================================  GPIO CFGD GPIO31OUTCFG [29..30]  ============================================ */
24246 typedef enum {                                  /*!< GPIO_CFGD_GPIO31OUTCFG                                                    */
24247   GPIO_CFGD_GPIO31OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD31FNCSEL = GPIO - Output disabled                   */
24248   GPIO_CFGD_GPIO31OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD31FNCSEL = GPIO - Output is push-pull          */
24249   GPIO_CFGD_GPIO31OUTCFG_OD            = 2,     /*!< OD : Applies when PAD31FNCSEL = GPIO - Output is open drain               */
24250   GPIO_CFGD_GPIO31OUTCFG_TS            = 3,     /*!< TS : Applies when PAD31FNCSEL = GPIO - Output is tri-state                */
24251 } GPIO_CFGD_GPIO31OUTCFG_Enum;
24252 
24253 /* ============================================  GPIO CFGD GPIO31INCFG [28..28]  ============================================= */
24254 typedef enum {                                  /*!< GPIO_CFGD_GPIO31INCFG                                                     */
24255   GPIO_CFGD_GPIO31INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24256   GPIO_CFGD_GPIO31INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24257 } GPIO_CFGD_GPIO31INCFG_Enum;
24258 
24259 /* =============================================  GPIO CFGD GPIO30INTD [27..27]  ============================================= */
24260 typedef enum {                                  /*!< GPIO_CFGD_GPIO30INTD                                                      */
24261   GPIO_CFGD_GPIO30INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD30FNCSEL = NCE30 - nCE polarity active
24262                                                      low                                                                       */
24263   GPIO_CFGD_GPIO30INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD30FNCSEL = NCE30 - nCE polarity active
24264                                                      high                                                                      */
24265 } GPIO_CFGD_GPIO30INTD_Enum;
24266 
24267 /* ============================================  GPIO CFGD GPIO30OUTCFG [25..26]  ============================================ */
24268 typedef enum {                                  /*!< GPIO_CFGD_GPIO30OUTCFG                                                    */
24269   GPIO_CFGD_GPIO30OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD30FNCSEL = GPIO - Output disabled                   */
24270   GPIO_CFGD_GPIO30OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD30FNCSEL = GPIO - Output is push-pull          */
24271   GPIO_CFGD_GPIO30OUTCFG_OD            = 2,     /*!< OD : Applies when PAD30FNCSEL = GPIO - Output is open drain               */
24272   GPIO_CFGD_GPIO30OUTCFG_TS            = 3,     /*!< TS : Applies when PAD30FNCSEL = GPIO - Output is tri-state                */
24273 } GPIO_CFGD_GPIO30OUTCFG_Enum;
24274 
24275 /* ============================================  GPIO CFGD GPIO30INCFG [24..24]  ============================================= */
24276 typedef enum {                                  /*!< GPIO_CFGD_GPIO30INCFG                                                     */
24277   GPIO_CFGD_GPIO30INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24278   GPIO_CFGD_GPIO30INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24279 } GPIO_CFGD_GPIO30INCFG_Enum;
24280 
24281 /* =============================================  GPIO CFGD GPIO29INTD [23..23]  ============================================= */
24282 typedef enum {                                  /*!< GPIO_CFGD_GPIO29INTD                                                      */
24283   GPIO_CFGD_GPIO29INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD29FNCSEL = NCE29 - nCE polarity active
24284                                                      low                                                                       */
24285   GPIO_CFGD_GPIO29INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD29FNCSEL = NCE29 - nCE polarity active
24286                                                      high                                                                      */
24287 } GPIO_CFGD_GPIO29INTD_Enum;
24288 
24289 /* ============================================  GPIO CFGD GPIO29OUTCFG [21..22]  ============================================ */
24290 typedef enum {                                  /*!< GPIO_CFGD_GPIO29OUTCFG                                                    */
24291   GPIO_CFGD_GPIO29OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD29FNCSEL = GPIO - Output disabled                   */
24292   GPIO_CFGD_GPIO29OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD29FNCSEL = GPIO - Output is push-pull          */
24293   GPIO_CFGD_GPIO29OUTCFG_OD            = 2,     /*!< OD : Applies when PAD29FNCSEL = GPIO - Output is open drain               */
24294   GPIO_CFGD_GPIO29OUTCFG_TS            = 3,     /*!< TS : Applies when PAD29FNCSEL = GPIO - Output is tri-state                */
24295 } GPIO_CFGD_GPIO29OUTCFG_Enum;
24296 
24297 /* ============================================  GPIO CFGD GPIO29INCFG [20..20]  ============================================= */
24298 typedef enum {                                  /*!< GPIO_CFGD_GPIO29INCFG                                                     */
24299   GPIO_CFGD_GPIO29INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24300   GPIO_CFGD_GPIO29INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24301 } GPIO_CFGD_GPIO29INCFG_Enum;
24302 
24303 /* =============================================  GPIO CFGD GPIO28INTD [19..19]  ============================================= */
24304 typedef enum {                                  /*!< GPIO_CFGD_GPIO28INTD                                                      */
24305   GPIO_CFGD_GPIO28INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD28FNCSEL = NCE28 - nCE polarity active
24306                                                      low                                                                       */
24307   GPIO_CFGD_GPIO28INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD28FNCSEL = NCE28 - nCE polarity active
24308                                                      high                                                                      */
24309 } GPIO_CFGD_GPIO28INTD_Enum;
24310 
24311 /* ============================================  GPIO CFGD GPIO28OUTCFG [17..18]  ============================================ */
24312 typedef enum {                                  /*!< GPIO_CFGD_GPIO28OUTCFG                                                    */
24313   GPIO_CFGD_GPIO28OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD28FNCSEL = GPIO - Output disabled                   */
24314   GPIO_CFGD_GPIO28OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD28FNCSEL = GPIO - Output is push-pull          */
24315   GPIO_CFGD_GPIO28OUTCFG_OD            = 2,     /*!< OD : Applies when PAD28FNCSEL = GPIO - Output is open drain               */
24316   GPIO_CFGD_GPIO28OUTCFG_TS            = 3,     /*!< TS : Applies when PAD28FNCSEL = GPIO - Output is tri-state                */
24317 } GPIO_CFGD_GPIO28OUTCFG_Enum;
24318 
24319 /* ============================================  GPIO CFGD GPIO28INCFG [16..16]  ============================================= */
24320 typedef enum {                                  /*!< GPIO_CFGD_GPIO28INCFG                                                     */
24321   GPIO_CFGD_GPIO28INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24322   GPIO_CFGD_GPIO28INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24323 } GPIO_CFGD_GPIO28INCFG_Enum;
24324 
24325 /* =============================================  GPIO CFGD GPIO27INTD [15..15]  ============================================= */
24326 typedef enum {                                  /*!< GPIO_CFGD_GPIO27INTD                                                      */
24327   GPIO_CFGD_GPIO27INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD27FNCSEL = NCE27 - nCE polarity active
24328                                                      low                                                                       */
24329   GPIO_CFGD_GPIO27INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD27FNCSEL = NCE27 - nCE polarity active
24330                                                      high                                                                      */
24331 } GPIO_CFGD_GPIO27INTD_Enum;
24332 
24333 /* ============================================  GPIO CFGD GPIO27OUTCFG [13..14]  ============================================ */
24334 typedef enum {                                  /*!< GPIO_CFGD_GPIO27OUTCFG                                                    */
24335   GPIO_CFGD_GPIO27OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD27FNCSEL = GPIO - Output disabled                   */
24336   GPIO_CFGD_GPIO27OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD27FNCSEL = GPIO - Output is push-pull          */
24337   GPIO_CFGD_GPIO27OUTCFG_OD            = 2,     /*!< OD : Applies when PAD27FNCSEL = GPIO - Output is open drain               */
24338   GPIO_CFGD_GPIO27OUTCFG_TS            = 3,     /*!< TS : Applies when PAD27FNCSEL = GPIO - Output is tri-state                */
24339 } GPIO_CFGD_GPIO27OUTCFG_Enum;
24340 
24341 /* ============================================  GPIO CFGD GPIO27INCFG [12..12]  ============================================= */
24342 typedef enum {                                  /*!< GPIO_CFGD_GPIO27INCFG                                                     */
24343   GPIO_CFGD_GPIO27INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24344   GPIO_CFGD_GPIO27INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24345 } GPIO_CFGD_GPIO27INCFG_Enum;
24346 
24347 /* =============================================  GPIO CFGD GPIO26INTD [11..11]  ============================================= */
24348 typedef enum {                                  /*!< GPIO_CFGD_GPIO26INTD                                                      */
24349   GPIO_CFGD_GPIO26INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD26FNCSEL = NCE26 - nCE polarity active
24350                                                      low                                                                       */
24351   GPIO_CFGD_GPIO26INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD26FNCSEL = NCE26 - nCE polarity active
24352                                                      high                                                                      */
24353 } GPIO_CFGD_GPIO26INTD_Enum;
24354 
24355 /* ============================================  GPIO CFGD GPIO26OUTCFG [9..10]  ============================================= */
24356 typedef enum {                                  /*!< GPIO_CFGD_GPIO26OUTCFG                                                    */
24357   GPIO_CFGD_GPIO26OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD26FNCSEL = GPIO - Output disabled                   */
24358   GPIO_CFGD_GPIO26OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD26FNCSEL = GPIO - Output is push-pull          */
24359   GPIO_CFGD_GPIO26OUTCFG_OD            = 2,     /*!< OD : Applies when PAD26FNCSEL = GPIO - Output is open drain               */
24360   GPIO_CFGD_GPIO26OUTCFG_TS            = 3,     /*!< TS : Applies when PAD26FNCSEL = GPIO - Output is tri-state                */
24361 } GPIO_CFGD_GPIO26OUTCFG_Enum;
24362 
24363 /* =============================================  GPIO CFGD GPIO26INCFG [8..8]  ============================================== */
24364 typedef enum {                                  /*!< GPIO_CFGD_GPIO26INCFG                                                     */
24365   GPIO_CFGD_GPIO26INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24366   GPIO_CFGD_GPIO26INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24367 } GPIO_CFGD_GPIO26INCFG_Enum;
24368 
24369 /* ==============================================  GPIO CFGD GPIO25INTD [7..7]  ============================================== */
24370 typedef enum {                                  /*!< GPIO_CFGD_GPIO25INTD                                                      */
24371   GPIO_CFGD_GPIO25INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD25FNCSEL = NCE25 - nCE polarity active
24372                                                      low                                                                       */
24373   GPIO_CFGD_GPIO25INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD25FNCSEL = NCE25 - nCE polarity active
24374                                                      high                                                                      */
24375 } GPIO_CFGD_GPIO25INTD_Enum;
24376 
24377 /* =============================================  GPIO CFGD GPIO25OUTCFG [5..6]  ============================================= */
24378 typedef enum {                                  /*!< GPIO_CFGD_GPIO25OUTCFG                                                    */
24379   GPIO_CFGD_GPIO25OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD25FNCSEL = GPIO - Output disabled                   */
24380   GPIO_CFGD_GPIO25OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD25FNCSEL = GPIO - Output is push-pull          */
24381   GPIO_CFGD_GPIO25OUTCFG_OD            = 2,     /*!< OD : Applies when PAD25FNCSEL = GPIO - Output is open drain               */
24382   GPIO_CFGD_GPIO25OUTCFG_TS            = 3,     /*!< TS : Applies when PAD25FNCSEL = GPIO - Output is tri-state                */
24383 } GPIO_CFGD_GPIO25OUTCFG_Enum;
24384 
24385 /* =============================================  GPIO CFGD GPIO25INCFG [4..4]  ============================================== */
24386 typedef enum {                                  /*!< GPIO_CFGD_GPIO25INCFG                                                     */
24387   GPIO_CFGD_GPIO25INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24388   GPIO_CFGD_GPIO25INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24389 } GPIO_CFGD_GPIO25INCFG_Enum;
24390 
24391 /* ==============================================  GPIO CFGD GPIO24INTD [3..3]  ============================================== */
24392 typedef enum {                                  /*!< GPIO_CFGD_GPIO24INTD                                                      */
24393   GPIO_CFGD_GPIO24INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD24FNCSEL = NCE24 - nCE polarity active
24394                                                      low                                                                       */
24395   GPIO_CFGD_GPIO24INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD24FNCSEL = NCE24 - nCE polarity active
24396                                                      high                                                                      */
24397 } GPIO_CFGD_GPIO24INTD_Enum;
24398 
24399 /* =============================================  GPIO CFGD GPIO24OUTCFG [1..2]  ============================================= */
24400 typedef enum {                                  /*!< GPIO_CFGD_GPIO24OUTCFG                                                    */
24401   GPIO_CFGD_GPIO24OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD24FNCSEL = GPIO - Output disabled                   */
24402   GPIO_CFGD_GPIO24OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD24FNCSEL = GPIO - Output is push-pull          */
24403   GPIO_CFGD_GPIO24OUTCFG_OD            = 2,     /*!< OD : Applies when PAD24FNCSEL = GPIO - Output is open drain               */
24404   GPIO_CFGD_GPIO24OUTCFG_TS            = 3,     /*!< TS : Applies when PAD24FNCSEL = GPIO - Output is tri-state                */
24405 } GPIO_CFGD_GPIO24OUTCFG_Enum;
24406 
24407 /* =============================================  GPIO CFGD GPIO24INCFG [0..0]  ============================================== */
24408 typedef enum {                                  /*!< GPIO_CFGD_GPIO24INCFG                                                     */
24409   GPIO_CFGD_GPIO24INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24410   GPIO_CFGD_GPIO24INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24411 } GPIO_CFGD_GPIO24INCFG_Enum;
24412 
24413 /* =========================================================  CFGE  ========================================================== */
24414 /* =============================================  GPIO CFGE GPIO39INTD [31..31]  ============================================= */
24415 typedef enum {                                  /*!< GPIO_CFGE_GPIO39INTD                                                      */
24416   GPIO_CFGE_GPIO39INTD_INTDIS          = 0,     /*!< INTDIS : Applies when GPIO39INCFG = 1 - No interrupt on GPIO
24417                                                      transition                                                                */
24418   GPIO_CFGE_GPIO39INTD_INTBOTH         = 1,     /*!< INTBOTH : Applies when GPIO39INCFG = 1 - Interrupt on either
24419                                                      low to high or high to low GPIO transition                                */
24420 } GPIO_CFGE_GPIO39INTD_Enum;
24421 
24422 /* ============================================  GPIO CFGE GPIO39OUTCFG [29..30]  ============================================ */
24423 typedef enum {                                  /*!< GPIO_CFGE_GPIO39OUTCFG                                                    */
24424   GPIO_CFGE_GPIO39OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD39FNCSEL = GPIO - Output disabled                   */
24425   GPIO_CFGE_GPIO39OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD39FNCSEL = GPIO - Output is push-pull          */
24426   GPIO_CFGE_GPIO39OUTCFG_OD            = 2,     /*!< OD : Applies when PAD39FNCSEL = GPIO - Output is open drain               */
24427   GPIO_CFGE_GPIO39OUTCFG_TS            = 3,     /*!< TS : Applies when PAD39FNCSEL = GPIO - Output is tri-state                */
24428 } GPIO_CFGE_GPIO39OUTCFG_Enum;
24429 
24430 /* ============================================  GPIO CFGE GPIO39INCFG [28..28]  ============================================= */
24431 typedef enum {                                  /*!< GPIO_CFGE_GPIO39INCFG                                                     */
24432   GPIO_CFGE_GPIO39INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24433   GPIO_CFGE_GPIO39INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24434 } GPIO_CFGE_GPIO39INCFG_Enum;
24435 
24436 /* =============================================  GPIO CFGE GPIO38INTD [27..27]  ============================================= */
24437 typedef enum {                                  /*!< GPIO_CFGE_GPIO38INTD                                                      */
24438   GPIO_CFGE_GPIO38INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD38FNCSEL = NCE38 - nCE polarity active
24439                                                      low                                                                       */
24440   GPIO_CFGE_GPIO38INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD38FNCSEL = NCE38 - nCE polarity active
24441                                                      high                                                                      */
24442 } GPIO_CFGE_GPIO38INTD_Enum;
24443 
24444 /* ============================================  GPIO CFGE GPIO38OUTCFG [25..26]  ============================================ */
24445 typedef enum {                                  /*!< GPIO_CFGE_GPIO38OUTCFG                                                    */
24446   GPIO_CFGE_GPIO38OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD38FNCSEL = GPIO - Output disabled                   */
24447   GPIO_CFGE_GPIO38OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD38FNCSEL = GPIO - Output is push-pull          */
24448   GPIO_CFGE_GPIO38OUTCFG_OD            = 2,     /*!< OD : Applies when PAD38FNCSEL = GPIO - Output is open drain               */
24449   GPIO_CFGE_GPIO38OUTCFG_TS            = 3,     /*!< TS : Applies when PAD38FNCSEL = GPIO - Output is tri-state                */
24450 } GPIO_CFGE_GPIO38OUTCFG_Enum;
24451 
24452 /* ============================================  GPIO CFGE GPIO38INCFG [24..24]  ============================================= */
24453 typedef enum {                                  /*!< GPIO_CFGE_GPIO38INCFG                                                     */
24454   GPIO_CFGE_GPIO38INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24455   GPIO_CFGE_GPIO38INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24456 } GPIO_CFGE_GPIO38INCFG_Enum;
24457 
24458 /* =============================================  GPIO CFGE GPIO37INTD [23..23]  ============================================= */
24459 typedef enum {                                  /*!< GPIO_CFGE_GPIO37INTD                                                      */
24460   GPIO_CFGE_GPIO37INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD37FNCSEL = NCE37 - nCE polarity active
24461                                                      low                                                                       */
24462   GPIO_CFGE_GPIO37INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD37FNCSEL = NCE37 - nCE polarity active
24463                                                      high                                                                      */
24464 } GPIO_CFGE_GPIO37INTD_Enum;
24465 
24466 /* ============================================  GPIO CFGE GPIO37OUTCFG [21..22]  ============================================ */
24467 typedef enum {                                  /*!< GPIO_CFGE_GPIO37OUTCFG                                                    */
24468   GPIO_CFGE_GPIO37OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD37FNCSEL = GPIO - Output disabled                   */
24469   GPIO_CFGE_GPIO37OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD37FNCSEL = GPIO - Output is push-pull          */
24470   GPIO_CFGE_GPIO37OUTCFG_OD            = 2,     /*!< OD : Applies when PAD37FNCSEL = GPIO - Output is open drain               */
24471   GPIO_CFGE_GPIO37OUTCFG_TS            = 3,     /*!< TS : Applies when PAD37FNCSEL = GPIO - Output is tri-state                */
24472 } GPIO_CFGE_GPIO37OUTCFG_Enum;
24473 
24474 /* ============================================  GPIO CFGE GPIO37INCFG [20..20]  ============================================= */
24475 typedef enum {                                  /*!< GPIO_CFGE_GPIO37INCFG                                                     */
24476   GPIO_CFGE_GPIO37INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24477   GPIO_CFGE_GPIO37INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24478 } GPIO_CFGE_GPIO37INCFG_Enum;
24479 
24480 /* =============================================  GPIO CFGE GPIO36INTD [19..19]  ============================================= */
24481 typedef enum {                                  /*!< GPIO_CFGE_GPIO36INTD                                                      */
24482   GPIO_CFGE_GPIO36INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD36FNCSEL = NCE36 - nCE polarity active
24483                                                      low                                                                       */
24484   GPIO_CFGE_GPIO36INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD36FNCSEL = NCE36 - nCE polarity active
24485                                                      high                                                                      */
24486 } GPIO_CFGE_GPIO36INTD_Enum;
24487 
24488 /* ============================================  GPIO CFGE GPIO36OUTCFG [17..18]  ============================================ */
24489 typedef enum {                                  /*!< GPIO_CFGE_GPIO36OUTCFG                                                    */
24490   GPIO_CFGE_GPIO36OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD36FNCSEL = GPIO - Output disabled                   */
24491   GPIO_CFGE_GPIO36OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD36FNCSEL = GPIO - Output is push-pull          */
24492   GPIO_CFGE_GPIO36OUTCFG_OD            = 2,     /*!< OD : Applies when PAD36FNCSEL = GPIO - Output is open drain               */
24493   GPIO_CFGE_GPIO36OUTCFG_TS            = 3,     /*!< TS : Applies when PAD36FNCSEL = GPIO - Output is tri-state                */
24494 } GPIO_CFGE_GPIO36OUTCFG_Enum;
24495 
24496 /* ============================================  GPIO CFGE GPIO36INCFG [16..16]  ============================================= */
24497 typedef enum {                                  /*!< GPIO_CFGE_GPIO36INCFG                                                     */
24498   GPIO_CFGE_GPIO36INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24499   GPIO_CFGE_GPIO36INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24500 } GPIO_CFGE_GPIO36INCFG_Enum;
24501 
24502 /* =============================================  GPIO CFGE GPIO35INTD [15..15]  ============================================= */
24503 typedef enum {                                  /*!< GPIO_CFGE_GPIO35INTD                                                      */
24504   GPIO_CFGE_GPIO35INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD35FNCSEL = NCE35 - nCE polarity active
24505                                                      low                                                                       */
24506   GPIO_CFGE_GPIO35INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD35FNCSEL = NCE35 - nCE polarity active
24507                                                      high                                                                      */
24508 } GPIO_CFGE_GPIO35INTD_Enum;
24509 
24510 /* ============================================  GPIO CFGE GPIO35OUTCFG [13..14]  ============================================ */
24511 typedef enum {                                  /*!< GPIO_CFGE_GPIO35OUTCFG                                                    */
24512   GPIO_CFGE_GPIO35OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD35FNCSEL = GPIO - Output disabled                   */
24513   GPIO_CFGE_GPIO35OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD35FNCSEL = GPIO - Output is push-pull          */
24514   GPIO_CFGE_GPIO35OUTCFG_OD            = 2,     /*!< OD : Applies when PAD35FNCSEL = GPIO - Output is open drain               */
24515   GPIO_CFGE_GPIO35OUTCFG_TS            = 3,     /*!< TS : Applies when PAD35FNCSEL = GPIO - Output is tri-state                */
24516 } GPIO_CFGE_GPIO35OUTCFG_Enum;
24517 
24518 /* ============================================  GPIO CFGE GPIO35INCFG [12..12]  ============================================= */
24519 typedef enum {                                  /*!< GPIO_CFGE_GPIO35INCFG                                                     */
24520   GPIO_CFGE_GPIO35INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24521   GPIO_CFGE_GPIO35INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24522 } GPIO_CFGE_GPIO35INCFG_Enum;
24523 
24524 /* =============================================  GPIO CFGE GPIO34INTD [11..11]  ============================================= */
24525 typedef enum {                                  /*!< GPIO_CFGE_GPIO34INTD                                                      */
24526   GPIO_CFGE_GPIO34INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD34FNCSEL = NCE34 - nCE polarity active
24527                                                      low                                                                       */
24528   GPIO_CFGE_GPIO34INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD34FNCSEL = NCE34 - nCE polarity active
24529                                                      high                                                                      */
24530 } GPIO_CFGE_GPIO34INTD_Enum;
24531 
24532 /* ============================================  GPIO CFGE GPIO34OUTCFG [9..10]  ============================================= */
24533 typedef enum {                                  /*!< GPIO_CFGE_GPIO34OUTCFG                                                    */
24534   GPIO_CFGE_GPIO34OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD34FNCSEL = GPIO - Output disabled                   */
24535   GPIO_CFGE_GPIO34OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD34FNCSEL = GPIO - Output is push-pull          */
24536   GPIO_CFGE_GPIO34OUTCFG_OD            = 2,     /*!< OD : Applies when PAD34FNCSEL = GPIO - Output is open drain               */
24537   GPIO_CFGE_GPIO34OUTCFG_TS            = 3,     /*!< TS : Applies when PAD34FNCSEL = GPIO - Output is tri-state                */
24538 } GPIO_CFGE_GPIO34OUTCFG_Enum;
24539 
24540 /* =============================================  GPIO CFGE GPIO34INCFG [8..8]  ============================================== */
24541 typedef enum {                                  /*!< GPIO_CFGE_GPIO34INCFG                                                     */
24542   GPIO_CFGE_GPIO34INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24543   GPIO_CFGE_GPIO34INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24544 } GPIO_CFGE_GPIO34INCFG_Enum;
24545 
24546 /* ==============================================  GPIO CFGE GPIO33INTD [7..7]  ============================================== */
24547 typedef enum {                                  /*!< GPIO_CFGE_GPIO33INTD                                                      */
24548   GPIO_CFGE_GPIO33INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD33FNCSEL = NCE33 - nCE polarity active
24549                                                      low                                                                       */
24550   GPIO_CFGE_GPIO33INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD33FNCSEL = NCE33 - nCE polarity active
24551                                                      high                                                                      */
24552 } GPIO_CFGE_GPIO33INTD_Enum;
24553 
24554 /* =============================================  GPIO CFGE GPIO33OUTCFG [5..6]  ============================================= */
24555 typedef enum {                                  /*!< GPIO_CFGE_GPIO33OUTCFG                                                    */
24556   GPIO_CFGE_GPIO33OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD33FNCSEL = GPIO - Output disabled                   */
24557   GPIO_CFGE_GPIO33OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD33FNCSEL = GPIO - Output is push-pull          */
24558   GPIO_CFGE_GPIO33OUTCFG_OD            = 2,     /*!< OD : Applies when PAD33FNCSEL = GPIO - Output is open drain               */
24559   GPIO_CFGE_GPIO33OUTCFG_TS            = 3,     /*!< TS : Applies when PAD33FNCSEL = GPIO - Output is tri-state                */
24560 } GPIO_CFGE_GPIO33OUTCFG_Enum;
24561 
24562 /* =============================================  GPIO CFGE GPIO33INCFG [4..4]  ============================================== */
24563 typedef enum {                                  /*!< GPIO_CFGE_GPIO33INCFG                                                     */
24564   GPIO_CFGE_GPIO33INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24565   GPIO_CFGE_GPIO33INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24566 } GPIO_CFGE_GPIO33INCFG_Enum;
24567 
24568 /* ==============================================  GPIO CFGE GPIO32INTD [3..3]  ============================================== */
24569 typedef enum {                                  /*!< GPIO_CFGE_GPIO32INTD                                                      */
24570   GPIO_CFGE_GPIO32INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD32FNCSEL = NCE32 - nCE polarity active
24571                                                      low                                                                       */
24572   GPIO_CFGE_GPIO32INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD32FNCSEL = NCE32 - nCE polarity active
24573                                                      high                                                                      */
24574 } GPIO_CFGE_GPIO32INTD_Enum;
24575 
24576 /* =============================================  GPIO CFGE GPIO32OUTCFG [1..2]  ============================================= */
24577 typedef enum {                                  /*!< GPIO_CFGE_GPIO32OUTCFG                                                    */
24578   GPIO_CFGE_GPIO32OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD32FNCSEL = GPIO - Output disabled                   */
24579   GPIO_CFGE_GPIO32OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD32FNCSEL = GPIO - Output is push-pull          */
24580   GPIO_CFGE_GPIO32OUTCFG_OD            = 2,     /*!< OD : Applies when PAD32FNCSEL = GPIO - Output is open drain               */
24581   GPIO_CFGE_GPIO32OUTCFG_TS            = 3,     /*!< TS : Applies when PAD32FNCSEL = GPIO - Output is tri-state                */
24582 } GPIO_CFGE_GPIO32OUTCFG_Enum;
24583 
24584 /* =============================================  GPIO CFGE GPIO32INCFG [0..0]  ============================================== */
24585 typedef enum {                                  /*!< GPIO_CFGE_GPIO32INCFG                                                     */
24586   GPIO_CFGE_GPIO32INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24587   GPIO_CFGE_GPIO32INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24588 } GPIO_CFGE_GPIO32INCFG_Enum;
24589 
24590 /* =========================================================  CFGF  ========================================================== */
24591 /* =============================================  GPIO CFGF GPIO47INTD [31..31]  ============================================= */
24592 typedef enum {                                  /*!< GPIO_CFGF_GPIO47INTD                                                      */
24593   GPIO_CFGF_GPIO47INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD47FNCSEL = NCE47 - nCE polarity active
24594                                                      low                                                                       */
24595   GPIO_CFGF_GPIO47INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD47FNCSEL = NCE47 - nCE polarity active
24596                                                      high                                                                      */
24597 } GPIO_CFGF_GPIO47INTD_Enum;
24598 
24599 /* ============================================  GPIO CFGF GPIO47OUTCFG [29..30]  ============================================ */
24600 typedef enum {                                  /*!< GPIO_CFGF_GPIO47OUTCFG                                                    */
24601   GPIO_CFGF_GPIO47OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD47FNCSEL = GPIO - Output disabled                   */
24602   GPIO_CFGF_GPIO47OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD47FNCSEL = GPIO - Output is push-pull          */
24603   GPIO_CFGF_GPIO47OUTCFG_OD            = 2,     /*!< OD : Applies when PAD47FNCSEL = GPIO - Output is open drain               */
24604   GPIO_CFGF_GPIO47OUTCFG_TS            = 3,     /*!< TS : Applies when PAD47FNCSEL = GPIO - Output is tri-state                */
24605 } GPIO_CFGF_GPIO47OUTCFG_Enum;
24606 
24607 /* ============================================  GPIO CFGF GPIO47INCFG [28..28]  ============================================= */
24608 typedef enum {                                  /*!< GPIO_CFGF_GPIO47INCFG                                                     */
24609   GPIO_CFGF_GPIO47INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24610   GPIO_CFGF_GPIO47INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24611 } GPIO_CFGF_GPIO47INCFG_Enum;
24612 
24613 /* =============================================  GPIO CFGF GPIO46INTD [27..27]  ============================================= */
24614 typedef enum {                                  /*!< GPIO_CFGF_GPIO46INTD                                                      */
24615   GPIO_CFGF_GPIO46INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD46FNCSEL = NCE46 - nCE polarity active
24616                                                      low                                                                       */
24617   GPIO_CFGF_GPIO46INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD46FNCSEL = NCE46 - nCE polarity active
24618                                                      high                                                                      */
24619 } GPIO_CFGF_GPIO46INTD_Enum;
24620 
24621 /* ============================================  GPIO CFGF GPIO46OUTCFG [25..26]  ============================================ */
24622 typedef enum {                                  /*!< GPIO_CFGF_GPIO46OUTCFG                                                    */
24623   GPIO_CFGF_GPIO46OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD46FNCSEL = GPIO - Output disabled                   */
24624   GPIO_CFGF_GPIO46OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD46FNCSEL = GPIO - Output is push-pull          */
24625   GPIO_CFGF_GPIO46OUTCFG_OD            = 2,     /*!< OD : Applies when PAD46FNCSEL = GPIO - Output is open drain               */
24626   GPIO_CFGF_GPIO46OUTCFG_TS            = 3,     /*!< TS : Applies when PAD46FNCSEL = GPIO - Output is tri-state                */
24627 } GPIO_CFGF_GPIO46OUTCFG_Enum;
24628 
24629 /* ============================================  GPIO CFGF GPIO46INCFG [24..24]  ============================================= */
24630 typedef enum {                                  /*!< GPIO_CFGF_GPIO46INCFG                                                     */
24631   GPIO_CFGF_GPIO46INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24632   GPIO_CFGF_GPIO46INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24633 } GPIO_CFGF_GPIO46INCFG_Enum;
24634 
24635 /* =============================================  GPIO CFGF GPIO45INTD [23..23]  ============================================= */
24636 typedef enum {                                  /*!< GPIO_CFGF_GPIO45INTD                                                      */
24637   GPIO_CFGF_GPIO45INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD45FNCSEL = NCE45 - nCE polarity active
24638                                                      low                                                                       */
24639   GPIO_CFGF_GPIO45INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD45FNCSEL = NCE45 - nCE polarity active
24640                                                      high                                                                      */
24641 } GPIO_CFGF_GPIO45INTD_Enum;
24642 
24643 /* ============================================  GPIO CFGF GPIO45OUTCFG [21..22]  ============================================ */
24644 typedef enum {                                  /*!< GPIO_CFGF_GPIO45OUTCFG                                                    */
24645   GPIO_CFGF_GPIO45OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD45FNCSEL = GPIO - Output disabled                   */
24646   GPIO_CFGF_GPIO45OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD45FNCSEL = GPIO - Output is push-pull          */
24647   GPIO_CFGF_GPIO45OUTCFG_OD            = 2,     /*!< OD : Applies when PAD45FNCSEL = GPIO - Output is open drain               */
24648   GPIO_CFGF_GPIO45OUTCFG_TS            = 3,     /*!< TS : Applies when PAD45FNCSEL = GPIO - Output is tri-state                */
24649 } GPIO_CFGF_GPIO45OUTCFG_Enum;
24650 
24651 /* ============================================  GPIO CFGF GPIO45INCFG [20..20]  ============================================= */
24652 typedef enum {                                  /*!< GPIO_CFGF_GPIO45INCFG                                                     */
24653   GPIO_CFGF_GPIO45INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24654   GPIO_CFGF_GPIO45INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24655 } GPIO_CFGF_GPIO45INCFG_Enum;
24656 
24657 /* =============================================  GPIO CFGF GPIO44INTD [19..19]  ============================================= */
24658 typedef enum {                                  /*!< GPIO_CFGF_GPIO44INTD                                                      */
24659   GPIO_CFGF_GPIO44INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD44FNCSEL = NCE44 - nCE polarity active
24660                                                      low                                                                       */
24661   GPIO_CFGF_GPIO44INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD44FNCSEL = NCE44 - nCE polarity active
24662                                                      high                                                                      */
24663 } GPIO_CFGF_GPIO44INTD_Enum;
24664 
24665 /* ============================================  GPIO CFGF GPIO44OUTCFG [17..18]  ============================================ */
24666 typedef enum {                                  /*!< GPIO_CFGF_GPIO44OUTCFG                                                    */
24667   GPIO_CFGF_GPIO44OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD44FNCSEL = GPIO - Output disabled                   */
24668   GPIO_CFGF_GPIO44OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD44FNCSEL = GPIO - Output is push-pull          */
24669   GPIO_CFGF_GPIO44OUTCFG_OD            = 2,     /*!< OD : Applies when PAD44FNCSEL = GPIO - Output is open drain               */
24670   GPIO_CFGF_GPIO44OUTCFG_TS            = 3,     /*!< TS : Applies when PAD44FNCSEL = GPIO - Output is tri-state                */
24671 } GPIO_CFGF_GPIO44OUTCFG_Enum;
24672 
24673 /* ============================================  GPIO CFGF GPIO44INCFG [16..16]  ============================================= */
24674 typedef enum {                                  /*!< GPIO_CFGF_GPIO44INCFG                                                     */
24675   GPIO_CFGF_GPIO44INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24676   GPIO_CFGF_GPIO44INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24677 } GPIO_CFGF_GPIO44INCFG_Enum;
24678 
24679 /* =============================================  GPIO CFGF GPIO43INTD [15..15]  ============================================= */
24680 typedef enum {                                  /*!< GPIO_CFGF_GPIO43INTD                                                      */
24681   GPIO_CFGF_GPIO43INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD43FNCSEL = NCE43 - nCE polarity active
24682                                                      low                                                                       */
24683   GPIO_CFGF_GPIO43INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD43FNCSEL = NCE43 - nCE polarity active
24684                                                      high                                                                      */
24685 } GPIO_CFGF_GPIO43INTD_Enum;
24686 
24687 /* ============================================  GPIO CFGF GPIO43OUTCFG [13..14]  ============================================ */
24688 typedef enum {                                  /*!< GPIO_CFGF_GPIO43OUTCFG                                                    */
24689   GPIO_CFGF_GPIO43OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD43FNCSEL = GPIO - Output disabled                   */
24690   GPIO_CFGF_GPIO43OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD43FNCSEL = GPIO - Output is push-pull          */
24691   GPIO_CFGF_GPIO43OUTCFG_OD            = 2,     /*!< OD : Applies when PAD43FNCSEL = GPIO - Output is open drain               */
24692   GPIO_CFGF_GPIO43OUTCFG_TS            = 3,     /*!< TS : Applies when PAD43FNCSEL = GPIO - Output is tri-state                */
24693 } GPIO_CFGF_GPIO43OUTCFG_Enum;
24694 
24695 /* ============================================  GPIO CFGF GPIO43INCFG [12..12]  ============================================= */
24696 typedef enum {                                  /*!< GPIO_CFGF_GPIO43INCFG                                                     */
24697   GPIO_CFGF_GPIO43INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24698   GPIO_CFGF_GPIO43INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24699 } GPIO_CFGF_GPIO43INCFG_Enum;
24700 
24701 /* =============================================  GPIO CFGF GPIO42INTD [11..11]  ============================================= */
24702 typedef enum {                                  /*!< GPIO_CFGF_GPIO42INTD                                                      */
24703   GPIO_CFGF_GPIO42INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD42FNCSEL = NCE42 - nCE polarity active
24704                                                      low                                                                       */
24705   GPIO_CFGF_GPIO42INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD42FNCSEL = NCE42 - nCE polarity active
24706                                                      high                                                                      */
24707 } GPIO_CFGF_GPIO42INTD_Enum;
24708 
24709 /* ============================================  GPIO CFGF GPIO42OUTCFG [9..10]  ============================================= */
24710 typedef enum {                                  /*!< GPIO_CFGF_GPIO42OUTCFG                                                    */
24711   GPIO_CFGF_GPIO42OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD42FNCSEL = GPIO - Output disabled                   */
24712   GPIO_CFGF_GPIO42OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD42FNCSEL = GPIO - Output is push-pull          */
24713   GPIO_CFGF_GPIO42OUTCFG_OD            = 2,     /*!< OD : Applies when PAD42FNCSEL = GPIO - Output is open drain               */
24714   GPIO_CFGF_GPIO42OUTCFG_TS            = 3,     /*!< TS : Applies when PAD42FNCSEL = GPIO - Output is tri-state                */
24715 } GPIO_CFGF_GPIO42OUTCFG_Enum;
24716 
24717 /* =============================================  GPIO CFGF GPIO42INCFG [8..8]  ============================================== */
24718 typedef enum {                                  /*!< GPIO_CFGF_GPIO42INCFG                                                     */
24719   GPIO_CFGF_GPIO42INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24720   GPIO_CFGF_GPIO42INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24721 } GPIO_CFGF_GPIO42INCFG_Enum;
24722 
24723 /* ==============================================  GPIO CFGF GPIO41INTD [7..7]  ============================================== */
24724 typedef enum {                                  /*!< GPIO_CFGF_GPIO41INTD                                                      */
24725   GPIO_CFGF_GPIO41INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD41FNCSEL = NCE41 - nCE polarity active
24726                                                      low                                                                       */
24727   GPIO_CFGF_GPIO41INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD41FNCSEL = NCE41 - nCE polarity active
24728                                                      high                                                                      */
24729 } GPIO_CFGF_GPIO41INTD_Enum;
24730 
24731 /* =============================================  GPIO CFGF GPIO41OUTCFG [5..6]  ============================================= */
24732 typedef enum {                                  /*!< GPIO_CFGF_GPIO41OUTCFG                                                    */
24733   GPIO_CFGF_GPIO41OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD41FNCSEL = GPIO - Output disabled                   */
24734   GPIO_CFGF_GPIO41OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD41FNCSEL = GPIO - Output is push-pull          */
24735   GPIO_CFGF_GPIO41OUTCFG_OD            = 2,     /*!< OD : Applies when PAD41FNCSEL = GPIO - Output is open drain               */
24736   GPIO_CFGF_GPIO41OUTCFG_TS            = 3,     /*!< TS : Applies when PAD41FNCSEL = GPIO - Output is tri-state                */
24737 } GPIO_CFGF_GPIO41OUTCFG_Enum;
24738 
24739 /* =============================================  GPIO CFGF GPIO41INCFG [4..4]  ============================================== */
24740 typedef enum {                                  /*!< GPIO_CFGF_GPIO41INCFG                                                     */
24741   GPIO_CFGF_GPIO41INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24742   GPIO_CFGF_GPIO41INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24743 } GPIO_CFGF_GPIO41INCFG_Enum;
24744 
24745 /* ==============================================  GPIO CFGF GPIO40INTD [3..3]  ============================================== */
24746 typedef enum {                                  /*!< GPIO_CFGF_GPIO40INTD                                                      */
24747   GPIO_CFGF_GPIO40INTD_INTDIS          = 0,     /*!< INTDIS : Applies when GPIO40INCFG = 1 - No interrupt on GPIO
24748                                                      transition                                                                */
24749   GPIO_CFGF_GPIO40INTD_INTBOTH         = 1,     /*!< INTBOTH : Applies when GPIO40INCFG = 1 - Interrupt on either
24750                                                      low to high or high to low GPIO transition                                */
24751 } GPIO_CFGF_GPIO40INTD_Enum;
24752 
24753 /* =============================================  GPIO CFGF GPIO40OUTCFG [1..2]  ============================================= */
24754 typedef enum {                                  /*!< GPIO_CFGF_GPIO40OUTCFG                                                    */
24755   GPIO_CFGF_GPIO40OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD40FNCSEL = GPIO - Output disabled                   */
24756   GPIO_CFGF_GPIO40OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD40FNCSEL = GPIO - Output is push-pull          */
24757   GPIO_CFGF_GPIO40OUTCFG_OD            = 2,     /*!< OD : Applies when PAD40FNCSEL = GPIO - Output is open drain               */
24758   GPIO_CFGF_GPIO40OUTCFG_TS            = 3,     /*!< TS : Applies when PAD40FNCSEL = GPIO - Output is tri-state                */
24759 } GPIO_CFGF_GPIO40OUTCFG_Enum;
24760 
24761 /* =============================================  GPIO CFGF GPIO40INCFG [0..0]  ============================================== */
24762 typedef enum {                                  /*!< GPIO_CFGF_GPIO40INCFG                                                     */
24763   GPIO_CFGF_GPIO40INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24764   GPIO_CFGF_GPIO40INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24765 } GPIO_CFGF_GPIO40INCFG_Enum;
24766 
24767 /* =========================================================  CFGG  ========================================================== */
24768 /* =============================================  GPIO CFGG GPIO55INTD [31..31]  ============================================= */
24769 typedef enum {                                  /*!< GPIO_CFGG_GPIO55INTD                                                      */
24770   GPIO_CFGG_GPIO55INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD55FNCSEL = NCE55 - nCE polarity active
24771                                                      low                                                                       */
24772   GPIO_CFGG_GPIO55INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD55FNCSEL = NCE55 - nCE polarity active
24773                                                      high                                                                      */
24774 } GPIO_CFGG_GPIO55INTD_Enum;
24775 
24776 /* ============================================  GPIO CFGG GPIO55OUTCFG [29..30]  ============================================ */
24777 typedef enum {                                  /*!< GPIO_CFGG_GPIO55OUTCFG                                                    */
24778   GPIO_CFGG_GPIO55OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD55FNCSEL = GPIO - Output disabled                   */
24779   GPIO_CFGG_GPIO55OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD55FNCSEL = GPIO - Output is push-pull          */
24780   GPIO_CFGG_GPIO55OUTCFG_OD            = 2,     /*!< OD : Applies when PAD55FNCSEL = GPIO - Output is open drain               */
24781   GPIO_CFGG_GPIO55OUTCFG_TS            = 3,     /*!< TS : Applies when PAD55FNCSEL = GPIO - Output is tri-state                */
24782 } GPIO_CFGG_GPIO55OUTCFG_Enum;
24783 
24784 /* ============================================  GPIO CFGG GPIO55INCFG [28..28]  ============================================= */
24785 typedef enum {                                  /*!< GPIO_CFGG_GPIO55INCFG                                                     */
24786   GPIO_CFGG_GPIO55INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24787   GPIO_CFGG_GPIO55INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24788 } GPIO_CFGG_GPIO55INCFG_Enum;
24789 
24790 /* =============================================  GPIO CFGG GPIO54INTD [27..27]  ============================================= */
24791 typedef enum {                                  /*!< GPIO_CFGG_GPIO54INTD                                                      */
24792   GPIO_CFGG_GPIO54INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD54FNCSEL = NCE54 - nCE polarity active
24793                                                      low                                                                       */
24794   GPIO_CFGG_GPIO54INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD54FNCSEL = NCE54 - nCE polarity active
24795                                                      high                                                                      */
24796 } GPIO_CFGG_GPIO54INTD_Enum;
24797 
24798 /* ============================================  GPIO CFGG GPIO54OUTCFG [25..26]  ============================================ */
24799 typedef enum {                                  /*!< GPIO_CFGG_GPIO54OUTCFG                                                    */
24800   GPIO_CFGG_GPIO54OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD54FNCSEL = GPIO - Output disabled                   */
24801   GPIO_CFGG_GPIO54OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD54FNCSEL = GPIO - Output is push-pull          */
24802   GPIO_CFGG_GPIO54OUTCFG_OD            = 2,     /*!< OD : Applies when PAD54FNCSEL = GPIO - Output is open drain               */
24803   GPIO_CFGG_GPIO54OUTCFG_TS            = 3,     /*!< TS : Applies when PAD54FNCSEL = GPIO - Output is tri-state                */
24804 } GPIO_CFGG_GPIO54OUTCFG_Enum;
24805 
24806 /* ============================================  GPIO CFGG GPIO54INCFG [24..24]  ============================================= */
24807 typedef enum {                                  /*!< GPIO_CFGG_GPIO54INCFG                                                     */
24808   GPIO_CFGG_GPIO54INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24809   GPIO_CFGG_GPIO54INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24810 } GPIO_CFGG_GPIO54INCFG_Enum;
24811 
24812 /* =============================================  GPIO CFGG GPIO53INTD [23..23]  ============================================= */
24813 typedef enum {                                  /*!< GPIO_CFGG_GPIO53INTD                                                      */
24814   GPIO_CFGG_GPIO53INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD53FNCSEL = NCE53 - nCE polarity active
24815                                                      low                                                                       */
24816   GPIO_CFGG_GPIO53INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD53FNCSEL = NCE53 - nCE polarity active
24817                                                      high                                                                      */
24818 } GPIO_CFGG_GPIO53INTD_Enum;
24819 
24820 /* ============================================  GPIO CFGG GPIO53OUTCFG [21..22]  ============================================ */
24821 typedef enum {                                  /*!< GPIO_CFGG_GPIO53OUTCFG                                                    */
24822   GPIO_CFGG_GPIO53OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD53FNCSEL = GPIO - Output disabled                   */
24823   GPIO_CFGG_GPIO53OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD53FNCSEL = GPIO - Output is push-pull          */
24824   GPIO_CFGG_GPIO53OUTCFG_OD            = 2,     /*!< OD : Applies when PAD53FNCSEL = GPIO - Output is open drain               */
24825   GPIO_CFGG_GPIO53OUTCFG_TS            = 3,     /*!< TS : Applies when PAD53FNCSEL = GPIO - Output is tri-state                */
24826 } GPIO_CFGG_GPIO53OUTCFG_Enum;
24827 
24828 /* ============================================  GPIO CFGG GPIO53INCFG [20..20]  ============================================= */
24829 typedef enum {                                  /*!< GPIO_CFGG_GPIO53INCFG                                                     */
24830   GPIO_CFGG_GPIO53INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24831   GPIO_CFGG_GPIO53INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24832 } GPIO_CFGG_GPIO53INCFG_Enum;
24833 
24834 /* =============================================  GPIO CFGG GPIO52INTD [19..19]  ============================================= */
24835 typedef enum {                                  /*!< GPIO_CFGG_GPIO52INTD                                                      */
24836   GPIO_CFGG_GPIO52INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD52FNCSEL = NCE52 - nCE polarity active
24837                                                      low                                                                       */
24838   GPIO_CFGG_GPIO52INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD52FNCSEL = NCE52 - nCE polarity active
24839                                                      high                                                                      */
24840 } GPIO_CFGG_GPIO52INTD_Enum;
24841 
24842 /* ============================================  GPIO CFGG GPIO52OUTCFG [17..18]  ============================================ */
24843 typedef enum {                                  /*!< GPIO_CFGG_GPIO52OUTCFG                                                    */
24844   GPIO_CFGG_GPIO52OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD52FNCSEL = GPIO - Output disabled                   */
24845   GPIO_CFGG_GPIO52OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD52FNCSEL = GPIO - Output is push-pull          */
24846   GPIO_CFGG_GPIO52OUTCFG_OD            = 2,     /*!< OD : Applies when PAD52FNCSEL = GPIO - Output is open drain               */
24847   GPIO_CFGG_GPIO52OUTCFG_TS            = 3,     /*!< TS : Applies when PAD52FNCSEL = GPIO - Output is tri-state                */
24848 } GPIO_CFGG_GPIO52OUTCFG_Enum;
24849 
24850 /* ============================================  GPIO CFGG GPIO52INCFG [16..16]  ============================================= */
24851 typedef enum {                                  /*!< GPIO_CFGG_GPIO52INCFG                                                     */
24852   GPIO_CFGG_GPIO52INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24853   GPIO_CFGG_GPIO52INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24854 } GPIO_CFGG_GPIO52INCFG_Enum;
24855 
24856 /* =============================================  GPIO CFGG GPIO51INTD [15..15]  ============================================= */
24857 typedef enum {                                  /*!< GPIO_CFGG_GPIO51INTD                                                      */
24858   GPIO_CFGG_GPIO51INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD51FNCSEL = NCE51 - nCE polarity active
24859                                                      low                                                                       */
24860   GPIO_CFGG_GPIO51INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD51FNCSEL = NCE51 - nCE polarity active
24861                                                      high                                                                      */
24862 } GPIO_CFGG_GPIO51INTD_Enum;
24863 
24864 /* ============================================  GPIO CFGG GPIO51OUTCFG [13..14]  ============================================ */
24865 typedef enum {                                  /*!< GPIO_CFGG_GPIO51OUTCFG                                                    */
24866   GPIO_CFGG_GPIO51OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD51FNCSEL = GPIO - Output disabled                   */
24867   GPIO_CFGG_GPIO51OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD51FNCSEL = GPIO - Output is push-pull          */
24868   GPIO_CFGG_GPIO51OUTCFG_OD            = 2,     /*!< OD : Applies when PAD51FNCSEL = GPIO - Output is open drain               */
24869   GPIO_CFGG_GPIO51OUTCFG_TS            = 3,     /*!< TS : Applies when PAD51FNCSEL = GPIO - Output is tri-state                */
24870 } GPIO_CFGG_GPIO51OUTCFG_Enum;
24871 
24872 /* ============================================  GPIO CFGG GPIO51INCFG [12..12]  ============================================= */
24873 typedef enum {                                  /*!< GPIO_CFGG_GPIO51INCFG                                                     */
24874   GPIO_CFGG_GPIO51INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24875   GPIO_CFGG_GPIO51INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24876 } GPIO_CFGG_GPIO51INCFG_Enum;
24877 
24878 /* =============================================  GPIO CFGG GPIO50INTD [11..11]  ============================================= */
24879 typedef enum {                                  /*!< GPIO_CFGG_GPIO50INTD                                                      */
24880   GPIO_CFGG_GPIO50INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD50FNCSEL = NCE50 - nCE polarity active
24881                                                      low                                                                       */
24882   GPIO_CFGG_GPIO50INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD50FNCSEL = NCE50 - nCE polarity active
24883                                                      high                                                                      */
24884 } GPIO_CFGG_GPIO50INTD_Enum;
24885 
24886 /* ============================================  GPIO CFGG GPIO50OUTCFG [9..10]  ============================================= */
24887 typedef enum {                                  /*!< GPIO_CFGG_GPIO50OUTCFG                                                    */
24888   GPIO_CFGG_GPIO50OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD50FNCSEL = GPIO - Output disabled                   */
24889   GPIO_CFGG_GPIO50OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD50FNCSEL = GPIO - Output is push-pull          */
24890   GPIO_CFGG_GPIO50OUTCFG_OD            = 2,     /*!< OD : Applies when PAD50FNCSEL = GPIO - Output is open drain               */
24891   GPIO_CFGG_GPIO50OUTCFG_TS            = 3,     /*!< TS : Applies when PAD50FNCSEL = GPIO - Output is tri-state                */
24892 } GPIO_CFGG_GPIO50OUTCFG_Enum;
24893 
24894 /* =============================================  GPIO CFGG GPIO50INCFG [8..8]  ============================================== */
24895 typedef enum {                                  /*!< GPIO_CFGG_GPIO50INCFG                                                     */
24896   GPIO_CFGG_GPIO50INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24897   GPIO_CFGG_GPIO50INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24898 } GPIO_CFGG_GPIO50INCFG_Enum;
24899 
24900 /* ==============================================  GPIO CFGG GPIO49INTD [7..7]  ============================================== */
24901 typedef enum {                                  /*!< GPIO_CFGG_GPIO49INTD                                                      */
24902   GPIO_CFGG_GPIO49INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD49FNCSEL = NCE49 - nCE polarity active
24903                                                      low                                                                       */
24904   GPIO_CFGG_GPIO49INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD49FNCSEL = NCE49 - nCE polarity active
24905                                                      high                                                                      */
24906 } GPIO_CFGG_GPIO49INTD_Enum;
24907 
24908 /* =============================================  GPIO CFGG GPIO49OUTCFG [5..6]  ============================================= */
24909 typedef enum {                                  /*!< GPIO_CFGG_GPIO49OUTCFG                                                    */
24910   GPIO_CFGG_GPIO49OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD49FNCSEL = GPIO - Output disabled                   */
24911   GPIO_CFGG_GPIO49OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD49FNCSEL = GPIO - Output is push-pull          */
24912   GPIO_CFGG_GPIO49OUTCFG_OD            = 2,     /*!< OD : Applies when PAD49FNCSEL = GPIO - Output is open drain               */
24913   GPIO_CFGG_GPIO49OUTCFG_TS            = 3,     /*!< TS : Applies when PAD49FNCSEL = GPIO - Output is tri-state                */
24914 } GPIO_CFGG_GPIO49OUTCFG_Enum;
24915 
24916 /* =============================================  GPIO CFGG GPIO49INCFG [4..4]  ============================================== */
24917 typedef enum {                                  /*!< GPIO_CFGG_GPIO49INCFG                                                     */
24918   GPIO_CFGG_GPIO49INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24919   GPIO_CFGG_GPIO49INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24920 } GPIO_CFGG_GPIO49INCFG_Enum;
24921 
24922 /* ==============================================  GPIO CFGG GPIO48INTD [3..3]  ============================================== */
24923 typedef enum {                                  /*!< GPIO_CFGG_GPIO48INTD                                                      */
24924   GPIO_CFGG_GPIO48INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD48FNCSEL = NCE48 - nCE polarity active
24925                                                      low                                                                       */
24926   GPIO_CFGG_GPIO48INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD48FNCSEL = NCE48 - nCE polarity active
24927                                                      high                                                                      */
24928 } GPIO_CFGG_GPIO48INTD_Enum;
24929 
24930 /* =============================================  GPIO CFGG GPIO48OUTCFG [1..2]  ============================================= */
24931 typedef enum {                                  /*!< GPIO_CFGG_GPIO48OUTCFG                                                    */
24932   GPIO_CFGG_GPIO48OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD48FNCSEL = GPIO - Output disabled                   */
24933   GPIO_CFGG_GPIO48OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD48FNCSEL = GPIO - Output is push-pull          */
24934   GPIO_CFGG_GPIO48OUTCFG_OD            = 2,     /*!< OD : Applies when PAD48FNCSEL = GPIO - Output is open drain               */
24935   GPIO_CFGG_GPIO48OUTCFG_TS            = 3,     /*!< TS : Applies when PAD48FNCSEL = GPIO - Output is tri-state                */
24936 } GPIO_CFGG_GPIO48OUTCFG_Enum;
24937 
24938 /* =============================================  GPIO CFGG GPIO48INCFG [0..0]  ============================================== */
24939 typedef enum {                                  /*!< GPIO_CFGG_GPIO48INCFG                                                     */
24940   GPIO_CFGG_GPIO48INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24941   GPIO_CFGG_GPIO48INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24942 } GPIO_CFGG_GPIO48INCFG_Enum;
24943 
24944 /* =========================================================  CFGH  ========================================================== */
24945 /* =============================================  GPIO CFGH GPIO63INTD [31..31]  ============================================= */
24946 typedef enum {                                  /*!< GPIO_CFGH_GPIO63INTD                                                      */
24947   GPIO_CFGH_GPIO63INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD63FNCSEL = NCE63 - nCE polarity active
24948                                                      low                                                                       */
24949   GPIO_CFGH_GPIO63INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD63FNCSEL = NCE63 - nCE polarity active
24950                                                      high                                                                      */
24951 } GPIO_CFGH_GPIO63INTD_Enum;
24952 
24953 /* ============================================  GPIO CFGH GPIO63OUTCFG [29..30]  ============================================ */
24954 typedef enum {                                  /*!< GPIO_CFGH_GPIO63OUTCFG                                                    */
24955   GPIO_CFGH_GPIO63OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD63FNCSEL = GPIO - Output disabled                   */
24956   GPIO_CFGH_GPIO63OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD63FNCSEL = GPIO - Output is push-pull          */
24957   GPIO_CFGH_GPIO63OUTCFG_OD            = 2,     /*!< OD : Applies when PAD63FNCSEL = GPIO - Output is open drain               */
24958   GPIO_CFGH_GPIO63OUTCFG_TS            = 3,     /*!< TS : Applies when PAD63FNCSEL = GPIO - Output is tri-state                */
24959 } GPIO_CFGH_GPIO63OUTCFG_Enum;
24960 
24961 /* ============================================  GPIO CFGH GPIO63INCFG [28..28]  ============================================= */
24962 typedef enum {                                  /*!< GPIO_CFGH_GPIO63INCFG                                                     */
24963   GPIO_CFGH_GPIO63INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24964   GPIO_CFGH_GPIO63INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24965 } GPIO_CFGH_GPIO63INCFG_Enum;
24966 
24967 /* =============================================  GPIO CFGH GPIO62INTD [27..27]  ============================================= */
24968 typedef enum {                                  /*!< GPIO_CFGH_GPIO62INTD                                                      */
24969   GPIO_CFGH_GPIO62INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD62FNCSEL = NCE62 - nCE polarity active
24970                                                      low                                                                       */
24971   GPIO_CFGH_GPIO62INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD62FNCSEL = NCE62 - nCE polarity active
24972                                                      high                                                                      */
24973 } GPIO_CFGH_GPIO62INTD_Enum;
24974 
24975 /* ============================================  GPIO CFGH GPIO62OUTCFG [25..26]  ============================================ */
24976 typedef enum {                                  /*!< GPIO_CFGH_GPIO62OUTCFG                                                    */
24977   GPIO_CFGH_GPIO62OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD62FNCSEL = GPIO - Output disabled                   */
24978   GPIO_CFGH_GPIO62OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD62FNCSEL = GPIO - Output is push-pull          */
24979   GPIO_CFGH_GPIO62OUTCFG_OD            = 2,     /*!< OD : Applies when PAD62FNCSEL = GPIO - Output is open drain               */
24980   GPIO_CFGH_GPIO62OUTCFG_TS            = 3,     /*!< TS : Applies when PAD62FNCSEL = GPIO - Output is tri-state                */
24981 } GPIO_CFGH_GPIO62OUTCFG_Enum;
24982 
24983 /* ============================================  GPIO CFGH GPIO62INCFG [24..24]  ============================================= */
24984 typedef enum {                                  /*!< GPIO_CFGH_GPIO62INCFG                                                     */
24985   GPIO_CFGH_GPIO62INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
24986   GPIO_CFGH_GPIO62INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
24987 } GPIO_CFGH_GPIO62INCFG_Enum;
24988 
24989 /* =============================================  GPIO CFGH GPIO61INTD [23..23]  ============================================= */
24990 typedef enum {                                  /*!< GPIO_CFGH_GPIO61INTD                                                      */
24991   GPIO_CFGH_GPIO61INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD61FNCSEL = NCE61 - nCE polarity active
24992                                                      low                                                                       */
24993   GPIO_CFGH_GPIO61INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD61FNCSEL = NCE61 - nCE polarity active
24994                                                      high                                                                      */
24995 } GPIO_CFGH_GPIO61INTD_Enum;
24996 
24997 /* ============================================  GPIO CFGH GPIO61OUTCFG [21..22]  ============================================ */
24998 typedef enum {                                  /*!< GPIO_CFGH_GPIO61OUTCFG                                                    */
24999   GPIO_CFGH_GPIO61OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD61FNCSEL = GPIO - Output disabled                   */
25000   GPIO_CFGH_GPIO61OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD61FNCSEL = GPIO - Output is push-pull          */
25001   GPIO_CFGH_GPIO61OUTCFG_OD            = 2,     /*!< OD : Applies when PAD61FNCSEL = GPIO - Output is open drain               */
25002   GPIO_CFGH_GPIO61OUTCFG_TS            = 3,     /*!< TS : Applies when PAD61FNCSEL = GPIO - Output is tri-state                */
25003 } GPIO_CFGH_GPIO61OUTCFG_Enum;
25004 
25005 /* ============================================  GPIO CFGH GPIO61INCFG [20..20]  ============================================= */
25006 typedef enum {                                  /*!< GPIO_CFGH_GPIO61INCFG                                                     */
25007   GPIO_CFGH_GPIO61INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25008   GPIO_CFGH_GPIO61INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25009 } GPIO_CFGH_GPIO61INCFG_Enum;
25010 
25011 /* =============================================  GPIO CFGH GPIO60INTD [19..19]  ============================================= */
25012 typedef enum {                                  /*!< GPIO_CFGH_GPIO60INTD                                                      */
25013   GPIO_CFGH_GPIO60INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD60FNCSEL = NCE60 - nCE polarity active
25014                                                      low                                                                       */
25015   GPIO_CFGH_GPIO60INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD60FNCSEL = NCE60 - nCE polarity active
25016                                                      high                                                                      */
25017 } GPIO_CFGH_GPIO60INTD_Enum;
25018 
25019 /* ============================================  GPIO CFGH GPIO60OUTCFG [17..18]  ============================================ */
25020 typedef enum {                                  /*!< GPIO_CFGH_GPIO60OUTCFG                                                    */
25021   GPIO_CFGH_GPIO60OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD60FNCSEL = GPIO - Output disabled                   */
25022   GPIO_CFGH_GPIO60OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD60FNCSEL = GPIO - Output is push-pull          */
25023   GPIO_CFGH_GPIO60OUTCFG_OD            = 2,     /*!< OD : Applies when PAD60FNCSEL = GPIO - Output is open drain               */
25024   GPIO_CFGH_GPIO60OUTCFG_TS            = 3,     /*!< TS : Applies when PAD60FNCSEL = GPIO - Output is tri-state                */
25025 } GPIO_CFGH_GPIO60OUTCFG_Enum;
25026 
25027 /* ============================================  GPIO CFGH GPIO60INCFG [16..16]  ============================================= */
25028 typedef enum {                                  /*!< GPIO_CFGH_GPIO60INCFG                                                     */
25029   GPIO_CFGH_GPIO60INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25030   GPIO_CFGH_GPIO60INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25031 } GPIO_CFGH_GPIO60INCFG_Enum;
25032 
25033 /* =============================================  GPIO CFGH GPIO59INTD [15..15]  ============================================= */
25034 typedef enum {                                  /*!< GPIO_CFGH_GPIO59INTD                                                      */
25035   GPIO_CFGH_GPIO59INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD59FNCSEL = NCE59 - nCE polarity active
25036                                                      low                                                                       */
25037   GPIO_CFGH_GPIO59INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD59FNCSEL = NCE59 - nCE polarity active
25038                                                      high                                                                      */
25039 } GPIO_CFGH_GPIO59INTD_Enum;
25040 
25041 /* ============================================  GPIO CFGH GPIO59OUTCFG [13..14]  ============================================ */
25042 typedef enum {                                  /*!< GPIO_CFGH_GPIO59OUTCFG                                                    */
25043   GPIO_CFGH_GPIO59OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD59FNCSEL = GPIO - Output disabled                   */
25044   GPIO_CFGH_GPIO59OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD59FNCSEL = GPIO - Output is push-pull          */
25045   GPIO_CFGH_GPIO59OUTCFG_OD            = 2,     /*!< OD : Applies when PAD59FNCSEL = GPIO - Output is open drain               */
25046   GPIO_CFGH_GPIO59OUTCFG_TS            = 3,     /*!< TS : Applies when PAD59FNCSEL = GPIO - Output is tri-state                */
25047 } GPIO_CFGH_GPIO59OUTCFG_Enum;
25048 
25049 /* ============================================  GPIO CFGH GPIO59INCFG [12..12]  ============================================= */
25050 typedef enum {                                  /*!< GPIO_CFGH_GPIO59INCFG                                                     */
25051   GPIO_CFGH_GPIO59INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25052   GPIO_CFGH_GPIO59INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25053 } GPIO_CFGH_GPIO59INCFG_Enum;
25054 
25055 /* =============================================  GPIO CFGH GPIO58INTD [11..11]  ============================================= */
25056 typedef enum {                                  /*!< GPIO_CFGH_GPIO58INTD                                                      */
25057   GPIO_CFGH_GPIO58INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD58FNCSEL = NCE58 - nCE polarity active
25058                                                      low                                                                       */
25059   GPIO_CFGH_GPIO58INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD58FNCSEL = NCE58 - nCE polarity active
25060                                                      high                                                                      */
25061 } GPIO_CFGH_GPIO58INTD_Enum;
25062 
25063 /* ============================================  GPIO CFGH GPIO58OUTCFG [9..10]  ============================================= */
25064 typedef enum {                                  /*!< GPIO_CFGH_GPIO58OUTCFG                                                    */
25065   GPIO_CFGH_GPIO58OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD58FNCSEL = GPIO - Output disabled                   */
25066   GPIO_CFGH_GPIO58OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD58FNCSEL = GPIO - Output is push-pull          */
25067   GPIO_CFGH_GPIO58OUTCFG_OD            = 2,     /*!< OD : Applies when PAD58FNCSEL = GPIO - Output is open drain               */
25068   GPIO_CFGH_GPIO58OUTCFG_TS            = 3,     /*!< TS : Applies when PAD58FNCSEL = GPIO - Output is tri-state                */
25069 } GPIO_CFGH_GPIO58OUTCFG_Enum;
25070 
25071 /* =============================================  GPIO CFGH GPIO58INCFG [8..8]  ============================================== */
25072 typedef enum {                                  /*!< GPIO_CFGH_GPIO58INCFG                                                     */
25073   GPIO_CFGH_GPIO58INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25074   GPIO_CFGH_GPIO58INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25075 } GPIO_CFGH_GPIO58INCFG_Enum;
25076 
25077 /* ==============================================  GPIO CFGH GPIO57INTD [7..7]  ============================================== */
25078 typedef enum {                                  /*!< GPIO_CFGH_GPIO57INTD                                                      */
25079   GPIO_CFGH_GPIO57INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD57FNCSEL = NCE57 - nCE polarity active
25080                                                      low                                                                       */
25081   GPIO_CFGH_GPIO57INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD57FNCSEL = NCE57 - nCE polarity active
25082                                                      high                                                                      */
25083 } GPIO_CFGH_GPIO57INTD_Enum;
25084 
25085 /* =============================================  GPIO CFGH GPIO57OUTCFG [5..6]  ============================================= */
25086 typedef enum {                                  /*!< GPIO_CFGH_GPIO57OUTCFG                                                    */
25087   GPIO_CFGH_GPIO57OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD57FNCSEL = GPIO - Output disabled                   */
25088   GPIO_CFGH_GPIO57OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD57FNCSEL = GPIO - Output is push-pull          */
25089   GPIO_CFGH_GPIO57OUTCFG_OD            = 2,     /*!< OD : Applies when PAD57FNCSEL = GPIO - Output is open drain               */
25090   GPIO_CFGH_GPIO57OUTCFG_TS            = 3,     /*!< TS : Applies when PAD57FNCSEL = GPIO - Output is tri-state                */
25091 } GPIO_CFGH_GPIO57OUTCFG_Enum;
25092 
25093 /* =============================================  GPIO CFGH GPIO57INCFG [4..4]  ============================================== */
25094 typedef enum {                                  /*!< GPIO_CFGH_GPIO57INCFG                                                     */
25095   GPIO_CFGH_GPIO57INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25096   GPIO_CFGH_GPIO57INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25097 } GPIO_CFGH_GPIO57INCFG_Enum;
25098 
25099 /* ==============================================  GPIO CFGH GPIO56INTD [3..3]  ============================================== */
25100 typedef enum {                                  /*!< GPIO_CFGH_GPIO56INTD                                                      */
25101   GPIO_CFGH_GPIO56INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD56FNCSEL = NCE56 - nCE polarity active
25102                                                      low                                                                       */
25103   GPIO_CFGH_GPIO56INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD56FNCSEL = NCE56 - nCE polarity active
25104                                                      high                                                                      */
25105 } GPIO_CFGH_GPIO56INTD_Enum;
25106 
25107 /* =============================================  GPIO CFGH GPIO56OUTCFG [1..2]  ============================================= */
25108 typedef enum {                                  /*!< GPIO_CFGH_GPIO56OUTCFG                                                    */
25109   GPIO_CFGH_GPIO56OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD56FNCSEL = GPIO - Output disabled                   */
25110   GPIO_CFGH_GPIO56OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD56FNCSEL = GPIO - Output is push-pull          */
25111   GPIO_CFGH_GPIO56OUTCFG_OD            = 2,     /*!< OD : Applies when PAD56FNCSEL = GPIO - Output is open drain               */
25112   GPIO_CFGH_GPIO56OUTCFG_TS            = 3,     /*!< TS : Applies when PAD56FNCSEL = GPIO - Output is tri-state                */
25113 } GPIO_CFGH_GPIO56OUTCFG_Enum;
25114 
25115 /* =============================================  GPIO CFGH GPIO56INCFG [0..0]  ============================================== */
25116 typedef enum {                                  /*!< GPIO_CFGH_GPIO56INCFG                                                     */
25117   GPIO_CFGH_GPIO56INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25118   GPIO_CFGH_GPIO56INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25119 } GPIO_CFGH_GPIO56INCFG_Enum;
25120 
25121 /* =========================================================  CFGI  ========================================================== */
25122 /* =============================================  GPIO CFGI GPIO71INTD [31..31]  ============================================= */
25123 typedef enum {                                  /*!< GPIO_CFGI_GPIO71INTD                                                      */
25124   GPIO_CFGI_GPIO71INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD71FNCSEL = NCE71 - nCE polarity active
25125                                                      low                                                                       */
25126   GPIO_CFGI_GPIO71INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD71FNCSEL = NCE71 - nCE polarity active
25127                                                      high                                                                      */
25128 } GPIO_CFGI_GPIO71INTD_Enum;
25129 
25130 /* ============================================  GPIO CFGI GPIO71OUTCFG [29..30]  ============================================ */
25131 typedef enum {                                  /*!< GPIO_CFGI_GPIO71OUTCFG                                                    */
25132   GPIO_CFGI_GPIO71OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD71FNCSEL = GPIO - Output disabled                   */
25133   GPIO_CFGI_GPIO71OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD71FNCSEL = GPIO - Output is push-pull          */
25134   GPIO_CFGI_GPIO71OUTCFG_OD            = 2,     /*!< OD : Applies when PAD71FNCSEL = GPIO - Output is open drain               */
25135   GPIO_CFGI_GPIO71OUTCFG_TS            = 3,     /*!< TS : Applies when PAD71FNCSEL = GPIO - Output is tri-state                */
25136 } GPIO_CFGI_GPIO71OUTCFG_Enum;
25137 
25138 /* ============================================  GPIO CFGI GPIO71INCFG [28..28]  ============================================= */
25139 typedef enum {                                  /*!< GPIO_CFGI_GPIO71INCFG                                                     */
25140   GPIO_CFGI_GPIO71INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25141   GPIO_CFGI_GPIO71INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25142 } GPIO_CFGI_GPIO71INCFG_Enum;
25143 
25144 /* =============================================  GPIO CFGI GPIO70INTD [27..27]  ============================================= */
25145 typedef enum {                                  /*!< GPIO_CFGI_GPIO70INTD                                                      */
25146   GPIO_CFGI_GPIO70INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD70FNCSEL = NCE70 - nCE polarity active
25147                                                      low                                                                       */
25148   GPIO_CFGI_GPIO70INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD70FNCSEL = NCE70 - nCE polarity active
25149                                                      high                                                                      */
25150 } GPIO_CFGI_GPIO70INTD_Enum;
25151 
25152 /* ============================================  GPIO CFGI GPIO70OUTCFG [25..26]  ============================================ */
25153 typedef enum {                                  /*!< GPIO_CFGI_GPIO70OUTCFG                                                    */
25154   GPIO_CFGI_GPIO70OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD70FNCSEL = GPIO - Output disabled                   */
25155   GPIO_CFGI_GPIO70OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD70FNCSEL = GPIO - Output is push-pull          */
25156   GPIO_CFGI_GPIO70OUTCFG_OD            = 2,     /*!< OD : Applies when PAD70FNCSEL = GPIO - Output is open drain               */
25157   GPIO_CFGI_GPIO70OUTCFG_TS            = 3,     /*!< TS : Applies when PAD70FNCSEL = GPIO - Output is tri-state                */
25158 } GPIO_CFGI_GPIO70OUTCFG_Enum;
25159 
25160 /* ============================================  GPIO CFGI GPIO70INCFG [24..24]  ============================================= */
25161 typedef enum {                                  /*!< GPIO_CFGI_GPIO70INCFG                                                     */
25162   GPIO_CFGI_GPIO70INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25163   GPIO_CFGI_GPIO70INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25164 } GPIO_CFGI_GPIO70INCFG_Enum;
25165 
25166 /* =============================================  GPIO CFGI GPIO69INTD [23..23]  ============================================= */
25167 typedef enum {                                  /*!< GPIO_CFGI_GPIO69INTD                                                      */
25168   GPIO_CFGI_GPIO69INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD69FNCSEL = NCE69 - nCE polarity active
25169                                                      low                                                                       */
25170   GPIO_CFGI_GPIO69INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD69FNCSEL = NCE69 - nCE polarity active
25171                                                      high                                                                      */
25172 } GPIO_CFGI_GPIO69INTD_Enum;
25173 
25174 /* ============================================  GPIO CFGI GPIO69OUTCFG [21..22]  ============================================ */
25175 typedef enum {                                  /*!< GPIO_CFGI_GPIO69OUTCFG                                                    */
25176   GPIO_CFGI_GPIO69OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD69FNCSEL = GPIO - Output disabled                   */
25177   GPIO_CFGI_GPIO69OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD69FNCSEL = GPIO - Output is push-pull          */
25178   GPIO_CFGI_GPIO69OUTCFG_OD            = 2,     /*!< OD : Applies when PAD69FNCSEL = GPIO - Output is open drain               */
25179   GPIO_CFGI_GPIO69OUTCFG_TS            = 3,     /*!< TS : Applies when PAD69FNCSEL = GPIO - Output is tri-state                */
25180 } GPIO_CFGI_GPIO69OUTCFG_Enum;
25181 
25182 /* ============================================  GPIO CFGI GPIO69INCFG [20..20]  ============================================= */
25183 typedef enum {                                  /*!< GPIO_CFGI_GPIO69INCFG                                                     */
25184   GPIO_CFGI_GPIO69INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25185   GPIO_CFGI_GPIO69INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25186 } GPIO_CFGI_GPIO69INCFG_Enum;
25187 
25188 /* =============================================  GPIO CFGI GPIO68INTD [19..19]  ============================================= */
25189 typedef enum {                                  /*!< GPIO_CFGI_GPIO68INTD                                                      */
25190   GPIO_CFGI_GPIO68INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD68FNCSEL = NCE68 - nCE polarity active
25191                                                      low                                                                       */
25192   GPIO_CFGI_GPIO68INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD68FNCSEL = NCE68 - nCE polarity active
25193                                                      high                                                                      */
25194 } GPIO_CFGI_GPIO68INTD_Enum;
25195 
25196 /* ============================================  GPIO CFGI GPIO68OUTCFG [17..18]  ============================================ */
25197 typedef enum {                                  /*!< GPIO_CFGI_GPIO68OUTCFG                                                    */
25198   GPIO_CFGI_GPIO68OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD68FNCSEL = GPIO - Output disabled                   */
25199   GPIO_CFGI_GPIO68OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD68FNCSEL = GPIO - Output is push-pull          */
25200   GPIO_CFGI_GPIO68OUTCFG_OD            = 2,     /*!< OD : Applies when PAD68FNCSEL = GPIO - Output is open drain               */
25201   GPIO_CFGI_GPIO68OUTCFG_TS            = 3,     /*!< TS : Applies when PAD68FNCSEL = GPIO - Output is tri-state                */
25202 } GPIO_CFGI_GPIO68OUTCFG_Enum;
25203 
25204 /* ============================================  GPIO CFGI GPIO68INCFG [16..16]  ============================================= */
25205 typedef enum {                                  /*!< GPIO_CFGI_GPIO68INCFG                                                     */
25206   GPIO_CFGI_GPIO68INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25207   GPIO_CFGI_GPIO68INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25208 } GPIO_CFGI_GPIO68INCFG_Enum;
25209 
25210 /* =============================================  GPIO CFGI GPIO67INTD [15..15]  ============================================= */
25211 typedef enum {                                  /*!< GPIO_CFGI_GPIO67INTD                                                      */
25212   GPIO_CFGI_GPIO67INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD67FNCSEL = NCE67 - nCE polarity active
25213                                                      low                                                                       */
25214   GPIO_CFGI_GPIO67INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD67FNCSEL = NCE67 - nCE polarity active
25215                                                      high                                                                      */
25216 } GPIO_CFGI_GPIO67INTD_Enum;
25217 
25218 /* ============================================  GPIO CFGI GPIO67OUTCFG [13..14]  ============================================ */
25219 typedef enum {                                  /*!< GPIO_CFGI_GPIO67OUTCFG                                                    */
25220   GPIO_CFGI_GPIO67OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD67FNCSEL = GPIO - Output disabled                   */
25221   GPIO_CFGI_GPIO67OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD67FNCSEL = GPIO - Output is push-pull          */
25222   GPIO_CFGI_GPIO67OUTCFG_OD            = 2,     /*!< OD : Applies when PAD67FNCSEL = GPIO - Output is open drain               */
25223   GPIO_CFGI_GPIO67OUTCFG_TS            = 3,     /*!< TS : Applies when PAD67FNCSEL = GPIO - Output is tri-state                */
25224 } GPIO_CFGI_GPIO67OUTCFG_Enum;
25225 
25226 /* ============================================  GPIO CFGI GPIO67INCFG [12..12]  ============================================= */
25227 typedef enum {                                  /*!< GPIO_CFGI_GPIO67INCFG                                                     */
25228   GPIO_CFGI_GPIO67INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25229   GPIO_CFGI_GPIO67INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25230 } GPIO_CFGI_GPIO67INCFG_Enum;
25231 
25232 /* =============================================  GPIO CFGI GPIO66INTD [11..11]  ============================================= */
25233 typedef enum {                                  /*!< GPIO_CFGI_GPIO66INTD                                                      */
25234   GPIO_CFGI_GPIO66INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD66FNCSEL = NCE66 - nCE polarity active
25235                                                      low                                                                       */
25236   GPIO_CFGI_GPIO66INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD66FNCSEL = NCE66 - nCE polarity active
25237                                                      high                                                                      */
25238 } GPIO_CFGI_GPIO66INTD_Enum;
25239 
25240 /* ============================================  GPIO CFGI GPIO66OUTCFG [9..10]  ============================================= */
25241 typedef enum {                                  /*!< GPIO_CFGI_GPIO66OUTCFG                                                    */
25242   GPIO_CFGI_GPIO66OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD66FNCSEL = GPIO - Output disabled                   */
25243   GPIO_CFGI_GPIO66OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD66FNCSEL = GPIO - Output is push-pull          */
25244   GPIO_CFGI_GPIO66OUTCFG_OD            = 2,     /*!< OD : Applies when PAD66FNCSEL = GPIO - Output is open drain               */
25245   GPIO_CFGI_GPIO66OUTCFG_TS            = 3,     /*!< TS : Applies when PAD66FNCSEL = GPIO - Output is tri-state                */
25246 } GPIO_CFGI_GPIO66OUTCFG_Enum;
25247 
25248 /* =============================================  GPIO CFGI GPIO66INCFG [8..8]  ============================================== */
25249 typedef enum {                                  /*!< GPIO_CFGI_GPIO66INCFG                                                     */
25250   GPIO_CFGI_GPIO66INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25251   GPIO_CFGI_GPIO66INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25252 } GPIO_CFGI_GPIO66INCFG_Enum;
25253 
25254 /* ==============================================  GPIO CFGI GPIO65INTD [7..7]  ============================================== */
25255 typedef enum {                                  /*!< GPIO_CFGI_GPIO65INTD                                                      */
25256   GPIO_CFGI_GPIO65INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD65FNCSEL = NCE65 - nCE polarity active
25257                                                      low                                                                       */
25258   GPIO_CFGI_GPIO65INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD65FNCSEL = NCE65 - nCE polarity active
25259                                                      high                                                                      */
25260 } GPIO_CFGI_GPIO65INTD_Enum;
25261 
25262 /* =============================================  GPIO CFGI GPIO65OUTCFG [5..6]  ============================================= */
25263 typedef enum {                                  /*!< GPIO_CFGI_GPIO65OUTCFG                                                    */
25264   GPIO_CFGI_GPIO65OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD65FNCSEL = GPIO - Output disabled                   */
25265   GPIO_CFGI_GPIO65OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD65FNCSEL = GPIO - Output is push-pull          */
25266   GPIO_CFGI_GPIO65OUTCFG_OD            = 2,     /*!< OD : Applies when PAD65FNCSEL = GPIO - Output is open drain               */
25267   GPIO_CFGI_GPIO65OUTCFG_TS            = 3,     /*!< TS : Applies when PAD65FNCSEL = GPIO - Output is tri-state                */
25268 } GPIO_CFGI_GPIO65OUTCFG_Enum;
25269 
25270 /* =============================================  GPIO CFGI GPIO65INCFG [4..4]  ============================================== */
25271 typedef enum {                                  /*!< GPIO_CFGI_GPIO65INCFG                                                     */
25272   GPIO_CFGI_GPIO65INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25273   GPIO_CFGI_GPIO65INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25274 } GPIO_CFGI_GPIO65INCFG_Enum;
25275 
25276 /* ==============================================  GPIO CFGI GPIO64INTD [3..3]  ============================================== */
25277 typedef enum {                                  /*!< GPIO_CFGI_GPIO64INTD                                                      */
25278   GPIO_CFGI_GPIO64INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD64FNCSEL = NCE64 - nCE polarity active
25279                                                      low                                                                       */
25280   GPIO_CFGI_GPIO64INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD64FNCSEL = NCE64 - nCE polarity active
25281                                                      high                                                                      */
25282 } GPIO_CFGI_GPIO64INTD_Enum;
25283 
25284 /* =============================================  GPIO CFGI GPIO64OUTCFG [1..2]  ============================================= */
25285 typedef enum {                                  /*!< GPIO_CFGI_GPIO64OUTCFG                                                    */
25286   GPIO_CFGI_GPIO64OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD64FNCSEL = GPIO - Output disabled                   */
25287   GPIO_CFGI_GPIO64OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD64FNCSEL = GPIO - Output is push-pull          */
25288   GPIO_CFGI_GPIO64OUTCFG_OD            = 2,     /*!< OD : Applies when PAD64FNCSEL = GPIO - Output is open drain               */
25289   GPIO_CFGI_GPIO64OUTCFG_TS            = 3,     /*!< TS : Applies when PAD64FNCSEL = GPIO - Output is tri-state                */
25290 } GPIO_CFGI_GPIO64OUTCFG_Enum;
25291 
25292 /* =============================================  GPIO CFGI GPIO64INCFG [0..0]  ============================================== */
25293 typedef enum {                                  /*!< GPIO_CFGI_GPIO64INCFG                                                     */
25294   GPIO_CFGI_GPIO64INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25295   GPIO_CFGI_GPIO64INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25296 } GPIO_CFGI_GPIO64INCFG_Enum;
25297 
25298 /* =========================================================  CFGJ  ========================================================== */
25299 /* ==============================================  GPIO CFGJ GPIO73INTD [7..7]  ============================================== */
25300 typedef enum {                                  /*!< GPIO_CFGJ_GPIO73INTD                                                      */
25301   GPIO_CFGJ_GPIO73INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD73FNCSEL = NCE73 - nCE polarity active
25302                                                      low                                                                       */
25303   GPIO_CFGJ_GPIO73INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD73FNCSEL = NCE73 - nCE polarity active
25304                                                      high                                                                      */
25305 } GPIO_CFGJ_GPIO73INTD_Enum;
25306 
25307 /* =============================================  GPIO CFGJ GPIO73OUTCFG [5..6]  ============================================= */
25308 typedef enum {                                  /*!< GPIO_CFGJ_GPIO73OUTCFG                                                    */
25309   GPIO_CFGJ_GPIO73OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD73FNCSEL = GPIO - Output disabled                   */
25310   GPIO_CFGJ_GPIO73OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD73FNCSEL = GPIO - Output is push-pull          */
25311   GPIO_CFGJ_GPIO73OUTCFG_OD            = 2,     /*!< OD : Applies when PAD73FNCSEL = GPIO - Output is open drain               */
25312   GPIO_CFGJ_GPIO73OUTCFG_TS            = 3,     /*!< TS : Applies when PAD73FNCSEL = GPIO - Output is tri-state                */
25313 } GPIO_CFGJ_GPIO73OUTCFG_Enum;
25314 
25315 /* =============================================  GPIO CFGJ GPIO73INCFG [4..4]  ============================================== */
25316 typedef enum {                                  /*!< GPIO_CFGJ_GPIO73INCFG                                                     */
25317   GPIO_CFGJ_GPIO73INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25318   GPIO_CFGJ_GPIO73INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25319 } GPIO_CFGJ_GPIO73INCFG_Enum;
25320 
25321 /* ==============================================  GPIO CFGJ GPIO72INTD [3..3]  ============================================== */
25322 typedef enum {                                  /*!< GPIO_CFGJ_GPIO72INTD                                                      */
25323   GPIO_CFGJ_GPIO72INTD_nCELOW          = 0,     /*!< nCELOW : Applies when PAD72FNCSEL = NCE72 - nCE polarity active
25324                                                      low                                                                       */
25325   GPIO_CFGJ_GPIO72INTD_nCEHIGH         = 1,     /*!< nCEHIGH : Applies when PAD72FNCSEL = NCE72 - nCE polarity active
25326                                                      high                                                                      */
25327 } GPIO_CFGJ_GPIO72INTD_Enum;
25328 
25329 /* =============================================  GPIO CFGJ GPIO72OUTCFG [1..2]  ============================================= */
25330 typedef enum {                                  /*!< GPIO_CFGJ_GPIO72OUTCFG                                                    */
25331   GPIO_CFGJ_GPIO72OUTCFG_DIS           = 0,     /*!< DIS : Applies when PAD72FNCSEL = GPIO - Output disabled                   */
25332   GPIO_CFGJ_GPIO72OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : Applies when PAD72FNCSEL = GPIO - Output is push-pull          */
25333   GPIO_CFGJ_GPIO72OUTCFG_OD            = 2,     /*!< OD : Applies when PAD72FNCSEL = GPIO - Output is open drain               */
25334   GPIO_CFGJ_GPIO72OUTCFG_TS            = 3,     /*!< TS : Applies when PAD72FNCSEL = GPIO - Output is tri-state                */
25335 } GPIO_CFGJ_GPIO72OUTCFG_Enum;
25336 
25337 /* =============================================  GPIO CFGJ GPIO72INCFG [0..0]  ============================================== */
25338 typedef enum {                                  /*!< GPIO_CFGJ_GPIO72INCFG                                                     */
25339   GPIO_CFGJ_GPIO72INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
25340   GPIO_CFGJ_GPIO72INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Read-back will always be zero                         */
25341 } GPIO_CFGJ_GPIO72INCFG_Enum;
25342 
25343 /* ========================================================  PADKEY  ========================================================= */
25344 /* ==============================================  GPIO PADKEY PADKEY [0..31]  =============================================== */
25345 typedef enum {                                  /*!< GPIO_PADKEY_PADKEY                                                        */
25346   GPIO_PADKEY_PADKEY_Key               = 115,   /*!< Key : Key value to unlock the register.                                   */
25347 } GPIO_PADKEY_PADKEY_Enum;
25348 
25349 /* ==========================================================  RDA  ========================================================== */
25350 /* ==========================================================  RDB  ========================================================== */
25351 /* ==========================================================  RDC  ========================================================== */
25352 /* ==========================================================  WTA  ========================================================== */
25353 /* ==========================================================  WTB  ========================================================== */
25354 /* ==========================================================  WTC  ========================================================== */
25355 /* =========================================================  WTSA  ========================================================== */
25356 /* =========================================================  WTSB  ========================================================== */
25357 /* =========================================================  WTSC  ========================================================== */
25358 /* =========================================================  WTCA  ========================================================== */
25359 /* =========================================================  WTCB  ========================================================== */
25360 /* =========================================================  WTCC  ========================================================== */
25361 /* ==========================================================  ENA  ========================================================== */
25362 /* ==========================================================  ENB  ========================================================== */
25363 /* ==========================================================  ENC  ========================================================== */
25364 /* =========================================================  ENSA  ========================================================== */
25365 /* =========================================================  ENSB  ========================================================== */
25366 /* =========================================================  ENSC  ========================================================== */
25367 /* =========================================================  ENCA  ========================================================== */
25368 /* =========================================================  ENCB  ========================================================== */
25369 /* =========================================================  ENCC  ========================================================== */
25370 /* ========================================================  STMRCAP  ======================================================== */
25371 /* =============================================  GPIO STMRCAP STPOL3 [31..31]  ============================================== */
25372 typedef enum {                                  /*!< GPIO_STMRCAP_STPOL3                                                       */
25373   GPIO_STMRCAP_STPOL3_CAPLH            = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
25374   GPIO_STMRCAP_STPOL3_CAPHL            = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
25375 } GPIO_STMRCAP_STPOL3_Enum;
25376 
25377 /* =============================================  GPIO STMRCAP STPOL2 [23..23]  ============================================== */
25378 typedef enum {                                  /*!< GPIO_STMRCAP_STPOL2                                                       */
25379   GPIO_STMRCAP_STPOL2_CAPLH            = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
25380   GPIO_STMRCAP_STPOL2_CAPHL            = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
25381 } GPIO_STMRCAP_STPOL2_Enum;
25382 
25383 /* =============================================  GPIO STMRCAP STPOL1 [15..15]  ============================================== */
25384 typedef enum {                                  /*!< GPIO_STMRCAP_STPOL1                                                       */
25385   GPIO_STMRCAP_STPOL1_CAPLH            = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
25386   GPIO_STMRCAP_STPOL1_CAPHL            = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
25387 } GPIO_STMRCAP_STPOL1_Enum;
25388 
25389 /* ==============================================  GPIO STMRCAP STPOL0 [7..7]  =============================================== */
25390 typedef enum {                                  /*!< GPIO_STMRCAP_STPOL0                                                       */
25391   GPIO_STMRCAP_STPOL0_CAPLH            = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
25392   GPIO_STMRCAP_STPOL0_CAPHL            = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
25393 } GPIO_STMRCAP_STPOL0_Enum;
25394 
25395 /* ========================================================  IOM0IRQ  ======================================================== */
25396 /* ========================================================  IOM1IRQ  ======================================================== */
25397 /* ========================================================  IOM2IRQ  ======================================================== */
25398 /* ========================================================  IOM3IRQ  ======================================================== */
25399 /* ========================================================  IOM4IRQ  ======================================================== */
25400 /* ========================================================  IOM5IRQ  ======================================================== */
25401 /* =======================================================  BLEIFIRQ  ======================================================== */
25402 /* ========================================================  GPIOOBS  ======================================================== */
25403 /* ======================================================  ALTPADCFGA  ======================================================= */
25404 /* ===========================================  GPIO ALTPADCFGA PAD3_SR [28..28]  ============================================ */
25405 typedef enum {                                  /*!< GPIO_ALTPADCFGA_PAD3_SR                                                   */
25406   GPIO_ALTPADCFGA_PAD3_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25407 } GPIO_ALTPADCFGA_PAD3_SR_Enum;
25408 
25409 /* ===========================================  GPIO ALTPADCFGA PAD2_SR [20..20]  ============================================ */
25410 typedef enum {                                  /*!< GPIO_ALTPADCFGA_PAD2_SR                                                   */
25411   GPIO_ALTPADCFGA_PAD2_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25412 } GPIO_ALTPADCFGA_PAD2_SR_Enum;
25413 
25414 /* ===========================================  GPIO ALTPADCFGA PAD1_SR [12..12]  ============================================ */
25415 typedef enum {                                  /*!< GPIO_ALTPADCFGA_PAD1_SR                                                   */
25416   GPIO_ALTPADCFGA_PAD1_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25417 } GPIO_ALTPADCFGA_PAD1_SR_Enum;
25418 
25419 /* ============================================  GPIO ALTPADCFGA PAD0_SR [4..4]  ============================================= */
25420 typedef enum {                                  /*!< GPIO_ALTPADCFGA_PAD0_SR                                                   */
25421   GPIO_ALTPADCFGA_PAD0_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25422 } GPIO_ALTPADCFGA_PAD0_SR_Enum;
25423 
25424 /* ======================================================  ALTPADCFGB  ======================================================= */
25425 /* ===========================================  GPIO ALTPADCFGB PAD7_SR [28..28]  ============================================ */
25426 typedef enum {                                  /*!< GPIO_ALTPADCFGB_PAD7_SR                                                   */
25427   GPIO_ALTPADCFGB_PAD7_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25428 } GPIO_ALTPADCFGB_PAD7_SR_Enum;
25429 
25430 /* ===========================================  GPIO ALTPADCFGB PAD6_SR [20..20]  ============================================ */
25431 typedef enum {                                  /*!< GPIO_ALTPADCFGB_PAD6_SR                                                   */
25432   GPIO_ALTPADCFGB_PAD6_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25433 } GPIO_ALTPADCFGB_PAD6_SR_Enum;
25434 
25435 /* ===========================================  GPIO ALTPADCFGB PAD5_SR [12..12]  ============================================ */
25436 typedef enum {                                  /*!< GPIO_ALTPADCFGB_PAD5_SR                                                   */
25437   GPIO_ALTPADCFGB_PAD5_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25438 } GPIO_ALTPADCFGB_PAD5_SR_Enum;
25439 
25440 /* ============================================  GPIO ALTPADCFGB PAD4_SR [4..4]  ============================================= */
25441 typedef enum {                                  /*!< GPIO_ALTPADCFGB_PAD4_SR                                                   */
25442   GPIO_ALTPADCFGB_PAD4_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25443 } GPIO_ALTPADCFGB_PAD4_SR_Enum;
25444 
25445 /* ======================================================  ALTPADCFGC  ======================================================= */
25446 /* ===========================================  GPIO ALTPADCFGC PAD11_SR [28..28]  =========================================== */
25447 typedef enum {                                  /*!< GPIO_ALTPADCFGC_PAD11_SR                                                  */
25448   GPIO_ALTPADCFGC_PAD11_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25449 } GPIO_ALTPADCFGC_PAD11_SR_Enum;
25450 
25451 /* ===========================================  GPIO ALTPADCFGC PAD10_SR [20..20]  =========================================== */
25452 typedef enum {                                  /*!< GPIO_ALTPADCFGC_PAD10_SR                                                  */
25453   GPIO_ALTPADCFGC_PAD10_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25454 } GPIO_ALTPADCFGC_PAD10_SR_Enum;
25455 
25456 /* ===========================================  GPIO ALTPADCFGC PAD9_SR [12..12]  ============================================ */
25457 typedef enum {                                  /*!< GPIO_ALTPADCFGC_PAD9_SR                                                   */
25458   GPIO_ALTPADCFGC_PAD9_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25459 } GPIO_ALTPADCFGC_PAD9_SR_Enum;
25460 
25461 /* ============================================  GPIO ALTPADCFGC PAD8_SR [4..4]  ============================================= */
25462 typedef enum {                                  /*!< GPIO_ALTPADCFGC_PAD8_SR                                                   */
25463   GPIO_ALTPADCFGC_PAD8_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25464 } GPIO_ALTPADCFGC_PAD8_SR_Enum;
25465 
25466 /* ======================================================  ALTPADCFGD  ======================================================= */
25467 /* ===========================================  GPIO ALTPADCFGD PAD15_SR [28..28]  =========================================== */
25468 typedef enum {                                  /*!< GPIO_ALTPADCFGD_PAD15_SR                                                  */
25469   GPIO_ALTPADCFGD_PAD15_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25470 } GPIO_ALTPADCFGD_PAD15_SR_Enum;
25471 
25472 /* ===========================================  GPIO ALTPADCFGD PAD14_SR [20..20]  =========================================== */
25473 typedef enum {                                  /*!< GPIO_ALTPADCFGD_PAD14_SR                                                  */
25474   GPIO_ALTPADCFGD_PAD14_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25475 } GPIO_ALTPADCFGD_PAD14_SR_Enum;
25476 
25477 /* ===========================================  GPIO ALTPADCFGD PAD13_SR [12..12]  =========================================== */
25478 typedef enum {                                  /*!< GPIO_ALTPADCFGD_PAD13_SR                                                  */
25479   GPIO_ALTPADCFGD_PAD13_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25480 } GPIO_ALTPADCFGD_PAD13_SR_Enum;
25481 
25482 /* ============================================  GPIO ALTPADCFGD PAD12_SR [4..4]  ============================================ */
25483 typedef enum {                                  /*!< GPIO_ALTPADCFGD_PAD12_SR                                                  */
25484   GPIO_ALTPADCFGD_PAD12_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25485 } GPIO_ALTPADCFGD_PAD12_SR_Enum;
25486 
25487 /* ======================================================  ALTPADCFGE  ======================================================= */
25488 /* ===========================================  GPIO ALTPADCFGE PAD19_SR [28..28]  =========================================== */
25489 typedef enum {                                  /*!< GPIO_ALTPADCFGE_PAD19_SR                                                  */
25490   GPIO_ALTPADCFGE_PAD19_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25491 } GPIO_ALTPADCFGE_PAD19_SR_Enum;
25492 
25493 /* ===========================================  GPIO ALTPADCFGE PAD18_SR [20..20]  =========================================== */
25494 typedef enum {                                  /*!< GPIO_ALTPADCFGE_PAD18_SR                                                  */
25495   GPIO_ALTPADCFGE_PAD18_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25496 } GPIO_ALTPADCFGE_PAD18_SR_Enum;
25497 
25498 /* ===========================================  GPIO ALTPADCFGE PAD17_SR [12..12]  =========================================== */
25499 typedef enum {                                  /*!< GPIO_ALTPADCFGE_PAD17_SR                                                  */
25500   GPIO_ALTPADCFGE_PAD17_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25501 } GPIO_ALTPADCFGE_PAD17_SR_Enum;
25502 
25503 /* ============================================  GPIO ALTPADCFGE PAD16_SR [4..4]  ============================================ */
25504 typedef enum {                                  /*!< GPIO_ALTPADCFGE_PAD16_SR                                                  */
25505   GPIO_ALTPADCFGE_PAD16_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25506 } GPIO_ALTPADCFGE_PAD16_SR_Enum;
25507 
25508 /* ======================================================  ALTPADCFGF  ======================================================= */
25509 /* ===========================================  GPIO ALTPADCFGF PAD23_SR [28..28]  =========================================== */
25510 typedef enum {                                  /*!< GPIO_ALTPADCFGF_PAD23_SR                                                  */
25511   GPIO_ALTPADCFGF_PAD23_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25512 } GPIO_ALTPADCFGF_PAD23_SR_Enum;
25513 
25514 /* ===========================================  GPIO ALTPADCFGF PAD22_SR [20..20]  =========================================== */
25515 typedef enum {                                  /*!< GPIO_ALTPADCFGF_PAD22_SR                                                  */
25516   GPIO_ALTPADCFGF_PAD22_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25517 } GPIO_ALTPADCFGF_PAD22_SR_Enum;
25518 
25519 /* ===========================================  GPIO ALTPADCFGF PAD21_SR [12..12]  =========================================== */
25520 typedef enum {                                  /*!< GPIO_ALTPADCFGF_PAD21_SR                                                  */
25521   GPIO_ALTPADCFGF_PAD21_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25522 } GPIO_ALTPADCFGF_PAD21_SR_Enum;
25523 
25524 /* ============================================  GPIO ALTPADCFGF PAD20_SR [4..4]  ============================================ */
25525 typedef enum {                                  /*!< GPIO_ALTPADCFGF_PAD20_SR                                                  */
25526   GPIO_ALTPADCFGF_PAD20_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25527 } GPIO_ALTPADCFGF_PAD20_SR_Enum;
25528 
25529 /* ======================================================  ALTPADCFGG  ======================================================= */
25530 /* ===========================================  GPIO ALTPADCFGG PAD27_SR [28..28]  =========================================== */
25531 typedef enum {                                  /*!< GPIO_ALTPADCFGG_PAD27_SR                                                  */
25532   GPIO_ALTPADCFGG_PAD27_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25533 } GPIO_ALTPADCFGG_PAD27_SR_Enum;
25534 
25535 /* ===========================================  GPIO ALTPADCFGG PAD26_SR [20..20]  =========================================== */
25536 typedef enum {                                  /*!< GPIO_ALTPADCFGG_PAD26_SR                                                  */
25537   GPIO_ALTPADCFGG_PAD26_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25538 } GPIO_ALTPADCFGG_PAD26_SR_Enum;
25539 
25540 /* ===========================================  GPIO ALTPADCFGG PAD25_SR [12..12]  =========================================== */
25541 typedef enum {                                  /*!< GPIO_ALTPADCFGG_PAD25_SR                                                  */
25542   GPIO_ALTPADCFGG_PAD25_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25543 } GPIO_ALTPADCFGG_PAD25_SR_Enum;
25544 
25545 /* ============================================  GPIO ALTPADCFGG PAD24_SR [4..4]  ============================================ */
25546 typedef enum {                                  /*!< GPIO_ALTPADCFGG_PAD24_SR                                                  */
25547   GPIO_ALTPADCFGG_PAD24_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25548 } GPIO_ALTPADCFGG_PAD24_SR_Enum;
25549 
25550 /* ======================================================  ALTPADCFGH  ======================================================= */
25551 /* ===========================================  GPIO ALTPADCFGH PAD31_SR [28..28]  =========================================== */
25552 typedef enum {                                  /*!< GPIO_ALTPADCFGH_PAD31_SR                                                  */
25553   GPIO_ALTPADCFGH_PAD31_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25554 } GPIO_ALTPADCFGH_PAD31_SR_Enum;
25555 
25556 /* ===========================================  GPIO ALTPADCFGH PAD30_SR [20..20]  =========================================== */
25557 typedef enum {                                  /*!< GPIO_ALTPADCFGH_PAD30_SR                                                  */
25558   GPIO_ALTPADCFGH_PAD30_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25559 } GPIO_ALTPADCFGH_PAD30_SR_Enum;
25560 
25561 /* ===========================================  GPIO ALTPADCFGH PAD29_SR [12..12]  =========================================== */
25562 typedef enum {                                  /*!< GPIO_ALTPADCFGH_PAD29_SR                                                  */
25563   GPIO_ALTPADCFGH_PAD29_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25564 } GPIO_ALTPADCFGH_PAD29_SR_Enum;
25565 
25566 /* ============================================  GPIO ALTPADCFGH PAD28_SR [4..4]  ============================================ */
25567 typedef enum {                                  /*!< GPIO_ALTPADCFGH_PAD28_SR                                                  */
25568   GPIO_ALTPADCFGH_PAD28_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25569 } GPIO_ALTPADCFGH_PAD28_SR_Enum;
25570 
25571 /* ======================================================  ALTPADCFGI  ======================================================= */
25572 /* ===========================================  GPIO ALTPADCFGI PAD35_SR [28..28]  =========================================== */
25573 typedef enum {                                  /*!< GPIO_ALTPADCFGI_PAD35_SR                                                  */
25574   GPIO_ALTPADCFGI_PAD35_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25575 } GPIO_ALTPADCFGI_PAD35_SR_Enum;
25576 
25577 /* ===========================================  GPIO ALTPADCFGI PAD34_SR [20..20]  =========================================== */
25578 typedef enum {                                  /*!< GPIO_ALTPADCFGI_PAD34_SR                                                  */
25579   GPIO_ALTPADCFGI_PAD34_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25580 } GPIO_ALTPADCFGI_PAD34_SR_Enum;
25581 
25582 /* ===========================================  GPIO ALTPADCFGI PAD33_SR [12..12]  =========================================== */
25583 typedef enum {                                  /*!< GPIO_ALTPADCFGI_PAD33_SR                                                  */
25584   GPIO_ALTPADCFGI_PAD33_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25585 } GPIO_ALTPADCFGI_PAD33_SR_Enum;
25586 
25587 /* ============================================  GPIO ALTPADCFGI PAD32_SR [4..4]  ============================================ */
25588 typedef enum {                                  /*!< GPIO_ALTPADCFGI_PAD32_SR                                                  */
25589   GPIO_ALTPADCFGI_PAD32_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25590 } GPIO_ALTPADCFGI_PAD32_SR_Enum;
25591 
25592 /* ======================================================  ALTPADCFGJ  ======================================================= */
25593 /* ===========================================  GPIO ALTPADCFGJ PAD39_SR [28..28]  =========================================== */
25594 typedef enum {                                  /*!< GPIO_ALTPADCFGJ_PAD39_SR                                                  */
25595   GPIO_ALTPADCFGJ_PAD39_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25596 } GPIO_ALTPADCFGJ_PAD39_SR_Enum;
25597 
25598 /* ===========================================  GPIO ALTPADCFGJ PAD38_SR [20..20]  =========================================== */
25599 typedef enum {                                  /*!< GPIO_ALTPADCFGJ_PAD38_SR                                                  */
25600   GPIO_ALTPADCFGJ_PAD38_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25601 } GPIO_ALTPADCFGJ_PAD38_SR_Enum;
25602 
25603 /* ===========================================  GPIO ALTPADCFGJ PAD37_SR [12..12]  =========================================== */
25604 typedef enum {                                  /*!< GPIO_ALTPADCFGJ_PAD37_SR                                                  */
25605   GPIO_ALTPADCFGJ_PAD37_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25606 } GPIO_ALTPADCFGJ_PAD37_SR_Enum;
25607 
25608 /* ============================================  GPIO ALTPADCFGJ PAD36_SR [4..4]  ============================================ */
25609 typedef enum {                                  /*!< GPIO_ALTPADCFGJ_PAD36_SR                                                  */
25610   GPIO_ALTPADCFGJ_PAD36_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25611 } GPIO_ALTPADCFGJ_PAD36_SR_Enum;
25612 
25613 /* ======================================================  ALTPADCFGK  ======================================================= */
25614 /* ===========================================  GPIO ALTPADCFGK PAD43_SR [28..28]  =========================================== */
25615 typedef enum {                                  /*!< GPIO_ALTPADCFGK_PAD43_SR                                                  */
25616   GPIO_ALTPADCFGK_PAD43_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25617 } GPIO_ALTPADCFGK_PAD43_SR_Enum;
25618 
25619 /* ===========================================  GPIO ALTPADCFGK PAD42_SR [20..20]  =========================================== */
25620 typedef enum {                                  /*!< GPIO_ALTPADCFGK_PAD42_SR                                                  */
25621   GPIO_ALTPADCFGK_PAD42_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25622 } GPIO_ALTPADCFGK_PAD42_SR_Enum;
25623 
25624 /* ===========================================  GPIO ALTPADCFGK PAD41_SR [12..12]  =========================================== */
25625 typedef enum {                                  /*!< GPIO_ALTPADCFGK_PAD41_SR                                                  */
25626   GPIO_ALTPADCFGK_PAD41_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25627 } GPIO_ALTPADCFGK_PAD41_SR_Enum;
25628 
25629 /* ============================================  GPIO ALTPADCFGK PAD40_SR [4..4]  ============================================ */
25630 typedef enum {                                  /*!< GPIO_ALTPADCFGK_PAD40_SR                                                  */
25631   GPIO_ALTPADCFGK_PAD40_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25632 } GPIO_ALTPADCFGK_PAD40_SR_Enum;
25633 
25634 /* ======================================================  ALTPADCFGL  ======================================================= */
25635 /* ===========================================  GPIO ALTPADCFGL PAD47_SR [28..28]  =========================================== */
25636 typedef enum {                                  /*!< GPIO_ALTPADCFGL_PAD47_SR                                                  */
25637   GPIO_ALTPADCFGL_PAD47_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25638 } GPIO_ALTPADCFGL_PAD47_SR_Enum;
25639 
25640 /* ===========================================  GPIO ALTPADCFGL PAD46_SR [20..20]  =========================================== */
25641 typedef enum {                                  /*!< GPIO_ALTPADCFGL_PAD46_SR                                                  */
25642   GPIO_ALTPADCFGL_PAD46_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25643 } GPIO_ALTPADCFGL_PAD46_SR_Enum;
25644 
25645 /* ===========================================  GPIO ALTPADCFGL PAD45_SR [12..12]  =========================================== */
25646 typedef enum {                                  /*!< GPIO_ALTPADCFGL_PAD45_SR                                                  */
25647   GPIO_ALTPADCFGL_PAD45_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25648 } GPIO_ALTPADCFGL_PAD45_SR_Enum;
25649 
25650 /* ============================================  GPIO ALTPADCFGL PAD44_SR [4..4]  ============================================ */
25651 typedef enum {                                  /*!< GPIO_ALTPADCFGL_PAD44_SR                                                  */
25652   GPIO_ALTPADCFGL_PAD44_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25653 } GPIO_ALTPADCFGL_PAD44_SR_Enum;
25654 
25655 /* ======================================================  ALTPADCFGM  ======================================================= */
25656 /* ===========================================  GPIO ALTPADCFGM PAD51_SR [28..28]  =========================================== */
25657 typedef enum {                                  /*!< GPIO_ALTPADCFGM_PAD51_SR                                                  */
25658   GPIO_ALTPADCFGM_PAD51_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25659 } GPIO_ALTPADCFGM_PAD51_SR_Enum;
25660 
25661 /* ===========================================  GPIO ALTPADCFGM PAD50_SR [20..20]  =========================================== */
25662 typedef enum {                                  /*!< GPIO_ALTPADCFGM_PAD50_SR                                                  */
25663   GPIO_ALTPADCFGM_PAD50_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25664 } GPIO_ALTPADCFGM_PAD50_SR_Enum;
25665 
25666 /* ===========================================  GPIO ALTPADCFGM PAD49_SR [12..12]  =========================================== */
25667 typedef enum {                                  /*!< GPIO_ALTPADCFGM_PAD49_SR                                                  */
25668   GPIO_ALTPADCFGM_PAD49_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25669 } GPIO_ALTPADCFGM_PAD49_SR_Enum;
25670 
25671 /* ============================================  GPIO ALTPADCFGM PAD48_SR [4..4]  ============================================ */
25672 typedef enum {                                  /*!< GPIO_ALTPADCFGM_PAD48_SR                                                  */
25673   GPIO_ALTPADCFGM_PAD48_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25674 } GPIO_ALTPADCFGM_PAD48_SR_Enum;
25675 
25676 /* ======================================================  ALTPADCFGN  ======================================================= */
25677 /* ===========================================  GPIO ALTPADCFGN PAD55_SR [28..28]  =========================================== */
25678 typedef enum {                                  /*!< GPIO_ALTPADCFGN_PAD55_SR                                                  */
25679   GPIO_ALTPADCFGN_PAD55_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25680 } GPIO_ALTPADCFGN_PAD55_SR_Enum;
25681 
25682 /* ===========================================  GPIO ALTPADCFGN PAD54_SR [20..20]  =========================================== */
25683 typedef enum {                                  /*!< GPIO_ALTPADCFGN_PAD54_SR                                                  */
25684   GPIO_ALTPADCFGN_PAD54_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25685 } GPIO_ALTPADCFGN_PAD54_SR_Enum;
25686 
25687 /* ===========================================  GPIO ALTPADCFGN PAD53_SR [12..12]  =========================================== */
25688 typedef enum {                                  /*!< GPIO_ALTPADCFGN_PAD53_SR                                                  */
25689   GPIO_ALTPADCFGN_PAD53_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25690 } GPIO_ALTPADCFGN_PAD53_SR_Enum;
25691 
25692 /* ============================================  GPIO ALTPADCFGN PAD52_SR [4..4]  ============================================ */
25693 typedef enum {                                  /*!< GPIO_ALTPADCFGN_PAD52_SR                                                  */
25694   GPIO_ALTPADCFGN_PAD52_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25695 } GPIO_ALTPADCFGN_PAD52_SR_Enum;
25696 
25697 /* ======================================================  ALTPADCFGO  ======================================================= */
25698 /* ===========================================  GPIO ALTPADCFGO PAD59_SR [28..28]  =========================================== */
25699 typedef enum {                                  /*!< GPIO_ALTPADCFGO_PAD59_SR                                                  */
25700   GPIO_ALTPADCFGO_PAD59_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25701 } GPIO_ALTPADCFGO_PAD59_SR_Enum;
25702 
25703 /* ===========================================  GPIO ALTPADCFGO PAD58_SR [20..20]  =========================================== */
25704 typedef enum {                                  /*!< GPIO_ALTPADCFGO_PAD58_SR                                                  */
25705   GPIO_ALTPADCFGO_PAD58_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25706 } GPIO_ALTPADCFGO_PAD58_SR_Enum;
25707 
25708 /* ===========================================  GPIO ALTPADCFGO PAD57_SR [12..12]  =========================================== */
25709 typedef enum {                                  /*!< GPIO_ALTPADCFGO_PAD57_SR                                                  */
25710   GPIO_ALTPADCFGO_PAD57_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25711 } GPIO_ALTPADCFGO_PAD57_SR_Enum;
25712 
25713 /* ============================================  GPIO ALTPADCFGO PAD56_SR [4..4]  ============================================ */
25714 typedef enum {                                  /*!< GPIO_ALTPADCFGO_PAD56_SR                                                  */
25715   GPIO_ALTPADCFGO_PAD56_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25716 } GPIO_ALTPADCFGO_PAD56_SR_Enum;
25717 
25718 /* ======================================================  ALTPADCFGP  ======================================================= */
25719 /* ===========================================  GPIO ALTPADCFGP PAD63_SR [28..28]  =========================================== */
25720 typedef enum {                                  /*!< GPIO_ALTPADCFGP_PAD63_SR                                                  */
25721   GPIO_ALTPADCFGP_PAD63_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25722 } GPIO_ALTPADCFGP_PAD63_SR_Enum;
25723 
25724 /* ===========================================  GPIO ALTPADCFGP PAD62_SR [20..20]  =========================================== */
25725 typedef enum {                                  /*!< GPIO_ALTPADCFGP_PAD62_SR                                                  */
25726   GPIO_ALTPADCFGP_PAD62_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25727 } GPIO_ALTPADCFGP_PAD62_SR_Enum;
25728 
25729 /* ===========================================  GPIO ALTPADCFGP PAD61_SR [12..12]  =========================================== */
25730 typedef enum {                                  /*!< GPIO_ALTPADCFGP_PAD61_SR                                                  */
25731   GPIO_ALTPADCFGP_PAD61_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25732 } GPIO_ALTPADCFGP_PAD61_SR_Enum;
25733 
25734 /* ============================================  GPIO ALTPADCFGP PAD60_SR [4..4]  ============================================ */
25735 typedef enum {                                  /*!< GPIO_ALTPADCFGP_PAD60_SR                                                  */
25736   GPIO_ALTPADCFGP_PAD60_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25737 } GPIO_ALTPADCFGP_PAD60_SR_Enum;
25738 
25739 /* ======================================================  ALTPADCFGQ  ======================================================= */
25740 /* ===========================================  GPIO ALTPADCFGQ PAD67_SR [28..28]  =========================================== */
25741 typedef enum {                                  /*!< GPIO_ALTPADCFGQ_PAD67_SR                                                  */
25742   GPIO_ALTPADCFGQ_PAD67_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25743 } GPIO_ALTPADCFGQ_PAD67_SR_Enum;
25744 
25745 /* ===========================================  GPIO ALTPADCFGQ PAD66_SR [20..20]  =========================================== */
25746 typedef enum {                                  /*!< GPIO_ALTPADCFGQ_PAD66_SR                                                  */
25747   GPIO_ALTPADCFGQ_PAD66_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25748 } GPIO_ALTPADCFGQ_PAD66_SR_Enum;
25749 
25750 /* ===========================================  GPIO ALTPADCFGQ PAD65_SR [12..12]  =========================================== */
25751 typedef enum {                                  /*!< GPIO_ALTPADCFGQ_PAD65_SR                                                  */
25752   GPIO_ALTPADCFGQ_PAD65_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25753 } GPIO_ALTPADCFGQ_PAD65_SR_Enum;
25754 
25755 /* ============================================  GPIO ALTPADCFGQ PAD64_SR [4..4]  ============================================ */
25756 typedef enum {                                  /*!< GPIO_ALTPADCFGQ_PAD64_SR                                                  */
25757   GPIO_ALTPADCFGQ_PAD64_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25758 } GPIO_ALTPADCFGQ_PAD64_SR_Enum;
25759 
25760 /* ======================================================  ALTPADCFGR  ======================================================= */
25761 /* ===========================================  GPIO ALTPADCFGR PAD71_SR [28..28]  =========================================== */
25762 typedef enum {                                  /*!< GPIO_ALTPADCFGR_PAD71_SR                                                  */
25763   GPIO_ALTPADCFGR_PAD71_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25764 } GPIO_ALTPADCFGR_PAD71_SR_Enum;
25765 
25766 /* ===========================================  GPIO ALTPADCFGR PAD70_SR [20..20]  =========================================== */
25767 typedef enum {                                  /*!< GPIO_ALTPADCFGR_PAD70_SR                                                  */
25768   GPIO_ALTPADCFGR_PAD70_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25769 } GPIO_ALTPADCFGR_PAD70_SR_Enum;
25770 
25771 /* ===========================================  GPIO ALTPADCFGR PAD69_SR [12..12]  =========================================== */
25772 typedef enum {                                  /*!< GPIO_ALTPADCFGR_PAD69_SR                                                  */
25773   GPIO_ALTPADCFGR_PAD69_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25774 } GPIO_ALTPADCFGR_PAD69_SR_Enum;
25775 
25776 /* ============================================  GPIO ALTPADCFGR PAD68_SR [4..4]  ============================================ */
25777 typedef enum {                                  /*!< GPIO_ALTPADCFGR_PAD68_SR                                                  */
25778   GPIO_ALTPADCFGR_PAD68_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25779 } GPIO_ALTPADCFGR_PAD68_SR_Enum;
25780 
25781 /* ======================================================  ALTPADCFGS  ======================================================= */
25782 /* ===========================================  GPIO ALTPADCFGS PAD73_SR [12..12]  =========================================== */
25783 typedef enum {                                  /*!< GPIO_ALTPADCFGS_PAD73_SR                                                  */
25784   GPIO_ALTPADCFGS_PAD73_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25785 } GPIO_ALTPADCFGS_PAD73_SR_Enum;
25786 
25787 /* ============================================  GPIO ALTPADCFGS PAD72_SR [4..4]  ============================================ */
25788 typedef enum {                                  /*!< GPIO_ALTPADCFGS_PAD72_SR                                                  */
25789   GPIO_ALTPADCFGS_PAD72_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
25790 } GPIO_ALTPADCFGS_PAD72_SR_Enum;
25791 
25792 /* =========================================================  SCDET  ========================================================= */
25793 /* ========================================================  CTENCFG  ======================================================== */
25794 /* ==============================================  GPIO CTENCFG EN31 [31..31]  =============================================== */
25795 typedef enum {                                  /*!< GPIO_CTENCFG_EN31                                                         */
25796   GPIO_CTENCFG_EN31_DIS                = 1,     /*!< DIS : Disable CT31 for output                                             */
25797   GPIO_CTENCFG_EN31_EN                 = 0,     /*!< EN : Enable CT31 for output                                               */
25798 } GPIO_CTENCFG_EN31_Enum;
25799 
25800 /* ==============================================  GPIO CTENCFG EN30 [30..30]  =============================================== */
25801 typedef enum {                                  /*!< GPIO_CTENCFG_EN30                                                         */
25802   GPIO_CTENCFG_EN30_DIS                = 1,     /*!< DIS : Disable CT30 for output                                             */
25803   GPIO_CTENCFG_EN30_EN                 = 0,     /*!< EN : Enable CT30 for output                                               */
25804 } GPIO_CTENCFG_EN30_Enum;
25805 
25806 /* ==============================================  GPIO CTENCFG EN29 [29..29]  =============================================== */
25807 typedef enum {                                  /*!< GPIO_CTENCFG_EN29                                                         */
25808   GPIO_CTENCFG_EN29_DIS                = 1,     /*!< DIS : Disable CT29 for output                                             */
25809   GPIO_CTENCFG_EN29_EN                 = 0,     /*!< EN : Enable CT29 for output                                               */
25810 } GPIO_CTENCFG_EN29_Enum;
25811 
25812 /* ==============================================  GPIO CTENCFG EN28 [28..28]  =============================================== */
25813 typedef enum {                                  /*!< GPIO_CTENCFG_EN28                                                         */
25814   GPIO_CTENCFG_EN28_DIS                = 1,     /*!< DIS : Disable CT28 for output                                             */
25815   GPIO_CTENCFG_EN28_EN                 = 0,     /*!< EN : Enable CT28 for output                                               */
25816 } GPIO_CTENCFG_EN28_Enum;
25817 
25818 /* ==============================================  GPIO CTENCFG EN27 [27..27]  =============================================== */
25819 typedef enum {                                  /*!< GPIO_CTENCFG_EN27                                                         */
25820   GPIO_CTENCFG_EN27_DIS                = 1,     /*!< DIS : Disable CT27 for output                                             */
25821   GPIO_CTENCFG_EN27_EN                 = 0,     /*!< EN : Enable CT27 for output                                               */
25822 } GPIO_CTENCFG_EN27_Enum;
25823 
25824 /* ==============================================  GPIO CTENCFG EN26 [26..26]  =============================================== */
25825 typedef enum {                                  /*!< GPIO_CTENCFG_EN26                                                         */
25826   GPIO_CTENCFG_EN26_DIS                = 1,     /*!< DIS : Disable CT26 for output                                             */
25827   GPIO_CTENCFG_EN26_EN                 = 0,     /*!< EN : Enable CT26 for output                                               */
25828 } GPIO_CTENCFG_EN26_Enum;
25829 
25830 /* ==============================================  GPIO CTENCFG EN25 [25..25]  =============================================== */
25831 typedef enum {                                  /*!< GPIO_CTENCFG_EN25                                                         */
25832   GPIO_CTENCFG_EN25_DIS                = 1,     /*!< DIS : Disable CT25 for output                                             */
25833   GPIO_CTENCFG_EN25_EN                 = 0,     /*!< EN : Enable CT25 for output                                               */
25834 } GPIO_CTENCFG_EN25_Enum;
25835 
25836 /* ==============================================  GPIO CTENCFG EN24 [24..24]  =============================================== */
25837 typedef enum {                                  /*!< GPIO_CTENCFG_EN24                                                         */
25838   GPIO_CTENCFG_EN24_DIS                = 1,     /*!< DIS : Disable CT24 for output                                             */
25839   GPIO_CTENCFG_EN24_EN                 = 0,     /*!< EN : Enable CT24 for output                                               */
25840 } GPIO_CTENCFG_EN24_Enum;
25841 
25842 /* ==============================================  GPIO CTENCFG EN23 [23..23]  =============================================== */
25843 typedef enum {                                  /*!< GPIO_CTENCFG_EN23                                                         */
25844   GPIO_CTENCFG_EN23_DIS                = 1,     /*!< DIS : Disable CT23 for output                                             */
25845   GPIO_CTENCFG_EN23_EN                 = 0,     /*!< EN : Enable CT23 for output                                               */
25846 } GPIO_CTENCFG_EN23_Enum;
25847 
25848 /* ==============================================  GPIO CTENCFG EN22 [22..22]  =============================================== */
25849 typedef enum {                                  /*!< GPIO_CTENCFG_EN22                                                         */
25850   GPIO_CTENCFG_EN22_DIS                = 1,     /*!< DIS : Disable CT22 for output                                             */
25851   GPIO_CTENCFG_EN22_EN                 = 0,     /*!< EN : Enable CT22 for output                                               */
25852 } GPIO_CTENCFG_EN22_Enum;
25853 
25854 /* ==============================================  GPIO CTENCFG EN21 [21..21]  =============================================== */
25855 typedef enum {                                  /*!< GPIO_CTENCFG_EN21                                                         */
25856   GPIO_CTENCFG_EN21_DIS                = 1,     /*!< DIS : Disable CT21 for output                                             */
25857   GPIO_CTENCFG_EN21_EN                 = 0,     /*!< EN : Enable CT21 for output                                               */
25858 } GPIO_CTENCFG_EN21_Enum;
25859 
25860 /* ==============================================  GPIO CTENCFG EN20 [20..20]  =============================================== */
25861 typedef enum {                                  /*!< GPIO_CTENCFG_EN20                                                         */
25862   GPIO_CTENCFG_EN20_DIS                = 1,     /*!< DIS : Disable CT20 for output                                             */
25863   GPIO_CTENCFG_EN20_EN                 = 0,     /*!< EN : Enable CT20 for output                                               */
25864 } GPIO_CTENCFG_EN20_Enum;
25865 
25866 /* ==============================================  GPIO CTENCFG EN19 [19..19]  =============================================== */
25867 typedef enum {                                  /*!< GPIO_CTENCFG_EN19                                                         */
25868   GPIO_CTENCFG_EN19_DIS                = 1,     /*!< DIS : Disable CT19 for output                                             */
25869   GPIO_CTENCFG_EN19_EN                 = 0,     /*!< EN : Enable CT19 for output                                               */
25870 } GPIO_CTENCFG_EN19_Enum;
25871 
25872 /* ==============================================  GPIO CTENCFG EN18 [18..18]  =============================================== */
25873 typedef enum {                                  /*!< GPIO_CTENCFG_EN18                                                         */
25874   GPIO_CTENCFG_EN18_DIS                = 1,     /*!< DIS : Disable CT18 for output                                             */
25875   GPIO_CTENCFG_EN18_EN                 = 0,     /*!< EN : Enable CT18 for output                                               */
25876 } GPIO_CTENCFG_EN18_Enum;
25877 
25878 /* ==============================================  GPIO CTENCFG EN17 [17..17]  =============================================== */
25879 typedef enum {                                  /*!< GPIO_CTENCFG_EN17                                                         */
25880   GPIO_CTENCFG_EN17_DIS                = 1,     /*!< DIS : Disable CT17 for output                                             */
25881   GPIO_CTENCFG_EN17_EN                 = 0,     /*!< EN : Enable CT17 for output                                               */
25882 } GPIO_CTENCFG_EN17_Enum;
25883 
25884 /* ==============================================  GPIO CTENCFG EN16 [16..16]  =============================================== */
25885 typedef enum {                                  /*!< GPIO_CTENCFG_EN16                                                         */
25886   GPIO_CTENCFG_EN16_DIS                = 1,     /*!< DIS : Disable CT16 for output                                             */
25887   GPIO_CTENCFG_EN16_EN                 = 0,     /*!< EN : Enable CT16 for output                                               */
25888 } GPIO_CTENCFG_EN16_Enum;
25889 
25890 /* ==============================================  GPIO CTENCFG EN15 [15..15]  =============================================== */
25891 typedef enum {                                  /*!< GPIO_CTENCFG_EN15                                                         */
25892   GPIO_CTENCFG_EN15_DIS                = 1,     /*!< DIS : Disable CT15 for output                                             */
25893   GPIO_CTENCFG_EN15_EN                 = 0,     /*!< EN : Enable CT15 for output                                               */
25894 } GPIO_CTENCFG_EN15_Enum;
25895 
25896 /* ==============================================  GPIO CTENCFG EN14 [14..14]  =============================================== */
25897 typedef enum {                                  /*!< GPIO_CTENCFG_EN14                                                         */
25898   GPIO_CTENCFG_EN14_DIS                = 1,     /*!< DIS : Disable CT14 for output                                             */
25899   GPIO_CTENCFG_EN14_EN                 = 0,     /*!< EN : Enable CT14 for output                                               */
25900 } GPIO_CTENCFG_EN14_Enum;
25901 
25902 /* ==============================================  GPIO CTENCFG EN13 [13..13]  =============================================== */
25903 typedef enum {                                  /*!< GPIO_CTENCFG_EN13                                                         */
25904   GPIO_CTENCFG_EN13_DIS                = 1,     /*!< DIS : Disable CT13 for output                                             */
25905   GPIO_CTENCFG_EN13_EN                 = 0,     /*!< EN : Enable CT13 for output                                               */
25906 } GPIO_CTENCFG_EN13_Enum;
25907 
25908 /* ==============================================  GPIO CTENCFG EN12 [12..12]  =============================================== */
25909 typedef enum {                                  /*!< GPIO_CTENCFG_EN12                                                         */
25910   GPIO_CTENCFG_EN12_DIS                = 1,     /*!< DIS : Disable CT12 for output                                             */
25911   GPIO_CTENCFG_EN12_EN                 = 0,     /*!< EN : Enable CT12 for output                                               */
25912 } GPIO_CTENCFG_EN12_Enum;
25913 
25914 /* ==============================================  GPIO CTENCFG EN11 [11..11]  =============================================== */
25915 typedef enum {                                  /*!< GPIO_CTENCFG_EN11                                                         */
25916   GPIO_CTENCFG_EN11_DIS                = 1,     /*!< DIS : Disable CT11 for output                                             */
25917   GPIO_CTENCFG_EN11_EN                 = 0,     /*!< EN : Enable CT11 for output                                               */
25918 } GPIO_CTENCFG_EN11_Enum;
25919 
25920 /* ==============================================  GPIO CTENCFG EN10 [10..10]  =============================================== */
25921 typedef enum {                                  /*!< GPIO_CTENCFG_EN10                                                         */
25922   GPIO_CTENCFG_EN10_DIS                = 1,     /*!< DIS : Disable CT10 for output                                             */
25923   GPIO_CTENCFG_EN10_EN                 = 0,     /*!< EN : Enable CT10 for output                                               */
25924 } GPIO_CTENCFG_EN10_Enum;
25925 
25926 /* ================================================  GPIO CTENCFG EN9 [9..9]  ================================================ */
25927 typedef enum {                                  /*!< GPIO_CTENCFG_EN9                                                          */
25928   GPIO_CTENCFG_EN9_DIS                 = 0,     /*!< DIS : Disable CT9 for output                                              */
25929 } GPIO_CTENCFG_EN9_Enum;
25930 
25931 /* ================================================  GPIO CTENCFG EN8 [8..8]  ================================================ */
25932 typedef enum {                                  /*!< GPIO_CTENCFG_EN8                                                          */
25933   GPIO_CTENCFG_EN8_DIS                 = 1,     /*!< DIS : Disable CT8 for output                                              */
25934   GPIO_CTENCFG_EN8_EN                  = 0,     /*!< EN : Enable CT8 for output                                                */
25935 } GPIO_CTENCFG_EN8_Enum;
25936 
25937 /* ================================================  GPIO CTENCFG EN7 [7..7]  ================================================ */
25938 typedef enum {                                  /*!< GPIO_CTENCFG_EN7                                                          */
25939   GPIO_CTENCFG_EN7_DIS                 = 1,     /*!< DIS : Disable CT7 for output                                              */
25940   GPIO_CTENCFG_EN7_EN                  = 0,     /*!< EN : Enable CT7 for output                                                */
25941 } GPIO_CTENCFG_EN7_Enum;
25942 
25943 /* ================================================  GPIO CTENCFG EN6 [6..6]  ================================================ */
25944 typedef enum {                                  /*!< GPIO_CTENCFG_EN6                                                          */
25945   GPIO_CTENCFG_EN6_DIS                 = 1,     /*!< DIS : Disable CT6 for output                                              */
25946   GPIO_CTENCFG_EN6_EN                  = 0,     /*!< EN : Enable CT6 for output                                                */
25947 } GPIO_CTENCFG_EN6_Enum;
25948 
25949 /* ================================================  GPIO CTENCFG EN5 [5..5]  ================================================ */
25950 typedef enum {                                  /*!< GPIO_CTENCFG_EN5                                                          */
25951   GPIO_CTENCFG_EN5_DIS                 = 1,     /*!< DIS : Disable CT5 for output                                              */
25952   GPIO_CTENCFG_EN5_EN                  = 0,     /*!< EN : Enable CT5 for output                                                */
25953 } GPIO_CTENCFG_EN5_Enum;
25954 
25955 /* ================================================  GPIO CTENCFG EN4 [4..4]  ================================================ */
25956 typedef enum {                                  /*!< GPIO_CTENCFG_EN4                                                          */
25957   GPIO_CTENCFG_EN4_DIS                 = 1,     /*!< DIS : Disable CT4 for output                                              */
25958   GPIO_CTENCFG_EN4_EN                  = 0,     /*!< EN : Enable CT4 for output                                                */
25959 } GPIO_CTENCFG_EN4_Enum;
25960 
25961 /* ================================================  GPIO CTENCFG EN3 [3..3]  ================================================ */
25962 typedef enum {                                  /*!< GPIO_CTENCFG_EN3                                                          */
25963   GPIO_CTENCFG_EN3_DIS                 = 1,     /*!< DIS : Disable CT3 for output                                              */
25964   GPIO_CTENCFG_EN3_EN                  = 0,     /*!< EN : Enable CT3 for output                                                */
25965 } GPIO_CTENCFG_EN3_Enum;
25966 
25967 /* ================================================  GPIO CTENCFG EN2 [2..2]  ================================================ */
25968 typedef enum {                                  /*!< GPIO_CTENCFG_EN2                                                          */
25969   GPIO_CTENCFG_EN2_DIS                 = 1,     /*!< DIS : Disable CT2 for output                                              */
25970   GPIO_CTENCFG_EN2_EN                  = 0,     /*!< EN : Enable CT2 for output                                                */
25971 } GPIO_CTENCFG_EN2_Enum;
25972 
25973 /* ================================================  GPIO CTENCFG EN1 [1..1]  ================================================ */
25974 typedef enum {                                  /*!< GPIO_CTENCFG_EN1                                                          */
25975   GPIO_CTENCFG_EN1_DIS                 = 1,     /*!< DIS : Disable CT1 for output                                              */
25976   GPIO_CTENCFG_EN1_EN                  = 0,     /*!< EN : Enable CT1 for output                                                */
25977 } GPIO_CTENCFG_EN1_Enum;
25978 
25979 /* ================================================  GPIO CTENCFG EN0 [0..0]  ================================================ */
25980 typedef enum {                                  /*!< GPIO_CTENCFG_EN0                                                          */
25981   GPIO_CTENCFG_EN0_DIS                 = 1,     /*!< DIS : Disable CT0 for output                                              */
25982   GPIO_CTENCFG_EN0_EN                  = 0,     /*!< EN : Enable CT0 for output                                                */
25983 } GPIO_CTENCFG_EN0_Enum;
25984 
25985 /* ========================================================  INT0EN  ========================================================= */
25986 /* =======================================================  INT0STAT  ======================================================== */
25987 /* ========================================================  INT0CLR  ======================================================== */
25988 /* ========================================================  INT0SET  ======================================================== */
25989 /* ========================================================  INT1EN  ========================================================= */
25990 /* =======================================================  INT1STAT  ======================================================== */
25991 /* ========================================================  INT1CLR  ======================================================== */
25992 /* ========================================================  INT1SET  ======================================================== */
25993 /* ========================================================  INT2EN  ========================================================= */
25994 /* =======================================================  INT2STAT  ======================================================== */
25995 /* ========================================================  INT2CLR  ======================================================== */
25996 /* ========================================================  INT2SET  ======================================================== */
25997 /* ========================================================  DBGCTRL  ======================================================== */
25998 
25999 
26000 /* =========================================================================================================================== */
26001 /* ================                                           IOM0                                            ================ */
26002 /* =========================================================================================================================== */
26003 
26004 /* =========================================================  FIFO  ========================================================== */
26005 /* ========================================================  FIFOPTR  ======================================================== */
26006 /* ========================================================  FIFOTHR  ======================================================== */
26007 /* ========================================================  FIFOPOP  ======================================================== */
26008 /* =======================================================  FIFOPUSH  ======================================================== */
26009 /* =======================================================  FIFOCTRL  ======================================================== */
26010 /* ========================================================  FIFOLOC  ======================================================== */
26011 /* =========================================================  INTEN  ========================================================= */
26012 /* ========================================================  INTSTAT  ======================================================== */
26013 /* ========================================================  INTCLR  ========================================================= */
26014 /* ========================================================  INTSET  ========================================================= */
26015 /* ========================================================  CLKCFG  ========================================================= */
26016 /* ==============================================  IOM0 CLKCFG DIVEN [12..12]  =============================================== */
26017 typedef enum {                                  /*!< IOM0_CLKCFG_DIVEN                                                         */
26018   IOM0_CLKCFG_DIVEN_DIS                = 0,     /*!< DIS : Disable TOTPER division.                                            */
26019   IOM0_CLKCFG_DIVEN_EN                 = 1,     /*!< EN : Enable TOTPER division.                                              */
26020 } IOM0_CLKCFG_DIVEN_Enum;
26021 
26022 /* ===============================================  IOM0 CLKCFG DIV3 [11..11]  =============================================== */
26023 typedef enum {                                  /*!< IOM0_CLKCFG_DIV3                                                          */
26024   IOM0_CLKCFG_DIV3_DIS                 = 0,     /*!< DIS : Select divide by 1.                                                 */
26025   IOM0_CLKCFG_DIV3_EN                  = 1,     /*!< EN : Select divide by 3.                                                  */
26026 } IOM0_CLKCFG_DIV3_Enum;
26027 
26028 /* ===============================================  IOM0 CLKCFG FSEL [8..10]  ================================================ */
26029 typedef enum {                                  /*!< IOM0_CLKCFG_FSEL                                                          */
26030   IOM0_CLKCFG_FSEL_MIN_PWR             = 0,     /*!< MIN_PWR : Selects the minimum power clock. This setting should
26031                                                      be used whenever the IOM is not active.                                   */
26032   IOM0_CLKCFG_FSEL_HFRC                = 1,     /*!< HFRC : Selects the HFRC as the input clock.                               */
26033   IOM0_CLKCFG_FSEL_HFRC_DIV2           = 2,     /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock.                      */
26034   IOM0_CLKCFG_FSEL_HFRC_DIV4           = 3,     /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock.                      */
26035   IOM0_CLKCFG_FSEL_HFRC_DIV8           = 4,     /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock.                      */
26036   IOM0_CLKCFG_FSEL_HFRC_DIV16          = 5,     /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock.                    */
26037   IOM0_CLKCFG_FSEL_HFRC_DIV32          = 6,     /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock.                    */
26038   IOM0_CLKCFG_FSEL_HFRC_DIV64          = 7,     /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock.                    */
26039 } IOM0_CLKCFG_FSEL_Enum;
26040 
26041 /* ======================================================  SUBMODCTRL  ======================================================= */
26042 /* ===========================================  IOM0 SUBMODCTRL SMOD1TYPE [5..7]  ============================================ */
26043 typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD1TYPE                                                 */
26044   IOM0_SUBMODCTRL_SMOD1TYPE_MSPI       = 0,     /*!< MSPI : SPI Master submodule                                               */
26045   IOM0_SUBMODCTRL_SMOD1TYPE_I2C_MASTER = 1,     /*!< I2C_MASTER : MI2C submodule                                               */
26046   IOM0_SUBMODCTRL_SMOD1TYPE_SSPI       = 2,     /*!< SSPI : SPI Slave submodule                                                */
26047   IOM0_SUBMODCTRL_SMOD1TYPE_SI2C       = 3,     /*!< SI2C : I2C Slave submodule                                                */
26048   IOM0_SUBMODCTRL_SMOD1TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
26049 } IOM0_SUBMODCTRL_SMOD1TYPE_Enum;
26050 
26051 /* ===========================================  IOM0 SUBMODCTRL SMOD0TYPE [1..3]  ============================================ */
26052 typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD0TYPE                                                 */
26053   IOM0_SUBMODCTRL_SMOD0TYPE_SPI_MASTER = 0,     /*!< SPI_MASTER : MSPI submodule                                               */
26054   IOM0_SUBMODCTRL_SMOD0TYPE_I2C_MASTER = 1,     /*!< I2C_MASTER : I2C Master submodule                                         */
26055   IOM0_SUBMODCTRL_SMOD0TYPE_SSPI       = 2,     /*!< SSPI : SPI Slave submodule                                                */
26056   IOM0_SUBMODCTRL_SMOD0TYPE_SI2C       = 3,     /*!< SI2C : I2C Slave submodule                                                */
26057   IOM0_SUBMODCTRL_SMOD0TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
26058 } IOM0_SUBMODCTRL_SMOD0TYPE_Enum;
26059 
26060 /* ==========================================================  CMD  ========================================================== */
26061 /* ==================================================  IOM0 CMD CMD [0..4]  ================================================== */
26062 typedef enum {                                  /*!< IOM0_CMD_CMD                                                              */
26063   IOM0_CMD_CMD_WRITE                   = 1,     /*!< WRITE : Write command using count of offset bytes specified
26064                                                      in the OFFSETCNT field                                                    */
26065   IOM0_CMD_CMD_READ                    = 2,     /*!< READ : Read command using count of offset bytes specified in
26066                                                      the OFFSETCNT field                                                       */
26067   IOM0_CMD_CMD_TMW                     = 3,     /*!< TMW : SPI only. Test mode to do constant write operations. Useful
26068                                                      for debug and power measurements. Will continually send
26069                                                      data in OFFSET field                                                      */
26070   IOM0_CMD_CMD_TMR                     = 4,     /*!< TMR : SPI Only. Test mode to do constant read operations. Useful
26071                                                      for debug and power measurements. Will continually read
26072                                                      data from external input                                                  */
26073 } IOM0_CMD_CMD_Enum;
26074 
26075 /* ==========================================================  DCX  ========================================================== */
26076 /* =================================================  IOM0 DCX DCXEN [4..4]  ================================================= */
26077 typedef enum {                                  /*!< IOM0_DCX_DCXEN                                                            */
26078   IOM0_DCX_DCXEN_EN                    = 1,     /*!< EN : Enable DCX.                                                          */
26079   IOM0_DCX_DCXEN_DIS                   = 0,     /*!< DIS : Disable DCX.                                                        */
26080 } IOM0_DCX_DCXEN_Enum;
26081 
26082 /* =======================================================  OFFSETHI  ======================================================== */
26083 /* ========================================================  CMDSTAT  ======================================================== */
26084 /* ==============================================  IOM0 CMDSTAT CMDSTAT [5..7]  ============================================== */
26085 typedef enum {                                  /*!< IOM0_CMDSTAT_CMDSTAT                                                      */
26086   IOM0_CMDSTAT_CMDSTAT_ERR             = 1,     /*!< ERR : Error encountered with command                                      */
26087   IOM0_CMDSTAT_CMDSTAT_ACTIVE          = 2,     /*!< ACTIVE : Actively processing command                                      */
26088   IOM0_CMDSTAT_CMDSTAT_IDLE            = 4,     /*!< IDLE : Idle state, no active command, no error                            */
26089   IOM0_CMDSTAT_CMDSTAT_WAIT            = 6,     /*!< WAIT : Command in progress, but waiting on data from host                 */
26090 } IOM0_CMDSTAT_CMDSTAT_Enum;
26091 
26092 /* =======================================================  DMATRIGEN  ======================================================= */
26093 /* ======================================================  DMATRIGSTAT  ====================================================== */
26094 /* ========================================================  DMACFG  ========================================================= */
26095 /* ==============================================  IOM0 DMACFG DPWROFF [9..9]  =============================================== */
26096 typedef enum {                                  /*!< IOM0_DMACFG_DPWROFF                                                       */
26097   IOM0_DMACFG_DPWROFF_DIS              = 0,     /*!< DIS : Power off disabled                                                  */
26098   IOM0_DMACFG_DPWROFF_EN               = 1,     /*!< EN : Power off enabled                                                    */
26099 } IOM0_DMACFG_DPWROFF_Enum;
26100 
26101 /* ===============================================  IOM0 DMACFG DMAPRI [8..8]  =============================================== */
26102 typedef enum {                                  /*!< IOM0_DMACFG_DMAPRI                                                        */
26103   IOM0_DMACFG_DMAPRI_LOW               = 0,     /*!< LOW : Low Priority (service as best effort)                               */
26104   IOM0_DMACFG_DMAPRI_HIGH              = 1,     /*!< HIGH : High Priority (service immediately)                                */
26105 } IOM0_DMACFG_DMAPRI_Enum;
26106 
26107 /* ===============================================  IOM0 DMACFG DMADIR [1..1]  =============================================== */
26108 typedef enum {                                  /*!< IOM0_DMACFG_DMADIR                                                        */
26109   IOM0_DMACFG_DMADIR_P2M               = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when
26110                                                      doing IOM read operations, i.e., reading data from external
26111                                                      devices.                                                                  */
26112   IOM0_DMACFG_DMADIR_M2P               = 1,     /*!< M2P : Memory to Peripheral transaction. To be set when doing
26113                                                      IOM write operations, i.e., writing data to external devices.             */
26114 } IOM0_DMACFG_DMADIR_Enum;
26115 
26116 /* ===============================================  IOM0 DMACFG DMAEN [0..0]  ================================================ */
26117 typedef enum {                                  /*!< IOM0_DMACFG_DMAEN                                                         */
26118   IOM0_DMACFG_DMAEN_DIS                = 0,     /*!< DIS : Disable DMA Function                                                */
26119   IOM0_DMACFG_DMAEN_EN                 = 1,     /*!< EN : Enable DMA Function                                                  */
26120 } IOM0_DMACFG_DMAEN_Enum;
26121 
26122 /* ======================================================  DMATOTCOUNT  ====================================================== */
26123 /* ======================================================  DMATARGADDR  ====================================================== */
26124 /* ========================================================  DMASTAT  ======================================================== */
26125 /* =========================================================  CQCFG  ========================================================= */
26126 /* =============================================  IOM0 CQCFG MSPIFLGSEL [2..3]  ============================================== */
26127 typedef enum {                                  /*!< IOM0_CQCFG_MSPIFLGSEL                                                     */
26128   IOM0_CQCFG_MSPIFLGSEL_MSPI0FLGSEL    = 0,     /*!< MSPI0FLGSEL : Selects MPSI0 as source of signals used in CGFLAG[11:8].    */
26129   IOM0_CQCFG_MSPIFLGSEL_MSPI1FLGSEL    = 1,     /*!< MSPI1FLGSEL : Selects MPSI1 as source of signals used in CGFLAG[11:8].    */
26130   IOM0_CQCFG_MSPIFLGSEL_MSPI2FLGSEL    = 2,     /*!< MSPI2FLGSEL : Selects MPSI2 as source of signals used in CGFLAG[11:8].    */
26131 } IOM0_CQCFG_MSPIFLGSEL_Enum;
26132 
26133 /* ================================================  IOM0 CQCFG CQPRI [1..1]  ================================================ */
26134 typedef enum {                                  /*!< IOM0_CQCFG_CQPRI                                                          */
26135   IOM0_CQCFG_CQPRI_LOW                 = 0,     /*!< LOW : Low Priority (service as best effort)                               */
26136   IOM0_CQCFG_CQPRI_HIGH                = 1,     /*!< HIGH : High Priority (service immediately)                                */
26137 } IOM0_CQCFG_CQPRI_Enum;
26138 
26139 /* ================================================  IOM0 CQCFG CQEN [0..0]  ================================================= */
26140 typedef enum {                                  /*!< IOM0_CQCFG_CQEN                                                           */
26141   IOM0_CQCFG_CQEN_DIS                  = 0,     /*!< DIS : Disable CQ Function                                                 */
26142   IOM0_CQCFG_CQEN_EN                   = 1,     /*!< EN : Enable CQ Function                                                   */
26143 } IOM0_CQCFG_CQEN_Enum;
26144 
26145 /* ========================================================  CQADDR  ========================================================= */
26146 /* ========================================================  CQSTAT  ========================================================= */
26147 /* ========================================================  CQFLAGS  ======================================================== */
26148 /* ======================================================  CQSETCLEAR  ======================================================= */
26149 /* =======================================================  CQPAUSEEN  ======================================================= */
26150 /* =============================================  IOM0 CQPAUSEEN CQPEN [0..15]  ============================================== */
26151 typedef enum {                                  /*!< IOM0_CQPAUSEEN_CQPEN                                                      */
26152   IOM0_CQPAUSEEN_CQPEN_IDXEQ           = 32768, /*!< IDXEQ : Pauses the command queue when the current index matches
26153                                                      the last index                                                            */
26154   IOM0_CQPAUSEEN_CQPEN_BLEXOREN        = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with
26155                                                      SWFLAG4 is '1'                                                            */
26156   IOM0_CQPAUSEEN_CQPEN_IOMXOREN        = 8192,  /*!< IOMXOREN : Pause command queue when input IOM bit XORed with
26157                                                      SWFLAG3 is '1'                                                            */
26158   IOM0_CQPAUSEEN_CQPEN_GPIOXOREN       = 4096,  /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed
26159                                                      with SWFLAG2 is '1'                                                       */
26160   IOM0_CQPAUSEEN_CQPEN_MSPI1XNOREN     = 2048,  /*!< MSPI1XNOREN : Pause command queue when selected MSPI input bit
26161                                                      1 (buffer 1 ready) XNORed with SWFLAG1 is '1'. MSPI used
26162                                                      is selected in CQCFG.MSPIFLGSEL field.                                    */
26163   IOM0_CQPAUSEEN_CQPEN_MSPI0XNOREN     = 1024,  /*!< MSPI0XNOREN : Pause command queue when selected MSPI input bit
26164                                                      0 (buffer 0 ready) XNORed with SWFLAG1 is '1'. MSPI used
26165                                                      is selected in CQCFG.MSPIFLGSEL field.                                    */
26166   IOM0_CQPAUSEEN_CQPEN_MSPI1XOREN      = 512,   /*!< MSPI1XOREN : Pause command queue when selected MSPI input bit
26167                                                      1 (buffer 1 ready) XORed with SWFLAG1 is '1'. MSPI used
26168                                                      is selected in CQCFG.MSPIFLGSEL field.                                    */
26169   IOM0_CQPAUSEEN_CQPEN_MSPI0XOREN      = 256,   /*!< MSPI0XOREN : Pause command queue when selected MSPI input bit
26170                                                      0 (buffer 0 ready) XORed with SWFLAG1 is '1'. MSPI used
26171                                                      is selected in CQCFG.MSPIFLGSEL field.                                    */
26172   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7       = 128,   /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7
26173                                                      is '1'.                                                                   */
26174   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6       = 64,    /*!< SWFLAGEN6 : Pause the command queue when software flag bit 6
26175                                                      is '1'                                                                    */
26176   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5       = 32,    /*!< SWFLAGEN5 : Pause the command queue when software flag bit 5
26177                                                      is '1'                                                                    */
26178   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN4       = 16,    /*!< SWFLAGEN4 : Pause the command queue when software flag bit 4
26179                                                      is '1'                                                                    */
26180   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN3       = 8,     /*!< SWFLAGEN3 : Pause the command queue when software flag bit 3
26181                                                      is '1'                                                                    */
26182   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN2       = 4,     /*!< SWFLAGEN2 : Pause the command queue when software flag bit 2
26183                                                      is '1'                                                                    */
26184   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN1       = 2,     /*!< SWFLAGEN1 : Pause the command queue when software flag bit 1
26185                                                      is '1'                                                                    */
26186   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN0       = 1,     /*!< SWFLAGEN0 : Pause the command queue when software flag bit 0
26187                                                      is '1'                                                                    */
26188 } IOM0_CQPAUSEEN_CQPEN_Enum;
26189 
26190 /* =======================================================  CQCURIDX  ======================================================== */
26191 /* =======================================================  CQENDIDX  ======================================================== */
26192 /* ========================================================  STATUS  ========================================================= */
26193 /* ===============================================  IOM0 STATUS IDLEST [2..2]  =============================================== */
26194 typedef enum {                                  /*!< IOM0_STATUS_IDLEST                                                        */
26195   IOM0_STATUS_IDLEST_IDLE              = 1,     /*!< IDLE : The I/O state machine is in the idle state.                        */
26196 } IOM0_STATUS_IDLEST_Enum;
26197 
26198 /* ===============================================  IOM0 STATUS CMDACT [1..1]  =============================================== */
26199 typedef enum {                                  /*!< IOM0_STATUS_CMDACT                                                        */
26200   IOM0_STATUS_CMDACT_ACTIVE            = 1,     /*!< ACTIVE : An I/O command is active. Indicates the active module
26201                                                      has an active command and is processing this. De-asserted
26202                                                      when the command is completed.                                            */
26203 } IOM0_STATUS_CMDACT_Enum;
26204 
26205 /* ================================================  IOM0 STATUS ERR [0..0]  ================================================= */
26206 typedef enum {                                  /*!< IOM0_STATUS_ERR                                                           */
26207   IOM0_STATUS_ERR_ERROR                = 1,     /*!< ERROR : Bit has been deprecated and will always return 0.                 */
26208 } IOM0_STATUS_ERR_Enum;
26209 
26210 /* ========================================================  MSPICFG  ======================================================== */
26211 /* =============================================  IOM0 MSPICFG SPILSB [23..23]  ============================================== */
26212 typedef enum {                                  /*!< IOM0_MSPICFG_SPILSB                                                       */
26213   IOM0_MSPICFG_SPILSB_MSB              = 0,     /*!< MSB : Send and receive MSB bit first                                      */
26214   IOM0_MSPICFG_SPILSB_LSB              = 1,     /*!< LSB : Send and receive LSB bit first                                      */
26215 } IOM0_MSPICFG_SPILSB_Enum;
26216 
26217 /* =============================================  IOM0 MSPICFG RDFCPOL [22..22]  ============================================= */
26218 typedef enum {                                  /*!< IOM0_MSPICFG_RDFCPOL                                                      */
26219   IOM0_MSPICFG_RDFCPOL_HIGH            = 0,     /*!< HIGH : Flow control signal high creates flow control.                     */
26220   IOM0_MSPICFG_RDFCPOL_LOW             = 1,     /*!< LOW : Flow control signal low creates flow control.                       */
26221 } IOM0_MSPICFG_RDFCPOL_Enum;
26222 
26223 /* =============================================  IOM0 MSPICFG WTFCPOL [21..21]  ============================================= */
26224 typedef enum {                                  /*!< IOM0_MSPICFG_WTFCPOL                                                      */
26225   IOM0_MSPICFG_WTFCPOL_HIGH            = 0,     /*!< HIGH : Flow control signal high(1) creates flow control and
26226                                                      byte transfers will stop until the flow control signal
26227                                                      goes low.                                                                 */
26228   IOM0_MSPICFG_WTFCPOL_LOW             = 1,     /*!< LOW : Flow control signal low(0) creates flow control and byte
26229                                                      transfers will stop until the flow control signal goes
26230                                                      high(1).                                                                  */
26231 } IOM0_MSPICFG_WTFCPOL_Enum;
26232 
26233 /* =============================================  IOM0 MSPICFG WTFCIRQ [20..20]  ============================================= */
26234 typedef enum {                                  /*!< IOM0_MSPICFG_WTFCIRQ                                                      */
26235   IOM0_MSPICFG_WTFCIRQ_MISO            = 0,     /*!< MISO : MISO is used as the write mode flow control signal.                */
26236   IOM0_MSPICFG_WTFCIRQ_IRQ             = 1,     /*!< IRQ : IRQ is used as the write mode flow control signal.                  */
26237 } IOM0_MSPICFG_WTFCIRQ_Enum;
26238 
26239 /* =============================================  IOM0 MSPICFG MOSIINV [18..18]  ============================================= */
26240 typedef enum {                                  /*!< IOM0_MSPICFG_MOSIINV                                                      */
26241   IOM0_MSPICFG_MOSIINV_NORMAL          = 0,     /*!< NORMAL : MOSI is set to 0 in read mode and 1 in write mode.               */
26242   IOM0_MSPICFG_MOSIINV_INVERT          = 1,     /*!< INVERT : MOSI is set to 1 in read mode and 0 in write mode.               */
26243 } IOM0_MSPICFG_MOSIINV_Enum;
26244 
26245 /* ==============================================  IOM0 MSPICFG RDFC [17..17]  =============================================== */
26246 typedef enum {                                  /*!< IOM0_MSPICFG_RDFC                                                         */
26247   IOM0_MSPICFG_RDFC_DIS                = 0,     /*!< DIS : Read mode flow control disabled.                                    */
26248   IOM0_MSPICFG_RDFC_EN                 = 1,     /*!< EN : Read mode flow control enabled.                                      */
26249 } IOM0_MSPICFG_RDFC_Enum;
26250 
26251 /* ==============================================  IOM0 MSPICFG WTFC [16..16]  =============================================== */
26252 typedef enum {                                  /*!< IOM0_MSPICFG_WTFC                                                         */
26253   IOM0_MSPICFG_WTFC_DIS                = 0,     /*!< DIS : Write mode flow control disabled.                                   */
26254   IOM0_MSPICFG_WTFC_EN                 = 1,     /*!< EN : Write mode flow control enabled.                                     */
26255 } IOM0_MSPICFG_WTFC_Enum;
26256 
26257 /* ===============================================  IOM0 MSPICFG SPHA [1..1]  ================================================ */
26258 typedef enum {                                  /*!< IOM0_MSPICFG_SPHA                                                         */
26259   IOM0_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0,    /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge.           */
26260   IOM0_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1,   /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock
26261                                                      edge.                                                                     */
26262 } IOM0_MSPICFG_SPHA_Enum;
26263 
26264 /* ===============================================  IOM0 MSPICFG SPOL [0..0]  ================================================ */
26265 typedef enum {                                  /*!< IOM0_MSPICFG_SPOL                                                         */
26266   IOM0_MSPICFG_SPOL_CLK_BASE_0         = 0,     /*!< CLK_BASE_0 : The base value of the clock is 0.                            */
26267   IOM0_MSPICFG_SPOL_CLK_BASE_1         = 1,     /*!< CLK_BASE_1 : The base value of the clock is 1.                            */
26268 } IOM0_MSPICFG_SPOL_Enum;
26269 
26270 /* ========================================================  MI2CCFG  ======================================================== */
26271 /* ===============================================  IOM0 MI2CCFG ARBEN [2..2]  =============================================== */
26272 typedef enum {                                  /*!< IOM0_MI2CCFG_ARBEN                                                        */
26273   IOM0_MI2CCFG_ARBEN_ARBEN             = 1,     /*!< ARBEN : Enable multi-master bus arbitration support for this
26274                                                      I2C master                                                                */
26275   IOM0_MI2CCFG_ARBEN_ARBDIS            = 0,     /*!< ARBDIS : Disable multi-master bus arbitration support for this
26276                                                      I2C master                                                                */
26277 } IOM0_MI2CCFG_ARBEN_Enum;
26278 
26279 /* ==============================================  IOM0 MI2CCFG I2CLSB [1..1]  =============================================== */
26280 typedef enum {                                  /*!< IOM0_MI2CCFG_I2CLSB                                                       */
26281   IOM0_MI2CCFG_I2CLSB_MSBFIRST         = 0,     /*!< MSBFIRST : Byte data is transmitted MSB first onto the bus/read
26282                                                      from the bus                                                              */
26283   IOM0_MI2CCFG_I2CLSB_LSBFIRST         = 1,     /*!< LSBFIRST : Byte data is transmitted LSB first onto the bus/read
26284                                                      from the bus                                                              */
26285 } IOM0_MI2CCFG_I2CLSB_Enum;
26286 
26287 /* ==============================================  IOM0 MI2CCFG ADDRSZ [0..0]  =============================================== */
26288 typedef enum {                                  /*!< IOM0_MI2CCFG_ADDRSZ                                                       */
26289   IOM0_MI2CCFG_ADDRSZ_ADDRSZ7          = 0,     /*!< ADDRSZ7 : Use 7-bit addressing for I2C master transactions                */
26290   IOM0_MI2CCFG_ADDRSZ_ADDRSZ10         = 1,     /*!< ADDRSZ10 : Use 10-bit addressing for I2C master transactions              */
26291 } IOM0_MI2CCFG_ADDRSZ_Enum;
26292 
26293 /* ========================================================  DEVCFG  ========================================================= */
26294 /* ========================================================  IOMDBG  ========================================================= */
26295 
26296 
26297 /* =========================================================================================================================== */
26298 /* ================                                          IOSLAVE                                          ================ */
26299 /* =========================================================================================================================== */
26300 
26301 /* ========================================================  FIFOPTR  ======================================================== */
26302 /* ========================================================  FIFOCFG  ======================================================== */
26303 /* ========================================================  FIFOTHR  ======================================================== */
26304 /* =========================================================  FUPD  ========================================================== */
26305 /* ========================================================  FIFOCTR  ======================================================== */
26306 /* ========================================================  FIFOINC  ======================================================== */
26307 /* ==========================================================  CFG  ========================================================== */
26308 /* ==============================================  IOSLAVE CFG IFCEN [31..31]  =============================================== */
26309 typedef enum {                                  /*!< IOSLAVE_CFG_IFCEN                                                         */
26310   IOSLAVE_CFG_IFCEN_DIS                = 0,     /*!< DIS : Disable the IOSLAVE                                                 */
26311   IOSLAVE_CFG_IFCEN_EN                 = 1,     /*!< EN : Enable the IOSLAVE                                                   */
26312 } IOSLAVE_CFG_IFCEN_Enum;
26313 
26314 /* ==============================================  IOSLAVE CFG STARTRD [4..4]  =============================================== */
26315 typedef enum {                                  /*!< IOSLAVE_CFG_STARTRD                                                       */
26316   IOSLAVE_CFG_STARTRD_LATE             = 0,     /*!< LATE : Initiate I/O RAM read late in each transferred byte.               */
26317   IOSLAVE_CFG_STARTRD_EARLY            = 1,     /*!< EARLY : Initiate I/O RAM read early in each transferred byte.             */
26318 } IOSLAVE_CFG_STARTRD_Enum;
26319 
26320 /* ================================================  IOSLAVE CFG LSB [2..2]  ================================================= */
26321 typedef enum {                                  /*!< IOSLAVE_CFG_LSB                                                           */
26322   IOSLAVE_CFG_LSB_MSB_FIRST            = 0,     /*!< MSB_FIRST : Data is assumed to be sent and received with MSB
26323                                                      first.                                                                    */
26324   IOSLAVE_CFG_LSB_LSB_FIRST            = 1,     /*!< LSB_FIRST : Data is assumed to be sent and received with LSB
26325                                                      first.                                                                    */
26326 } IOSLAVE_CFG_LSB_Enum;
26327 
26328 /* ================================================  IOSLAVE CFG SPOL [1..1]  ================================================ */
26329 typedef enum {                                  /*!< IOSLAVE_CFG_SPOL                                                          */
26330   IOSLAVE_CFG_SPOL_SPI_MODES_0_3       = 0,     /*!< SPI_MODES_0_3 : Polarity 0, handles SPI modes 0 and 3.                    */
26331   IOSLAVE_CFG_SPOL_SPI_MODES_1_2       = 1,     /*!< SPI_MODES_1_2 : Polarity 1, handles SPI modes 1 and 2.                    */
26332 } IOSLAVE_CFG_SPOL_Enum;
26333 
26334 /* ===============================================  IOSLAVE CFG IFCSEL [0..0]  =============================================== */
26335 typedef enum {                                  /*!< IOSLAVE_CFG_IFCSEL                                                        */
26336   IOSLAVE_CFG_IFCSEL_I2C               = 0,     /*!< I2C : Selects I2C interface for the IO Slave.                             */
26337   IOSLAVE_CFG_IFCSEL_SPI               = 1,     /*!< SPI : Selects SPI interface for the IO Slave.                             */
26338 } IOSLAVE_CFG_IFCSEL_Enum;
26339 
26340 /* =========================================================  PRENC  ========================================================= */
26341 /* =======================================================  IOINTCTL  ======================================================== */
26342 /* ========================================================  GENADD  ========================================================= */
26343 /* =========================================================  INTEN  ========================================================= */
26344 /* ========================================================  INTSTAT  ======================================================== */
26345 /* ========================================================  INTCLR  ========================================================= */
26346 /* ========================================================  INTSET  ========================================================= */
26347 /* ======================================================  REGACCINTEN  ====================================================== */
26348 /* =====================================================  REGACCINTSTAT  ===================================================== */
26349 /* =====================================================  REGACCINTCLR  ====================================================== */
26350 /* =====================================================  REGACCINTSET  ====================================================== */
26351 
26352 
26353 /* =========================================================================================================================== */
26354 /* ================                                          MCUCTRL                                          ================ */
26355 /* =========================================================================================================================== */
26356 
26357 /* ========================================================  CHIPPN  ========================================================= */
26358 /* ============================================  MCUCTRL CHIPPN PARTNUM [0..31]  ============================================= */
26359 typedef enum {                                  /*!< MCUCTRL_CHIPPN_PARTNUM                                                    */
26360   MCUCTRL_CHIPPN_PARTNUM_APOLLO3P      = 0x07000000,/*!< APOLLO3P : Apollo3 Blue Plus part number is 0x07xxxxxx.                */
26361   MCUCTRL_CHIPPN_PARTNUM_APOLLO3       = 0x06000000,/*!< APOLLO3 : Apollo3 Blue part number is 0x06xxxxxx.                      */
26362   MCUCTRL_CHIPPN_PARTNUM_APOLLO2       = 0x03000000,/*!< APOLLO2 : Apollo2 part number is 0x03xxxxxx.                            */
26363   MCUCTRL_CHIPPN_PARTNUM_APOLLO        = 0x01000000,/*!< APOLLO : Apollo part number is 0x01xxxxxx.                              */
26364   MCUCTRL_CHIPPN_PARTNUM_PN_M          = 0xFF000000,/*!< PN_M : Mask for the part number field.                                 */
26365   MCUCTRL_CHIPPN_PARTNUM_PN_S          = 24,    /*!< PN_S : Bit position for the part number field.                            */
26366   MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M   = 0x00F00000,/*!< FLASHSIZE_M : Mask for the FLASH_SIZE field.Values:0: 16KB1:
26367                                                      32KB2: 64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 2MB8: 1.5MB                   */
26368   MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S   = 20,    /*!< FLASHSIZE_S : Bit position for the FLASH_SIZE field.                      */
26369   MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M    = 0xF0000,/*!< SRAMSIZE_M : Mask for the SRAM_SIZE field.Values:0: 16KB1: 32KB2:
26370                                                      64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 384KB8: 768KB                        */
26371   MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S    = 16,    /*!< SRAMSIZE_S : Bit position for the SRAM_SIZE field.                        */
26372   MCUCTRL_CHIPPN_PARTNUM_REV_M         = 0xFF00,/*!< REV_M : Mask for the revision field. Bits [15:12] are major
26373                                                      rev, [11:8] are minor rev.Values:0: Major Rev A, Minor
26374                                                      Rev 01: Major Rev B, Minor Rev 1                                          */
26375   MCUCTRL_CHIPPN_PARTNUM_REV_S         = 8,     /*!< REV_S : Bit position for the revision field.                              */
26376   MCUCTRL_CHIPPN_PARTNUM_PKG_M         = 0xC0,  /*!< PKG_M : Mask for the package field.Values:0: SIP1: QFN2: BGA3:
26377                                                      CSP                                                                       */
26378   MCUCTRL_CHIPPN_PARTNUM_PKG_S         = 6,     /*!< PKG_S : Bit position for the package field.                               */
26379   MCUCTRL_CHIPPN_PARTNUM_PINS_M        = 0x38,  /*!< PINS_M : Mask for the pins field.Values:0: 25 pins1: 49 pins2:
26380                                                      64 pins3: 81 pins                                                         */
26381   MCUCTRL_CHIPPN_PARTNUM_PINS_S        = 3,     /*!< PINS_S : Bit position for the pins field.                                 */
26382   MCUCTRL_CHIPPN_PARTNUM_TEMP_S        = 1,     /*!< TEMP_S : Bit position for the temperature field.                          */
26383 } MCUCTRL_CHIPPN_PARTNUM_Enum;
26384 
26385 /* ========================================================  CHIPID0  ======================================================== */
26386 /* ============================================  MCUCTRL CHIPID0 CHIPID0 [0..31]  ============================================ */
26387 typedef enum {                                  /*!< MCUCTRL_CHIPID0_CHIPID0                                                   */
26388   MCUCTRL_CHIPID0_CHIPID0_APOLLO3      = 0,     /*!< APOLLO3 : Apollo3 Blue Plus CHIPID0.                                      */
26389 } MCUCTRL_CHIPID0_CHIPID0_Enum;
26390 
26391 /* ========================================================  CHIPID1  ======================================================== */
26392 /* ============================================  MCUCTRL CHIPID1 CHIPID1 [0..31]  ============================================ */
26393 typedef enum {                                  /*!< MCUCTRL_CHIPID1_CHIPID1                                                   */
26394   MCUCTRL_CHIPID1_CHIPID1_APOLLO3      = 0,     /*!< APOLLO3 : Apollo3 Blue Plus CHIPID1.                                      */
26395 } MCUCTRL_CHIPID1_CHIPID1_Enum;
26396 
26397 /* ========================================================  CHIPREV  ======================================================== */
26398 /* =============================================  MCUCTRL CHIPREV REVMAJ [4..7]  ============================================= */
26399 typedef enum {                                  /*!< MCUCTRL_CHIPREV_REVMAJ                                                    */
26400   MCUCTRL_CHIPREV_REVMAJ_C             = 3,     /*!< C : Apollo3 Blue Plus                                                     */
26401   MCUCTRL_CHIPREV_REVMAJ_B             = 2,     /*!< B : Apollo3 Blue revision B                                               */
26402   MCUCTRL_CHIPREV_REVMAJ_A             = 1,     /*!< A : Apollo3 Blue revision A                                               */
26403 } MCUCTRL_CHIPREV_REVMAJ_Enum;
26404 
26405 /* =============================================  MCUCTRL CHIPREV REVMIN [0..3]  ============================================= */
26406 typedef enum {                                  /*!< MCUCTRL_CHIPREV_REVMIN                                                    */
26407   MCUCTRL_CHIPREV_REVMIN_REV1          = 2,     /*!< REV1 : Apollo3 Blue minor rev 1.                                          */
26408   MCUCTRL_CHIPREV_REVMIN_REV0          = 1,     /*!< REV0 : Apollo3 Blue minor rev 0. Minor revision value, succeeding
26409                                                      minor revisions will increment from this value.                           */
26410 } MCUCTRL_CHIPREV_REVMIN_Enum;
26411 
26412 /* =======================================================  VENDORID  ======================================================== */
26413 /* ===========================================  MCUCTRL VENDORID VENDORID [0..31]  =========================================== */
26414 typedef enum {                                  /*!< MCUCTRL_VENDORID_VENDORID                                                 */
26415   MCUCTRL_VENDORID_VENDORID_AMBIQ      = 1095582289,/*!< AMBIQ : Ambiq Vendor ID 'AMBQ'                                        */
26416 } MCUCTRL_VENDORID_VENDORID_Enum;
26417 
26418 /* ==========================================================  SKU  ========================================================== */
26419 /* =====================================================  FEATUREENABLE  ===================================================== */
26420 /* ========================================  MCUCTRL FEATUREENABLE BURSTAVAIL [6..6]  ======================================== */
26421 typedef enum {                                  /*!< MCUCTRL_FEATUREENABLE_BURSTAVAIL                                          */
26422   MCUCTRL_FEATUREENABLE_BURSTAVAIL_AVAIL = 1,   /*!< AVAIL : Burst functionality available                                     */
26423   MCUCTRL_FEATUREENABLE_BURSTAVAIL_NOTAVAIL = 0,/*!< NOTAVAIL : Burst functionality not available                              */
26424 } MCUCTRL_FEATUREENABLE_BURSTAVAIL_Enum;
26425 
26426 /* =========================================  MCUCTRL FEATUREENABLE BURSTREQ [4..4]  ========================================= */
26427 typedef enum {                                  /*!< MCUCTRL_FEATUREENABLE_BURSTREQ                                            */
26428   MCUCTRL_FEATUREENABLE_BURSTREQ_EN    = 1,     /*!< EN : Enable the Burst functionality                                       */
26429   MCUCTRL_FEATUREENABLE_BURSTREQ_DIS   = 0,     /*!< DIS : Disable the Burst functionality                                     */
26430 } MCUCTRL_FEATUREENABLE_BURSTREQ_Enum;
26431 
26432 /* =========================================  MCUCTRL FEATUREENABLE BLEAVAIL [2..2]  ========================================= */
26433 typedef enum {                                  /*!< MCUCTRL_FEATUREENABLE_BLEAVAIL                                            */
26434   MCUCTRL_FEATUREENABLE_BLEAVAIL_AVAIL = 1,     /*!< AVAIL : BLE functionality available                                       */
26435   MCUCTRL_FEATUREENABLE_BLEAVAIL_NOTAVAIL = 0,  /*!< NOTAVAIL : BLE functionality not available                                */
26436 } MCUCTRL_FEATUREENABLE_BLEAVAIL_Enum;
26437 
26438 /* ==========================================  MCUCTRL FEATUREENABLE BLEREQ [0..0]  ========================================== */
26439 typedef enum {                                  /*!< MCUCTRL_FEATUREENABLE_BLEREQ                                              */
26440   MCUCTRL_FEATUREENABLE_BLEREQ_EN      = 1,     /*!< EN : Enable the BLE functionality                                         */
26441   MCUCTRL_FEATUREENABLE_BLEREQ_DIS     = 0,     /*!< DIS : Disable the BLE functionality                                       */
26442 } MCUCTRL_FEATUREENABLE_BLEREQ_Enum;
26443 
26444 /* =======================================================  DEBUGGER  ======================================================== */
26445 /* =================================================  DMASRAMWRITEPROTECT2  ================================================== */
26446 /* ========================================================  VRCTRL1  ======================================================== */
26447 /* ========================================================  VRCTRL2  ======================================================== */
26448 /* ========================================================  LDOREG1  ======================================================== */
26449 /* ========================================================  LDOREG2  ======================================================== */
26450 /* =======================================================  ADCPWRDLY  ======================================================= */
26451 /* ========================================================  ADCCAL  ========================================================= */
26452 /* ==========================================  MCUCTRL ADCCAL ADCCALIBRATED [1..1]  ========================================== */
26453 typedef enum {                                  /*!< MCUCTRL_ADCCAL_ADCCALIBRATED                                              */
26454   MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE   = 0,     /*!< FALSE : ADC is not calibrated                                             */
26455   MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE    = 1,     /*!< TRUE : ADC is calibrated                                                  */
26456 } MCUCTRL_ADCCAL_ADCCALIBRATED_Enum;
26457 
26458 /* ===========================================  MCUCTRL ADCCAL CALONPWRUP [0..0]  ============================================ */
26459 typedef enum {                                  /*!< MCUCTRL_ADCCAL_CALONPWRUP                                                 */
26460   MCUCTRL_ADCCAL_CALONPWRUP_DIS        = 0,     /*!< DIS : Disable automatic calibration on initial power up                   */
26461   MCUCTRL_ADCCAL_CALONPWRUP_EN         = 1,     /*!< EN : Enable automatic calibration on initial power up                     */
26462 } MCUCTRL_ADCCAL_CALONPWRUP_Enum;
26463 
26464 /* ======================================================  ADCBATTLOAD  ====================================================== */
26465 /* ==========================================  MCUCTRL ADCBATTLOAD BATTLOAD [0..0]  ========================================== */
26466 typedef enum {                                  /*!< MCUCTRL_ADCBATTLOAD_BATTLOAD                                              */
26467   MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS     = 0,     /*!< DIS : Battery load is disconnected                                        */
26468   MCUCTRL_ADCBATTLOAD_BATTLOAD_EN      = 1,     /*!< EN : Battery load is enabled                                              */
26469 } MCUCTRL_ADCBATTLOAD_BATTLOAD_Enum;
26470 
26471 /* ========================================================  ADCTRIM  ======================================================== */
26472 /* ======================================================  ADCREFCOMP  ======================================================= */
26473 /* =======================================================  XTALCTRL  ======================================================== */
26474 /* ==========================================  MCUCTRL XTALCTRL PWDBODXTAL [5..5]  =========================================== */
26475 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_PWDBODXTAL                                               */
26476   MCUCTRL_XTALCTRL_PWDBODXTAL_PWRUPBOD = 0,     /*!< PWRUPBOD : Power up XTAL on BOD.                                          */
26477   MCUCTRL_XTALCTRL_PWDBODXTAL_PWRDNBOD = 1,     /*!< PWRDNBOD : Power down XTAL on BOD.                                        */
26478 } MCUCTRL_XTALCTRL_PWDBODXTAL_Enum;
26479 
26480 /* =========================================  MCUCTRL XTALCTRL PDNBCMPRXTAL [4..4]  ========================================== */
26481 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_PDNBCMPRXTAL                                             */
26482   MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRUPCOMP = 1,  /*!< PWRUPCOMP : Power up XTAL oscillator comparator.                          */
26483   MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRDNCOMP = 0,  /*!< PWRDNCOMP : Power down XTAL oscillator comparator.                        */
26484 } MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Enum;
26485 
26486 /* =========================================  MCUCTRL XTALCTRL PDNBCOREXTAL [3..3]  ========================================== */
26487 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_PDNBCOREXTAL                                             */
26488   MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRUPCORE = 1,  /*!< PWRUPCORE : Power up XTAL oscillator core.                                */
26489   MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRDNCORE = 0,  /*!< PWRDNCORE : Power down XTAL oscillator core.                              */
26490 } MCUCTRL_XTALCTRL_PDNBCOREXTAL_Enum;
26491 
26492 /* ==========================================  MCUCTRL XTALCTRL BYPCMPRXTAL [2..2]  ========================================== */
26493 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_BYPCMPRXTAL                                              */
26494   MCUCTRL_XTALCTRL_BYPCMPRXTAL_USECOMP = 0,     /*!< USECOMP : Use the XTAL oscillator comparator.                             */
26495   MCUCTRL_XTALCTRL_BYPCMPRXTAL_BYPCOMP = 1,     /*!< BYPCOMP : Bypass the XTAL oscillator comparator.                          */
26496 } MCUCTRL_XTALCTRL_BYPCMPRXTAL_Enum;
26497 
26498 /* =========================================  MCUCTRL XTALCTRL FDBKDSBLXTAL [1..1]  ========================================== */
26499 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_FDBKDSBLXTAL                                             */
26500   MCUCTRL_XTALCTRL_FDBKDSBLXTAL_EN     = 0,     /*!< EN : Enable XTAL oscillator comparator.                                   */
26501   MCUCTRL_XTALCTRL_FDBKDSBLXTAL_DIS    = 1,     /*!< DIS : Disable XTAL oscillator comparator.                                 */
26502 } MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Enum;
26503 
26504 /* ============================================  MCUCTRL XTALCTRL XTALSWE [0..0]  ============================================ */
26505 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALSWE                                                  */
26506   MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS = 0,    /*!< OVERRIDE_DIS : XTAL Software Override Disable.                            */
26507   MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN = 1,     /*!< OVERRIDE_EN : XTAL Software Override Enable.                              */
26508 } MCUCTRL_XTALCTRL_XTALSWE_Enum;
26509 
26510 /* ======================================================  XTALGENCTRL  ====================================================== */
26511 /* ==========================================  MCUCTRL XTALGENCTRL ACWARMUP [0..1]  ========================================== */
26512 typedef enum {                                  /*!< MCUCTRL_XTALGENCTRL_ACWARMUP                                              */
26513   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC1    = 0,     /*!< SEC1 : Warm-up period of 1-2 seconds                                      */
26514   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC2    = 1,     /*!< SEC2 : Warm-up period of 2-4 seconds                                      */
26515   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC4    = 2,     /*!< SEC4 : Warm-up period of 4-8 seconds                                      */
26516   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC8    = 3,     /*!< SEC8 : Warm-up period of 8-16 seconds                                     */
26517 } MCUCTRL_XTALGENCTRL_ACWARMUP_Enum;
26518 
26519 /* ======================================================  MISCPWRCTRL  ====================================================== */
26520 /* ======================================  MCUCTRL MISCPWRCTRL VDDRBURSTOVER [17..17]  ======================================= */
26521 typedef enum {                                  /*!< MCUCTRL_MISCPWRCTRL_VDDRBURSTOVER                                         */
26522   MCUCTRL_MISCPWRCTRL_VDDRBURSTOVER_EN = 1,     /*!< EN : Writing a '1' will enable this register to override pwrsw_vddr_burst_en
26523                                                      control signals from pwrctrl to mcu_ctrl                                  */
26524 } MCUCTRL_MISCPWRCTRL_VDDRBURSTOVER_Enum;
26525 
26526 /* ======================================  MCUCTRL MISCPWRCTRL VDDRACTIVEOVER [15..15]  ====================================== */
26527 typedef enum {                                  /*!< MCUCTRL_MISCPWRCTRL_VDDRACTIVEOVER                                        */
26528   MCUCTRL_MISCPWRCTRL_VDDRACTIVEOVER_EN = 1,    /*!< EN : Writing a '1' will enable this register to override pwrsw_vddr_active_en
26529                                                      control signals from pwrctrl to mcu_ctrl                                  */
26530 } MCUCTRL_MISCPWRCTRL_VDDRACTIVEOVER_Enum;
26531 
26532 /* ======================================  MCUCTRL MISCPWRCTRL VDDLHBURSTOVER [13..13]  ====================================== */
26533 typedef enum {                                  /*!< MCUCTRL_MISCPWRCTRL_VDDLHBURSTOVER                                        */
26534   MCUCTRL_MISCPWRCTRL_VDDLHBURSTOVER_EN = 1,    /*!< EN : Writing a '1' will enable this register to override pwrsw_vddlh_burst_en
26535                                                      control signals from pwrctrl to mcu_ctrl                                  */
26536 } MCUCTRL_MISCPWRCTRL_VDDLHBURSTOVER_Enum;
26537 
26538 /* =======================================================  MISCCTRL  ======================================================== */
26539 /* ======================================================  BOOTLOADER  ======================================================= */
26540 /* =======================================  MCUCTRL BOOTLOADER SECBOOTONRST [30..31]  ======================================== */
26541 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOTONRST                                           */
26542   MCUCTRL_BOOTLOADER_SECBOOTONRST_DISABLED = 0, /*!< DISABLED : Secure boot disabled                                           */
26543   MCUCTRL_BOOTLOADER_SECBOOTONRST_ENABLED = 1,  /*!< ENABLED : Secure boot enabled                                             */
26544   MCUCTRL_BOOTLOADER_SECBOOTONRST_ERROR = 2,    /*!< ERROR : Error in secure boot configuration                                */
26545 } MCUCTRL_BOOTLOADER_SECBOOTONRST_Enum;
26546 
26547 /* ==========================================  MCUCTRL BOOTLOADER SECBOOT [28..29]  ========================================== */
26548 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOT                                                */
26549   MCUCTRL_BOOTLOADER_SECBOOT_DISABLED  = 0,     /*!< DISABLED : Secure boot disabled                                           */
26550   MCUCTRL_BOOTLOADER_SECBOOT_ENABLED   = 1,     /*!< ENABLED : Secure boot enabled                                             */
26551   MCUCTRL_BOOTLOADER_SECBOOT_ERROR     = 2,     /*!< ERROR : Error in secure boot configuration                                */
26552 } MCUCTRL_BOOTLOADER_SECBOOT_Enum;
26553 
26554 /* ======================================  MCUCTRL BOOTLOADER SECBOOTFEATURE [26..27]  ======================================= */
26555 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOTFEATURE                                         */
26556   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_DISABLED = 0,/*!< DISABLED : Secure boot disabled                                          */
26557   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ENABLED = 1,/*!< ENABLED : Secure boot enabled                                             */
26558   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ERROR = 2,  /*!< ERROR : Error in secure boot configuration                                */
26559 } MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Enum;
26560 
26561 /* ==========================================  MCUCTRL BOOTLOADER PROTLOCK [2..2]  =========================================== */
26562 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_PROTLOCK                                               */
26563   MCUCTRL_BOOTLOADER_PROTLOCK_LOCK     = 1,     /*!< LOCK : Enable the secure boot lock                                        */
26564 } MCUCTRL_BOOTLOADER_PROTLOCK_Enum;
26565 
26566 /* ===========================================  MCUCTRL BOOTLOADER SBLOCK [1..1]  ============================================ */
26567 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SBLOCK                                                 */
26568   MCUCTRL_BOOTLOADER_SBLOCK_LOCK       = 1,     /*!< LOCK : Enable the secure boot lock                                        */
26569 } MCUCTRL_BOOTLOADER_SBLOCK_Enum;
26570 
26571 /* ========================================  MCUCTRL BOOTLOADER BOOTLOADERLOW [0..0]  ======================================== */
26572 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_BOOTLOADERLOW                                          */
26573   MCUCTRL_BOOTLOADER_BOOTLOADERLOW_ADDR0 = 1,   /*!< ADDR0 : Bootloader code at 0x00000000.                                    */
26574 } MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Enum;
26575 
26576 /* ======================================================  SHADOWVALID  ====================================================== */
26577 /* ========================================  MCUCTRL SHADOWVALID INFO0_VALID [2..2]  ========================================= */
26578 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_INFO0_VALID                                           */
26579   MCUCTRL_SHADOWVALID_INFO0_VALID_VALID = 1,    /*!< VALID : Flash INFO0 (customer) space contains valid data.                 */
26580 } MCUCTRL_SHADOWVALID_INFO0_VALID_Enum;
26581 
26582 /* ==========================================  MCUCTRL SHADOWVALID BLDSLEEP [1..1]  ========================================== */
26583 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_BLDSLEEP                                              */
26584   MCUCTRL_SHADOWVALID_BLDSLEEP_DEEPSLEEP = 1,   /*!< DEEPSLEEP : Bootloader will go to deep sleep if no flash image
26585                                                      loaded                                                                    */
26586 } MCUCTRL_SHADOWVALID_BLDSLEEP_Enum;
26587 
26588 /* ===========================================  MCUCTRL SHADOWVALID VALID [0..0]  ============================================ */
26589 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_VALID                                                 */
26590   MCUCTRL_SHADOWVALID_VALID_VALID      = 1,     /*!< VALID : Flash information space contains valid data.                      */
26591 } MCUCTRL_SHADOWVALID_VALID_Enum;
26592 
26593 /* =======================================================  SCRATCH0  ======================================================== */
26594 /* =======================================================  SCRATCH1  ======================================================== */
26595 /* ====================================================  ICODEFAULTADDR  ===================================================== */
26596 /* ====================================================  DCODEFAULTADDR  ===================================================== */
26597 /* =====================================================  SYSFAULTADDR  ====================================================== */
26598 /* ======================================================  FAULTSTATUS  ====================================================== */
26599 /* ==========================================  MCUCTRL FAULTSTATUS SYSFAULT [2..2]  ========================================== */
26600 typedef enum {                                  /*!< MCUCTRL_FAULTSTATUS_SYSFAULT                                              */
26601   MCUCTRL_FAULTSTATUS_SYSFAULT_NOFAULT = 0,     /*!< NOFAULT : No bus fault has been detected.                                 */
26602   MCUCTRL_FAULTSTATUS_SYSFAULT_FAULT   = 1,     /*!< FAULT : Bus fault detected.                                               */
26603 } MCUCTRL_FAULTSTATUS_SYSFAULT_Enum;
26604 
26605 /* =========================================  MCUCTRL FAULTSTATUS DCODEFAULT [1..1]  ========================================= */
26606 typedef enum {                                  /*!< MCUCTRL_FAULTSTATUS_DCODEFAULT                                            */
26607   MCUCTRL_FAULTSTATUS_DCODEFAULT_NOFAULT = 0,   /*!< NOFAULT : No DCODE fault has been detected.                               */
26608   MCUCTRL_FAULTSTATUS_DCODEFAULT_FAULT = 1,     /*!< FAULT : DCODE fault detected.                                             */
26609 } MCUCTRL_FAULTSTATUS_DCODEFAULT_Enum;
26610 
26611 /* =========================================  MCUCTRL FAULTSTATUS ICODEFAULT [0..0]  ========================================= */
26612 typedef enum {                                  /*!< MCUCTRL_FAULTSTATUS_ICODEFAULT                                            */
26613   MCUCTRL_FAULTSTATUS_ICODEFAULT_NOFAULT = 0,   /*!< NOFAULT : No ICODE fault has been detected.                               */
26614   MCUCTRL_FAULTSTATUS_ICODEFAULT_FAULT = 1,     /*!< FAULT : ICODE fault detected.                                             */
26615 } MCUCTRL_FAULTSTATUS_ICODEFAULT_Enum;
26616 
26617 /* ====================================================  FAULTCAPTUREEN  ===================================================== */
26618 /* =====================================  MCUCTRL FAULTCAPTUREEN FAULTCAPTUREEN [0..0]  ====================================== */
26619 typedef enum {                                  /*!< MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN                                     */
26620   MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_DIS = 0,/*!< DIS : Disable fault capture.                                              */
26621   MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_EN = 1, /*!< EN : Enable fault capture.                                                */
26622 } MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Enum;
26623 
26624 /* =========================================================  DBGR1  ========================================================= */
26625 /* =========================================================  DBGR2  ========================================================= */
26626 /* =======================================================  PMUENABLE  ======================================================= */
26627 /* ============================================  MCUCTRL PMUENABLE ENABLE [0..0]  ============================================ */
26628 typedef enum {                                  /*!< MCUCTRL_PMUENABLE_ENABLE                                                  */
26629   MCUCTRL_PMUENABLE_ENABLE_DIS         = 0,     /*!< DIS : Disable MCU power management.                                       */
26630   MCUCTRL_PMUENABLE_ENABLE_EN          = 1,     /*!< EN : Enable MCU power management.                                         */
26631 } MCUCTRL_PMUENABLE_ENABLE_Enum;
26632 
26633 /* =======================================================  TPIUCTRL  ======================================================== */
26634 /* ============================================  MCUCTRL TPIUCTRL CLKSEL [8..10]  ============================================ */
26635 typedef enum {                                  /*!< MCUCTRL_TPIUCTRL_CLKSEL                                                   */
26636   MCUCTRL_TPIUCTRL_CLKSEL_LOWPWR       = 0,     /*!< LOWPWR : Low power state.                                                 */
26637   MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV2     = 1,     /*!< HFRCDIV2 : Selects HFRC divided by 2 as the source TPIU clock             */
26638   MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV8     = 2,     /*!< HFRCDIV8 : Selects HFRC divided by 8 as the source TPIU clock             */
26639   MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV16    = 3,     /*!< HFRCDIV16 : Selects HFRC divided by 16 as the source TPIU clock           */
26640   MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV32    = 4,     /*!< HFRCDIV32 : Selects HFRC divided by 32 as the source TPIU clock           */
26641 } MCUCTRL_TPIUCTRL_CLKSEL_Enum;
26642 
26643 /* ============================================  MCUCTRL TPIUCTRL ENABLE [0..0]  ============================================= */
26644 typedef enum {                                  /*!< MCUCTRL_TPIUCTRL_ENABLE                                                   */
26645   MCUCTRL_TPIUCTRL_ENABLE_DIS          = 0,     /*!< DIS : Disable the TPIU.                                                   */
26646   MCUCTRL_TPIUCTRL_ENABLE_EN           = 1,     /*!< EN : Enable the TPIU.                                                     */
26647 } MCUCTRL_TPIUCTRL_ENABLE_Enum;
26648 
26649 /* ======================================================  OTAPOINTER  ======================================================= */
26650 /* =======================================================  SRAMMODE  ======================================================== */
26651 /* ======================================================  KEXTCLKSEL  ======================================================= */
26652 /* =========================================  MCUCTRL KEXTCLKSEL KEXTCLKSEL [0..31]  ========================================= */
26653 typedef enum {                                  /*!< MCUCTRL_KEXTCLKSEL_KEXTCLKSEL                                             */
26654   MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Key    = 83,    /*!< Key : Key value to unlock the register.                                   */
26655 } MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Enum;
26656 
26657 /* =======================================================  SIMOBUCK1  ======================================================= */
26658 /* =======================================================  SIMOBUCK2  ======================================================= */
26659 /* =======================================================  SIMOBUCK3  ======================================================= */
26660 /* =======================================================  SIMOBUCK4  ======================================================= */
26661 /* =======================================================  BLEBUCK1  ======================================================== */
26662 /* =======================================================  BLEBUCK2  ======================================================== */
26663 /* ======================================================  FLASHWPROT0  ====================================================== */
26664 /* ======================================================  FLASHWPROT1  ====================================================== */
26665 /* ======================================================  FLASHWPROT2  ====================================================== */
26666 /* ======================================================  FLASHWPROT3  ====================================================== */
26667 /* ======================================================  FLASHRPROT0  ====================================================== */
26668 /* ======================================================  FLASHRPROT1  ====================================================== */
26669 /* ======================================================  FLASHRPROT2  ====================================================== */
26670 /* ======================================================  FLASHRPROT3  ====================================================== */
26671 /* =================================================  DMASRAMWRITEPROTECT0  ================================================== */
26672 /* =================================================  DMASRAMWRITEPROTECT1  ================================================== */
26673 /* ==================================================  DMASRAMREADPROTECT0  ================================================== */
26674 /* ==================================================  DMASRAMREADPROTECT1  ================================================== */
26675 /* ==================================================  DMASRAMREADPROTECT2  ================================================== */
26676 
26677 
26678 /* =========================================================================================================================== */
26679 /* ================                                           MSPI0                                           ================ */
26680 /* =========================================================================================================================== */
26681 
26682 /* =========================================================  CTRL  ========================================================== */
26683 /* ==========================================================  CFG  ========================================================== */
26684 /* ================================================  MSPI0 CFG CPOL [17..17]  ================================================ */
26685 typedef enum {                                  /*!< MSPI0_CFG_CPOL                                                            */
26686   MSPI0_CFG_CPOL_LOW                   = 0,     /*!< LOW : Clock inactive state is low.                                        */
26687   MSPI0_CFG_CPOL_HIGH                  = 1,     /*!< HIGH : Clock inactive state is high.                                      */
26688 } MSPI0_CFG_CPOL_Enum;
26689 
26690 /* ================================================  MSPI0 CFG CPHA [16..16]  ================================================ */
26691 typedef enum {                                  /*!< MSPI0_CFG_CPHA                                                            */
26692   MSPI0_CFG_CPHA_MIDDLE                = 0,     /*!< MIDDLE : Clock toggles in middle of data bit.                             */
26693   MSPI0_CFG_CPHA_START                 = 1,     /*!< START : Clock toggles at start of data bit.                               */
26694 } MSPI0_CFG_CPHA_Enum;
26695 
26696 /* ================================================  MSPI0 CFG ASIZE [4..5]  ================================================= */
26697 typedef enum {                                  /*!< MSPI0_CFG_ASIZE                                                           */
26698   MSPI0_CFG_ASIZE_A1                   = 0,     /*!< A1 : Send one address byte                                                */
26699   MSPI0_CFG_ASIZE_A2                   = 1,     /*!< A2 : Send two address bytes                                               */
26700   MSPI0_CFG_ASIZE_A3                   = 2,     /*!< A3 : Send three address bytes                                             */
26701   MSPI0_CFG_ASIZE_A4                   = 3,     /*!< A4 : Send four address bytes                                              */
26702 } MSPI0_CFG_ASIZE_Enum;
26703 
26704 /* ================================================  MSPI0 CFG DEVCFG [0..3]  ================================================ */
26705 typedef enum {                                  /*!< MSPI0_CFG_DEVCFG                                                          */
26706   MSPI0_CFG_DEVCFG_SERIAL0             = 1,     /*!< SERIAL0 : Single bit SPI flash on chip select 0                           */
26707   MSPI0_CFG_DEVCFG_SERIAL1             = 2,     /*!< SERIAL1 : Single bit SPI flash on chip select 1                           */
26708   MSPI0_CFG_DEVCFG_DUAL0               = 5,     /*!< DUAL0 : Dual SPI flash on chip select 0                                   */
26709   MSPI0_CFG_DEVCFG_DUAL1               = 6,     /*!< DUAL1 : Dual bit SPI flash on chip select 1                               */
26710   MSPI0_CFG_DEVCFG_QUAD0               = 9,     /*!< QUAD0 : Quad SPI flash on chip select 0                                   */
26711   MSPI0_CFG_DEVCFG_QUAD1               = 10,    /*!< QUAD1 : Quad SPI flash on chip select 1                                   */
26712   MSPI0_CFG_DEVCFG_OCTAL0              = 13,    /*!< OCTAL0 : Octal SPI flash on chip select 0                                 */
26713   MSPI0_CFG_DEVCFG_OCTAL1              = 14,    /*!< OCTAL1 : Octal SPI flash on chip select 1                                 */
26714 } MSPI0_CFG_DEVCFG_Enum;
26715 
26716 /* =========================================================  ADDR  ========================================================== */
26717 /* =========================================================  INSTR  ========================================================= */
26718 /* ========================================================  TXFIFO  ========================================================= */
26719 /* ========================================================  RXFIFO  ========================================================= */
26720 /* =======================================================  TXENTRIES  ======================================================= */
26721 /* =======================================================  RXENTRIES  ======================================================= */
26722 /* =======================================================  THRESHOLD  ======================================================= */
26723 /* ========================================================  MSPICFG  ======================================================== */
26724 /* =============================================  MSPI0 MSPICFG CLKDIV [8..13]  ============================================== */
26725 typedef enum {                                  /*!< MSPI0_MSPICFG_CLKDIV                                                      */
26726   MSPI0_MSPICFG_CLKDIV_CLK48           = 1,     /*!< CLK48 : 48 MHz MSPI clock                                                 */
26727   MSPI0_MSPICFG_CLKDIV_CLK24           = 2,     /*!< CLK24 : 24 MHz MSPI clock                                                 */
26728   MSPI0_MSPICFG_CLKDIV_CLK12           = 4,     /*!< CLK12 : 12 MHz MSPI clock                                                 */
26729   MSPI0_MSPICFG_CLKDIV_CLK6            = 8,     /*!< CLK6 : 6 MHz MSPI clock                                                   */
26730   MSPI0_MSPICFG_CLKDIV_CLK3            = 16,    /*!< CLK3 : 3 MHz MSPI clock                                                   */
26731   MSPI0_MSPICFG_CLKDIV_CLK1_5          = 32,    /*!< CLK1_5 : 1.5 MHz MSPI clock                                               */
26732 } MSPI0_MSPICFG_CLKDIV_Enum;
26733 
26734 /* ==============================================  MSPI0 MSPICFG IOMSEL [4..7]  ============================================== */
26735 typedef enum {                                  /*!< MSPI0_MSPICFG_IOMSEL                                                      */
26736   MSPI0_MSPICFG_IOMSEL_IOM0            = 0,     /*!< IOM0 : Select IOM0                                                        */
26737   MSPI0_MSPICFG_IOMSEL_IOM1            = 1,     /*!< IOM1 : Select IOM1                                                        */
26738   MSPI0_MSPICFG_IOMSEL_IOM2            = 2,     /*!< IOM2 : Select IOM2                                                        */
26739   MSPI0_MSPICFG_IOMSEL_IOM3            = 3,     /*!< IOM3 : Select IOM3                                                        */
26740   MSPI0_MSPICFG_IOMSEL_IOM4            = 4,     /*!< IOM4 : Select IOM4                                                        */
26741   MSPI0_MSPICFG_IOMSEL_IOM5            = 5,     /*!< IOM5 : Select IOM5                                                        */
26742   MSPI0_MSPICFG_IOMSEL_MSPI0           = 8,     /*!< MSPI0 : Select MSPI0                                                      */
26743   MSPI0_MSPICFG_IOMSEL_MSPI1           = 9,     /*!< MSPI1 : Select MSPI1                                                      */
26744   MSPI0_MSPICFG_IOMSEL_MSPI2           = 10,    /*!< MSPI2 : Select MSPI2                                                      */
26745   MSPI0_MSPICFG_IOMSEL_DISABLED        = 7,     /*!< DISABLED : No IOM selected. Signals always zero.                          */
26746 } MSPI0_MSPICFG_IOMSEL_Enum;
26747 
26748 /* ==============================================  MSPI0 MSPICFG TXNEG [3..3]  =============================================== */
26749 typedef enum {                                  /*!< MSPI0_MSPICFG_TXNEG                                                       */
26750   MSPI0_MSPICFG_TXNEG_NORMAL           = 0,     /*!< NORMAL : TX launched from posedge internal clock                          */
26751   MSPI0_MSPICFG_TXNEG_NEGEDGE          = 1,     /*!< NEGEDGE : TX data launched from negedge of internal clock                 */
26752 } MSPI0_MSPICFG_TXNEG_Enum;
26753 
26754 /* ==============================================  MSPI0 MSPICFG RXNEG [2..2]  =============================================== */
26755 typedef enum {                                  /*!< MSPI0_MSPICFG_RXNEG                                                       */
26756   MSPI0_MSPICFG_RXNEG_NORMAL           = 0,     /*!< NORMAL : RX data sampled on posedge of internal clock                     */
26757   MSPI0_MSPICFG_RXNEG_NEGEDGE          = 1,     /*!< NEGEDGE : RX data sampled on negedge of internal clock                    */
26758 } MSPI0_MSPICFG_RXNEG_Enum;
26759 
26760 /* ==============================================  MSPI0 MSPICFG RXCAP [1..1]  =============================================== */
26761 typedef enum {                                  /*!< MSPI0_MSPICFG_RXCAP                                                       */
26762   MSPI0_MSPICFG_RXCAP_NORMAL           = 0,     /*!< NORMAL : RX Capture phase aligns with CPHA setting                        */
26763   MSPI0_MSPICFG_RXCAP_DELAY            = 1,     /*!< DELAY : RX Capture phase is delayed from CPHA setting by one
26764                                                      clock edge                                                                */
26765 } MSPI0_MSPICFG_RXCAP_Enum;
26766 
26767 /* ==============================================  MSPI0 MSPICFG APBCLK [0..0]  ============================================== */
26768 typedef enum {                                  /*!< MSPI0_MSPICFG_APBCLK                                                      */
26769   MSPI0_MSPICFG_APBCLK_DIS             = 0,     /*!< DIS : Disable continuous clock.                                           */
26770   MSPI0_MSPICFG_APBCLK_EN              = 1,     /*!< EN : Enable continuous clock.                                             */
26771 } MSPI0_MSPICFG_APBCLK_Enum;
26772 
26773 /* ========================================================  MSPIDDR  ======================================================== */
26774 /* ========================================================  PADCFG  ========================================================= */
26775 /* =======================================================  PADOUTEN  ======================================================== */
26776 /* ==============================================  MSPI0 PADOUTEN OUTEN [0..9]  ============================================== */
26777 typedef enum {                                  /*!< MSPI0_PADOUTEN_OUTEN                                                      */
26778   MSPI0_PADOUTEN_OUTEN_QUAD0           = 271,   /*!< QUAD0 : Quad0 (4 data + 1 clock)                                          */
26779   MSPI0_PADOUTEN_OUTEN_QUAD1           = 496,   /*!< QUAD1 : Quad1 (4 data + 1 clock)                                          */
26780   MSPI0_PADOUTEN_OUTEN_OCTAL           = 1023,  /*!< OCTAL : Octal (8 data + 1 clock)                                          */
26781   MSPI0_PADOUTEN_OUTEN_SERIAL0         = 259,   /*!< SERIAL0 : Serial (2 data + 1 clock)                                       */
26782   MSPI0_PADOUTEN_OUTEN_SERIAL1         = 304,   /*!< SERIAL1 : Serial (2 data + 1 clock)                                       */
26783 } MSPI0_PADOUTEN_OUTEN_Enum;
26784 
26785 /* =======================================================  PADOVEREN  ======================================================= */
26786 /* ========================================================  PADOVER  ======================================================== */
26787 /* =========================================================  FLASH  ========================================================= */
26788 /* =============================================  MSPI0 FLASH XIPMIXED [8..10]  ============================================== */
26789 typedef enum {                                  /*!< MSPI0_FLASH_XIPMIXED                                                      */
26790   MSPI0_FLASH_XIPMIXED_NORMAL          = 0,     /*!< NORMAL : Transfers all proceed using the settings in DEVCFG
26791                                                      register (everything in the same data rate)                               */
26792   MSPI0_FLASH_XIPMIXED_D2              = 1,     /*!< D2 : Data operations proceed in dual data rate                            */
26793   MSPI0_FLASH_XIPMIXED_AD2             = 3,     /*!< AD2 : Address and Data operations proceed in dual data rate               */
26794   MSPI0_FLASH_XIPMIXED_D4              = 5,     /*!< D4 : Data operations proceed in quad data rate                            */
26795   MSPI0_FLASH_XIPMIXED_AD4             = 7,     /*!< AD4 : Address and Data operations proceed in quad data rate               */
26796 } MSPI0_FLASH_XIPMIXED_Enum;
26797 
26798 /* ===============================================  MSPI0 FLASH XIPACK [2..3]  =============================================== */
26799 typedef enum {                                  /*!< MSPI0_FLASH_XIPACK                                                        */
26800   MSPI0_FLASH_XIPACK_NOACK             = 0,     /*!< NOACK : No acknowledgment sent. Data IOs are tri-stated the
26801                                                      first turnaround cycle                                                    */
26802   MSPI0_FLASH_XIPACK_ACK               = 2,     /*!< ACK : Positive acknowledgment sent. Data IOs are driven to 0
26803                                                      the first turnaround cycle to acknowledge XIP mode                        */
26804   MSPI0_FLASH_XIPACK_TERMINATE         = 3,     /*!< TERMINATE : Negative acknowledgment sent. Data IOs are driven
26805                                                      to 1 the first turnaround cycle to terminate XIP mode.
26806                                                      XIPSENDI should be re-enabled for the next transfer                       */
26807 } MSPI0_FLASH_XIPACK_Enum;
26808 
26809 /* =======================================================  XIPINSTR  ======================================================== */
26810 /* ======================================================  SCRAMBLING  ======================================================= */
26811 /* =========================================================  INTEN  ========================================================= */
26812 /* ========================================================  INTSTAT  ======================================================== */
26813 /* ========================================================  INTCLR  ========================================================= */
26814 /* ========================================================  INTSET  ========================================================= */
26815 /* ========================================================  DMACFG  ========================================================= */
26816 /* ==============================================  MSPI0 DMACFG DMAPRI [3..4]  =============================================== */
26817 typedef enum {                                  /*!< MSPI0_DMACFG_DMAPRI                                                       */
26818   MSPI0_DMACFG_DMAPRI_LOW              = 0,     /*!< LOW : Low Priority (service as best effort)                               */
26819   MSPI0_DMACFG_DMAPRI_HIGH             = 1,     /*!< HIGH : High Priority (service immediately)                                */
26820   MSPI0_DMACFG_DMAPRI_AUTO             = 2,     /*!< AUTO : Auto Priority (priority raised once TX FIFO empties or
26821                                                      RX FIFO fills)                                                            */
26822 } MSPI0_DMACFG_DMAPRI_Enum;
26823 
26824 /* ==============================================  MSPI0 DMACFG DMADIR [2..2]  =============================================== */
26825 typedef enum {                                  /*!< MSPI0_DMACFG_DMADIR                                                       */
26826   MSPI0_DMACFG_DMADIR_P2M              = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
26827   MSPI0_DMACFG_DMADIR_M2P              = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
26828 } MSPI0_DMACFG_DMADIR_Enum;
26829 
26830 /* ===============================================  MSPI0 DMACFG DMAEN [0..1]  =============================================== */
26831 typedef enum {                                  /*!< MSPI0_DMACFG_DMAEN                                                        */
26832   MSPI0_DMACFG_DMAEN_DIS               = 0,     /*!< DIS : Disable DMA Function                                                */
26833   MSPI0_DMACFG_DMAEN_EN                = 3,     /*!< EN : Enable HW controlled DMA Function to manage DMA to flash
26834                                                      devices. HW will automatically handle issuance of instruction/address
26835                                                      bytes based on settings in the FLASH register.                            */
26836 } MSPI0_DMACFG_DMAEN_Enum;
26837 
26838 /* ========================================================  DMASTAT  ======================================================== */
26839 /* ======================================================  DMATARGADDR  ====================================================== */
26840 /* ======================================================  DMADEVADDR  ======================================================= */
26841 /* ======================================================  DMATOTCOUNT  ====================================================== */
26842 /* =======================================================  DMABCOUNT  ======================================================= */
26843 /* =======================================================  DMATHRESH  ======================================================= */
26844 /* ======================================================  DMABOUNDARY  ====================================================== */
26845 /* ==========================================  MSPI0 DMABOUNDARY DMABOUND [12..15]  ========================================== */
26846 typedef enum {                                  /*!< MSPI0_DMABOUNDARY_DMABOUND                                                */
26847   MSPI0_DMABOUNDARY_DMABOUND_NONE      = 0,     /*!< NONE : Disable DMA address boundary breaks                                */
26848   MSPI0_DMABOUNDARY_DMABOUND_BREAK32   = 1,     /*!< BREAK32 : Break at 32 byte boundary (0x20 increments)                     */
26849   MSPI0_DMABOUNDARY_DMABOUND_BREAK64   = 2,     /*!< BREAK64 : Break at 64 byte boundary (0x40 increments)                     */
26850   MSPI0_DMABOUNDARY_DMABOUND_BREAK128  = 3,     /*!< BREAK128 : Break at 128 byte boundary (0x80 increments)                   */
26851   MSPI0_DMABOUNDARY_DMABOUND_BREAK256  = 4,     /*!< BREAK256 : Break at 256 byte boundary (0x100 increments)                  */
26852   MSPI0_DMABOUNDARY_DMABOUND_BREAK512  = 5,     /*!< BREAK512 : Break at 512 byte boundary (0x200 increments)                  */
26853   MSPI0_DMABOUNDARY_DMABOUND_BREAK1K   = 6,     /*!< BREAK1K : Break at 1KB boundary (0x400 increments)                        */
26854   MSPI0_DMABOUNDARY_DMABOUND_BREAK2K   = 7,     /*!< BREAK2K : Break at 2KB boundary (0x800 increments)                        */
26855   MSPI0_DMABOUNDARY_DMABOUND_BREAK4K   = 8,     /*!< BREAK4K : Break at 4KB boundary (0x1000 increments)                       */
26856   MSPI0_DMABOUNDARY_DMABOUND_BREAK8K   = 9,     /*!< BREAK8K : Break at 8KB boundary (0x2000 increments)                       */
26857   MSPI0_DMABOUNDARY_DMABOUND_BREAK16K  = 10,    /*!< BREAK16K : Break at 16KB boundary (0x4000 increments)                     */
26858 } MSPI0_DMABOUNDARY_DMABOUND_Enum;
26859 
26860 /* =========================================================  CQCFG  ========================================================= */
26861 /* ===============================================  MSPI0 CQCFG CQPRI [1..1]  ================================================ */
26862 typedef enum {                                  /*!< MSPI0_CQCFG_CQPRI                                                         */
26863   MSPI0_CQCFG_CQPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
26864   MSPI0_CQCFG_CQPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
26865 } MSPI0_CQCFG_CQPRI_Enum;
26866 
26867 /* ================================================  MSPI0 CQCFG CQEN [0..0]  ================================================ */
26868 typedef enum {                                  /*!< MSPI0_CQCFG_CQEN                                                          */
26869   MSPI0_CQCFG_CQEN_DIS                 = 0,     /*!< DIS : Disable CQ Function                                                 */
26870   MSPI0_CQCFG_CQEN_EN                  = 1,     /*!< EN : Enable CQ Function                                                   */
26871 } MSPI0_CQCFG_CQEN_Enum;
26872 
26873 /* ========================================================  CQADDR  ========================================================= */
26874 /* ========================================================  CQSTAT  ========================================================= */
26875 /* ========================================================  CQFLAGS  ======================================================== */
26876 /* =============================================  MSPI0 CQFLAGS CQFLAGS [0..15]  ============================================= */
26877 typedef enum {                                  /*!< MSPI0_CQFLAGS_CQFLAGS                                                     */
26878   MSPI0_CQFLAGS_CQFLAGS_STOP           = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete.               */
26879   MSPI0_CQFLAGS_CQFLAGS_CQIDX          = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match.                          */
26880   MSPI0_CQFLAGS_CQFLAGS_BUF1XOREN      = 8192,  /*!< BUF1XOREN : Buffer 1 Ready Status (from selected IOM/MSPI).
26881                                                      This status is the result of XOR'ing the IOM1START with
26882                                                      the incoming status from the IOM. When high, MSPI can transfer
26883                                                      the buffer.                                                               */
26884   MSPI0_CQFLAGS_CQFLAGS_BUF0XOREN      = 4096,  /*!< BUF0XOREN : Buffer 0 Ready Status (from selected IOM/MSPI).
26885                                                      This status is the result of XOR'ing the IOM0START with
26886                                                      the incoming status from the IOM. When high, MSPI can transfer
26887                                                      the buffer.                                                               */
26888   MSPI0_CQFLAGS_CQFLAGS_DMACPL         = 2048,  /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT)            */
26889   MSPI0_CQFLAGS_CQFLAGS_CMDCPL         = 1024,  /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register)            */
26890   MSPI0_CQFLAGS_CQFLAGS_IOM1READY      = 512,   /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This
26891                                                      status is the result of XNOR'ing the IOM0START with the
26892                                                      incoming status from the IOM. When high, MSPI can send
26893                                                      to the buffer.                                                            */
26894   MSPI0_CQFLAGS_CQFLAGS_IOM0READY      = 256,   /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This
26895                                                      status is the result of XNOR'ing the IOM0START with the
26896                                                      incoming status from the IOM. When high, MSPI can send
26897                                                      to the buffer.                                                            */
26898   MSPI0_CQFLAGS_CQFLAGS_SWFLAG7        = 128,   /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
26899                                                      operations.                                                               */
26900   MSPI0_CQFLAGS_CQFLAGS_SWFLAG6        = 64,    /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
26901                                                      operations.                                                               */
26902   MSPI0_CQFLAGS_CQFLAGS_SWFLAG5        = 32,    /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
26903                                                      operations.                                                               */
26904   MSPI0_CQFLAGS_CQFLAGS_SWFLAG4        = 16,    /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
26905                                                      operations.                                                               */
26906   MSPI0_CQFLAGS_CQFLAGS_SWFLAG3        = 8,     /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
26907                                                      operations.                                                               */
26908   MSPI0_CQFLAGS_CQFLAGS_SWFLAG2        = 4,     /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
26909                                                      operations.                                                               */
26910   MSPI0_CQFLAGS_CQFLAGS_SWFLAG1        = 2,     /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
26911                                                      operations.                                                               */
26912   MSPI0_CQFLAGS_CQFLAGS_SWFLAG0        = 1,     /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
26913                                                      operations.                                                               */
26914 } MSPI0_CQFLAGS_CQFLAGS_Enum;
26915 
26916 /* ======================================================  CQSETCLEAR  ======================================================= */
26917 /* ========================================================  CQPAUSE  ======================================================== */
26918 /* =============================================  MSPI0 CQPAUSE CQMASK [0..15]  ============================================== */
26919 typedef enum {                                  /*!< MSPI0_CQPAUSE_CQMASK                                                      */
26920   MSPI0_CQPAUSE_CQMASK_STOP            = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete.               */
26921   MSPI0_CQPAUSE_CQMASK_CQIDX           = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match.                          */
26922   MSPI0_CQPAUSE_CQMASK_BUF1XOREN       = 8192,  /*!< BUF1XOREN : Buffer 1 Ready Status (from selected IOM/MSPI).
26923                                                      This status is the result of XOR'ing the IOM1START with
26924                                                      the incoming status from the IOM. When high, MSPI can transfer
26925                                                      the buffer.                                                               */
26926   MSPI0_CQPAUSE_CQMASK_BUF0XOREN       = 4096,  /*!< BUF0XOREN : Buffer 0 Ready Status (from selected IOM/MSPI).
26927                                                      This status is the result of XOR'ing the IOM0START with
26928                                                      the incoming status from the IOM. When high, MSPI can transfer
26929                                                      the buffer.                                                               */
26930   MSPI0_CQPAUSE_CQMASK_DMACPL          = 2048,  /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT)            */
26931   MSPI0_CQPAUSE_CQMASK_CMDCPL          = 1024,  /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register)            */
26932   MSPI0_CQPAUSE_CQMASK_IOM1READY       = 512,   /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This
26933                                                      status is the result of XNOR'ing the IOM0START with the
26934                                                      incoming status from the IOM. When high, MSPI can send
26935                                                      to the buffer.                                                            */
26936   MSPI0_CQPAUSE_CQMASK_IOM0READY       = 256,   /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This
26937                                                      status is the result of XNOR'ing the IOM0START with the
26938                                                      incoming status from the IOM. When high, MSPI can send
26939                                                      to the buffer.                                                            */
26940   MSPI0_CQPAUSE_CQMASK_SWFLAG7         = 128,   /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
26941                                                      operations.                                                               */
26942   MSPI0_CQPAUSE_CQMASK_SWFLAG6         = 64,    /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
26943                                                      operations.                                                               */
26944   MSPI0_CQPAUSE_CQMASK_SWFLAG5         = 32,    /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
26945                                                      operations.                                                               */
26946   MSPI0_CQPAUSE_CQMASK_SWFLAG4         = 16,    /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
26947                                                      operations.                                                               */
26948   MSPI0_CQPAUSE_CQMASK_SWFLAG3         = 8,     /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
26949                                                      operations.                                                               */
26950   MSPI0_CQPAUSE_CQMASK_SWFLAG2         = 4,     /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
26951                                                      operations.                                                               */
26952   MSPI0_CQPAUSE_CQMASK_SWFLAG1         = 2,     /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
26953                                                      operations.                                                               */
26954   MSPI0_CQPAUSE_CQMASK_SWFLAG0         = 1,     /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
26955                                                      operations.                                                               */
26956 } MSPI0_CQPAUSE_CQMASK_Enum;
26957 
26958 /* =======================================================  CQCURIDX  ======================================================== */
26959 /* =======================================================  CQENDIDX  ======================================================== */
26960 
26961 
26962 /* =========================================================================================================================== */
26963 /* ================                                            PDM                                            ================ */
26964 /* =========================================================================================================================== */
26965 
26966 /* =========================================================  PCFG  ========================================================== */
26967 /* ===============================================  PDM PCFG LRSWAP [31..31]  ================================================ */
26968 typedef enum {                                  /*!< PDM_PCFG_LRSWAP                                                           */
26969   PDM_PCFG_LRSWAP_EN                   = 1,     /*!< EN : Swap left and right channels (FIFO Read RIGHT_LEFT).                 */
26970   PDM_PCFG_LRSWAP_NOSWAP               = 0,     /*!< NOSWAP : No channel swapping (IFO Read LEFT_RIGHT).                       */
26971 } PDM_PCFG_LRSWAP_Enum;
26972 
26973 /* ==============================================  PDM PCFG PGARIGHT [26..30]  =============================================== */
26974 typedef enum {                                  /*!< PDM_PCFG_PGARIGHT                                                         */
26975   PDM_PCFG_PGARIGHT_P405DB             = 31,    /*!< P405DB : 40.5 db gain.                                                    */
26976   PDM_PCFG_PGARIGHT_P390DB             = 30,    /*!< P390DB : 39.0 db gain.                                                    */
26977   PDM_PCFG_PGARIGHT_P375DB             = 29,    /*!< P375DB : 37.5 db gain.                                                    */
26978   PDM_PCFG_PGARIGHT_P360DB             = 28,    /*!< P360DB : 36.0 db gain.                                                    */
26979   PDM_PCFG_PGARIGHT_P345DB             = 27,    /*!< P345DB : 34.5 db gain.                                                    */
26980   PDM_PCFG_PGARIGHT_P330DB             = 26,    /*!< P330DB : 33.0 db gain.                                                    */
26981   PDM_PCFG_PGARIGHT_P315DB             = 25,    /*!< P315DB : 31.5 db gain.                                                    */
26982   PDM_PCFG_PGARIGHT_P300DB             = 24,    /*!< P300DB : 30.0 db gain.                                                    */
26983   PDM_PCFG_PGARIGHT_P285DB             = 23,    /*!< P285DB : 28.5 db gain.                                                    */
26984   PDM_PCFG_PGARIGHT_P270DB             = 22,    /*!< P270DB : 27.0 db gain.                                                    */
26985   PDM_PCFG_PGARIGHT_P255DB             = 21,    /*!< P255DB : 25.5 db gain.                                                    */
26986   PDM_PCFG_PGARIGHT_P240DB             = 20,    /*!< P240DB : 24.0 db gain.                                                    */
26987   PDM_PCFG_PGARIGHT_P225DB             = 19,    /*!< P225DB : 22.5 db gain.                                                    */
26988   PDM_PCFG_PGARIGHT_P210DB             = 18,    /*!< P210DB : 21.0 db gain.                                                    */
26989   PDM_PCFG_PGARIGHT_P195DB             = 17,    /*!< P195DB : 19.5 db gain.                                                    */
26990   PDM_PCFG_PGARIGHT_P180DB             = 16,    /*!< P180DB : 18.0 db gain.                                                    */
26991   PDM_PCFG_PGARIGHT_P165DB             = 15,    /*!< P165DB : 16.5 db gain.                                                    */
26992   PDM_PCFG_PGARIGHT_P150DB             = 14,    /*!< P150DB : 15.0 db gain.                                                    */
26993   PDM_PCFG_PGARIGHT_P135DB             = 13,    /*!< P135DB : 13.5 db gain.                                                    */
26994   PDM_PCFG_PGARIGHT_P120DB             = 12,    /*!< P120DB : 12.0 db gain.                                                    */
26995   PDM_PCFG_PGARIGHT_P105DB             = 11,    /*!< P105DB : 10.5 db gain.                                                    */
26996   PDM_PCFG_PGARIGHT_P90DB              = 10,    /*!< P90DB : 9.0 db gain.                                                      */
26997   PDM_PCFG_PGARIGHT_P75DB              = 9,     /*!< P75DB : 7.5 db gain.                                                      */
26998   PDM_PCFG_PGARIGHT_P60DB              = 8,     /*!< P60DB : 6.0 db gain.                                                      */
26999   PDM_PCFG_PGARIGHT_P45DB              = 7,     /*!< P45DB : 4.5 db gain.                                                      */
27000   PDM_PCFG_PGARIGHT_P30DB              = 6,     /*!< P30DB : 3.0 db gain.                                                      */
27001   PDM_PCFG_PGARIGHT_P15DB              = 5,     /*!< P15DB : 1.5 db gain.                                                      */
27002   PDM_PCFG_PGARIGHT_0DB                = 4,     /*!< 0DB : 0.0 db gain.                                                        */
27003   PDM_PCFG_PGARIGHT_M15DB              = 3,     /*!< M15DB : -1.5 db gain.                                                     */
27004   PDM_PCFG_PGARIGHT_M300DB             = 2,     /*!< M300DB : -3.0 db gain.                                                    */
27005   PDM_PCFG_PGARIGHT_M45DB              = 1,     /*!< M45DB : -4.5 db gain.                                                     */
27006   PDM_PCFG_PGARIGHT_M60DB              = 0,     /*!< M60DB : -6.0 db gain.                                                     */
27007 } PDM_PCFG_PGARIGHT_Enum;
27008 
27009 /* ===============================================  PDM PCFG PGALEFT [21..25]  =============================================== */
27010 typedef enum {                                  /*!< PDM_PCFG_PGALEFT                                                          */
27011   PDM_PCFG_PGALEFT_P405DB              = 31,    /*!< P405DB : 40.5 db gain.                                                    */
27012   PDM_PCFG_PGALEFT_P390DB              = 30,    /*!< P390DB : 39.0 db gain.                                                    */
27013   PDM_PCFG_PGALEFT_P375DB              = 29,    /*!< P375DB : 37.5 db gain.                                                    */
27014   PDM_PCFG_PGALEFT_P360DB              = 28,    /*!< P360DB : 36.0 db gain.                                                    */
27015   PDM_PCFG_PGALEFT_P345DB              = 27,    /*!< P345DB : 34.5 db gain.                                                    */
27016   PDM_PCFG_PGALEFT_P330DB              = 26,    /*!< P330DB : 33.0 db gain.                                                    */
27017   PDM_PCFG_PGALEFT_P315DB              = 25,    /*!< P315DB : 31.5 db gain.                                                    */
27018   PDM_PCFG_PGALEFT_P300DB              = 24,    /*!< P300DB : 30.0 db gain.                                                    */
27019   PDM_PCFG_PGALEFT_P285DB              = 23,    /*!< P285DB : 28.5 db gain.                                                    */
27020   PDM_PCFG_PGALEFT_P270DB              = 22,    /*!< P270DB : 27.0 db gain.                                                    */
27021   PDM_PCFG_PGALEFT_P255DB              = 21,    /*!< P255DB : 25.5 db gain.                                                    */
27022   PDM_PCFG_PGALEFT_P240DB              = 20,    /*!< P240DB : 24.0 db gain.                                                    */
27023   PDM_PCFG_PGALEFT_P225DB              = 19,    /*!< P225DB : 22.5 db gain.                                                    */
27024   PDM_PCFG_PGALEFT_P210DB              = 18,    /*!< P210DB : 21.0 db gain.                                                    */
27025   PDM_PCFG_PGALEFT_P195DB              = 17,    /*!< P195DB : 19.5 db gain.                                                    */
27026   PDM_PCFG_PGALEFT_P180DB              = 16,    /*!< P180DB : 18.0 db gain.                                                    */
27027   PDM_PCFG_PGALEFT_P165DB              = 15,    /*!< P165DB : 16.5 db gain.                                                    */
27028   PDM_PCFG_PGALEFT_P150DB              = 14,    /*!< P150DB : 15.0 db gain.                                                    */
27029   PDM_PCFG_PGALEFT_P135DB              = 13,    /*!< P135DB : 13.5 db gain.                                                    */
27030   PDM_PCFG_PGALEFT_P120DB              = 12,    /*!< P120DB : 12.0 db gain.                                                    */
27031   PDM_PCFG_PGALEFT_P105DB              = 11,    /*!< P105DB : 10.5 db gain.                                                    */
27032   PDM_PCFG_PGALEFT_P90DB               = 10,    /*!< P90DB : 9.0 db gain.                                                      */
27033   PDM_PCFG_PGALEFT_P75DB               = 9,     /*!< P75DB : 7.5 db gain.                                                      */
27034   PDM_PCFG_PGALEFT_P60DB               = 8,     /*!< P60DB : 6.0 db gain.                                                      */
27035   PDM_PCFG_PGALEFT_P45DB               = 7,     /*!< P45DB : 4.5 db gain.                                                      */
27036   PDM_PCFG_PGALEFT_P30DB               = 6,     /*!< P30DB : 3.0 db gain.                                                      */
27037   PDM_PCFG_PGALEFT_P15DB               = 5,     /*!< P15DB : 1.5 db gain.                                                      */
27038   PDM_PCFG_PGALEFT_0DB                 = 4,     /*!< 0DB : 0.0 db gain.                                                        */
27039   PDM_PCFG_PGALEFT_M15DB               = 3,     /*!< M15DB : -1.5 db gain.                                                     */
27040   PDM_PCFG_PGALEFT_M300DB              = 2,     /*!< M300DB : -3.0 db gain.                                                    */
27041   PDM_PCFG_PGALEFT_M45DB               = 1,     /*!< M45DB : -4.5 db gain.                                                     */
27042   PDM_PCFG_PGALEFT_M60DB               = 0,     /*!< M60DB : -6.0 db gain.                                                     */
27043 } PDM_PCFG_PGALEFT_Enum;
27044 
27045 /* ===============================================  PDM PCFG MCLKDIV [17..18]  =============================================== */
27046 typedef enum {                                  /*!< PDM_PCFG_MCLKDIV                                                          */
27047   PDM_PCFG_MCLKDIV_MCKDIV4             = 3,     /*!< MCKDIV4 : Divide input clock by 4                                         */
27048   PDM_PCFG_MCLKDIV_MCKDIV3             = 2,     /*!< MCKDIV3 : Divide input clock by 3                                         */
27049   PDM_PCFG_MCLKDIV_MCKDIV2             = 1,     /*!< MCKDIV2 : Divide input clock by 2                                         */
27050   PDM_PCFG_MCLKDIV_MCKDIV1             = 0,     /*!< MCKDIV1 : Divide input clock by 1                                         */
27051 } PDM_PCFG_MCLKDIV_Enum;
27052 
27053 /* ================================================  PDM PCFG ADCHPD [9..9]  ================================================= */
27054 typedef enum {                                  /*!< PDM_PCFG_ADCHPD                                                           */
27055   PDM_PCFG_ADCHPD_EN                   = 0,     /*!< EN : Enable high pass filter.                                             */
27056   PDM_PCFG_ADCHPD_DIS                  = 1,     /*!< DIS : Disable high pass filter.                                           */
27057 } PDM_PCFG_ADCHPD_Enum;
27058 
27059 /* ===============================================  PDM PCFG SOFTMUTE [1..1]  ================================================ */
27060 typedef enum {                                  /*!< PDM_PCFG_SOFTMUTE                                                         */
27061   PDM_PCFG_SOFTMUTE_EN                 = 1,     /*!< EN : Enable Soft Mute.                                                    */
27062   PDM_PCFG_SOFTMUTE_DIS                = 0,     /*!< DIS : Disable Soft Mute.                                                  */
27063 } PDM_PCFG_SOFTMUTE_Enum;
27064 
27065 /* ===============================================  PDM PCFG PDMCOREEN [0..0]  =============================================== */
27066 typedef enum {                                  /*!< PDM_PCFG_PDMCOREEN                                                        */
27067   PDM_PCFG_PDMCOREEN_EN                = 1,     /*!< EN : Enable Data Streaming.                                               */
27068   PDM_PCFG_PDMCOREEN_DIS               = 0,     /*!< DIS : Disable Data Streaming.                                             */
27069 } PDM_PCFG_PDMCOREEN_Enum;
27070 
27071 /* =========================================================  VCFG  ========================================================== */
27072 /* ===============================================  PDM VCFG IOCLKEN [31..31]  =============================================== */
27073 typedef enum {                                  /*!< PDM_VCFG_IOCLKEN                                                          */
27074   PDM_VCFG_IOCLKEN_DIS                 = 0,     /*!< DIS : Disable FIFO read.                                                  */
27075   PDM_VCFG_IOCLKEN_EN                  = 1,     /*!< EN : Enable FIFO read.                                                    */
27076 } PDM_VCFG_IOCLKEN_Enum;
27077 
27078 /* ================================================  PDM VCFG RSTB [30..30]  ================================================= */
27079 typedef enum {                                  /*!< PDM_VCFG_RSTB                                                             */
27080   PDM_VCFG_RSTB_RESET                  = 0,     /*!< RESET : Reset the core.                                                   */
27081   PDM_VCFG_RSTB_NORM                   = 1,     /*!< NORM : Enable the core.                                                   */
27082 } PDM_VCFG_RSTB_Enum;
27083 
27084 /* ==============================================  PDM VCFG PDMCLKSEL [27..29]  ============================================== */
27085 typedef enum {                                  /*!< PDM_VCFG_PDMCLKSEL                                                        */
27086   PDM_VCFG_PDMCLKSEL_DISABLE           = 0,     /*!< DISABLE : Static value.                                                   */
27087   PDM_VCFG_PDMCLKSEL_12MHz             = 1,     /*!< 12MHz : PDM clock is 12 MHz.                                              */
27088   PDM_VCFG_PDMCLKSEL_6MHz              = 2,     /*!< 6MHz : PDM clock is 6 MHz.                                                */
27089   PDM_VCFG_PDMCLKSEL_3MHz              = 3,     /*!< 3MHz : PDM clock is 3 MHz.                                                */
27090   PDM_VCFG_PDMCLKSEL_1_5MHz            = 4,     /*!< 1_5MHz : PDM clock is 1.5 MHz.                                            */
27091   PDM_VCFG_PDMCLKSEL_750KHz            = 5,     /*!< 750KHz : PDM clock is 750 KHz.                                            */
27092   PDM_VCFG_PDMCLKSEL_375KHz            = 6,     /*!< 375KHz : PDM clock is 375 KHz.                                            */
27093   PDM_VCFG_PDMCLKSEL_187KHz            = 7,     /*!< 187KHz : PDM clock is 187.5 KHz.                                          */
27094 } PDM_VCFG_PDMCLKSEL_Enum;
27095 
27096 /* ==============================================  PDM VCFG PDMCLKEN [26..26]  =============================================== */
27097 typedef enum {                                  /*!< PDM_VCFG_PDMCLKEN                                                         */
27098   PDM_VCFG_PDMCLKEN_DIS                = 0,     /*!< DIS : Disable serial clock.                                               */
27099   PDM_VCFG_PDMCLKEN_EN                 = 1,     /*!< EN : Enable serial clock.                                                 */
27100 } PDM_VCFG_PDMCLKEN_Enum;
27101 
27102 /* ================================================  PDM VCFG I2SEN [20..20]  ================================================ */
27103 typedef enum {                                  /*!< PDM_VCFG_I2SEN                                                            */
27104   PDM_VCFG_I2SEN_DIS                   = 0,     /*!< DIS : Disable I2S interface.                                              */
27105   PDM_VCFG_I2SEN_EN                    = 1,     /*!< EN : Enable I2S interface.                                                */
27106 } PDM_VCFG_I2SEN_Enum;
27107 
27108 /* ===============================================  PDM VCFG BCLKINV [19..19]  =============================================== */
27109 typedef enum {                                  /*!< PDM_VCFG_BCLKINV                                                          */
27110   PDM_VCFG_BCLKINV_INV                 = 0,     /*!< INV : BCLK inverted.                                                      */
27111   PDM_VCFG_BCLKINV_NORM                = 1,     /*!< NORM : BCLK not inverted.                                                 */
27112 } PDM_VCFG_BCLKINV_Enum;
27113 
27114 /* ==============================================  PDM VCFG DMICKDEL [17..17]  =============================================== */
27115 typedef enum {                                  /*!< PDM_VCFG_DMICKDEL                                                         */
27116   PDM_VCFG_DMICKDEL_0CYC               = 0,     /*!< 0CYC : No delay.                                                          */
27117   PDM_VCFG_DMICKDEL_1CYC               = 1,     /*!< 1CYC : 1 cycle delay.                                                     */
27118 } PDM_VCFG_DMICKDEL_Enum;
27119 
27120 /* ================================================  PDM VCFG SELAP [16..16]  ================================================ */
27121 typedef enum {                                  /*!< PDM_VCFG_SELAP                                                            */
27122   PDM_VCFG_SELAP_I2S                   = 1,     /*!< I2S : Clock source from I2S BCLK.                                         */
27123   PDM_VCFG_SELAP_INTERNAL              = 0,     /*!< INTERNAL : Clock source from internal clock generator.                    */
27124 } PDM_VCFG_SELAP_Enum;
27125 
27126 /* ================================================  PDM VCFG PCMPACK [8..8]  ================================================ */
27127 typedef enum {                                  /*!< PDM_VCFG_PCMPACK                                                          */
27128   PDM_VCFG_PCMPACK_DIS                 = 0,     /*!< DIS : Disable PCM packing.                                                */
27129   PDM_VCFG_PCMPACK_EN                  = 1,     /*!< EN : Enable PCM packing.                                                  */
27130 } PDM_VCFG_PCMPACK_Enum;
27131 
27132 /* =================================================  PDM VCFG CHSET [3..4]  ================================================= */
27133 typedef enum {                                  /*!< PDM_VCFG_CHSET                                                            */
27134   PDM_VCFG_CHSET_DIS                   = 0,     /*!< DIS : Channel disabled.                                                   */
27135   PDM_VCFG_CHSET_LEFT                  = 1,     /*!< LEFT : Mono left channel.                                                 */
27136   PDM_VCFG_CHSET_RIGHT                 = 2,     /*!< RIGHT : Mono right channel.                                               */
27137   PDM_VCFG_CHSET_STEREO                = 3,     /*!< STEREO : Stereo channels.                                                 */
27138 } PDM_VCFG_CHSET_Enum;
27139 
27140 /* =======================================================  VOICESTAT  ======================================================= */
27141 /* =======================================================  FIFOREAD  ======================================================== */
27142 /* =======================================================  FIFOFLUSH  ======================================================= */
27143 /* ========================================================  FIFOTHR  ======================================================== */
27144 /* =========================================================  INTEN  ========================================================= */
27145 /* ========================================================  INTSTAT  ======================================================== */
27146 /* ========================================================  INTCLR  ========================================================= */
27147 /* ========================================================  INTSET  ========================================================= */
27148 /* =======================================================  DMATRIGEN  ======================================================= */
27149 /* ======================================================  DMATRIGSTAT  ====================================================== */
27150 /* ========================================================  DMACFG  ========================================================= */
27151 /* ===============================================  PDM DMACFG DMAPRI [8..8]  ================================================ */
27152 typedef enum {                                  /*!< PDM_DMACFG_DMAPRI                                                         */
27153   PDM_DMACFG_DMAPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
27154   PDM_DMACFG_DMAPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
27155 } PDM_DMACFG_DMAPRI_Enum;
27156 
27157 /* ===============================================  PDM DMACFG DMADIR [2..2]  ================================================ */
27158 typedef enum {                                  /*!< PDM_DMACFG_DMADIR                                                         */
27159   PDM_DMACFG_DMADIR_P2M                = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. THe PDM module
27160                                                      will only DMA to memory.                                                  */
27161   PDM_DMACFG_DMADIR_M2P                = 1,     /*!< M2P : Memory to Peripheral transaction. Not available for PDM
27162                                                      module                                                                    */
27163 } PDM_DMACFG_DMADIR_Enum;
27164 
27165 /* ================================================  PDM DMACFG DMAEN [0..0]  ================================================ */
27166 typedef enum {                                  /*!< PDM_DMACFG_DMAEN                                                          */
27167   PDM_DMACFG_DMAEN_DIS                 = 0,     /*!< DIS : Disable DMA Function                                                */
27168   PDM_DMACFG_DMAEN_EN                  = 1,     /*!< EN : Enable DMA Function                                                  */
27169 } PDM_DMACFG_DMAEN_Enum;
27170 
27171 /* ======================================================  DMATOTCOUNT  ====================================================== */
27172 /* ======================================================  DMATARGADDR  ====================================================== */
27173 /* ========================================================  DMASTAT  ======================================================== */
27174 
27175 
27176 /* =========================================================================================================================== */
27177 /* ================                                          PWRCTRL                                          ================ */
27178 /* =========================================================================================================================== */
27179 
27180 /* =======================================================  SUPPLYSRC  ======================================================= */
27181 /* ==========================================  PWRCTRL SUPPLYSRC BLEBUCKEN [0..0]  =========================================== */
27182 typedef enum {                                  /*!< PWRCTRL_SUPPLYSRC_BLEBUCKEN                                               */
27183   PWRCTRL_SUPPLYSRC_BLEBUCKEN_EN       = 1,     /*!< EN : Enable the BLE Buck.                                                 */
27184   PWRCTRL_SUPPLYSRC_BLEBUCKEN_DIS      = 0,     /*!< DIS : Disable the BLE Buck.                                               */
27185 } PWRCTRL_SUPPLYSRC_BLEBUCKEN_Enum;
27186 
27187 /* =====================================================  SUPPLYSTATUS  ====================================================== */
27188 /* =========================================  PWRCTRL SUPPLYSTATUS BLEBUCKON [1..1]  ========================================= */
27189 typedef enum {                                  /*!< PWRCTRL_SUPPLYSTATUS_BLEBUCKON                                            */
27190   PWRCTRL_SUPPLYSTATUS_BLEBUCKON_LDO   = 0,     /*!< LDO : Indicates the the LDO is supplying the BLE/Burst power
27191                                                      domain                                                                    */
27192   PWRCTRL_SUPPLYSTATUS_BLEBUCKON_BUCK  = 1,     /*!< BUCK : Indicates the the Buck is supplying the BLE/Burst power
27193                                                      domain                                                                    */
27194 } PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Enum;
27195 
27196 /* ========================================  PWRCTRL SUPPLYSTATUS SIMOBUCKON [0..0]  ========================================= */
27197 typedef enum {                                  /*!< PWRCTRL_SUPPLYSTATUS_SIMOBUCKON                                           */
27198   PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_OFF  = 0,     /*!< OFF : Indicates the the SIMO Buck is OFF.                                 */
27199   PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_ON   = 1,     /*!< ON : Indicates the the SIMO Buck is ON.                                   */
27200 } PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Enum;
27201 
27202 /* =======================================================  DEVPWREN  ======================================================== */
27203 /* ===========================================  PWRCTRL DEVPWREN PWRBLEL [15..15]  =========================================== */
27204 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRBLEL                                                  */
27205   PWRCTRL_DEVPWREN_PWRBLEL_EN          = 1,     /*!< EN : Power up BLE controller                                              */
27206   PWRCTRL_DEVPWREN_PWRBLEL_DIS         = 0,     /*!< DIS : Power down BLE controller                                           */
27207 } PWRCTRL_DEVPWREN_PWRBLEL_Enum;
27208 
27209 /* ===========================================  PWRCTRL DEVPWREN PWRPDM [14..14]  ============================================ */
27210 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRPDM                                                   */
27211   PWRCTRL_DEVPWREN_PWRPDM_EN           = 1,     /*!< EN : Power up PDM                                                         */
27212   PWRCTRL_DEVPWREN_PWRPDM_DIS          = 0,     /*!< DIS : Power down PDM                                                      */
27213 } PWRCTRL_DEVPWREN_PWRPDM_Enum;
27214 
27215 /* ==========================================  PWRCTRL DEVPWREN PWRMSPI2 [13..13]  =========================================== */
27216 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRMSPI2                                                 */
27217   PWRCTRL_DEVPWREN_PWRMSPI2_EN         = 1,     /*!< EN : Power up MSPI2                                                       */
27218   PWRCTRL_DEVPWREN_PWRMSPI2_DIS        = 0,     /*!< DIS : Power down MSPI2                                                    */
27219 } PWRCTRL_DEVPWREN_PWRMSPI2_Enum;
27220 
27221 /* ==========================================  PWRCTRL DEVPWREN PWRMSPI1 [12..12]  =========================================== */
27222 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRMSPI1                                                 */
27223   PWRCTRL_DEVPWREN_PWRMSPI1_EN         = 1,     /*!< EN : Power up MSPI1                                                       */
27224   PWRCTRL_DEVPWREN_PWRMSPI1_DIS        = 0,     /*!< DIS : Power down MSPI1                                                    */
27225 } PWRCTRL_DEVPWREN_PWRMSPI1_Enum;
27226 
27227 /* ==========================================  PWRCTRL DEVPWREN PWRMSPI0 [11..11]  =========================================== */
27228 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRMSPI0                                                 */
27229   PWRCTRL_DEVPWREN_PWRMSPI0_EN         = 1,     /*!< EN : Power up MSPI0                                                       */
27230   PWRCTRL_DEVPWREN_PWRMSPI0_DIS        = 0,     /*!< DIS : Power down MSPI0                                                    */
27231 } PWRCTRL_DEVPWREN_PWRMSPI0_Enum;
27232 
27233 /* ==========================================  PWRCTRL DEVPWREN PWRSCARD [10..10]  =========================================== */
27234 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRSCARD                                                 */
27235   PWRCTRL_DEVPWREN_PWRSCARD_EN         = 1,     /*!< EN : Power up SCARD                                                       */
27236   PWRCTRL_DEVPWREN_PWRSCARD_DIS        = 0,     /*!< DIS : Power down SCARD                                                    */
27237 } PWRCTRL_DEVPWREN_PWRSCARD_Enum;
27238 
27239 /* ============================================  PWRCTRL DEVPWREN PWRADC [9..9]  ============================================= */
27240 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRADC                                                   */
27241   PWRCTRL_DEVPWREN_PWRADC_EN           = 1,     /*!< EN : Power up ADC                                                         */
27242   PWRCTRL_DEVPWREN_PWRADC_DIS          = 0,     /*!< DIS : Power Down ADC                                                      */
27243 } PWRCTRL_DEVPWREN_PWRADC_Enum;
27244 
27245 /* ===========================================  PWRCTRL DEVPWREN PWRUART1 [8..8]  ============================================ */
27246 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRUART1                                                 */
27247   PWRCTRL_DEVPWREN_PWRUART1_EN         = 1,     /*!< EN : Power up UART 1                                                      */
27248   PWRCTRL_DEVPWREN_PWRUART1_DIS        = 0,     /*!< DIS : Power down UART 1                                                   */
27249 } PWRCTRL_DEVPWREN_PWRUART1_Enum;
27250 
27251 /* ===========================================  PWRCTRL DEVPWREN PWRUART0 [7..7]  ============================================ */
27252 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRUART0                                                 */
27253   PWRCTRL_DEVPWREN_PWRUART0_EN         = 1,     /*!< EN : Power up UART 0                                                      */
27254   PWRCTRL_DEVPWREN_PWRUART0_DIS        = 0,     /*!< DIS : Power down UART 0                                                   */
27255 } PWRCTRL_DEVPWREN_PWRUART0_Enum;
27256 
27257 /* ============================================  PWRCTRL DEVPWREN PWRIOM5 [6..6]  ============================================ */
27258 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM5                                                  */
27259   PWRCTRL_DEVPWREN_PWRIOM5_EN          = 1,     /*!< EN : Power up IO Master 5                                                 */
27260   PWRCTRL_DEVPWREN_PWRIOM5_DIS         = 0,     /*!< DIS : Power down IO Master 5                                              */
27261 } PWRCTRL_DEVPWREN_PWRIOM5_Enum;
27262 
27263 /* ============================================  PWRCTRL DEVPWREN PWRIOM4 [5..5]  ============================================ */
27264 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM4                                                  */
27265   PWRCTRL_DEVPWREN_PWRIOM4_EN          = 1,     /*!< EN : Power up IO Master 4                                                 */
27266   PWRCTRL_DEVPWREN_PWRIOM4_DIS         = 0,     /*!< DIS : Power down IO Master 4                                              */
27267 } PWRCTRL_DEVPWREN_PWRIOM4_Enum;
27268 
27269 /* ============================================  PWRCTRL DEVPWREN PWRIOM3 [4..4]  ============================================ */
27270 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM3                                                  */
27271   PWRCTRL_DEVPWREN_PWRIOM3_EN          = 1,     /*!< EN : Power up IO Master 3                                                 */
27272   PWRCTRL_DEVPWREN_PWRIOM3_DIS         = 0,     /*!< DIS : Power down IO Master 3                                              */
27273 } PWRCTRL_DEVPWREN_PWRIOM3_Enum;
27274 
27275 /* ============================================  PWRCTRL DEVPWREN PWRIOM2 [3..3]  ============================================ */
27276 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM2                                                  */
27277   PWRCTRL_DEVPWREN_PWRIOM2_EN          = 1,     /*!< EN : Power up IO Master 2                                                 */
27278   PWRCTRL_DEVPWREN_PWRIOM2_DIS         = 0,     /*!< DIS : Power down IO Master 2                                              */
27279 } PWRCTRL_DEVPWREN_PWRIOM2_Enum;
27280 
27281 /* ============================================  PWRCTRL DEVPWREN PWRIOM1 [2..2]  ============================================ */
27282 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM1                                                  */
27283   PWRCTRL_DEVPWREN_PWRIOM1_EN          = 1,     /*!< EN : Power up IO Master 1                                                 */
27284   PWRCTRL_DEVPWREN_PWRIOM1_DIS         = 0,     /*!< DIS : Power down IO Master 1                                              */
27285 } PWRCTRL_DEVPWREN_PWRIOM1_Enum;
27286 
27287 /* ============================================  PWRCTRL DEVPWREN PWRIOM0 [1..1]  ============================================ */
27288 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM0                                                  */
27289   PWRCTRL_DEVPWREN_PWRIOM0_EN          = 1,     /*!< EN : Power up IO Master 0                                                 */
27290   PWRCTRL_DEVPWREN_PWRIOM0_DIS         = 0,     /*!< DIS : Power down IO Master 0                                              */
27291 } PWRCTRL_DEVPWREN_PWRIOM0_Enum;
27292 
27293 /* ============================================  PWRCTRL DEVPWREN PWRIOS [0..0]  ============================================= */
27294 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOS                                                   */
27295   PWRCTRL_DEVPWREN_PWRIOS_EN           = 1,     /*!< EN : Power up IO slave                                                    */
27296   PWRCTRL_DEVPWREN_PWRIOS_DIS          = 0,     /*!< DIS : Power down IO slave                                                 */
27297 } PWRCTRL_DEVPWREN_PWRIOS_Enum;
27298 
27299 /* =====================================================  MEMPWDINSLEEP  ===================================================== */
27300 /* ======================================  PWRCTRL MEMPWDINSLEEP CACHEPWDSLP [31..31]  ======================================= */
27301 typedef enum {                                  /*!< PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP                                         */
27302   PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN = 1,     /*!< EN : Power down cache in deep sleep                                       */
27303   PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_DIS = 0,    /*!< DIS : Retain cache in deep sleep                                          */
27304 } PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Enum;
27305 
27306 /* ======================================  PWRCTRL MEMPWDINSLEEP FLASH1PWDSLP [14..14]  ====================================== */
27307 typedef enum {                                  /*!< PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP                                        */
27308   PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_EN = 1,    /*!< EN : FLASH1 is powered down during deep sleep                             */
27309   PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_DIS = 0,   /*!< DIS : FLASH1 is kept powered on during deep sleep                         */
27310 } PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Enum;
27311 
27312 /* ======================================  PWRCTRL MEMPWDINSLEEP FLASH0PWDSLP [13..13]  ====================================== */
27313 typedef enum {                                  /*!< PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP                                        */
27314   PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_EN = 1,    /*!< EN : FLASH0 is powered down during deep sleep                             */
27315   PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_DIS = 0,   /*!< DIS : FLASH0 is kept powered on during deep sleep                         */
27316 } PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Enum;
27317 
27318 /* =======================================  PWRCTRL MEMPWDINSLEEP SRAMPWDSLP [3..12]  ======================================== */
27319 typedef enum {                                  /*!< PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP                                          */
27320   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_NONE = 0,    /*!< NONE : All banks retained                                                 */
27321   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP0 = 1,  /*!< GROUP0 : SRAM GROUP0 powered down (64KB-128KB)                            */
27322   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP1 = 2,  /*!< GROUP1 : SRAM GROUP1 powered down (128KB-192KB)                           */
27323   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP2 = 4,  /*!< GROUP2 : SRAM GROUP2 powered down (192KB-256KB)                           */
27324   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP3 = 8,  /*!< GROUP3 : SRAM GROUP3 powered down (256KB-320KB)                           */
27325   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP4 = 16, /*!< GROUP4 : SRAM GROUP4 powered down (320KB-384KB)                           */
27326   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP5 = 32, /*!< GROUP5 : SRAM GROUP5 powered down (384KB-448KB)                           */
27327   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP6 = 64, /*!< GROUP6 : SRAM GROUP6 powered down (448KB-512KB)                           */
27328   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP7 = 128,/*!< GROUP7 : SRAM GROUP7 powered down (512KB-576KB)                           */
27329   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP8 = 256,/*!< GROUP8 : SRAM GROUP8 powered down (576KB-672KB)                           */
27330   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP9 = 512,/*!< GROUP9 : SRAM GROUP9 powered down (672KB-768KB)                           */
27331   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM128K = 3,/*!< SRAM128K : Power-down lower 128k SRAM (64KB-192KB)                        */
27332   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM256K = 15,/*!< SRAM256K : Power-down lower 256k SRAM (64KB-320KB)                       */
27333   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER64K = 1022,/*!< ALLBUTLOWER64K : All SRAM banks but lower 64k powered down.      */
27334   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER128K = 1020,/*!< ALLBUTLOWER128K : All banks but lower 128k powered down.        */
27335   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER256K = 1008,/*!< ALLBUTLOWER256K : All banks but lower 256k powered down.        */
27336   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALL = 1023,  /*!< ALL : All banks powered down.                                             */
27337 } PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Enum;
27338 
27339 /* ========================================  PWRCTRL MEMPWDINSLEEP DTCMPWDSLP [0..2]  ======================================== */
27340 typedef enum {                                  /*!< PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP                                          */
27341   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_NONE = 0,    /*!< NONE : All DTCM retained                                                  */
27342   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM0 = 1,/*!< GROUP0DTCM0 : Group0_DTCM0 powered down in deep sleep (0KB-8KB)        */
27343   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM1 = 2,/*!< GROUP0DTCM1 : Group0_DTCM1 powered down in deep sleep (8KB-32KB)       */
27344   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0 = 3,  /*!< GROUP0 : Both DTCMs in group0 are powered down in deep sleep
27345                                                      (0KB-32KB)                                                                */
27346   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALLBUTGROUP0DTCM0 = 6,/*!< ALLBUTGROUP0DTCM0 : Group1 and Group0_DTCM1 are powered down
27347                                                      in deep sleep (8KB-64KB)                                                  */
27348   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP1 = 4,  /*!< GROUP1 : Group1 DTCM powered down in deep sleep (32KB-64KB)               */
27349   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL = 7,     /*!< ALL : All DTCMs powered down in deep sleep (0KB-64KB)                     */
27350 } PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Enum;
27351 
27352 /* =======================================================  MEMPWREN  ======================================================== */
27353 /* ===========================================  PWRCTRL MEMPWREN CACHEB2 [31..31]  =========================================== */
27354 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_CACHEB2                                                  */
27355   PWRCTRL_MEMPWREN_CACHEB2_EN          = 1,     /*!< EN : Power up Cache Bank 2                                                */
27356   PWRCTRL_MEMPWREN_CACHEB2_DIS         = 0,     /*!< DIS : Power down Cache Bank 2                                             */
27357 } PWRCTRL_MEMPWREN_CACHEB2_Enum;
27358 
27359 /* ===========================================  PWRCTRL MEMPWREN CACHEB0 [30..30]  =========================================== */
27360 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_CACHEB0                                                  */
27361   PWRCTRL_MEMPWREN_CACHEB0_EN          = 1,     /*!< EN : Power up Cache Bank 0                                                */
27362   PWRCTRL_MEMPWREN_CACHEB0_DIS         = 0,     /*!< DIS : Power down Cache Bank 0                                             */
27363 } PWRCTRL_MEMPWREN_CACHEB0_Enum;
27364 
27365 /* ===========================================  PWRCTRL MEMPWREN FLASH1 [14..14]  ============================================ */
27366 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_FLASH1                                                   */
27367   PWRCTRL_MEMPWREN_FLASH1_EN           = 1,     /*!< EN : Power up FLASH group 1 (1MB-2MB)                                     */
27368   PWRCTRL_MEMPWREN_FLASH1_DIS          = 0,     /*!< DIS : Power down FLASH group 1 (1MB-2MB)                                  */
27369 } PWRCTRL_MEMPWREN_FLASH1_Enum;
27370 
27371 /* ===========================================  PWRCTRL MEMPWREN FLASH0 [13..13]  ============================================ */
27372 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_FLASH0                                                   */
27373   PWRCTRL_MEMPWREN_FLASH0_EN           = 1,     /*!< EN : Power up FLASH group 0 (0MB-1MB)                                     */
27374   PWRCTRL_MEMPWREN_FLASH0_DIS          = 0,     /*!< DIS : Power down FLASH group 0 (0MB-1MB)                                  */
27375 } PWRCTRL_MEMPWREN_FLASH0_Enum;
27376 
27377 /* =============================================  PWRCTRL MEMPWREN SRAM [3..12]  ============================================= */
27378 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_SRAM                                                     */
27379   PWRCTRL_MEMPWREN_SRAM_NONE           = 0,     /*!< NONE : Do not power ON any of the SRAM banks                              */
27380   PWRCTRL_MEMPWREN_SRAM_GROUP0         = 1,     /*!< GROUP0 : Power ON only SRAM 64KB group0 (addr: 0x10010000 -
27381                                                      0x1001FFFF)                                                               */
27382   PWRCTRL_MEMPWREN_SRAM_GROUP1         = 2,     /*!< GROUP1 : Power ON only SRAM 64KB group1 (addr: 0x10020000 -
27383                                                      0x1002FFFF)                                                               */
27384   PWRCTRL_MEMPWREN_SRAM_GROUP2         = 4,     /*!< GROUP2 : Power ON only SRAM 64KB group2 (addr: 0x10030000 -
27385                                                      0x1003FFFF)                                                               */
27386   PWRCTRL_MEMPWREN_SRAM_GROUP3         = 8,     /*!< GROUP3 : Power ON only SRAM 64KB group3 (addr: 0x10040000 -
27387                                                      0x1004FFFF)                                                               */
27388   PWRCTRL_MEMPWREN_SRAM_GROUP4         = 16,    /*!< GROUP4 : Power ON only SRAM 64KB group4 (addr: 0x10050000 -
27389                                                      0x1005FFFF)                                                               */
27390   PWRCTRL_MEMPWREN_SRAM_GROUP5         = 32,    /*!< GROUP5 : Power ON only SRAM 64KB group5 (addr: 0x10060000 -
27391                                                      0x1006FFFF)                                                               */
27392   PWRCTRL_MEMPWREN_SRAM_GROUP6         = 64,    /*!< GROUP6 : Power ON only SRAM 64KB group6 (addr: 0x10070000 -
27393                                                      0x1007FFFF)                                                               */
27394   PWRCTRL_MEMPWREN_SRAM_GROUP7         = 128,   /*!< GROUP7 : Power ON only SRAM 64KB group7 (addr: 0x10080000 -
27395                                                      0x1008FFFF)                                                               */
27396   PWRCTRL_MEMPWREN_SRAM_GROUP8         = 256,   /*!< GROUP8 : Power ON only SRAM 96KB group8 (addr: 0x10090000 -
27397                                                      0x100A7FFF)                                                               */
27398   PWRCTRL_MEMPWREN_SRAM_GROUP9         = 512,   /*!< GROUP9 : Power ON only SRAM 96KB group9 (addr: 0x100A8000 -
27399                                                      0x100BFFFF)                                                               */
27400   PWRCTRL_MEMPWREN_SRAM_SRAM128K       = 3,     /*!< SRAM128K : Power ON only lower 128k (addr: 0x10010000 - 0x1002FFFF)       */
27401   PWRCTRL_MEMPWREN_SRAM_SRAM256K       = 15,    /*!< SRAM256K : Power ON only lower 256k (addr: 0x10010000 - 0x1004FFFF)       */
27402   PWRCTRL_MEMPWREN_SRAM_SRAM512K       = 255,   /*!< SRAM512K : Power ON only lower 512k (addr: 0x10010000 - 0x1008FFFF)       */
27403   PWRCTRL_MEMPWREN_SRAM_ALL            = 1023,  /*!< ALL : All SRAM banks (704K) powered ON (addr: 0x10010000 - 0x100BFFFF)    */
27404 } PWRCTRL_MEMPWREN_SRAM_Enum;
27405 
27406 /* =============================================  PWRCTRL MEMPWREN DTCM [0..2]  ============================================== */
27407 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_DTCM                                                     */
27408   PWRCTRL_MEMPWREN_DTCM_NONE           = 0,     /*!< NONE : Do not enable power to any DTCMs                                   */
27409   PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0    = 1,     /*!< GROUP0DTCM0 : Power ON only 8KB GROUP0_DTCM0 (0 - 8KB, addr:
27410                                                      0x10000000 - 0x10001FFF)                                                  */
27411   PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM1    = 2,     /*!< GROUP0DTCM1 : Power ON only 24KB GROUP0_DTCM1 (8KB - 32KB, addr:
27412                                                      0x10002000 - 0x10007FFF)                                                  */
27413   PWRCTRL_MEMPWREN_DTCM_GROUP0         = 3,     /*!< GROUP0 : Power ON only DTCMs in 32KB group0 (0 - 32KB, addr:
27414                                                      0x10000000 - 0x10007FFF)                                                  */
27415   PWRCTRL_MEMPWREN_DTCM_GROUP1         = 4,     /*!< GROUP1 : Power ON only DTCMs in 32KB group1 (32KB - 64KB, addr:
27416                                                      0x10008000 - 0x1000FFFF)                                                  */
27417   PWRCTRL_MEMPWREN_DTCM_ALL            = 7,     /*!< ALL : Power ON all DTCMs (0 - 64KB, addr: 0x10000000 - 0x1000FFFF)        */
27418 } PWRCTRL_MEMPWREN_DTCM_Enum;
27419 
27420 /* =====================================================  MEMPWRSTATUS  ====================================================== */
27421 /* =====================================================  DEVPWRSTATUS  ====================================================== */
27422 /* =======================================================  SRAMCTRL  ======================================================== */
27423 /* ========================================  PWRCTRL SRAMCTRL SRAMLIGHTSLEEP [8..19]  ======================================== */
27424 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP                                           */
27425   PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_ALL  = 255,   /*!< ALL : Enable LIGHT SLEEP for ALL SRAMs                                    */
27426   PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_DIS  = 0,     /*!< DIS : Disables LIGHT SLEEP for ALL SRAMs                                  */
27427 } PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Enum;
27428 
27429 /* =======================================  PWRCTRL SRAMCTRL SRAMMASTERCLKGATE [2..2]  ======================================= */
27430 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE                                        */
27431   PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_EN = 1,    /*!< EN : Enable Master SRAM Clock Gate                                        */
27432   PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_DIS = 0,   /*!< DIS : Disables Master SRAM Clock Gating                                   */
27433 } PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Enum;
27434 
27435 /* ==========================================  PWRCTRL SRAMCTRL SRAMCLKGATE [1..1]  ========================================== */
27436 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMCLKGATE                                              */
27437   PWRCTRL_SRAMCTRL_SRAMCLKGATE_EN      = 1,     /*!< EN : Enable Individual SRAM Clock Gating                                  */
27438   PWRCTRL_SRAMCTRL_SRAMCLKGATE_DIS     = 0,     /*!< DIS : Disables Individual SRAM Clock Gating                               */
27439 } PWRCTRL_SRAMCTRL_SRAMCLKGATE_Enum;
27440 
27441 /* =======================================================  ADCSTATUS  ======================================================= */
27442 /* =========================================================  MISC  ========================================================== */
27443 /* ============================================  PWRCTRL MISC MEMVRLPBLE [6..6]  ============================================= */
27444 typedef enum {                                  /*!< PWRCTRL_MISC_MEMVRLPBLE                                                   */
27445   PWRCTRL_MISC_MEMVRLPBLE_EN           = 1,     /*!< EN : Mem VR can go to lp mode even when BLE is powered on.                */
27446   PWRCTRL_MISC_MEMVRLPBLE_DIS          = 0,     /*!< DIS : Mem VR will stay in active mode when BLE is powered on.             */
27447 } PWRCTRL_MISC_MEMVRLPBLE_Enum;
27448 
27449 /* ============================================  PWRCTRL MISC SIMOBUCKEN [0..0]  ============================================= */
27450 typedef enum {                                  /*!< PWRCTRL_MISC_SIMOBUCKEN                                                   */
27451   PWRCTRL_MISC_SIMOBUCKEN_EN           = 1,     /*!< EN : Enable the SIMO Buck                                                 */
27452   PWRCTRL_MISC_SIMOBUCKEN_DIS          = 0,     /*!< DIS : Disable the SIMO Buck                                               */
27453 } PWRCTRL_MISC_SIMOBUCKEN_Enum;
27454 
27455 /* =====================================================  DEVPWREVENTEN  ===================================================== */
27456 /* =======================================  PWRCTRL DEVPWREVENTEN BURSTEVEN [31..31]  ======================================== */
27457 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_BURSTEVEN                                           */
27458   PWRCTRL_DEVPWREVENTEN_BURSTEVEN_EN   = 1,     /*!< EN : Enable BURST status event                                            */
27459   PWRCTRL_DEVPWREVENTEN_BURSTEVEN_DIS  = 0,     /*!< DIS : Disable BURST status event                                          */
27460 } PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Enum;
27461 
27462 /* ====================================  PWRCTRL DEVPWREVENTEN BURSTFEATUREEVEN [30..30]  ==================================== */
27463 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN                                    */
27464   PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_EN = 1,/*!< EN : Enable BURSTFEATURE status event                                     */
27465   PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_DIS = 0,/*!< DIS : Disable BURSTFEATURE status event                                  */
27466 } PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Enum;
27467 
27468 /* =====================================  PWRCTRL DEVPWREVENTEN BLEFEATUREEVEN [29..29]  ===================================== */
27469 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN                                      */
27470   PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_EN = 1,  /*!< EN : Enable BLEFEATURE status event                                       */
27471   PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_DIS = 0, /*!< DIS : Disable BLEFEATURE status event                                     */
27472 } PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Enum;
27473 
27474 /* =========================================  PWRCTRL DEVPWREVENTEN BLELEVEN [8..8]  ========================================= */
27475 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_BLELEVEN                                            */
27476   PWRCTRL_DEVPWREVENTEN_BLELEVEN_EN    = 1,     /*!< EN : Enable BLE power-on status event                                     */
27477   PWRCTRL_DEVPWREVENTEN_BLELEVEN_DIS   = 0,     /*!< DIS : Disable BLE power-on status event                                   */
27478 } PWRCTRL_DEVPWREVENTEN_BLELEVEN_Enum;
27479 
27480 /* =========================================  PWRCTRL DEVPWREVENTEN PDMEVEN [7..7]  ========================================== */
27481 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_PDMEVEN                                             */
27482   PWRCTRL_DEVPWREVENTEN_PDMEVEN_EN     = 1,     /*!< EN : Enable PDM power-on status event                                     */
27483   PWRCTRL_DEVPWREVENTEN_PDMEVEN_DIS    = 0,     /*!< DIS : Disable PDM power-on status event                                   */
27484 } PWRCTRL_DEVPWREVENTEN_PDMEVEN_Enum;
27485 
27486 /* =========================================  PWRCTRL DEVPWREVENTEN MSPIEVEN [6..6]  ========================================= */
27487 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MSPIEVEN                                            */
27488   PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN    = 1,     /*!< EN : Enable MSPI power-on status event                                    */
27489   PWRCTRL_DEVPWREVENTEN_MSPIEVEN_DIS   = 0,     /*!< DIS : Disable MSPI power-on status event                                  */
27490 } PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Enum;
27491 
27492 /* =========================================  PWRCTRL DEVPWREVENTEN ADCEVEN [5..5]  ========================================== */
27493 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_ADCEVEN                                             */
27494   PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN     = 1,     /*!< EN : Enable ADC power-on status event                                     */
27495   PWRCTRL_DEVPWREVENTEN_ADCEVEN_DIS    = 0,     /*!< DIS : Disable ADC power-on status event                                   */
27496 } PWRCTRL_DEVPWREVENTEN_ADCEVEN_Enum;
27497 
27498 /* =========================================  PWRCTRL DEVPWREVENTEN HCPCEVEN [4..4]  ========================================= */
27499 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPCEVEN                                            */
27500   PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN    = 1,     /*!< EN : Enable HCPC power-on status event                                    */
27501   PWRCTRL_DEVPWREVENTEN_HCPCEVEN_DIS   = 0,     /*!< DIS : Disable HCPC power-on status event                                  */
27502 } PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Enum;
27503 
27504 /* =========================================  PWRCTRL DEVPWREVENTEN HCPBEVEN [3..3]  ========================================= */
27505 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPBEVEN                                            */
27506   PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN    = 1,     /*!< EN : Enable HCPB power-on status event                                    */
27507   PWRCTRL_DEVPWREVENTEN_HCPBEVEN_DIS   = 0,     /*!< DIS : Disable HCPB power-on status event                                  */
27508 } PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Enum;
27509 
27510 /* =========================================  PWRCTRL DEVPWREVENTEN HCPAEVEN [2..2]  ========================================= */
27511 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPAEVEN                                            */
27512   PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN    = 1,     /*!< EN : Enable HCPA power-on status event                                    */
27513   PWRCTRL_DEVPWREVENTEN_HCPAEVEN_DIS   = 0,     /*!< DIS : Disable HCPA power-on status event                                  */
27514 } PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Enum;
27515 
27516 /* =========================================  PWRCTRL DEVPWREVENTEN MCUHEVEN [1..1]  ========================================= */
27517 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MCUHEVEN                                            */
27518   PWRCTRL_DEVPWREVENTEN_MCUHEVEN_EN    = 1,     /*!< EN : Enable MCHU power-on status event                                    */
27519   PWRCTRL_DEVPWREVENTEN_MCUHEVEN_DIS   = 0,     /*!< DIS : Disable MCUH power-on status event                                  */
27520 } PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Enum;
27521 
27522 /* =========================================  PWRCTRL DEVPWREVENTEN MCULEVEN [0..0]  ========================================= */
27523 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MCULEVEN                                            */
27524   PWRCTRL_DEVPWREVENTEN_MCULEVEN_EN    = 1,     /*!< EN : Enable MCUL power-on status event                                    */
27525   PWRCTRL_DEVPWREVENTEN_MCULEVEN_DIS   = 0,     /*!< DIS : Disable MCUL power-on status event                                  */
27526 } PWRCTRL_DEVPWREVENTEN_MCULEVEN_Enum;
27527 
27528 /* =====================================================  MEMPWREVENTEN  ===================================================== */
27529 /* =======================================  PWRCTRL MEMPWREVENTEN CACHEB2EN [31..31]  ======================================== */
27530 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_CACHEB2EN                                           */
27531   PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN   = 1,     /*!< EN : Enable CACHE BANK 2 status event                                     */
27532   PWRCTRL_MEMPWREVENTEN_CACHEB2EN_DIS  = 0,     /*!< DIS : Disable CACHE BANK 2 status event                                   */
27533 } PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Enum;
27534 
27535 /* =======================================  PWRCTRL MEMPWREVENTEN CACHEB0EN [30..30]  ======================================== */
27536 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_CACHEB0EN                                           */
27537   PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN   = 1,     /*!< EN : Enable CACHE BANK 0 status event                                     */
27538   PWRCTRL_MEMPWREVENTEN_CACHEB0EN_DIS  = 0,     /*!< DIS : Disable CACHE BANK 0 status event                                   */
27539 } PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Enum;
27540 
27541 /* ========================================  PWRCTRL MEMPWREVENTEN FLASH1EN [14..14]  ======================================== */
27542 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_FLASH1EN                                            */
27543   PWRCTRL_MEMPWREVENTEN_FLASH1EN_EN    = 1,     /*!< EN : Enable FLASH status event                                            */
27544   PWRCTRL_MEMPWREVENTEN_FLASH1EN_DIS   = 0,     /*!< DIS : Disables FLASH status event                                         */
27545 } PWRCTRL_MEMPWREVENTEN_FLASH1EN_Enum;
27546 
27547 /* ========================================  PWRCTRL MEMPWREVENTEN FLASH0EN [13..13]  ======================================== */
27548 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_FLASH0EN                                            */
27549   PWRCTRL_MEMPWREVENTEN_FLASH0EN_EN    = 1,     /*!< EN : Enable FLASH status event                                            */
27550   PWRCTRL_MEMPWREVENTEN_FLASH0EN_DIS   = 0,     /*!< DIS : Disables FLASH status event                                         */
27551 } PWRCTRL_MEMPWREVENTEN_FLASH0EN_Enum;
27552 
27553 /* =========================================  PWRCTRL MEMPWREVENTEN SRAMEN [3..12]  ========================================== */
27554 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_SRAMEN                                              */
27555   PWRCTRL_MEMPWREVENTEN_SRAMEN_NONE    = 0,     /*!< NONE : Disable SRAM power-on status event                                 */
27556   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP0EN = 1,    /*!< GROUP0EN : Enable SRAM group0 (0KB-32KB) power on status event            */
27557   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP1EN = 2,    /*!< GROUP1EN : Enable SRAM group1 (32KB-64KB) power on status event           */
27558   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP2EN = 4,    /*!< GROUP2EN : Enable SRAM group2 (64KB-96KB) power on status event           */
27559   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP3EN = 8,    /*!< GROUP3EN : Enable SRAM group3 (96KB-128KB) power on status event          */
27560   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP4EN = 16,   /*!< GROUP4EN : Enable SRAM group4 (128KB-160KB) power on status
27561                                                      event                                                                     */
27562   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP5EN = 32,   /*!< GROUP5EN : Enable SRAM group5 (160KB-192KB) power on status
27563                                                      event                                                                     */
27564   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP6EN = 64,   /*!< GROUP6EN : Enable SRAM group6 (192KB-224KB) power on status
27565                                                      event                                                                     */
27566   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP7EN = 128,  /*!< GROUP7EN : Enable SRAM group7 (224KB-256KB) power on status
27567                                                      event                                                                     */
27568   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP8EN = 256,  /*!< GROUP8EN : Enable SRAM group8 (256KB-288KB) power on status
27569                                                      event                                                                     */
27570   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP9EN = 512,  /*!< GROUP9EN : Enable SRAM group9 (288KB-320KB) power on status
27571                                                      event                                                                     */
27572 } PWRCTRL_MEMPWREVENTEN_SRAMEN_Enum;
27573 
27574 /* ==========================================  PWRCTRL MEMPWREVENTEN DTCMEN [0..2]  ========================================== */
27575 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_DTCMEN                                              */
27576   PWRCTRL_MEMPWREVENTEN_DTCMEN_NONE    = 0,     /*!< NONE : Do not enable DTCM power-on status event                           */
27577   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN = 1,/*!< GROUP0DTCM0EN : Enable GROUP0_DTCM0 power on status event                */
27578   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM1EN = 2,/*!< GROUP0DTCM1EN : Enable GROUP0_DTCM1 power on status event                */
27579   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN = 3,    /*!< GROUP0EN : Enable DTCMs in group0 power on status event                   */
27580   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP1EN = 4,    /*!< GROUP1EN : Enable DTCMs in group1 power on status event                   */
27581   PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL     = 7,     /*!< ALL : Enable all DTCM power on status event                               */
27582 } PWRCTRL_MEMPWREVENTEN_DTCMEN_Enum;
27583 
27584 
27585 
27586 /* =========================================================================================================================== */
27587 /* ================                                          RSTGEN                                           ================ */
27588 /* =========================================================================================================================== */
27589 
27590 /* ==========================================================  CFG  ========================================================== */
27591 /* =========================================================  SWPOI  ========================================================= */
27592 /* =============================================  RSTGEN SWPOI SWPOIKEY [0..7]  ============================================== */
27593 typedef enum {                                  /*!< RSTGEN_SWPOI_SWPOIKEY                                                     */
27594   RSTGEN_SWPOI_SWPOIKEY_KEYVALUE       = 27,    /*!< KEYVALUE : Writing 0x1B key value generates a software POI reset.         */
27595 } RSTGEN_SWPOI_SWPOIKEY_Enum;
27596 
27597 /* =========================================================  SWPOR  ========================================================= */
27598 /* =============================================  RSTGEN SWPOR SWPORKEY [0..7]  ============================================== */
27599 typedef enum {                                  /*!< RSTGEN_SWPOR_SWPORKEY                                                     */
27600   RSTGEN_SWPOR_SWPORKEY_KEYVALUE       = 212,   /*!< KEYVALUE : Writing 0xD4 key value generates a software POR reset.         */
27601 } RSTGEN_SWPOR_SWPORKEY_Enum;
27602 
27603 /* ========================================================  TPIURST  ======================================================== */
27604 /* =========================================================  INTEN  ========================================================= */
27605 /* ========================================================  INTSTAT  ======================================================== */
27606 /* ========================================================  INTCLR  ========================================================= */
27607 /* ========================================================  INTSET  ========================================================= */
27608 /* =========================================================  STAT  ========================================================== */
27609 
27610 
27611 /* =========================================================================================================================== */
27612 /* ================                                            RTC                                            ================ */
27613 /* =========================================================================================================================== */
27614 
27615 /* ========================================================  CTRLOW  ========================================================= */
27616 /* =========================================================  CTRUP  ========================================================= */
27617 /* ===============================================  RTC CTRUP CTERR [31..31]  ================================================ */
27618 typedef enum {                                  /*!< RTC_CTRUP_CTERR                                                           */
27619   RTC_CTRUP_CTERR_NOERR                = 0,     /*!< NOERR : No read error occurred                                            */
27620   RTC_CTRUP_CTERR_RDERR                = 1,     /*!< RDERR : Read error occurred                                               */
27621 } RTC_CTRUP_CTERR_Enum;
27622 
27623 /* ================================================  RTC CTRUP CEB [28..28]  ================================================= */
27624 typedef enum {                                  /*!< RTC_CTRUP_CEB                                                             */
27625   RTC_CTRUP_CEB_DIS                    = 0,     /*!< DIS : Disable the Century bit from changing                               */
27626   RTC_CTRUP_CEB_EN                     = 1,     /*!< EN : Enable the Century bit to change                                     */
27627 } RTC_CTRUP_CEB_Enum;
27628 
27629 /* =================================================  RTC CTRUP CB [27..27]  ================================================= */
27630 typedef enum {                                  /*!< RTC_CTRUP_CB                                                              */
27631   RTC_CTRUP_CB_2000                    = 0,     /*!< 2000 : Century is 2000s                                                   */
27632   RTC_CTRUP_CB_1900_2100               = 1,     /*!< 1900_2100 : Century is 1900s/2100s                                        */
27633 } RTC_CTRUP_CB_Enum;
27634 
27635 /* ========================================================  ALMLOW  ========================================================= */
27636 /* =========================================================  ALMUP  ========================================================= */
27637 /* ========================================================  RTCCTL  ========================================================= */
27638 /* ===============================================  RTC RTCCTL HR1224 [5..5]  ================================================ */
27639 typedef enum {                                  /*!< RTC_RTCCTL_HR1224                                                         */
27640   RTC_RTCCTL_HR1224_24HR               = 0,     /*!< 24HR : Hours in 24 hour mode                                              */
27641   RTC_RTCCTL_HR1224_12HR               = 1,     /*!< 12HR : Hours in 12 hour mode                                              */
27642 } RTC_RTCCTL_HR1224_Enum;
27643 
27644 /* ================================================  RTC RTCCTL RSTOP [4..4]  ================================================ */
27645 typedef enum {                                  /*!< RTC_RTCCTL_RSTOP                                                          */
27646   RTC_RTCCTL_RSTOP_RUN                 = 0,     /*!< RUN : Allow the RTC input clock to run                                    */
27647   RTC_RTCCTL_RSTOP_STOP                = 1,     /*!< STOP : Stop the RTC input clock                                           */
27648 } RTC_RTCCTL_RSTOP_Enum;
27649 
27650 /* =================================================  RTC RTCCTL RPT [1..3]  ================================================= */
27651 typedef enum {                                  /*!< RTC_RTCCTL_RPT                                                            */
27652   RTC_RTCCTL_RPT_DIS                   = 0,     /*!< DIS : Alarm interrupt disabled                                            */
27653   RTC_RTCCTL_RPT_YEAR                  = 1,     /*!< YEAR : Interrupt every year                                               */
27654   RTC_RTCCTL_RPT_MONTH                 = 2,     /*!< MONTH : Interrupt every month                                             */
27655   RTC_RTCCTL_RPT_WEEK                  = 3,     /*!< WEEK : Interrupt every week                                               */
27656   RTC_RTCCTL_RPT_DAY                   = 4,     /*!< DAY : Interrupt every day                                                 */
27657   RTC_RTCCTL_RPT_HR                    = 5,     /*!< HR : Interrupt every hour                                                 */
27658   RTC_RTCCTL_RPT_MIN                   = 6,     /*!< MIN : Interrupt every minute                                              */
27659   RTC_RTCCTL_RPT_SEC                   = 7,     /*!< SEC : Interrupt every second/10th/100th                                   */
27660 } RTC_RTCCTL_RPT_Enum;
27661 
27662 /* ================================================  RTC RTCCTL WRTC [0..0]  ================================================= */
27663 typedef enum {                                  /*!< RTC_RTCCTL_WRTC                                                           */
27664   RTC_RTCCTL_WRTC_DIS                  = 0,     /*!< DIS : Counter writes are disabled                                         */
27665   RTC_RTCCTL_WRTC_EN                   = 1,     /*!< EN : Counter writes are enabled                                           */
27666 } RTC_RTCCTL_WRTC_Enum;
27667 
27668 /* =========================================================  INTEN  ========================================================= */
27669 /* ========================================================  INTSTAT  ======================================================== */
27670 /* ========================================================  INTCLR  ========================================================= */
27671 /* ========================================================  INTSET  ========================================================= */
27672 
27673 
27674 /* =========================================================================================================================== */
27675 /* ================                                           SCARD                                           ================ */
27676 /* =========================================================================================================================== */
27677 
27678 /* ==========================================================  SR  =========================================================== */
27679 /* ==================================================  SCARD SR FHF [6..6]  ================================================== */
27680 typedef enum {                                  /*!< SCARD_SR_FHF                                                              */
27681   SCARD_SR_FHF_HALFFULL                = 1,     /*!< HALFFULL : FIFO is half full.                                             */
27682 } SCARD_SR_FHF_Enum;
27683 
27684 /* ================================================  SCARD SR FT2REND [5..5]  ================================================ */
27685 typedef enum {                                  /*!< SCARD_SR_FT2REND                                                          */
27686   SCARD_SR_FT2REND_CMPL                = 1,     /*!< CMPL : TX to RX completed.                                                */
27687   SCARD_SR_FT2REND_NOTCMPL             = 0,     /*!< NOTCMPL : TX to RX not completed.                                         */
27688 } SCARD_SR_FT2REND_Enum;
27689 
27690 /* ==================================================  SCARD SR PE [4..4]  =================================================== */
27691 typedef enum {                                  /*!< SCARD_SR_PE                                                               */
27692   SCARD_SR_PE_PEERR                    = 1,     /*!< PEERR : Parity error.                                                     */
27693   SCARD_SR_PE_PENONE                   = 0,     /*!< PENONE : No parity error.                                                 */
27694 } SCARD_SR_PE_Enum;
27695 
27696 /* ==================================================  SCARD SR OVR [3..3]  ================================================== */
27697 typedef enum {                                  /*!< SCARD_SR_OVR                                                              */
27698   SCARD_SR_OVR_RXOVR                   = 1,     /*!< RXOVR : RX FIFO overflow.                                                 */
27699   SCARD_SR_OVR_RXOVRNONE               = 0,     /*!< RXOVRNONE : RX FIFO no overflow.                                          */
27700 } SCARD_SR_OVR_Enum;
27701 
27702 /* ==================================================  SCARD SR FER [2..2]  ================================================== */
27703 typedef enum {                                  /*!< SCARD_SR_FER                                                              */
27704   SCARD_SR_FER_FRAMINGERR              = 1,     /*!< FRAMINGERR : Framing error.                                               */
27705   SCARD_SR_FER_NOFRAMINGERR            = 0,     /*!< NOFRAMINGERR : No framing error detected.                                 */
27706 } SCARD_SR_FER_Enum;
27707 
27708 /* ================================================  SCARD SR TBERBF [1..1]  ================================================= */
27709 typedef enum {                                  /*!< SCARD_SR_TBERBF                                                           */
27710   SCARD_SR_TBERBF_TXFIFOEMPTY          = 1,     /*!< TXFIFOEMPTY : Transmit: FIFO empty.                                       */
27711   SCARD_SR_TBERBF_TXFIFONOTEMPTY       = 0,     /*!< TXFIFONOTEMPTY : Transmit: FIFO not empty.                                */
27712 } SCARD_SR_TBERBF_Enum;
27713 
27714 /* ==================================================  SCARD SR FNE [0..0]  ================================================== */
27715 typedef enum {                                  /*!< SCARD_SR_FNE                                                              */
27716   SCARD_SR_FNE_NOTEMPTY                = 1,     /*!< NOTEMPTY : RX FIFO not empty.                                             */
27717   SCARD_SR_FNE_EMPTY                   = 0,     /*!< EMPTY : RX FIFO empty.                                                    */
27718 } SCARD_SR_FNE_Enum;
27719 
27720 /* ==========================================================  IER  ========================================================== */
27721 /* ==========================================================  TCR  ========================================================== */
27722 /* ==========================================================  UCR  ========================================================== */
27723 /* ==========================================================  DR  =========================================================== */
27724 /* =========================================================  BPRL  ========================================================== */
27725 /* =========================================================  BPRH  ========================================================== */
27726 /* =========================================================  UCR1  ========================================================== */
27727 /* ==========================================================  SR1  ========================================================== */
27728 /* =================================================  SCARD SR1 IDLE [3..3]  ================================================= */
27729 typedef enum {                                  /*!< SCARD_SR1_IDLE                                                            */
27730   SCARD_SR1_IDLE_IDLE                  = 1,     /*!< IDLE : ISO7816 idle.                                                      */
27731   SCARD_SR1_IDLE_ACTIVE                = 0,     /*!< ACTIVE : ISO7816 active.                                                  */
27732 } SCARD_SR1_IDLE_Enum;
27733 
27734 /* ===============================================  SCARD SR1 SYNCEND [2..2]  ================================================ */
27735 typedef enum {                                  /*!< SCARD_SR1_SYNCEND                                                         */
27736   SCARD_SR1_SYNCEND_CMPL               = 1,     /*!< CMPL : Synchronization complete.                                          */
27737   SCARD_SR1_SYNCEND_INCMPL             = 0,     /*!< INCMPL : Incomplete.                                                      */
27738 } SCARD_SR1_SYNCEND_Enum;
27739 
27740 /* =================================================  SCARD SR1 PRL [1..1]  ================================================== */
27741 typedef enum {                                  /*!< SCARD_SR1_PRL                                                             */
27742   SCARD_SR1_PRL_INSREM                 = 1,     /*!< INSREM : Card inserted/removed.                                           */
27743 } SCARD_SR1_PRL_Enum;
27744 
27745 /* ===============================================  SCARD SR1 ECNTOVER [0..0]  =============================================== */
27746 typedef enum {                                  /*!< SCARD_SR1_ECNTOVER                                                        */
27747   SCARD_SR1_ECNTOVER_OVR               = 1,     /*!< OVR : ETU overflow.                                                       */
27748 } SCARD_SR1_ECNTOVER_Enum;
27749 
27750 /* =========================================================  IER1  ========================================================== */
27751 /* =========================================================  ECNTL  ========================================================= */
27752 /* =========================================================  ECNTH  ========================================================= */
27753 /* ==========================================================  GTR  ========================================================== */
27754 /* ========================================================  RETXCNT  ======================================================== */
27755 /* ======================================================  RETXCNTRMI  ======================================================= */
27756 /* ========================================================  CLKCTRL  ======================================================== */
27757 
27758 
27759 /* =========================================================================================================================== */
27760 /* ================                                         SECURITY                                          ================ */
27761 /* =========================================================================================================================== */
27762 
27763 /* =========================================================  CTRL  ========================================================== */
27764 /* =============================================  SECURITY CTRL FUNCTION [4..7]  ============================================= */
27765 typedef enum {                                  /*!< SECURITY_CTRL_FUNCTION                                                    */
27766   SECURITY_CTRL_FUNCTION_CRC32         = 0,     /*!< CRC32 : Perform CRC32 operation                                           */
27767   SECURITY_CTRL_FUNCTION_RAND          = 1,     /*!< RAND : DMA pseudo-random number stream based on CRC value                 */
27768   SECURITY_CTRL_FUNCTION_GENADDR       = 2,     /*!< GENADDR : Generate DMA stream based on address                            */
27769 } SECURITY_CTRL_FUNCTION_Enum;
27770 
27771 /* ========================================================  SRCADDR  ======================================================== */
27772 /* ==========================================================  LEN  ========================================================== */
27773 /* ========================================================  RESULT  ========================================================= */
27774 /* =======================================================  LOCKCTRL  ======================================================== */
27775 /* ============================================  SECURITY LOCKCTRL SELECT [0..7]  ============================================ */
27776 typedef enum {                                  /*!< SECURITY_LOCKCTRL_SELECT                                                  */
27777   SECURITY_LOCKCTRL_SELECT_CUSTOMER_KEY = 1,    /*!< CUSTOMER_KEY : Unlock Customer Key (access to top half of INFO0)          */
27778   SECURITY_LOCKCTRL_SELECT_NONE        = 0,     /*!< NONE : Lock Control should be set to NONE when not in use.                */
27779 } SECURITY_LOCKCTRL_SELECT_Enum;
27780 
27781 /* =======================================================  LOCKSTAT  ======================================================== */
27782 /* ===========================================  SECURITY LOCKSTAT STATUS [0..31]  ============================================ */
27783 typedef enum {                                  /*!< SECURITY_LOCKSTAT_STATUS                                                  */
27784   SECURITY_LOCKSTAT_STATUS_CUSTOMER_KEY = 1,    /*!< CUSTOMER_KEY : Customer Key is unlocked (access is granted to
27785                                                      top half of INFO0)                                                        */
27786   SECURITY_LOCKSTAT_STATUS_NONE        = 0,     /*!< NONE : No resources are unlocked                                          */
27787 } SECURITY_LOCKSTAT_STATUS_Enum;
27788 
27789 /* =========================================================  KEY0  ========================================================== */
27790 /* =========================================================  KEY1  ========================================================== */
27791 /* =========================================================  KEY2  ========================================================== */
27792 /* =========================================================  KEY3  ========================================================== */
27793 
27794 
27795 /* =========================================================================================================================== */
27796 /* ================                                           UART0                                           ================ */
27797 /* =========================================================================================================================== */
27798 
27799 /* ==========================================================  DR  =========================================================== */
27800 /* ===============================================  UART0 DR OEDATA [11..11]  ================================================ */
27801 typedef enum {                                  /*!< UART0_DR_OEDATA                                                           */
27802   UART0_DR_OEDATA_NOERR                = 0,     /*!< NOERR : No error on UART OEDATA, overrun error indicator.                 */
27803   UART0_DR_OEDATA_ERR                  = 1,     /*!< ERR : Error on UART OEDATA, overrun error indicator.                      */
27804 } UART0_DR_OEDATA_Enum;
27805 
27806 /* ===============================================  UART0 DR BEDATA [10..10]  ================================================ */
27807 typedef enum {                                  /*!< UART0_DR_BEDATA                                                           */
27808   UART0_DR_BEDATA_NOERR                = 0,     /*!< NOERR : No error on UART BEDATA, break error indicator.                   */
27809   UART0_DR_BEDATA_ERR                  = 1,     /*!< ERR : Error on UART BEDATA, break error indicator.                        */
27810 } UART0_DR_BEDATA_Enum;
27811 
27812 /* ================================================  UART0 DR PEDATA [9..9]  ================================================= */
27813 typedef enum {                                  /*!< UART0_DR_PEDATA                                                           */
27814   UART0_DR_PEDATA_NOERR                = 0,     /*!< NOERR : No error on UART PEDATA, parity error indicator.                  */
27815   UART0_DR_PEDATA_ERR                  = 1,     /*!< ERR : Error on UART PEDATA, parity error indicator.                       */
27816 } UART0_DR_PEDATA_Enum;
27817 
27818 /* ================================================  UART0 DR FEDATA [8..8]  ================================================= */
27819 typedef enum {                                  /*!< UART0_DR_FEDATA                                                           */
27820   UART0_DR_FEDATA_NOERR                = 0,     /*!< NOERR : No error on UART FEDATA, framing error indicator.                 */
27821   UART0_DR_FEDATA_ERR                  = 1,     /*!< ERR : Error on UART FEDATA, framing error indicator.                      */
27822 } UART0_DR_FEDATA_Enum;
27823 
27824 /* ==========================================================  RSR  ========================================================== */
27825 /* ================================================  UART0 RSR OESTAT [3..3]  ================================================ */
27826 typedef enum {                                  /*!< UART0_RSR_OESTAT                                                          */
27827   UART0_RSR_OESTAT_NOERR               = 0,     /*!< NOERR : No error on UART OESTAT, overrun error indicator.                 */
27828   UART0_RSR_OESTAT_ERR                 = 1,     /*!< ERR : Error on UART OESTAT, overrun error indicator.                      */
27829 } UART0_RSR_OESTAT_Enum;
27830 
27831 /* ================================================  UART0 RSR BESTAT [2..2]  ================================================ */
27832 typedef enum {                                  /*!< UART0_RSR_BESTAT                                                          */
27833   UART0_RSR_BESTAT_NOERR               = 0,     /*!< NOERR : No error on UART BESTAT, break error indicator.                   */
27834   UART0_RSR_BESTAT_ERR                 = 1,     /*!< ERR : Error on UART BESTAT, break error indicator.                        */
27835 } UART0_RSR_BESTAT_Enum;
27836 
27837 /* ================================================  UART0 RSR PESTAT [1..1]  ================================================ */
27838 typedef enum {                                  /*!< UART0_RSR_PESTAT                                                          */
27839   UART0_RSR_PESTAT_NOERR               = 0,     /*!< NOERR : No error on UART PESTAT, parity error indicator.                  */
27840   UART0_RSR_PESTAT_ERR                 = 1,     /*!< ERR : Error on UART PESTAT, parity error indicator.                       */
27841 } UART0_RSR_PESTAT_Enum;
27842 
27843 /* ================================================  UART0 RSR FESTAT [0..0]  ================================================ */
27844 typedef enum {                                  /*!< UART0_RSR_FESTAT                                                          */
27845   UART0_RSR_FESTAT_NOERR               = 0,     /*!< NOERR : No error on UART FESTAT, framing error indicator.                 */
27846   UART0_RSR_FESTAT_ERR                 = 1,     /*!< ERR : Error on UART FESTAT, framing error indicator.                      */
27847 } UART0_RSR_FESTAT_Enum;
27848 
27849 /* ==========================================================  FR  =========================================================== */
27850 /* =================================================  UART0 FR TXFE [7..7]  ================================================== */
27851 typedef enum {                                  /*!< UART0_FR_TXFE                                                             */
27852   UART0_FR_TXFE_XMTFIFO_EMPTY          = 1,     /*!< XMTFIFO_EMPTY : Transmit FIFO is empty.                                   */
27853 } UART0_FR_TXFE_Enum;
27854 
27855 /* =================================================  UART0 FR RXFF [6..6]  ================================================== */
27856 typedef enum {                                  /*!< UART0_FR_RXFF                                                             */
27857   UART0_FR_RXFF_RCVFIFO_FULL           = 1,     /*!< RCVFIFO_FULL : Receive FIFO is full.                                      */
27858 } UART0_FR_RXFF_Enum;
27859 
27860 /* =================================================  UART0 FR TXFF [5..5]  ================================================== */
27861 typedef enum {                                  /*!< UART0_FR_TXFF                                                             */
27862   UART0_FR_TXFF_XMTFIFO_FULL           = 1,     /*!< XMTFIFO_FULL : Transmit FIFO is full.                                     */
27863 } UART0_FR_TXFF_Enum;
27864 
27865 /* =================================================  UART0 FR RXFE [4..4]  ================================================== */
27866 typedef enum {                                  /*!< UART0_FR_RXFE                                                             */
27867   UART0_FR_RXFE_RCVFIFO_EMPTY          = 1,     /*!< RCVFIFO_EMPTY : Receive FIFO is empty.                                    */
27868 } UART0_FR_RXFE_Enum;
27869 
27870 /* =================================================  UART0 FR BUSY [3..3]  ================================================== */
27871 typedef enum {                                  /*!< UART0_FR_BUSY                                                             */
27872   UART0_FR_BUSY_BUSY                   = 1,     /*!< BUSY : UART busy indicator.                                               */
27873 } UART0_FR_BUSY_Enum;
27874 
27875 /* ==================================================  UART0 FR DCD [2..2]  ================================================== */
27876 typedef enum {                                  /*!< UART0_FR_DCD                                                              */
27877   UART0_FR_DCD_DETECTED                = 1,     /*!< DETECTED : Data carrier detect detected.                                  */
27878 } UART0_FR_DCD_Enum;
27879 
27880 /* ==================================================  UART0 FR DSR [1..1]  ================================================== */
27881 typedef enum {                                  /*!< UART0_FR_DSR                                                              */
27882   UART0_FR_DSR_READY                   = 1,     /*!< READY : Data set ready.                                                   */
27883 } UART0_FR_DSR_Enum;
27884 
27885 /* ==================================================  UART0 FR CTS [0..0]  ================================================== */
27886 typedef enum {                                  /*!< UART0_FR_CTS                                                              */
27887   UART0_FR_CTS_CLEARTOSEND             = 1,     /*!< CLEARTOSEND : Clear to send is indicated.                                 */
27888 } UART0_FR_CTS_Enum;
27889 
27890 /* =========================================================  ILPR  ========================================================== */
27891 /* =========================================================  IBRD  ========================================================== */
27892 /* =========================================================  FBRD  ========================================================== */
27893 /* =========================================================  LCRH  ========================================================== */
27894 /* ==========================================================  CR  =========================================================== */
27895 /* ================================================  UART0 CR CLKSEL [4..6]  ================================================= */
27896 typedef enum {                                  /*!< UART0_CR_CLKSEL                                                           */
27897   UART0_CR_CLKSEL_NOCLK                = 0,     /*!< NOCLK : No UART clock. This is the low power default.                     */
27898   UART0_CR_CLKSEL_24MHZ                = 1,     /*!< 24MHZ : 24 MHz clock.                                                     */
27899   UART0_CR_CLKSEL_12MHZ                = 2,     /*!< 12MHZ : 12 MHz clock.                                                     */
27900   UART0_CR_CLKSEL_6MHZ                 = 3,     /*!< 6MHZ : 6 MHz clock.                                                       */
27901   UART0_CR_CLKSEL_3MHZ                 = 4,     /*!< 3MHZ : 3 MHz clock.                                                       */
27902 } UART0_CR_CLKSEL_Enum;
27903 
27904 /* =========================================================  IFLS  ========================================================== */
27905 /* ==========================================================  IER  ========================================================== */
27906 /* ==========================================================  IES  ========================================================== */
27907 /* ==========================================================  MIS  ========================================================== */
27908 /* ==========================================================  IEC  ========================================================== */
27909 
27910 
27911 /* =========================================================================================================================== */
27912 /* ================                                           VCOMP                                           ================ */
27913 /* =========================================================================================================================== */
27914 
27915 /* ==========================================================  CFG  ========================================================== */
27916 /* ===============================================  VCOMP CFG LVLSEL [16..19]  =============================================== */
27917 typedef enum {                                  /*!< VCOMP_CFG_LVLSEL                                                          */
27918   VCOMP_CFG_LVLSEL_0P58V               = 0,     /*!< 0P58V : Set Reference input to 0.58 Volts.                                */
27919   VCOMP_CFG_LVLSEL_0P77V               = 1,     /*!< 0P77V : Set Reference input to 0.77 Volts.                                */
27920   VCOMP_CFG_LVLSEL_0P97V               = 2,     /*!< 0P97V : Set Reference input to 0.97 Volts.                                */
27921   VCOMP_CFG_LVLSEL_1P16V               = 3,     /*!< 1P16V : Set Reference input to 1.16 Volts.                                */
27922   VCOMP_CFG_LVLSEL_1P35V               = 4,     /*!< 1P35V : Set Reference input to 1.35 Volts.                                */
27923   VCOMP_CFG_LVLSEL_1P55V               = 5,     /*!< 1P55V : Set Reference input to 1.55 Volts.                                */
27924   VCOMP_CFG_LVLSEL_1P74V               = 6,     /*!< 1P74V : Set Reference input to 1.74 Volts.                                */
27925   VCOMP_CFG_LVLSEL_1P93V               = 7,     /*!< 1P93V : Set Reference input to 1.93 Volts.                                */
27926   VCOMP_CFG_LVLSEL_2P13V               = 8,     /*!< 2P13V : Set Reference input to 2.13 Volts.                                */
27927   VCOMP_CFG_LVLSEL_2P32V               = 9,     /*!< 2P32V : Set Reference input to 2.32 Volts.                                */
27928   VCOMP_CFG_LVLSEL_2P51V               = 10,    /*!< 2P51V : Set Reference input to 2.51 Volts.                                */
27929   VCOMP_CFG_LVLSEL_2P71V               = 11,    /*!< 2P71V : Set Reference input to 2.71 Volts.                                */
27930   VCOMP_CFG_LVLSEL_2P90V               = 12,    /*!< 2P90V : Set Reference input to 2.90 Volts.                                */
27931   VCOMP_CFG_LVLSEL_3P09V               = 13,    /*!< 3P09V : Set Reference input to 3.09 Volts.                                */
27932   VCOMP_CFG_LVLSEL_3P29V               = 14,    /*!< 3P29V : Set Reference input to 3.29 Volts.                                */
27933   VCOMP_CFG_LVLSEL_3P48V               = 15,    /*!< 3P48V : Set Reference input to 3.48 Volts.                                */
27934 } VCOMP_CFG_LVLSEL_Enum;
27935 
27936 /* =================================================  VCOMP CFG NSEL [8..9]  ================================================= */
27937 typedef enum {                                  /*!< VCOMP_CFG_NSEL                                                            */
27938   VCOMP_CFG_NSEL_VREFEXT1              = 0,     /*!< VREFEXT1 : Use external reference 1 for reference input.                  */
27939   VCOMP_CFG_NSEL_VREFEXT2              = 1,     /*!< VREFEXT2 : Use external reference 2 for reference input.                  */
27940   VCOMP_CFG_NSEL_VREFEXT3              = 2,     /*!< VREFEXT3 : Use external reference 3 for reference input.                  */
27941   VCOMP_CFG_NSEL_DAC                   = 3,     /*!< DAC : Use DAC output selected by LVLSEL for reference input.              */
27942 } VCOMP_CFG_NSEL_Enum;
27943 
27944 /* =================================================  VCOMP CFG PSEL [0..1]  ================================================= */
27945 typedef enum {                                  /*!< VCOMP_CFG_PSEL                                                            */
27946   VCOMP_CFG_PSEL_VDDADJ                = 0,     /*!< VDDADJ : Use VDDADJ for the positive input.                               */
27947   VCOMP_CFG_PSEL_VTEMP                 = 1,     /*!< VTEMP : Use the temperature sensor output for the positive input.
27948                                                      Note: If this channel is selected for PSEL, the bandgap
27949                                                      circuit required for temperature comparisons will automatically
27950                                                      turn on. The bandgap circuit requires 11 us to stabilize.                 */
27951   VCOMP_CFG_PSEL_VEXT1                 = 2,     /*!< VEXT1 : Use external voltage 0 for positive input.                        */
27952   VCOMP_CFG_PSEL_VEXT2                 = 3,     /*!< VEXT2 : Use external voltage 1 for positive input.                        */
27953 } VCOMP_CFG_PSEL_Enum;
27954 
27955 /* =========================================================  STAT  ========================================================== */
27956 /* ===============================================  VCOMP STAT PWDSTAT [1..1]  =============================================== */
27957 typedef enum {                                  /*!< VCOMP_STAT_PWDSTAT                                                        */
27958   VCOMP_STAT_PWDSTAT_POWERED_DOWN      = 1,     /*!< POWERED_DOWN : The voltage comparator is powered down.                    */
27959 } VCOMP_STAT_PWDSTAT_Enum;
27960 
27961 /* ===============================================  VCOMP STAT CMPOUT [0..0]  ================================================ */
27962 typedef enum {                                  /*!< VCOMP_STAT_CMPOUT                                                         */
27963   VCOMP_STAT_CMPOUT_VOUT_LOW           = 0,     /*!< VOUT_LOW : The negative input of the comparator is greater than
27964                                                      the positive input.                                                       */
27965   VCOMP_STAT_CMPOUT_VOUT_HIGH          = 1,     /*!< VOUT_HIGH : The positive input of the comparator is greater
27966                                                      than the negative input.                                                  */
27967 } VCOMP_STAT_CMPOUT_Enum;
27968 
27969 /* ========================================================  PWDKEY  ========================================================= */
27970 /* ==============================================  VCOMP PWDKEY PWDKEY [0..31]  ============================================== */
27971 typedef enum {                                  /*!< VCOMP_PWDKEY_PWDKEY                                                       */
27972   VCOMP_PWDKEY_PWDKEY_Key              = 55,    /*!< Key : Key value to unlock the register.                                   */
27973 } VCOMP_PWDKEY_PWDKEY_Enum;
27974 
27975 /* =========================================================  INTEN  ========================================================= */
27976 /* ========================================================  INTSTAT  ======================================================== */
27977 /* ========================================================  INTCLR  ========================================================= */
27978 /* ========================================================  INTSET  ========================================================= */
27979 
27980 
27981 /* =========================================================================================================================== */
27982 /* ================                                            WDT                                            ================ */
27983 /* =========================================================================================================================== */
27984 
27985 /* ==========================================================  CFG  ========================================================== */
27986 /* ================================================  WDT CFG CLKSEL [24..26]  ================================================ */
27987 typedef enum {                                  /*!< WDT_CFG_CLKSEL                                                            */
27988   WDT_CFG_CLKSEL_OFF                   = 0,     /*!< OFF : Low Power Mode. This setting disables the watch dog timer.          */
27989   WDT_CFG_CLKSEL_128HZ                 = 1,     /*!< 128HZ : 128 Hz LFRC clock.                                                */
27990   WDT_CFG_CLKSEL_16HZ                  = 2,     /*!< 16HZ : 16 Hz LFRC clock.                                                  */
27991   WDT_CFG_CLKSEL_1HZ                   = 3,     /*!< 1HZ : 1 Hz LFRC clock.                                                    */
27992   WDT_CFG_CLKSEL_1_16HZ                = 4,     /*!< 1_16HZ : 1/16th Hz LFRC clock.                                            */
27993 } WDT_CFG_CLKSEL_Enum;
27994 
27995 /* =========================================================  RSTRT  ========================================================= */
27996 /* ================================================  WDT RSTRT RSTRT [0..7]  ================================================= */
27997 typedef enum {                                  /*!< WDT_RSTRT_RSTRT                                                           */
27998   WDT_RSTRT_RSTRT_KEYVALUE             = 178,   /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart
27999                                                      the WDT. This is a write only register.                                   */
28000 } WDT_RSTRT_RSTRT_Enum;
28001 
28002 /* =========================================================  LOCK  ========================================================== */
28003 /* =================================================  WDT LOCK LOCK [0..7]  ================================================== */
28004 typedef enum {                                  /*!< WDT_LOCK_LOCK                                                             */
28005   WDT_LOCK_LOCK_KEYVALUE               = 58,    /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock
28006                                                      the WDT.                                                                  */
28007 } WDT_LOCK_LOCK_Enum;
28008 
28009 /* =========================================================  COUNT  ========================================================= */
28010 /* =========================================================  INTEN  ========================================================= */
28011 /* ========================================================  INTSTAT  ======================================================== */
28012 /* ========================================================  INTCLR  ========================================================= */
28013 /* ========================================================  INTSET  ========================================================= */
28014 
28015 /** @} */ /* End of group EnumValue_peripherals */
28016 
28017 
28018 #ifdef __cplusplus
28019 }
28020 #endif
28021 
28022 #endif /* APOLLO3P_H */
28023 
28024 
28025 /** @} */ /* End of group apollo3p */
28026 
28027 /** @} */ /* End of group Ambiq Micro */
28028