1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3  <peripheral>
4    <name>TRIMSIR</name>
5    <description>Trim System Initilazation Registers</description>
6    <baseAddress>0x40105400</baseAddress>
7    <addressBlock>
8      <offset>0x00</offset>
9      <size>0x400</size>
10      <usage>registers</usage>
11    </addressBlock>
12    <registers>
13      <register>
14        <!-- CFG2 -->
15        <name>BB_SIR2</name>
16        <description>System Init. Configuration Register 2.</description>
17        <addressOffset>0x08</addressOffset>
18        <access>read-write</access>
19        <fields>
20          <!-- FIELD 1 Trim IBRO RBIAS -->
21          <field>
22            <name>TRIM_IBRO_RBIAS</name>
23            <description>HIRC8M Trim</description>
24            <bitOffset>0</bitOffset>
25            <bitWidth>6</bitWidth>
26          </field>
27          <!-- FIELD 2 RAM 0 and RAM 1 ECC Enable -->
28          <field>
29            <name>RAM0_1ECCEN</name>
30            <description>RAM 0 and RAM 1 ECC Enable</description>
31            <bitOffset>8</bitOffset>
32            <bitWidth>1</bitWidth>
33            <enumeratedValues>
34              <enumeratedValue>
35                <name>dis</name>
36                <description>ECC Disabled.</description>
37                <value>0</value>
38              </enumeratedValue>
39              <enumeratedValue>
40                <name>en</name>
41                <description>ECC Enabled.</description>
42                <value>1</value>
43              </enumeratedValue>
44            </enumeratedValues>
45          </field>
46          <!-- FIELD 3 RAM 2 ECC Enable -->
47          <field derivedFrom="RAM0_1ECCEN">
48            <name>RAM2ECCEN</name>
49            <description>RAM 2 ECC Enable</description>
50            <bitOffset>9</bitOffset>
51            <bitWidth>1</bitWidth>
52          </field>
53          <!-- FIELD 4 RAM 3 ECC Enable -->
54          <field derivedFrom="RAM0_1ECCEN">
55            <name>RAM3ECCEN</name>
56            <description>RAM 3 ECC Enable</description>
57            <bitOffset>10</bitOffset>
58            <bitWidth>1</bitWidth>
59          </field>
60          <!-- FIELD 5 ICC 0 ECC Enable -->
61          <field derivedFrom="RAM0_1ECCEN">
62            <name>ICC0ECCEN</name>
63            <description>ICC 0 ECC Enable</description>
64            <bitOffset>11</bitOffset>
65            <bitWidth>1</bitWidth>
66          </field>
67          <!-- FIELD 6 FL 0 ECC Enable -->
68          <field derivedFrom="RAM0_1ECCEN">
69            <name>FL0ECCEN</name>
70            <description>Flash 0 ECC Enable</description>
71            <bitOffset>12</bitOffset>
72            <bitWidth>1</bitWidth>
73          </field>
74          <!-- FIELD 7 FL 1 ECC Enable -->
75          <field derivedFrom="RAM0_1ECCEN">
76            <name>FL1ECCEN</name>
77            <description>Flash 1 ECC Enable</description>
78            <bitOffset>13</bitOffset>
79            <bitWidth>1</bitWidth>
80          </field>
81          <!-- FIELD 8 Trim IBRO -->
82          <field>
83            <name>TRIM_IBRO</name>
84            <description>HIRC8M Trim</description>
85            <bitOffset>16</bitOffset>
86            <bitWidth>16</bitWidth>
87          </field>
88        </fields>
89      </register>
90      <register>
91        <!-- CFG3 -->
92        <name>BB_SIR3</name>
93        <description>System Init. Configuration Register 3.</description>
94        <addressOffset>0x0C</addressOffset>
95        <access>read-write</access>
96      </register>
97      <register>
98        <!-- CFG6 -->
99        <name>BB_SIR6</name>
100        <description>System Init. Configuration Register 6.</description>
101        <addressOffset>0x18</addressOffset>
102        <access>read-only</access>
103        <fields>
104          <!-- FIELD 1 RTCX1 Trim -->
105          <field>
106            <name>RTCX1TRIM</name>
107            <description>RTCX1 Trim</description>
108            <bitOffset>4</bitOffset>
109            <bitWidth>5</bitWidth>
110          </field>
111          <!-- FIELD 2 RTCX1 Trim -->
112          <field>
113            <name>RTCX2TRIM</name>
114            <description>RTCX2 Trim</description>
115            <bitOffset>9</bitOffset>
116            <bitWidth>5</bitWidth>
117          </field>
118        </fields>
119      </register>
120    </registers>
121  </peripheral>
122  <!-- TRIMSIR:Trim System Initilazation Registers -->
123</device>