1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>MCR</name> 5 <description>Misc Control.</description> 6 <baseAddress>0x40106C00</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <!-- RST --> 15 <name>RST</name> 16 <description>Low Power Reset Control Register</description> 17 <addressOffset>0x04</addressOffset> 18 <fields> 19 <field> 20 <name>LPTMR0</name> 21 <description>Low Power Timer0 Reset.</description> 22 <bitOffset>0</bitOffset> 23 <bitWidth>1</bitWidth> 24 <enumeratedValues> 25 <name>reset</name> 26 <usage>read-write</usage> 27 <enumeratedValue> 28 <name>reset_done</name> 29 <description>Reset complete.</description> 30 <value>0</value> 31 </enumeratedValue> 32 <enumeratedValue> 33 <name>busy</name> 34 <description>Starts Reset or indicates reset in progress.</description> 35 <value>1</value> 36 </enumeratedValue> 37 </enumeratedValues> 38 </field> 39 <field derivedFrom="LPTMR0"> 40 <name>LPTMR1</name> 41 <description>Low Power Timer1 Reset.</description> 42 <bitOffset>1</bitOffset> 43 <bitWidth>1</bitWidth> 44 </field> 45 <field derivedFrom="LPTMR0"> 46 <name>LPUART0</name> 47 <description>Low Power UART0 Reset.</description> 48 <bitOffset>2</bitOffset> 49 <bitWidth>1</bitWidth> 50 </field> 51 <field derivedFrom="LPTMR0"> 52 <name>RTC</name> 53 <description>RTC Reset.</description> 54 <bitOffset>3</bitOffset> 55 <bitWidth>1</bitWidth> 56 </field> 57 </fields> 58 </register> 59 <register> 60 <!-- CLKCTRL --> 61 <name>CLKCTRL</name> 62 <description>Clock Control.</description> 63 <addressOffset>0x08</addressOffset> 64 <fields> 65 <field> 66 <name>ERTCO_PD</name> 67 <description>32KHz Crystal Oscillator Power Down.</description> 68 <bitOffset>16</bitOffset> 69 <bitWidth>1</bitWidth> 70 </field> 71 <field> 72 <name>ERTCO_EN</name> 73 <description>32KHz Crystal Oscillator Enable.</description> 74 <bitOffset>17</bitOffset> 75 <bitWidth>1</bitWidth> 76 <enumeratedValues> 77 <enumeratedValue> 78 <name>dis</name> 79 <description>Is Disabled.</description> 80 <value>0</value> 81 </enumeratedValue> 82 <enumeratedValue> 83 <name>en</name> 84 <description>Is Enabled.</description> 85 <value>1</value> 86 </enumeratedValue> 87 </enumeratedValues> 88 </field> 89 </fields> 90 </register> 91 <register> 92 <!-- AINCOMP --> 93 <name>AINCOMP</name> 94 <description>AIN Comparator.</description> 95 <addressOffset>0x0C</addressOffset> 96 <fields> 97 <field> 98 <name>PD</name> 99 <description>AIN Comparator Power Down control.</description> 100 <bitOffset>0</bitOffset> 101 <bitWidth>2</bitWidth> 102 </field> 103 <field> 104 <name>HYST</name> 105 <description>AIN Comparator Hysteresis control.</description> 106 <bitOffset>2</bitOffset> 107 <bitWidth>2</bitWidth> 108 </field> 109 <field> 110 <name>NSEL_COMP0</name> 111 <description>Negative input select for AIN Comparator 0.</description> 112 <bitOffset>16</bitOffset> 113 <bitWidth>4</bitWidth> 114 </field> 115 <field> 116 <name>PSEL_COMP0</name> 117 <description>Positive input select for AIN Comparator 0</description> 118 <bitOffset>20</bitOffset> 119 <bitWidth>4</bitWidth> 120 </field> 121 <field> 122 <name>NSEL_COMP1</name> 123 <description>Negative input select for AIN Comparator 1</description> 124 <bitOffset>24</bitOffset> 125 <bitWidth>4</bitWidth> 126 </field> 127 <field> 128 <name>PSEL_COMP1</name> 129 <description>Positive input select for AIN Comparator 1</description> 130 <bitOffset>28</bitOffset> 131 <bitWidth>4</bitWidth> 132 </field> 133 </fields> 134 </register> 135 <register> 136 <!-- AINCOMP --> 137 <name>LPPIOCTRL</name> 138 <description>Low Power Peripheral IO Control Register.</description> 139 <addressOffset>0x10</addressOffset> 140 <fields> 141 <field> 142 <name>LPTMR0_I</name> 143 <description>Enable control for LPTMR0 input.</description> 144 <bitOffset>0</bitOffset> 145 <bitWidth>1</bitWidth> 146 </field> 147 <field> 148 <name>LPTMR0_O</name> 149 <description>Enable control for LPTMR0 output.</description> 150 <bitOffset>1</bitOffset> 151 <bitWidth>1</bitWidth> 152 </field> 153 <field> 154 <name>LPTMR1_I</name> 155 <description>Enable control for LPTMR1 input.</description> 156 <bitOffset>2</bitOffset> 157 <bitWidth>1</bitWidth> 158 </field> 159 <field> 160 <name>LPTMR1_O</name> 161 <description>Enable control for LPTMR1 output.</description> 162 <bitOffset>3</bitOffset> 163 <bitWidth>1</bitWidth> 164 </field> 165 <field> 166 <name>LPUART0_RX</name> 167 <description>Enable control for LPUART0 RX.</description> 168 <bitOffset>4</bitOffset> 169 <bitWidth>1</bitWidth> 170 </field> 171 <field> 172 <name>LPUART0_TX</name> 173 <description>Enable control for LPUART0 TX.</description> 174 <bitOffset>5</bitOffset> 175 <bitWidth>1</bitWidth> 176 </field> 177 <field> 178 <name>LPUART0_CTS</name> 179 <description>Enable control for LPUART0 CTS.</description> 180 <bitOffset>6</bitOffset> 181 <bitWidth>1</bitWidth> 182 </field> 183 <field> 184 <name>LPUART0_RTS</name> 185 <description>Enable control for LPUART0 RTS.</description> 186 <bitOffset>7</bitOffset> 187 <bitWidth>1</bitWidth> 188 </field> 189 </fields> 190 </register> 191 <register> 192 <!-- PCLKDIS --> 193 <name>PCLKDIS</name> 194 <description>Low Power Peripheral Clock Disable.</description> 195 <addressOffset>0x24</addressOffset> 196 <fields> 197 <field> 198 <name>LPTMR0</name> 199 <description>Low Power Timer0 Clock Disable.</description> 200 <bitOffset>0</bitOffset> 201 <bitWidth>1</bitWidth> 202 <enumeratedValues> 203 <enumeratedValue> 204 <name>en</name> 205 <description>enable it.</description> 206 <value>0</value> 207 </enumeratedValue> 208 <enumeratedValue> 209 <name>dis</name> 210 <description>disable it.</description> 211 <value>1</value> 212 </enumeratedValue> 213 </enumeratedValues> 214 </field> 215 <field derivedFrom="LPTMR0"> 216 <name>LPTMR1</name> 217 <description>Low Power Timer1 Clock Disable.</description> 218 <bitOffset>1</bitOffset> 219 <bitWidth>1</bitWidth> 220 </field> 221 <field derivedFrom="LPTMR0"> 222 <name>LPUART0</name> 223 <description>Low Power UART0 Clock Disable.</description> 224 <bitOffset>2</bitOffset> 225 <bitWidth>1</bitWidth> 226 </field> 227 </fields> 228 </register> 229 <register> 230 <!-- AESKEY --> 231 <name>AESKEY</name> 232 <description>AES Key Pointer and Status.</description> 233 <addressOffset>0x34</addressOffset> 234 <fields> 235 <field> 236 <name>PTR</name> 237 <description>AESKEY Pointer and Status.</description> 238 <bitOffset>0</bitOffset> 239 <bitWidth>16</bitWidth> 240 </field> 241 </fields> 242 </register> 243 <register> 244 <!-- ADC_CFG0 Register --> 245 <name>ADC_CFG0</name> 246 <description>ADC Cfig Register0.</description> 247 <addressOffset>0x38</addressOffset> 248 <fields> 249 <!-- FIELD 1 LP_5K_DIS --> 250 <field> 251 <name>LP_5K_DIS</name> 252 <description>Disable 5K divider option in low power modes</description> 253 <bitOffset>0</bitOffset> 254 <bitWidth>1</bitWidth> 255 <enumeratedValues> 256 <enumeratedValue> 257 <name>en</name> 258 <description>Enable.</description> 259 <value>0</value> 260 </enumeratedValue> 261 <enumeratedValue> 262 <name>dis</name> 263 <description>Disable.</description> 264 <value>1</value> 265 </enumeratedValue> 266 </enumeratedValues> 267 </field> 268 <!-- FIELD 2 LP_50K_DIS --> 269 <field> 270 <name>LP_50K_DIS</name> 271 <description>Disable 50K divider option in low power modes</description> 272 <bitOffset>1</bitOffset> 273 <bitWidth>1</bitWidth> 274 <enumeratedValues> 275 <enumeratedValue> 276 <name>EN</name> 277 <description>Enable.</description> 278 <value>0</value> 279 </enumeratedValue> 280 <enumeratedValue> 281 <name>DIS</name> 282 <description>Disable.</description> 283 <value>1</value> 284 </enumeratedValue> 285 </enumeratedValues> 286 </field> 287 <!-- FIELD 3 EXT_REF --> 288 <field> 289 <name>EXT_REF</name> 290 <description>External Reference</description> 291 <bitOffset>2</bitOffset> 292 <bitWidth>1</bitWidth> 293 </field> 294 <!-- FIELD 4 REF_SEL --> 295 <field> 296 <name>REF_SEL</name> 297 <description>Reference Select</description> 298 <bitOffset>3</bitOffset> 299 <bitWidth>1</bitWidth> 300 </field> 301 </fields> 302 </register> 303 <register> 304 <!-- ADC_CFG1 Register --> 305 <name>ADC_CFG1</name> 306 <description>ADC Config Register1.</description> 307 <addressOffset>0x3C</addressOffset> 308 <fields> 309 <!-- FIELD 1 ADC PU Dynamic Control --> 310 <field> 311 <name>CH0_PU_DYN</name> 312 <description>ADC PU Dynamic Control for CH0</description> 313 <bitOffset>0</bitOffset> 314 <bitWidth>1</bitWidth> 315 <enumeratedValues> 316 <enumeratedValue> 317 <name>dis</name> 318 <description>divider select always used.</description> 319 <value>0</value> 320 </enumeratedValue> 321 <enumeratedValue> 322 <name>en</name> 323 <description>divider select only used when channel is selected.</description> 324 <value>1</value> 325 </enumeratedValue> 326 </enumeratedValues> 327 </field> 328 <field derivedFrom="CH0_PU_DYN"> 329 <name>CH1_PU_DYN</name> 330 <description>ADC PU Dynamic Control for CH1</description> 331 <bitOffset>1</bitOffset> 332 <bitWidth>1</bitWidth> 333 </field> 334 <field derivedFrom="CH0_PU_DYN"> 335 <name>CH2_PU_DYN</name> 336 <description>ADC PU Dynamic Control for CH2</description> 337 <bitOffset>2</bitOffset> 338 <bitWidth>1</bitWidth> 339 </field> 340 <field derivedFrom="CH0_PU_DYN"> 341 <name>CH3_PU_DYN</name> 342 <description>ADC PU Dynamic Control for CH3</description> 343 <bitOffset>3</bitOffset> 344 <bitWidth>1</bitWidth> 345 </field> 346 <field derivedFrom="CH0_PU_DYN"> 347 <name>CH4_PU_DYN</name> 348 <description>ADC PU Dynamic Control for CH4</description> 349 <bitOffset>4</bitOffset> 350 <bitWidth>1</bitWidth> 351 </field> 352 <field derivedFrom="CH0_PU_DYN"> 353 <name>CH5_PU_DYN</name> 354 <description>ADC PU Dynamic Control for CH5</description> 355 <bitOffset>5</bitOffset> 356 <bitWidth>1</bitWidth> 357 </field> 358 <field derivedFrom="CH0_PU_DYN"> 359 <name>CH6_PU_DYN</name> 360 <description>ADC PU Dynamic Control for CH6</description> 361 <bitOffset>6</bitOffset> 362 <bitWidth>1</bitWidth> 363 </field> 364 <field derivedFrom="CH0_PU_DYN"> 365 <name>CH7_PU_DYN</name> 366 <description>ADC PU Dynamic Control for CH7</description> 367 <bitOffset>7</bitOffset> 368 <bitWidth>1</bitWidth> 369 </field> 370 <field derivedFrom="CH0_PU_DYN"> 371 <name>CH8_PU_DYN</name> 372 <description>ADC PU Dynamic Control for CH8</description> 373 <bitOffset>8</bitOffset> 374 <bitWidth>1</bitWidth> 375 </field> 376 <field derivedFrom="CH0_PU_DYN"> 377 <name>CH9_PU_DYN</name> 378 <description>ADC PU Dynamic Control for CH9</description> 379 <bitOffset>9</bitOffset> 380 <bitWidth>1</bitWidth> 381 </field> 382 <field derivedFrom="CH0_PU_DYN"> 383 <name>CH10_PU_DYN</name> 384 <description>ADC PU Dynamic Control for CH10</description> 385 <bitOffset>10</bitOffset> 386 <bitWidth>1</bitWidth> 387 </field> 388 <field derivedFrom="CH0_PU_DYN"> 389 <name>CH11_PU_DYN</name> 390 <description>ADC PU Dynamic Control for CH11</description> 391 <bitOffset>11</bitOffset> 392 <bitWidth>1</bitWidth> 393 </field> 394 <field derivedFrom="CH0_PU_DYN"> 395 <name>CH12_PU_DYN</name> 396 <description>ADC PU Dynamic Control for CH12</description> 397 <bitOffset>12</bitOffset> 398 <bitWidth>1</bitWidth> 399 </field> 400 </fields> 401 </register> 402 <register> 403 <!-- ADC_CFG2 Register --> 404 <name>ADC_CFG2</name> 405 <description>ADC Config Register2.</description> 406 <addressOffset>0x40</addressOffset> 407 <fields> 408 <!-- FIELD 1 ADC Divider select channel 0 --> 409 <field> 410 <name>CH0</name> 411 <description>Divider Select for channel 0</description> 412 <bitOffset>0</bitOffset> 413 <bitWidth>2</bitWidth> 414 <enumeratedValues> 415 <enumeratedValue> 416 <name>div1</name> 417 <description>Pass through, no divider.</description> 418 <value>0</value> 419 </enumeratedValue> 420 <enumeratedValue> 421 <name>div2_5k</name> 422 <description>Divide by 2, 5Kohm.</description> 423 <value>1</value> 424 </enumeratedValue> 425 <enumeratedValue> 426 <name>div2_50k</name> 427 <description>Divide by 2, 50Kohm.</description> 428 <value>2</value> 429 </enumeratedValue> 430 </enumeratedValues> 431 </field> 432 <!-- FIELD 2 ADC Divider select channel 1 --> 433 <field derivedFrom="CH0"> 434 <name>CH1</name> 435 <description>Divider Select for channel 1</description> 436 <bitOffset>2</bitOffset> 437 <bitWidth>2</bitWidth> 438 </field> 439 <!-- FIELD 3 ADC Divider select channel 2 --> 440 <field derivedFrom="CH0"> 441 <name>CH2</name> 442 <description>Divider Select for channel 2</description> 443 <bitOffset>4</bitOffset> 444 <bitWidth>2</bitWidth> 445 </field> 446 <!-- FIELD 4 ADC Divider select channel 3 --> 447 <field derivedFrom="CH0"> 448 <name>CH3</name> 449 <description>Divider Select for channel 3</description> 450 <bitOffset>6</bitOffset> 451 <bitWidth>2</bitWidth> 452 </field> 453 <!-- FIELD 5 ADC Divider select channel 4 --> 454 <field derivedFrom="CH0"> 455 <name>CH4</name> 456 <description>Divider Select for channel 4</description> 457 <bitOffset>8</bitOffset> 458 <bitWidth>2</bitWidth> 459 </field> 460 <!-- FIELD 3 ADC Divider select channel 5 --> 461 <field derivedFrom="CH0"> 462 <name>CH5</name> 463 <description>Divider Select for channel 5</description> 464 <bitOffset>10</bitOffset> 465 <bitWidth>2</bitWidth> 466 </field> 467 <!-- FIELD 4 ADC Divider select channel 6 --> 468 <field derivedFrom="CH0"> 469 <name>CH6</name> 470 <description>Divider Select for channel 6</description> 471 <bitOffset>12</bitOffset> 472 <bitWidth>2</bitWidth> 473 </field> 474 <!-- FIELD 5 ADC Divider select channel 7 --> 475 <field derivedFrom="CH0"> 476 <name>CH7</name> 477 <description>Divider Select for channel 7</description> 478 <bitOffset>14</bitOffset> 479 <bitWidth>2</bitWidth> 480 </field> 481 <!-- FIELD 5 ADC Divider select channel 8 --> 482 <field derivedFrom="CH0"> 483 <name>CH8</name> 484 <description>Divider Select for channel 8</description> 485 <bitOffset>16</bitOffset> 486 <bitWidth>2</bitWidth> 487 </field> 488 <!-- FIELD 3 ADC Divider select channel 9 --> 489 <field derivedFrom="CH0"> 490 <name>CH9</name> 491 <description>Divider Select for channel 9</description> 492 <bitOffset>18</bitOffset> 493 <bitWidth>2</bitWidth> 494 </field> 495 <!-- FIELD 4 ADC Divider select channel 10 --> 496 <field derivedFrom="CH0"> 497 <name>CH10</name> 498 <description>Divider Select for channel 10</description> 499 <bitOffset>20</bitOffset> 500 <bitWidth>2</bitWidth> 501 </field> 502 <!-- FIELD 5 ADC Divider select channel 11 --> 503 <field derivedFrom="CH0"> 504 <name>CH11</name> 505 <description>Divider Select for channel 11</description> 506 <bitOffset>22</bitOffset> 507 <bitWidth>2</bitWidth> 508 </field> 509 <!-- FIELD 5 ADC Divider select channel 12 --> 510 <field derivedFrom="CH0"> 511 <name>CH12</name> 512 <description>Divider Select for channel 12</description> 513 <bitOffset>24</bitOffset> 514 <bitWidth>2</bitWidth> 515 </field> 516 </fields> 517 </register> 518 <register> 519 <!-- ADC_CFG3 Register --> 520 <name>ADC_CFG3</name> 521 <description>ADC Config Register3.</description> 522 <addressOffset>0x44</addressOffset> 523 <fields> 524 <field> 525 <name>VREFM</name> 526 <description>VREFM</description> 527 <bitOffset>0</bitOffset> 528 <bitWidth>7</bitWidth> 529 </field> 530 <field> 531 <name>VREFP</name> 532 <description>VREFP</description> 533 <bitOffset>8</bitOffset> 534 <bitWidth>7</bitWidth> 535 </field> 536 <field> 537 <name>IDRV</name> 538 <description>IDRV</description> 539 <bitOffset>16</bitOffset> 540 <bitWidth>4</bitWidth> 541 </field> 542 <field> 543 <name>VCM</name> 544 <description>VCM</description> 545 <bitOffset>20</bitOffset> 546 <bitWidth>2</bitWidth> 547 </field> 548 <field> 549 <name>ATB</name> 550 <description>ATB</description> 551 <bitOffset>22</bitOffset> 552 <bitWidth>2</bitWidth> 553 </field> 554 <field> 555 <name>D_IBOOST</name> 556 <description>D_IBOOST</description> 557 <bitOffset>24</bitOffset> 558 <bitWidth>1</bitWidth> 559 </field> 560 </fields> 561 </register> 562 </registers> 563 </peripheral> 564 <!-- MCR: MISC Control Register --> 565</device>
