1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>MCR</name> 5 <description>Misc Control.</description> 6 <baseAddress>0x40006C00</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>ECCEN</name> 15 <description>ECC Enable Register</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>RAM0</name> 20 <description>ECC System RAM0 Enable.</description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>1</bitWidth> 23 <enumeratedValues> 24 <enumeratedValue> 25 <name>dis</name> 26 <description>disabled.</description> 27 <value>0</value> 28 </enumeratedValue> 29 <enumeratedValue> 30 <name>en</name> 31 <description>enabled.</description> 32 <value>1</value> 33 </enumeratedValue> 34 </enumeratedValues> 35 </field> 36 <field> 37 <name>RAM1</name> 38 <description>ECC System RAM1 Enable.</description> 39 <bitOffset>1</bitOffset> 40 <bitWidth>1</bitWidth> 41 <enumeratedValues> 42 <enumeratedValue> 43 <name>dis</name> 44 <description>disabled.</description> 45 <value>0</value> 46 </enumeratedValue> 47 <enumeratedValue> 48 <name>en</name> 49 <description>enabled.</description> 50 <value>1</value> 51 </enumeratedValue> 52 </enumeratedValues> 53 </field> 54 <field> 55 <name>RAM2</name> 56 <description>ECC System RAM2 Enable.</description> 57 <bitOffset>2</bitOffset> 58 <bitWidth>1</bitWidth> 59 <enumeratedValues> 60 <enumeratedValue> 61 <name>dis</name> 62 <description>disabled.</description> 63 <value>0</value> 64 </enumeratedValue> 65 <enumeratedValue> 66 <name>en</name> 67 <description>enabled.</description> 68 <value>1</value> 69 </enumeratedValue> 70 </enumeratedValues> 71 </field> 72 <field> 73 <name>RAM3</name> 74 <description>ECC System RAM3 Enable.</description> 75 <bitOffset>3</bitOffset> 76 <bitWidth>1</bitWidth> 77 <enumeratedValues> 78 <enumeratedValue> 79 <name>dis</name> 80 <description>disabled.</description> 81 <value>0</value> 82 </enumeratedValue> 83 <enumeratedValue> 84 <name>en</name> 85 <description>enabled.</description> 86 <value>1</value> 87 </enumeratedValue> 88 </enumeratedValues> 89 </field> 90 <field> 91 <name>RAM4</name> 92 <description>ECC System RAM4 Enable.</description> 93 <bitOffset>4</bitOffset> 94 <bitWidth>1</bitWidth> 95 <enumeratedValues> 96 <enumeratedValue> 97 <name>dis</name> 98 <description>disabled.</description> 99 <value>0</value> 100 </enumeratedValue> 101 <enumeratedValue> 102 <name>en</name> 103 <description>enabled.</description> 104 <value>1</value> 105 </enumeratedValue> 106 </enumeratedValues> 107 </field> 108 <field> 109 <name>RAM5</name> 110 <description>ECC System RAM5 Enable.</description> 111 <bitOffset>5</bitOffset> 112 <bitWidth>1</bitWidth> 113 <enumeratedValues> 114 <enumeratedValue> 115 <name>dis</name> 116 <description>disabled.</description> 117 <value>0</value> 118 </enumeratedValue> 119 <enumeratedValue> 120 <name>en</name> 121 <description>enabled.</description> 122 <value>1</value> 123 </enumeratedValue> 124 </enumeratedValues> 125 </field> 126 <field> 127 <name>RAM6</name> 128 <description>ECC System RAM6 Enable.</description> 129 <bitOffset>6</bitOffset> 130 <bitWidth>1</bitWidth> 131 <enumeratedValues> 132 <enumeratedValue> 133 <name>dis</name> 134 <description>disabled.</description> 135 <value>0</value> 136 </enumeratedValue> 137 <enumeratedValue> 138 <name>en</name> 139 <description>enabled.</description> 140 <value>1</value> 141 </enumeratedValue> 142 </enumeratedValues> 143 </field> 144 <field> 145 <name>ICACHE0</name> 146 <description>ECC ICACHE0 Enable.</description> 147 <bitOffset>8</bitOffset> 148 <bitWidth>1</bitWidth> 149 <enumeratedValues> 150 <enumeratedValue> 151 <name>dis</name> 152 <description>disabled.</description> 153 <value>0</value> 154 </enumeratedValue> 155 <enumeratedValue> 156 <name>en</name> 157 <description>enabled.</description> 158 <value>1</value> 159 </enumeratedValue> 160 </enumeratedValues> 161 </field> 162 <field> 163 <name>ICACHEXIP</name> 164 <description>ECC ICACHE XIP Enable.</description> 165 <bitOffset>10</bitOffset> 166 <bitWidth>1</bitWidth> 167 <enumeratedValues> 168 <enumeratedValue> 169 <name>dis</name> 170 <description>disabled.</description> 171 <value>0</value> 172 </enumeratedValue> 173 <enumeratedValue> 174 <name>en</name> 175 <description>enabled.</description> 176 <value>1</value> 177 </enumeratedValue> 178 </enumeratedValues> 179 </field> 180 </fields> 181 </register> 182 <register> 183 <name>IPO_MTRIM</name> 184 <description>IPO Manual Register</description> 185 <addressOffset>0x04</addressOffset> 186 <fields> 187 <field> 188 <name>MTRIM</name> 189 <description>Manual Trim Value.</description> 190 <bitOffset>0</bitOffset> 191 <bitWidth>8</bitWidth> 192 </field> 193 <field> 194 <name>TRIM_RANGE</name> 195 <description>Trim Range Select.</description> 196 <bitOffset>8</bitOffset> 197 <bitWidth>1</bitWidth> 198 </field> 199 </fields> 200 </register> 201 <register> 202 <name>OUTEN</name> 203 <description>Output Enable Register</description> 204 <addressOffset>0x08</addressOffset> 205 <fields> 206 <field> 207 <name>SQWOUT_EN</name> 208 <description>Square Wave Output Enable.</description> 209 <bitOffset>0</bitOffset> 210 <bitWidth>1</bitWidth> 211 </field> 212 <field> 213 <name>PDOWN_OUT_EN</name> 214 <description>Power Down Output Enable.</description> 215 <bitOffset>1</bitOffset> 216 <bitWidth>1</bitWidth> 217 </field> 218 </fields> 219 </register> 220 <register> 221 <name>CMP_CTRL</name> 222 <description>Comparator Control Register.</description> 223 <addressOffset>0x0C</addressOffset> 224 <fields> 225 <field> 226 <name>EN</name> 227 <description>Comparator Enable.</description> 228 <bitOffset>0</bitOffset> 229 <bitWidth>1</bitWidth> 230 </field> 231 <field> 232 <name>POL</name> 233 <description>Polarity Select</description> 234 <bitOffset>5</bitOffset> 235 <bitWidth>1</bitWidth> 236 </field> 237 <field> 238 <name>INT_EN</name> 239 <description>IRQ Enable.</description> 240 <bitOffset>6</bitOffset> 241 <bitWidth>1</bitWidth> 242 </field> 243 <field> 244 <name>OUT</name> 245 <description>Comparator Output State.</description> 246 <bitOffset>14</bitOffset> 247 <bitWidth>1</bitWidth> 248 </field> 249 <field> 250 <name>INT_FL</name> 251 <description>IRQ Flag</description> 252 <bitOffset>15</bitOffset> 253 <bitWidth>1</bitWidth> 254 </field> 255 </fields> 256 </register> 257 <register> 258 <name>CTRL</name> 259 <description>Miscellaneous Control Register.</description> 260 <addressOffset>0x10</addressOffset> 261 <fields> 262 <field> 263 <name>CMPHYST</name> 264 <description>Comparator HYST.</description> 265 <bitOffset>0</bitOffset> 266 <bitWidth>2</bitWidth> 267 </field> 268 <field> 269 <name>INRO_EN</name> 270 <description>INRO Enable.</description> 271 <bitOffset>2</bitOffset> 272 <bitWidth>1</bitWidth> 273 </field> 274 <field> 275 <name>ERTCO_EN</name> 276 <description>ERTCO Enable.</description> 277 <bitOffset>3</bitOffset> 278 <bitWidth>1</bitWidth> 279 </field> 280 <field> 281 <name>IBRO_EN</name> 282 <description>IBRO Enable.</description> 283 <bitOffset>4</bitOffset> 284 <bitWidth>1</bitWidth> 285 </field> 286 <field> 287 <name>RSTNP1M</name> 288 <description>RSTNP1M</description> 289 <bitOffset>9</bitOffset> 290 <bitWidth>1</bitWidth> 291 </field> 292 <field> 293 <name>RSTNVDDIOHSEL</name> 294 <description>RSTNVFFIOHSEL</description> 295 <bitOffset>10</bitOffset> 296 <bitWidth>1</bitWidth> 297 </field> 298 </fields> 299 </register> 300 <register> 301 <name>GPIO4_CTRL</name> 302 <description>GPIO4 Pin Control Register.</description> 303 <addressOffset>0x20</addressOffset> 304 <fields> 305 <field> 306 <name>P40_DO</name> 307 <description>GPIO4 Pin 0 Data Output.</description> 308 <bitOffset>0</bitOffset> 309 <bitWidth>1</bitWidth> 310 </field> 311 <field> 312 <name>P40_OE</name> 313 <description>GPIO4 Pin 0 Output Enable.</description> 314 <bitOffset>1</bitOffset> 315 <bitWidth>1</bitWidth> 316 </field> 317 <field> 318 <name>P40_PE</name> 319 <description>GPIO4 Pin 0 Pull-up Enable.</description> 320 <bitOffset>2</bitOffset> 321 <bitWidth>1</bitWidth> 322 </field> 323 <field> 324 <name>P40_IN</name> 325 <description>GPIO4 Pin 0 Input Status.</description> 326 <bitOffset>3</bitOffset> 327 <bitWidth>1</bitWidth> 328 </field> 329 <field> 330 <name>P41_DO</name> 331 <description>GPIO4 Pin 1 Data Output.</description> 332 <bitOffset>4</bitOffset> 333 <bitWidth>1</bitWidth> 334 </field> 335 <field> 336 <name>P41_OE</name> 337 <description>GPIO4 Pin 1 Output Enable.</description> 338 <bitOffset>5</bitOffset> 339 <bitWidth>1</bitWidth> 340 </field> 341 <field> 342 <name>P41_PE</name> 343 <description>GPIO4 Pin 1 Pull-up Enable.</description> 344 <bitOffset>6</bitOffset> 345 <bitWidth>1</bitWidth> 346 </field> 347 <field> 348 <name>P41_IN</name> 349 <description>GPIO4 Pin 1 Input Status.</description> 350 <bitOffset>7</bitOffset> 351 <bitWidth>1</bitWidth> 352 </field> 353 </fields> 354 </register> 355 <register> 356 <name>CWD0</name> 357 <description>Code Word Data0</description> 358 <addressOffset>0x40</addressOffset> 359 <fields> 360 <field> 361 <name>data</name> 362 <description>Code word Data0 the register retains its value while vregi supply present</description> 363 <bitOffset>0</bitOffset> 364 <bitWidth>32</bitWidth> 365 </field> 366 </fields> 367 </register> 368 <register> 369 <name>CWD1</name> 370 <description>Code Word Data1</description> 371 <addressOffset>0x44</addressOffset> 372 <fields> 373 <field> 374 <name>data</name> 375 <description>Code word Data0 the register retains its value while vregi supply present</description> 376 <bitOffset>0</bitOffset> 377 <bitWidth>32</bitWidth> 378 </field> 379 </fields> 380 </register> 381 <register> 382 <name>ADCCFG0</name> 383 <description>ADC Config 0</description> 384 <addressOffset>0x50</addressOffset> 385 <fields> 386 <field> 387 <name>LP_5K_DIS</name> 388 <description>Disable 5K divider optionin low power modes</description> 389 <bitOffset>0</bitOffset> 390 <bitWidth>1</bitWidth> 391 </field> 392 <field> 393 <name>LP_50K_DIS</name> 394 <description>Disable 50K divider optionin low power modes</description> 395 <bitOffset>1</bitOffset> 396 <bitWidth>1</bitWidth> 397 </field> 398 <field> 399 <name>EXT_REF</name> 400 <description>External Reference Select Option</description> 401 <bitOffset>2</bitOffset> 402 <bitWidth>1</bitWidth> 403 </field> 404 <field> 405 <name>REF_SEL</name> 406 <description>Internal Reference Select Option</description> 407 <bitOffset>3</bitOffset> 408 <bitWidth>1</bitWidth> 409 </field> 410 </fields> 411 </register> 412 <register> 413 <name>ADCCFG1</name> 414 <description>ADC Config 1</description> 415 <addressOffset>0x54</addressOffset> 416 <fields> 417 <field> 418 <name>CHX_PU_DYN</name> 419 <description>ADC PU dynamic control</description> 420 <bitOffset>0</bitOffset> 421 <bitWidth>13</bitWidth> 422 </field> 423 </fields> 424 </register> 425 <register> 426 <name>ADCCFG2</name> 427 <description>ADC Config 2</description> 428 <addressOffset>0x58</addressOffset> 429 <fields> 430 <field> 431 <name>CH0</name> 432 <description>Divider option for ADC input channel 0</description> 433 <bitOffset>0</bitOffset> 434 <bitWidth>2</bitWidth> 435 <enumeratedValues> 436 <enumeratedValue> 437 <name>div1</name> 438 <description>div1</description> 439 <value>0</value> 440 </enumeratedValue> 441 <enumeratedValue> 442 <name>div2_5k</name> 443 <description>5k ohom</description> 444 <value>1</value> 445 </enumeratedValue> 446 <enumeratedValue> 447 <name>div2_50k</name> 448 <description>50k ohom</description> 449 <value>2</value> 450 </enumeratedValue> 451 </enumeratedValues> 452 </field> 453 <field derivedFrom="CH0"> 454 <name>CH1</name> 455 <description>Divider option for ADC input channel 1</description> 456 <bitOffset>2</bitOffset> 457 <bitWidth>2</bitWidth> 458 </field> 459 <field derivedFrom="CH0"> 460 <name>CH2</name> 461 <description>Divider option for ADC input channel 2</description> 462 <bitOffset>4</bitOffset> 463 <bitWidth>2</bitWidth> 464 </field> 465 <field derivedFrom="CH0"> 466 <name>CH3</name> 467 <description>Divider option for ADC input channel 3</description> 468 <bitOffset>6</bitOffset> 469 <bitWidth>2</bitWidth> 470 </field> 471 <field derivedFrom="CH0"> 472 <name>CH4</name> 473 <description>Divider option for ADC input channel 4</description> 474 <bitOffset>8</bitOffset> 475 <bitWidth>2</bitWidth> 476 </field> 477 <field derivedFrom="CH0"> 478 <name>CH5</name> 479 <description>Divider option for ADC input channel 5</description> 480 <bitOffset>10</bitOffset> 481 <bitWidth>2</bitWidth> 482 </field> 483 <field derivedFrom="CH0"> 484 <name>CH6</name> 485 <description>Divider option for ADC input channel 6</description> 486 <bitOffset>12</bitOffset> 487 <bitWidth>2</bitWidth> 488 </field> 489 <field derivedFrom="CH0"> 490 <name>CH7</name> 491 <description>Divider option for ADC input channel 7</description> 492 <bitOffset>14</bitOffset> 493 <bitWidth>2</bitWidth> 494 </field> 495 </fields> 496 </register> 497 <register> 498 <name>LDOCTRL</name> 499 <description>LDO Control</description> 500 <addressOffset>0x60</addressOffset> 501 <fields> 502 <field> 503 <name>0P9EN</name> 504 <description>LDO 0.9V Enable</description> 505 <bitOffset>0</bitOffset> 506 <bitWidth>1</bitWidth> 507 </field> 508 <field> 509 <name>2P5EN</name> 510 <description>LDO 2.5V Enable</description> 511 <bitOffset>1</bitOffset> 512 <bitWidth>1</bitWidth> 513 </field> 514 </fields> 515 </register> 516 </registers> 517 </peripheral> 518</device>
