1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>MCR</name> 5 <description>Misc Control.</description> 6 <baseAddress>0x40006C00</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>ECCEN</name> 15 <description>ECC Enable Register</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>RAM0</name> 20 <description>ECC System RAM0 Enable.</description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>1</bitWidth> 23 <enumeratedValues> 24 <enumeratedValue> 25 <name>dis</name> 26 <description>disabled.</description> 27 <value>0</value> 28 </enumeratedValue> 29 <enumeratedValue> 30 <name>en</name> 31 <description>enabled.</description> 32 <value>1</value> 33 </enumeratedValue> 34 </enumeratedValues> 35 </field> 36 </fields> 37 </register> 38 <register> 39 <name>IPO_MTRIM</name> 40 <description>IPO Manual Register</description> 41 <addressOffset>0x04</addressOffset> 42 <fields> 43 <field> 44 <name>MTRIM</name> 45 <description>Manual Trim Value.</description> 46 <bitOffset>0</bitOffset> 47 <bitWidth>8</bitWidth> 48 </field> 49 <field> 50 <name>TRIM_RANGE</name> 51 <description>Trim Range Select.</description> 52 <bitOffset>8</bitOffset> 53 <bitWidth>1</bitWidth> 54 </field> 55 </fields> 56 </register> 57 <register> 58 <name>OUTEN</name> 59 <description>Output Enable Register</description> 60 <addressOffset>0x08</addressOffset> 61 <fields> 62 <field> 63 <name>SQWOUT_EN</name> 64 <description>Square Wave Output Enable.</description> 65 <bitOffset>0</bitOffset> 66 <bitWidth>1</bitWidth> 67 </field> 68 <field> 69 <name>PDOWN_OUT_EN</name> 70 <description>Power Down Output Enable.</description> 71 <bitOffset>1</bitOffset> 72 <bitWidth>1</bitWidth> 73 </field> 74 </fields> 75 </register> 76 <register> 77 <name>CMP_CTRL</name> 78 <description>Comparator Control Register.</description> 79 <addressOffset>0x0C</addressOffset> 80 <fields> 81 <field> 82 <name>EN</name> 83 <description>Comparator Enable.</description> 84 <bitOffset>0</bitOffset> 85 <bitWidth>1</bitWidth> 86 </field> 87 <field> 88 <name>POL</name> 89 <description>Polarity Select</description> 90 <bitOffset>5</bitOffset> 91 <bitWidth>1</bitWidth> 92 </field> 93 <field> 94 <name>INT_EN</name> 95 <description>IRQ Enable.</description> 96 <bitOffset>6</bitOffset> 97 <bitWidth>1</bitWidth> 98 </field> 99 <field> 100 <name>OUT</name> 101 <description>Comparator Output State.</description> 102 <bitOffset>14</bitOffset> 103 <bitWidth>1</bitWidth> 104 </field> 105 <field> 106 <name>INT_FL</name> 107 <description>IRQ Flag</description> 108 <bitOffset>15</bitOffset> 109 <bitWidth>1</bitWidth> 110 </field> 111 </fields> 112 </register> 113 <register> 114 <name>CTRL</name> 115 <description>Miscellaneous Control Register.</description> 116 <addressOffset>0x10</addressOffset> 117 <fields> 118 <field> 119 <name>CMPHYST</name> 120 <description>Comparator hysteresis control.</description> 121 <bitOffset>0</bitOffset> 122 <bitWidth>2</bitWidth> 123 </field> 124 <field> 125 <name>INRO_EN</name> 126 <description>INRO Enable.</description> 127 <bitOffset>2</bitOffset> 128 <bitWidth>1</bitWidth> 129 </field> 130 <field> 131 <name>ERTCO_EN</name> 132 <description>ERTCO Enable.</description> 133 <bitOffset>3</bitOffset> 134 <bitWidth>1</bitWidth> 135 </field> 136 <field> 137 <name>IBRO_EN</name> 138 <description>IBRO Enable.</description> 139 <bitOffset>4</bitOffset> 140 <bitWidth>1</bitWidth> 141 </field> 142 <field> 143 <name>32KOSC_EN</name> 144 <description>Enable 32K Oscillator input.</description> 145 <bitOffset>5</bitOffset> 146 <bitWidth>1</bitWidth> 147 </field> 148 <field> 149 <name>SIMO_CLKSCL_EN</name> 150 <description>SIMO Clock Scaling Enable.</description> 151 <bitOffset>8</bitOffset> 152 <bitWidth>1</bitWidth> 153 </field> 154 <field> 155 <name>SIMO_RSTD</name> 156 <description>SIMO System Reset Disable.</description> 157 <bitOffset>9</bitOffset> 158 <bitWidth>1</bitWidth> 159 </field> 160 </fields> 161 </register> 162 <register> 163 <name>GPIO3_CTRL</name> 164 <description>GPIO3 Pin Control Register.</description> 165 <addressOffset>0x20</addressOffset> 166 <fields> 167 <field> 168 <name>P30_DO</name> 169 <description>GPIO3 Pin 0 Data Output.</description> 170 <bitOffset>0</bitOffset> 171 <bitWidth>1</bitWidth> 172 </field> 173 <field> 174 <name>P30_OE</name> 175 <description>GPIO3 Pin 0 Output Enable.</description> 176 <bitOffset>1</bitOffset> 177 <bitWidth>1</bitWidth> 178 </field> 179 <field> 180 <name>P30_PE</name> 181 <description>GPIO3 Pin 0 Pull-up Enable.</description> 182 <bitOffset>2</bitOffset> 183 <bitWidth>1</bitWidth> 184 </field> 185 <field> 186 <name>P30_IN</name> 187 <description>GPIO3 Pin 0 Input Status.</description> 188 <bitOffset>3</bitOffset> 189 <bitWidth>1</bitWidth> 190 </field> 191 <field> 192 <name>P31_DO</name> 193 <description>GPIO3 Pin 1 Data Output.</description> 194 <bitOffset>4</bitOffset> 195 <bitWidth>1</bitWidth> 196 </field> 197 <field> 198 <name>P31_OE</name> 199 <description>GPIO3 Pin 1 Output Enable.</description> 200 <bitOffset>5</bitOffset> 201 <bitWidth>1</bitWidth> 202 </field> 203 <field> 204 <name>P31_PE</name> 205 <description>GPIO3 Pin 1 Pull-up Enable.</description> 206 <bitOffset>6</bitOffset> 207 <bitWidth>1</bitWidth> 208 </field> 209 <field> 210 <name>P31_IN</name> 211 <description>GPIO3 Pin 1 Input Status.</description> 212 <bitOffset>7</bitOffset> 213 <bitWidth>1</bitWidth> 214 </field> 215 </fields> 216 </register> 217 </registers> 218 </peripheral> 219</device>
