1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>MCR</name> 5 <description>Miscellaneous Control Registers.</description> 6 <baseAddress>0x40106000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>RST</name> 15 <description>Reset control register 0.</description> 16 <addressOffset>0x04</addressOffset> 17 <resetMask>0</resetMask> 18 <fields> 19 <field> 20 <name>lptmr0</name> 21 <description>Setting this bit will reset LPTMR0.</description> 22 <bitOffset>0</bitOffset> 23 <bitWidth>1</bitWidth> 24 <enumeratedValues> 25 <enumeratedValue> 26 <name>rst</name> 27 <description>Reset LPTMR0.</description> 28 <value>1</value> 29 </enumeratedValue> 30 </enumeratedValues> 31 </field> 32 <field> 33 <name>lptmr1</name> 34 <description>Setting this bit will reset LPTMR1.</description> 35 <bitOffset>1</bitOffset> 36 <bitWidth>1</bitWidth> 37 <enumeratedValues> 38 <enumeratedValue> 39 <name>rst</name> 40 <description>Reset LPTMR1.</description> 41 <value>1</value> 42 </enumeratedValue> 43 </enumeratedValues> 44 </field> 45 <field> 46 <name>lpuart0</name> 47 <description>Setting this bit will reset LPUART0.</description> 48 <bitOffset>2</bitOffset> 49 <bitWidth>1</bitWidth> 50 <enumeratedValues> 51 <enumeratedValue> 52 <name>rst</name> 53 <description>Reset LPUART0.</description> 54 <value>1</value> 55 </enumeratedValue> 56 </enumeratedValues> 57 </field> 58 <field> 59 <name>rtc</name> 60 <description>Setting this bit will reset the Real-Time Clock.</description> 61 <bitOffset>3</bitOffset> 62 <bitWidth>1</bitWidth> 63 <enumeratedValues> 64 <enumeratedValue> 65 <name>rst</name> 66 <description>Reset Real-Time Clock.</description> 67 <value>1</value> 68 </enumeratedValue> 69 </enumeratedValues> 70 </field> 71 </fields> 72 </register> 73 <register> 74 <name>LPPIOCTRL</name> 75 <description>Low-power peripheral IO control.</description> 76 <addressOffset>0x10</addressOffset> 77 <resetMask>0</resetMask> 78 <fields> 79 <field> 80 <name>LPTMR0_I</name> 81 <description>Setting this bit will enable the low-power timer 0 (timer 4) input pin while operating in low-power modes.</description> 82 <bitOffset>0</bitOffset> 83 <bitWidth>1</bitWidth> 84 <enumeratedValues> 85 <enumeratedValue> 86 <name>dis</name> 87 <description>Disable LPTMR0 input pin.</description> 88 <value>0</value> 89 </enumeratedValue> 90 <enumeratedValue> 91 <name>en</name> 92 <description>Enable LPTMR0 input pin.</description> 93 <value>1</value> 94 </enumeratedValue> 95 </enumeratedValues> 96 </field> 97 <field> 98 <name>LPTMR0_O</name> 99 <description>Setting this bit will enable the low-power timer 0 (timer 4) output pin while operating in low-power modes.</description> 100 <bitOffset>1</bitOffset> 101 <bitWidth>1</bitWidth> 102 <enumeratedValues> 103 <enumeratedValue> 104 <name>dis</name> 105 <description>Disable LPTMR0 output pin.</description> 106 <value>0</value> 107 </enumeratedValue> 108 <enumeratedValue> 109 <name>en</name> 110 <description>Enable LPTMR0 output pin.</description> 111 <value>1</value> 112 </enumeratedValue> 113 </enumeratedValues> 114 </field> 115 <field> 116 <name>LPTMR1_I</name> 117 <description>Setting this bit will enable the low-power timer 1 (timer 5) input pin while operating in low-power modes.</description> 118 <bitOffset>2</bitOffset> 119 <bitWidth>1</bitWidth> 120 <enumeratedValues> 121 <enumeratedValue> 122 <name>dis</name> 123 <description>Disable LPTMR1 input pin.</description> 124 <value>0</value> 125 </enumeratedValue> 126 <enumeratedValue> 127 <name>en</name> 128 <description>Enable LPTMR1 input pin.</description> 129 <value>1</value> 130 </enumeratedValue> 131 </enumeratedValues> 132 </field> 133 <field> 134 <name>LPTMR1_O</name> 135 <description>Setting this bit will enable the low-power timer 1 (timer 5) output pin while operating in low-power modes.</description> 136 <bitOffset>3</bitOffset> 137 <bitWidth>1</bitWidth> 138 <enumeratedValues> 139 <enumeratedValue> 140 <name>dis</name> 141 <description>Disable LPTMR1 output pin.</description> 142 <value>0</value> 143 </enumeratedValue> 144 <enumeratedValue> 145 <name>en</name> 146 <description>Enable LPTMR1 output pin.</description> 147 <value>1</value> 148 </enumeratedValue> 149 </enumeratedValues> 150 </field> 151 <field> 152 <name>LPUART0_RX</name> 153 <description>Setting this bit will enable the low-power UART 0 (UART3) RX pin while operating in low-power modes.</description> 154 <bitOffset>4</bitOffset> 155 <bitWidth>1</bitWidth> 156 <enumeratedValues> 157 <enumeratedValue> 158 <name>dis</name> 159 <description>Disable LPUART0 RX pin.</description> 160 <value>0</value> 161 </enumeratedValue> 162 <enumeratedValue> 163 <name>en</name> 164 <description>Enable LPUART0 RX pin.</description> 165 <value>1</value> 166 </enumeratedValue> 167 </enumeratedValues> 168 </field> 169 <field> 170 <name>LPUART0_TX</name> 171 <description>Setting this bit will enable the low-power UART 0 (UART3) TX pin while operating in low-power modes.</description> 172 <bitOffset>5</bitOffset> 173 <bitWidth>1</bitWidth> 174 <enumeratedValues> 175 <enumeratedValue> 176 <name>dis</name> 177 <description>Disable LPUART0 TX pin.</description> 178 <value>0</value> 179 </enumeratedValue> 180 <enumeratedValue> 181 <name>en</name> 182 <description>Enable LPUART0 TX pin.</description> 183 <value>1</value> 184 </enumeratedValue> 185 </enumeratedValues> 186 </field> 187 <field> 188 <name>LPUART0_CTS</name> 189 <description>Setting this bit will enable the low-power UART 0 (UART3) CTS pin while operating in low-power modes.</description> 190 <bitOffset>6</bitOffset> 191 <bitWidth>1</bitWidth> 192 <enumeratedValues> 193 <enumeratedValue> 194 <name>dis</name> 195 <description>Disable LPUART0 CTS pin.</description> 196 <value>0</value> 197 </enumeratedValue> 198 <enumeratedValue> 199 <name>en</name> 200 <description>Enable LPUART0 CTS pin.</description> 201 <value>1</value> 202 </enumeratedValue> 203 </enumeratedValues> 204 </field> 205 <field> 206 <name>LPUART0_RTS</name> 207 <description>Setting this bit will enable the low-power UART 0 (UART3) RTS pin while operating in low-power modes.</description> 208 <bitOffset>7</bitOffset> 209 <bitWidth>1</bitWidth> 210 <enumeratedValues> 211 <enumeratedValue> 212 <name>dis</name> 213 <description>Disable LPUART0 RTS pin.</description> 214 <value>0</value> 215 </enumeratedValue> 216 <enumeratedValue> 217 <name>en</name> 218 <description>Enable LPUART0 RTS pin.</description> 219 <value>1</value> 220 </enumeratedValue> 221 </enumeratedValues> 222 </field> 223 </fields> 224 </register> 225 <register> 226 <name>CLKDIS</name> 227 <description>Peripheral clock control register.</description> 228 <addressOffset>0x24</addressOffset> 229 <resetMask>0xFFFFFFFF</resetMask> 230 <fields> 231 <field> 232 <name>lptmr0</name> 233 <description>Clearing this bit will enable the low-power timer 0 (timer 4) peripheral clock.</description> 234 <bitOffset>0</bitOffset> 235 <bitWidth>1</bitWidth> 236 <enumeratedValues> 237 <enumeratedValue> 238 <name>en</name> 239 <description>Enable LPTMR0 clock.</description> 240 <value>0</value> 241 </enumeratedValue> 242 <enumeratedValue> 243 <name>dis</name> 244 <description>Disable LPTMR0 clock.</description> 245 <value>1</value> 246 </enumeratedValue> 247 </enumeratedValues> 248 </field> 249 <field> 250 <name>lptmr1</name> 251 <description>Clearing this bit will enable the low-power timer 1 (timer 5) peripheral clock.</description> 252 <bitOffset>1</bitOffset> 253 <bitWidth>1</bitWidth> 254 <enumeratedValues> 255 <enumeratedValue> 256 <name>en</name> 257 <description>Enable LPTMR1 clock.</description> 258 <value>0</value> 259 </enumeratedValue> 260 <enumeratedValue> 261 <name>dis</name> 262 <description>Disable LPTMR1 clock.</description> 263 <value>1</value> 264 </enumeratedValue> 265 </enumeratedValues> 266 </field> 267 <field> 268 <name>lpuart0</name> 269 <description>Clearing this bit will enable the low-power UART 0 (UART3) peripheral clock.</description> 270 <bitOffset>2</bitOffset> 271 <bitWidth>1</bitWidth> 272 <enumeratedValues> 273 <enumeratedValue> 274 <name>en</name> 275 <description>Enable LPUART0 clock.</description> 276 <value>0</value> 277 </enumeratedValue> 278 <enumeratedValue> 279 <name>dis</name> 280 <description>Disable LPUART0 clock.</description> 281 <value>1</value> 282 </enumeratedValue> 283 </enumeratedValues> 284 </field> 285 </fields> 286 </register> 287 </registers> 288 </peripheral> 289</device> 290
