1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>MCR</name> 5 <description>Misc Control.</description> 6 <baseAddress>0x40006C00</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>RST</name> 15 <description>Reset Register.</description> 16 <addressOffset>0x04</addressOffset> 17 <fields> 18 <field> 19 <name>TMR3</name> 20 <description>TMR3 (LPTMR0) Reset. Setting this bit to 1 resets TMR3 (LPTMR0) block.</description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>1</bitWidth> 23 </field> 24 <field> 25 <name>RTC</name> 26 <description>Real Time Clock Reset.</description> 27 <bitOffset>3</bitOffset> 28 <bitWidth>1</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <name>CLKCTRL</name> 34 <description>System CLock Control Register.</description> 35 <addressOffset>0x08</addressOffset> 36 <fields> 37 <field> 38 <name>ERTCO_PD</name> 39 <description>32kHz Crystal Oscillator Power Down. Setting this bit powers down the ERTCO analog circuitry.</description> 40 <bitOffset>16</bitOffset> 41 <bitWidth>1</bitWidth> 42 </field> 43 <field> 44 <name>ERTCO_EN</name> 45 <description>32kHz Crystal Oscillator Enable.</description> 46 <bitOffset>17</bitOffset> 47 <bitWidth>1</bitWidth> 48 </field> 49 </fields> 50 </register> 51 <register> 52 <name>AINCOMP</name> 53 <description>AIN Comparator Control Register.</description> 54 <addressOffset>0x0C</addressOffset> 55 <fields> 56 <field> 57 <name>PD</name> 58 <description>AIN Compatator Power Down control. Before AIN Comparator is powered on, the positive and negative inputs selects for the comparator should be configured.</description> 59 <bitOffset>0</bitOffset> 60 <bitWidth>2</bitWidth> 61 </field> 62 <field> 63 <name>HYST</name> 64 <description>AIN Comparator Hysteresis control.</description> 65 <bitOffset>2</bitOffset> 66 <bitWidth>2</bitWidth> 67 </field> 68 <field> 69 <name>NSEL_COMP0</name> 70 <description>Negative input select for Comparator 0. No more than 1 input channel can be selected at any time. Corresponding GPIO must be configured for AF4.</description> 71 <bitOffset>16</bitOffset> 72 <bitWidth>2</bitWidth> 73 </field> 74 <field> 75 <name>PSEL_COMP0</name> 76 <description>Positive input select for AIN Comparator 0. No more than 1 input channel can be selected at any time. Corresponding GPIO must be configured for AF4.</description> 77 <bitOffset>20</bitOffset> 78 <bitWidth>2</bitWidth> 79 </field> 80 <field> 81 <name>NSEL_COMP1</name> 82 <description>Negative input select for Comparator 1. No more than 1 input channel can be selected at any time. Corresponding GPIO must be configured for AF4.</description> 83 <bitOffset>24</bitOffset> 84 <bitWidth>2</bitWidth> 85 </field> 86 <field> 87 <name>PSEL_COMP1</name> 88 <description>Positive input select for AIN Comparator 1. No more than 1 input channel can be selected at any time. Corresponding GPIO must be configured for AF4.</description> 89 <bitOffset>28</bitOffset> 90 <bitWidth>2</bitWidth> 91 </field> 92 </fields> 93 </register> 94 <register> 95 <name>LPPIOCTRL</name> 96 <description>Low Power Peripheral IO Control Register.</description> 97 <addressOffset>0x10</addressOffset> 98 <fields> 99 <field> 100 <name>TMR3_IN</name> 101 <description>Enable control for TMR3 (LPTMR0) input. If enabled, the associated GPIO 102input is connected to the peripheral; otherwise the input to the 103peripheral is forced low.</description> 104 <bitOffset>0</bitOffset> 105 <bitWidth>1</bitWidth> 106 </field> 107 <field> 108 <name>TMR3_OUT</name> 109 <description>Enable control for LPTMR0 output. If enabled and peripheral clock 110also enabled (PCLKDIS.LPTMR0), the peripheral output controls the 111associated GPIO in output mode; otherwise GPIO control comes 112from GPIO control module.</description> 113 <bitOffset>1</bitOffset> 114 <bitWidth>1</bitWidth> 115 </field> 116 <field> 117 <name>TMR3_OUT_N</name> 118 <description>Enable control for TMR3 (LPTMR0) complementary output. If enabled and 119peripheral clock also enabled (PCLKDIS.TMR3), the peripheral 120output controls the associated GPIO in output mode; otherwise GPIO 121control comes from GPIO control module</description> 122 <bitOffset>2</bitOffset> 123 <bitWidth>1</bitWidth> 124 </field> 125 </fields> 126 </register> 127 <register> 128 <name>PCLKDIS</name> 129 <description>Peripheral Clock Disable Register.</description> 130 <addressOffset>0x24</addressOffset> 131 <fields> 132 <field> 133 <name>TMR3</name> 134 <description>TMR3 (LPTMR0) Clock Disable.</description> 135 <bitOffset>0</bitOffset> 136 <bitWidth>1</bitWidth> 137 </field> 138 </fields> 139 </register> 140 <register> 141 <name>AESKEY</name> 142 <description>AES Key Pointer and Status Register.</description> 143 <addressOffset>0x34</addressOffset> 144 <fields> 145 <field> 146 <name>PTR</name> 147 <description>AES Key Pointer/Status</description> 148 <bitOffset>0</bitOffset> 149 <bitWidth>16</bitWidth> 150 </field> 151 </fields> 152 </register> 153 <register> 154 <name>ADCCFG0</name> 155 <description>ADC Config Register 0.</description> 156 <addressOffset>0x38</addressOffset> 157 <fields> 158 <field> 159 <name>LP_EXTCLK_EN</name> 160 <description>Enable input driver for LP External Clock.</description> 161 <bitOffset>0</bitOffset> 162 <bitWidth>1</bitWidth> 163 </field> 164 <field> 165 <name>EXT_REF</name> 166 <description>External Reference Select.</description> 167 <bitOffset>2</bitOffset> 168 <bitWidth>1</bitWidth> 169 </field> 170 <field> 171 <name>INT_REF</name> 172 <description>Internal Reference Select Option, when not using External Reference.</description> 173 <bitOffset>3</bitOffset> 174 <bitWidth>1</bitWidth> 175 </field> 176 </fields> 177 </register> 178 <register> 179 <name>ADCCFG1</name> 180 <description>ADC Config Register 1.</description> 181 <addressOffset>0x3C</addressOffset> 182 <fields> 183 <field> 184 <name>THRU_PAD_SW_EN</name> 185 <description>Enable the MUX switch, switch placed in padring, used in the buffer path. Each pad has a separate THRU_PAD_SW_EN signal.</description> 186 <bitOffset>0</bitOffset> 187 <bitWidth>4</bitWidth> 188 </field> 189 <field> 190 <name>AIN_INP_EN</name> 191 <description>AIN Input Enable.</description> 192 <bitOffset>4</bitOffset> 193 <bitWidth>4</bitWidth> 194 </field> 195 <field> 196 <name>THRU_EN</name> 197 <description>Enable the MUX switches, switch placed in analog_sys, used in the buffer path.</description> 198 <bitOffset>8</bitOffset> 199 <bitWidth>1</bitWidth> 200 </field> 201 <field> 202 <name>AMP_EN</name> 203 <description>Enable the buffer amplifier used in the buffer path.</description> 204 <bitOffset>9</bitOffset> 205 <bitWidth>1</bitWidth> 206 </field> 207 <field> 208 <name>AMP_RRI_EN</name> 209 <description>Enable the buffer amplifier to operatore for Rail to Rail Input, Active High. If it is low, only NMOS Input pair will be operating which would restrict the range,</description> 210 <bitOffset>10</bitOffset> 211 <bitWidth>1</bitWidth> 212 </field> 213 <field> 214 <name>DIVSEL</name> 215 <description>Select one of the three different signal paths.</description> 216 <bitOffset>11</bitOffset> 217 <bitWidth>2</bitWidth> 218 </field> 219 </fields> 220 </register> 221 <register> 222 <name>ADCCFG2</name> 223 <description>ADC Config Register 2.</description> 224 <addressOffset>0x40</addressOffset> 225 <fields> 226 <field> 227 <name>VREFM</name> 228 <description>Trimming code for VREFM output of reference buffer.</description> 229 <bitOffset>0</bitOffset> 230 <bitWidth>7</bitWidth> 231 </field> 232 <field> 233 <name>VREFP</name> 234 <description>Trimming code for VREFP output of reference buffer.</description> 235 <bitOffset>8</bitOffset> 236 <bitWidth>7</bitWidth> 237 </field> 238 <field> 239 <name>IDRV</name> 240 <description>Trimming code for reference buffer drive strength.</description> 241 <bitOffset>16</bitOffset> 242 <bitWidth>4</bitWidth> 243 </field> 244 <field> 245 <name>VCM</name> 246 <description>Trimming code for VCM output of reference buffer.</description> 247 <bitOffset>20</bitOffset> 248 <bitWidth>2</bitWidth> 249 </field> 250 <field> 251 <name>D_IBOOST</name> 252 <description>Trimming value for extra drive current in reference buffer outputs</description> 253 <bitOffset>24</bitOffset> 254 <bitWidth>1</bitWidth> 255 </field> 256 </fields> 257 </register> 258 </registers> 259 </peripheral> 260</device>
