1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>MCR</name> 5 <description>Misc Control.</description> 6 <baseAddress>0x40006C00</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>ECCEN</name> 15 <description>ECC Enable Register</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>RAM0</name> 20 <description>ECC System RAM0 Enable.</description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>1</bitWidth> 23 <enumeratedValues> 24 <enumeratedValue> 25 <name>dis</name> 26 <description>disabled.</description> 27 <value>0</value> 28 </enumeratedValue> 29 <enumeratedValue> 30 <name>en</name> 31 <description>enabled.</description> 32 <value>1</value> 33 </enumeratedValue> 34 </enumeratedValues> 35 </field> 36 </fields> 37 </register> 38 <register> 39 <name>IPO_MTRIM</name> 40 <description>IPO Manual Register</description> 41 <addressOffset>0x04</addressOffset> 42 <fields> 43 <field> 44 <name>MTRIM</name> 45 <description>Manual Trim Value.</description> 46 <bitOffset>0</bitOffset> 47 <bitWidth>8</bitWidth> 48 </field> 49 <field> 50 <name>TRIM_RANGE</name> 51 <description>Trim Range Select.</description> 52 <bitOffset>8</bitOffset> 53 <bitWidth>1</bitWidth> 54 </field> 55 </fields> 56 </register> 57 <register> 58 <name>OUTEN</name> 59 <description>Output Enable Register</description> 60 <addressOffset>0x08</addressOffset> 61 <fields> 62 <field> 63 <name>SQWOUT_EN</name> 64 <description>Square Wave Output Enable.</description> 65 <bitOffset>0</bitOffset> 66 <bitWidth>1</bitWidth> 67 </field> 68 <field> 69 <name>PDOWN_OUT_EN</name> 70 <description>Power Down Output Enable.</description> 71 <bitOffset>1</bitOffset> 72 <bitWidth>1</bitWidth> 73 </field> 74 </fields> 75 </register> 76 <register> 77 <name>CMP_CTRL</name> 78 <description>Comparator Control Register.</description> 79 <addressOffset>0x0C</addressOffset> 80 <fields> 81 <field> 82 <name>EN</name> 83 <description>Comparator Enable.</description> 84 <bitOffset>0</bitOffset> 85 <bitWidth>1</bitWidth> 86 </field> 87 <field> 88 <name>POL</name> 89 <description>Polarity Select</description> 90 <bitOffset>5</bitOffset> 91 <bitWidth>1</bitWidth> 92 </field> 93 <field> 94 <name>INT_EN</name> 95 <description>IRQ Enable.</description> 96 <bitOffset>6</bitOffset> 97 <bitWidth>1</bitWidth> 98 </field> 99 <field> 100 <name>OUT</name> 101 <description>Comparator Output State.</description> 102 <bitOffset>14</bitOffset> 103 <bitWidth>1</bitWidth> 104 </field> 105 <field> 106 <name>INT_FL</name> 107 <description>IRQ Flag</description> 108 <bitOffset>15</bitOffset> 109 <bitWidth>1</bitWidth> 110 </field> 111 </fields> 112 </register> 113 <register> 114 <name>CTRL</name> 115 <description>Miscellaneous Control Register.</description> 116 <addressOffset>0x10</addressOffset> 117 <fields> 118 <field> 119 <name>CMPHYST</name> 120 <description>Comparator HYST.</description> 121 <bitOffset>0</bitOffset> 122 <bitWidth>2</bitWidth> 123 </field> 124 <field> 125 <name>INRO_EN</name> 126 <description>INRO Enable.</description> 127 <bitOffset>2</bitOffset> 128 <bitWidth>1</bitWidth> 129 </field> 130 <field> 131 <name>ERTCO_EN</name> 132 <description>ERTCO Enable.</description> 133 <bitOffset>3</bitOffset> 134 <bitWidth>1</bitWidth> 135 </field> 136 <field> 137 <name>IBRO_EN</name> 138 <description>IBRO Enable.</description> 139 <bitOffset>4</bitOffset> 140 <bitWidth>1</bitWidth> 141 </field> 142 <field> 143 <name>SIMO_CLKSCL_EN</name> 144 <description>SIMO Clock Scaling Enable.</description> 145 <bitOffset>8</bitOffset> 146 <bitWidth>1</bitWidth> 147 </field> 148 <field> 149 <name>SIMO_RSTD</name> 150 <description>SIMO System Reset Disable.</description> 151 <bitOffset>9</bitOffset> 152 <bitWidth>1</bitWidth> 153 </field> 154 </fields> 155 </register> 156 <register> 157 <name>GPIO3_CTRL</name> 158 <description>GPIO3 Pin Control Register.</description> 159 <addressOffset>0x20</addressOffset> 160 <fields> 161 <field> 162 <name>P30_DO</name> 163 <description>GPIO3 Pin 0 Data Output.</description> 164 <bitOffset>0</bitOffset> 165 <bitWidth>1</bitWidth> 166 </field> 167 <field> 168 <name>P30_OE</name> 169 <description>GPIO3 Pin 0 Output Enable.</description> 170 <bitOffset>1</bitOffset> 171 <bitWidth>1</bitWidth> 172 </field> 173 <field> 174 <name>P30_PE</name> 175 <description>GPIO3 Pin 0 Pull-up Enable.</description> 176 <bitOffset>2</bitOffset> 177 <bitWidth>1</bitWidth> 178 </field> 179 <field> 180 <name>P30_IN</name> 181 <description>GPIO3 Pin 0 Input Status.</description> 182 <bitOffset>3</bitOffset> 183 <bitWidth>1</bitWidth> 184 </field> 185 <field> 186 <name>P31_DO</name> 187 <description>GPIO3 Pin 1 Data Output.</description> 188 <bitOffset>4</bitOffset> 189 <bitWidth>1</bitWidth> 190 </field> 191 <field> 192 <name>P31_OE</name> 193 <description>GPIO3 Pin 1 Output Enable.</description> 194 <bitOffset>5</bitOffset> 195 <bitWidth>1</bitWidth> 196 </field> 197 <field> 198 <name>P31_PE</name> 199 <description>GPIO3 Pin 1 Pull-up Enable.</description> 200 <bitOffset>6</bitOffset> 201 <bitWidth>1</bitWidth> 202 </field> 203 <field> 204 <name>P31_IN</name> 205 <description>GPIO3 Pin 1 Input Status.</description> 206 <bitOffset>7</bitOffset> 207 <bitWidth>1</bitWidth> 208 </field> 209 </fields> 210 </register> 211 <register> 212 <name>CWD0</name> 213 <description>Code Word Data0</description> 214 <addressOffset>0x40</addressOffset> 215 <fields> 216 <field> 217 <name>data</name> 218 <description>Code word Data0 the register retains its value while vregi supply present</description> 219 <bitOffset>0</bitOffset> 220 <bitWidth>32</bitWidth> 221 </field> 222 </fields> 223 </register> 224 <register> 225 <name>CWD1</name> 226 <description>Code Word Data1</description> 227 <addressOffset>0x44</addressOffset> 228 <fields> 229 <field> 230 <name>data</name> 231 <description>Code word Data0 the register retains its value while vregi supply present</description> 232 <bitOffset>0</bitOffset> 233 <bitWidth>32</bitWidth> 234 </field> 235 </fields> 236 </register> 237 <register> 238 <name>ADCCFG0</name> 239 <description>ADC Config 0</description> 240 <addressOffset>0x50</addressOffset> 241 <fields> 242 <field> 243 <name>LP_5K_DIS</name> 244 <description>Disable 5K divider optionin low power modes</description> 245 <bitOffset>0</bitOffset> 246 <bitWidth>1</bitWidth> 247 </field> 248 <field> 249 <name>LP_50K_DIS</name> 250 <description>Disable 50K divider optionin low power modes</description> 251 <bitOffset>1</bitOffset> 252 <bitWidth>1</bitWidth> 253 </field> 254 <field> 255 <name>EXT_REF</name> 256 <description>External Reference Select Option</description> 257 <bitOffset>2</bitOffset> 258 <bitWidth>1</bitWidth> 259 </field> 260 <field> 261 <name>REF_SEL</name> 262 <description>Internal Reference Select Option</description> 263 <bitOffset>3</bitOffset> 264 <bitWidth>1</bitWidth> 265 </field> 266 </fields> 267 </register> 268 <register> 269 <name>ADCCFG1</name> 270 <description>ADC Config 1</description> 271 <addressOffset>0x54</addressOffset> 272 <fields> 273 <field> 274 <name>CHX_PU_DYN</name> 275 <description>ADC PU dynamic control</description> 276 <bitOffset>0</bitOffset> 277 <bitWidth>13</bitWidth> 278 </field> 279 </fields> 280 </register> 281 <register> 282 <name>ADCCFG2</name> 283 <description>ADC Config 2</description> 284 <addressOffset>0x58</addressOffset> 285 <fields> 286 <field> 287 <name>CH0</name> 288 <description>Divider option for ADC input channel 0</description> 289 <bitOffset>0</bitOffset> 290 <bitWidth>2</bitWidth> 291 <enumeratedValues> 292 <enumeratedValue> 293 <name>div1</name> 294 <description>div1</description> 295 <value>0</value> 296 </enumeratedValue> 297 <enumeratedValue> 298 <name>div2_5k</name> 299 <description>5k ohom</description> 300 <value>1</value> 301 </enumeratedValue> 302 <enumeratedValue> 303 <name>div2_50k</name> 304 <description>50k ohom</description> 305 <value>2</value> 306 </enumeratedValue> 307 </enumeratedValues> 308 </field> 309 <field derivedFrom="CH0"> 310 <name>CH1</name> 311 <description>Divider option for ADC input channel 1</description> 312 <bitOffset>2</bitOffset> 313 <bitWidth>2</bitWidth> 314 </field> 315 <field derivedFrom="CH0"> 316 <name>CH2</name> 317 <description>Divider option for ADC input channel 2</description> 318 <bitOffset>4</bitOffset> 319 <bitWidth>2</bitWidth> 320 </field> 321 <field derivedFrom="CH0"> 322 <name>CH3</name> 323 <description>Divider option for ADC input channel 3</description> 324 <bitOffset>6</bitOffset> 325 <bitWidth>2</bitWidth> 326 </field> 327 <field derivedFrom="CH0"> 328 <name>CH4</name> 329 <description>Divider option for ADC input channel 4</description> 330 <bitOffset>8</bitOffset> 331 <bitWidth>2</bitWidth> 332 </field> 333 <field derivedFrom="CH0"> 334 <name>CH5</name> 335 <description>Divider option for ADC input channel 5</description> 336 <bitOffset>10</bitOffset> 337 <bitWidth>2</bitWidth> 338 </field> 339 <field derivedFrom="CH0"> 340 <name>CH6</name> 341 <description>Divider option for ADC input channel 6</description> 342 <bitOffset>12</bitOffset> 343 <bitWidth>2</bitWidth> 344 </field> 345 <field derivedFrom="CH0"> 346 <name>CH7</name> 347 <description>Divider option for ADC input channel 7</description> 348 <bitOffset>14</bitOffset> 349 <bitWidth>2</bitWidth> 350 </field> 351 </fields> 352 </register> 353 <register> 354 <name>LDOCTRL</name> 355 <description>LDO Control</description> 356 <addressOffset>0x60</addressOffset> 357 <fields> 358 <field> 359 <name>0P9EN</name> 360 <description>LDO 0.9V Enable</description> 361 <bitOffset>0</bitOffset> 362 <bitWidth>1</bitWidth> 363 </field> 364 <field> 365 <name>2P5EN</name> 366 <description>LDO 2.5V Enable</description> 367 <bitOffset>1</bitOffset> 368 <bitWidth>1</bitWidth> 369 </field> 370 </fields> 371 </register> 372 </registers> 373 </peripheral> 374</device>
