1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3 <peripheral>
4  <name>LPGCR</name>
5  <description>Low Power Global Control.</description>
6  <baseAddress>0x40080000</baseAddress>
7  <addressBlock>
8   <offset>0x00</offset>
9   <size>0x400</size>
10   <usage>registers</usage>
11  </addressBlock>
12  <registers>
13   <register>
14    <name>RST</name>
15    <description>Low Power Reset Register.</description>
16    <addressOffset>0x08</addressOffset>
17    <fields>
18     <field>
19      <name>GPIO2</name>
20      <description>Low Power GPIO 2 Reset.</description>
21      <bitOffset>0</bitOffset>
22      <bitWidth>1</bitWidth>
23      <enumeratedValues>
24       <name>reset</name>
25       <usage>read-write</usage>
26       <enumeratedValue>
27        <name>reset_done</name>
28        <description>Reset complete.</description>
29        <value>0</value>
30       </enumeratedValue>
31       <enumeratedValue>
32        <name>busy</name>
33        <description>Starts Reset or indicates reset in progress.</description>
34        <value>1</value>
35       </enumeratedValue>
36      </enumeratedValues>
37     </field>
38     <field derivedFrom="GPIO2">
39      <name>WDT1</name>
40      <description>Low Power Watchdog Timer 1 Reset.</description>
41      <bitOffset>1</bitOffset>
42      <bitWidth>1</bitWidth>
43     </field>
44     <field derivedFrom="GPIO2">
45      <name>TMR4</name>
46      <description>Low Power Timer 4 Reset.</description>
47      <bitOffset>2</bitOffset>
48      <bitWidth>1</bitWidth>
49     </field>
50     <field derivedFrom="GPIO2">
51      <name>TMR5</name>
52      <description>Low Power Timer 5 Reset.</description>
53      <bitOffset>3</bitOffset>
54      <bitWidth>1</bitWidth>
55     </field>
56     <field derivedFrom="GPIO2">
57      <name>UART3</name>
58      <description>Low Power UART 3 Reset.</description>
59      <bitOffset>4</bitOffset>
60      <bitWidth>1</bitWidth>
61     </field>
62     <field derivedFrom="GPIO2">
63      <name>LPCOMP</name>
64      <description>Low Power Comparator Reset.</description>
65      <bitOffset>6</bitOffset>
66      <bitWidth>1</bitWidth>
67     </field>
68    </fields>
69   </register>
70   <register>
71    <name>PCLKDIS</name>
72    <description>Low Power Peripheral Clock Disable Register.</description>
73    <addressOffset>0x0C</addressOffset>
74    <fields>
75     <field>
76      <name>GPIO2</name>
77      <description>Low Power GPIO 2 Clock Disable.</description>
78      <bitOffset>0</bitOffset>
79      <bitWidth>1</bitWidth>
80      <enumeratedValues>
81       <enumeratedValue>
82        <name>en</name>
83        <description>enable it.</description>
84        <value>0</value>
85       </enumeratedValue>
86       <enumeratedValue>
87        <name>dis</name>
88        <description>disable it.</description>
89        <value>1</value>
90       </enumeratedValue>
91      </enumeratedValues>
92     </field>
93     <field derivedFrom="GPIO2">
94      <name>WDT1</name>
95      <description>Low Power Watchdog 1 Clock Disable.</description>
96      <bitOffset>1</bitOffset>
97      <bitWidth>1</bitWidth>
98     </field>
99     <field derivedFrom="GPIO2">
100      <name>TMR4</name>
101      <description>Low Power Timer 4 Clock Disable.</description>
102      <bitOffset>2</bitOffset>
103      <bitWidth>1</bitWidth>
104     </field>
105     <field derivedFrom="GPIO2">
106      <name>TMR5</name>
107      <description>Low Power Timer 5 Clock Disable.</description>
108      <bitOffset>3</bitOffset>
109      <bitWidth>1</bitWidth>
110     </field>
111     <field derivedFrom="GPIO2">
112      <name>UART3</name>
113      <description>Low Power UART 3 Clock Disable.</description>
114      <bitOffset>4</bitOffset>
115      <bitWidth>1</bitWidth>
116     </field>
117     <field derivedFrom="GPIO2">
118      <name>LPCOMP</name>
119      <description>Low Power Comparator Clock Disable.</description>
120      <bitOffset>6</bitOffset>
121      <bitWidth>1</bitWidth>
122     </field>
123    </fields>
124   </register>
125  </registers>
126 </peripheral>
127</device>
128