1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>GCR</name> 5 <description>Global Control Registers.</description> 6 <baseAddress>0x40000000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>SYSCTRL</name> 15 <description>System Control.</description> 16 <addressOffset>0x00</addressOffset> 17 <resetMask>0xFFFFFFFE</resetMask> 18 <fields> 19 <field> 20 <name>BSTAPEN</name> 21 <description>Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE.</description> 22 <bitOffset>0</bitOffset> 23 <bitWidth>1</bitWidth> 24 <enumeratedValues> 25 <enumeratedValue> 26 <name>dis</name> 27 <description>Boundary Scan TAP port disabled.</description> 28 <value>0</value> 29 </enumeratedValue> 30 <enumeratedValue> 31 <name>en</name> 32 <description>Boundary Scan TAP port enabled.</description> 33 <value>1</value> 34 </enumeratedValue> 35 </enumeratedValues> 36 </field> 37 <field> 38 <name>SBUSARB</name> 39 <description>System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.</description> 40 <bitOffset>1</bitOffset> 41 <bitWidth>2</bitWidth> 42 <enumeratedValues> 43 <enumeratedValue> 44 <name>fix</name> 45 <description>Fixed Burst abritration.</description> 46 <value>0</value> 47 </enumeratedValue> 48 <enumeratedValue> 49 <name>round</name> 50 <description>Round-robin scheme.</description> 51 <value>1</value> 52 </enumeratedValue> 53 </enumeratedValues> 54 </field> 55 <field> 56 <name>FPU_DIS</name> 57 <description>Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4.</description> 58 <bitOffset>5</bitOffset> 59 <bitWidth>1</bitWidth> 60 </field> 61 <field> 62 <name>SFCC_FLUSH</name> 63 <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description> 64 <bitOffset>6</bitOffset> 65 <bitWidth>1</bitWidth> 66 <enumeratedValues> 67 <enumeratedValue> 68 <name>normal</name> 69 <description>Normal Code Cache Operation</description> 70 <value>0</value> 71 </enumeratedValue> 72 <enumeratedValue> 73 <name>flush</name> 74 <description>Code Caches and CPU instruction buffer are flushed </description> 75 <value>1</value> 76 </enumeratedValue> 77 </enumeratedValues> 78 </field> 79 <field> 80 <name>CHKRES1</name> 81 <description>Result of CPU1 ROM1 Checksum.</description> 82 <bitOffset>11</bitOffset> 83 <bitWidth>1</bitWidth> 84 </field> 85 <field> 86 <name>CCHK1</name> 87 <description>Compute CPU1 ROM1 Checksum</description> 88 <bitOffset>12</bitOffset> 89 <bitWidth>1</bitWidth> 90 </field> 91 <field> 92 <name>CCHK0</name> 93 <description>Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description> 94 <bitOffset>13</bitOffset> 95 <bitWidth>1</bitWidth> 96 <enumeratedValues> 97 <enumeratedValue> 98 <name>complete</name> 99 <description>No operation/complete.</description> 100 <value>0</value> 101 </enumeratedValue> 102 <enumeratedValue> 103 <name>start</name> 104 <description>Start operation.</description> 105 <value>1</value> 106 </enumeratedValue> 107 </enumeratedValues> 108 </field> 109 <field> 110 <name>SWD_DIS</name> 111 <description> Serial Wire Debug Disable.</description> 112 <bitOffset>14</bitOffset> 113 <bitWidth>1</bitWidth> 114 </field> 115 <field> 116 <name>CHKRES0</name> 117 <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description> 118 <bitOffset>15</bitOffset> 119 <bitWidth>1</bitWidth> 120 <enumeratedValues> 121 <enumeratedValue> 122 <name>pass</name> 123 <description>ROM Checksum Correct.</description> 124 <value>0</value> 125 </enumeratedValue> 126 <enumeratedValue> 127 <name>fail</name> 128 <description>ROM Checksum Fail.</description> 129 <value>1</value> 130 </enumeratedValue> 131 </enumeratedValues> 132 </field> 133 </fields> 134 </register> 135 <register> 136 <name>RST0</name> 137 <description>Reset.</description> 138 <addressOffset>0x04</addressOffset> 139 <fields> 140 <field> 141 <name>DMA</name> 142 <description>DMA Reset.</description> 143 <bitOffset>0</bitOffset> 144 <bitWidth>1</bitWidth> 145 <enumeratedValues> 146 <name>reset</name> 147 <usage>read-write</usage> 148 <enumeratedValue> 149 <name>reset_done</name> 150 <description>Reset complete.</description> 151 <value>0</value> 152 </enumeratedValue> 153 <enumeratedValue> 154 <name>busy</name> 155 <description>Starts Reset or indicates reset in progress.</description> 156 <value>1</value> 157 </enumeratedValue> 158 </enumeratedValues> 159 </field> 160 <field derivedFrom="DMA"> 161 <name>WDT0</name> 162 <description>Watchdog Timer 0 Reset.</description> 163 <bitOffset>1</bitOffset> 164 <bitWidth>1</bitWidth> 165 </field> 166 <field derivedFrom="DMA"> 167 <name>GPIO0</name> 168 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 169 <bitOffset>2</bitOffset> 170 <bitWidth>1</bitWidth> 171 </field> 172 <field derivedFrom="DMA"> 173 <name>GPIO1</name> 174 <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description> 175 <bitOffset>3</bitOffset> 176 <bitWidth>1</bitWidth> 177 </field> 178 <field derivedFrom="DMA"> 179 <name>TMR0</name> 180 <description>Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 181 <bitOffset>5</bitOffset> 182 <bitWidth>1</bitWidth> 183 </field> 184 <field derivedFrom="DMA"> 185 <name>TMR1</name> 186 <description>Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 187 <bitOffset>6</bitOffset> 188 <bitWidth>1</bitWidth> 189 </field> 190 <field derivedFrom="DMA"> 191 <name>TMR2</name> 192 <description>Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 193 <bitOffset>7</bitOffset> 194 <bitWidth>1</bitWidth> 195 </field> 196 <field derivedFrom="DMA"> 197 <name>TMR3</name> 198 <description>Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description> 199 <bitOffset>8</bitOffset> 200 <bitWidth>1</bitWidth> 201 </field> 202 <field derivedFrom="DMA"> 203 <name>TMR4</name> 204 <description>Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks.</description> 205 <bitOffset>9</bitOffset> 206 <bitWidth>1</bitWidth> 207 </field> 208 <field derivedFrom="DMA"> 209 <name>TMR5</name> 210 <description>Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks.</description> 211 <bitOffset>10</bitOffset> 212 <bitWidth>1</bitWidth> 213 </field> 214 <field derivedFrom="DMA"> 215 <name>UART0</name> 216 <description>UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 217 <bitOffset>11</bitOffset> 218 <bitWidth>1</bitWidth> 219 </field> 220 <field derivedFrom="DMA"> 221 <name>UART1</name> 222 <description>UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description> 223 <bitOffset>12</bitOffset> 224 <bitWidth>1</bitWidth> 225 </field> 226 <field derivedFrom="DMA"> 227 <name>SPI0</name> 228 <description>SPI 0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description> 229 <bitOffset>13</bitOffset> 230 <bitWidth>1</bitWidth> 231 </field> 232 <field derivedFrom="DMA"> 233 <name>SPI1</name> 234 <description>SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 235 <bitOffset>14</bitOffset> 236 <bitWidth>1</bitWidth> 237 </field> 238 <field derivedFrom="DMA"> 239 <name>I2C0</name> 240 <description>I2C 0 Reset.</description> 241 <bitOffset>16</bitOffset> 242 <bitWidth>1</bitWidth> 243 </field> 244 <field derivedFrom="DMA"> 245 <name>CRYPTO</name> 246 <description>Crypto Reset.</description> 247 <bitOffset>18</bitOffset> 248 <bitWidth>1</bitWidth> 249 </field> 250 <field derivedFrom="DMA"> 251 <name>USB</name> 252 <description>USB Reset.</description> 253 <bitOffset>23</bitOffset> 254 <bitWidth>1</bitWidth> 255 </field> 256 <field derivedFrom="DMA"> 257 <name>TRNG</name> 258 <description>TRNG Reset.</description> 259 <bitOffset>24</bitOffset> 260 <bitWidth>1</bitWidth> 261 </field> 262 <field derivedFrom="DMA"> 263 <name>ADC</name> 264 <description>ADC Reset.</description> 265 <bitOffset>26</bitOffset> 266 <bitWidth>1</bitWidth> 267 </field> 268 <field derivedFrom="DMA"> 269 <name>UART2</name> 270 <description>UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.</description> 271 <bitOffset>28</bitOffset> 272 <bitWidth>1</bitWidth> 273 </field> 274 <field derivedFrom="DMA"> 275 <name>SOFT</name> 276 <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description> 277 <bitOffset>29</bitOffset> 278 <bitWidth>1</bitWidth> 279 </field> 280 <field derivedFrom="DMA"> 281 <name>PERIPH</name> 282 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 283 <bitOffset>30</bitOffset> 284 <bitWidth>1</bitWidth> 285 </field> 286 <field derivedFrom="DMA"> 287 <name>SYS</name> 288 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 289 <bitOffset>31</bitOffset> 290 <bitWidth>1</bitWidth> 291 </field> 292 </fields> 293 </register> 294 <register> 295 <name>CLKCTRL</name> 296 <description>Clock Control.</description> 297 <addressOffset>0x08</addressOffset> 298 <resetValue>0x00000008</resetValue> 299 <fields> 300 <field> 301 <name>PCLK_DIV</name> 302 <description>PCLK Divider.</description> 303 <bitOffset>3</bitOffset> 304 <bitWidth>3</bitWidth> 305 <enumeratedValues> 306 <enumeratedValue> 307 <name>div1</name> 308 <description>Divide by 1.</description> 309 <value>0</value> 310 </enumeratedValue> 311 <enumeratedValue> 312 <name>div2</name> 313 <description>Divide by 2.</description> 314 <value>1</value> 315 </enumeratedValue> 316 <enumeratedValue> 317 <name>div4</name> 318 <description>Divide by 4.</description> 319 <value>2</value> 320 </enumeratedValue> 321 <enumeratedValue> 322 <name>div8</name> 323 <description>Divide by 8.</description> 324 <value>3</value> 325 </enumeratedValue> 326 </enumeratedValues> 327 </field> 328 <field> 329 <name>SYSCLK_DIV</name> 330 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 331 <bitOffset>6</bitOffset> 332 <bitWidth>3</bitWidth> 333 <enumeratedValues> 334 <enumeratedValue> 335 <name>div1</name> 336 <description>Divide by 1.</description> 337 <value>0</value> 338 </enumeratedValue> 339 <enumeratedValue> 340 <name>div2</name> 341 <description>Divide by 2.</description> 342 <value>1</value> 343 </enumeratedValue> 344 <enumeratedValue> 345 <name>div4</name> 346 <description>Divide by 4.</description> 347 <value>2</value> 348 </enumeratedValue> 349 <enumeratedValue> 350 <name>div8</name> 351 <description>Divide by 8.</description> 352 <value>3</value> 353 </enumeratedValue> 354 <enumeratedValue> 355 <name>div16</name> 356 <description>Divide by 16.</description> 357 <value>4</value> 358 </enumeratedValue> 359 <enumeratedValue> 360 <name>div32</name> 361 <description>Divide by 32.</description> 362 <value>5</value> 363 </enumeratedValue> 364 <enumeratedValue> 365 <name>div64</name> 366 <description>Divide by 64.</description> 367 <value>6</value> 368 </enumeratedValue> 369 <enumeratedValue> 370 <name>div128</name> 371 <description>Divide by 128.</description> 372 <value>7</value> 373 </enumeratedValue> 374 </enumeratedValues> 375 </field> 376 <field> 377 <name>SYSCLK_SEL</name> 378 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 379 <bitOffset>9</bitOffset> 380 <bitWidth>3</bitWidth> 381 <enumeratedValues> 382 <enumeratedValue> 383 <name>ISO</name> 384 <description>The internal 60 MHz oscillator is used for the system clock.</description> 385 <value>0</value> 386 </enumeratedValue> 387 <enumeratedValue> 388 <name>ERFO</name> 389 <description>The external 32 MHz input is used for the system clock.</description> 390 <value>2</value> 391 </enumeratedValue> 392 <enumeratedValue> 393 <name>INRO</name> 394 <description>8 kHz LIRC is used for the system clock.</description> 395 <value>3</value> 396 </enumeratedValue> 397 <enumeratedValue> 398 <name>IPO</name> 399 <description>The internal 100 MHz oscillator is used for the system clock.</description> 400 <value>4</value> 401 </enumeratedValue> 402 <enumeratedValue> 403 <name>IBRO</name> 404 <description>The internal 7.3725 MHz oscillator is used for the system clock.</description> 405 <value>5</value> 406 </enumeratedValue> 407 <enumeratedValue> 408 <name>ERTCO</name> 409 <description>External 32 kHz input is used for the system clock.</description> 410 <value>6</value> 411 </enumeratedValue> 412 </enumeratedValues> 413 </field> 414 <field> 415 <name>CRYPTOCLK_DIV</name> 416 <description>Cryptographic clock divider</description> 417 <bitOffset>12</bitOffset> 418 <bitWidth>1</bitWidth> 419 <enumeratedValues> 420 <enumeratedValue> 421 <name>non_div</name> 422 <description>The cryptographic accelerator clock is running in non-divided mode.</description> 423 <value>0</value> 424 </enumeratedValue> 425 <enumeratedValue> 426 <name>div</name> 427 <description>The cryptographic accelerator clock is running in divided mode.</description> 428 <value>1</value> 429 </enumeratedValue> 430 </enumeratedValues> 431 </field> 432 <field> 433 <name>SYSCLK_RDY</name> 434 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 435 <bitOffset>13</bitOffset> 436 <bitWidth>1</bitWidth> 437 <access>read-only</access> 438 <enumeratedValues> 439 <enumeratedValue> 440 <name>busy</name> 441 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 442 <value>0</value> 443 </enumeratedValue> 444 <enumeratedValue> 445 <name>ready</name> 446 <description>System clock running from CLKSEL clock source.</description> 447 <value>1</value> 448 </enumeratedValue> 449 </enumeratedValues> 450 </field> 451 <field> 452 <name>IPO_DIV</name> 453 <description>IPO Divider.</description> 454 <bitOffset>14</bitOffset> 455 <bitWidth>2</bitWidth> 456 <enumeratedValues> 457 <enumeratedValue> 458 <name>DIV1</name> 459 <description>Divide by 1.</description> 460 <value>0</value> 461 </enumeratedValue> 462 <enumeratedValue> 463 <name>DIV2</name> 464 <description>Divide by 2.</description> 465 <value>1</value> 466 </enumeratedValue> 467 <enumeratedValue> 468 <name>DIV4</name> 469 <description>Divide by 4.</description> 470 <value>2</value> 471 </enumeratedValue> 472 <enumeratedValue> 473 <name>DIV8</name> 474 <description>Divide by 8.</description> 475 <value>3</value> 476 </enumeratedValue> 477 </enumeratedValues> 478 </field> 479 <field> 480 <name>ERFO_EN</name> 481 <description>27 MHz Crystal Oscillator Enable.</description> 482 <bitOffset>16</bitOffset> 483 <bitWidth>1</bitWidth> 484 <enumeratedValues> 485 <enumeratedValue> 486 <name>dis</name> 487 <description>Is Disabled.</description> 488 <value>0</value> 489 </enumeratedValue> 490 <enumeratedValue> 491 <name>en</name> 492 <description>Is Enabled.</description> 493 <value>1</value> 494 </enumeratedValue> 495 </enumeratedValues> 496 </field> 497 <field derivedFrom="ERFO_EN"> 498 <name>ISO_EN</name> 499 <description>60 MHz Internal Oscillator Enable.</description> 500 <bitOffset>18</bitOffset> 501 <bitWidth>1</bitWidth> 502 </field> 503 <field derivedFrom="ERFO_EN"> 504 <name>IPO_EN</name> 505 <description>100 MHz Clock Enable.</description> 506 <bitOffset>19</bitOffset> 507 <bitWidth>1</bitWidth> 508 </field> 509 <field derivedFrom="ERFO_EN"> 510 <name>IBRO_EN</name> 511 <description>7.3725 MHz Clock Enable.</description> 512 <bitOffset>20</bitOffset> 513 <bitWidth>1</bitWidth> 514 </field> 515 <field> 516 <name>IBRO_VS</name> 517 <description>7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO.</description> 518 <bitOffset>21</bitOffset> 519 <bitWidth>1</bitWidth> 520 <enumeratedValues> 521 <enumeratedValue> 522 <name>Vcor</name> 523 <description>VCore Supply</description> 524 <value>0</value> 525 </enumeratedValue> 526 <enumeratedValue> 527 <name>1V</name> 528 <description>Dedicated 1V regulated supply.</description> 529 <value>1</value> 530 </enumeratedValue> 531 </enumeratedValues> 532 </field> 533 <field> 534 <name>ERFO_RDY</name> 535 <description>32 MHz Oscillator Ready</description> 536 <bitOffset>24</bitOffset> 537 <bitWidth>1</bitWidth> 538 <access>read-only</access> 539 <enumeratedValues> 540 <enumeratedValue> 541 <name>not</name> 542 <description>Is not Ready.</description> 543 <value>0</value> 544 </enumeratedValue> 545 <enumeratedValue> 546 <name>ready</name> 547 <description>Is Ready.</description> 548 <value>1</value> 549 </enumeratedValue> 550 </enumeratedValues> 551 </field> 552 <field derivedFrom="ERFO_RDY"> 553 <name>ERTCO_RDY</name> 554 <description>32 kHz Crystal Oscillator Ready</description> 555 <bitOffset>25</bitOffset> 556 <bitWidth>1</bitWidth> 557 </field> 558 <field derivedFrom="ERFO_RDY"> 559 <name>ISO_RDY</name> 560 <description>60 MHz Oscillator Ready.</description> 561 <bitOffset>26</bitOffset> 562 <bitWidth>1</bitWidth> 563 </field> 564 <field derivedFrom="ERFO_RDY"> 565 <name>IPO_RDY</name> 566 <description>100 MHz Clock Ready.</description> 567 <bitOffset>27</bitOffset> 568 <bitWidth>1</bitWidth> 569 </field> 570 <field derivedFrom="ERFO_RDY"> 571 <name>IBRO_RDY</name> 572 <description>7.3725 MHz HIRC Ready.</description> 573 <bitOffset>28</bitOffset> 574 <bitWidth>1</bitWidth> 575 </field> 576 <field derivedFrom="ERFO_RDY"> 577 <name>INRO_RDY</name> 578 <description>8 kHz Low Frequency Reference Clock Ready.</description> 579 <bitOffset>29</bitOffset> 580 <bitWidth>1</bitWidth> 581 </field> 582 </fields> 583 </register> 584 <register> 585 <name>PM</name> 586 <description>Power Management.</description> 587 <addressOffset>0x0C</addressOffset> 588 <fields> 589 <field> 590 <name>MODE</name> 591 <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 592 <bitOffset>0</bitOffset> 593 <bitWidth>3</bitWidth> 594 <enumeratedValues> 595 <enumeratedValue> 596 <name>active</name> 597 <description>Active Mode.</description> 598 <value>0</value> 599 </enumeratedValue> 600 <enumeratedValue> 601 <name>sleep</name> 602 <description>Sleep Mode.</description> 603 <value>1</value> 604 </enumeratedValue> 605 <enumeratedValue> 606 <name>deepsleep</name> 607 <description>DeepSleep Mode.</description> 608 <value>2</value> 609 </enumeratedValue> 610 <enumeratedValue> 611 <name>shutdown</name> 612 <description>ShutDown Mode.</description> 613 <value>3</value> 614 </enumeratedValue> 615 <enumeratedValue> 616 <name>backup</name> 617 <description>Backup Mode.</description> 618 <value>4</value> 619 </enumeratedValue> 620 </enumeratedValues> 621 </field> 622 <field> 623 <name>GPIO_WE</name> 624 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 625 <bitOffset>4</bitOffset> 626 <bitWidth>1</bitWidth> 627 <enumeratedValues> 628 <enumeratedValue> 629 <name>dis</name> 630 <description>Wake Up Disable.</description> 631 <value>0</value> 632 </enumeratedValue> 633 <enumeratedValue> 634 <name>en</name> 635 <description>Wake Up Enable.</description> 636 <value>1</value> 637 </enumeratedValue> 638 </enumeratedValues> 639 </field> 640 <field derivedFrom="GPIO_WE"> 641 <name>RTC_WE</name> 642 <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description> 643 <bitOffset>5</bitOffset> 644 <bitWidth>1</bitWidth> 645 </field> 646 <field derivedFrom="GPIO_WE"> 647 <name>USB_WE</name> 648 <description>USB Wake Up Enable. This bit enables USB IRQ as wakeup source</description> 649 <bitOffset>6</bitOffset> 650 <bitWidth>1</bitWidth> 651 </field> 652 <field> 653 <name>ERFO_PD</name> 654 <description>27 MHz power down. This bit selects the 27 MHz clock power state in DEEPSLEEP mode.</description> 655 <bitOffset>12</bitOffset> 656 <bitWidth>1</bitWidth> 657 <enumeratedValues> 658 <enumeratedValue> 659 <name>active</name> 660 <description>Mode is Active.</description> 661 <value>0</value> 662 </enumeratedValue> 663 <enumeratedValue> 664 <name>deepsleep</name> 665 <description>Powered down in DEEPSLEEP.</description> 666 <value>1</value> 667 </enumeratedValue> 668 </enumeratedValues> 669 </field> 670 <field derivedFrom="ERFO_PD"> 671 <name>ISO_PD</name> 672 <description>60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode.</description> 673 <bitOffset>15</bitOffset> 674 <bitWidth>1</bitWidth> 675 </field> 676 <field derivedFrom="ERFO_PD"> 677 <name>IPO_PD</name> 678 <description>100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode. </description> 679 <bitOffset>16</bitOffset> 680 <bitWidth>1</bitWidth> 681 </field> 682 <field derivedFrom="ERFO_PD"> 683 <name>IBRO_PD</name> 684 <description>7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode. </description> 685 <bitOffset>17</bitOffset> 686 <bitWidth>1</bitWidth> 687 </field> 688 <field> 689 <name>ERFO_BP</name> 690 <description>27MHz Oscillator Bypass.</description> 691 <bitOffset>20</bitOffset> 692 <bitWidth>1</bitWidth> 693 </field> 694 </fields> 695 </register> 696 <register> 697 <name>PCLKDIV</name> 698 <description>Peripheral Clock Divider.</description> 699 <addressOffset>0x18</addressOffset> 700 <resetValue>0x00000001</resetValue> 701 <fields> 702 <field> 703 <name>SKBDFRQ</name> 704 <description>GCR Frequency Indicator for Secure Keyboard.</description> 705 <bitOffset>0</bitOffset> 706 <bitWidth>3</bitWidth> 707 </field> 708 <field> 709 <name>ADCFRQ</name> 710 <description>ADC clock Frequency. These bits define the ADC clock frequency. fADC = fPCLK / (ADCFRQ)</description> 711 <bitOffset>10</bitOffset> 712 <bitWidth>4</bitWidth> 713 </field> 714 <field> 715 <name>AONCLKDIV</name> 716 <description>AON Clock Divider. These bits define the AON Domain Clock Divider.</description> 717 <bitOffset>14</bitOffset> 718 <bitWidth>2</bitWidth> 719 <enumeratedValues> 720 <enumeratedValue> 721 <name>div4</name> 722 <value>0</value> 723 </enumeratedValue> 724 <enumeratedValue> 725 <name>div8</name> 726 <value>1</value> 727 </enumeratedValue> 728 <enumeratedValue> 729 <name>div16</name> 730 <value>2</value> 731 </enumeratedValue> 732 <enumeratedValue> 733 <name>div32</name> 734 <value>3</value> 735 </enumeratedValue> 736 </enumeratedValues> 737 </field> 738 </fields> 739 </register> 740 <register> 741 <name>PCLKDIS0</name> 742 <description>Peripheral Clock Disable.</description> 743 <addressOffset>0x24</addressOffset> 744 <fields> 745 <field> 746 <name>GPIO0</name> 747 <description>GPIO0 Clock Disable.</description> 748 <bitOffset>0</bitOffset> 749 <bitWidth>1</bitWidth> 750 <enumeratedValues> 751 <enumeratedValue> 752 <name>en</name> 753 <description>enable it.</description> 754 <value>0</value> 755 </enumeratedValue> 756 <enumeratedValue> 757 <name>dis</name> 758 <description>disable it.</description> 759 <value>1</value> 760 </enumeratedValue> 761 </enumeratedValues> 762 </field> 763 <field derivedFrom="GPIO0"> 764 <name>GPIO1</name> 765 <description>GPIO1 Clock Disable.</description> 766 <bitOffset>1</bitOffset> 767 <bitWidth>1</bitWidth> 768 </field> 769 <field derivedFrom="GPIO0"> 770 <name>USB</name> 771 <description>USB Clock Disable.</description> 772 <bitOffset>3</bitOffset> 773 <bitWidth>1</bitWidth> 774 </field> 775 <field derivedFrom="GPIO0"> 776 <name>DMA</name> 777 <description>DMA Clock Disable.</description> 778 <bitOffset>5</bitOffset> 779 <bitWidth>1</bitWidth> 780 </field> 781 <field derivedFrom="GPIO0"> 782 <name>SPI0</name> 783 <description>SPI 0 Clock Disable.</description> 784 <bitOffset>6</bitOffset> 785 <bitWidth>1</bitWidth> 786 </field> 787 <field derivedFrom="GPIO0"> 788 <name>SPI1</name> 789 <description>SPI 1 Clock Disable.</description> 790 <bitOffset>7</bitOffset> 791 <bitWidth>1</bitWidth> 792 </field> 793 <field derivedFrom="GPIO0"> 794 <name>UART0</name> 795 <description>UART 0 Clock Disable.</description> 796 <bitOffset>9</bitOffset> 797 <bitWidth>1</bitWidth> 798 </field> 799 <field derivedFrom="GPIO0"> 800 <name>UART1</name> 801 <description>UART 1 Clock Disable.</description> 802 <bitOffset>10</bitOffset> 803 <bitWidth>1</bitWidth> 804 </field> 805 <field derivedFrom="GPIO0"> 806 <name>I2C0</name> 807 <description>I2C 0 Clock Disable.</description> 808 <bitOffset>13</bitOffset> 809 <bitWidth>1</bitWidth> 810 </field> 811 <field derivedFrom="GPIO0"> 812 <name>CRYPTO</name> 813 <description>Crypto Clock Disable.</description> 814 <bitOffset>14</bitOffset> 815 <bitWidth>1</bitWidth> 816 </field> 817 <field derivedFrom="GPIO0"> 818 <name>TMR0</name> 819 <description>Timer 0 Clock Disable.</description> 820 <bitOffset>15</bitOffset> 821 <bitWidth>1</bitWidth> 822 </field> 823 <field derivedFrom="GPIO0"> 824 <name>TMR1</name> 825 <description>Timer 1 Clock Disable.</description> 826 <bitOffset>16</bitOffset> 827 <bitWidth>1</bitWidth> 828 </field> 829 <field derivedFrom="GPIO0"> 830 <name>TMR2</name> 831 <description>Timer 2 Clock Disable.</description> 832 <bitOffset>17</bitOffset> 833 <bitWidth>1</bitWidth> 834 </field> 835 <field derivedFrom="GPIO0"> 836 <name>TMR3</name> 837 <description>Timer 3 Clock Disable.</description> 838 <bitOffset>18</bitOffset> 839 <bitWidth>1</bitWidth> 840 </field> 841 <field derivedFrom="GPIO0"> 842 <name>TMR4</name> 843 <description>Timer 4 Clock Disable.</description> 844 <bitOffset>19</bitOffset> 845 <bitWidth>1</bitWidth> 846 </field> 847 <field derivedFrom="GPIO0"> 848 <name>TMR5</name> 849 <description>Timer 5 Clock Disable.</description> 850 <bitOffset>20</bitOffset> 851 <bitWidth>1</bitWidth> 852 </field> 853 <field derivedFrom="GPIO0"> 854 <name>SKBD</name> 855 <description>Secure Keypad Clock Disable.</description> 856 <bitOffset>22</bitOffset> 857 <bitWidth>1</bitWidth> 858 </field> 859 <field derivedFrom="GPIO0"> 860 <name>ADC</name> 861 <description>ADC Clock Disable.</description> 862 <bitOffset>23</bitOffset> 863 <bitWidth>1</bitWidth> 864 </field> 865 <field derivedFrom="GPIO0"> 866 <name>HTMR0</name> 867 <description>High Speed Timer 0 Clock Disable.</description> 868 <bitOffset>26</bitOffset> 869 <bitWidth>1</bitWidth> 870 </field> 871 <field derivedFrom="GPIO0"> 872 <name>HTMR1</name> 873 <description>High Speed Timer 1 Clock Disable.</description> 874 <bitOffset>27</bitOffset> 875 <bitWidth>1</bitWidth> 876 </field> 877 <field derivedFrom="GPIO0"> 878 <name>I2C1</name> 879 <description>I2C 1 Clock Disable.</description> 880 <bitOffset>28</bitOffset> 881 <bitWidth>1</bitWidth> 882 </field> 883 <field derivedFrom="GPIO0"> 884 <name>PT</name> 885 <description>Pluse Train Clock Disable.</description> 886 <bitOffset>29</bitOffset> 887 <bitWidth>1</bitWidth> 888 </field> 889 <field derivedFrom="GPIO0"> 890 <name>SPIXIP</name> 891 <description>SPI XIP Clock Disable.</description> 892 <bitOffset>30</bitOffset> 893 <bitWidth>1</bitWidth> 894 </field> 895 <field derivedFrom="GPIO0"> 896 <name>SPIXIPC</name> 897 <description>SPI XIPC Clock Disable.</description> 898 <bitOffset>31</bitOffset> 899 <bitWidth>1</bitWidth> 900 </field> 901 </fields> 902 </register> 903 <register> 904 <name>MEMCTRL</name> 905 <description>Memory Clock Control Register.</description> 906 <addressOffset>0x28</addressOffset> 907 <fields> 908 <field> 909 <name>FWS</name> 910 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description> 911 <bitOffset>0</bitOffset> 912 <bitWidth>3</bitWidth> 913 </field> 914 <field> 915 <name>RAM4_WS</name> 916 <description>System RAM4 WS Select.</description> 917 <bitOffset>4</bitOffset> 918 <bitWidth>1</bitWidth> 919 </field> 920 <field> 921 <name>RAM5_WS</name> 922 <description>System RAM5 WS Select.</description> 923 <bitOffset>5</bitOffset> 924 <bitWidth>1</bitWidth> 925 </field> 926 <field> 927 <name>RAM6_WS</name> 928 <description>System RAM6 WS Select.</description> 929 <bitOffset>6</bitOffset> 930 <bitWidth>1</bitWidth> 931 </field> 932 <field> 933 <name>ROM1_WS</name> 934 <description>ROM1 WS Select.</description> 935 <bitOffset>7</bitOffset> 936 <bitWidth>1</bitWidth> 937 </field> 938 <field> 939 <name>RAM0LS_EN</name> 940 <description>System RAM 0 Light Sleep Mode.</description> 941 <bitOffset>16</bitOffset> 942 <bitWidth>1</bitWidth> 943 <enumeratedValues> 944 <enumeratedValue> 945 <name>active</name> 946 <description>RAM is active.</description> 947 <value>0</value> 948 </enumeratedValue> 949 <enumeratedValue> 950 <name>light_sleep</name> 951 <description>RAM is in Light Sleep mode.</description> 952 <value>1</value> 953 </enumeratedValue> 954 </enumeratedValues> 955 </field> 956 <field derivedFrom="RAM0LS_EN"> 957 <name>RAM1LS_EN</name> 958 <description>System RAM 1 Light Sleep Mode.</description> 959 <bitOffset>17</bitOffset> 960 <bitWidth>1</bitWidth> 961 </field> 962 <field derivedFrom="RAM0LS_EN"> 963 <name>RAM2LS_EN</name> 964 <description>System RAM 2 Light Sleep Mode.</description> 965 <bitOffset>18</bitOffset> 966 <bitWidth>1</bitWidth> 967 </field> 968 <field derivedFrom="RAM0LS_EN"> 969 <name>RAM3LS_EN</name> 970 <description>System RAM 3 Light Sleep Mode.</description> 971 <bitOffset>19</bitOffset> 972 <bitWidth>1</bitWidth> 973 </field> 974 <field derivedFrom="RAM0LS_EN"> 975 <name>RAM4LS_EN</name> 976 <description>System RAM 4 Light Sleep Mode.</description> 977 <bitOffset>20</bitOffset> 978 <bitWidth>1</bitWidth> 979 </field> 980 <field derivedFrom="RAM0LS_EN"> 981 <name>RAM5LS_EN</name> 982 <description>System RAM 5 Light Sleep Mode.</description> 983 <bitOffset>21</bitOffset> 984 <bitWidth>1</bitWidth> 985 </field> 986 <field derivedFrom="RAM0LS_EN"> 987 <name>RAM6LS_EN</name> 988 <description>System RAM 6 Light Sleep Mode.</description> 989 <bitOffset>22</bitOffset> 990 <bitWidth>1</bitWidth> 991 </field> 992 <field derivedFrom="RAM0LS_EN"> 993 <name>ICCXIPLS_EN</name> 994 <description>ICACHE-XIP RAM Light Sleep Mode.</description> 995 <bitOffset>25</bitOffset> 996 <bitWidth>1</bitWidth> 997 </field> 998 <field derivedFrom="RAM0LS_EN"> 999 <name>CRYPTOLS_EN</name> 1000 <description>MEU RAM Light Sleep Mode.</description> 1001 <bitOffset>27</bitOffset> 1002 <bitWidth>1</bitWidth> 1003 </field> 1004 <field derivedFrom="RAM0LS_EN"> 1005 <name>USBLS_EN</name> 1006 <description>USB FIFO Light Sleep Mode.</description> 1007 <bitOffset>28</bitOffset> 1008 <bitWidth>1</bitWidth> 1009 </field> 1010 <field derivedFrom="RAM0LS_EN"> 1011 <name>ROM0LS_EN</name> 1012 <description>ROM0 Light Sleep Mode.</description> 1013 <bitOffset>29</bitOffset> 1014 <bitWidth>1</bitWidth> 1015 </field> 1016 <field derivedFrom="RAM0LS_EN"> 1017 <name>ROM1LS_EN</name> 1018 <description>ROM1 Light Sleep Mode.</description> 1019 <bitOffset>30</bitOffset> 1020 <bitWidth>1</bitWidth> 1021 </field> 1022 <field derivedFrom="RAM0LS_EN"> 1023 <name>MAALS_EN</name> 1024 <description>MAA Light Sleep Mode.</description> 1025 <bitOffset>31</bitOffset> 1026 <bitWidth>1</bitWidth> 1027 </field> 1028 </fields> 1029 </register> 1030 <register> 1031 <name>MEMZ</name> 1032 <description>Memory Zeroize Control.</description> 1033 <addressOffset>0x2C</addressOffset> 1034 <fields> 1035 <field> 1036 <name>RAM0</name> 1037 <description>System RAM Block 0 Zeroization.</description> 1038 <bitOffset>0</bitOffset> 1039 <bitWidth>1</bitWidth> 1040 <enumeratedValues> 1041 <enumeratedValue> 1042 <name>nop</name> 1043 <description>No operation/complete.</description> 1044 <value>0</value> 1045 </enumeratedValue> 1046 <enumeratedValue> 1047 <name>start</name> 1048 <description>Start operation.</description> 1049 <value>1</value> 1050 </enumeratedValue> 1051 </enumeratedValues> 1052 </field> 1053 <field derivedFrom="RAM0"> 1054 <name>RAM1</name> 1055 <description>System RAM Block 1 Zeroization.</description> 1056 <bitOffset>1</bitOffset> 1057 <bitWidth>1</bitWidth> 1058 </field> 1059 <field derivedFrom="RAM0"> 1060 <name>RAM2</name> 1061 <description>System RAM Block 2 Zeroization.</description> 1062 <bitOffset>2</bitOffset> 1063 <bitWidth>1</bitWidth> 1064 </field> 1065 <field derivedFrom="RAM0"> 1066 <name>RAM3</name> 1067 <description>System RAM Block 3 Zeroization.</description> 1068 <bitOffset>3</bitOffset> 1069 <bitWidth>1</bitWidth> 1070 </field> 1071 <field derivedFrom="RAM0"> 1072 <name>RAM4</name> 1073 <description>System RAM Block 4 Zeroization.</description> 1074 <bitOffset>4</bitOffset> 1075 <bitWidth>1</bitWidth> 1076 </field> 1077 <field derivedFrom="RAM0"> 1078 <name>RAM5</name> 1079 <description>System RAM Block 5 Zeroization.</description> 1080 <bitOffset>5</bitOffset> 1081 <bitWidth>1</bitWidth> 1082 </field> 1083 <field derivedFrom="RAM0"> 1084 <name>RAM6</name> 1085 <description>System RAM Block 6 Zeroization.</description> 1086 <bitOffset>6</bitOffset> 1087 <bitWidth>1</bitWidth> 1088 </field> 1089 <field derivedFrom="RAM0"> 1090 <name>ICCXIP</name> 1091 <description>Internal ICC XIP Data and Tag RAM Zeroization.</description> 1092 <bitOffset>9</bitOffset> 1093 <bitWidth>1</bitWidth> 1094 </field> 1095 <field derivedFrom="RAM0"> 1096 <name>CRYPTO</name> 1097 <description>MEU Memory Zeroization.</description> 1098 <bitOffset>12</bitOffset> 1099 <bitWidth>1</bitWidth> 1100 </field> 1101 <field derivedFrom="RAM0"> 1102 <name>USBFIFO</name> 1103 <description>USB FIFO Zeroization.</description> 1104 <bitOffset>13</bitOffset> 1105 <bitWidth>1</bitWidth> 1106 </field> 1107 </fields> 1108 </register> 1109 <register> 1110 <name>SCCLKCTRL</name> 1111 <description>Smart Card Clock Control.</description> 1112 <addressOffset>0x34</addressOffset> 1113 <resetValue>0x00000000</resetValue> 1114 <fields> 1115 <field> 1116 <name>SC0CLK_DIV</name> 1117 <description>Smart Card0 Clock Divider</description> 1118 <bitOffset>0</bitOffset> 1119 <bitWidth>6</bitWidth> 1120 </field> 1121 <field> 1122 <name>SC1CLK_DIV</name> 1123 <description>Smart Card1 Clock Divider</description> 1124 <bitOffset>8</bitOffset> 1125 <bitWidth>6</bitWidth> 1126 </field> 1127 </fields> 1128 </register> 1129 <register> 1130 <name>SYSST</name> 1131 <description>System Status Register.</description> 1132 <addressOffset>0x40</addressOffset> 1133 <fields> 1134 <field> 1135 <name>ICELOCK</name> 1136 <description>ARM ICE Lock Status.</description> 1137 <bitOffset>0</bitOffset> 1138 <bitWidth>1</bitWidth> 1139 <enumeratedValues> 1140 <enumeratedValue> 1141 <name>unlocked</name> 1142 <description>ICE is unlocked.</description> 1143 <value>0</value> 1144 </enumeratedValue> 1145 <enumeratedValue> 1146 <name>locked</name> 1147 <description>ICE is locked.</description> 1148 <value>1</value> 1149 </enumeratedValue> 1150 </enumeratedValues> 1151 </field> 1152 <field> 1153 <name>CODEINTERR</name> 1154 <description>Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. </description> 1155 <bitOffset>1</bitOffset> 1156 <bitWidth>1</bitWidth> 1157 <enumeratedValues> 1158 <enumeratedValue> 1159 <name>norm</name> 1160 <description>Normal Operating Condition.</description> 1161 <value>0</value> 1162 </enumeratedValue> 1163 <enumeratedValue> 1164 <name>code</name> 1165 <description>Code Integrity Error.</description> 1166 <value>1</value> 1167 </enumeratedValue> 1168 </enumeratedValues> 1169 </field> 1170 <field> 1171 <name>SCMEMF</name> 1172 <description>System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface.</description> 1173 <bitOffset>5</bitOffset> 1174 <bitWidth>1</bitWidth> 1175 <enumeratedValues> 1176 <enumeratedValue> 1177 <name>norm</name> 1178 <description>Normal Operating Condition.</description> 1179 <value>0</value> 1180 </enumeratedValue> 1181 <enumeratedValue> 1182 <name>memory</name> 1183 <description>Memory Fault.</description> 1184 <value>1</value> 1185 </enumeratedValue> 1186 </enumeratedValues> 1187 </field> 1188 </fields> 1189 </register> 1190 <register> 1191 <name>RST1</name> 1192 <description>Reset 1.</description> 1193 <addressOffset>0x44</addressOffset> 1194 <fields> 1195 <field> 1196 <name>I2C1</name> 1197 <description>I2C1 Reset.</description> 1198 <bitOffset>0</bitOffset> 1199 <bitWidth>1</bitWidth> 1200 <enumeratedValues> 1201 <name>reset_read</name> 1202 <usage>read</usage> 1203 <enumeratedValue> 1204 <name>reset_done</name> 1205 <description>Reset complete.</description> 1206 <value>0</value> 1207 </enumeratedValue> 1208 <enumeratedValue> 1209 <name>busy</name> 1210 <description>Starts reset or indicates reset in progress.</description> 1211 <value>1</value> 1212 </enumeratedValue> 1213 </enumeratedValues> 1214 </field> 1215 <field derivedFrom="I2C1"> 1216 <name>PT</name> 1217 <description>PT Reset.</description> 1218 <bitOffset>1</bitOffset> 1219 <bitWidth>1</bitWidth> 1220 </field> 1221 <field derivedFrom="I2C1"> 1222 <name>SPIXIP</name> 1223 <description>SPI XIPF Reset.</description> 1224 <bitOffset>3</bitOffset> 1225 <bitWidth>1</bitWidth> 1226 </field> 1227 <field derivedFrom="I2C1"> 1228 <name>SPIXIPM</name> 1229 <description>SPI XIP Master Reset.</description> 1230 <bitOffset>4</bitOffset> 1231 <bitWidth>1</bitWidth> 1232 </field> 1233 <field derivedFrom="I2C1"> 1234 <name>WDT1</name> 1235 <description>WDT1 Reset.</description> 1236 <bitOffset>8</bitOffset> 1237 <bitWidth>1</bitWidth> 1238 </field> 1239 <field derivedFrom="I2C1"> 1240 <name>SPI3</name> 1241 <description>SPI3 Reset.</description> 1242 <bitOffset>9</bitOffset> 1243 <bitWidth>1</bitWidth> 1244 </field> 1245 <field derivedFrom="I2C1"> 1246 <name>AC</name> 1247 <description>Auto-Cal Reset.</description> 1248 <bitOffset>14</bitOffset> 1249 <bitWidth>1</bitWidth> 1250 </field> 1251 <field derivedFrom="I2C1"> 1252 <name>SEMA</name> 1253 <description>Semaphore Reset.</description> 1254 <bitOffset>16</bitOffset> 1255 <bitWidth>1</bitWidth> 1256 </field> 1257 <field derivedFrom="I2C1"> 1258 <name>UART3</name> 1259 <description>UART3 Reset.</description> 1260 <bitOffset>18</bitOffset> 1261 <bitWidth>1</bitWidth> 1262 </field> 1263 <field derivedFrom="I2C1"> 1264 <name>SKBD</name> 1265 <description>SKBD Reset.</description> 1266 <bitOffset>21</bitOffset> 1267 <bitWidth>1</bitWidth> 1268 </field> 1269 <field derivedFrom="I2C1"> 1270 <name>MSRADC</name> 1271 <description>MSRADC Reset.</description> 1272 <bitOffset>22</bitOffset> 1273 <bitWidth>1</bitWidth> 1274 </field> 1275 <field derivedFrom="I2C1"> 1276 <name>SC0</name> 1277 <description>SC0 Reset.</description> 1278 <bitOffset>23</bitOffset> 1279 <bitWidth>1</bitWidth> 1280 </field> 1281 <field derivedFrom="I2C1"> 1282 <name>SC1</name> 1283 <description>SC1 Reset.</description> 1284 <bitOffset>24</bitOffset> 1285 <bitWidth>1</bitWidth> 1286 </field> 1287 <field derivedFrom="I2C1"> 1288 <name>HTMR0</name> 1289 <description>HTIMER0 Reset.</description> 1290 <bitOffset>28</bitOffset> 1291 <bitWidth>1</bitWidth> 1292 </field> 1293 <field derivedFrom="I2C1"> 1294 <name>HTMR1</name> 1295 <description>HTIMER1 Reset.</description> 1296 <bitOffset>29</bitOffset> 1297 <bitWidth>1</bitWidth> 1298 </field> 1299 <field derivedFrom="I2C1"> 1300 <name>CPU1</name> 1301 <description>CPU1 Reset.</description> 1302 <bitOffset>31</bitOffset> 1303 <bitWidth>1</bitWidth> 1304 </field> 1305 </fields> 1306 </register> 1307 <register> 1308 <name>PCLKDIS1</name> 1309 <description>Peripheral Clock Disable.</description> 1310 <addressOffset>0x48</addressOffset> 1311 <fields> 1312 <field> 1313 <name>UART2</name> 1314 <description>UART2 Clock Disable.</description> 1315 <bitOffset>1</bitOffset> 1316 <bitWidth>1</bitWidth> 1317 <enumeratedValues> 1318 <enumeratedValue> 1319 <name>en</name> 1320 <description>Clock enabled to the peripheral.</description> 1321 <value>0</value> 1322 </enumeratedValue> 1323 <enumeratedValue> 1324 <name>dis</name> 1325 <description>Clock disabled to the peripheral.</description> 1326 <value>1</value> 1327 </enumeratedValue> 1328 </enumeratedValues> 1329 </field> 1330 <field derivedFrom="UART2"> 1331 <name>TRNG</name> 1332 <description>TRNG Clock Disable.</description> 1333 <bitOffset>2</bitOffset> 1334 <bitWidth>1</bitWidth> 1335 </field> 1336 <field derivedFrom="UART2"> 1337 <name>OTP</name> 1338 <description>OTP Clock Disable.</description> 1339 <bitOffset>3</bitOffset> 1340 <bitWidth>1</bitWidth> 1341 </field> 1342 <field derivedFrom="UART2"> 1343 <name>WDT0</name> 1344 <description>Watchdog 0 Clock Disable.</description> 1345 <bitOffset>4</bitOffset> 1346 <bitWidth>1</bitWidth> 1347 </field> 1348 <field derivedFrom="UART2"> 1349 <name>WDT1</name> 1350 <description>Watchdog 1 Clock Disable.</description> 1351 <bitOffset>5</bitOffset> 1352 <bitWidth>1</bitWidth> 1353 </field> 1354 <field derivedFrom="UART2"> 1355 <name>SEMA</name> 1356 <description>Semaphore Disable.</description> 1357 <bitOffset>9</bitOffset> 1358 <bitWidth>1</bitWidth> 1359 </field> 1360 <field derivedFrom="UART2"> 1361 <name>SPI3</name> 1362 <description>SPI3 Clock Disable.</description> 1363 <bitOffset>14</bitOffset> 1364 <bitWidth>1</bitWidth> 1365 </field> 1366 <field derivedFrom="UART2"> 1367 <name>UART3</name> 1368 <description>UART3 Clock Disable.</description> 1369 <bitOffset>22</bitOffset> 1370 <bitWidth>1</bitWidth> 1371 </field> 1372 <field derivedFrom="UART2"> 1373 <name>MSRADC</name> 1374 <description>MSRADC Clock Disable.</description> 1375 <bitOffset>25</bitOffset> 1376 <bitWidth>1</bitWidth> 1377 </field> 1378 <field derivedFrom="UART2"> 1379 <name>SC0</name> 1380 <description>SC0 Clock Disable.</description> 1381 <bitOffset>26</bitOffset> 1382 <bitWidth>1</bitWidth> 1383 </field> 1384 <field derivedFrom="UART2"> 1385 <name>SC1</name> 1386 <description>SC1 Clock Disable.</description> 1387 <bitOffset>27</bitOffset> 1388 <bitWidth>1</bitWidth> 1389 </field> 1390 <field derivedFrom="UART2"> 1391 <name>CPU1</name> 1392 <description>CPU1 Clock Disable.</description> 1393 <bitOffset>31</bitOffset> 1394 <bitWidth>1</bitWidth> 1395 </field> 1396 </fields> 1397 </register> 1398 <register> 1399 <name>EVENTEN</name> 1400 <description>Event Enable Register.</description> 1401 <addressOffset>0x4C</addressOffset> 1402 <fields> 1403 <field> 1404 <name>DMA</name> 1405 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 1406 <bitOffset>0</bitOffset> 1407 <bitWidth>1</bitWidth> 1408 </field> 1409 <field> 1410 <name>RX</name> 1411 <description>Enable RXEV pin event. When this bit is set, RXEV event from the CPU is output to GPIO1.9.</description> 1412 <bitOffset>1</bitOffset> 1413 <bitWidth>1</bitWidth> 1414 </field> 1415 <field> 1416 <name>TX</name> 1417 <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9.</description> 1418 <bitOffset>2</bitOffset> 1419 <bitWidth>1</bitWidth> 1420 </field> 1421 </fields> 1422 </register> 1423 <register> 1424 <name>REVISION</name> 1425 <description>Revision Register.</description> 1426 <addressOffset>0x50</addressOffset> 1427 <access>read-only</access> 1428 <fields> 1429 <field> 1430 <name>REVISION</name> 1431 <description>Manufacturer Chip Revision.</description> 1432 <bitOffset>0</bitOffset> 1433 <bitWidth>16</bitWidth> 1434 </field> 1435 </fields> 1436 </register> 1437 <register> 1438 <name>SYSIE</name> 1439 <description>System Status Interrupt Enable Register.</description> 1440 <addressOffset>0x54</addressOffset> 1441 <fields> 1442 <field> 1443 <name>ICEUNLOCK</name> 1444 <description>ARM ICE Unlock Interrupt Enable.</description> 1445 <bitOffset>0</bitOffset> 1446 <bitWidth>1</bitWidth> 1447 <enumeratedValues> 1448 <enumeratedValue> 1449 <name>dis</name> 1450 <description>disabled.</description> 1451 <value>0</value> 1452 </enumeratedValue> 1453 <enumeratedValue> 1454 <name>en</name> 1455 <description>enabled.</description> 1456 <value>1</value> 1457 </enumeratedValue> 1458 </enumeratedValues> 1459 </field> 1460 <field derivedFrom="ICEUNLOCK"> 1461 <name>CIE</name> 1462 <description>Code Integrity Error Interrupt Enable.</description> 1463 <bitOffset>1</bitOffset> 1464 <bitWidth>1</bitWidth> 1465 </field> 1466 <field derivedFrom="ICEUNLOCK"> 1467 <name>SCMF</name> 1468 <description>System Cache Memory Fault Interrupt Enable.</description> 1469 <bitOffset>5</bitOffset> 1470 <bitWidth>1</bitWidth> 1471 </field> 1472 </fields> 1473 </register> 1474 <register> 1475 <name>IPOCNT</name> 1476 <description>IPO Warmup Count Register.</description> 1477 <addressOffset>0x58</addressOffset> 1478 <fields> 1479 <field> 1480 <name>WMUPCNT</name> 1481 <description>TBD</description> 1482 <bitOffset>0</bitOffset> 1483 <bitWidth>10</bitWidth> 1484 </field> 1485 </fields> 1486 </register> 1487 </registers> 1488 </peripheral> 1489</device>
